mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-07 19:49:33 -04:00
Merge tag 'pci-v6.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull pci updates from Bjorn Helgaas:
"Enumeration:
- Skip E820 checks for MCFG ECAM regions for new (2016+) machines,
since there's no requirement to describe them in E820 and some
platforms require ECAM to work (Bjorn Helgaas)
- Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more specific (Damien
Le Moal)
- Remove last user and pci_enable_device_io() (Heiner Kallweit)
- Wait for Link Training==0 to avoid possible race (Ilpo Järvinen)
- Skip waiting for devices that have been disconnected while
suspended (Ilpo Järvinen)
- Clear Secondary Status errors after enumeration since Master Aborts
and Unsupported Request errors are an expected part of enumeration
(Vidya Sagar)
MSI:
- Remove unused IMS (Interrupt Message Store) support (Bjorn Helgaas)
Error handling:
- Mask Genesys GL975x SD host controller Replay Timer Timeout
correctable errors caused by a hardware defect; the errors cause
interrupts that prevent system suspend (Kai-Heng Feng)
- Fix EDR-related _DSM support, which previously evaluated revision 5
but assumed revision 6 behavior (Kuppuswamy Sathyanarayanan)
ASPM:
- Simplify link state definitions and mask calculation (Ilpo
Järvinen)
Power management:
- Avoid D3cold for HP Pavilion 17 PC/1972 PCIe Ports, where BIOS
apparently doesn't know how to put them back in D0 (Mario
Limonciello)
CXL:
- Support resetting CXL devices; special handling required because
CXL Ports mask Secondary Bus Reset by default (Dave Jiang)
DOE:
- Support DOE Discovery Version 2 (Alexey Kardashevskiy)
Endpoint framework:
- Set endpoint BAR to be 64-bit if the driver says that's all the
device supports, in addition to doing so if the size is >2GB
(Niklas Cassel)
- Simplify endpoint BAR allocation and setting interfaces (Niklas
Cassel)
Cadence PCIe controller driver:
- Drop DT binding redundant msi-parent and pci-bus.yaml (Krzysztof
Kozlowski)
Cadence PCIe endpoint driver:
- Configure endpoint BARs to be 64-bit based on the BAR type, not the
BAR value (Niklas Cassel)
Freescale Layerscape PCIe controller driver:
- Convert DT binding to YAML (Frank Li)
MediaTek MT7621 PCIe controller driver:
- Add DT binding missing 'reg' property for child Root Ports
(Krzysztof Kozlowski)
- Fix theoretical string truncation in PHY name (Sergio Paracuellos)
NVIDIA Tegra194 PCIe controller driver:
- Return success for endpoint probe instead of falling through to the
failure path (Vidya Sagar)
Renesas R-Car PCIe controller driver:
- Add DT binding missing IOMMU properties (Geert Uytterhoeven)
- Add DT binding R-Car V4H compatible for host and endpoint mode
(Yoshihiro Shimoda)
Rockchip PCIe controller driver:
- Configure endpoint BARs to be 64-bit based on the BAR type, not the
BAR value (Niklas Cassel)
- Add DT binding missing maxItems to ep-gpios (Krzysztof Kozlowski)
- Set the Subsystem Vendor ID, which was previously zero because it
was masked incorrectly (Rick Wertenbroek)
Synopsys DesignWare PCIe controller driver:
- Restructure DBI register access to accommodate devices where this
requires Refclk to be active (Manivannan Sadhasivam)
- Remove the deinit() callback, which was only need by the
pcie-rcar-gen4, and do it directly in that driver (Manivannan
Sadhasivam)
- Add dw_pcie_ep_cleanup() so drivers that support PERST# can clean
up things like eDMA (Manivannan Sadhasivam)
- Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit() to make it parallel
to dw_pcie_ep_init() (Manivannan Sadhasivam)
- Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers() to
reflect the actual functionality (Manivannan Sadhasivam)
- Call dw_pcie_ep_init_registers() directly from all the glue
drivers, not just those that require active Refclk from the host
(Manivannan Sadhasivam)
- Remove the "core_init_notifier" flag, which was an obscure way for
glue drivers to indicate that they depend on Refclk from the host
(Manivannan Sadhasivam)
TI J721E PCIe driver:
- Add DT binding J784S4 SoC Device ID (Siddharth Vadapalli)
- Add DT binding J722S SoC support (Siddharth Vadapalli)
TI Keystone PCIe controller driver:
- Add DT binding missing num-viewport, phys and phy-name properties
(Jan Kiszka)
Miscellaneous:
- Constify and annotate with __ro_after_init (Heiner Kallweit)
- Convert DT bindings to YAML (Krzysztof Kozlowski)
- Check for kcalloc() failure in of_pci_prop_intr_map() (Duoming
Zhou)"
* tag 'pci-v6.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (97 commits)
PCI: Do not wait for disconnected devices when resuming
x86/pci: Skip early E820 check for ECAM region
PCI: Remove unused pci_enable_device_io()
ata: pata_cs5520: Remove unnecessary call to pci_enable_device_io()
PCI: Update pci_find_capability() stub return types
PCI: Remove PCI_IRQ_LEGACY
scsi: vmw_pvscsi: Do not use PCI_IRQ_LEGACY instead of PCI_IRQ_LEGACY
scsi: pmcraid: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY
scsi: mpt3sas: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY
scsi: megaraid_sas: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY
scsi: ipr: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY
scsi: hpsa: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY
scsi: arcmsr: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY
wifi: rtw89: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY
dt-bindings: PCI: rockchip,rk3399-pcie: Add missing maxItems to ep-gpios
Revert "genirq/msi: Provide constants for PCI/IMS support"
Revert "x86/apic/msi: Enable PCI/IMS"
Revert "iommu/vt-d: Enable PCI/IMS"
Revert "iommu/amd: Enable PCI/IMS"
Revert "PCI/MSI: Provide IMS (Interrupt Message Store) support"
...
This commit is contained in:
Linus Torvalds
@@ -25,7 +25,6 @@ enum irq_domain_bus_token {
|
||||
DOMAIN_BUS_PCI_DEVICE_MSIX,
|
||||
DOMAIN_BUS_DMAR,
|
||||
DOMAIN_BUS_AMDVI,
|
||||
DOMAIN_BUS_PCI_DEVICE_IMS,
|
||||
DOMAIN_BUS_DEVICE_MSI,
|
||||
DOMAIN_BUS_WIRED_TO_MSI,
|
||||
};
|
||||
|
||||
@@ -297,6 +297,9 @@ extern void lock_unpin_lock(struct lockdep_map *lock, struct pin_cookie);
|
||||
.wait_type_inner = _wait_type, \
|
||||
.lock_type = LD_LOCK_WAIT_OVERRIDE, }
|
||||
|
||||
#define lock_map_assert_held(l) \
|
||||
lockdep_assert(lock_is_held(l) != LOCK_STATE_NOT_HELD)
|
||||
|
||||
#else /* !CONFIG_LOCKDEP */
|
||||
|
||||
static inline void lockdep_init_task(struct task_struct *task)
|
||||
@@ -388,6 +391,8 @@ extern int lockdep_is_held(const void *);
|
||||
#define DEFINE_WAIT_OVERRIDE_MAP(_name, _wait_type) \
|
||||
struct lockdep_map __maybe_unused _name = {}
|
||||
|
||||
#define lock_map_assert_held(l) do { (void)(l); } while (0)
|
||||
|
||||
#endif /* !LOCKDEP */
|
||||
|
||||
#ifdef CONFIG_PROVE_LOCKING
|
||||
|
||||
@@ -573,8 +573,6 @@ enum {
|
||||
MSI_FLAG_MSIX_CONTIGUOUS = (1 << 19),
|
||||
/* PCI/MSI-X vectors can be dynamically allocated/freed post MSI-X enable */
|
||||
MSI_FLAG_PCI_MSIX_ALLOC_DYN = (1 << 20),
|
||||
/* Support for PCI/IMS */
|
||||
MSI_FLAG_PCI_IMS = (1 << 21),
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@@ -15,7 +15,6 @@ struct device;
|
||||
*/
|
||||
enum msi_domain_ids {
|
||||
MSI_DEFAULT_DOMAIN,
|
||||
MSI_SECONDARY_DOMAIN,
|
||||
MSI_MAX_DEVICE_IRQDOMAINS,
|
||||
};
|
||||
|
||||
|
||||
@@ -128,6 +128,8 @@ struct pci_epc_mem {
|
||||
* @group: configfs group representing the PCI EPC device
|
||||
* @lock: mutex to protect pci_epc ops
|
||||
* @function_num_map: bitmap to manage physical function number
|
||||
* @init_complete: flag to indicate whether the EPC initialization is complete
|
||||
* or not
|
||||
*/
|
||||
struct pci_epc {
|
||||
struct device dev;
|
||||
@@ -143,6 +145,7 @@ struct pci_epc {
|
||||
/* mutex to protect against concurrent access of EP controller */
|
||||
struct mutex lock;
|
||||
unsigned long function_num_map;
|
||||
bool init_complete;
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -179,8 +182,6 @@ struct pci_epc_bar_desc {
|
||||
/**
|
||||
* struct pci_epc_features - features supported by a EPC device per function
|
||||
* @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
|
||||
* @core_init_notifier: indicate cores that can notify about their availability
|
||||
* for initialization
|
||||
* @msi_capable: indicate if the endpoint function has MSI capability
|
||||
* @msix_capable: indicate if the endpoint function has MSI-X capability
|
||||
* @bar: array specifying the hardware description for each BAR
|
||||
@@ -188,7 +189,6 @@ struct pci_epc_bar_desc {
|
||||
*/
|
||||
struct pci_epc_features {
|
||||
unsigned int linkup_notifier : 1;
|
||||
unsigned int core_init_notifier : 1;
|
||||
unsigned int msi_capable : 1;
|
||||
unsigned int msix_capable : 1;
|
||||
struct pci_epc_bar_desc bar[PCI_STD_NUM_BARS];
|
||||
@@ -225,6 +225,7 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf,
|
||||
void pci_epc_linkup(struct pci_epc *epc);
|
||||
void pci_epc_linkdown(struct pci_epc *epc);
|
||||
void pci_epc_init_notify(struct pci_epc *epc);
|
||||
void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf);
|
||||
void pci_epc_bme_notify(struct pci_epc *epc);
|
||||
void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf,
|
||||
enum pci_epc_interface_type type);
|
||||
|
||||
@@ -51,7 +51,7 @@
|
||||
PCI_STATUS_PARITY)
|
||||
|
||||
/* Number of reset methods used in pci_reset_fn_methods array in pci.c */
|
||||
#define PCI_NUM_RESET_METHODS 7
|
||||
#define PCI_NUM_RESET_METHODS 8
|
||||
|
||||
#define PCI_RESET_PROBE true
|
||||
#define PCI_RESET_DO_RESET false
|
||||
@@ -413,6 +413,8 @@ struct pci_dev {
|
||||
struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
|
||||
|
||||
bool match_driver; /* Skip attaching driver */
|
||||
struct lock_class_key cfg_access_key;
|
||||
struct lockdep_map cfg_access_lock;
|
||||
|
||||
unsigned int transparent:1; /* Subtractive decode bridge */
|
||||
unsigned int io_window:1; /* Bridge has I/O window */
|
||||
@@ -1077,8 +1079,6 @@ enum {
|
||||
#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
|
||||
#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
|
||||
|
||||
#define PCI_IRQ_LEGACY PCI_IRQ_INTX /* Deprecated! Use PCI_IRQ_INTX */
|
||||
|
||||
/* These external functions are only available when PCI support is enabled */
|
||||
#ifdef CONFIG_PCI
|
||||
|
||||
@@ -1315,7 +1315,6 @@ int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
|
||||
int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
|
||||
|
||||
int __must_check pci_enable_device(struct pci_dev *dev);
|
||||
int __must_check pci_enable_device_io(struct pci_dev *dev);
|
||||
int __must_check pci_enable_device_mem(struct pci_dev *dev);
|
||||
int __must_check pci_reenable_device(struct pci_dev *);
|
||||
int __must_check pcim_enable_device(struct pci_dev *pdev);
|
||||
@@ -1648,8 +1647,7 @@ int pci_set_vga_state(struct pci_dev *pdev, bool decode,
|
||||
*/
|
||||
#define PCI_IRQ_VIRTUAL (1 << 4)
|
||||
|
||||
#define PCI_IRQ_ALL_TYPES \
|
||||
(PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
|
||||
#define PCI_IRQ_ALL_TYPES (PCI_IRQ_INTX | PCI_IRQ_MSI | PCI_IRQ_MSIX)
|
||||
|
||||
#include <linux/dmapool.h>
|
||||
|
||||
@@ -1658,8 +1656,6 @@ struct msix_entry {
|
||||
u16 entry; /* Driver uses to specify entry, OS writes */
|
||||
};
|
||||
|
||||
struct msi_domain_template;
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
int pci_msi_vec_count(struct pci_dev *dev);
|
||||
void pci_disable_msi(struct pci_dev *dev);
|
||||
@@ -1692,11 +1688,6 @@ void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
|
||||
void pci_free_irq_vectors(struct pci_dev *dev);
|
||||
int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
|
||||
const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
|
||||
bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
|
||||
unsigned int hwsize, void *data);
|
||||
struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
|
||||
const struct irq_affinity_desc *affdesc);
|
||||
void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
|
||||
|
||||
#else
|
||||
static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
|
||||
@@ -1719,7 +1710,7 @@ pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
|
||||
unsigned int max_vecs, unsigned int flags,
|
||||
struct irq_affinity *aff_desc)
|
||||
{
|
||||
if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
|
||||
if ((flags & PCI_IRQ_INTX) && min_vecs == 1 && dev->irq)
|
||||
return 1;
|
||||
return -ENOSPC;
|
||||
}
|
||||
@@ -1760,25 +1751,6 @@ static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
|
||||
{
|
||||
return cpu_possible_mask;
|
||||
}
|
||||
|
||||
static inline bool pci_create_ims_domain(struct pci_dev *pdev,
|
||||
const struct msi_domain_template *template,
|
||||
unsigned int hwsize, void *data)
|
||||
{ return false; }
|
||||
|
||||
static inline struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev,
|
||||
union msi_instance_cookie *icookie,
|
||||
const struct irq_affinity_desc *affdesc)
|
||||
{
|
||||
struct msi_map map = { .index = -ENOSYS, };
|
||||
|
||||
return map;
|
||||
}
|
||||
|
||||
static inline void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
@@ -1821,17 +1793,21 @@ extern bool pcie_ports_native;
|
||||
#define pcie_ports_native false
|
||||
#endif
|
||||
|
||||
#define PCIE_LINK_STATE_L0S BIT(0)
|
||||
#define PCIE_LINK_STATE_L1 BIT(1)
|
||||
#define PCIE_LINK_STATE_CLKPM BIT(2)
|
||||
#define PCIE_LINK_STATE_L1_1 BIT(3)
|
||||
#define PCIE_LINK_STATE_L1_2 BIT(4)
|
||||
#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
|
||||
#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
|
||||
#define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\
|
||||
PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\
|
||||
PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\
|
||||
#define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */
|
||||
#define PCIE_LINK_STATE_L1 BIT(2) /* L1 state */
|
||||
#define PCIE_LINK_STATE_L1_1 BIT(3) /* ASPM L1.1 state */
|
||||
#define PCIE_LINK_STATE_L1_2 BIT(4) /* ASPM L1.2 state */
|
||||
#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) /* PCI-PM L1.1 state */
|
||||
#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) /* PCI-PM L1.2 state */
|
||||
#define PCIE_LINK_STATE_ASPM_ALL (PCIE_LINK_STATE_L0S |\
|
||||
PCIE_LINK_STATE_L1 |\
|
||||
PCIE_LINK_STATE_L1_1 |\
|
||||
PCIE_LINK_STATE_L1_2 |\
|
||||
PCIE_LINK_STATE_L1_1_PCIPM |\
|
||||
PCIE_LINK_STATE_L1_2_PCIPM)
|
||||
#define PCIE_LINK_STATE_CLKPM BIT(7)
|
||||
#define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_ASPM_ALL |\
|
||||
PCIE_LINK_STATE_CLKPM)
|
||||
|
||||
#ifdef CONFIG_PCIEASPM
|
||||
int pci_disable_link_state(struct pci_dev *pdev, int state);
|
||||
@@ -2014,10 +1990,9 @@ static inline int pci_register_driver(struct pci_driver *drv)
|
||||
static inline void pci_unregister_driver(struct pci_driver *drv) { }
|
||||
static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
|
||||
{ return 0; }
|
||||
static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
|
||||
int cap)
|
||||
static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap)
|
||||
{ return 0; }
|
||||
static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
|
||||
static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
|
||||
{ return 0; }
|
||||
|
||||
static inline u64 pci_get_dsn(struct pci_dev *dev)
|
||||
@@ -2519,7 +2494,12 @@ static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
|
||||
|
||||
static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
|
||||
{
|
||||
return dev->error_state == pci_channel_io_perm_failure;
|
||||
/*
|
||||
* error_state is set in pci_dev_set_io_state() using xchg/cmpxchg()
|
||||
* and read w/o common lock. READ_ONCE() ensures compiler cannot cache
|
||||
* the value (e.g. inside the loop in pci_dev_wait()).
|
||||
*/
|
||||
return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure;
|
||||
}
|
||||
|
||||
void pci_request_acs(void);
|
||||
|
||||
@@ -2608,6 +2608,8 @@
|
||||
|
||||
#define PCI_VENDOR_ID_ALIBABA 0x1ded
|
||||
|
||||
#define PCI_VENDOR_ID_CXL 0x1e98
|
||||
|
||||
#define PCI_VENDOR_ID_TEHUTI 0x1fc9
|
||||
#define PCI_DEVICE_ID_TEHUTI_3009 0x3009
|
||||
#define PCI_DEVICE_ID_TEHUTI_3010 0x3010
|
||||
|
||||
@@ -1144,8 +1144,14 @@
|
||||
#define PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH 0x0003ffff
|
||||
|
||||
#define PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX 0x000000ff
|
||||
#define PCI_DOE_DATA_OBJECT_DISC_REQ_3_VER 0x0000ff00
|
||||
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID 0x0000ffff
|
||||
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000
|
||||
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000
|
||||
|
||||
/* Compute Express Link (CXL r3.1, sec 8.1.5) */
|
||||
#define PCI_DVSEC_CXL_PORT 3
|
||||
#define PCI_DVSEC_CXL_PORT_CTL 0x0c
|
||||
#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
|
||||
|
||||
#endif /* LINUX_PCI_REGS_H */
|
||||
|
||||
Reference in New Issue
Block a user