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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge remote-tracking branch 'regulator/for-5.12' into regulator-next
This commit is contained in:
Mark Brown
@@ -1,166 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
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* Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
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* Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
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*/
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#ifndef __LINUX_MFD_AB8500_REGULATOR_H
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#define __LINUX_MFD_AB8500_REGULATOR_H
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#include <linux/platform_device.h>
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/* AB8500 regulators */
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enum ab8500_regulator_id {
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AB8500_LDO_AUX1,
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AB8500_LDO_AUX2,
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AB8500_LDO_AUX3,
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AB8500_LDO_INTCORE,
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AB8500_LDO_TVOUT,
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AB8500_LDO_AUDIO,
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AB8500_LDO_ANAMIC1,
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AB8500_LDO_ANAMIC2,
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AB8500_LDO_DMIC,
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AB8500_LDO_ANA,
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AB8500_NUM_REGULATORS,
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};
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/* AB8505 regulators */
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enum ab8505_regulator_id {
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AB8505_LDO_AUX1,
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AB8505_LDO_AUX2,
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AB8505_LDO_AUX3,
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AB8505_LDO_AUX4,
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AB8505_LDO_AUX5,
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AB8505_LDO_AUX6,
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AB8505_LDO_INTCORE,
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AB8505_LDO_ADC,
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AB8505_LDO_AUDIO,
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AB8505_LDO_ANAMIC1,
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AB8505_LDO_ANAMIC2,
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AB8505_LDO_AUX8,
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AB8505_LDO_ANA,
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AB8505_NUM_REGULATORS,
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};
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/* AB8500 and AB8505 register initialization */
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struct ab8500_regulator_reg_init {
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int id;
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u8 mask;
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u8 value;
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};
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#define INIT_REGULATOR_REGISTER(_id, _mask, _value) \
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{ \
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.id = _id, \
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.mask = _mask, \
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.value = _value, \
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}
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/* AB8500 registers */
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enum ab8500_regulator_reg {
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AB8500_REGUREQUESTCTRL2,
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AB8500_REGUREQUESTCTRL3,
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AB8500_REGUREQUESTCTRL4,
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AB8500_REGUSYSCLKREQ1HPVALID1,
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AB8500_REGUSYSCLKREQ1HPVALID2,
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AB8500_REGUHWHPREQ1VALID1,
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AB8500_REGUHWHPREQ1VALID2,
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AB8500_REGUHWHPREQ2VALID1,
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AB8500_REGUHWHPREQ2VALID2,
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AB8500_REGUSWHPREQVALID1,
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AB8500_REGUSWHPREQVALID2,
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AB8500_REGUSYSCLKREQVALID1,
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AB8500_REGUSYSCLKREQVALID2,
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AB8500_REGUMISC1,
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AB8500_VAUDIOSUPPLY,
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AB8500_REGUCTRL1VAMIC,
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AB8500_VPLLVANAREGU,
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AB8500_VREFDDR,
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AB8500_EXTSUPPLYREGU,
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AB8500_VAUX12REGU,
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AB8500_VRF1VAUX3REGU,
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AB8500_VAUX1SEL,
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AB8500_VAUX2SEL,
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AB8500_VRF1VAUX3SEL,
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AB8500_REGUCTRL2SPARE,
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AB8500_REGUCTRLDISCH,
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AB8500_REGUCTRLDISCH2,
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AB8500_NUM_REGULATOR_REGISTERS,
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};
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/* AB8505 registers */
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enum ab8505_regulator_reg {
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AB8505_REGUREQUESTCTRL1,
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AB8505_REGUREQUESTCTRL2,
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AB8505_REGUREQUESTCTRL3,
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AB8505_REGUREQUESTCTRL4,
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AB8505_REGUSYSCLKREQ1HPVALID1,
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AB8505_REGUSYSCLKREQ1HPVALID2,
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AB8505_REGUHWHPREQ1VALID1,
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AB8505_REGUHWHPREQ1VALID2,
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AB8505_REGUHWHPREQ2VALID1,
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AB8505_REGUHWHPREQ2VALID2,
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AB8505_REGUSWHPREQVALID1,
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AB8505_REGUSWHPREQVALID2,
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AB8505_REGUSYSCLKREQVALID1,
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AB8505_REGUSYSCLKREQVALID2,
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AB8505_REGUVAUX4REQVALID,
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AB8505_REGUMISC1,
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AB8505_VAUDIOSUPPLY,
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AB8505_REGUCTRL1VAMIC,
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AB8505_VSMPSAREGU,
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AB8505_VSMPSBREGU,
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AB8505_VSAFEREGU, /* NOTE! PRCMU register */
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AB8505_VPLLVANAREGU,
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AB8505_EXTSUPPLYREGU,
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AB8505_VAUX12REGU,
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AB8505_VRF1VAUX3REGU,
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AB8505_VSMPSASEL1,
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AB8505_VSMPSASEL2,
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AB8505_VSMPSASEL3,
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AB8505_VSMPSBSEL1,
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AB8505_VSMPSBSEL2,
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AB8505_VSMPSBSEL3,
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AB8505_VSAFESEL1, /* NOTE! PRCMU register */
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AB8505_VSAFESEL2, /* NOTE! PRCMU register */
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AB8505_VSAFESEL3, /* NOTE! PRCMU register */
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AB8505_VAUX1SEL,
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AB8505_VAUX2SEL,
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AB8505_VRF1VAUX3SEL,
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AB8505_VAUX4REQCTRL,
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AB8505_VAUX4REGU,
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AB8505_VAUX4SEL,
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AB8505_REGUCTRLDISCH,
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AB8505_REGUCTRLDISCH2,
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AB8505_REGUCTRLDISCH3,
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AB8505_CTRLVAUX5,
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AB8505_CTRLVAUX6,
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AB8505_NUM_REGULATOR_REGISTERS,
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};
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/* AB8500 external regulators */
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struct ab8500_ext_regulator_cfg {
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bool hwreq; /* requires hw mode or high power mode */
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};
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enum ab8500_ext_regulator_id {
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AB8500_EXT_SUPPLY1,
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AB8500_EXT_SUPPLY2,
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AB8500_EXT_SUPPLY3,
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AB8500_NUM_EXT_REGULATORS,
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};
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/* AB8500 regulator platform data */
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struct ab8500_regulator_platform_data {
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int num_reg_init;
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struct ab8500_regulator_reg_init *reg_init;
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int num_regulator;
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struct regulator_init_data *regulator;
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int num_ext_regulator;
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struct regulator_init_data *ext_regulator;
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};
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#endif
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44
include/linux/regulator/mt6315-regulator.h
Normal file
44
include/linux/regulator/mt6315-regulator.h
Normal file
@@ -0,0 +1,44 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __LINUX_REGULATOR_MT6315_H
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#define __LINUX_REGULATOR_MT6315_H
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#define MT6315_RP 3
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#define MT6315_PP 6
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#define MT6315_SP 7
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enum {
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MT6315_VBUCK1 = 0,
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MT6315_VBUCK2,
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MT6315_VBUCK3,
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MT6315_VBUCK4,
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MT6315_VBUCK_MAX,
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};
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/* Register */
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#define MT6315_TOP2_ELR7 0x139
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#define MT6315_TOP_TMA_KEY 0x39F
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#define MT6315_TOP_TMA_KEY_H 0x3A0
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#define MT6315_BUCK_TOP_CON0 0x1440
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#define MT6315_BUCK_TOP_CON1 0x1443
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#define MT6315_BUCK_TOP_ELR0 0x1449
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#define MT6315_BUCK_TOP_ELR2 0x144B
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#define MT6315_BUCK_TOP_ELR4 0x144D
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#define MT6315_BUCK_TOP_ELR6 0x144F
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#define MT6315_VBUCK1_DBG0 0x1499
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#define MT6315_VBUCK1_DBG4 0x149D
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#define MT6315_VBUCK2_DBG0 0x1519
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#define MT6315_VBUCK2_DBG4 0x151D
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#define MT6315_VBUCK3_DBG0 0x1599
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#define MT6315_VBUCK3_DBG4 0x159D
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#define MT6315_VBUCK4_DBG0 0x1619
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#define MT6315_VBUCK4_DBG4 0x161D
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#define MT6315_BUCK_TOP_4PHASE_ANA_CON42 0x16B1
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#define PROTECTION_KEY_H 0x9C
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#define PROTECTION_KEY 0xEA
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#endif /* __LINUX_REGULATOR_MT6315_H */
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@@ -216,4 +216,11 @@ enum {
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#define IRQ_THERM_105 0x02
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#define IRQ_THERM_125 0x01
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/* PCA9450_REG_RESET_CTRL bits */
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#define WDOG_B_CFG_MASK 0xC0
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#define WDOG_B_CFG_NONE 0x00
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#define WDOG_B_CFG_WARM 0x40
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#define WDOG_B_CFG_COLD_LDO12 0x80
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#define WDOG_B_CFG_COLD 0xC0
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#endif /* __LINUX_REG_PCA9450_H__ */
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