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Merge branches 'clk-aspeed', 'clk-keystone', 'clk-mobileye' and 'clk-allwinner' into clk-next

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* clk-aspeed:
  clk: ast2600: Add FSI parent clock with correct rate
  dt-bindings: clock: ast2600: Add FSI clock

* clk-keystone:
  clk: keystone: sci-clk: Adding support for non contiguous clocks

* clk-mobileye:
  dt-bindings: reset: mobileye,eyeq5-reset: add bindings
  dt-bindings: clock: mobileye,eyeq5-clk: add bindings
  clk: fixed-factor: add fwname-based constructor functions
  clk: fixed-factor: add optional accuracy support

* clk-allwinner:
  clk: sunxi: usb: fix kernel-doc warnings
  clk: sunxi: sun9i-cpus: fix kernel-doc warnings
  clk: sunxi: a20-gmac: fix kernel-doc warnings
This commit is contained in:
Stephen Boyd
2024-03-13 12:34:04 -07:00
parent cf5f06c8ee 56ce4e733c ad3ac13c6e c6e0897eca 84448fa6e3
commit ee2d2a4e9c
11 changed files with 265 additions and 35 deletions
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1
include/dt-bindings/clock/ast2600-clock.h
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@@ -86,6 +86,7 @@
#define ASPEED_CLK_MAC3RCLK 69
#define ASPEED_CLK_MAC4RCLK 70
#define ASPEED_CLK_I3C 71
#define ASPEED_CLK_FSI 72
/* Only list resets here that are not part of a clock gate + reset pair */
#define ASPEED_RESET_ADC 55

22
include/dt-bindings/clock/mobileye,eyeq5-clk.h Normal file
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@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2024 Mobileye Vision Technologies Ltd.
*/
#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
#define EQ5C_PLL_CPU 0
#define EQ5C_PLL_VMP 1
#define EQ5C_PLL_PMA 2
#define EQ5C_PLL_VDI 3
#define EQ5C_PLL_DDR0 4
#define EQ5C_PLL_PCI 5
#define EQ5C_PLL_PER 6
#define EQ5C_PLL_PMAC 7
#define EQ5C_PLL_MPC 8
#define EQ5C_PLL_DDR1 9
#define EQ5C_DIV_OSPI 10
#endif

26
include/linux/clk-provider.h
View File

@@ -1084,18 +1084,28 @@ void of_fixed_factor_clk_setup(struct device_node *node);
* @hw: handle between common and hardware-specific interfaces
* @mult: multiplier
* @div: divider
* @acc: fixed accuracy in ppb
* @flags: behavior modifying flags
*
* Clock with a fixed multiplier and divider. The output frequency is the
* parent clock rate divided by div and multiplied by mult.
* Implements .recalc_rate, .set_rate and .round_rate
* Implements .recalc_rate, .set_rate, .round_rate and .recalc_accuracy
*
* Flags:
* * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
* parent clk accuracy.
*/
struct clk_fixed_factor {
struct clk_hw hw;
unsigned int mult;
unsigned int div;
unsigned long acc;
unsigned int flags;
};
#define CLK_FIXED_FACTOR_FIXED_ACCURACY BIT(0)
#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
extern const struct clk_ops clk_fixed_factor_ops;
@@ -1106,10 +1116,24 @@ void clk_unregister_fixed_factor(struct clk *clk);
struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div);
struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div,
unsigned long acc);
void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div);
struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div,
unsigned long acc);
struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
const char *name, unsigned int index, unsigned long flags,
unsigned int mult, unsigned int div);