From d07e187cf0621891514a47f316597fea8963e5a7 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 5 Jan 2016 14:18:16 -0600 Subject: [PATCH 01/10] ARM: dts: socfpga: add cap-sd-highspeed for SD/MMC node Enable SD highspeed support for the SoCFPGA Arria10 devkit. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts index dbbb751ac1ba..8a7dfa473e98 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts @@ -21,6 +21,7 @@ &mmc { status = "okay"; num-slots = <1>; + cap-sd-highspeed; broken-cd; bus-width = <4>; }; From faf68cdfdf6c9f0999686802ad066b1378b89413 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 5 Jan 2016 14:59:38 -0600 Subject: [PATCH 02/10] ARM: dts: socfpga: add the clk-phase property for sd/mmc clock The CIU clock for the SD/MMC should be the sdmmc_clk and not the sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 1c5e139e4d05..f75dd232ec2e 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -362,6 +362,7 @@ sdmmc_clk: sdmmc_clk { compatible = "altr,socfpga-a10-gate-clk"; clocks = <&sdmmc_free_clk>; clk-gate = <0xC8 5>; + clk-phase = <0 135>; }; qspi_clk: qspi_clk { @@ -589,7 +590,7 @@ mmc: dwmmc0@ff808000 { reg = <0xff808000 0x1000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; fifo-depth = <0x400>; - clocks = <&l4_mp_clk>, <&sdmmc_free_clk>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; status = "disabled"; }; From a1e89630ea8b3797f8ecbdc95e210e29ea461bfa Mon Sep 17 00:00:00 2001 From: Graham Moore Date: Tue, 8 Mar 2016 17:02:50 +0000 Subject: [PATCH 03/10] ARM: dts: socfpga: Add missing clock and interrupt fields for Arria10 DMA The PL330 DMA driver will not load on Arria10 without devicetree entries for clocks and clock_names. This patch adds those entries. It also adds the ninth interrupt, which is required for error detection. Signed-off-by: Graham Moore Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index f75dd232ec2e..8d102d310212 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -78,10 +78,13 @@ pdma: pdma@ffda1000 { <0 87 IRQ_TYPE_LEVEL_HIGH>, <0 88 IRQ_TYPE_LEVEL_HIGH>, <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; + <0 90 IRQ_TYPE_LEVEL_HIGH>, + <0 91 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; }; }; From ebaea3a7852e19bcffcbc8d7de055f2ebacda7ca Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 19 Mar 2016 23:57:04 +0000 Subject: [PATCH 04/10] ARM: dts: socfpga: Drop phy-addr OF property from CV dtsi The phy-addr property of stmmac is deprecated and the stmmac driver does not use it either. On the contrary, the driver will warn if this property is defined. Remove it. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 06db951e06f8..418c19eb2b40 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -40,7 +40,6 @@ mmc0: dwmmc0@ff704000 { ethernet@ff702000 { phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ status = "okay"; }; From 702744ce8b3ef369ed8f8e257cbee4db44beb415 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 19 Mar 2016 23:57:05 +0000 Subject: [PATCH 05/10] ARM: dts: socfpga: Drop gmac0 from CV dtsi The socfpga_cyclone5.dtsi is included by all DTS files which describe boards using the Cyclone V SoC. The Cyclone V SoC has two ethernet controllers and different boards use none, one or both of them. The /soc/ethernet@ff702000/{} node in socfpga_cyclone5.dtsi unconditionaly enabled gmac0 interface, which is clearly wrong for those boards which use gmac1 interface instead. This patch removes the entire /soc/ethernet@ff702000/{} node from the socfpga_cyclone5.dtsi file. This is correct, since all of the board which include this file also have correct gmac0 or gmac1 node present in them. Minor correction had to be done to EBV SoCrates, which didn't define PHY mode explicitly, but inherited it from the socfpga_cyclone5.dtsi . Signed-off-by: Marek Vasut Cc: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 5 ----- arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 1 + 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 418c19eb2b40..a05e3df23103 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -38,11 +38,6 @@ mmc0: dwmmc0@ff704000 { cap-sd-highspeed; }; - ethernet@ff702000 { - phy-mode = "rgmii"; - status = "okay"; - }; - sysmgr@ffd08000 { cpu1-start-addr = <0xffd080c4>; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index 019dd2fea208..e1a61f20873f 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -36,6 +36,7 @@ leds: gpio-leds { }; &gmac1 { + phy-mode = "rgmii"; status = "okay"; }; From e9f503254a5e0ea6b2b68b4c31491770b47a3ff0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 19 Mar 2016 23:57:45 +0000 Subject: [PATCH 06/10] ARM: dts: socfpga: Add support for HPS LEDs on SoCKit Add support for the blue LEDs on the SoCFPGA SoCkit board. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index b61f22f9ac9f..146169016f0c 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -39,6 +39,34 @@ aliases { ethernet0 = &gmac1; }; + leds { + compatible = "gpio-leds"; + + hps_led0 { + label = "hps:blue:led0"; + gpios = <&portb 24 0>; /* HPS_GPIO53 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led1 { + label = "hps:blue:led1"; + gpios = <&portb 25 0>; /* HPS_GPIO54 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led2 { + label = "hps:blue:led2"; + gpios = <&portb 26 0>; /* HPS_GPIO55 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led3 { + label = "hps:blue:led3"; + gpios = <&portb 27 0>; /* HPS_GPIO56 */ + linux,default-trigger = "heartbeat"; + }; + }; + regulator_3_3v: vcc3p3-regulator { compatible = "regulator-fixed"; regulator-name = "VCC3P3"; @@ -61,6 +89,10 @@ &gmac1 { rxc-skew-ps = <2000>; }; +&gpio1 { /* GPIO 30..57 */ + status = "okay"; +}; + &gpio2 { status = "okay"; }; From 95c16caaa8c1ffff2b58007da3989d7c470069eb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 19 Mar 2016 23:57:46 +0000 Subject: [PATCH 07/10] ARM: dts: socfpga: Add support for HPS KEYs/SWs on SoCKit Add support for the keys and flip-switches on the SoCFPGA SoCkit board. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 62 ++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index 146169016f0c..02e22f554ef0 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -67,6 +67,62 @@ hps_led3 { }; }; + gpio-keys { + compatible = "gpio-keys"; + + hps_sw0 { + label = "hps_sw0"; + gpios = <&portc 20 0>; /* HPS_GPI7 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; /* SW_LID */ + }; + + hps_sw1 { + label = "hps_sw1"; + gpios = <&portc 19 0>; /* HPS_GPI6 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x5>; /* SW_DOCK */ + }; + + hps_sw2 { + label = "hps_sw2"; + gpios = <&portc 18 0>; /* HPS_GPI5 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0xa>; /* SW_KEYPAD_SLIDE */ + }; + + hps_sw3 { + label = "hps_sw3"; + gpios = <&portc 17 0>; /* HPS_GPI4 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0xc>; /* SW_ROTATE_LOCK */ + }; + + hps_hkey0 { + label = "hps_hkey0"; + gpios = <&portc 21 1>; /* HPS_GPI8 */ + linux,code = <187>; /* KEY_F17 */ + }; + + hps_hkey1 { + label = "hps_hkey1"; + gpios = <&portc 22 1>; /* HPS_GPI9 */ + linux,code = <188>; /* KEY_F18 */ + }; + + hps_hkey2 { + label = "hps_hkey2"; + gpios = <&portc 23 1>; /* HPS_GPI10 */ + linux,code = <189>; /* KEY_F19 */ + }; + + hps_hkey3 { + label = "hps_hkey3"; + gpios = <&portc 24 1>; /* HPS_GPI11 */ + linux,code = <190>; /* KEY_F20 */ + }; + }; + regulator_3_3v: vcc3p3-regulator { compatible = "regulator-fixed"; regulator-name = "VCC3P3"; @@ -89,11 +145,15 @@ &gmac1 { rxc-skew-ps = <2000>; }; +&gpio0 { /* GPIO 0..29 */ + status = "okay"; +}; + &gpio1 { /* GPIO 30..57 */ status = "okay"; }; -&gpio2 { +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ status = "okay"; }; From 64ded09d293932621aad94dddf6d14eb0690246a Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Mon, 21 Mar 2016 16:01:46 +0000 Subject: [PATCH 08/10] ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry Add the device tree entries needed to support the Altera L2 cache EDAC on the Arria10 chip. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 8d102d310212..04da5eac8376 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -603,6 +603,21 @@ ocram: sram@ffe00000 { reg = <0xffe00000 0x40000>; }; + eccmgr: eccmgr@ffd06000 { + compatible = "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 IRQ_TYPE_LEVEL_HIGH>; + ranges; + + l2-ecc@ffd06010 { + compatible = "altr,socfpga-a10-l2-ecc"; + reg = <0xffd06010 0x4>; + }; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; From a44a77115f76a7dd7de4396a7ba159eed1d8be21 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Thu, 31 Mar 2016 18:48:07 +0000 Subject: [PATCH 09/10] ARM: dts: socfpga: Add Altera Arria10 OCRAM EDAC devicetree entry Add the device tree entries needed to support the Altera On-Chip RAM EDAC on the Arria10 chip. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 04da5eac8376..4eec2c7f2167 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -616,6 +616,11 @@ l2-ecc@ffd06010 { compatible = "altr,socfpga-a10-l2-ecc"; reg = <0xffd06010 0x4>; }; + + ocram-ecc@ff8c3000 { + compatible = "altr,socfpga-a10-ocram-ecc"; + reg = <0xff8c3000 0x400>; + }; }; rst: rstmgr@ffd05000 { From 249ff32e1f8b6ffa92e1390e371702dd8633bcac Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 23 Mar 2016 15:40:54 -0500 Subject: [PATCH 10/10] ARM: dts: socfpga: add reset control for USB Add the resets property for the 2 USB controllers. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 4 ++++ arch/arm/boot/dts/socfpga_arria10.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b89cbde3b289..9f48141270b8 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -831,6 +831,8 @@ usb0: usb@ffb00000 { interrupts = <0 125 4>; clocks = <&usb_mp_clk>; clock-names = "otg"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -842,6 +844,8 @@ usb1: usb@ffb40000 { interrupts = <0 128 4>; clocks = <&usb_mp_clk>; clock-names = "otg"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4eec2c7f2167..17e81dc9213e 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -713,6 +713,8 @@ usb0: usb@ffb00000 { interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usb_clk>; clock-names = "otg"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -724,6 +726,8 @@ usb1: usb@ffb40000 { interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usb_clk>; clock-names = "otg"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled";