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soc: mediatek: pm-domains: Add support for mt8188

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Add domain control data including bus protection data size
change due to more protection steps in mt8188.

Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221223080553.9397-3-Garmin.Chang@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Garmin.Chang
2022-12-23 16:05:53 +08:00
committed by Matthias Brugger
parent 1725dde87f
commit e610e81464
3 changed files with 749 additions and 0 deletions
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121
include/linux/soc/mediatek/infracfg.h
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@@ -140,6 +140,127 @@
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
#define MT8188_TOP_AXI_PROT_EN_SET 0x2A0
#define MT8188_TOP_AXI_PROT_EN_CLR 0x2A4
#define MT8188_TOP_AXI_PROT_EN_STA 0x228
#define MT8188_TOP_AXI_PROT_EN_1_SET 0x2A8
#define MT8188_TOP_AXI_PROT_EN_1_CLR 0x2AC
#define MT8188_TOP_AXI_PROT_EN_1_STA 0x258
#define MT8188_TOP_AXI_PROT_EN_2_SET 0x714
#define MT8188_TOP_AXI_PROT_EN_2_CLR 0x718
#define MT8188_TOP_AXI_PROT_EN_2_STA 0x724
#define MT8188_TOP_AXI_PROT_EN_MM_SET 0x2D4
#define MT8188_TOP_AXI_PROT_EN_MM_CLR 0x2D8
#define MT8188_TOP_AXI_PROT_EN_MM_STA 0x2EC
#define MT8188_TOP_AXI_PROT_EN_MM_2_SET 0xDCC
#define MT8188_TOP_AXI_PROT_EN_MM_2_CLR 0xDD0
#define MT8188_TOP_AXI_PROT_EN_MM_2_STA 0xDD8
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET 0xB84
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR 0xB88
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA 0xB90
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xBCC
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xBD0
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA 0xBD8
#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP1 BIT(11)
#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2 BIT(7)
#define MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3 BIT(19)
#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(5)
#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP5 GENMASK(22, 21)
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6 BIT(17)
#define MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1 BIT(2)
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2 (BIT(8) | BIT(18) | BIT(30))
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1 BIT(24)
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1 BIT(20)
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1 GENMASK(31, 29)
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2 (GENMASK(4, 3) | BIT(28))
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1 (GENMASK(16, 14) | BIT(23) | \
BIT(27))
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2 (GENMASK(19, 17) | GENMASK(26, 25))
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1 GENMASK(11, 8)
#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2 GENMASK(22, 21)
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1 BIT(20)
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2 BIT(12)
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1 BIT(24)
#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2 BIT(13)
#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1 BIT(10)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2 GENMASK(9, 8)
#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3 BIT(23)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4 (BIT(1) | BIT(4) | BIT(11))
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5 (BIT(20))
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1 (GENMASK(18, 17) | GENMASK(21, 20))
#define MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2 BIT(6)
#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3 BIT(21)
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1 GENMASK(31, 30)
#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2 BIT(22)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3 BIT(10)
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1 BIT(23)
#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1 BIT(22)
#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1 GENMASK(6, 5)
#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2 BIT(23)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3 BIT(18)
#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1 BIT(23)
#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2 BIT(21)
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(13)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(13)
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(14)
#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(29)
#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1 (BIT(9) | BIT(11))
#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2 BIT(26)
#define MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3 BIT(2)
#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1 (BIT(1) | BIT(3))
#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2 BIT(25)
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3 BIT(16)
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1 GENMASK(27, 26)
#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2 GENMASK(25, 24)
#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1 (BIT(2) | BIT(4))
#define MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2 BIT(0)
#define MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3 BIT(22)
#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4 BIT(24)
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5 BIT(17)
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1 GENMASK(31, 30)
#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2 BIT(2)
#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3 GENMASK(29, 28)
#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4 BIT(1)
#define MT8188_SMI_COMMON_CLAMP_EN_STA 0x3C0
#define MT8188_SMI_COMMON_CLAMP_EN_SET 0x3C4
#define MT8188_SMI_COMMON_CLAMP_EN_CLR 0x3C8
#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VDO0 GENMASK(3, 1)
#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VPP1 GENMASK(2, 1)
#define MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1 BIT(0)
#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBA_TO_VPP0 GENMASK(3, 2)
#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBB_TO_VDO0 GENMASK(3, 2)
#define MT8188_SMI_LARB10_RESET_ADDR 0xC
#define MT8188_SMI_LARB11A_RESET_ADDR 0xC
#define MT8188_SMI_LARB11C_RESET_ADDR 0xC
#define MT8188_SMI_LARB12_RESET_ADDR 0xC
#define MT8188_SMI_LARB11B_RESET_ADDR 0xC
#define MT8188_SMI_LARB15_RESET_ADDR 0xC
#define MT8188_SMI_LARB16B_RESET_ADDR 0xA0
#define MT8188_SMI_LARB17B_RESET_ADDR 0xA0
#define MT8188_SMI_LARB16A_RESET_ADDR 0xA0
#define MT8188_SMI_LARB17A_RESET_ADDR 0xA0
#define MT8188_SMI_LARB10_RESET BIT(0)
#define MT8188_SMI_LARB11A_RESET BIT(0)
#define MT8188_SMI_LARB11C_RESET BIT(0)
#define MT8188_SMI_LARB12_RESET BIT(8)
#define MT8188_SMI_LARB11B_RESET BIT(0)
#define MT8188_SMI_LARB15_RESET BIT(0)
#define MT8188_SMI_LARB16B_RESET BIT(4)
#define MT8188_SMI_LARB17B_RESET BIT(4)
#define MT8188_SMI_LARB16A_RESET BIT(4)
#define MT8188_SMI_LARB17A_RESET BIT(4)
#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
#define MT8186_TOP_AXI_PROT_EN_STA (0x228)