From b9631bc2013479ca52c42d1f2cea9051abe9828e Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 31 Jan 2020 11:37:09 +0100 Subject: [PATCH 1/9] ARM: dts: exynos: Fix broken reboot on some Odroid U2/X2/U3 boards The bootloader on Odroid U2/X2/U3 boards configures main ARM clock to 1GHz. During the system shutdown procedure Linux kernel selects so called 'suspend-opp' for the CPU cores, what means that ARM clock is set to 800MHz and the CPU supply voltage is adjusted to that value. PMIC configuration is preserved during the board reboot. Later when the bootloader tries to enter the 1GHz mode, the voltage value configured by the kernel might be not high enough for the CPU to operate stable. This depends on the individual physical properties of each SoC (usually it is related to the production series) and varies between the boards. Typically most of the Odroid U3 boards work fine, while most of the U2 and X2 hangs during the reboot. This commit switches suspend-opp to 1GHz for the Odroid U2/X2/U3 boards, what finally fixes this issue. Signed-off-by: Marek Szyprowski Tested-by: Andrzej Pietrasiewicz Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 9c39e82e4ecb..73d6a71da88d 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -165,6 +165,15 @@ &cpu0 { cpu0-supply = <&buck2_reg>; }; +&cpu0_opp_table { + opp-1000000000 { + opp-suspend; + }; + opp-800000000 { + /delete-property/opp-suspend; + }; +}; + &pinctrl_1 { gpio_power_key: power_key { samsung,pins = "gpx1-3"; From 1c651356f482ff08f6acef197a362f2e71d55a98 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 21 Jan 2020 08:05:10 +0100 Subject: [PATCH 2/9] ARM: dts: exynos: Add GPU thermal zone cooling maps for Odroid XU3/XU4/HC1 Add trip points and cooling maps for GPU thermal zone for Odroid XU3/XU4/HC1 boards. Trip points are based on the CPU thermal zone for the those boards. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidhc1.dts | 30 ++++++++++ .../boot/dts/exynos5422-odroidxu3-common.dtsi | 59 +++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index f163206265bb..812659260278 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -215,6 +215,36 @@ map1 { }; }; }; + gpu_thermal: gpu-thermal { + thermal-sensors = <&tmu_gpu 0>; + trips { + gpu_alert0: gpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + gpu_alert1: gpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + gpu_crit0: gpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu 0 2>; + }; + map1 { + trip = <&gpu_alert1>; + cooling-device = <&gpu 3 6>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 1865a708b49f..5da2d81e3be2 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -357,6 +357,65 @@ cpu3_cooling_map4: map4 { }; }; }; + gpu_thermal: gpu-thermal { + thermal-sensors = <&tmu_gpu 0>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + gpu_alert0: gpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + gpu_alert1: gpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + gpu_alert2: gpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + gpu_crit0: gpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + gpu_alert3: gpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + gpu_alert4: gpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&gpu_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&gpu_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&gpu_alert3>; + cooling-device = <&gpu 0 2>; + }; + map4 { + trip = <&gpu_alert4>; + cooling-device = <&gpu 3 6>; + }; + }; + }; }; }; From e4dcb4ab3b24150d99c9d94123d99f76095f1e3c Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Thu, 20 Feb 2020 09:56:35 +0000 Subject: [PATCH 3/9] ARM: dts: exynos: Add dynamic-power-coefficient to Exynos5422 CPUs To use Energy Aware Scheduler (EAS) the Energy Model (EM) should be registered for CPUs. Add dynamic-power-coefficient into CPU nodes which let CPUFreq subsystem register the EM structures. This will increase energy efficiency of big.LITTLE platforms. The 'dynamic-power-coefficient' values have been obtained experimenting with different workloads. The power measurements taken from big CPU Cluster and LITTLE CPU Cluster has been compared with official documents and synthetic workloads estimations. The effective power ratio between Cortex-A7 and Cortex-A15 CPUs (~3x) is also aligned with documentation. Signed-off-by: Lukasz Luba Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index 1b8605cf2407..4b641b9b8179 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -31,6 +31,7 @@ cpu0: cpu@100 { operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; }; cpu1: cpu@101 { @@ -43,6 +44,7 @@ cpu1: cpu@101 { operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; }; cpu2: cpu@102 { @@ -55,6 +57,7 @@ cpu2: cpu@102 { operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; }; cpu3: cpu@103 { @@ -67,6 +70,7 @@ cpu3: cpu@103 { operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; }; cpu4: cpu@0 { @@ -79,6 +83,7 @@ cpu4: cpu@0 { operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; }; cpu5: cpu@1 { @@ -91,6 +96,7 @@ cpu5: cpu@1 { operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; }; cpu6: cpu@2 { @@ -103,6 +109,7 @@ cpu6: cpu@2 { operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; }; cpu7: cpu@3 { @@ -115,6 +122,7 @@ cpu7: cpu@3 { operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; }; }; }; From a5e7a22d73a63dbb8313b2d831bc60419435a841 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 20 Feb 2020 15:28:05 +0100 Subject: [PATCH 4/9] ARM: dts: exynos: Fix MMC regulator on Arndale5250 board According to the schematic, both eMMC and SDMMC use dedicated fixed regulators connected directly to the DC5V and MAIN_DC rails. Remove the GPX1-1 line assigned to the MMC regulator, because such control connection doesn't exist. Also change its name to VDD_MMC to avoid conflict with LDO18 output of S5M8767 PMIC. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250-arndale.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index f8ebc620f42d..bff24c61212b 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -98,11 +98,9 @@ main_dc_reg: regulator@0 { mmc_reg: regulator@1 { compatible = "regulator-fixed"; reg = <1>; - regulator-name = "VDD_33ON_2.8V"; + regulator-name = "VDD_MMC"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; }; reg_hdmi_en: regulator@2 { From 8f274b90b87840665a751aefd798e771e8e4ef35 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 20 Feb 2020 15:28:06 +0100 Subject: [PATCH 5/9] ARM: dts: exynos: Make fixed regulators always-on on Arndale5250 The fixed regulators defined for Arndale5250 boards have no control lines, so mark them as 'always-on' to better describe the hardware and also kill the strange messages like 'MAIN_DC: disabling' after boot. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250-arndale.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index bff24c61212b..6904091d4837 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -93,6 +93,7 @@ main_dc_reg: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "MAIN_DC"; + regulator-always-on; }; mmc_reg: regulator@1 { @@ -101,12 +102,14 @@ mmc_reg: regulator@1 { regulator-name = "VDD_MMC"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + regulator-always-on; }; reg_hdmi_en: regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "hdmi-en"; + regulator-always-on; }; vcc_1v2_reg: regulator@3 { @@ -115,6 +118,7 @@ vcc_1v2_reg: regulator@3 { regulator-name = "VCC_1V2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-always-on; }; vcc_1v8_reg: regulator@4 { @@ -123,6 +127,7 @@ vcc_1v8_reg: regulator@4 { regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; vcc_3v3_reg: regulator@5 { @@ -131,6 +136,7 @@ vcc_3v3_reg: regulator@5 { regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; }; From 91bf0eee413733ac7975d1f4df64d5bc86d428a0 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 25 Feb 2020 12:40:17 +0100 Subject: [PATCH 6/9] ARM: dts: exynos: Fix memory on Artik5 evaluation boards The last 8MB of physical memory on Artik520 family boards is reserved for secure firmware. Adjust the total amount of the memory defined in exynos3250-artik5.dtsi to match the memory available for the Linux kernel. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-artik5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index dee35e3a5c4b..b27a82072365 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -23,7 +23,7 @@ chosen { memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x1ff00000>; + reg = <0x40000000 0x1f800000>; }; firmware@205f000 { From fbec0a1f775aa03ebb86c16fa761e6f52bb299ea Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 28 Feb 2020 15:55:01 +0100 Subject: [PATCH 7/9] ARM: dts: exynos: Fix G3D power domain supply on Odroid XU3/XU4/HC1 boards G3D power domain in Exynos5422 SoC is supplied from VDD_G3D. Besides the main GPU MALI module it also contains the power domain control logic and clocks. Turning the VDD_G3D power supply off causes the power domain to fail to operate properly and breaks for example system suspend/resume. GPU should use VDD_G3D supply mainly to control the DVFS. Fixes: 1a5a85c56402 ("ARM: dts: exynos: Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4") Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 5cf1aed20490..ab27ff8bc3dc 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -901,6 +901,7 @@ buck4_reg: BUCK4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; regulator-boot-on; + regulator-always-on; regulator-state-mem { regulator-off-in-suspend; From 604e8b79c8864a308a459689c7054a508d52841f Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 28 Feb 2020 15:55:02 +0100 Subject: [PATCH 8/9] ARM: dts: exynos: Fix G3D power domain supply on Arndale Octa boards G3D power domain in Exynos5420 SoC is supplied from PVDD_G3DS_1V0 and PVDD_G3D_1V0. Besides the main GPU MALI module it also contains the power domain control logic and clocks. Turning the power supplies off causes the power domain to fail to operate properly if GPU drivers are loaded as modules. GPU should use PVDD_G3D_1V0 supply mainly to control the DVFS. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index ee28d30f5476..e9a09dd0a49b 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -584,6 +584,7 @@ ldo27_reg: LDO27 { regulator-name = "PVDD_G3DS_1V0"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1100000>; + regulator-always-on; regulator-state-mem { regulator-on-in-suspend; @@ -697,6 +698,7 @@ buck4_reg: BUCK4 { regulator-name = "PVDD_G3D_1V0"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; + regulator-always-on; regulator-state-mem { regulator-off-in-suspend; From 32a1671ff8e84f0dfff3a50d4b2091d25e91f5e2 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 4 Mar 2020 15:37:26 +0100 Subject: [PATCH 9/9] ARM: dts: exynos: Fix polarity of the LCD SPI bus on UniversalC210 board Recent changes in the SPI core and the SPI-GPIO driver revealed that the GPIO lines for the LD9040 LCD controller on the UniversalC210 board are defined incorrectly. Fix the polarity for those lines to match the old behavior and hardware requirements to fix LCD panel operation with recent kernels. Cc: # 5.0.x Signed-off-by: Marek Szyprowski Reviewed-by: Andrzej Hajda Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-universal_c210.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index a1bdf7830a87..9dda6bdb9253 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -115,7 +115,7 @@ spi-lcd { gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>; gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; - cs-gpios = <&gpy4 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; lcd@0 { compatible = "samsung,ld9040"; @@ -124,8 +124,6 @@ lcd@0 { vci-supply = <&ldo17_reg>; reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; spi-max-frequency = <1200000>; - spi-cpol; - spi-cpha; power-on-delay = <10>; reset-delay = <10>; panel-width-mm = <90>;