From 7d7275b3e866cf8092bd12553ec53ba26864f7bb Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Thu, 28 Jan 2021 21:15:48 +0200 Subject: [PATCH 01/53] bus: omap_l3_noc: mark l3 irqs as IRQF_NO_THREAD The main purpose of l3 IRQs is to catch OCP bus access errors and identify corresponding code places by showing call stack, so it's important to handle L3 interconnect errors as fast as possible. On RT these IRQs will became threaded and will be scheduled much more late from the moment actual error occurred so showing completely useless information. Hence, mark l3 IRQs as IRQF_NO_THREAD so they will not be forced threaded on RT or if force_irqthreads = true. Fixes: 0ee7261c9212 ("drivers: bus: Move the OMAP interconnect driver to drivers/bus/") Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- drivers/bus/omap_l3_noc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c index b040447575ad..dcfb32ee5cb6 100644 --- a/drivers/bus/omap_l3_noc.c +++ b/drivers/bus/omap_l3_noc.c @@ -285,7 +285,7 @@ static int omap_l3_probe(struct platform_device *pdev) */ l3->debug_irq = platform_get_irq(pdev, 0); ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler, - 0x0, "l3-dbg-irq", l3); + IRQF_NO_THREAD, "l3-dbg-irq", l3); if (ret) { dev_err(l3->dev, "request_irq failed for %d\n", l3->debug_irq); @@ -294,7 +294,7 @@ static int omap_l3_probe(struct platform_device *pdev) l3->app_irq = platform_get_irq(pdev, 1); ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler, - 0x0, "l3-app-irq", l3); + IRQF_NO_THREAD, "l3-app-irq", l3); if (ret) dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq); From 9bbce32a20d6a72c767a7f85fd6127babd1410ac Mon Sep 17 00:00:00 2001 From: Mans Rullgard Date: Thu, 28 Jan 2021 15:56:44 +0000 Subject: [PATCH 02/53] ARM: dts: am33xx: add aliases for mmc interfaces Without DT aliases, the numbering of mmc interfaces is unpredictable. Adding them makes it possible to refer to devices consistently. The popular suggestion to use UUIDs obviously doesn't work with a blank device fresh from the factory. See commit fa2d0aa96941 ("mmc: core: Allow setting slot index via device tree alias") for more discussion. Signed-off-by: Mans Rullgard Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 5b213a1e68bb..5e33d0e88f5b 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -40,6 +40,9 @@ aliases { ethernet1 = &cpsw_emac1; spi0 = &spi0; spi1 = &spi1; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; }; cpus { From a249ca66d15fa4b54dc6deaff4155df3db1308e1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Feb 2021 10:37:51 +0200 Subject: [PATCH 03/53] soc: ti: omap-prm: Fix reboot issue with invalid pcie reset map for dra7 Yongqin Liu reported an issue where reboot hangs on beagleboard-x15. This started happening after commit 7078a5ba7a58 ("soc: ti: omap-prm: Fix boot time errors for rst_map_012 bits 0 and 1"). We now assert any 012 type resets on init to prevent unconfigured accelerator MMUs getting enabled on init depending on the bootloader or kexec configured state. Turns out that we now also wrongly assert dra7 l3init domain PCIe reset bits causing a hang during reboot. Let's fix the l3init reset bits to use a 01 map instead of 012 map. There are only two rstctrl bits and not three. This is documented in TRM "Table 3-1647. RM_PCIESS_RSTCTRL". Fixes: 5a68c87afde0 ("soc: ti: omap-prm: dra7: add genpd support for remaining PRM instances") Fixes: 7078a5ba7a58 ("soc: ti: omap-prm: Fix boot time errors for rst_map_012 bits 0 and 1") Cc: Kishon Vijay Abraham I Reported-by: Yongqin Liu Signed-off-by: Tony Lindgren --- drivers/soc/ti/omap_prm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index bf1468e5bccb..17ea6a74a988 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -332,7 +332,7 @@ static const struct omap_prm_data dra7_prm_data[] = { { .name = "l3init", .base = 0x4ae07300, .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon, - .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012, + .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01, .clkdm_name = "pcie" }, { From fbfa463be8dc7957ee4f81556e9e1ea2a951807d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Feb 2021 10:53:48 +0200 Subject: [PATCH 04/53] ARM: OMAP2+: Fix smartreflex init regression after dropping legacy data When I dropped legacy data for omap4 and dra7 smartreflex in favor of device tree based data, it seems I only testd for the "SmartReflex Class3 initialized" line in dmesg. I missed the fact that there is also omap_devinit_smartreflex() that happens later, and now it produces an error on boot for "No Voltage table for the corresponding vdd. Cannot create debugfs entries for n-values". This happens as we no longer have the smartreflex instance legacy data, and have not yet moved completely to device tree based booting for the driver. Let's fix the issue by changing the smartreflex init to use names. This should all eventually go away in favor of doing the init in the driver based on devicetree compatible value. Note that dra7xx_init_early() is not calling any voltage domain init like omap54xx_voltagedomains_init(), or a dra7 specific voltagedomains init. This means that on dra7 smartreflex is still not fully initialized, and also seems to be missing the related devicetree nodes. Fixes: a6b1e717e942 ("ARM: OMAP2+: Drop legacy platform data for omap4 smartreflex") Fixes: e54740b4afe8 ("ARM: OMAP2+: Drop legacy platform data for dra7 smartreflex") Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/sr_device.c | 75 +++++++++++++++++++++++++-------- 1 file changed, 58 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 62df666c2bd0..17b66f0d0dee 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -88,34 +88,26 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data, extern struct omap_sr_data omap_sr_pdata[]; -static int __init sr_dev_init(struct omap_hwmod *oh, void *user) +static int __init sr_init_by_name(const char *name, const char *voltdm) { struct omap_sr_data *sr_data = NULL; struct omap_volt_data *volt_data; - struct omap_smartreflex_dev_attr *sr_dev_attr; static int i; - if (!strncmp(oh->name, "smartreflex_mpu_iva", 20) || - !strncmp(oh->name, "smartreflex_mpu", 16)) + if (!strncmp(name, "smartreflex_mpu_iva", 20) || + !strncmp(name, "smartreflex_mpu", 16)) sr_data = &omap_sr_pdata[OMAP_SR_MPU]; - else if (!strncmp(oh->name, "smartreflex_core", 17)) + else if (!strncmp(name, "smartreflex_core", 17)) sr_data = &omap_sr_pdata[OMAP_SR_CORE]; - else if (!strncmp(oh->name, "smartreflex_iva", 16)) + else if (!strncmp(name, "smartreflex_iva", 16)) sr_data = &omap_sr_pdata[OMAP_SR_IVA]; if (!sr_data) { - pr_err("%s: Unknown instance %s\n", __func__, oh->name); + pr_err("%s: Unknown instance %s\n", __func__, name); return -EINVAL; } - sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr; - if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) { - pr_err("%s: No voltage domain specified for %s. Cannot initialize\n", - __func__, oh->name); - goto exit; - } - - sr_data->name = oh->name; + sr_data->name = name; if (cpu_is_omap343x()) sr_data->ip_type = 1; else @@ -136,10 +128,10 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) } } - sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name); + sr_data->voltdm = voltdm_lookup(voltdm); if (!sr_data->voltdm) { pr_err("%s: Unable to get voltage domain pointer for VDD %s\n", - __func__, sr_dev_attr->sensor_voltdm_name); + __func__, voltdm); goto exit; } @@ -160,6 +152,20 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) return 0; } +static int __init sr_dev_init(struct omap_hwmod *oh, void *user) +{ + struct omap_smartreflex_dev_attr *sr_dev_attr; + + sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr; + if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) { + pr_err("%s: No voltage domain specified for %s. Cannot initialize\n", + __func__, oh->name); + return 0; + } + + return sr_init_by_name(oh->name, sr_dev_attr->sensor_voltdm_name); +} + /* * API to be called from board files to enable smartreflex * autocompensation at init. @@ -169,7 +175,42 @@ void __init omap_enable_smartreflex_on_init(void) sr_enable_on_init = true; } +static const char * const omap4_sr_instances[] = { + "mpu", + "iva", + "core", +}; + +static const char * const dra7_sr_instances[] = { + "mpu", + "core", +}; + int __init omap_devinit_smartreflex(void) { + const char * const *sr_inst; + int i, nr_sr = 0; + + if (soc_is_omap44xx()) { + sr_inst = omap4_sr_instances; + nr_sr = ARRAY_SIZE(omap4_sr_instances); + + } else if (soc_is_dra7xx()) { + sr_inst = dra7_sr_instances; + nr_sr = ARRAY_SIZE(dra7_sr_instances); + } + + if (nr_sr) { + const char *name, *voltdm; + + for (i = 0; i < nr_sr; i++) { + name = kasprintf(GFP_KERNEL, "smartreflex_%s", sr_inst[i]); + voltdm = sr_inst[i]; + sr_init_by_name(name, voltdm); + } + + return 0; + } + return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL); } From a7b5d7c4969aba8d1f04c29048906abaa71fb6a9 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 18 Feb 2021 13:06:57 +0200 Subject: [PATCH 05/53] bus: ti-sysc: Fix warning on unbind if reset is not deasserted We currently get thefollowing on driver unbind if a reset is configured and asserted: WARNING: CPU: 0 PID: 993 at drivers/reset/core.c:432 reset_control_assert ... (reset_control_assert) from [] (sysc_remove+0x190/0x1e4) (sysc_remove) from [] (platform_remove+0x24/0x3c) (platform_remove) from [] (__device_release_driver+0x154/0x214) (__device_release_driver) from [] (device_driver_detach+0x3c/0x8c) (device_driver_detach) from [] (unbind_store+0x60/0xd4) (unbind_store) from [] (kernfs_fop_write_iter+0x10c/0x1cc) Let's fix it by checking the reset status. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index a27d751cf219..3d74f237f005 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -3053,7 +3053,9 @@ static int sysc_remove(struct platform_device *pdev) pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); - reset_control_assert(ddata->rsts); + + if (!reset_control_status(ddata->rsts)) + reset_control_assert(ddata->rsts); unprepare: sysc_unprepare(ddata); From effe89e40037038db7711bdab5d3401fe297d72c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 18 Feb 2021 13:46:33 +0200 Subject: [PATCH 06/53] soc: ti: omap-prm: Fix occasional abort on reset deassert for dra7 iva On reset deassert, we must wait a bit after the rstst bit change before we allow clockdomain autoidle again. Otherwise we get the following oops sometimes on dra7 with iva: Unhandled fault: imprecise external abort (0x1406) at 0x00000000 44000000.ocp:L3 Standard Error: MASTER MPU TARGET IVA_CONFIG (Read Link): At Address: 0x0005A410 : Data Access in User mode during Functional access Internal error: : 1406 [#1] SMP ARM ... (sysc_write_sysconfig) from [] (sysc_enable_module+0xcc/0x260) (sysc_enable_module) from [] (sysc_runtime_resume+0xc8/0x174) (sysc_runtime_resume) from [] (genpd_runtime_resume+0x94/0x224) (genpd_runtime_resume) from [] (__rpm_callback+0xd8/0x180) It is unclear what all devices this might affect, but presumably other devices with the rstst bit too can be affected. So let's just enable the delay for all the devices with rstst bit for now. Later on we may want to limit the list to the know affected devices if needed. Fixes: d30cd83f6853 ("soc: ti: omap-prm: add support for denying idle for reset clockdomain") Reported-by: Yongqin Liu Signed-off-by: Tony Lindgren --- drivers/soc/ti/omap_prm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 17ea6a74a988..51143a68a889 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -830,8 +830,12 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, reset->prm->data->name, id); exit: - if (reset->clkdm) + if (reset->clkdm) { + /* At least dra7 iva needs a delay before clkdm idle */ + if (has_rstst) + udelay(1); pdata->clkdm_allow_idle(reset->clkdm); + } return ret; } From 140a776833957539c84301dbdb4c3013876de118 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 8 Mar 2021 11:26:25 +0200 Subject: [PATCH 07/53] ARM: dts: Drop duplicate sha2md5_fck to fix clk_disable race We have a duplicate legacy clock defined for sha2md5_fck that can sometimes race with clk_disable() with the dts configured clock for OMAP4_SHA2MD5_CLKCTRL when unused clocks are disabled during boot causing an "Unhandled fault: imprecise external abort". Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap44xx-clocks.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 532868591107..1f1c04d8f472 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -770,14 +770,6 @@ per_abe_nc_fclk: per_abe_nc_fclk@108 { ti,max-div = <2>; }; - sha2md5_fck: sha2md5_fck@15c8 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x15c8>; - }; - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; From 77335a040178a0456d4eabc8bf17a7ca3ee4a327 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 8 Mar 2021 11:30:45 +0200 Subject: [PATCH 08/53] ARM: dts: Fix moving mmc devices with aliases for omap4 & 5 Fix moving mmc devices with dts aliases as discussed on the lists. Without this we now have internal eMMC mmc1 show up as mmc2 compared to the earlier order of devices. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 5 +++++ arch/arm/boot/dts/omap5.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 72e4f6481776..4a9f9496a867 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -22,6 +22,11 @@ aliases { i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; + mmc3 = &mmc4; + mmc4 = &mmc5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index e025b7c9a357..ee821d0ab364 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -25,6 +25,11 @@ aliases { i2c2 = &i2c3; i2c3 = &i2c4; i2c4 = &i2c5; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; + mmc3 = &mmc4; + mmc4 = &mmc5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; From 7bad5af826aba00487fed9a3300d3f43f0cba11b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 8 Mar 2021 11:35:06 +0200 Subject: [PATCH 09/53] bus: ti-sysc: Fix initializing module_pa for modules without sysc register We have interconnect target modules with no known registers using only clocks and resets, but we still want to detect them based on the module IO range. So let's call sysc_parse_and_check_child_range() earlier so we have module_pa properly initialized. Fixes: 2928135c93f8 ("bus: ti-sysc: Support modules without control registers") Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 3d74f237f005..f6491bcfe5a6 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -856,15 +856,15 @@ static int sysc_map_and_check_registers(struct sysc *ddata) struct device_node *np = ddata->dev->of_node; int error; - if (!of_get_property(np, "reg", NULL)) - return 0; - error = sysc_parse_and_check_child_range(ddata); if (error) return error; sysc_check_children(ddata); + if (!of_get_property(np, "reg", NULL)) + return 0; + error = sysc_parse_registers(ddata); if (error) return error; From 4700a00755fb5a4bb5109128297d6fd2d1272ee6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 8 Mar 2021 11:35:07 +0200 Subject: [PATCH 10/53] bus: ti-sysc: Probe for l4_wkup and l4_cfg interconnect devices first We want to probe l4_wkup and l4_cfg interconnect devices first to avoid issues with missing resources. Otherwise we attempt to probe l4_per devices first causing pointless deferred probe and also annoyingh renumbering of the MMC devices for example. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 49 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index f6491bcfe5a6..68145e326eb9 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -635,6 +635,51 @@ static int sysc_parse_and_check_child_range(struct sysc *ddata) return 0; } +/* Interconnect instances to probe before l4_per instances */ +static struct resource early_bus_ranges[] = { + /* am3/4 l4_wkup */ + { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, }, + /* omap4/5 and dra7 l4_cfg */ + { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, }, + /* omap4 l4_wkup */ + { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, }, + /* omap5 and dra7 l4_wkup without dra7 dcan segment */ + { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, }, +}; + +static atomic_t sysc_defer = ATOMIC_INIT(10); + +/** + * sysc_defer_non_critical - defer non_critical interconnect probing + * @ddata: device driver data + * + * We want to probe l4_cfg and l4_wkup interconnect instances before any + * l4_per instances as l4_per instances depend on resources on l4_cfg and + * l4_wkup interconnects. + */ +static int sysc_defer_non_critical(struct sysc *ddata) +{ + struct resource *res; + int i; + + if (!atomic_read(&sysc_defer)) + return 0; + + for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) { + res = &early_bus_ranges[i]; + if (ddata->module_pa >= res->start && + ddata->module_pa <= res->end) { + atomic_set(&sysc_defer, 0); + + return 0; + } + } + + atomic_dec_if_positive(&sysc_defer); + + return -EPROBE_DEFER; +} + static struct device_node *stdout_path; static void sysc_init_stdout_path(struct sysc *ddata) @@ -860,6 +905,10 @@ static int sysc_map_and_check_registers(struct sysc *ddata) if (error) return error; + error = sysc_defer_non_critical(ddata); + if (error) + return error; + sysc_check_children(ddata); if (!of_get_property(np, "reg", NULL)) From f2dc0755fc9b4628d38e4832ecf207ce135b93ae Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 8 Mar 2021 11:35:07 +0200 Subject: [PATCH 11/53] bus: ti-sysc: Detect more modules for debugging We want to see what the interconnect target module names are for debugging. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 68145e326eb9..b715e5901373 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1496,12 +1496,16 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), + SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), + SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0), + SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0), SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), + SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0), SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), @@ -1513,11 +1517,14 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), + SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), + SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), + SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, 0), SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), From 5f7259a578e9c6759255996b86be5bed41d62193 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 8 Mar 2021 11:35:09 +0200 Subject: [PATCH 12/53] bus: ti-sysc: Check for old incomplete dtb Let's be nice and show an error on the SoCs about old imcomplete devicetree if the dtb is still using "simple-bus" instead of "simple-pm-bus" for the root OCP node. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index b715e5901373..65943d1a2557 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -2858,6 +2858,7 @@ static int sysc_init_soc(struct sysc *ddata) const struct soc_device_attribute *match; struct ti_sysc_platform_data *pdata; unsigned long features = 0; + struct device_node *np; if (sysc_soc) return 0; @@ -2878,6 +2879,21 @@ static int sysc_init_soc(struct sysc *ddata) if (match && match->data) sysc_soc->soc = (int)match->data; + /* + * Check and warn about possible old incomplete dtb. We now want to see + * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs. + */ + switch (sysc_soc->soc) { + case SOC_AM3: + case SOC_AM4: + np = of_find_node_by_path("/ocp"); + WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"), + "ti-sysc: Incomplete old dtb, please update\n"); + break; + default: + break; + } + /* Ignore devices that are not available on HS and EMU SoCs */ if (!sysc_soc->general_purpose) { switch (sysc_soc->soc) { From a15de032a72d511431294331f4bb47245f18b801 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 8 Mar 2021 11:35:08 +0200 Subject: [PATCH 13/53] ARM: OMAP2+: Init both prm and prcm nodes early for clocks We need to probe both prm and prcm nodes early for clocks as they are needed by system timers. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pdata-quirks.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 2e3a10914c40..9f304525b193 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -569,10 +569,29 @@ static void pdata_quirks_check(struct pdata_init *quirks) } } -void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) +static const char * const pdata_quirks_init_nodes[] = { + "prcm", + "prm", +}; + +void __init +pdata_quirks_init_clocks(const struct of_device_id *omap_dt_match_table) { struct device_node *np; + int i; + for (i = 0; i < ARRAY_SIZE(pdata_quirks_init_nodes); i++) { + np = of_find_node_by_name(NULL, pdata_quirks_init_nodes[i]); + if (!np) + continue; + + of_platform_populate(np, omap_dt_match_table, + omap_auxdata_lookup, NULL); + } +} + +void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) +{ /* * We still need this for omap2420 and omap3 PM to work, others are * using drivers/misc/sram.c already. @@ -585,13 +604,7 @@ void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) omap3_mcbsp_init(); pdata_quirks_check(auxdata_quirks); - /* Populate always-on PRCM in l4_wkup to probe l4_wkup */ - np = of_find_node_by_name(NULL, "prcm"); - if (!np) - np = of_find_node_by_name(NULL, "prm"); - if (np) - of_platform_populate(np, omap_dt_match_table, - omap_auxdata_lookup, NULL); + pdata_quirks_init_clocks(omap_dt_match_table); of_platform_populate(NULL, omap_dt_match_table, omap_auxdata_lookup, NULL); From bc0b964da3f692a08f648f0dac328785ada38f68 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 8 Mar 2021 11:35:08 +0200 Subject: [PATCH 14/53] soc: ti: omap-prm: Allow hardware supported retention when idle When moving the l4 interconnect instances to probe with simple-pm-bus and genpd, we will have l4per and core domains stop idling unless we configure the domain bits to allow retention when idle. As the TI SoCs have hardware autoidle capabilities, this is safe to do. The domains will only enter retention on WFI when none of the devices on the domain block autoidle in the hardware. This follows what we are already currently doing. Cc: Santosh Shilimkar Cc: Tero Kristo Signed-off-by: Tony Lindgren --- drivers/soc/ti/omap_prm.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 51143a68a889..ea64e187854e 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -88,6 +88,7 @@ struct omap_reset_data { #define OMAP_PRM_HAS_RSTCTRL BIT(0) #define OMAP_PRM_HAS_RSTST BIT(1) #define OMAP_PRM_HAS_NO_CLKDM BIT(2) +#define OMAP_PRM_RET_WHEN_IDLE BIT(3) #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) @@ -174,7 +175,8 @@ static const struct omap_prm_data omap4_prm_data[] = { .name = "core", .base = 0x4a306700, .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati", - .rstmap = rst_map_012 + .rstmap = rst_map_012, + .flags = OMAP_PRM_RET_WHEN_IDLE, }, { .name = "ivahd", .base = 0x4a306f00, @@ -199,7 +201,8 @@ static const struct omap_prm_data omap4_prm_data[] = { }, { .name = "l4per", .base = 0x4a307400, - .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton + .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton, + .flags = OMAP_PRM_RET_WHEN_IDLE, }, { .name = "cefuse", .base = 0x4a307600, @@ -517,7 +520,7 @@ static int omap_prm_domain_power_on(struct generic_pm_domain *domain) { struct omap_prm_domain *prmd; int ret; - u32 v; + u32 v, mode; prmd = genpd_to_prm_domain(domain); if (!prmd->cap) @@ -530,7 +533,12 @@ static int omap_prm_domain_power_on(struct generic_pm_domain *domain) else v = readl_relaxed(prmd->prm->base + prmd->pwrstctrl); - writel_relaxed(v | OMAP_PRMD_ON_ACTIVE, + if (prmd->prm->data->flags & OMAP_PRM_RET_WHEN_IDLE) + mode = OMAP_PRMD_RETENTION; + else + mode = OMAP_PRMD_ON_ACTIVE; + + writel_relaxed((v & ~PRM_POWERSTATE_MASK) | mode, prmd->prm->base + prmd->pwrstctrl); /* wait for the transition bit to get cleared */ From 7f7acef8571a239568abaf5f3dc7694d18ae970b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 8 Mar 2021 11:35:08 +0200 Subject: [PATCH 15/53] clk: ti: omap5: Add missing gpmc and ocmc clkctrl The gpmc clock is needed to update omap5 to boot with genpd with the related devicetree patches. The ocmc clock is currently not used but let's add it so we have all the clocks for the l3main2 defined. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren --- drivers/clk/ti/clk-54xx.c | 2 ++ include/dt-bindings/clock/omap5.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index f0542391ca4b..90e0a9ea6351 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -156,6 +156,8 @@ static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initcon static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = { { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { OMAP5_L3_MAIN_2_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, { 0 }, }; diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h index 41775272fd27..90e0d4b00127 100644 --- a/include/dt-bindings/clock/omap5.h +++ b/include/dt-bindings/clock/omap5.h @@ -32,6 +32,8 @@ /* l3main2 clocks */ #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_L3_MAIN_2_GPMC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) /* ipu clocks */ #define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) From e259c2926c016dd815e5547412356d378fc1f589 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:01:00 +0200 Subject: [PATCH 16/53] PCI: pci-dra7xx: Prepare for deferred probe with module_platform_driver After updating pci-dra7xx driver to probe with ti-sysc and genpd, I noticed that dra7xx_pcie_probe() would not run if a power-domains property was configured for the interconnect target module. Turns out that module_platform_driver_probe uses platform_driver_probe(), while builtin_platform_driver uses platform_driver_register(). Only platform_driver_register() works for deferred probe as noted in the comments for __platform_driver_probe() in drivers/base/platform.c with a line saying "Note that this is incompatible with deferred probing". With module_platform_driver_probe, we have platform_driver_probe() produce -ENODEV error at device_initcall() level, and no further attempts are done. Let's fix this by using module_platform_driver instead. Note this is not an issue currently as we probe devices with simple-bus, and only is needed as we start probing the device with ti-sysc, or when probed with simple-pm-bus. Note that we must now also remove __init for probe related functions to avoid a section mismatch warning. Cc: linux-pci@vger.kernel.org Cc: Bjorn Helgaas Cc: Lorenzo Pieralisi Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- drivers/pci/controller/dwc/pci-dra7xx.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index b105af63854a..047cfbdc1330 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -443,8 +443,8 @@ static const struct dw_pcie_ep_ops pcie_ep_ops = { .get_features = dra7xx_pcie_get_features, }; -static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, - struct platform_device *pdev) +static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, + struct platform_device *pdev) { int ret; struct dw_pcie_ep *ep; @@ -472,8 +472,8 @@ static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, return 0; } -static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, - struct platform_device *pdev) +static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, + struct platform_device *pdev) { int ret; struct dw_pcie *pci = dra7xx->pci; @@ -682,7 +682,7 @@ static int dra7xx_pcie_configure_two_lane(struct device *dev, return 0; } -static int __init dra7xx_pcie_probe(struct platform_device *pdev) +static int dra7xx_pcie_probe(struct platform_device *pdev) { u32 reg; int ret; @@ -938,6 +938,7 @@ static const struct dev_pm_ops dra7xx_pcie_pm_ops = { }; static struct platform_driver dra7xx_pcie_driver = { + .probe = dra7xx_pcie_probe, .driver = { .name = "dra7-pcie", .of_match_table = of_dra7xx_pcie_match, @@ -946,4 +947,4 @@ static struct platform_driver dra7xx_pcie_driver = { }, .shutdown = dra7xx_pcie_shutdown, }; -builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe); +builtin_platform_driver(dra7xx_pcie_driver); From c761028ef5e27f477fe14d2b134164c584fc21ee Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:45 +0200 Subject: [PATCH 17/53] ARM: dts: Update pcie ranges for dra7 In order to update pcie to probe with ti-sysc and genpd, let's update the pcie ranges to not use address 0 for 0x20000000 and 0x30000000. The range for 0 is typically used for child devices as the offset from the module base. In the following patches, we will update pcie to probe with ti-sysc, and the patches become a bit confusing to read compared to other similar modules unless we update the ranges first. So let's just use the full addresses for ranges for the 0x20000000 and 0x30000000 ranges. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ce1194744f84..39614c7232bf 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -170,22 +170,24 @@ axi@0 { compatible = "simple-bus"; #size-cells = <1>; #address-cells = <1>; - ranges = <0x51000000 0x51000000 0x3000 - 0x0 0x20000000 0x10000000>; + ranges = <0x51000000 0x51000000 0x3000>, + <0x20000000 0x20000000 0x10000000>; dma-ranges; /** * To enable PCI endpoint mode, disable the pcie1_rc * node and enable pcie1_ep mode. */ pcie1_rc: pcie@51000000 { - reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; + reg = <0x51000000 0x2000>, + <0x51002000 0x14c>, + <0x20001000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; interrupts = <0 232 0x4>, <0 233 0x4>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x03000 0 0x00010000 - 0x82000000 0 0x20013000 0x13000 0 0xffed000>; + ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>, + <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; @@ -209,7 +211,10 @@ pcie1_intc: interrupt-controller { }; pcie1_ep: pcie_ep@51000000 { - reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; + reg = <0x51000000 0x28>, + <0x51002000 0x14c>, + <0x51001000 0x28>, + <0x20001000 0x10000000>; reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; interrupts = <0 232 0x4>; num-lanes = <1>; @@ -228,19 +233,21 @@ axi@1 { compatible = "simple-bus"; #size-cells = <1>; #address-cells = <1>; - ranges = <0x51800000 0x51800000 0x3000 - 0x0 0x30000000 0x10000000>; + ranges = <0x51800000 0x51800000 0x3000>, + <0x30000000 0x30000000 0x10000000>; dma-ranges; status = "disabled"; pcie2_rc: pcie@51800000 { - reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; + reg = <0x51800000 0x2000>, + <0x51802000 0x14c>, + <0x30001000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; interrupts = <0 355 0x4>, <0 356 0x4>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x03000 0 0x00010000 - 0x82000000 0 0x30013000 0x13000 0 0xffed000>; + ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>, + <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; From 785d943c768ef631271d1ed5caef1c162e001d6b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:45 +0200 Subject: [PATCH 18/53] ARM: dts: Configure interconnect target module for dra7 pcie We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 39614c7232bf..f7e40227d7de 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -166,8 +166,21 @@ l4_per2: interconnect@48400000 { l4_per3: interconnect@48800000 { }; - axi@0 { - compatible = "simple-bus"; + /* + * Register access seems to have complex dependencies and also + * seems to need an enabled phy. See the TRM chapter for "Table + * 26-678. Main Sequence PCIe Controller Global Initialization" + * and also dra7xx_pcie_probe(). + */ + axi0: target-module@51000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + power-domains = <&prm_l3init>; + resets = <&prm_l3init 0>; + reset-names = "rstctrl"; + clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>; + clock-names = "fck", "phy-clk", "phy-clk-div"; #size-cells = <1>; #address-cells = <1>; ranges = <0x51000000 0x51000000 0x3000>, @@ -229,8 +242,21 @@ pcie1_ep: pcie_ep@51000000 { }; }; - axi@1 { - compatible = "simple-bus"; + /* + * Register access seems to have complex dependencies and also + * seems to need an enabled phy. See the TRM chapter for "Table + * 26-678. Main Sequence PCIe Controller Global Initialization" + * and also dra7xx_pcie_probe(). + */ + axi1: target-module@51800000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>; + clock-names = "fck", "phy-clk", "phy-clk-div"; + power-domains = <&prm_l3init>; + resets = <&prm_l3init 1>; + reset-names = "rstctrl"; #size-cells = <1>; #address-cells = <1>; ranges = <0x51800000 0x51800000 0x3000>, From 075249bc554614199f893061082741c1b2ceac29 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:45 +0200 Subject: [PATCH 19/53] ARM: dts: Properly configure dra7 edma sysconfig registers Looks like the TRM is not listing the sysconfig for edma, let's add it based on am437x TRM edma registers as listed in sections "Table 10-26. EDMA3CC Registers" and "Table 10-99. EDMA3TC Registers". Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index f7e40227d7de..4906e2f47486 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -369,8 +369,15 @@ dra7_iodelay_core: padconf@4844a000 { target-module@43300000 { compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x43300000 0x4>; - reg-names = "rev"; + reg = <0x43300000 0x4>, + <0x43300010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; @@ -402,8 +409,15 @@ edma: dma@0 { target-module@43400000 { compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x43400000 0x4>; - reg-names = "rev"; + reg = <0x43400000 0x4>, + <0x43400010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; @@ -420,8 +434,15 @@ edma_tptc0: dma@0 { target-module@43500000 { compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x43500000 0x4>; - reg-names = "rev"; + reg = <0x43500000 0x4>, + <0x43500010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; From 7f2659ce657e87cb7f47e6b15099608eaa1349ac Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:46 +0200 Subject: [PATCH 20/53] ARM: dts: Move dra7 l3 noc to a separate node In order to prepare for probing l3 with genpd, we need to move l3 noc into a separate node for l3 interconnect to have it's own regs, and to avoid it claiming more than it needs for the io regions. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4906e2f47486..dff9262ca677 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -144,16 +144,20 @@ mpu { * hierarchy. */ ocp: ocp { - compatible = "ti,dra7-l3-noc", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; ti,hwmods = "l3_main_1", "l3_main_2"; - reg = <0x0 0x44000000 0x0 0x1000000>, - <0x0 0x45000000 0x0 0x1000>; - interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + + l3-noc@44000000 { + compatible = "ti,dra7-l3-noc"; + reg = <0x44000000 0x1000>, + <0x45000000 0x1000>; + interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; l4_cfg: interconnect@4a000000 { }; From e2d637b069783f9db6cc76b8296f830f937a64f3 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:46 +0200 Subject: [PATCH 21/53] ARM: dts: Configure interconnect target module for dra7 qspi We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Vignesh Raghavendra Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 41 ++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index dff9262ca677..91d5763b09f4 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -752,20 +752,37 @@ abb_gpu: regulator-abb-gpu { >; }; - qspi: spi@4b300000 { - compatible = "ti,dra7xxx-qspi"; - reg = <0x4b300000 0x100>, - <0x5c000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - syscon-chipselects = <&scm_conf 0x558>; - #address-cells = <1>; - #size-cells = <0>; + target-module@4b300000 { + compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "qspi"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; + reg = <0x4b300000 0x4>, + <0x4b300010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>; clock-names = "fck"; - num-cs = <4>; - interrupts = ; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b300000 0x1000>, + <0x5c000000 0x5c000000 0x4000000>; + + qspi: spi@0 { + compatible = "ti,dra7xxx-qspi"; + reg = <0 0x100>, + <0x5c000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; + syscon-chipselects = <&scm_conf 0x558>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; + clock-names = "fck"; + num-cs = <4>; + interrupts = ; + status = "disabled"; + }; }; /* OCP2SCP3 */ From 8af15365a36845c4c15d4c8046ddccff331d5263 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:47 +0200 Subject: [PATCH 22/53] ARM: dts: Configure interconnect target module for dra7 sata We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Note that the old sysc register offset is wrong, the real offset is at 0x1100 as listed in TRM for SATA_SYSCONFIG register. Looks like we've been happily using sata on the bootloader configured sysconfig register and nobody noticed. Also the old register range for SATAMAC_wrapper registers is wrong at 7 while it should be 8. But that too seems harmless. There is also an L3 parent interconnect range that we don't seem to be using. That can be added as needed later on. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 29 ++++++++++++++++++++++++++--- arch/arm/boot/dts/dra7.dtsi | 12 ------------ 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 3bf90d9e3335..2c5c682a15ee 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -572,11 +572,34 @@ target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ }; target-module@40000 { /* 0x4a140000, ap 31 06.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "sata"; + reg = <0x400fc 4>, + <0x41100 4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + , + ; + power-domains = <&prm_l3init>; + clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>; + clock-names = "fck"; #size-cells = <1>; + #address-cells = <1>; ranges = <0x0 0x40000 0x10000>; + + sata: sata@0 { + compatible = "snps,dwc-ahci"; + reg = <0 0x1100>, <0x1100 0x8>; + interrupts = ; + phys = <&sata_phy>; + phy-names = "sata-phy"; + clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; + ports-implemented = <0x1>; + }; }; target-module@51000 { /* 0x4a151000, ap 33 50.0 */ diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 91d5763b09f4..e9f3435521ee 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -785,18 +785,6 @@ qspi: spi@0 { }; }; - /* OCP2SCP3 */ - sata: sata@4a141100 { - compatible = "snps,dwc-ahci"; - reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = ; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; - ti,hwmods = "sata"; - ports-implemented = <0x1>; - }; - /* OCP2SCP1 */ /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ From f5d0aba7c198ea653df92c1afb94484c9f0fc483 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:47 +0200 Subject: [PATCH 23/53] ARM: dts: Configure interconnect target module for dra7 mpu We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e9f3435521ee..a2e053e44528 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -124,18 +124,6 @@ opp_high@1500000000 { }; }; - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap5-mpu"; - ti,hwmods = "mpu"; - }; - }; - /* * XXX: Use a flat representation of the SOC interconnect. * The real OMAP interconnect network is quite complex. @@ -165,6 +153,21 @@ l4_wkup: interconnect@4ae00000 { }; l4_per1: interconnect@48000000 { }; + + target-module@48210000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_mpu>; + clocks = <&mpu_clkctrl DRA7_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48210000 0x1f0000>; + + mpu { + compatible = "ti,omap5-mpu"; + }; + }; + l4_per2: interconnect@48400000 { }; l4_per3: interconnect@48800000 { From 27559a8bd436495b5bbda63b9657eb14a345f266 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:47 +0200 Subject: [PATCH 24/53] ARM: dts: Configure interconnect target module for dra7 dmm We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index a2e053e44528..c2b5135d9763 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -464,11 +464,24 @@ edma_tptc1: dma@0 { }; }; - dmm@4e000000 { - compatible = "ti,omap5-dmm"; - reg = <0x4e000000 0x800>; - interrupts = ; + target-module@4e000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "dmm"; + reg = <0x4e000000 0x4>, + <0x4e000010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + ranges = <0x0 0x4e000000 0x2000000>; + #size-cells = <1>; + #address-cells = <1>; + + dmm@0 { + compatible = "ti,omap5-dmm"; + reg = <0 0x800>; + interrupts = ; + }; }; ipu1: ipu@58820000 { From 9a75368b6426739e8b798592f084cb682d760568 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:48 +0200 Subject: [PATCH 25/53] ARM: dts: Configure simple-pm-bus for dra7 l4_wkup We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 2c5c682a15ee..720d1e736d90 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -4228,7 +4228,10 @@ vpe: vpe@0 { }; &l4_wkup { /* 0x4ae00000 */ - compatible = "ti,dra7-l4-wkup", "simple-bus"; + compatible = "ti,dra7-l4-wkup", "simple-pm-bus"; + power-domains = <&prm_wkupaon>; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>; + clock-names = "fck"; reg = <0x4ae00000 0x800>, <0x4ae00800 0x800>, <0x4ae01000 0x1000>; @@ -4241,7 +4244,7 @@ &l4_wkup { /* 0x4ae00000 */ <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ segment@0 { /* 0x4ae00000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -4318,7 +4321,7 @@ scm_wkup: scm_conf@0 { }; segment@10000 { /* 0x4ae10000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ @@ -4428,7 +4431,7 @@ target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ }; segment@20000 { /* 0x4ae20000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ @@ -4534,7 +4537,7 @@ target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ }; segment@30000 { /* 0x4ae30000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ From f483a3e123410bd1c78af295bf65feffb6769a98 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:48 +0200 Subject: [PATCH 26/53] ARM: dts: Configure simple-pm-bus for dra7 l4_per1 We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 720d1e736d90..270ec797717d 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -1029,7 +1029,10 @@ target-module@36000 { /* 0x4a236000, ap 119 62.0 */ }; &l4_per1 { /* 0x48000000 */ - compatible = "ti,dra7-l4-per1", "simple-bus"; + compatible = "ti,dra7-l4-per1", "simple-pm-bus"; + power-domains = <&prm_l4per>; + clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>; + clock-names = "fck"; reg = <0x48000000 0x800>, <0x48000800 0x800>, <0x48001000 0x400>, @@ -1043,7 +1046,7 @@ &l4_per1 { /* 0x48000000 */ <0x00200000 0x48200000 0x200000>; /* segment 1 */ segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -2292,7 +2295,7 @@ target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ }; segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; }; From 26c36e16d45e3e18bb8d9a082c0799e471e647d6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:49 +0200 Subject: [PATCH 27/53] ARM: dts: Configure simple-pm-bus for dra7 l4_per2 We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 270ec797717d..1435f42d1f35 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -2302,7 +2302,10 @@ segment@200000 { /* 0x48200000 */ }; &l4_per2 { /* 0x48400000 */ - compatible = "ti,dra7-l4-per2", "simple-bus"; + compatible = "ti,dra7-l4-per2", "simple-pm-bus"; + power-domains = <&prm_l4per>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>; + clock-names = "fck"; reg = <0x48400000 0x800>, <0x48400800 0x800>, <0x48401000 0x400>, @@ -2322,7 +2325,7 @@ &l4_per2 { /* 0x48400000 */ <0x48454000 0x48454000 0x400000>; /* L3 data port */ segment@0 { /* 0x48400000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ From bdfafc8e2b3d9587e4bacdf0c25a70c2b429a6d7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:49 +0200 Subject: [PATCH 28/53] ARM: dts: Configure simple-pm-bus for dra7 l4_per3 We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 1435f42d1f35..64935a09cab4 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -3123,7 +3123,10 @@ cpts { }; &l4_per3 { /* 0x48800000 */ - compatible = "ti,dra7-l4-per3", "simple-bus"; + compatible = "ti,dra7-l4-per3", "simple-pm-bus"; + power-domains = <&prm_l4per>; + clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>; + clock-names = "fck"; reg = <0x48800000 0x800>, <0x48800800 0x800>, <0x48801000 0x400>, @@ -3135,7 +3138,7 @@ &l4_per3 { /* 0x48800000 */ ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ segment@0 { /* 0x48800000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ From e93e4104a23acff82dc8d7e7414a0e01defecac5 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:49 +0200 Subject: [PATCH 29/53] ARM: dts: Configure simple-pm-bus for dra7 l4_cfg We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 64935a09cab4..1c50ae7b0e17 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -1,5 +1,8 @@ &l4_cfg { /* 0x4a000000 */ - compatible = "ti,dra7-l4-cfg", "simple-bus"; + compatible = "ti,dra7-l4-cfg", "simple-pm-bus"; + power-domains = <&prm_coreaon>; + clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>; + clock-names = "fck"; reg = <0x4a000000 0x800>, <0x4a000800 0x800>, <0x4a001000 0x1000>; @@ -11,7 +14,7 @@ &l4_cfg { /* 0x4a000000 */ <0x00200000 0x4a200000 0x100000>; /* segment 2 */ segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -493,7 +496,7 @@ hwspinlock: spinlock@0 { }; segment@100000 { /* 0x4a100000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ @@ -812,7 +815,7 @@ target-module@87000 { /* 0x4a187000, ap 75 74.0 */ }; segment@200000 { /* 0x4a200000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ From ecb4c5c0961bce27199a89f9fa6759b36c59a1c8 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:03:50 +0200 Subject: [PATCH 30/53] ARM: dts: Configure simple-pm-bus for dra7 l3 We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c2b5135d9763..c988f1d039cf 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -132,12 +132,14 @@ opp_high@1500000000 { * hierarchy. */ ocp: ocp { - compatible = "simple-bus"; + compatible = "simple-pm-bus"; + power-domains = <&prm_core>; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>, + <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; - ti,hwmods = "l3_main_1", "l3_main_2"; l3-noc@44000000 { compatible = "ti,dra7-l3-noc"; From 345ac6b17b18915478aa2cd7c3d87ea6e68a87c7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:28 +0200 Subject: [PATCH 31/53] ARM: dts: Configure power-domain for omap4 gfx Configure power-domain for omap4 dts gfx in preparation to probing devices with simple-pm-bus and genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 4a9f9496a867..9627d9ef8b7a 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -440,6 +440,7 @@ sgx_module: target-module@56000000 { , , ; + power-domains = <&prm_gfx>; clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; From 398c66ed22fa85d44d5ff3c12efc282c98c4da89 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:29 +0200 Subject: [PATCH 32/53] ARM: dts: Configure power-domain for omap4 dts iss Configure power-domain for omap4 dts iss in preparation to probing devices with simple-pm-bus and genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 9627d9ef8b7a..ddfbc10c851c 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -203,6 +203,7 @@ target-module@52000000 { , ; ti,sysc-delay-us = <2>; + power-domains = <&prm_cam>; clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; From fe85baacd73be867812c5bf869970eeceeac6c46 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:29 +0200 Subject: [PATCH 33/53] ARM: dts: Configure interconnect target module for omap4 dmm We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Let's also use GIC_SPI and IRQ_TYPE_LEVEL_HIGH defines while at it. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index ddfbc10c851c..cccbeb3b231d 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -262,11 +262,24 @@ target-module@4012c000 { /* No child device binding or driver in mainline */ }; - dmm@4e000000 { - compatible = "ti,omap4-dmm"; - reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; + target-module@4e000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "dmm"; + reg = <0x4e000000 0x4>, + <0x4e000010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + ranges = <0x0 0x4e000000 0x2000000>; + #size-cells = <1>; + #address-cells = <1>; + + dmm@0 { + compatible = "ti,omap4-dmm"; + reg = <0 0x800>; + interrupts = ; + }; }; emif1: emif@4c000000 { From 0600dabe34cc03909bd1c973b41fa7e0adc52966 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:29 +0200 Subject: [PATCH 34/53] ARM: dts: Configure interconnect target module for omap4 emif We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 58 +++++++++++++++++++++++++----------- 1 file changed, 40 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index cccbeb3b231d..26d460666014 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -282,28 +282,50 @@ dmm@0 { }; }; - emif1: emif@4c000000 { - compatible = "ti,emif-4d"; - reg = <0x4c000000 0x100>; - interrupts = ; + target-module@4c000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; ti,hwmods = "emif1"; - ti,no-idle-on-init; - phy-type = <1>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; + reg = <0x4c000000 0x4>; + reg-names = "rev"; + clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000000 0x1000000>; + + emif1: emif@0 { + compatible = "ti,emif-4d"; + reg = <0 0x100>; + interrupts = ; + phy-type = <1>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; }; - emif2: emif@4d000000 { - compatible = "ti,emif-4d"; - reg = <0x4d000000 0x100>; - interrupts = ; + target-module@4d000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; ti,hwmods = "emif2"; - ti,no-idle-on-init; - phy-type = <1>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; + reg = <0x4d000000 0x4>; + reg-names = "rev"; + clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4d000000 0x1000000>; + + emif2: emif@0 { + compatible = "ti,emif-4d"; + reg = <0 0x100>; + interrupts = ; + phy-type = <1>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; }; dsp: dsp { From 932ddde183185b33c92c5b7810cbdbb792cfcafd Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:30 +0200 Subject: [PATCH 35/53] ARM: dts: Configure interconnect target module for omap4 debugss We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 32 +++++++++++++++++++++----------- arch/arm/boot/dts/omap4460.dtsi | 13 ++++++------- 2 files changed, 27 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 26d460666014..675d29748480 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -58,17 +58,6 @@ cpu@1 { }; }; - /* - * Note that 4430 needs cross trigger interface (CTI) supported - * before we can configure the interrupts. This means sampling - * events are not supported for pmu. Note that 4460 does not use - * CTI, see also 4460.dtsi. - */ - pmu { - compatible = "arm,cortex-a9-pmu"; - ti,hwmods = "debugss"; - }; - gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; @@ -213,6 +202,27 @@ target-module@52000000 { /* No child device binding, driver in staging */ }; + /* + * Note that 4430 needs cross trigger interface (CTI) supported + * before we can configure the interrupts. This means sampling + * events are not supported for pmu. Note that 4460 does not use + * CTI, see also 4460.dtsi. + */ + target-module@54000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "debugss"; + power-domains = <&prm_emu>; + clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x54000000 0x1000000>; + + pmu: pmu { + compatible = "arm,cortex-a9-pmu"; + }; + }; + target-module@55082000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x55082000 0x4>, diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index 2d3e54901b6e..3d6db1db94e0 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi @@ -26,13 +26,6 @@ cpu0: cpu@0 { }; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - ti,hwmods = "debugss"; - }; - thermal-zones { #include "omap4-cpu-thermal.dtsi" }; @@ -128,4 +121,10 @@ &l4_cfg_target_0 { <0x00030000 0x00030000 0x00010000>; }; +&pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + ; +}; + /include/ "omap446x-clocks.dtsi" From e55cc3f0404c6bb22ca843a6d16fae2ca193ca09 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:30 +0200 Subject: [PATCH 36/53] ARM: dts: Configure interconnect target module for omap4 mpu We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 675d29748480..5fe4dcaa24c5 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -90,19 +90,6 @@ wakeupgen: interrupt-controller@48281000 { interrupt-parent = <&gic>; }; - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; - sram = <&ocmcram>; - }; - }; - /* * XXX: Use a flat representation of the OMAP4 interconnect. * The real OMAP interconnect network is quite complex. @@ -131,6 +118,21 @@ l4_cfg: interconnect@4a000000 { l4_per: interconnect@48000000 { }; + target-module@48210000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_mpu>; + clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48210000 0x1f0000>; + + mpu { + compatible = "ti,omap4-mpu"; + sram = <&ocmcram>; + }; + }; + l4_abe: interconnect@40100000 { }; From fbe8285d65a9e7c69fdbe6cc069d33581302c72d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:31 +0200 Subject: [PATCH 37/53] ARM: dts: Move omap4 mmio-sram out of l3 interconnect We need mmio-sram early for omap4_sram_init() for IO barrier init, and will be moving l3 interconnect to probe with simple-pm-bus that probes at module_init() time. So let's move mmio-sram out of l3 to prepare for that. Otherwise we will get the following after probing the interconnects with simple-pm-bus: omap4_sram_init:Unable to get sram pool needed to handle errata I688 Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 5fe4dcaa24c5..d0c809715444 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -58,6 +58,15 @@ cpu@1 { }; }; + /* + * Needed early by omap4_sram_init() for barrier, do not move to l3 + * interconnect as simple-pm-bus probes at module_init() time. + */ + ocmcram: sram@40304000 { + compatible = "mmio-sram"; + reg = <0x40304000 0xa000>; /* 40k */ + }; + gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; @@ -136,11 +145,6 @@ mpu { l4_abe: interconnect@40100000 { }; - ocmcram: sram@40304000 { - compatible = "mmio-sram"; - reg = <0x40304000 0xa000>; /* 40k */ - }; - target-module@50000000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x50000000 4>, From bacc83e5eef9ba4a10ed36a8b657da226ebf66db Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:31 +0200 Subject: [PATCH 38/53] ARM: dts: Move omap4 l3-noc to a separate node In preparation for probing l3 with simple-pm-bus and genpd, we must move l3 noc to a separate node. This is to prevent omap_l3_noc.c driver from claiming the whole l3 instance before simple-pm-bus has a chance to probe. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index d0c809715444..76340c37a06e 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -107,16 +107,20 @@ wakeupgen: interrupt-controller@48281000 { * hierarchy. */ ocp { - compatible = "ti,omap4-l3-noc", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0x44000000 0x1000>, - <0x44800000 0x2000>, - <0x45000000 0x1000>; - interrupts = , - ; + + l3-noc@44000000 { + compatible = "ti,omap4-l3-noc"; + reg = <0x44000000 0x1000>, + <0x44800000 0x2000>, + <0x45000000 0x1000>; + interrupts = , + ; + }; l4_wkup: interconnect@4a300000 { }; From d978b69fa7b20604bb3113b541dd74cbf2a395cf Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:31 +0200 Subject: [PATCH 39/53] ARM: dts: Configure simple-pm-bus for omap4 l4_wkup We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index e0bb60a30779..51e4fa8a3018 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -944,7 +944,10 @@ l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ }; &l4_wkup { /* 0x4a300000 */ - compatible = "ti,omap4-l4-wkup", "simple-bus"; + compatible = "ti,omap4-l4-wkup", "simple-pm-bus"; + power-domains = <&prm_wkup>; + clocks = <&l4_wkup_clkctrl OMAP4_L4_WKUP_CLKCTRL 0>; + clock-names = "fck"; reg = <0x4a300000 0x800>, <0x4a300800 0x800>, <0x4a301000 0x1000>; @@ -956,7 +959,7 @@ &l4_wkup { /* 0x4a300000 */ <0x00020000 0x4a320000 0x010000>; /* segment 2 */ segment@0 { /* 0x4a300000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -1062,7 +1065,7 @@ omap4_scm_wkup: scm@c000 { }; segment@10000 { /* 0x4a310000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ @@ -1231,7 +1234,7 @@ omap4_pmx_wkup: pinmux@40 { }; segment@20000 { /* 0x4a320000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ From 67dcfdc4a63b34f24102f70fca42477aceed578b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:32 +0200 Subject: [PATCH 40/53] ARM: dts: Configure simple-pm-bus for omap4 l4_per We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 51e4fa8a3018..fdb56a8b3d1e 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -1287,7 +1287,10 @@ target-module@6000 { /* 0x4a326000, ap 13 28.0 */ }; &l4_per { /* 0x48000000 */ - compatible = "ti,omap4-l4-per", "simple-bus"; + compatible = "ti,omap4-l4-per", "simple-pm-bus"; + power-domains = <&prm_l4per>; + clocks = <&l4_per_clkctrl OMAP4_L4_PER_CLKCTRL 0>; + clock-names = "fck"; reg = <0x48000000 0x800>, <0x48000800 0x800>, <0x48001000 0x400>, @@ -1301,7 +1304,7 @@ &l4_per { /* 0x48000000 */ <0x00200000 0x48200000 0x200000>; /* segment 1 */ segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -2440,7 +2443,7 @@ mmc5: mmc@0 { }; segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */ From 9a1d0c2837c93e6a7e31e2865ff730dcf8f26d56 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:32 +0200 Subject: [PATCH 41/53] ARM: dts: Configure simple-pm-bus for omap4 l4_cfg We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index fdb56a8b3d1e..c83849dfde24 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 &l4_cfg { /* 0x4a000000 */ - compatible = "ti,omap4-l4-cfg", "simple-bus"; + compatible = "ti,omap4-l4-cfg", "simple-pm-bus"; + power-domains = <&prm_core>; + clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>; + clock-names = "fck"; reg = <0x4a000000 0x800>, <0x4a000800 0x800>, <0x4a001000 0x1000>; @@ -16,7 +19,7 @@ &l4_cfg { /* 0x4a000000 */ <0x00300000 0x4a300000 0x080000>; /* segment 6 */ segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -347,7 +350,7 @@ mmu_dsp: mmu@0 { }; segment@80000 { /* 0x4a080000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ @@ -639,7 +642,7 @@ hwspinlock: spinlock@0 { }; segment@100000 { /* 0x4a100000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */ @@ -741,13 +744,13 @@ target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ }; segment@180000 { /* 0x4a180000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; }; segment@200000 { /* 0x4a200000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */ @@ -903,13 +906,13 @@ target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ }; segment@280000 { /* 0x4a280000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; }; l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ From e1d4a11d68b695cdf82d8da5f0c0d237652fb376 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:33 +0200 Subject: [PATCH 42/53] ARM: dts: Prepare for simple-pm-bus for omap4 l3 Let's configure omap4 l3 for power-domain and clocks in preparation for starting to use simple-pm-bus. We will flip over to using simple-pm-bus later on after dropping the legacy data for all the devices on l3 interconnect. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 76340c37a06e..fc0be942dbeb 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -108,6 +108,10 @@ wakeupgen: interrupt-controller@48281000 { */ ocp { compatible = "simple-bus"; + power-domains = <&prm_l4per>; + clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>, + <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>, + <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>; #address-cells = <1>; #size-cells = <1>; ranges; From 84864f8d2c4e413ab88ec98e538517fff2fbd9a8 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:54 +0200 Subject: [PATCH 43/53] ARM: dts: Configure interconnect target module for omap5 dmm We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index ee821d0ab364..a571a45561ad 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -246,11 +246,24 @@ ipu: ipu@55020000 { status = "disabled"; }; - dmm@4e000000 { - compatible = "ti,omap5-dmm"; - reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; + target-module@4e000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "dmm"; + reg = <0x4e000000 0x4>, + <0x4e000010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + ranges = <0x0 0x4e000000 0x2000000>; + #size-cells = <1>; + #address-cells = <1>; + + dmm@0 { + compatible = "ti,omap5-dmm"; + reg = <0 0x800>; + interrupts = ; + }; }; emif1: emif@4c000000 { From 9921f0b9d07a70079d2eabf4a4f61ac815b21bbb Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:55 +0200 Subject: [PATCH 44/53] ARM: dts: Configure interconnect target module for omap5 emif We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 62 ++++++++++++++++++++++++------------ 1 file changed, 42 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index a571a45561ad..823a59aba286 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -266,28 +266,50 @@ dmm@0 { }; }; - emif1: emif@4c000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif1"; - ti,no-idle-on-init; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4c000000 0x400>; - interrupts = ; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; + target-module@4c000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "emif1"; + reg = <0x4c000000 0x4>; + reg-names = "rev"; + clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000000 0x1000000>; + + emif1: emif@0 { + compatible = "ti,emif-4d5"; + reg = <0 0x400>; + interrupts = ; + phy-type = <2>; /* DDR PHY type: Intelli PHY */ + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; }; - emif2: emif@4d000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif2"; - ti,no-idle-on-init; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4d000000 0x400>; - interrupts = ; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; + target-module@4d000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "emif2"; + reg = <0x4d000000 0x4>; + reg-names = "rev"; + clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4d000000 0x1000000>; + + emif2: emif@0 { + compatible = "ti,emif-4d5"; + reg = <0 0x400>; + interrupts = ; + phy-type = <2>; /* DDR PHY type: Intelli PHY */ + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; }; aes1_target: target-module@4b501000 { From 0e666eb531ea74892cd3314806cbf721ba0ec04f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:55 +0200 Subject: [PATCH 45/53] ARM: dts: Configure interconnect target module for omap5 mpu We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 823a59aba286..5c7697726e18 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -125,19 +125,6 @@ wakeupgen: interrupt-controller@48281000 { interrupt-parent = <&gic>; }; - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; - sram = <&ocmcram>; - }; - }; - /* * XXX: Use a flat representation of the OMAP3 interconnect. * The real OMAP interconnect network is quite complex. @@ -167,6 +154,21 @@ l4_cfg: interconnect@4a000000 { l4_per: interconnect@48000000 { }; + target-module@48210000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_mpu>; + clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48210000 0x1f0000>; + + mpu { + compatible = "ti,omap4-mpu"; + sram = <&ocmcram>; + }; + }; + l4_abe: interconnect@40100000 { }; From 5f89cdc1034c16a1d130d6c9e1a43a55e2c42f03 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:56 +0200 Subject: [PATCH 46/53] ARM: dts: Configure interconnect target module for omap5 gpmc We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 49 ++++++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 5c7697726e18..5beab4964d5b 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -177,23 +177,40 @@ ocmcram: sram@40300000 { reg = <0x40300000 0x20000>; /* 128k */ }; - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = ; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - clocks = <&l3_iclk_div>; + target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000000 4>, + <0x50000010 4>, + <0x50000014 4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + ti,no-idle-on-init; + clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>; clock-names = "fck"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ + <0x00000000 0x00000000 0x40000000>; /* data */ + + gpmc: gpmc@50000000 { + compatible = "ti,omap4430-gpmc"; + reg = <0x50000000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + interrupts = ; + dmas = <&sdma 4>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + clock-names = "fck"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; }; target-module@55082000 { From 41ccb6623711da26c5e6b34f3e05e271857bebb4 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:56 +0200 Subject: [PATCH 47/53] ARM: dts: Configure interconnect target module for omap5 sata We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Note that the old sysc register offset is wrong, the real offset is at 0x1100 as listed in TRM for SATA_SYSCONFIG register. Looks like we've been happily using sata on the bootloader configured sysconfig register and nobody noticed. Also the old register range for SATAMAC_wrapper registers is wrong at 7 while it should be 8. But that too seems harmless. There is also an L3 parent interconnect range that we don't seem to be using. That can be added as needed later on. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 28 +++++++++++++++++++++++++--- arch/arm/boot/dts/omap5.dtsi | 12 ------------ 2 files changed, 25 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 887b3359dd5a..b4b6adea4f45 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -691,11 +691,33 @@ target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ }; target-module@40000 { /* 0x4a140000, ap 101 16.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x400fc 4>, + <0x41100 4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + , + ; + power-domains = <&prm_l3init>; + clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 0>; + clock-names = "fck"; #size-cells = <1>; + #address-cells = <1>; ranges = <0x0 0x40000 0x10000>; + + sata: sata@0 { + compatible = "snps,dwc-ahci"; + reg = <0 0x1100>, <0x1100 0x8>; + interrupts = ; + phys = <&sata_phy>; + phy-names = "sata-phy"; + clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; + ports-implemented = <0x1>; + }; }; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 5beab4964d5b..f4132dfae814 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -428,18 +428,6 @@ bandgap: bandgap@4a0021e0 { #thermal-sensor-cells = <1>; }; - /* OCP2SCP3 */ - sata: sata@4a141100 { - compatible = "snps,dwc-ahci"; - reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = ; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - ti,hwmods = "sata"; - ports-implemented = <0x1>; - }; - target-module@56000000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x5600fe00 0x4>, From a571cc394194543cc039ad92545e059a840a8e12 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:57 +0200 Subject: [PATCH 48/53] ARM: dts: Move omap5 mmio-sram out of l3 interconnect We need mmio-sram early for omap4_sram_init() for IO barrier init, and will be moving l3 interconnect to probe with simple-pm-bus that probes at module_init() time. So let's move mmio-sram out of l3 to prepare for that. Otherwise we will get the following after probing the interconnects with simple-pm-bus: omap4_sram_init:Unable to get sram pool needed to handle errata I688 Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index f4132dfae814..42b525510b52 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -106,6 +106,15 @@ pmu { ; }; + /* + * Needed early by omap4_sram_init() for barrier, do not move to l3 + * interconnect as simple-pm-bus probes at module_init() time. + */ + ocmcram: sram@40300000 { + compatible = "mmio-sram"; + reg = <0 0x40300000 0 0x20000>; /* 128k */ + }; + gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; @@ -172,11 +181,6 @@ mpu { l4_abe: interconnect@40100000 { }; - ocmcram: sram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x20000>; /* 128k */ - }; - target-module@50000000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x50000000 4>, From d1d16959fea79c0dc6290cef732d5d0a821e14df Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:57 +0200 Subject: [PATCH 49/53] ARM: dts: Move omap5 l3-noc to a separate node In preparation for probing l3 with simple-pm-bus and genpd, we must move l3 noc to a separate node. This is to prevent omap_l3_noc.c driver from claiming the whole l3 instance before simple-pm-bus has a chance to probe. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 42b525510b52..dcc4077c2188 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -142,17 +142,21 @@ wakeupgen: interrupt-controller@48281000 { * hierarchy. */ ocp { - compatible = "ti,omap5-l3-noc", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xc0000000>; dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0 0x44000000 0 0x2000>, - <0 0x44800000 0 0x3000>, - <0 0x45000000 0 0x4000>; - interrupts = , - ; + + l3-noc@44000000 { + compatible = "ti,omap5-l3-noc"; + reg = <0x44000000 0x2000>, + <0x44800000 0x3000>, + <0x45000000 0x4000>; + interrupts = , + ; + }; l4_wkup: interconnect@4ae00000 { }; From 689919e6e2b9d27027625b352351f4597e3c25dc Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:57 +0200 Subject: [PATCH 50/53] ARM: dts: Configure simple-pm-bus for omap5 l4_wkup We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index b4b6adea4f45..e3de9a0a7ca9 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -2177,7 +2177,10 @@ segment@200000 { /* 0x48200000 */ }; &l4_wkup { /* 0x4ae00000 */ - compatible = "ti,omap5-l4-wkup", "simple-bus"; + compatible = "ti,omap5-l4-wkup", "simple-pm-bus"; + power-domains = <&prm_wkupaon>; + clocks = <&wkupaon_clkctrl OMAP5_L4_WKUP_CLKCTRL 0>; + clock-names = "fck"; reg = <0x4ae00000 0x800>, <0x4ae00800 0x800>, <0x4ae01000 0x1000>; @@ -2189,7 +2192,7 @@ &l4_wkup { /* 0x4ae00000 */ <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ segment@0 { /* 0x4ae00000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -2318,7 +2321,7 @@ scm_wkup_pad_conf_clocks: clocks@0 { }; segment@10000 { /* 0x4ae10000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ @@ -2445,7 +2448,7 @@ keypad: keypad@0 { }; segment@20000 { /* 0x4ae20000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ From 6fe4ff901607fbab2b93b7e8f9404bfcb93f685e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:58 +0200 Subject: [PATCH 51/53] ARM: dts: Configure simple-pm-bus for omap5 l4_per We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index e3de9a0a7ca9..b7a0ce367559 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -947,7 +947,10 @@ segment@300000 { /* 0x4a300000 */ }; &l4_per { /* 0x48000000 */ - compatible = "ti,omap5-l4-per", "simple-bus"; + compatible = "ti,omap5-l4-per", "simple-pm-bus"; + power-domains = <&prm_core>; + clocks = <&l4per_clkctrl OMAP5_L4_PER_CLKCTRL 0>; + clock-names = "fck"; reg = <0x48000000 0x800>, <0x48000800 0x800>, <0x48001000 0x400>, @@ -961,7 +964,7 @@ &l4_per { /* 0x48000000 */ <0x00200000 0x48200000 0x200000>; /* segment 1 */ segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -2170,7 +2173,7 @@ mmc5: mmc@0 { }; segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; }; From abd1d31d82920726c3cdd46fb016d93ada919639 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:58 +0200 Subject: [PATCH 52/53] ARM: dts: Configure simple-pm-bus for omap5 l4_cfg We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index b7a0ce367559..b148b289e830 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -1,5 +1,8 @@ &l4_cfg { /* 0x4a000000 */ - compatible = "ti,omap5-l4-cfg", "simple-bus"; + compatible = "ti,omap5-l4-cfg", "simple-pm-bus"; + power-domains = <&prm_core>; + clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>; + clock-names = "fck"; reg = <0x4a000000 0x800>, <0x4a000800 0x800>, <0x4a001000 0x1000>; @@ -15,7 +18,7 @@ &l4_cfg { /* 0x4a000000 */ <0x00300000 0x4a300000 0x080000>; /* segment 6 */ segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -391,7 +394,7 @@ target-module@75000 { /* 0x4a075000, ap 81 32.0 */ }; segment@80000 { /* 0x4a080000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ @@ -654,7 +657,7 @@ hwspinlock: spinlock@0 { }; segment@100000 { /* 0x4a100000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ @@ -722,13 +725,13 @@ sata: sata@0 { }; segment@180000 { /* 0x4a180000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; }; segment@200000 { /* 0x4a200000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ @@ -934,13 +937,13 @@ target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ }; segment@280000 { /* 0x4a280000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; }; segment@300000 { /* 0x4a300000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; }; From e180887946137ccb4b6aeb172872cb1368cfe219 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Mar 2021 14:04:58 +0200 Subject: [PATCH 53/53] ARM: dts: Configure simple-pm-bus for omap5 l3 We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index dcc4077c2188..681fee379b88 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -142,7 +142,11 @@ wakeupgen: interrupt-controller@48281000 { * hierarchy. */ ocp { - compatible = "simple-bus"; + compatible = "simple-pm-bus"; + power-domains = <&prm_core>; + clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>, + <&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>, + <&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xc0000000>;