From 626c0a0ee921a3ea001e4b4f35db89186649f822 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 6 Jun 2017 13:59:29 +0800 Subject: [PATCH 01/11] ARM: dts: sun6i: a31: Use new sun6i-a31-r-intc compatible for NMI/R_INTC We introduced a new compatible for the NMI or R_INTC interrupt controller. This new compatible has the register region aligned to the boundary listed in the SoC's memory map. This patch converts the NMI/R_INTC node to using the new compatible, and fixes up the register region and device node name. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index aebc3f9dc7b6..b147cb0dc14b 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -1155,11 +1155,11 @@ rtc: rtc@01f00000 { ; }; - nmi_intc: interrupt-controller@01f00c0c { - compatible = "allwinner,sun6i-a31-sc-nmi"; + nmi_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun6i-a31-r-intc"; interrupt-controller; #interrupt-cells = <2>; - reg = <0x01f00c0c 0x38>; + reg = <0x01f00c00 0x400>; interrupts = ; }; From a180791004fa28b2727a01df114941cbbf2a06d5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 6 Jun 2017 13:59:30 +0800 Subject: [PATCH 02/11] ARM: dts: sun8i: a23/a33: Use new sun6i-a31-r-intc compatible for NMI/R_INTC We introduced a new compatible for the NMI or R_INTC interrupt controller. This new compatible has the register region aligned to the boundary listed in the SoC's memory map. This patch converts the NMI/R_INTC node to using the new compatible, and fixes up the register region and device node name. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index a8b978d0f35b..ea50dda75adc 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -519,11 +519,11 @@ rtc: rtc@01f00000 { #clock-cells = <1>; }; - nmi_intc: interrupt-controller@01f00c0c { - compatible = "allwinner,sun6i-a31-sc-nmi"; + nmi_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun6i-a31-r-intc"; interrupt-controller; #interrupt-cells = <2>; - reg = <0x01f00c0c 0x38>; + reg = <0x01f00c00 0x400>; interrupts = ; }; From 23ee53b1e262dcb19901f15a53428ead6a2bf137 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 6 Jun 2017 13:59:31 +0800 Subject: [PATCH 03/11] ARM: dts: sun8i: a83t: Add device node for R_INTC interrupt controller The R_INTC interrupt controller handles the NMI interrupt pin for the SoC. While there is no documentation or code from the vendor for this device on the A83T, existing mainline kernel drivers and bindings show this to be similar to the old Allwinner interrupt controller found on the A10 SoC, but with only the NMI interrupt wired. Register poking experiments confirm this. The device seems to be the same across all recent Allwinner SoCs, apart from the A20 and A80, which have a separate set of registers to handle the NMI interrupt. We already have a set of bindings supporting this on the A31. Add a device node for it, with an SoC specific compatible. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 19a8f4fcfab5..beed05e10a3b 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -281,6 +281,15 @@ gic: interrupt-controller@1c81000 { interrupts = ; }; + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun8i-a83t-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c00 0x400>; + interrupts = ; + }; + r_ccu: clock@1f01400 { compatible = "allwinner,sun8i-a83t-r-ccu"; reg = <0x01f01400 0x400>; From 9b807037d7148a97286392c5ff53148d2708d584 Mon Sep 17 00:00:00 2001 From: Alexander Syring Date: Wed, 5 Jul 2017 10:30:20 +0200 Subject: [PATCH 04/11] ARM: dts: sun7i: enable battery power supply subnode on cubietruck The Cubietruck has an AXP209 PMIC with battery connector. This enables the battery power supply subnode. Signed-off-by: Alexander Syring Signed-off-by: Maxime Ripard [wens@csie.org: Correct subject prefix order] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index bb510187602c..852a0aa24dce 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -271,6 +271,10 @@ &ac_power_supply { status = "okay"; }; +&battery_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; From 77c6511a012970b87a8525607d7bd8573e304f9b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 11 Apr 2017 14:49:56 +0200 Subject: [PATCH 05/11] ARM: dts: sun8i: Add BananaPI M2-Magic DTS The Bananapi M2-Magic is a board with an A33, a USB host and USB OTG connectors, and 8GB eMMC, an AP6212 WiFi/Bluetooth chip and connectors for DSI, CSI and GPIOs. Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard [wens@csie.org: Correct subject prefix case] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 321 +++++++++++++++++++ 2 files changed, 322 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4b17f35dc9a7..e0d77ab79f5f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -918,6 +918,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-pc-plus.dtb \ sun8i-h3-orangepi-plus.dtb \ sun8i-h3-orangepi-plus2e.dtb \ + sun8i-r16-bananapi-m2m.dtb \ sun8i-r16-parrot.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts new file mode 100644 index 000000000000..eaf09666720d --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2017 Free Electrons + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" + +#include + +/ { + model = "BananaPi M2 Magic"; + compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "bpi-m2m:blue:usr"; + gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; + }; + + green { + label = "bpi-m2m:green:usr"; + gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; + }; + + red { + label = "bpi-m2m:red:power"; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ + }; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&cpu0_opp_table { + opp@1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; +}; + +&dai { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +/* This is the i2c bus exposed on the DSI connector for the touch panel */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "disabled"; +}; + +/* This is the i2c bus exposed on the GPIO header */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "disabled"; +}; + +/* This is the i2c bus exposed on the CSI connector to control the sensor */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp223.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +/* + * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same + * time, with the two being in sync. Since this is not really + * supported right now, just use the two as always on, and we will fix + * it later. + */ +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi0"; +}; + +®_dldo2 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi1"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&sound { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; From 6c75582a85fe30f458ea07cd36eb3bbeb6c82140 Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Sun, 23 Jul 2017 16:49:49 +0200 Subject: [PATCH 06/11] ARM: dts: sun8i: h3: Enable USB OTG on the Beelink X2 This STB has a type A socket which acts as OTG. Signed-off-by: Marcus Cooper Signed-off-by: Maxime Ripard Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 24 +++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index e7fae65eb5d3..10da56e86ab8 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -100,6 +100,10 @@ spdif_out: spdif-out { }; }; +&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -147,10 +151,19 @@ &mmc2 { status = "okay"; }; +&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + &spdif { pinctrl-names = "default"; pinctrl-0 = <&spdif_tx_pins_a>; @@ -163,7 +176,14 @@ &uart0 { status = "okay"; }; -&usbphy { - /* USB VBUS is on as long as VCC-IO is on */ +&usb_otg { + dr_mode = "otg"; status = "okay"; }; + +&usbphy { + /* USB VBUS is always on except for the OTG port */ + status = "okay"; + usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */ + usb0_vbus-supply = <®_usb0_vbus>; +}; From ddb56254ae52acff7bd7fbd8f963e79bffc324d4 Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Sun, 23 Jul 2017 16:49:50 +0200 Subject: [PATCH 07/11] ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2 The dwmac-sun8i hardware is present on the Beelink X2. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Marcus Cooper Signed-off-by: Maxime Ripard [wens@csie.org: Fixed typo in commit subject] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index 10da56e86ab8..546837ccd8af 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -53,7 +53,7 @@ / { aliases { serial0 = &uart0; - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &sdiowifi; }; @@ -108,6 +108,13 @@ &ehci1 { status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; From 1e72097f1e6b7fb839e7aec6c700e3b19b95fbf9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 24 Jul 2017 21:59:02 +0800 Subject: [PATCH 08/11] ARM: dts: sun8i: a83t: Add MMC controller device nodes The A83T has 3 MMC controllers. The third one is a bit special, as it supports a wider 8-bit bus, and a "new timing mode". Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 59 +++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index beed05e10a3b..21ab668abfac 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -182,6 +182,65 @@ dma: dma-controller@1c02000 { #dma-cells = <1>; }; + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-a83t-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun8i-a83t-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun8i-a83t-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-a83t-ccu"; reg = <0x01c20000 0x400>; From 3ea38e38d31ba298536344cec699495d18e08920 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 24 Jul 2017 21:59:03 +0800 Subject: [PATCH 09/11] ARM: dts: sun8i: a83t: Add pingroup for 8-bit eMMC on mmc2 mmc2 can support 8-bit eMMC chips, with a dedicated reset line. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 21ab668abfac..d9b4372dbdf3 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -271,6 +271,15 @@ mmc0_pins: mmc0-pins { bias-pull-up; }; + mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { + pins = "PC5", "PC6", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", + "PC14", "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + spdif_tx_pin: spdif-tx-pin { pins = "PE18"; function = "spdif"; From 06b234ac4eebcea7ad60fdacefec33e15a76439a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 24 Jul 2017 21:59:04 +0800 Subject: [PATCH 10/11] ARM: dts: sun8i: a83t: cubietruck-plus: Enable micro-SD card and eMMC Now that we support the MMC controllers on the A83T SoC, we can enable them on some boards. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- .../boot/dts/sun8i-a83t-cubietruck-plus.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index cff33454fc24..163ddf8868b5 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -83,6 +83,13 @@ green { }; }; + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "On-board SPDIF"; @@ -102,6 +109,26 @@ spdif_out: spdif-out { }; }; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + &spdif { status = "okay"; }; From 581ae76e96c6ab3bf942da7c4822ce9fa2074a01 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 24 Jul 2017 21:59:05 +0800 Subject: [PATCH 11/11] ARM: dts: sun8i: a83t: h8homlet: Enable micro-SD card and onboard eMMC The H8 homlet has a micro-SD card slot connected to mmc0, and onboard eMMC from FORESEE, connected to mmc2. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index aecdeeb368ed..7afbaa4eea8d 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "sun8i-a83t.dtsi" +#include "sunxi-common-regulators.dtsi" / { model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; @@ -57,6 +58,26 @@ chosen { }; }; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v0>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + bus-width = <4>; + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + vmmc-supply = <®_vcc3v0>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>;