diff --git a/.mailmap b/.mailmap index 34acd34bbf9b..99dba08041fa 100644 --- a/.mailmap +++ b/.mailmap @@ -19,6 +19,7 @@ Abhinav Kumar Ahmad Masri Adam Oldham Adam Radford +Aditya Garg Adriana Reus Adrian Bunk Ajay Kaher @@ -207,6 +208,7 @@ Claudiu Beznea Colin Ian King Corey Minyard Damian Hobson-Garcia +Dan Carpenter Dan Carpenter Dan Williams Daniel Borkmann @@ -495,6 +497,7 @@ Leon Romanovsky Leon Romanovsky Leon Romanovsky Leo Yan +Liam R. Howlett Liam Mark Linas Vepstas Linus Lüssing @@ -505,6 +508,8 @@ Linus Walleij Linus Walleij Linus Walleij +Li Wang +Li Wang Li Yang Li Yang Lior David @@ -579,6 +584,8 @@ Mayuresh Janorkar Md Sadre Alam Miaoqing Pan Michael Buesch +Michal Grzeschik +Michal Grzeschik Michael Riesch Michal Simek Michel Dänzer @@ -677,6 +684,7 @@ Peter A Jonsson Peter Hilber Peter Oruba Peter Oruba +Peter Rosin Pierre-Louis Bossart Pratyush Anand Pratyush Yadav @@ -687,6 +695,7 @@ Punit Agrawal Puranjay Mohan Qais Yousef Qais Yousef +Qi Zheng Quentin Monnet Quentin Monnet Quentin Perret @@ -850,6 +859,7 @@ Tobias Klauser Tobias Klauser Tobias Klauser Todor Tomov +Tomasz Jeznach Tony Luck Trilok Soni TripleX Chung diff --git a/Documentation/.renames.txt b/Documentation/.renames.txt index 43d44753ab93..aa7e5aa4a81b 100644 --- a/Documentation/.renames.txt +++ b/Documentation/.renames.txt @@ -786,6 +786,7 @@ networking/altera_tse networking/device_drivers/ethernet/altera/altera_tse networking/bpf_flow_dissector bpf/prog_flow_dissector networking/cxacru networking/device_drivers/atm/cxacru networking/defza networking/device_drivers/fddi/defza +networking/device_drivers/3com/3c509 networking/device_drivers/ethernet/3com/3c509 networking/device_drivers/3com/vortex networking/device_drivers/ethernet/3com/vortex networking/device_drivers/amazon/ena networking/device_drivers/ethernet/amazon/ena networking/device_drivers/aquantia/atlantic networking/device_drivers/ethernet/aquantia/atlantic diff --git a/Documentation/ABI/obsolete/sysfs-driver-ivpu b/Documentation/ABI/obsolete/sysfs-driver-ivpu new file mode 100644 index 000000000000..b906e7149729 --- /dev/null +++ b/Documentation/ABI/obsolete/sysfs-driver-ivpu @@ -0,0 +1,30 @@ +What: /sys/bus/pci/drivers/intel_vpu/.../sched_mode +Date: October 2024 +KernelVersion: 6.12 +Contact: dri-devel@lists.freedesktop.org +Description: Current NPU scheduling mode. Returns one of the following strings: + - "HW" - Hardware Scheduler mode + - "OS" - Operating System Scheduler mode + Read-only. + Deprecated since the "OS" scheduling mode is not usable + and will be removed from future versions of the driver. + Will be removed in 2027 + +What: /sys/bus/pci/drivers/intel_vpu/.../npu_max_frequency_mhz +Date: April 2025 +KernelVersion: 6.15 +Contact: dri-devel@lists.freedesktop.org +Description: Legacy alias for /sys/bus/pci/drivers/intel_vpu/.../freq/hw_max_freq. + Shows maximum frequency in MHz of the NPU's data processing unit. + Read-only. + Will be removed in 2027 + +What: /sys/bus/pci/drivers/intel_vpu/.../npu_current_frequency_mhz +Date: April 2025 +KernelVersion: 6.15 +Contact: dri-devel@lists.freedesktop.org +Description: Legacy alias for /sys/bus/pci/drivers/intel_vpu/.../freq/current_freq. + Shows current frequency in MHz of the NPU's data processing unit. + The value is read only when the device is active; otherwise it returns 0. + Read-only. + Will be removed in 2027 diff --git a/Documentation/ABI/obsolete/sysfs-selinux-user b/Documentation/ABI/removed/sysfs-selinux-user similarity index 100% rename from Documentation/ABI/obsolete/sysfs-selinux-user rename to Documentation/ABI/removed/sysfs-selinux-user diff --git a/Documentation/ABI/testing/sysfs-driver-ivpu b/Documentation/ABI/testing/sysfs-driver-ivpu new file mode 100644 index 000000000000..91685774edfc --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-ivpu @@ -0,0 +1,65 @@ +What: /sys/bus/pci/drivers/intel_vpu/.../npu_busy_time_us +Date: May 2024 +KernelVersion: 6.11 +Contact: dri-devel@lists.freedesktop.org +Description: Time in microseconds that the device spent executing jobs. The time is + counted when and only when there are jobs submitted to firmware. This time + can be used to measure the utilization of NPU, either by calculating the + difference between two timepoints or monitoring utilization percentage by + reading periodically. Recommended read period is 1 second to avoid impact + on job submission performance. Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../npu_memory_utilization +Date: Jan 2025 +KernelVersion: 6.15 +Contact: dri-devel@lists.freedesktop.org +Description: Current NPU memory utilization in bytes. Reports the total size of all + resident buffer objects allocated for NPU use. Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/hw_min_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Minimum frequency in MHz supported by the NPU hardware. This is a + hardware capability and cannot be changed. Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/hw_efficient_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Most efficient operating frequency in MHz for the NPU. This represents + the frequency at which the NPU operates most efficiently in terms of power + and performance. Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/hw_max_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Maximum frequency in MHz supported by the NPU hardware. This is a + hardware capability and cannot be changed. Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/current_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Current operating frequency in MHz of the NPU. The value is valid only + when the device is active; returns 0 when idle. The actual frequency may + be lower than the requested range due to power or thermal constraints. + Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/set_min_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Configured minimum operating frequency in MHz (50XX devices and newer). + Values written are clamped to hardware limits (hw_min_freq to hw_max_freq). + If set_min_freq exceeds set_max_freq, the driver clamps set_min_freq to + set_max_freq when selecting the operating frequency. Read-write. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/set_max_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Configured maximum operating frequency in MHz (50XX devices and newer). + Values written are clamped to hardware limits (hw_min_freq to hw_max_freq). + Read-write. diff --git a/Documentation/accel/amdxdna/amdnpu.rst b/Documentation/accel/amdxdna/amdnpu.rst index 42e54904f9a8..064973bf4893 100644 --- a/Documentation/accel/amdxdna/amdnpu.rst +++ b/Documentation/accel/amdxdna/amdnpu.rst @@ -270,6 +270,31 @@ MERT can report various kinds of telemetry information like the following: * Deep Sleep counter * etc. +.. _amdxdna-usage-stats: + +Amdxdna DRM client usage stats implementation +============================================= + +The amdxdna driver implements the DRM client usage stats specification as +documented in :ref:`drm-client-usage-stats`. + +Example of the output showing the implemented key value pairs: + +:: + + pos: 0 + flags: 0100002 + mnt_id: 29 + ino: 939 + drm-driver: amdxdna_accel_driver + drm-client-id: 3219 + drm-pdev: 0000:c5:00.1 + amdxdna_accel_driver-heap-alloc: 60 KiB + amdxdna_accel_driver-internal-alloc: 67588 KiB + amdxdna_accel_driver-external-alloc: 0 + drm-total-memory: 67632 KiB + drm-shared-memory: 0 + References ========== diff --git a/Documentation/admin-guide/cgroup-v1/memcg_test.rst b/Documentation/admin-guide/cgroup-v1/memcg_test.rst index 9f8e27355cba..7c7cd457cf69 100644 --- a/Documentation/admin-guide/cgroup-v1/memcg_test.rst +++ b/Documentation/admin-guide/cgroup-v1/memcg_test.rst @@ -47,21 +47,19 @@ Please note that implementation details can be changed. Called when swp_entry's refcnt goes down to 0. A charge against swap disappears. -3. charge-commit-cancel +3. charge-commit ======================= Memcg pages are charged in two steps: - mem_cgroup_try_charge() - - mem_cgroup_commit_charge() or mem_cgroup_cancel_charge() + - commit_charge() At try_charge(), there are no flags to say "this page is charged". at this point, usage += PAGE_SIZE. At commit(), the page is associated with the memcg. - At cancel(), simply usage -= PAGE_SIZE. - Under below explanation, we assume CONFIG_SWAP=y. 4. Anonymous diff --git a/Documentation/admin-guide/cgroup-v2.rst b/Documentation/admin-guide/cgroup-v2.rst index 8ad0b2781317..6efd0095ed99 100644 --- a/Documentation/admin-guide/cgroup-v2.rst +++ b/Documentation/admin-guide/cgroup-v2.rst @@ -220,7 +220,7 @@ cgroup v2 currently supports the following mount options. memory_hugetlb_accounting Count HugeTLB memory usage towards the cgroup's overall memory usage for the memory controller (for the purpose of - statistics reporting and memory protetion). This is a new + statistics reporting and memory protection). This is a new behavior that could regress existing setups, so it must be explicitly opted in with this mount option. diff --git a/Documentation/admin-guide/laptops/uniwill-laptop.rst b/Documentation/admin-guide/laptops/uniwill-laptop.rst index 561334865feb..1f3ca84c7d88 100644 --- a/Documentation/admin-guide/laptops/uniwill-laptop.rst +++ b/Documentation/admin-guide/laptops/uniwill-laptop.rst @@ -43,6 +43,11 @@ Support for changing the platform performance mode is currently not implemented. Battery Charging Control ------------------------ +.. warning:: Some devices do not properly implement the charging threshold interface. Forcing + the driver to enable access to said interface on such devices might damage the + battery [1]_. Because of this the driver will not enable said feature even when + using the ``force`` module parameter. + The ``uniwill-laptop`` driver supports controlling the battery charge limit. This happens over the standard ``charge_control_end_threshold`` power supply sysfs attribute. All values between 1 and 100 percent are supported. @@ -70,3 +75,8 @@ The ``uniwill-laptop`` driver allows to set the configurable TGP for devices wit allow it. See Documentation/ABI/testing/sysfs-driver-uniwill-laptop for details. + +References +========== + +.. [1] https://www.reddit.com/r/XMG_gg/comments/ld9yyf/battery_limit_hidden_function_discovered_on/ diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index f8e7050fc762..a95e2ebce005 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -358,9 +358,9 @@ Dynamic energy performance profile The amd-pstate driver supports dynamically selecting the energy performance profile based on whether the machine is running on AC or DC power. -Whether this behavior is enabled by default depends on the kernel -config option `CONFIG_X86_AMD_PSTATE_DYNAMIC_EPP`. This behavior can also be overridden -at runtime by the sysfs file ``/sys/devices/system/cpu/cpufreq/policyX/dynamic_epp``. +Whether this behavior is enabled by default depends on the kernel command line option +``amd_dynamic_epp`` is set. This behavior can also be overridden +at runtime by the sysfs file ``/sys/devices/system/cpu/amd_pstate/dynamic_epp``. When set to enabled, the driver will select a different energy performance profile when the machine is running on battery or AC power. The driver will @@ -485,9 +485,8 @@ kernel parameter ``amd_prefcore=disable``. ``amd_dynamic_epp`` When AMD pstate is in auto mode, dynamic EPP will control whether the kernel -autonomously changes the EPP mode. The default is configured by -``CONFIG_X86_AMD_PSTATE_DYNAMIC_EPP`` but can be explicitly enabled with -``amd_dynamic_epp=enable`` or disabled with ``amd_dynamic_epp=disable``. +autonomously changes the EPP mode. The default is disabled. It can be enabled +with the kernel parameter ``amd_dynamic_epp=enable``. User Space Interface in ``sysfs`` - General =========================================== diff --git a/Documentation/admin-guide/pm/intel_pstate.rst b/Documentation/admin-guide/pm/intel_pstate.rst index fde967b0c2e0..25fe5d88fea6 100644 --- a/Documentation/admin-guide/pm/intel_pstate.rst +++ b/Documentation/admin-guide/pm/intel_pstate.rst @@ -355,11 +355,12 @@ HyperThreading (HT) in the context of Intel processors, is enabled on at least one core, ``intel_pstate`` assigns performance-based priorities to CPUs. Namely, the priority of a given CPU reflects its highest HWP performance level which causes the CPU scheduler to generally prefer more performant CPUs, so the less -performant CPUs are used when the other ones are fully loaded. However, SMT -siblings (that is, logical CPUs sharing one physical core) are treated in a -special way such that if one of them is in use, the effective priority of the -other ones is lowered below the priorities of the CPUs located in the other -physical cores. +performant CPUs are used when the other ones are fully loaded. SMT siblings +(that is, logical CPUs sharing one physical core) are given the same priority. +The scheduler can pull tasks from lower-priority cores and place them on any +sibling. Since the scheduler spreads tasks among physical cores, tasks will be +placed on the SMT siblings of physical cores only after all physical cores are +busy. This approach maximizes performance in the majority of cases, but unfortunately it also leads to excessive energy usage in some important scenarios, like video diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/cmodx.rst index 40ba53bed5df..cbfa812a11b4 100644 --- a/Documentation/arch/riscv/cmodx.rst +++ b/Documentation/arch/riscv/cmodx.rst @@ -21,13 +21,13 @@ call at each patchable function entry, and patches it dynamically at runtime to enable or disable the redirection. In the case of RISC-V, 2 instructions, AUIPC + JALR, are required to compose a function call. However, it is impossible to patch 2 instructions and expect that a concurrent read-side executes them -without a race condition. This series makes atmoic code patching possible in +without a race condition. This series makes atomic code patching possible in RISC-V ftrace. Kernel preemption makes things even worse as it allows the old state to persist across the patching process with stop_machine(). In order to get rid of stop_machine() and run dynamic ftrace with full kernel preemption, we partially initialize each patchable function entry at boot-time, -setting the first instruction to AUIPC, and the second to NOP. Now, atmoic +setting the first instruction to AUIPC, and the second to NOP. Now, atomic patching is possible because the kernel only has to update one instruction. According to Ziccif, as long as an instruction is naturally aligned, the ISA guarantee an atomic update. @@ -36,8 +36,8 @@ By fixing down the first instruction, AUIPC, the range of the ftrace trampoline is limited to +-2K from the predetermined target, ftrace_caller, due to the lack of immediate encoding space in RISC-V. To address the issue, we introduce CALL_OPS, where an 8B naturally align metadata is added in front of each -pacthable function. The metadata is resolved at the first trampoline, then the -execution can be derect to another custom trampoline. +patchable function. The metadata is resolved at the first trampoline, then the +execution can be directed to another custom trampoline. CMODX in the User Space ----------------------- diff --git a/Documentation/arch/riscv/zicfilp.rst b/Documentation/arch/riscv/zicfilp.rst index ab7d8e62ddaf..12b35969d17a 100644 --- a/Documentation/arch/riscv/zicfilp.rst +++ b/Documentation/arch/riscv/zicfilp.rst @@ -78,7 +78,7 @@ the program. Per-task indirect branch tracking state can be monitored and controlled via the :c:macro:`PR_GET_CFI` and :c:macro:`PR_SET_CFI` -``prctl()` arguments (respectively), by supplying +``prctl()`` arguments (respectively), by supplying :c:macro:`PR_CFI_BRANCH_LANDING_PADS` as the second argument. These are architecture-agnostic, and will return -EINVAL if the underlying functionality is not supported. diff --git a/Documentation/crypto/krb5.rst b/Documentation/crypto/krb5.rst index beffa0133446..f62e07ac6811 100644 --- a/Documentation/crypto/krb5.rst +++ b/Documentation/crypto/krb5.rst @@ -158,13 +158,22 @@ returned. When a message has been received, the location and size of the data with the message can be determined by calling:: - void crypto_krb5_where_is_the_data(const struct krb5_enctype *krb5, - enum krb5_crypto_mode mode, - size_t *_offset, size_t *_len); + int crypto_krb5_where_is_the_data(const struct krb5_enctype *krb5, + enum krb5_crypto_mode mode, + size_t *_offset, size_t *_len); The caller provides the offset and length of the message to the function, which then alters those values to indicate the region containing the data (plus any -padding). It is up to the caller to determine how much padding there is. +padding). It is up to the caller to determine how much padding there is. The +function returns an error if the length is too small or if the mode is +unsupported. An additional function:: + + int crypto_krb5_check_data_len(const struct krb5_enctype *krb5, + enum krb5_crypto_mode mode, + size_t len, size_t min_content); + +is provided to just do a basic check that the decrypted/verified message would +have a sufficient minimum payload. Preparation Functions --------------------- diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml index 9a6e9b25d14a..7cfe92a8bcd7 100644 --- a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml @@ -36,18 +36,56 @@ properties: properties: port@0: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Primary MIPI DSI port-1 for MIPI input or LVDS port-1 for LVDS input or DPI input. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + port@1: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Additional MIPI port-2 for MIPI input or LVDS port-2 for LVDS input. Used in combination with primary port-1 to drive higher resolution displays + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + port@2: $ref: /schemas/graph.yaml#/properties/port description: @@ -99,6 +137,7 @@ examples: reg = <0>; endpoint { + data-lanes = <1 2 3 4>; remote-endpoint = <&dsi0_out>; }; }; diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml index 7586d681bcc6..0363201f0e61 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -34,6 +34,7 @@ properties: - items: - enum: - doestek,dtc34lm85am # For the Doestek DTC34LM85AM Flat Panel Display (FPD) Transmitter + - idt,v103 # For the Triple 10-BIT LVDS Transmitter - onnn,fin3385 # OnSemi FIN3385 - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer diff --git a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml index e6808419f625..7636c24906ba 100644 --- a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml +++ b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml @@ -30,6 +30,7 @@ properties: - algoltek,ag6311 - asl-tek,cs5263 - dumb-vga-dac + - mstar,tsumu88adt3-lf-1 - parade,ps185hdm - radxa,ra620 - realtek,rtd2171 diff --git a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml index 3820dd7e11af..4d34a92192bf 100644 --- a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml @@ -10,11 +10,14 @@ maintainers: - Joseph Guo description: - Waveshare bridge board is part of Waveshare panel which converts DSI to DPI. + Waveshare bridge board is part of Waveshare panel which converts DSI to DPI + or LVDS. properties: compatible: - const: waveshare,dsi2dpi + enum: + - waveshare,dsi2dpi + - waveshare,dsi2lvds reg: maxItems: 1 @@ -53,7 +56,7 @@ properties: port@1: $ref: /schemas/graph.yaml#/properties/port description: - Video port for MIPI DPI output panel. + Video port for MIPI DPI or LVDS output to the panel. required: - port@0 diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 8239adb7f7d3..094a6383bb77 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -219,6 +219,7 @@ allOf: - required: - "#sound-dai-cells" else: + $ref: /schemas/sound/dai-common.yaml# properties: aux-bus: false required: @@ -243,7 +244,7 @@ allOf: clocks: minItems: 5 maxItems: 5 - clocks-names: + clock-names: minItems: 5 maxItems: 5 @@ -264,7 +265,7 @@ allOf: clocks: minItems: 5 maxItems: 6 - clocks-names: + clock-names: minItems: 5 maxItems: 6 @@ -277,7 +278,6 @@ allOf: - qcom,sc8180x-dp - qcom,sdm845-dp - qcom,sm8350-dp - - qcom,sm8650-dp then: properties: reg: @@ -286,6 +286,24 @@ allOf: clocks: minItems: 6 maxItems: 6 + clock-names: + minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8650-dp + then: + properties: + reg: + minItems: 5 + maxItems: 9 + clocks: + minItems: 6 + maxItems: 6 clocks-names: minItems: 6 maxItems: 6 @@ -306,7 +324,7 @@ allOf: clocks: minItems: 6 maxItems: 8 - clocks-names: + clock-names: minItems: 6 maxItems: 8 @@ -326,7 +344,7 @@ allOf: clocks: minItems: 5 maxItems: 6 - clocks-names: + clock-names: minItems: 5 maxItems: 6 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml index 47938d13d1ca..bd4ba91a171f 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml @@ -119,7 +119,7 @@ examples: mdss_mdp: display-controller@ae01000 { compatible = "qcom,eliza-dpu"; reg = <0x0ae01000 0x93000>, - <0x0aeb0000 0x2008>; + <0x0aeb0000 0x3000>; reg-names = "mdp", "vbif"; @@ -304,7 +304,7 @@ examples: mdss_dsi0_phy: phy@ae95000 { compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; reg = <0x0ae95000 0x200>, - <0x0ae95200 0x280>, + <0x0ae95200 0x300>, <0x0ae95500 0x400>; reg-names = "dsi_phy", "dsi_phy_lane", @@ -388,7 +388,7 @@ examples: mdss_dsi1_phy: phy@ae97000 { compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; reg = <0x0ae97000 0x200>, - <0x0ae97200 0x280>, + <0x0ae97200 0x300>, <0x0ae97500 0x400>; reg-names = "dsi_phy", "dsi_phy_lane", @@ -407,11 +407,15 @@ examples: displayport-controller@af54000 { compatible = "qcom,eliza-dp", "qcom,sm8650-dp"; - reg = <0xaf54000 0x104>, - <0xaf54200 0xc0>, - <0xaf55000 0x770>, - <0xaf56000 0x9c>, - <0xaf57000 0x9c>; + reg = <0x0af54000 0x200>, + <0x0af54200 0x200>, + <0x0af55000 0xc00>, + <0x0af56000 0x400>, + <0x0af57000 0x400>, + <0x0af58000 0x400>, + <0x0af59000 0x400>, + <0x0af5a000 0x600>, + <0x0af5b000 0x600>; interrupts-extended = <&mdss 12>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index dccac525d202..134321b50897 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -70,7 +70,7 @@ examples: display-controller@ae01000 { compatible = "qcom,sm8650-dpu"; reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; + <0x0aeb0000 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc_axi_clk>, diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml index a1c53e191033..0f7f79527748 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml @@ -112,7 +112,7 @@ examples: display-controller@ae01000 { compatible = "qcom,sm8650-dpu"; reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; + <0x0aeb0000 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc_axi_clk>, diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml index a38c2261ef1a..46dc0d28da29 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -117,7 +117,7 @@ examples: display-controller@ae01000 { compatible = "qcom,sm8750-dpu"; reg = <0x0ae01000 0x93000>, - <0x0aeb0000 0x2008>; + <0x0aeb0000 0x3000>; reg-names = "mdp", "vbif"; @@ -389,11 +389,15 @@ examples: displayport-controller@af54000 { compatible = "qcom,sm8750-dp", "qcom,sm8650-dp"; - reg = <0xaf54000 0x104>, - <0xaf54200 0xc0>, - <0xaf55000 0x770>, - <0xaf56000 0x9c>, - <0xaf57000 0x9c>; + reg = <0x0af54000 0x200>, + <0x0af54200 0x200>, + <0x0af55000 0xc00>, + <0x0af56000 0x400>, + <0x0af57000 0x400>, + <0x0af58000 0x400>, + <0x0af59000 0x400>, + <0x0af5a000 0x600>, + <0x0af5b000 0x600>; interrupts-extended = <&mdss 12>; diff --git a/Documentation/devicetree/bindings/display/panel/chipwealth,ch13726a.yaml b/Documentation/devicetree/bindings/display/panel/chipwealth,ch13726a.yaml new file mode 100644 index 000000000000..c8d7b61037e6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/chipwealth,ch13726a.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/chipwealth,ch13726a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chip Wealth Technology CH13726A AMOLED driver + +maintainers: + - Neil Armstrong + +description: + Chip Wealth Technology CH13726A is a single-chip solution + for AMOLED connected using a MIPI-DSI video interface. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: ayntec,thor-panel-bottom + - const: chipwealth,ch13726a + + reg: + maxItems: 1 + description: DSI virtual channel + + vdd-supply: true + vddio-supply: true + vdd1v2-supply: true + avdd-supply: true + + port: true + reset-gpios: true + rotation: true + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + - vdd1v2-supply + - avdd-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "ayntec,thor-panel-bottom", "chipwealth,ch13726a"; + reg = <0>; + vdd1v2-supply = <&vreg_l11b_1p2>; + vddio-supply = <&vdd_disp_1v8>; + vdd-supply = <&vreg_l13b_3p0>; + avdd-supply = <&vdd_disp2_2v8>; + reset-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml b/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml new file mode 100644 index 000000000000..db6775f4d75c --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/focaltech,ota7290b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Focaltech OTA7290B DSI panels + +maintainers: + - Dmitry Baryshkov + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: waveshare,8.8-dsi-touch-a + + reg: + maxItems: 1 + + vdd-supply: + description: supply regulator for VDD, usually 3.3V + + vdda-supply: + description: supply regulator for VDDA, 7-10V + + vcc-supply: + description: supply regulator for VCCIO, usually 1.5V + + reset-gpios: true + backlight: true + rotation: true + port: true + +required: + - compatible + - reg + - vdd-supply + - vcc-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "waveshare,8.8-dsi-touch-a"; + reg = <0>; + vdd-supply = <&vdd>; + vcc-supply = <&vccio>; + reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + + port { + endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; + +... + diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml index 66404b425af3..7667428bf9a8 100644 --- a/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml +++ b/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml @@ -30,6 +30,8 @@ properties: - starry,2082109qfh040022-50e # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel - starry,himax83102-j02 + # Waveshare 12.3-DSI-TOUCH-A panel + - waveshare,12.3-dsi-touch-a - const: himax,hx83102 reg: diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml index 84e840e0224f..83c343b02835 100644 --- a/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml +++ b/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml @@ -23,6 +23,8 @@ properties: - hannstar,hsd060bhw4 - microchip,ac40t08a-mipi-panel - powkiddy,x55-panel + - waveshare,5.0-dsi-touch-a + - waveshare,5.5-dsi-touch-a - const: himax,hx8394 - items: - enum: diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml index d979701a00a8..42e35986fbf6 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml @@ -24,6 +24,7 @@ properties: - raspberrypi,dsi-7inch - startek,kd050hdfia020 - tdo,tl050hdv35 + - waveshare,7.0-dsi-touch-a - wanchanglong,w552946aaa - wanchanglong,w552946aba - const: ilitek,ili9881c @@ -34,6 +35,7 @@ properties: backlight: true port: true power-supply: true + iovcc-supply: true reset-gpios: true rotation: true diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml index e39efb44ed42..4eae802de9fd 100644 --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml @@ -24,6 +24,12 @@ properties: - radxa,display-10hd-ad001 - radxa,display-8hd-ad002 - taiguanck,xti05101-01a + - waveshare,3.4-dsi-touch-c + - waveshare,4.0-dsi-touch-c + - waveshare,8.0-dsi-touch-a + - waveshare,9.0-dsi-touch-b + - waveshare,10.1-dsi-touch-a + - waveshare,10.1-dsi-touch-b - const: jadard,jd9365da-h3 reg: diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml new file mode 100644 index 000000000000..ff6fdad7febf --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt35532.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT35532-based DSI display panels + +maintainers: + - Cristian Cozzolino + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - flipkart,rimob-panel-nt35532-cs + - const: novatek,nt35532 + + reg: + maxItems: 1 + + backlight: true + reset-gpios: true + + avdd-supply: + description: positive boost supply regulator + + avee-supply: + description: negative boost supply regulator + + vci-supply: + description: regulator that supplies the analog voltage + + vddam-supply: + description: power supply for MIPI interface + + vddi-supply: + description: regulator that supplies the I/O voltage + + port: true + +required: + - compatible + - reg + - reset-gpios + - vddi-supply + - port + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "flipkart,rimob-panel-nt35532-cs", "novatek,nt35532"; + reg = <0>; + + backlight = <&pmi8950_wled>; + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; + avdd-supply = <&lab>; + avee-supply = <&ibb>; + vci-supply = <&pm8953_l17>; + vddi-supply = <&pm8953_l6>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml index cc8d795df732..6d4133b91e7c 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml @@ -63,6 +63,8 @@ properties: - samsung,s6e3fa7-ams559nk06 # Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel - tdo,tl070wsh30 + # Team Source Display Technology 7" TST070WSBE-196C 1024x600 TFT LCD panel + - team-source-display,tst070wsbe-196c reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 3e41ed0ef5d5..44ec7388d851 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -97,6 +97,8 @@ properties: - dataimage,fg1001l0dsswmg01 # DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface. - dataimage,scf0700c48ggu18 + # Displaytech DT050BTFT-PTS 5.0" 800x480 TFT LCD Panel + - displaytech,dt050btft-pts # DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel - dlc,dlc1010gig # Emerging Display Technology Corp. 3.5" QVGA TFT LCD panel @@ -304,6 +306,8 @@ properties: - shelly,sca07010-bfn-lnn # Starry KR070PE2T 7" WVGA TFT LCD panel - starry,kr070pe2t + # Startek KD070HDFLD092 7" WSVGA TFT LCD panel + - startek,kd070hdfld092 # Startek KD070WVFPA043-C069A 7" TFT LCD panel - startek,kd070wvfpa # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel @@ -341,10 +345,38 @@ properties: - vivax,tpc9150-panel # VXT 800x480 color TFT LCD panel - vxt,vl050-8048nt-c01 + # Waveshare 10.1" WXGA (1280x800) LCD panel + - waveshare,10.1inch-c-panel + # Waveshare 11.9" (320x1480) LCD panel + - waveshare,11.9inch-panel # Waveshare 13.3" FHD (1920x1080) LCD panel - waveshare,13.3inch-panel + # Waveshare 2.8" VGA (480x640) LCD panel + - waveshare,2.8inch-panel + # Waveshare 3.4" (800x800) LCD panel + - waveshare,3.4inch-c-panel + # Waveshare 4.0" WVGA (480x800) LCD panel + - waveshare,4.0inch-panel + # Waveshare 4.0" (720x720) LCD panel + - waveshare,4.0inch-c-panel + # Waveshare 5.0" WSVGA (1024x600) LCD panel + - waveshare,5.0inch-c-panel + # Waveshare 5.0" HD 720p (720x1280) LCD panel + - waveshare,5.0inch-d-panel + # Waveshare 6.25" (720x1560) LCD panel + - waveshare,6.25inch-panel # Waveshare 7.0" WSVGA (1024x600) LCD panel - waveshare,7.0inch-c-panel + # Waveshare 7.0" WXGA (1280x800) LCD panel + - waveshare,7.0inch-e-panel + # Waveshare 7.0" HD 720p (720x1280) LCD panel + - waveshare,7.0inch-h-panel + # Waveshare 7.9" (400x1280) LCD panel + - waveshare,7.9inch-panel + # Waveshare 8.0" WXGA (1280x800) LCD panel + - waveshare,8.0inch-c-panel + # Waveshare 8.8" (480x1920) LCD panel + - waveshare,8.8inch-panel # Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel - winstar,wf35ltiacd # Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index db49b8ff8c74..9db9f84ad964 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -26,6 +26,7 @@ properties: - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a08g046-mali - renesas,r9a09g047-mali - renesas,r9a09g056-mali - renesas,r9a09g057-mali @@ -150,6 +151,7 @@ allOf: enum: - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a08g046-mali - renesas,r9a09g047-mali - renesas,r9a09g056-mali - renesas,r9a09g057-mali diff --git a/Documentation/devicetree/bindings/i2c/amlogic,meson6-i2c.yaml b/Documentation/devicetree/bindings/i2c/amlogic,meson6-i2c.yaml index c4cc8af18280..7b59b60b62e5 100644 --- a/Documentation/devicetree/bindings/i2c/amlogic,meson6-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/amlogic,meson6-i2c.yaml @@ -16,10 +16,15 @@ allOf: properties: compatible: - enum: - - amlogic,meson6-i2c # Meson6, Meson8 and compatible SoCs - - amlogic,meson-gxbb-i2c # GXBB and compatible SoCs - - amlogic,meson-axg-i2c # AXG and compatible SoCs + oneOf: + - items: + - enum: + - amlogic,t7-i2c + - const: amlogic,meson-axg-i2c + - enum: + - amlogic,meson6-i2c # Meson6, Meson8 and compatible SoCs + - amlogic,meson-gxbb-i2c # GXBB and compatible SoCs + - amlogic,meson-axg-i2c # AXG and compatible SoCs reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index 500a965bdb7a..9e59200ad37b 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -22,7 +22,9 @@ properties: compatible: oneOf: - items: - - const: apple,t6020-i2c + - enum: + - apple,t6020-i2c + - apple,t8122-i2c - const: apple,t8103-i2c - items: - enum: diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index 7c4d6170491d..f5c584cf2146 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -24,6 +24,7 @@ properties: compatible: items: - enum: + - qcom,eliza-ipcc - qcom,glymur-ipcc - qcom,kaanapali-ipcc - qcom,milos-ipcc diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml index 91e8cd1db67b..b66ae6300faf 100644 --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -73,6 +73,15 @@ properties: HSP CSR is to control and get status of different high-speed peripherals (such as Ethernet, USB, SATA, etc.) via register, which can tune board-level's parameters of PHY, etc. + + Additional background information about the High-Speed Subsystem + and the HSP CSR block is available in Chapter 10 ("High-Speed Interface") + of the EIC7700X SoC Technical Reference Manual, Part 4 + (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is + publicly available at + https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases + + This reference is provided for background information only. $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: @@ -82,6 +91,8 @@ properties: - description: Offset of AXI clock controller Low-Power request register - description: Offset of register controlling TX/RX clock delay + - description: Optional offset of register controlling TXD delay + - description: Optional offset of register controlling RXD delay required: - compatible @@ -116,7 +127,7 @@ examples: reset-names = "stmmaceth"; rx-internal-delay-ps = <200>; tx-internal-delay-ps = <200>; - eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>; snps,axi-config = <&stmmac_axi_setup>; snps,aal; snps,fixed-burst; diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650-rt5514.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650-rt5514.yaml index ed698c9ff42b..becc7a11f8dc 100644 --- a/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650-rt5514.yaml +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650-rt5514.yaml @@ -18,7 +18,9 @@ properties: description: Phandles of rt5650 and rt5514 codecs items: - description: phandle of rt5650 codec + maxItems: 1 - description: phandle of rt5514 codec + maxItems: 1 mediatek,platform: $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml index 1d10cfbad86c..504df31a4f90 100644 --- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml @@ -20,6 +20,9 @@ properties: - fsl,ls1021a-qspi - fsl,ls2080a-qspi - spacemit,k1-qspi + - items: + - const: spacemit,k3-qspi + - const: spacemit,k1-qspi - items: - enum: - fsl,ls1043a-qspi diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 28784d66ae7b..11c55b5df0e4 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -437,6 +437,8 @@ patternProperties: description: Diodes, Inc. "^dioo,.*": description: Dioo Microcircuit Co., Ltd + "^displaytech,.*": + description: Displaytech Ltd. "^djn,.*": description: Shenzhen DJN Optronics Technology Co., Ltd "^dlc,.*": diff --git a/Documentation/filesystems/isofs.rst b/Documentation/filesystems/isofs.rst index 08fd469091d4..2a30999b024f 100644 --- a/Documentation/filesystems/isofs.rst +++ b/Documentation/filesystems/isofs.rst @@ -57,7 +57,7 @@ Mount options unique to the isofs filesystem. Recommended documents about ISO 9660 standard are located at: - http://www.y-adagio.com/ -- ftp://ftp.ecma.ch/ecma-st/Ecma-119.pdf +- https://ecma-international.org/wp-content/uploads/ECMA-119_2nd_edition_december_1987.pdf Quoting from the PDF "This 2nd Edition of Standard ECMA-119 is technically identical with ISO 9660.", so it is a valid and gratis substitute of the diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst index 033167025fcc..d553dd599c96 100644 --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst @@ -233,8 +233,15 @@ we have a dedicated glossary for Display Core at TC Texture Cache + TCC + Texture Cache per Channel - L2 cache attached to the memory channels. + May be used when shader cores are accessing memory. + Despite "Texture" in the name, this is used by any kind of memory access. + TCCs may be mapped to TCPs, depending on the architecture. + TCP (AMDGPU) - Texture Cache per Pipe. Even though the name "Texture" is part of this + Texture Cache per Pipe - L1 cache attached to each CU. + Even though the name "Texture" is part of this acronym, the TCP represents the path to memory shaders; i.e., it is not related to texture. The name is a leftover from older designs where shader stages had different cache designs; it refers to the L1 cache in older diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst index 8732084186a4..b2ab182236ef 100644 --- a/Documentation/gpu/amdgpu/index.rst +++ b/Documentation/gpu/amdgpu/index.rst @@ -23,3 +23,4 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures. debugfs process-isolation amdgpu-glossary + ptl diff --git a/Documentation/gpu/amdgpu/ptl.rst b/Documentation/gpu/amdgpu/ptl.rst new file mode 100644 index 000000000000..c7f16dea7954 --- /dev/null +++ b/Documentation/gpu/amdgpu/ptl.rst @@ -0,0 +1,94 @@ +======================================= +Peak Tops Limiter (PTL) sysfs Interface +======================================= + +Overview +-------- +The Peak Tops Limiter (PTL) sysfs interface enables users to control and +configure the PTL feature for each GPU individually. All PTL-related +sysfs files are located under `/sys/class/drm/cardX/device/ptl/`, where +`X` is the GPU index. Through these files, users can enable or disable +PTL, set preferred data formats, and query supported formats for each GPU. + +PTL sysfs files +---------------- +The following files are available under `/sys/class/drm/cardX/device/ptl/`: + +- `ptl_enable` +- `ptl_format` +- `ptl_supported_formats` + +PTL Enable/Disable +------------------ +File: `ptl_enable` +Type: Read/Write (rw) + +Read: Returns the current PTL status as a string: `enabled` if PTL +is active, or `disabled` if inactive. + +Write: + +- Write `1` or `enabled` to enable PTL +- Write `0` or `disabled` to disable PTL + +Examples:: + + # Query PTL status + cat /sys/class/drm/card1/device/ptl/ptl_enable + # Output: enabled + + # Enable PTL + sudo bash -c "echo 1 > /sys/class/drm/card1/device/ptl/ptl_enable" + + # Disable PTL + sudo bash -c "echo 0 > /sys/class/drm/card1/device/ptl/ptl_enable" + +PTL Format (Preferred Data Formats) +----------------------------------- +File: `ptl_format` +Type: Read/Write (rw) + +Read: Returns the two preferred formats, e.g. `I8,F32`. + +Write: Accepts two formats separated by a comma, e.g. `I8,F32`. + +- Both formats must be supported and different. +- If an invalid format is provided (not supported, or both formats are the + same), the driver will return "write error: Invalid argument". + +Examples:: + + # Query PTL formats + cat /sys/class/drm/card1/device/ptl/ptl_format + # Output: I8,F32 + + # Set PTL formats + sudo bash -c "echo I8,F32 > /sys/class/drm/card1/device/ptl/ptl_format" + +Supported Formats +----------------- +File: `ptl_supported_formats` +Type: Read-only (r) + +Read: Returns a comma-separated list of supported formats, e.g. +`I8,F16,BF16,F32,F64`. + +Example:: + + # Check supported formats + cat /sys/class/drm/card1/device/ptl/ptl_supported_formats + # Output: I8,F16,BF16,F32,F64 + +Behavioral Notes +---------------- +- PTL formats can only be set when PTL is enabled. +- If PTL is disabled, `ptl_format` returns `N/A`. +- Only two formats can be set at a time, and they must be from the supported set and different.. +- All commands support per-GPU targeting. +- Root permission is required to enable/disable PTL or change formats. +- If the hardware does not support PTL, the PTL sysfs directory will not + be created. + +Implementation +-------------- +The PTL sysfs nodes are implemented in `drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c`. diff --git a/Documentation/gpu/driver-uapi.rst b/Documentation/gpu/driver-uapi.rst index 1f15a8ca1265..627fc68c7a21 100644 --- a/Documentation/gpu/driver-uapi.rst +++ b/Documentation/gpu/driver-uapi.rst @@ -2,6 +2,8 @@ DRM Driver uAPI =============== +.. contents:: + drm/i915 uAPI ============= diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst index 2e13e0ad7e88..20d2c454aa1d 100644 --- a/Documentation/gpu/drivers.rst +++ b/Documentation/gpu/drivers.rst @@ -8,6 +8,7 @@ GPU Driver Documentation amdgpu/index i915 imagination/index + intel-display/index mcde meson nouveau diff --git a/Documentation/gpu/drm-internals.rst b/Documentation/gpu/drm-internals.rst index 94f93fd3b8a0..a3ce25a36f1d 100644 --- a/Documentation/gpu/drm-internals.rst +++ b/Documentation/gpu/drm-internals.rst @@ -18,6 +18,8 @@ event handling, memory management, output management, framebuffer management, command submission & fencing, suspend/resume support, and DMA services. +.. contents:: + Driver Initialization ===================== diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst index b4a9e5ae81f6..80453dda33b8 100644 --- a/Documentation/gpu/drm-kms-helpers.rst +++ b/Documentation/gpu/drm-kms-helpers.rst @@ -33,6 +33,8 @@ There are a few areas these helpers can grouped into: pipeline: Planes, handling rectangles for visibility checking and scissoring, flip queues and assorted bits. +.. contents:: + Modeset Helper Reference for Common Vtables =========================================== diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 2292e65f044c..fa69a5450f96 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -1,3 +1,6 @@ + +.. _drm-kms: + ========================= Kernel Mode Setting (KMS) ========================= @@ -15,6 +18,8 @@ be setup by initializing the following fields. - struct drm_mode_config_funcs \*funcs; Mode setting functions. +.. contents:: + Overview ======== @@ -206,11 +211,11 @@ Atomic Mode Setting style=dashed label="Free-standing state" - "drm_atomic_state" -> "duplicated drm_plane_state A" - "drm_atomic_state" -> "duplicated drm_plane_state B" - "drm_atomic_state" -> "duplicated drm_crtc_state" - "drm_atomic_state" -> "duplicated drm_connector_state" - "drm_atomic_state" -> "duplicated driver private state" + "drm_atomic_commit" -> "duplicated drm_plane_state A" + "drm_atomic_commit" -> "duplicated drm_plane_state B" + "drm_atomic_commit" -> "duplicated drm_crtc_state" + "drm_atomic_commit" -> "duplicated drm_connector_state" + "drm_atomic_commit" -> "duplicated driver private state" } subgraph cluster_current { @@ -230,7 +235,7 @@ Atomic Mode Setting "driver private object" -> "driver private state" } - "drm_atomic_state" -> "drm_device" [label="atomic_commit"] + "drm_atomic_commit" -> "drm_device" [label="atomic_commit"] "duplicated drm_plane_state A" -> "drm_device"[style=invis] } @@ -265,7 +270,7 @@ Taken all together there's two consequences for the atomic design: drm_private_state`. - An atomic update is assembled and validated as an entirely free-standing pile - of structures within the :c:type:`drm_atomic_state ` + of structures within the :c:type:`drm_atomic_commit ` container. Driver private state structures are also tracked in the same structure; see the next chapter. Only when a state is committed is it applied to the driver and modeset objects. This way rolling back an update boils down diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst index 32fb506db05b..2dea94f77d52 100644 --- a/Documentation/gpu/drm-mm.rst +++ b/Documentation/gpu/drm-mm.rst @@ -25,6 +25,8 @@ share it. GEM has simpler initialization and execution requirements than TTM, but has no video RAM management capabilities and is thus limited to UMA devices. +.. contents:: + The Translation Table Manager (TTM) =================================== diff --git a/Documentation/gpu/drm-ras.rst b/Documentation/gpu/drm-ras.rst index 70b246a78fc8..83c21853b74b 100644 --- a/Documentation/gpu/drm-ras.rst +++ b/Documentation/gpu/drm-ras.rst @@ -24,6 +24,8 @@ Key Goals: nodes for different IP blocks, sub-blocks, or other logical subdivisions as applicable. +.. contents:: + Nodes ===== @@ -52,6 +54,8 @@ User space tools can: as a parameter. * Query specific error counter values with the ``get-error-counter`` command, using both ``node-id`` and ``error-id`` as parameters. +* Clear specific error counters with the ``clear-error-counter`` command, using both + ``node-id`` and ``error-id`` as parameters. YAML-based Interface -------------------- @@ -101,3 +105,9 @@ Example: Query an error counter for a given node sudo ynl --family drm_ras --do get-error-counter --json '{"node-id":0, "error-id":1}' {'error-id': 1, 'error-name': 'error_name1', 'error-value': 0} +Example: Clear an error counter for a given node + +.. code-block:: bash + + sudo ynl --family drm_ras --do clear-error-counter --json '{"node-id":0, "error-id":1}' + None diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst index 579e87cb9ff7..2c2f939322fb 100644 --- a/Documentation/gpu/drm-uapi.rst +++ b/Documentation/gpu/drm-uapi.rst @@ -16,6 +16,8 @@ management, and output management. Cover generic ioctls and sysfs layout here. We only need high-level info, since man pages should cover the rest. +.. contents:: + libdrm Device Lookup ==================== @@ -118,6 +120,10 @@ is already rather painful for the DRM subsystem, with multiple different uAPIs for the same thing co-existing. If we add a few more complete mistakes into the mix every year it would be entirely unmanageable. +The DRM subsystem has however no concern with independent closed-source +userspace implementations. To officialize that position, the DRM uAPI headers +are covered by the MIT license. + .. _drm_render_node: Render nodes @@ -761,4 +767,4 @@ Stable uAPI events From ``drivers/gpu/drm/scheduler/gpu_scheduler_trace.h`` .. kernel-doc:: drivers/gpu/drm/scheduler/gpu_scheduler_trace.h - :doc: uAPI trace events \ No newline at end of file + :doc: uAPI trace events diff --git a/Documentation/gpu/drm-usage-stats.rst b/Documentation/gpu/drm-usage-stats.rst index 63d6b2abe5ad..70b7cfcc194f 100644 --- a/Documentation/gpu/drm-usage-stats.rst +++ b/Documentation/gpu/drm-usage-stats.rst @@ -16,6 +16,8 @@ output is split between common and driver specific parts. Having said that, wherever possible effort should still be made to standardise as much as possible. +.. contents:: + File format specification ========================= @@ -215,3 +217,4 @@ Driver specific implementations * :ref:`panfrost-usage-stats` * :ref:`panthor-usage-stats` * :ref:`xe-usage-stats` +* :ref:`amdxdna-usage-stats` diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index eba09c3ddce4..0c9d68758533 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -1,3 +1,6 @@ + +.. _drm/i915: + =========================== drm/i915 Intel GFX Driver =========================== @@ -7,6 +10,9 @@ models) integrated GFX chipsets with both Intel display and rendering blocks. This excludes a set of SoC platforms with an SGX rendering unit, those have basic support through the gma500 drm driver. +The display, or :ref:`drm-kms`, support for drm/i915 is provided by +:ref:`drm/intel-display`, and shared with :ref:`drm/xe `. + Core Driver Infrastructure ========================== @@ -64,200 +70,6 @@ Workarounds .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c :doc: Hardware workarounds -Display Hardware Handling -========================= - -This section covers everything related to the display hardware including -the mode setting infrastructure, plane, sprite and cursor handling and -display, output probing and related topics. - -Mode Setting Infrastructure ---------------------------- - -The i915 driver is thus far the only DRM driver which doesn't use the -common DRM helper code to implement mode setting sequences. Thus it has -its own tailor-made infrastructure for executing a display configuration -change. - -Frontbuffer Tracking --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c - :doc: frontbuffer tracking - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h - :internal: - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c - :internal: - -Display FIFO Underrun Reporting -------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c - :doc: fifo underrun handling - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c - :internal: - -Plane Configuration -------------------- - -This section covers plane configuration and composition with the primary -plane, sprites, cursors and overlays. This includes the infrastructure -to do atomic vsync'ed updates of all this state and also tightly coupled -topics like watermark setup and computation, framebuffer compression and -panel self refresh. - -Atomic Plane Helpers --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c - :doc: atomic plane helpers - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c - :internal: - -Asynchronous Page Flip ----------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c - :doc: asynchronous flip implementation - -Output Probing --------------- - -This section covers output probing and related infrastructure like the -hotplug interrupt storm detection and mitigation code. Note that the -i915 driver still uses most of the common DRM helper code for output -probing, so those sections fully apply. - -Hotplug -------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c - :doc: Hotplug - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c - :internal: - -High Definition Audio ---------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c - :doc: High Definition Audio over HDMI and Display Port - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c - :internal: - -.. kernel-doc:: include/drm/intel/i915_component.h - :internal: - -Intel HDMI LPE Audio Support ----------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c - :doc: LPE Audio integration for HDMI or DP playback - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c - :internal: - -Panel Self Refresh PSR (PSR/SRD) --------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c - :doc: Panel Self Refresh (PSR/SRD) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c - :internal: - -Frame Buffer Compression (FBC) ------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c - :doc: Frame Buffer Compression (FBC) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c - :internal: - -Display Refresh Rate Switching (DRRS) -------------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c - :doc: Display Refresh Rate Switching (DRRS) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c - :internal: - -DPIO ----- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c - :doc: DPIO - -DMC Firmware Support --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c - :doc: DMC Firmware Support - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c - :internal: - -DMC Flip Queue --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_flipq.c - :doc: DMC Flip Queue - -DMC wakelock support --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c - :doc: DMC wakelock support - -Video BIOS Table (VBT) ----------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c - :doc: Video BIOS Table (VBT) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c - :internal: - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h - :internal: - -Display clocks --------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c - :doc: CDCLK / RAWCLK - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c - :internal: - -Display PLLs ------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c - :doc: Display PLLs - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c - :internal: - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h - :internal: - -Display State Buffer --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c - :doc: DSB - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c - :internal: - GT Programming ============== @@ -568,7 +380,7 @@ The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ DMC --- -See `DMC Firmware Support`_ +See :ref:`drm/intel-display/dmc`. Tracing ======= diff --git a/Documentation/gpu/index.rst b/Documentation/gpu/index.rst index 5d708a106b3f..65bf3b26e4f4 100644 --- a/Documentation/gpu/index.rst +++ b/Documentation/gpu/index.rst @@ -3,6 +3,7 @@ GPU Driver Developer's Guide ============================ .. toctree:: + :maxdepth: 2 introduction drm-internals diff --git a/Documentation/gpu/intel-display/async-flip.rst b/Documentation/gpu/intel-display/async-flip.rst new file mode 100644 index 000000000000..40f93e885bb7 --- /dev/null +++ b/Documentation/gpu/intel-display/async-flip.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Asynchronous Page Flip +====================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c + :doc: asynchronous flip implementation diff --git a/Documentation/gpu/intel-display/atomic.rst b/Documentation/gpu/intel-display/atomic.rst new file mode 100644 index 000000000000..43a473181e7a --- /dev/null +++ b/Documentation/gpu/intel-display/atomic.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Atomic Modeset Support +====================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic.c + :doc: atomic modeset support + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic.c + :internal: diff --git a/Documentation/gpu/intel-display/audio.rst b/Documentation/gpu/intel-display/audio.rst new file mode 100644 index 000000000000..eef95df75f8d --- /dev/null +++ b/Documentation/gpu/intel-display/audio.rst @@ -0,0 +1,23 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +High Definition Audio +===================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c + :doc: High Definition Audio over HDMI and Display Port + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c + :internal: + +.. kernel-doc:: include/drm/intel/i915_component.h + :internal: + +Intel HDMI LPE Audio Support +============================ + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c + :doc: LPE Audio integration for HDMI or DP playback + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c + :internal: diff --git a/Documentation/gpu/intel-display/casf.rst b/Documentation/gpu/intel-display/casf.rst new file mode 100644 index 000000000000..406778ccd94c --- /dev/null +++ b/Documentation/gpu/intel-display/casf.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Content Adaptive Sharpness Filter (CASF) +======================================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_casf.c + :doc: Content Adaptive Sharpness Filter (CASF) diff --git a/Documentation/gpu/intel-display/cdclk.rst b/Documentation/gpu/intel-display/cdclk.rst new file mode 100644 index 000000000000..a66d623b0ec9 --- /dev/null +++ b/Documentation/gpu/intel-display/cdclk.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display clocks +============== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c + :doc: CDCLK / RAWCLK + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c + :internal: diff --git a/Documentation/gpu/intel-display/cmtg.rst b/Documentation/gpu/intel-display/cmtg.rst new file mode 100644 index 000000000000..04edd0bd165d --- /dev/null +++ b/Documentation/gpu/intel-display/cmtg.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Common Primary Timing Generator (CMTG) +====================================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cmtg.c + :doc: Common Primary Timing Generator (CMTG) diff --git a/Documentation/gpu/intel-display/dmc.rst b/Documentation/gpu/intel-display/dmc.rst new file mode 100644 index 000000000000..4368da4c7048 --- /dev/null +++ b/Documentation/gpu/intel-display/dmc.rst @@ -0,0 +1,26 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +.. _drm/intel-display/dmc: + +DMC Firmware Support +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c + :doc: DMC Firmware Support + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c + :internal: + + +DMC Flip Queue +============== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_flipq.c + :doc: DMC Flip Queue + +DMC wakelock support +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c + :doc: DMC wakelock support diff --git a/Documentation/gpu/intel-display/dpio.rst b/Documentation/gpu/intel-display/dpio.rst new file mode 100644 index 000000000000..84d92ac162f8 --- /dev/null +++ b/Documentation/gpu/intel-display/dpio.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +DPIO +==== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c + :doc: DPIO diff --git a/Documentation/gpu/intel-display/dpll.rst b/Documentation/gpu/intel-display/dpll.rst new file mode 100644 index 000000000000..c750352e0ae5 --- /dev/null +++ b/Documentation/gpu/intel-display/dpll.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display PLLs +============ + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c + :doc: Display PLLs + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h + :internal: diff --git a/Documentation/gpu/intel-display/drrs.rst b/Documentation/gpu/intel-display/drrs.rst new file mode 100644 index 000000000000..a5aaba63d6b9 --- /dev/null +++ b/Documentation/gpu/intel-display/drrs.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display Refresh Rate Switching (DRRS) +===================================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c + :doc: Display Refresh Rate Switching (DRRS) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c + :internal: diff --git a/Documentation/gpu/intel-display/dsb.rst b/Documentation/gpu/intel-display/dsb.rst new file mode 100644 index 000000000000..857aca59995a --- /dev/null +++ b/Documentation/gpu/intel-display/dsb.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display State Buffer +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c + :doc: DSB + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c + :internal: diff --git a/Documentation/gpu/intel-display/fbc.rst b/Documentation/gpu/intel-display/fbc.rst new file mode 100644 index 000000000000..de9e19021f50 --- /dev/null +++ b/Documentation/gpu/intel-display/fbc.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Frame Buffer Compression (FBC) +============================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c + :doc: Frame Buffer Compression (FBC) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c + :internal: diff --git a/Documentation/gpu/intel-display/fifo-underrun.rst b/Documentation/gpu/intel-display/fifo-underrun.rst new file mode 100644 index 000000000000..5d8f01921506 --- /dev/null +++ b/Documentation/gpu/intel-display/fifo-underrun.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display FIFO Underrun Reporting +=============================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c + :doc: fifo underrun handling + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c + :internal: diff --git a/Documentation/gpu/intel-display/frontbuffer.rst b/Documentation/gpu/intel-display/frontbuffer.rst new file mode 100644 index 000000000000..7ae38e0827bf --- /dev/null +++ b/Documentation/gpu/intel-display/frontbuffer.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Frontbuffer Tracking +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c + :doc: frontbuffer tracking + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c + :internal: diff --git a/Documentation/gpu/intel-display/hotplug.rst b/Documentation/gpu/intel-display/hotplug.rst new file mode 100644 index 000000000000..f33bc0087c27 --- /dev/null +++ b/Documentation/gpu/intel-display/hotplug.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Hotplug +======= + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c + :doc: Hotplug + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c + :internal: diff --git a/Documentation/gpu/intel-display/index.rst b/Documentation/gpu/intel-display/index.rst new file mode 100644 index 000000000000..01c3d1e576b7 --- /dev/null +++ b/Documentation/gpu/intel-display/index.rst @@ -0,0 +1,44 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +.. _drm/intel-display: + +==================== +Intel Display Driver +==================== + +The Intel display driver provides the display, or :ref:`drm-kms`, support for +both the :ref:`drm/xe ` and :ref:`drm/i915 ` Intel GPU +drivers. + +The source code currently resides under ``drivers/gpu/drm/i915/display`` due to +historical reasons, and it's compiled separately into both drm/xe and drm/i915 +kernel modules. + +The drm/xe and drm/i915 drivers are the "core" or "parent" drivers for display, +as they initialize and own the drm device, and pass that on to the display +driver. The display driver isn't an independent driver in that sense. + +.. toctree:: + :maxdepth: 1 + :caption: Detailed display topics + + async-flip + atomic + audio + casf + cdclk + cmtg + dmc + dpio + dpll + drrs + dsb + fbc + fifo-underrun + frontbuffer + hotplug + plane + psr + snps-phy + vbt diff --git a/Documentation/gpu/intel-display/plane.rst b/Documentation/gpu/intel-display/plane.rst new file mode 100644 index 000000000000..59932a82051b --- /dev/null +++ b/Documentation/gpu/intel-display/plane.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Atomic Plane Helpers +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c + :doc: atomic plane helpers + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c + :internal: diff --git a/Documentation/gpu/intel-display/psr.rst b/Documentation/gpu/intel-display/psr.rst new file mode 100644 index 000000000000..63e56abcdd56 --- /dev/null +++ b/Documentation/gpu/intel-display/psr.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Panel Self Refresh PSR (PSR/SRD) +================================ + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c + :doc: Panel Self Refresh (PSR/SRD) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c + :internal: diff --git a/Documentation/gpu/intel-display/snps-phy.rst b/Documentation/gpu/intel-display/snps-phy.rst new file mode 100644 index 000000000000..c9e333fa7f62 --- /dev/null +++ b/Documentation/gpu/intel-display/snps-phy.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Synopsis PHY support +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_snps_phy.c + :doc: Synopsis PHY support diff --git a/Documentation/gpu/intel-display/vbt.rst b/Documentation/gpu/intel-display/vbt.rst new file mode 100644 index 000000000000..be69f7fd7b39 --- /dev/null +++ b/Documentation/gpu/intel-display/vbt.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Video BIOS Table (VBT) +====================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c + :doc: Video BIOS Table (VBT) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h + :internal: diff --git a/Documentation/gpu/introduction.rst b/Documentation/gpu/introduction.rst index d8f519693fc2..64074ac22d9b 100644 --- a/Documentation/gpu/introduction.rst +++ b/Documentation/gpu/introduction.rst @@ -16,6 +16,8 @@ found in current kernels. [Insert diagram of typical DRM stack here] +.. contents:: + Style Guidelines ================ diff --git a/Documentation/gpu/komeda-kms.rst b/Documentation/gpu/komeda-kms.rst index eaea40eb725b..9c0745940659 100644 --- a/Documentation/gpu/komeda-kms.rst +++ b/Documentation/gpu/komeda-kms.rst @@ -367,7 +367,7 @@ So, one KMS-Obj represents a sub-pipeline of komeda resources. So, for komeda, we treat KMS crtc/plane/connector as users of pipeline and component, and at any one time a pipeline/component only can be used by one user. And pipeline/component will be treated as private object of DRM-KMS; the -state will be managed by drm_atomic_state as well. +state will be managed by drm_atomic_commit as well. How to map plane to Layer(input) pipeline ----------------------------------------- @@ -416,8 +416,8 @@ Add :c:type:`drm_private_obj` to :c:type:`komeda_component`, :c:type:`komeda_pip ... } -Tracking component_state/pipeline_state by drm_atomic_state ------------------------------------------------------------ +Tracking component_state/pipeline_state by drm_atomic_commit +------------------------------------------------------------ Add :c:type:`drm_private_state` and user to :c:type:`komeda_component_state`, :c:type:`komeda_pipeline_state` @@ -454,7 +454,7 @@ similar, usually including the following steps: put the data flow into next stage. Setup 2: check user_state with component features and capabilities to see if requirements can be met; if not, return fail. - Setup 3: get component_state from drm_atomic_state, and try set to set + Setup 3: get component_state from drm_atomic_commit, and try set to set user to component; fail if component has been assigned to another user already. Setup 3: configure the component_state, like set its input component, diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst index ef19b0ba2a3e..26a7ebe6fb44 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -18,23 +18,9 @@ host such documentation: .. toctree:: - gpusvm.rst - -.. toctree:: - - i915_gem_lmem.rst - -.. toctree:: - - i915_scheduler.rst - -.. toctree:: - - i915_small_bar.rst - -.. toctree:: - - i915_vm_bind.rst - -.. toctree:: - color_pipeline.rst \ No newline at end of file + gpusvm + i915_gem_lmem + i915_scheduler + i915_small_bar + i915_vm_bind + color_pipeline diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index bc9f14c8a2ec..cdddf8db35f5 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -152,29 +152,6 @@ Contact: Simona Vetter, respective driver maintainers Level: Advanced -Rename drm_atomic_state ------------------------ - -The KMS framework uses two slightly different definitions for the ``state`` -concept. For a given object (plane, CRTC, encoder, etc., so -``drm_$OBJECT_state``), the state is the entire state of that object. However, -at the device level, ``drm_atomic_state`` refers to a state update for a -limited number of objects. - -The state isn't the entire device state, but only the full state of some -objects in that device. This is confusing to newcomers, and -``drm_atomic_state`` should be renamed to something clearer like -``drm_atomic_commit``. - -In addition to renaming the structure itself, it would also imply renaming some -related functions (``drm_atomic_state_alloc``, ``drm_atomic_state_get``, -``drm_atomic_state_put``, ``drm_atomic_state_init``, -``__drm_atomic_state_free``, etc.). - -Contact: Maxime Ripard - -Level: Advanced - Fallout from atomic KMS ----------------------- diff --git a/Documentation/gpu/xe/index.rst b/Documentation/gpu/xe/index.rst index bc432c95d1a3..665c0e93601c 100644 --- a/Documentation/gpu/xe/index.rst +++ b/Documentation/gpu/xe/index.rst @@ -1,5 +1,7 @@ .. SPDX-License-Identifier: (GPL-2.0+ OR MIT) +.. _drm/xe: + ======================= drm/xe Intel GFX Driver ======================= @@ -8,6 +10,9 @@ The drm/xe driver supports some future GFX cards with rendering, display, compute and media. Support for currently available platforms like TGL, ADL, DG2, etc is provided to prototype the driver. +The display, or :ref:`drm-kms`, support for drm/xe is provided by +:ref:`drm/intel-display`, and shared with :ref:`drm/i915 `. + .. toctree:: :titlesonly: @@ -29,3 +34,4 @@ DG2, etc is provided to prototype the driver. xe_device xe-drm-usage-stats.rst xe_configfs + xe_gt_stats diff --git a/Documentation/gpu/xe/xe_gt_stats.rst b/Documentation/gpu/xe/xe_gt_stats.rst new file mode 100644 index 000000000000..5ff806abaddb --- /dev/null +++ b/Documentation/gpu/xe/xe_gt_stats.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +================ +Xe GT Statistics +================ + +.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_stats.c + :doc: Xe GT Statistics + +.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_stats_types.h + :internal: diff --git a/Documentation/hwmon/sy7636a-hwmon.rst b/Documentation/hwmon/sy7636a-hwmon.rst index 0143ce0e5db7..03d866aba6e8 100644 --- a/Documentation/hwmon/sy7636a-hwmon.rst +++ b/Documentation/hwmon/sy7636a-hwmon.rst @@ -22,5 +22,5 @@ The following sensors are supported sysfs-Interface --------------- -temp0_input +temp1_input - Temperature of external NTC (milli-degree C) diff --git a/Documentation/hwmon/yogafan.rst b/Documentation/hwmon/yogafan.rst index c553a381f772..68761947a1a8 100644 --- a/Documentation/hwmon/yogafan.rst +++ b/Documentation/hwmon/yogafan.rst @@ -135,4 +135,4 @@ References 4. **Lenovo IdeaPad Laptop Driver:** Reference for DMI-based hardware feature gating in Lenovo laptops. - https://github.com/torvalds/linux/blob/master/drivers/platform/x86/ideapad-laptop.c + https://github.com/torvalds/linux/blob/master/drivers/platform/x86/lenovo/ideapad-laptop.c diff --git a/Documentation/netlink/genetlink-c.yaml b/Documentation/netlink/genetlink-c.yaml index 57f59fe23e3f..4ea31e8fc4d1 100644 --- a/Documentation/netlink/genetlink-c.yaml +++ b/Documentation/netlink/genetlink-c.yaml @@ -69,6 +69,15 @@ properties: header: description: For C-compatible languages, header which already defines this value. type: string + scope: + description: | + Visibility of this definition. "uapi" (default) renders into + the uAPI header, "kernel" renders into the kernel-side + generated header, "user" renders into the user-side + generated header. When combined with `header:`, the + definition is not rendered, and the named header is + included only by code matching the scope. + enum: [ uapi, kernel, user ] type: enum: [ const, enum, flags ] doc: diff --git a/Documentation/netlink/genetlink-legacy.yaml b/Documentation/netlink/genetlink-legacy.yaml index 66fb8653a344..f9c44747729a 100644 --- a/Documentation/netlink/genetlink-legacy.yaml +++ b/Documentation/netlink/genetlink-legacy.yaml @@ -83,6 +83,15 @@ properties: header: description: For C-compatible languages, header which already defines this value. type: string + scope: + description: | + Visibility of this definition. "uapi" (default) renders into + the uAPI header, "kernel" renders into the kernel-side + generated header, "user" renders into the user-side + generated header. When combined with `header:`, the + definition is not rendered, and the named header is + included only by code matching the scope. + enum: [ uapi, kernel, user ] type: enum: [ const, enum, flags, struct ] # Trim doc: diff --git a/Documentation/netlink/genetlink.yaml b/Documentation/netlink/genetlink.yaml index a1194d5d93fc..d3f3f3399ddf 100644 --- a/Documentation/netlink/genetlink.yaml +++ b/Documentation/netlink/genetlink.yaml @@ -55,6 +55,15 @@ properties: header: description: For C-compatible languages, header which already defines this value. type: string + scope: + description: | + Visibility of this definition. "uapi" (default) renders into + the uAPI header, "kernel" renders into the kernel-side + generated header, "user" renders into the user-side + generated header. When combined with `header:`, the + definition is not rendered, and the named header is + included only by code matching the scope. + enum: [ uapi, kernel, user ] type: enum: [ const, enum, flags ] doc: diff --git a/Documentation/netlink/netlink-raw.yaml b/Documentation/netlink/netlink-raw.yaml index dd98dda55bd0..4c436b59a34b 100644 --- a/Documentation/netlink/netlink-raw.yaml +++ b/Documentation/netlink/netlink-raw.yaml @@ -87,6 +87,15 @@ properties: header: description: For C-compatible languages, header which already defines this value. type: string + scope: + description: | + Visibility of this definition. "uapi" (default) renders into + the uAPI header, "kernel" renders into the kernel-side + generated header, "user" renders into the user-side + generated header. When combined with `header:`, the + definition is not rendered, and the named header is + included only by code matching the scope. + enum: [ uapi, kernel, user ] type: enum: [ const, enum, flags, struct ] # Trim doc: diff --git a/Documentation/netlink/specs/drm_ras.yaml b/Documentation/netlink/specs/drm_ras.yaml index 79af25dac3c5..e113056f8c01 100644 --- a/Documentation/netlink/specs/drm_ras.yaml +++ b/Documentation/netlink/specs/drm_ras.yaml @@ -99,7 +99,7 @@ operations: flags: [admin-perm] do: request: - attributes: + attributes: &id-attrs - node-id - error-id reply: @@ -113,3 +113,14 @@ operations: - node-id reply: attributes: *errorinfo + - + name: clear-error-counter + doc: >- + Clear error counter for a given node. + The request includes the error-id and node-id of the + counter to be cleared. + attribute-set: error-counter-attrs + flags: [admin-perm] + do: + request: + attributes: *id-attrs diff --git a/Documentation/netlink/specs/net_shaper.yaml b/Documentation/netlink/specs/net_shaper.yaml index 3f2ad772b64b..de01f922040a 100644 --- a/Documentation/netlink/specs/net_shaper.yaml +++ b/Documentation/netlink/specs/net_shaper.yaml @@ -33,6 +33,11 @@ doc: | @cap-get operation. definitions: + - + type: const + name: max-handle-id + value: 0x3fffffe + scope: kernel - type: enum name: scope @@ -140,6 +145,8 @@ attribute-sets: - name: id type: u32 + checks: + max: max-handle-id doc: | Numeric identifier of a shaper. The id semantic depends on the scope. For @queue scope it's the queue id and for @node diff --git a/Documentation/netlink/specs/psp.yaml b/Documentation/netlink/specs/psp.yaml index 100c36cda8e5..bfcd6e4ecb85 100644 --- a/Documentation/netlink/specs/psp.yaml +++ b/Documentation/netlink/specs/psp.yaml @@ -188,6 +188,7 @@ operations: name: dev-set doc: Set the configuration of a PSP device. attribute-set: dev + flags: [admin-perm] do: request: attributes: @@ -207,6 +208,7 @@ operations: name: key-rotate doc: Rotate the device key. attribute-set: dev + flags: [admin-perm] do: request: attributes: diff --git a/Documentation/networking/device_drivers/ethernet/3com/3c509.rst b/Documentation/networking/device_drivers/ethernet/3com/3c509.rst new file mode 100644 index 000000000000..a8c5e5e6841d --- /dev/null +++ b/Documentation/networking/device_drivers/ethernet/3com/3c509.rst @@ -0,0 +1,249 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================================================================= +Linux and the 3Com EtherLink III Series Ethercards (driver v1.18c and higher) +============================================================================= + +This file contains the instructions and caveats for v1.18c and higher versions +of the 3c509 driver. You should not use the driver without reading this file. + +release 1.0 + +28 February 2002 + +Current maintainer (corrections to): + Maciej W. Rozycki + +Introduction +============ + +The following are notes and information on using the 3Com EtherLink III series +ethercards in Linux. These cards are commonly known by the most widely-used +card's 3Com model number, 3c509. They are all 10mb/s ISA-bus cards and shouldn't +be (but sometimes are) confused with the similarly-numbered PCI-bus "3c905" +(aka "Vortex" or "Boomerang") series. Kernel support for the 3c509 family is +provided by the module 3c509.c, which has code to support all of the following +models: + + - 3c509 (original ISA card) + - 3c509B (later revision of the ISA card; supports full-duplex) + - 3c589 (PCMCIA) + - 3c589B (later revision of the 3c589; supports full-duplex) + - 3c579 (EISA) + +Large portions of this documentation were heavily borrowed from the guide +written the original author of the 3c509 driver, Donald Becker. The master +copy of that document, which contains notes on older versions of the driver, +currently resides on Scyld web server: http://www.scyld.com/. + + +Special Driver Features +======================= + +Overriding card settings + +The driver allows boot- or load-time overriding of the card's detected IOADDR, +IRQ, and transceiver settings, although this capability shouldn't generally be +needed except to enable full-duplex mode (see below). An example of the syntax +for LILO parameters for doing this:: + + ether=10,0x310,3,0x3c509,eth0 + +This configures the first found 3c509 card for IRQ 10, base I/O 0x310, and +transceiver type 3 (10base2). The flag "0x3c509" must be set to avoid conflicts +with other card types when overriding the I/O address. When the driver is +loaded as a module, only the IRQ may be overridden. For example, +setting two cards to IRQ10 and IRQ11 is done by using the irq module +option:: + + options 3c509 irq=10,11 + + +Full-duplex mode +================ + +The v1.18c driver added support for the 3c509B's full-duplex capabilities. +In order to enable and successfully use full-duplex mode, three conditions +must be met: + +(a) You must have a Etherlink III card model whose hardware supports full- +duplex operations. Currently, the only members of the 3c509 family that are +positively known to support full-duplex are the 3c509B (ISA bus) and 3c589B +(PCMCIA) cards. Cards without the "B" model designation do *not* support +full-duplex mode; these include the original 3c509 (no "B"), the original +3c589, the 3c529 (MCA bus), and the 3c579 (EISA bus). + +(b) You must be using your card's 10baseT transceiver (i.e., the RJ-45 +connector), not its AUI (thick-net) or 10base2 (thin-net/coax) interfaces. +AUI and 10base2 network cabling is physically incapable of full-duplex +operation. + +(c) Most importantly, your 3c509B must be connected to a link partner that is +itself full-duplex capable. This is almost certainly one of two things: a full- +duplex-capable Ethernet switch (*not* a hub), or a full-duplex-capable NIC on +another system that's connected directly to the 3c509B via a crossover cable. + +Full-duplex mode can be enabled using 'ethtool'. + +.. warning:: + + Extremely important caution concerning full-duplex mode + + Understand that the 3c509B's hardware's full-duplex support is much more + limited than that provide by more modern network interface cards. Although + at the physical layer of the network it fully supports full-duplex operation, + the card was designed before the current Ethernet auto-negotiation (N-way) + spec was written. This means that the 3c509B family ***cannot and will not + auto-negotiate a full-duplex connection with its link partner under any + circumstances, no matter how it is initialized***. If the full-duplex mode + of the 3c509B is enabled, its link partner will very likely need to be + independently _forced_ into full-duplex mode as well; otherwise various nasty + failures will occur - at the very least, you'll see massive numbers of packet + collisions. This is one of very rare circumstances where disabling auto- + negotiation and forcing the duplex mode of a network interface card or switch + would ever be necessary or desirable. + + +Available Transceiver Types +=========================== + +For versions of the driver v1.18c and above, the available transceiver types are: + +== ========================================================================= +0 transceiver type from EEPROM config (normally 10baseT); force half-duplex +1 AUI (thick-net / DB15 connector) +2 (undefined) +3 10base2 (thin-net == coax / BNC connector) +4 10baseT (RJ-45 connector); force half-duplex mode +8 transceiver type and duplex mode taken from card's EEPROM config settings +12 10baseT (RJ-45 connector); force full-duplex mode +== ========================================================================= + +Prior to driver version 1.18c, only transceiver codes 0-4 were supported. Note +that the new transceiver codes 8 and 12 are the *only* ones that will enable +full-duplex mode, no matter what the card's detected EEPROM settings might be. +This insured that merely upgrading the driver from an earlier version would +never automatically enable full-duplex mode in an existing installation; +it must always be explicitly enabled via one of these code in order to be +activated. + +The transceiver type can be changed using 'ethtool'. + + +Interpretation of error messages and common problems +---------------------------------------------------- + +Error Messages +^^^^^^^^^^^^^^ + +eth0: Infinite loop in interrupt, status 2011. +These are "mostly harmless" message indicating that the driver had too much +work during that interrupt cycle. With a status of 0x2011 you are receiving +packets faster than they can be removed from the card. This should be rare +or impossible in normal operation. Possible causes of this error report are: + + - a "green" mode enabled that slows the processor down when there is no + keyboard activity. + + - some other device or device driver hogging the bus or disabling interrupts. + Check /proc/interrupts for excessive interrupt counts. The timer tick + interrupt should always be incrementing faster than the others. + +No received packets +^^^^^^^^^^^^^^^^^^^ + +If a 3c509, 3c562 or 3c589 can successfully transmit packets, but never +receives packets (as reported by /proc/net/dev or 'ifconfig') you likely +have an interrupt line problem. Check /proc/interrupts to verify that the +card is actually generating interrupts. If the interrupt count is not +increasing you likely have a physical conflict with two devices trying to +use the same ISA IRQ line. The common conflict is with a sound card on IRQ10 +or IRQ5, and the easiest solution is to move the 3c509 to a different +interrupt line. If the device is receiving packets but 'ping' doesn't work, +you have a routing problem. + +Tx Carrier Errors Reported in /proc/net/dev +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + +If an EtherLink III appears to transmit packets, but the "Tx carrier errors" +field in /proc/net/dev increments as quickly as the Tx packet count, you +likely have an unterminated network or the incorrect media transceiver selected. + +3c509B card is not detected on machines with an ISA PnP BIOS. +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +While the updated driver works with most PnP BIOS programs, it does not work +with all. This can be fixed by disabling PnP support using the 3Com-supplied +setup program. + +3c509 card is not detected on overclocked machines +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Increase the delay time in id_read_eeprom() from the current value, 500, +to an absurdly high value, such as 5000. + + +Decoding Status and Error Messages +---------------------------------- + + +The bits in the main status register are: + +===== ====================================== +value description +===== ====================================== +0x01 Interrupt latch +0x02 Tx overrun, or Rx underrun +0x04 Tx complete +0x08 Tx FIFO room available +0x10 A complete Rx packet has arrived +0x20 A Rx packet has started to arrive +0x40 The driver has requested an interrupt +0x80 Statistics counter nearly full +===== ====================================== + +The bits in the transmit (Tx) status word are: + +===== ============================================ +value description +===== ============================================ +0x02 Out-of-window collision. +0x04 Status stack overflow (normally impossible). +0x08 16 collisions. +0x10 Tx underrun (not enough PCI bus bandwidth). +0x20 Tx jabber. +0x40 Tx interrupt requested. +0x80 Status is valid (this should always be set). +===== ============================================ + + +When a transmit error occurs the driver produces a status message such as:: + + eth0: Transmit error, Tx status register 82 + +The two values typically seen here are: + +0x82 +^^^^ + +Out of window collision. This typically occurs when some other Ethernet +host is incorrectly set to full duplex on a half duplex network. + +0x88 +^^^^ + +16 collisions. This typically occurs when the network is exceptionally busy +or when another host doesn't correctly back off after a collision. If this +error is mixed with 0x82 errors it is the result of a host incorrectly set +to full duplex (see above). + +Both of these errors are the result of network problems that should be +corrected. They do not represent driver malfunction. + + +Revision history (this file) +============================ + +28Feb02 v1.0 DR New; major portions based on Becker original 3c509 docs + diff --git a/Documentation/networking/device_drivers/ethernet/index.rst b/Documentation/networking/device_drivers/ethernet/index.rst index 64621c21fd78..1d25be493ae9 100644 --- a/Documentation/networking/device_drivers/ethernet/index.rst +++ b/Documentation/networking/device_drivers/ethernet/index.rst @@ -10,6 +10,7 @@ Contents: .. toctree:: :maxdepth: 2 + 3com/3c509 3com/vortex amazon/ena altera/altera_tse diff --git a/Documentation/process/index.rst b/Documentation/process/index.rst index dbd6ea16aca7..aa7c959a52b8 100644 --- a/Documentation/process/index.rst +++ b/Documentation/process/index.rst @@ -86,6 +86,7 @@ regressions and security problems. debugging/index handling-regressions security-bugs + threat-model cve embargoed-hardware-issues diff --git a/Documentation/process/security-bugs.rst b/Documentation/process/security-bugs.rst index 27b028e85861..3c51ddde31dd 100644 --- a/Documentation/process/security-bugs.rst +++ b/Documentation/process/security-bugs.rst @@ -66,6 +66,42 @@ In addition, the following information are highly desirable: the issue appear. It is useful to share them, as they can be helpful to keep end users protected during the time it takes them to apply the fix. +What qualifies as a security bug +-------------------------------- + +It is important that most bugs are handled publicly so as to involve the widest +possible audience and find the best solution. By nature, bugs that are handled +in closed discussions between a small set of participants are less likely to +produce the best possible fix (e.g., risk of missing valid use cases, limited +testing abilities). + +It turns out that the majority of the bugs reported via the security team are +just regular bugs that have been improperly qualified as security bugs due to +a lack of awareness of the Linux kernel's threat model, as described in +Documentation/process/threat-model.rst, and ought to have been sent through +the normal channels described in Documentation/admin-guide/reporting-issues.rst +instead. + +The security list exists for urgent bugs that grant an attacker a capability +they are not supposed to have on a correctly configured production system, and +can be easily exploited, representing an imminent threat to many users. Before +reporting, consider whether the issue actually crosses a trust boundary on such +a system. + +**If you resorted to AI assistance to identify a bug, you must treat it as +public**. While you may have valid reasons to believe it is not, the security +team's experience shows that bugs discovered this way systematically surface +simultaneously across multiple researchers, often on the same day. In this +case, do not publicly share a reproducer, as this could cause unintended harm; +just mention that one is available and maintainers might ask for it privately +if they need it. + +If you are unsure whether an issue qualifies, err on the side of reporting +privately: the security team would rather triage a borderline report than miss +a real vulnerability. Reporting ordinary bugs to the security list, however, +does not make them move faster and consumes triage capacity that other reports +need. + Identifying contacts -------------------- @@ -74,7 +110,7 @@ affected subsystem's maintainers and Cc: the Linux kernel security team. Do not send it to a public list at this stage, unless you have good reasons to consider the issue as being public or trivial to discover (e.g. result of a widely available automated vulnerability scanning tool that can be repeated by -anyone). +anyone, or use of AI-based tools). If you're sending a report for issues affecting multiple parts in the kernel, even if they're fairly similar issues, please send individual messages (think @@ -131,6 +167,64 @@ the Linux kernel security team only. Your message will be triaged, and you will receive instructions about whom to contact, if needed. Your message may equally be forwarded as-is to the relevant maintainers. +Responsible use of AI to find bugs +---------------------------------- + +A significant fraction of bug reports submitted to the security team are +actually the result of code reviews assisted by AI tools. While this can be an +efficient means to find bugs in rarely explored areas, it causes an overload on +maintainers, who are sometimes forced to ignore such reports due to their poor +quality or accuracy. As such, reporters must be particularly cautious about a +number of points which tend to make these reports needlessly difficult to +handle: + + * **Length**: AI-generated reports tend to be excessively long, containing + multiple sections and excessive detail. This makes it difficult to spot + important information such as affected files, versions, and impact. Please + ensure that a clear summary of the problem and all critical details are + presented first. Do not require triage engineers to scan multiple pages of + text. Configure your tools to produce concise, human-style reports. + + * **Formatting**: Most AI-generated reports are littered with Markdown tags. + These decorations complicate the search for important information and do + not survive the quoting processes involved in forwarding or replying. + Please **always convert your report to plain text** without any formatting + decorations before sending it. + + * **Impact Evaluation**: Many AI-generated reports lack an understanding + of the kernel's threat model (see Documentation/process/threat-model.rst) + and go to great lengths inventing theoretical consequences. This adds + noise and complicates triage. Please stick to verifiable facts (e.g., + "this bug permits any user to gain CAP_NET_ADMIN") without enumerating + speculative implications. Have your tool read this documentation as + part of the evaluation process. + + * **Reproducer**: AI-based tools are often capable of generating reproducers. + Please always ensure your tool provides one and **test it thoroughly**. If + the reproducer does not work, or if the tool cannot produce one, the + validity of the report should be seriously questioned. Note that since the + report will be posted to a public list, the reproducer should only be + shared upon maintainers' request. + + * **Propose a Fix**: Many AI tools are actually better at writing code than + evaluating it. Please ask your tool to propose a fix and **test it** before + reporting the problem. If the fix cannot be tested because it relies on + rare hardware or almost extinct network protocols, the issue is likely not + a security bug. In any case, if a fix is proposed, it must adhere to + Documentation/process/submitting-patches.rst and include a 'Fixes:' tag + designating the commit that introduced the bug. + +Failure to consider these points exposes your report to the risk of being +ignored. + +Use common sense when evaluating the report. If the affected file has not been +touched for more than one year and is maintained by a single individual, it is +likely that usage has declined and exposed users are virtually non-existent +(e.g., drivers for very old hardware, obsolete filesystems). In such cases, +there is no need to consume a maintainer's time with an unimportant report. If +the issue is clearly trivial and publicly discoverable, you should report it +directly to the public mailing lists. + Sending the report ------------------ @@ -148,7 +242,15 @@ run additional tests. Reports where the reporter does not respond promptly or cannot effectively discuss their findings may be abandoned if the communication does not quickly improve. -The report must be sent to maintainers, with the security team in ``Cc:``. +The report must be sent to maintainers. If there are two or fewer +recipients in your message, you must also always Cc: the Linux kernel +security team who will ensure the message is delivered to the proper +people, and will be able to assist small maintainer teams with processes +they may not be familiar with. For larger teams, Cc: the Linux kernel +security team for your first few reports or when seeking specific help, +such as when resending a message which got no response within a week. +Once you have become comfortable with the process for a few reports, it is +no longer necessary to Cc: the security list when sending to large teams. The Linux kernel security team can be contacted by email at . This is a private list of security officers who will help verify the bug report and assist developers working on a fix. diff --git a/Documentation/process/threat-model.rst b/Documentation/process/threat-model.rst new file mode 100644 index 000000000000..f177b8d3c1ca --- /dev/null +++ b/Documentation/process/threat-model.rst @@ -0,0 +1,235 @@ +The Linux Kernel threat model +============================= + +There are a lot of assumptions regarding what the kernel does and does not +protect against. These assumptions tend to cause confusion for bug reports +(:doc:`security-related ones ` vs :doc:`non-security ones +<../admin-guide/reporting-issues>`), and can complicate security enforcement +when the responsibilities for some boundaries is not clear between the kernel, +distros, administrators and users. + +This document tries to clarify the responsibilities of the kernel in this +domain. + +The kernel's responsibilities +----------------------------- + +The kernel abstracts access to local hardware resources and to remote systems +in a way that allows multiple local users to get a fair share of the available +resources granted to them, and, when the underlying hardware permits, to assign +a level of confidentiality to their communications and to the data they are +processing or storing. + +The kernel assumes that the underlying hardware behaves according to its +specifications. This includes the integrity of the CPU's instruction set, the +transparency of the branch prediction unit and the cache units, the consistency +of the Memory Management Unit (MMU), the isolation of DMA-capable peripherals +(e.g., via IOMMU), state transitions in controllers, ranges of values read from +registers, the respect of documented hardware limitations, etc. + +When hardware fails to maintain its specified isolation (e.g., CPU bugs, +side-channels, hardware response to unexpected inputs), the kernel will usually +attempt to implement reasonable mitigations. These are best-effort measures +intended to reduce the attack surface or elevate the cost of an attack within +the limits of the hardware's facilities; they do not constitute a +kernel-provided safety guarantee. + +Users always perform their activities under the authority of an administrator +who is able to grant or deny various types of permissions that may affect how +users benefit from available resources, or the level of confidentiality of +their activities. Administrators may also delegate all or part of their own +permissions to some users, particularly via capabilities but not only. All this +is performed via configuration (sysctl, file-system permissions etc). + +The Linux Kernel applies a certain collection of default settings that match +its threat model. Distros have their own threat model and will come with their +own configuration presets, that the administrator may have to adjust to better +suit their expectations (relax or restrict). + +By default, the Linux Kernel guarantees the following protections when running +on common processors featuring privilege levels and memory management units: + +* **User-based isolation**: an unprivileged user may restrict access to their + own data from other unprivileged users running on the same system. This + includes: + + * stored data, via file system permissions + * in-memory data (pages are not accessible by default to other users) + * process activity (ptrace is not permitted to other users) + * inter-process communication (other users may not observe data exchanged via + UNIX domain sockets or other IPC mechanisms). + * network communications within the same or with other systems + +* **Capability-based protection**: + + * users not having elevated capabilities (including but not limited to + CAP_SYS_ADMIN) may not alter the + kernel's configuration, memory nor state, change other users' view of the + file system layout, grant any user capabilities they do not have, nor + affect the system's availability (shutdown, reboot, panic, hang, or making + the system unresponsive via unbounded resource exhaustion). + * users not having the ``CAP_NET_ADMIN`` capability may not alter the network + configuration, intercept nor spoof network communications from other users + nor systems. + * users not having ``CAP_SYS_PTRACE`` may not observe other users' processes + activities. + +When ``CONFIG_USER_NS`` is set, the kernel also permits unprivileged users to +create their own user namespace in which they have all capabilities, but with a +number of restrictions (they may not perform actions that have impacts on the +initial user namespace, such as changing time, loading modules or mounting +block devices). Please refer to ``user_namespaces(7)`` for more details, the +possibilities of user namespaces are not covered in this document. + +The kernel also offers a lot of troubleshooting and debugging facilities, which +can constitute attack vectors when placed in wrong hands. While some of them +are designed to be accessible to regular local users with a low risk (e.g. +kernel logs via ``/proc/kmsg``), some would expose enough information to +represent a risk in most places and the decision to expose them is under the +administrator's responsibility (perf events, traces), and others are not +designed to be accessed by non-privileged users (e.g. debugfs). Access to these +facilities by a user who has been explicitly granted permission by an +administrator does not constitute a security breach. + +Bugs that permit to violate the principles above constitute security breaches. +However, bugs that permit one violation only once another one was already +achieved are only weaknesses. The kernel applies a number of self-protection +measures whose purpose is to avoid crossing a security boundary when certain +classes of bugs are found, but a failure of these extra protections do not +constitute a vulnerability alone. + +What does not constitute a security bug +--------------------------------------- + +In the Linux kernel's threat model, the following classes of problems are +**NOT** considered as Linux Kernel security bugs. However, when it is believed +that the kernel could do better, they should be reported, so that they can be +reviewed and fixed where reasonably possible, but they will be handled as any +regular bug: + +* **Configuration**: + + * outdated kernels and particularly end-of-life branches are out of the scope + of the kernel's threat model: administrators are responsible for keeping + their system up to date. For a bug to qualify as a security bug, it must be + demonstrated that it affects actively maintained versions. + + * build-level: changes to the kernel configuration that are explicitly + documented as lowering the security level (e.g. ``CONFIG_NOMMU``), or + targeted at developers only. + + * OS-level: changes to command line parameters, sysctls, filesystem + permissions, user capabilities, exposure of privileged interfaces, that + explicitly increase exposure by either offering non-default access to + unprivileged users, or reduce the kernel's ability to enforce some + protections or mitigations. Example: write access to procfs or debugfs. + + * issues triggered only when using features intended for development or + debugging (e.g., LOCKDEP, KASAN, FAULT_INJECTION): these features are known + to introduce overhead and potential instability and are not intended for + production use. + + * issues affecting drivers exposed under CONFIG_STAGING, as well as features + marked EXPERIMENTAL in the configuration. + + * loading of explicitly insecure/broken/staging modules, and generally any + using any subsystem marked as experimental or not intended for production + use. + + * running out-of-tree modules or unofficial kernel forks; these should be + reported to the relevant vendor. + +* **Excess of initial privileges**: + + * actions performed by a user already possessing the privileges required to + perform that action or modify that state (e.g. ``CAP_SYS_ADMIN``, + ``CAP_NET_ADMIN``, ``CAP_SYS_RAWIO``, ``CAP_SYS_MODULE`` with no further + boundary being crossed). + + * actions performed in user namespace that do not bypass the restrictions + imposed to the initial user (e.g. ptrace usage, signal delivery, resource + usage, access to FS/device/sysctl/memory, network binding, system/network + configuration etc). + + * anything performed by the root user in the initial namespace (e.g. kernel + oops when writing to a privileged device). + +* **Out of production use**: + + This covers theoretical/probabilistic attacks that rely on laboratory + conditions with zero system noise, or those requiring an unrealistic number + of attempts (e.g., billions of trials) that would be detected by standard + system monitoring long before success, such as: + + * prediction of random numbers that only works in a totally silent + environment (such as IP ID, TCP ports or sequence numbers that can only be + guessed in a lab). + + * activity observation and information leaks based on probabilistic + approaches that are prone to measurement noise and not realistically + reproducible on a production system. + + * issues that can only be triggered by heavy attacks (e.g. brute force) whose + impact on the system makes it unlikely or impossible to remain undetected + before they succeed (e.g. consuming all memory before succeeding). + + * problems seen only under development simulators, emulators, or combinations + that do not exist on real systems at the time of reporting (issues + involving tens of millions of threads, tens of thousands of CPUs, + unrealistic CPU frequencies, RAM sizes or disk capacities, network speeds. + + * issues whose reproduction requires hardware modification or emulation, + including fake USB devices that pretend to be another one. + + * as well as issues that can be triggered at a cost that is orders of + magnitude higher than the expected benefits (e.g. fully functional keyboard + emulator only to retrieve 7 uninitialized bytes in a structure, or + brute-force method involving millions of connection attempts to guess a + port number). + +* **Hardening failures**: + + * ability to bypass some of the kernel's hardening measures with no + demonstrable exploit path (e.g. ASLR bypass, events timing or probing with + no demonstrable consequence). These are just weaknesses, not + vulnerabilities. + + * missing argument checks and failure to report certain errors with no + immediate consequence. + +* **Random information leaks**: + + This concerns information leaks of small data parts that happen to be there + and that cannot be chosen by the attacker, or face access restrictions: + + * structure padding reported by syscalls or other interfaces. + + * identifiers, partial data, non-terminated strings reported in error + messages. + + * Leaks of kernel memory addresses/pointers do not constitute an immediately + exploitable vector and are not security bugs, though they must be reported + and fixed. + +* **Crafted file system images**: + + * bugs triggered by mounting a corrupted or maliciously crafted file system + image are generally not security bugs, as the kernel assumes the underlying + storage media is under the administrator's control, unless the filesystem + driver is specifically documented as being hardened against untrusted media. + + * issues that are resolved, mitigated, or detected by running a filesystem + consistency check (fsck) on the image prior to mounting. + +* **Physical access**: + + Issues that require physical access to the machine, hardware modification, or + the use of specialized hardware (e.g., logic analyzers, DMA-attack tools over + PCI-E/Thunderbolt) are out of scope unless the system is explicitly + configured with technologies meant to defend against such attacks + (e.g. IOMMU). + +* **Functional and performance regressions**: + + Any issue that can be mitigated by setting proper permissions and limits + doesn't qualify as a security bug. diff --git a/Documentation/sound/codecs/cs35l56.rst b/Documentation/sound/codecs/cs35l56.rst index d5363b08f515..b3f8c1c23851 100644 --- a/Documentation/sound/codecs/cs35l56.rst +++ b/Documentation/sound/codecs/cs35l56.rst @@ -40,7 +40,7 @@ There are two drivers in the kernel *For systems using SoundWire*: sound/soc/codecs/cs35l56.c and associated files -*For systems using HDA*: sound/pci/hda/cs35l56_hda.c +*For systems using HDA*: sound/hda/codecs/side-codecs/cs35l56_hda.c Firmware ======== diff --git a/Documentation/userspace-api/rseq.rst b/Documentation/userspace-api/rseq.rst index 3cd27a3c7c7e..8549a6c61531 100644 --- a/Documentation/userspace-api/rseq.rst +++ b/Documentation/userspace-api/rseq.rst @@ -24,6 +24,97 @@ Quick access to CPU number, node ID Allows to implement per CPU data efficiently. Documentation is in code and selftests. :( +Optimized RSEQ V2 +----------------- + +On architectures which utilize the generic entry code and generic TIF bits +the kernel supports runtime optimizations for RSEQ, which also enable +enhanced features like scheduler time slice extensions. + +To enable them a task has to register the RSEQ region with at least the +length advertised by getauxval(AT_RSEQ_FEATURE_SIZE). + +If existing binaries register with RSEQ_ORIG_SIZE (32 bytes), the kernel +keeps the legacy low performance mode enabled to fulfil the expectations +of existing users regarding the original RSEQ implementation behaviour. + +The following table documents the ABI and behavioral guarantees of the +legacy and the optimized V2 mode. + +.. list-table:: RSEQ modes + :header-rows: 1 + + * - Nr + - What + + - Legacy + - Optimized V2 + + * - 1 + - The cpu_id_start, cpu_id, node_id and mm_cid fields (User mode read + only) + .. Legacy + - Updated by the kernel unconditionally after each context switch and + before signal delivery + .. Optimized V2 + - Updated by the kernel if and only if they change, i.e. if the task + is migrated or mm_cid changes + + * - 2 + - The rseq_cs critical section field + .. Legacy + - Evaluated and handled unconditionally after each context switch and + before signal delivery + .. Optimized V2 + - Evaluated and handled conditionally only when user space was + interrupted and was scheduled out or before delivering a signal in + the interrupted context. + + * - 3 + - Read only fields + .. Legacy + - No strict enforcement except in debug mode + .. Optimized V2 + - Strict enforcement + + * - 4 + - membarrier(...RSEQ) + .. Legacy + - All running threads of the process are interrupted and the ID fields + are rewritten and eventually active critical sections are aborted + before they return to user space. All threads which are scheduled + out whether voluntary or not are covered by #1/#2 above. + .. Optimized V2 + - All running threads of the process are interrupted and eventually + active critical sections are aborted before these threads return to + user space. The ID fields are only updated if changed as a + consequence of the interrupt. All threads which are scheduled out + whether voluntary or not are covered by #1/#2 above. + + * - 5 + - Time slice extensions + .. Legacy + - Not supported + .. Optimized V2 + - Supported + +The legacy mode is obviously less performant as it does unconditional +updates and critical section checks even if not strictly required by the +ABI contract. That can't be changed anymore as some users depend on that +observed behavior, which in turn enables them to violate the ABI and +overwrite the cpu_id_start field for their own purposes. This is obviously +discouraged as it renders RSEQ incompatible with the intended usage and +breaks the expectation of other libraries in the same application. + +The ABI compliant optimized v2 mode, which respects the read only fields, +does not require unconditional updates and therefore is way more +performant. The kernel validates the read only fields for compliance. If +user space modifies them, the process is killed. Compliant usage allows +multiple libraries in the same application to benefit from the RSEQ +functionality without disturbing each other. The ABI compliant optimized v2 +mode also enables extended RSEQ features like time slice extensions. + + Scheduler time slice extensions ------------------------------- @@ -37,7 +128,8 @@ The prerequisites for this functionality are: * Enabled at boot time (default is enabled) - * A rseq userspace pointer has been registered for the thread + * A rseq userspace pointer has been registered for the thread in + optimized V2 mode The thread has to enable the functionality via prctl(2):: diff --git a/Documentation/virt/kvm/x86/amd-memory-encryption.rst b/Documentation/virt/kvm/x86/amd-memory-encryption.rst index b2395dd4769d..bd04a908a8db 100644 --- a/Documentation/virt/kvm/x86/amd-memory-encryption.rst +++ b/Documentation/virt/kvm/x86/amd-memory-encryption.rst @@ -656,8 +656,8 @@ References See [white-paper]_, [api-spec]_, [amd-apm]_, [kvm-forum]_, and [snp-fw-abi]_ for more info. -.. [white-paper] https://developer.amd.com/wordpress/media/2013/12/AMD_Memory_Encryption_Whitepaper_v7-Public.pdf -.. [api-spec] https://support.amd.com/TechDocs/55766_SEV-KM_API_Specification.pdf -.. [amd-apm] https://support.amd.com/TechDocs/24593.pdf (section 15.34) +.. [white-paper] https://docs.amd.com/v/u/en-US/memory-encryption-white-paper +.. [api-spec] https://docs.amd.com/v/u/en-US/55766_PUB_3.24_SEV_API +.. [amd-apm] https://docs.amd.com/v/u/en-US/24593_3.44_APM_Vol2 (section 15.34) .. [kvm-forum] https://www.linux-kvm.org/images/7/74/02x08A-Thomas_Lendacky-AMDs_Virtualizatoin_Memory_Encryption_Technology.pdf -.. [snp-fw-abi] https://www.amd.com/system/files/TechDocs/56860.pdf +.. [snp-fw-abi] https://www.amd.com/content/dam/amd/en/documents/developer/56860.pdf diff --git a/MAINTAINERS b/MAINTAINERS index fb335dc25f43..4ae6919454c3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -68,6 +68,12 @@ Maintainers List first. When adding to this list, please keep the entries in alphabetical order. +3C509 NETWORK DRIVER +M: "Maciej W. Rozycki" +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/3com/3c509.c + 3C59X NETWORK DRIVER M: Steffen Klassert L: netdev@vger.kernel.org @@ -2015,7 +2021,7 @@ F: Documentation/hwmon/aquacomputer_d5next.rst F: drivers/hwmon/aquacomputer_d5next.c AQUANTIA ETHERNET DRIVER (atlantic) -M: Igor Russkikh +M: Sukhdeep Singh L: netdev@vger.kernel.org S: Maintained W: https://www.marvell.com/ @@ -2024,7 +2030,7 @@ F: Documentation/networking/device_drivers/ethernet/aquantia/atlantic.rst F: drivers/net/ethernet/aquantia/atlantic/ AQUANTIA ETHERNET DRIVER PTP SUBSYSTEM -M: Egor Pomozov +M: Sukhdeep Singh L: netdev@vger.kernel.org S: Maintained W: http://www.aquantia.com @@ -2058,7 +2064,7 @@ F: Documentation/devicetree/bindings/display/snps,arcpgu.txt F: drivers/gpu/drm/tiny/arcpgu.c ARCNET NETWORK LAYER -M: Michael Grzeschik +M: Michael Grzeschik L: netdev@vger.kernel.org S: Maintained F: drivers/net/arcnet/ @@ -3361,7 +3367,9 @@ F: drivers/irqchip/irq-rda-intc.c F: drivers/tty/serial/rda-uart.c ARM/REALTEK ARCHITECTURE -M: Andreas Färber +M: James Tai +M: Yu-Chun Lin +R: Andreas Färber L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-realtek-soc@lists.infradead.org (moderated for non-subscribers) S: Maintained @@ -3369,6 +3377,7 @@ F: Documentation/devicetree/bindings/arm/realtek.yaml F: arch/arm/boot/dts/realtek/ F: arch/arm/mach-realtek/ F: arch/arm64/boot/dts/realtek/ +F: drivers/pinctrl/realtek/ ARM/RISC-V/RENESAS ARCHITECTURE M: Geert Uytterhoeven @@ -4181,8 +4190,8 @@ F: include/uapi/linux/sonet.h F: net/atm/ ATMEL MACB ETHERNET DRIVER -M: Nicolas Ferre -M: Claudiu Beznea +M: Théo Lebrun +R: Conor Dooley S: Maintained F: drivers/net/ethernet/cadence/ @@ -4299,18 +4308,16 @@ F: Documentation/devicetree/bindings/leds/backlight/awinic,aw99706.yaml F: drivers/video/backlight/aw99706.c AXENTIA ARM DEVICES -M: Peter Rosin L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained +S: Orphan F: arch/arm/boot/dts/microchip/at91-linea.dtsi F: arch/arm/boot/dts/microchip/at91-natte.dtsi F: arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts F: arch/arm/boot/dts/microchip/at91-tse850-3.dts AXENTIA ASOC DRIVERS -M: Peter Rosin L: linux-sound@vger.kernel.org -S: Maintained +S: Orphan F: Documentation/devicetree/bindings/sound/axentia,* F: sound/soc/atmel/tse850-pcm5142.c @@ -6358,6 +6365,7 @@ F: include/uapi/linux/comedi.h COMMON CLK FRAMEWORK M: Michael Turquette M: Stephen Boyd +R: Brian Masney L: linux-clk@vger.kernel.org S: Maintained Q: http://patchwork.kernel.org/project/linux-clk/list/ @@ -7077,6 +7085,12 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git core/debugobjec F: include/linux/debugobjects.h F: lib/debugobjects.c +DEC LANCE NETWORK DRIVER +M: "Maciej W. Rozycki" +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/amd/declance.c + DECSTATION PLATFORM SUPPORT M: "Maciej W. Rozycki" L: linux-mips@vger.kernel.org @@ -7835,11 +7849,13 @@ F: drivers/soc/ti/smartreflex.c F: include/linux/power/smartreflex.h DRM ACCEL DRIVERS FOR INTEL VPU -M: Maciej Falkowski M: Karol Wachowski +M: Andrzej Kacprowski L: dri-devel@lists.freedesktop.org S: Supported T: git https://gitlab.freedesktop.org/drm/misc/kernel.git +F: Documentation/ABI/obsolete/sysfs-driver-ivpu +F: Documentation/ABI/testing/sysfs-driver-ivpu F: drivers/accel/ivpu/ F: include/uapi/drm/ivpu_accel.h @@ -7873,7 +7889,7 @@ F: drivers/gpu/drm/sun4i/sun8i* DRM DRIVER FOR APPLE TOUCH BARS M: Aun-Ali Zaidi -M: Aditya Garg +M: Aditya Garg L: dri-devel@lists.freedesktop.org S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git @@ -8148,6 +8164,12 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml F: drivers/gpu/drm/panel/panel-novatek-nt35510.c +DRM DRIVER FOR NOVATEK NT35532 PANELS +M: Cristian Cozzolino +S: Maintained +F: Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml +F: drivers/gpu/drm/panel/panel-novatek-nt35532.c + DRM DRIVER FOR NOVATEK NT35560 PANELS M: Linus Walleij S: Maintained @@ -8556,6 +8578,7 @@ M: Robert Foss R: Laurent Pinchart R: Jonas Karlman R: Jernej Skrabec +R: Luca Ceresoli S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/bridge/ @@ -12046,7 +12069,7 @@ F: Documentation/i2c/busses/i2c-nvidia-gpu.rst F: drivers/i2c/busses/i2c-nvidia-gpu.c I2C MUXES -M: Peter Rosin +M: Peter Rosin L: linux-i2c@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/i2c/i2c-arb* @@ -12447,7 +12470,7 @@ F: drivers/iio/industrialio-backend.c F: include/linux/iio/backend.h IIO DIGITAL POTENTIOMETER DAC -M: Peter Rosin +M: Peter Rosin L: linux-iio@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-bus-iio-dac-dpot-dac @@ -12455,7 +12478,7 @@ F: Documentation/devicetree/bindings/iio/dac/dpot-dac.yaml F: drivers/iio/dac/dpot-dac.c IIO ENVELOPE DETECTOR -M: Peter Rosin +M: Peter Rosin L: linux-iio@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-bus-iio-adc-envelope-detector @@ -12471,7 +12494,7 @@ F: include/linux/iio/iio-gts-helper.h F: drivers/iio/test/iio-test-gts.c IIO MULTIPLEXER -M: Peter Rosin +M: Peter Rosin L: linux-iio@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.yaml @@ -12502,7 +12525,7 @@ F: include/linux/iio/ F: tools/iio/ IIO UNIT CONVERTER -M: Peter Rosin +M: Peter Rosin L: linux-iio@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/iio/afe/current-sense-amplifier.yaml @@ -12779,7 +12802,6 @@ M: Cezary Rojewski M: Liam Girdwood M: Peter Ujfalusi M: Bard Liao -M: Ranjani Sridharan M: Kai Vehmanen R: Pierre-Louis Bossart L: linux-sound@vger.kernel.org @@ -13860,7 +13882,7 @@ M: Pratyush Yadav R: Dave Young L: kexec@lists.infradead.org S: Maintained -W: http://lse.sourceforge.net/kdump/ +T: git git://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git F: Documentation/admin-guide/kdump/ F: fs/proc/vmcore.c F: include/linux/crash_core.h @@ -14053,6 +14075,7 @@ KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64) M: Marc Zyngier M: Oliver Upton R: Joey Gouly +R: Steffen Eiden R: Suzuki K Poulose R: Zenghui Yu L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -14177,6 +14200,7 @@ M: Pasha Tatashin M: Pratyush Yadav L: kexec@lists.infradead.org W: http://kernel.org/pub/linux/utils/kernel/kexec/ +T: git git://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git F: include/linux/kexec.h F: include/uapi/linux/kexec.h F: kernel/kexec* @@ -14893,6 +14917,7 @@ LIVE UPDATE M: Pasha Tatashin M: Mike Rapoport M: Pratyush Yadav +L: kexec@lists.infradead.org L: linux-kernel@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git @@ -15019,7 +15044,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git F: drivers/hid/hid-lg-g15.c LONTIUM LT8912B MIPI TO HDMI BRIDGE -M: Adrien Grassein +M: Francesco Dolcini S: Maintained F: Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml F: drivers/gpu/drm/bridge/lontium-lt8912b.c @@ -15252,7 +15277,7 @@ M: Andrea Cervesato M: Cyril Hrubis M: Jan Stancek M: Petr Vorel -M: Li Wang +M: Li Wang M: Yang Xu M: Xiao Yang L: ltp@lists.linux.it (subscribers-only) @@ -15399,7 +15424,7 @@ F: include/net/netns/mctp.h F: net/mctp/ MAPLE TREE -M: Liam R. Howlett +M: Liam R. Howlett R: Alice Ryhl R: Andrew Ballance L: maple-tree@lists.infradead.org @@ -15719,7 +15744,7 @@ F: Documentation/devicetree/bindings/media/i2c/maxim,max96717.yaml F: drivers/media/i2c/max96717.c MAX9860 MONO AUDIO VOICE CODEC DRIVER -M: Peter Rosin +M: Peter Rosin L: linux-sound@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/sound/max9860.txt @@ -15934,7 +15959,7 @@ F: Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml F: drivers/net/can/spi/mcp251xfd/ MCP4018 AND MCP4531 MICROCHIP DIGITAL POTENTIOMETER DRIVERS -M: Peter Rosin +M: Peter Rosin L: linux-iio@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-bus-iio-potentiometer-mcp4531 @@ -16759,7 +16784,7 @@ MEMORY MANAGEMENT - CORE M: Andrew Morton M: David Hildenbrand R: Lorenzo Stoakes -R: Liam R. Howlett +R: Liam R. Howlett R: Vlastimil Babka R: Mike Rapoport R: Suren Baghdasaryan @@ -16805,7 +16830,7 @@ F: mm/sparse.c F: mm/util.c F: mm/vmpressure.c F: mm/vmstat.c -N: include/linux/page[-_]* +N: include\/linux\/page[-_][a-zA-Z]* MEMORY MANAGEMENT - EXECMEM M: Andrew Morton @@ -16895,7 +16920,7 @@ MEMORY MANAGEMENT - MISC M: Andrew Morton M: David Hildenbrand R: Lorenzo Stoakes -R: Liam R. Howlett +R: Liam R. Howlett R: Vlastimil Babka R: Mike Rapoport R: Suren Baghdasaryan @@ -16962,6 +16987,7 @@ S: Maintained F: include/linux/compaction.h F: include/linux/gfp.h F: include/linux/page-isolation.h +F: include/linux/pageblock-flags.h F: mm/compaction.c F: mm/debug_page_alloc.c F: mm/debug_page_ref.c @@ -16983,7 +17009,7 @@ M: Andrew Morton M: Johannes Weiner R: David Hildenbrand R: Michal Hocko -R: Qi Zheng +R: Qi Zheng R: Shakeel Butt R: Lorenzo Stoakes L: linux-mm@kvack.org @@ -16996,7 +17022,7 @@ M: Andrew Morton M: David Hildenbrand M: Lorenzo Stoakes R: Rik van Riel -R: Liam R. Howlett +R: Liam R. Howlett R: Vlastimil Babka R: Harry Yoo R: Jann Horn @@ -17043,7 +17069,7 @@ M: David Hildenbrand M: Lorenzo Stoakes R: Zi Yan R: Baolin Wang -R: Liam R. Howlett +R: Liam R. Howlett R: Nico Pache R: Ryan Roberts R: Dev Jain @@ -17081,7 +17107,7 @@ F: tools/testing/selftests/mm/uffd-*.[ch] MEMORY MANAGEMENT - RUST M: Alice Ryhl R: Lorenzo Stoakes -R: Liam R. Howlett +R: Liam R. Howlett L: linux-mm@kvack.org L: rust-for-linux@vger.kernel.org S: Maintained @@ -17095,7 +17121,7 @@ F: rust/kernel/page.rs MEMORY MAPPING M: Andrew Morton -M: Liam R. Howlett +M: Liam R. Howlett M: Lorenzo Stoakes R: Vlastimil Babka R: Jann Horn @@ -17127,7 +17153,7 @@ F: tools/testing/vma/ MEMORY MAPPING - LOCKING M: Andrew Morton M: Suren Baghdasaryan -M: Liam R. Howlett +M: Liam R. Howlett M: Lorenzo Stoakes R: Vlastimil Babka R: Shakeel Butt @@ -17142,7 +17168,7 @@ F: mm/mmap_lock.c MEMORY MAPPING - MADVISE (MEMORY ADVICE) M: Andrew Morton -M: Liam R. Howlett +M: Liam R. Howlett M: Lorenzo Stoakes M: David Hildenbrand R: Vlastimil Babka @@ -18238,7 +18264,7 @@ F: include/linux/mmc/ F: include/uapi/linux/mmc/ MULTIPLEXER SUBSYSTEM -M: Peter Rosin +M: Peter Rosin S: Odd Fixes F: Documentation/ABI/testing/sysfs-class-mux* F: Documentation/devicetree/bindings/mux/ @@ -18622,6 +18648,7 @@ F: tools/testing/selftests/net/ X: Documentation/networking/mac80211-injection.rst X: Documentation/networking/mac80211_hwsim/ X: Documentation/networking/regulatory.rst +X: include/net/bluetooth/ X: include/net/cfg80211.h X: include/net/ieee80211_radiotap.h X: include/net/iw_handler.h @@ -18672,19 +18699,59 @@ F: net/xfrm/ F: tools/testing/selftests/net/ipsec.c NETWORKING [IPv4/IPv6] -M: "David S. Miller" M: David Ahern +M: Ido Schimmel L: netdev@vger.kernel.org S: Maintained -T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git -F: arch/x86/net/* -F: include/linux/ip.h -F: include/linux/ipv6* +F: Documentation/netlink/specs/rt-addr.yaml +F: Documentation/netlink/specs/rt-neigh.yaml +F: Documentation/netlink/specs/rt-route.yaml +F: Documentation/netlink/specs/rt-rule.yaml +F: include/linux/inetdevice.h +F: include/linux/mroute* +F: include/net/addrconf.h +F: include/net/arp.h F: include/net/fib* +F: include/net/if_inet6.h +F: include/net/inetpeer.h F: include/net/ip* +F: include/net/lwtunnel.h +F: include/net/ndisc.h +F: include/net/netns/nexthop.h +F: include/net/nexthop.h F: include/net/route.h -F: net/ipv4/ -F: net/ipv6/ +F: include/uapi/linux/fib_rules.h +F: include/uapi/linux/in_route.h +F: include/uapi/linux/mroute* +F: include/uapi/linux/nexthop.h +F: net/core/fib* +F: net/core/lwtunnel.c +F: net/ipv4/arp.c +F: net/ipv4/devinet.c +F: net/ipv4/fib* +F: net/ipv4/icmp.c +F: net/ipv4/igmp.c +F: net/ipv4/inet_fragment.c +F: net/ipv4/inetpeer.c +F: net/ipv4/ip* +F: net/ipv4/metrics.c +F: net/ipv4/netlink.c +F: net/ipv4/nexthop.c +F: net/ipv4/route.c +F: net/ipv6/addr* +F: net/ipv6/anycast.c +F: net/ipv6/exthdrs.c +F: net/ipv6/exthdrs_core.c +F: net/ipv6/fib* +F: net/ipv6/icmp.c +F: net/ipv6/ip* +F: net/ipv6/mcast* +F: net/ipv6/ndisc.c +F: net/ipv6/output_core.c +F: net/ipv6/reassembly.c +F: net/ipv6/route.c +F: tools/testing/selftests/net/fib* +F: tools/testing/selftests/net/forwarding/ NETWORKING [LABELED] (NetLabel, Labeled IPsec, SECMARK) M: Paul Moore @@ -18819,18 +18886,11 @@ F: Documentation/networking/net_failover.rst F: drivers/net/net_failover.c F: include/net/net_failover.h -NEXTHOP -M: David Ahern -L: netdev@vger.kernel.org -S: Maintained -F: include/net/netns/nexthop.h -F: include/net/nexthop.h -F: include/uapi/linux/nexthop.h -F: net/ipv4/nexthop.c - NFC SUBSYSTEM -L: netdev@vger.kernel.org -S: Orphan +M: David Heidelberg +L: oe-linux-nfc@lists.linux.dev +S: Maintained +T: git https://codeberg.org/linux-nfc/linux.git F: Documentation/devicetree/bindings/net/nfc/ F: drivers/nfc/ F: include/net/nfc/ @@ -18898,7 +18958,8 @@ F: drivers/hid/hid-nintendo* NIOS2 ARCHITECTURE M: Dinh Nguyen -S: Maintained +M: Simon Schuster +S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git F: arch/nios2/ @@ -19314,7 +19375,7 @@ F: include/dt-bindings/display/tda998x.h K: "nxp,tda998x" NXP TFA9879 DRIVER -M: Peter Rosin +M: Peter Rosin L: linux-sound@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/sound/trivial-codec.yaml @@ -19412,7 +19473,6 @@ F: include/misc/ocxl* F: include/uapi/misc/ocxl.h OMAP AUDIO SUPPORT -M: Peter Ujfalusi M: Jarkko Nikula L: linux-sound@vger.kernel.org L: linux-omap@vger.kernel.org @@ -20315,13 +20375,14 @@ F: Documentation/devicetree/bindings/pci/marvell,armada8k-pcie.yaml F: drivers/pci/controller/dwc/pcie-armada8k.c PCI DRIVER FOR CADENCE PCIE IP +R: Aksh Garg L: linux-pci@vger.kernel.org S: Orphan F: Documentation/devicetree/bindings/pci/cdns,* -F: drivers/pci/controller/cadence/*cadence* +F: drivers/pci/controller/cadence/ PCI DRIVER FOR CIX Sky1 -M: Hans Zhang +M: Hans Zhang <18255117159@163.com> L: linux-pci@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pci/cix,sky1-pcie-*.yaml @@ -20433,7 +20494,7 @@ F: drivers/pci/controller/plda/pcie-plda-host.c F: drivers/pci/controller/plda/pcie-plda.h PCI DRIVER FOR RENESAS R-CAR -M: Marek Vasut +M: Marek Vasut M: Yoshihiro Shimoda L: linux-pci@vger.kernel.org L: linux-renesas-soc@vger.kernel.org @@ -20693,15 +20754,13 @@ F: Documentation/devicetree/bindings/pci/intel,keembay-pcie* F: drivers/pci/controller/dwc/pcie-keembay.c PCIE DRIVER FOR INTEL LGM GW SOC -M: Chuanhua Lei L: linux-pci@vger.kernel.org -S: Maintained +S: Orphan F: Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml F: drivers/pci/controller/dwc/pcie-intel-gw.c PCIE DRIVER FOR MEDIATEK M: Ryder Lee -M: Jianjun Wang L: linux-pci@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Supported @@ -20774,6 +20833,7 @@ M: Dominik Brodowski S: Odd Fixes T: git git://git.kernel.org/pub/scm/linux/kernel/git/brodo/linux.git F: Documentation/pcmcia/ +F: drivers/net/ethernet/8390/pcnet_cs.c F: drivers/pcmcia/ F: include/pcmcia/ F: tools/pcmcia/ @@ -22906,7 +22966,7 @@ N: riscv K: riscv RISC-V IOMMU -M: Tomasz Jeznach +M: Tomasz Jeznach L: iommu@lists.linux.dev L: linux-riscv@lists.infradead.org S: Maintained @@ -23369,7 +23429,7 @@ RUST [ALLOC] M: Danilo Krummrich R: Lorenzo Stoakes R: Vlastimil Babka -R: Liam R. Howlett +R: Liam R. Howlett R: Uladzislau Rezki L: rust-for-linux@vger.kernel.org S: Maintained @@ -23521,7 +23581,7 @@ F: drivers/s390/net/ S390 PCI SUBSYSTEM M: Niklas Schnelle -M: Gerald Schaefer +M: Gerd Bayer L: linux-s390@vger.kernel.org S: Supported F: Documentation/arch/s390/pci.rst @@ -24314,7 +24374,7 @@ F: include/media/i2c/rj54n1cb0c.h SHRINKER M: Andrew Morton M: Dave Chinner -R: Qi Zheng +R: Qi Zheng R: Roman Gushchin R: Muchun Song L: linux-mm@kvack.org @@ -24616,6 +24676,7 @@ S: Maintained F: fs/smb/client/smbdirect.* F: fs/smb/smbdirect/ F: fs/smb/server/transport_rdma.* +F: include/linux/smbdirect.h SMC91x ETHERNET DRIVER M: Nicolas Pitre @@ -24764,6 +24825,7 @@ SOFTWARE RAID (Multiple Disks) SUPPORT M: Song Liu M: Yu Kuai R: Li Nan +R: Xiao Ni L: linux-raid@vger.kernel.org S: Supported Q: https://patchwork.kernel.org/project/linux-raid/list/ @@ -25018,7 +25080,6 @@ SOUND - SOUND OPEN FIRMWARE (SOF) DRIVERS M: Liam Girdwood M: Peter Ujfalusi M: Bard Liao -M: Ranjani Sridharan M: Daniel Baluta R: Kai Vehmanen R: Pierre-Louis Bossart @@ -26311,7 +26372,7 @@ F: arch/xtensa/ F: drivers/irqchip/irq-xtensa-* TEXAS INSTRUMENTS ASoC DRIVERS -M: Peter Ujfalusi +M: Sen Wang L: linux-sound@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml @@ -26813,12 +26874,6 @@ S: Maintained F: Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml F: drivers/iio/adc/ti-tsc2046.c -TI TWL4030 SERIES SOC CODEC DRIVER -M: Peter Ujfalusi -L: linux-sound@vger.kernel.org -S: Maintained -F: sound/soc/codecs/twl4030* - TI VPE/CAL DRIVERS M: Yemike Abhilash Chandra L: linux-media@vger.kernel.org diff --git a/Makefile b/Makefile index e27c91ea56fc..f056c921ea9c 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ VERSION = 7 PATCHLEVEL = 1 SUBLEVEL = 0 -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc5 NAME = Baby Opossum Posse # *DOCUMENTATION* @@ -486,6 +486,8 @@ export rust_common_flags := --edition=2021 \ -Wclippy::as_ptr_cast_mut \ -Wclippy::as_underscore \ -Wclippy::cast_lossless \ + -Aclippy::collapsible_if \ + -Aclippy::collapsible_match \ -Wclippy::ignored_unit_patterns \ -Aclippy::incompatible_msrv \ -Wclippy::mut_mut \ diff --git a/arch/alpha/include/asm/Kbuild b/arch/alpha/include/asm/Kbuild index 483965c5a4de..b154b4e3dfa8 100644 --- a/arch/alpha/include/asm/Kbuild +++ b/arch/alpha/include/asm/Kbuild @@ -5,4 +5,5 @@ generic-y += agp.h generic-y += asm-offsets.h generic-y += kvm_para.h generic-y += mcs_spinlock.h +generic-y += ring_buffer.h generic-y += text-patching.h diff --git a/arch/arc/include/asm/Kbuild b/arch/arc/include/asm/Kbuild index 4c69522e0328..483caacc6988 100644 --- a/arch/arc/include/asm/Kbuild +++ b/arch/arc/include/asm/Kbuild @@ -5,5 +5,6 @@ generic-y += extable.h generic-y += kvm_para.h generic-y += mcs_spinlock.h generic-y += parport.h +generic-y += ring_buffer.h generic-y += user.h generic-y += text-patching.h diff --git a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts index 3c3756509714..da552a66615e 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts @@ -34,9 +34,6 @@ flash@18000000 { clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>; power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <1>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts index 91178fb9e721..3306bc9b7bc3 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts @@ -36,8 +36,6 @@ flash@18000000 { power-domains = <&cpg_clocks>; bank-width = <4>; device-width = <1>; - #address-cells = <1>; - #size-cells = <1>; partitions { compatible = "fixed-partitions"; diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi index 245c26bb8e03..6ec57ffa72e8 100644 --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -37,7 +37,7 @@ b_clk: b { clock-div = <3>; }; - bsc: bus { + bsc: bus@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7778.dtsi b/arch/arm/boot/dts/renesas/r8a7778.dtsi index 859dd29dfce3..7db456b19795 100644 --- a/arch/arm/boot/dts/renesas/r8a7778.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7778.dtsi @@ -40,7 +40,7 @@ aliases { spi2 = &hspi2; }; - lbsc: bus { + lbsc: bus@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7779.dtsi b/arch/arm/boot/dts/renesas/r8a7779.dtsi index e437c22f452d..9e8a7e190c89 100644 --- a/arch/arm/boot/dts/renesas/r8a7779.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7779.dtsi @@ -704,7 +704,7 @@ R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 }; }; - lbsc: bus { + lbsc: bus@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index 9e0de69ac3a3..fbdbcff1cbed 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -86,7 +86,7 @@ extal_clk: extal { bootph-all; }; - lbsc: bus { + lbsc: bus@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 03657ff8fbe3..decad5f2c826 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -3,6 +3,7 @@ generic-y += early_ioremap.h generic-y += extable.h generic-y += flat.h generic-y += parport.h +generic-y += ring_buffer.h generated-y += mach-types.h generated-y += unistd-nr.h diff --git a/arch/arm/mach-versatile/integrator_cp.c b/arch/arm/mach-versatile/integrator_cp.c index 2ed4ded56b3f..03dfb5f720b7 100644 --- a/arch/arm/mach-versatile/integrator_cp.c +++ b/arch/arm/mach-versatile/integrator_cp.c @@ -86,14 +86,6 @@ static u64 notrace intcp_read_sched_clock(void) return val; } -static void __init intcp_init_early(void) -{ - cm_map = syscon_regmap_lookup_by_compatible("arm,core-module-integrator"); - if (IS_ERR(cm_map)) - return; - sched_clock_register(intcp_read_sched_clock, 32, 24000000); -} - static void __init intcp_init_irq_of(void) { cm_init(); @@ -119,6 +111,10 @@ static void __init intcp_init_of(void) { struct device_node *cpcon; + cm_map = syscon_regmap_lookup_by_compatible("arm,core-module-integrator"); + if (!IS_ERR(cm_map)) + sched_clock_register(intcp_read_sched_clock, 32, 24000000); + cpcon = of_find_matching_node(NULL, intcp_syscon_match); if (!cpcon) return; @@ -138,7 +134,6 @@ static const char * intcp_dt_board_compat[] = { DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") .reserve = integrator_reserve, .map_io = intcp_map_io, - .init_early = intcp_init_early, .init_irq = intcp_init_irq_of, .init_machine = intcp_init_of, .dt_compat = intcp_dt_board_compat, diff --git a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso index 258f8668ca36..90767d74e21b 100644 --- a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso +++ b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso @@ -27,7 +27,12 @@ &lvds1 { status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + lvds1_out: endpoint { remote-endpoint = <&panel_in>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi index 3e1c98903cea..3ec1b53d2782 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -699,7 +699,7 @@ scif0: serial@c0700000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc0700000 0 0x40>; interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -709,7 +709,7 @@ scif1: serial@c0704000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc0704000 0 0x40>; interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -719,7 +719,7 @@ scif3: serial@c0708000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc0708000 0 0x40>; interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -729,7 +729,7 @@ scif4: serial@c070c000 { "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc070c000 0 0x40>; interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 40525470194e..7ccddd6a4a9a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -1327,6 +1327,7 @@ usb20phyrst: usb20phy-reset@15830000 { resets = <&cpg 0xaf>; power-domains = <&cpg>; #reset-cells = <0>; + #mux-state-cells = <1>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 9581af58024e..6f6fe5f36bef 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1345,6 +1345,7 @@ usb20phyrst: usb20phy-reset@15830000 { resets = <&cpg 0xaf>; power-domains = <&cpg>; #reset-cells = <0>; + #mux-state-cells = <1>; status = "disabled"; }; @@ -1355,6 +1356,7 @@ usb21phyrst: usb21phy-reset@15840000 { resets = <&cpg 0xaf>; power-domains = <&cpg>; #reset-cells = <0>; + #mux-state-cells = <1>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi index 4d2b0655859a..3feffa4f16a9 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi @@ -46,7 +46,12 @@ &csi2 { status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi2_in: endpoint { clock-lanes = <0>; data-lanes = <1 2>; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi index 36707576030d..f5412578ee65 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi @@ -26,7 +26,12 @@ &du { status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + du_out_rgb: endpoint { remote-endpoint = <&adv7513_in>; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso index c83a30adc6ad..7807c3f80409 100644 --- a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso +++ b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso @@ -27,7 +27,12 @@ &lvds0 { status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + lvds0_out: endpoint { remote-endpoint = <&panel_in>; }; diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index f463a654a2bb..cc0702fa64a7 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -409,7 +409,7 @@ __AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000) __AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000) __AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000) __AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000) -__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000) +__AARCH64_INSN_FUNCS(bcond, 0xFF000000, 0x54000000) __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001) __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002) __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003) diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index d4d7451c2c12..a8cb5a5c93b7 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -40,7 +40,7 @@ static __always_inline void __pmr_local_irq_enable(void) barrier(); } -static inline void arch_local_irq_enable(void) +static __always_inline void arch_local_irq_enable(void) { if (system_uses_irq_prio_masking()) { __pmr_local_irq_enable(); @@ -68,7 +68,7 @@ static __always_inline void __pmr_local_irq_disable(void) barrier(); } -static inline void arch_local_irq_disable(void) +static __always_inline void arch_local_irq_disable(void) { if (system_uses_irq_prio_masking()) { __pmr_local_irq_disable(); @@ -90,7 +90,7 @@ static __always_inline unsigned long __pmr_local_save_flags(void) /* * Save the current interrupt enable state. */ -static inline unsigned long arch_local_save_flags(void) +static __always_inline unsigned long arch_local_save_flags(void) { if (system_uses_irq_prio_masking()) { return __pmr_local_save_flags(); @@ -109,7 +109,7 @@ static __always_inline bool __pmr_irqs_disabled_flags(unsigned long flags) return flags != GIC_PRIO_IRQON; } -static inline bool arch_irqs_disabled_flags(unsigned long flags) +static __always_inline bool arch_irqs_disabled_flags(unsigned long flags) { if (system_uses_irq_prio_masking()) { return __pmr_irqs_disabled_flags(flags); @@ -128,7 +128,7 @@ static __always_inline bool __pmr_irqs_disabled(void) return __pmr_irqs_disabled_flags(__pmr_local_save_flags()); } -static inline bool arch_irqs_disabled(void) +static __always_inline bool arch_irqs_disabled(void) { if (system_uses_irq_prio_masking()) { return __pmr_irqs_disabled(); @@ -160,7 +160,7 @@ static __always_inline unsigned long __pmr_local_irq_save(void) return flags; } -static inline unsigned long arch_local_irq_save(void) +static __always_inline unsigned long arch_local_irq_save(void) { if (system_uses_irq_prio_masking()) { return __pmr_local_irq_save(); @@ -187,7 +187,7 @@ static __always_inline void __pmr_local_irq_restore(unsigned long flags) /* * restore saved IRQ state */ -static inline void arch_local_irq_restore(unsigned long flags) +static __always_inline void arch_local_irq_restore(unsigned long flags) { if (system_uses_irq_prio_masking()) { __pmr_local_irq_restore(flags); diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h index 74a4f738c5f5..229ee7976f69 100644 --- a/arch/arm64/include/asm/kernel-pgtable.h +++ b/arch/arm64/include/asm/kernel-pgtable.h @@ -68,7 +68,12 @@ #define KERNEL_SEGMENT_COUNT 5 #if SWAPPER_BLOCK_SIZE > SEGMENT_ALIGN -#define EARLY_SEGMENT_EXTRA_PAGES (KERNEL_SEGMENT_COUNT + 1) +/* + * KERNEL_SEGMENT_COUNT counts the permanent kernel VMAs. The early mapping + * has one additional split, [_text, _stext). Reserve one more page for the + * SWAPPER_BLOCK_SIZE-unaligned boundaries. + */ +#define EARLY_SEGMENT_EXTRA_PAGES (KERNEL_SEGMENT_COUNT + 2) /* * The initial ID map consists of the kernel image, mapped as two separate * segments, and may appear misaligned wrt the swapper block size. This means diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 37414440cee7..043495f7fc78 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -50,6 +50,9 @@ #include +#define MARKER(m) \ + m, __after_##m = m - 1 + enum __kvm_host_smccc_func { /* Hypercalls that are unavailable once pKVM has finalised. */ /* __KVM_HOST_SMCCC_FUNC___kvm_hyp_init */ @@ -59,8 +62,10 @@ enum __kvm_host_smccc_func { __KVM_HOST_SMCCC_FUNC___kvm_enable_ssbs, __KVM_HOST_SMCCC_FUNC___vgic_v3_init_lrs, __KVM_HOST_SMCCC_FUNC___vgic_v3_get_gic_config, + + MARKER(__KVM_HOST_SMCCC_FUNC_MIN_PKVM), + __KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize, - __KVM_HOST_SMCCC_FUNC_MIN_PKVM = __KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize, /* Hypercalls that are always available and common to [nh]VHE/pKVM. */ __KVM_HOST_SMCCC_FUNC___kvm_adjust_pc, @@ -72,11 +77,20 @@ enum __kvm_host_smccc_func { __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_range, __KVM_HOST_SMCCC_FUNC___kvm_flush_cpu_context, __KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff, + __KVM_HOST_SMCCC_FUNC___tracing_load, + __KVM_HOST_SMCCC_FUNC___tracing_unload, + __KVM_HOST_SMCCC_FUNC___tracing_enable, + __KVM_HOST_SMCCC_FUNC___tracing_swap_reader, + __KVM_HOST_SMCCC_FUNC___tracing_update_clock, + __KVM_HOST_SMCCC_FUNC___tracing_reset, + __KVM_HOST_SMCCC_FUNC___tracing_enable_event, + __KVM_HOST_SMCCC_FUNC___tracing_write_event, __KVM_HOST_SMCCC_FUNC___vgic_v3_save_aprs, __KVM_HOST_SMCCC_FUNC___vgic_v3_restore_vmcr_aprs, __KVM_HOST_SMCCC_FUNC___vgic_v5_save_apr, __KVM_HOST_SMCCC_FUNC___vgic_v5_restore_vmcr_apr, - __KVM_HOST_SMCCC_FUNC_MAX_NO_PKVM = __KVM_HOST_SMCCC_FUNC___vgic_v5_restore_vmcr_apr, + + MARKER(__KVM_HOST_SMCCC_FUNC_PKVM_ONLY), /* Hypercalls that are available only when pKVM has finalised. */ __KVM_HOST_SMCCC_FUNC___pkvm_host_share_hyp, @@ -100,14 +114,8 @@ enum __kvm_host_smccc_func { __KVM_HOST_SMCCC_FUNC___pkvm_vcpu_load, __KVM_HOST_SMCCC_FUNC___pkvm_vcpu_put, __KVM_HOST_SMCCC_FUNC___pkvm_tlb_flush_vmid, - __KVM_HOST_SMCCC_FUNC___tracing_load, - __KVM_HOST_SMCCC_FUNC___tracing_unload, - __KVM_HOST_SMCCC_FUNC___tracing_enable, - __KVM_HOST_SMCCC_FUNC___tracing_swap_reader, - __KVM_HOST_SMCCC_FUNC___tracing_update_clock, - __KVM_HOST_SMCCC_FUNC___tracing_reset, - __KVM_HOST_SMCCC_FUNC___tracing_enable_event, - __KVM_HOST_SMCCC_FUNC___tracing_write_event, + + MARKER(__KVM_HOST_SMCCC_FUNC_MAX) }; #define DECLARE_KVM_VHE_SYM(sym) extern char sym[] diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 851f6171751c..65eead8362e0 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -450,9 +450,6 @@ struct kvm_vcpu_fault_info { r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ __after_##r = __MAX__(__before_##r - 1, r) -#define MARKER(m) \ - m, __after_##m = m - 1 - enum vcpu_sysreg { __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ MPIDR_EL1, /* MultiProcessor Affinity Register */ @@ -1548,7 +1545,7 @@ static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f)) #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) -#define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) +#define kvm_vcpu_initialized(v) vcpu_get_flag(v, VCPU_INITIALIZED) int kvm_trng_call(struct kvm_vcpu *vcpu); #ifdef CONFIG_KVM diff --git a/arch/arm64/include/asm/kvm_nested.h b/arch/arm64/include/asm/kvm_nested.h index 091544e6af44..dc2957662ff2 100644 --- a/arch/arm64/include/asm/kvm_nested.h +++ b/arch/arm64/include/asm/kvm_nested.h @@ -23,6 +23,7 @@ static inline u64 tcr_el2_ps_to_tcr_el1_ips(u64 tcr_el2) static inline u64 translate_tcr_el2_to_tcr_el1(u64 tcr) { return TCR_EPD1_MASK | /* disable TTBR1_EL1 */ + ((tcr & TCR_EL2_DS) ? TCR_DS : 0) | ((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) | tcr_el2_ps_to_tcr_el1_ips(tcr) | (tcr & TCR_EL2_TG0_MASK) | diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h index e25d0d18f6d7..58200de8a221 100644 --- a/arch/arm64/include/asm/page.h +++ b/arch/arm64/include/asm/page.h @@ -33,7 +33,7 @@ struct folio *vma_alloc_zeroed_movable_folio(struct vm_area_struct *vma, unsigned long vaddr); #define vma_alloc_zeroed_movable_folio vma_alloc_zeroed_movable_folio -bool tag_clear_highpages(struct page *to, int numpages); +bool tag_clear_highpages(struct page *to, int numpages, bool clear_pages); #define __HAVE_ARCH_TAG_CLEAR_HIGHPAGES #define copy_user_page(to, from, vaddr, pg) copy_page(to, from) diff --git a/arch/arm64/include/asm/ring_buffer.h b/arch/arm64/include/asm/ring_buffer.h new file mode 100644 index 000000000000..62316c406888 --- /dev/null +++ b/arch/arm64/include/asm/ring_buffer.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_ARM64_RING_BUFFER_H +#define _ASM_ARM64_RING_BUFFER_H + +#include + +/* Flush D-cache on persistent ring buffer */ +#define arch_ring_buffer_flush_range(start, end) dcache_clean_pop(start, end) + +#endif /* _ASM_ARM64_RING_BUFFER_H */ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 736561480f36..7aa08d59d494 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -844,7 +844,7 @@ #define INIT_SCTLR_EL2_MMU_ON \ (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \ - SCTLR_ELx_ITFSB | SCTLR_EL2_RES1) + SCTLR_ELx_ITFSB | SCTLR_ELx_EIS | SCTLR_ELx_EOS | SCTLR_EL2_RES1) #define INIT_SCTLR_EL2_MMU_OFF \ (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h index 10869d7731b8..751bd57bc3ba 100644 --- a/arch/arm64/include/asm/tlb.h +++ b/arch/arm64/include/asm/tlb.h @@ -53,7 +53,8 @@ static inline int tlb_get_level(struct mmu_gather *tlb) static inline void tlb_flush(struct mmu_gather *tlb) { struct vm_area_struct vma = TLB_FLUSH_VMA(tlb->mm, 0); - tlbf_t flags = tlb->freed_tables ? TLBF_NONE : TLBF_NOWALKCACHE; + tlbf_t flags = (tlb->freed_tables || tlb->unshared_tables) ? + TLBF_NONE : TLBF_NOWALKCACHE; unsigned long stride = tlb_get_unmap_size(tlb); int tlb_level = tlb_get_level(tlb); diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c index cb54335465f6..c7a23f7c2212 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -62,6 +62,13 @@ static void noinstr arm64_exit_to_kernel_mode(struct pt_regs *regs, irqentry_exit_to_kernel_mode_after_preempt(regs, state); } +static __always_inline void arm64_syscall_enter_from_user_mode(struct pt_regs *regs) +{ + enter_from_user_mode(regs); + mte_disable_tco_entry(current); + sme_enter_from_user_mode(); +} + /* * Handle IRQ/context state management when entering from user mode. * Before this function is called it is not safe to call regular kernel code, @@ -70,20 +77,30 @@ static void noinstr arm64_exit_to_kernel_mode(struct pt_regs *regs, static __always_inline void arm64_enter_from_user_mode(struct pt_regs *regs) { enter_from_user_mode(regs); + rseq_note_user_irq_entry(); mte_disable_tco_entry(current); sme_enter_from_user_mode(); } +static __always_inline void arm64_syscall_exit_to_user_mode(struct pt_regs *regs) +{ + local_irq_disable(); + syscall_exit_to_user_mode_prepare(regs); + local_daif_mask(); + sme_exit_to_user_mode(); + mte_check_tfsr_exit(); + exit_to_user_mode(); +} + /* * Handle IRQ/context state management when exiting to user mode. * After this function returns it is not safe to call regular kernel code, * instrumentable code, or any code which may trigger an exception. */ - static __always_inline void arm64_exit_to_user_mode(struct pt_regs *regs) { local_irq_disable(); - exit_to_user_mode_prepare_legacy(regs); + irqentry_exit_to_user_mode_prepare(regs); local_daif_mask(); sme_exit_to_user_mode(); mte_check_tfsr_exit(); @@ -92,7 +109,7 @@ static __always_inline void arm64_exit_to_user_mode(struct pt_regs *regs) asmlinkage void noinstr asm_exit_to_user_mode(struct pt_regs *regs) { - arm64_exit_to_user_mode(regs); + arm64_syscall_exit_to_user_mode(regs); } /* @@ -716,12 +733,12 @@ static void noinstr el0_brk64(struct pt_regs *regs, unsigned long esr) static void noinstr el0_svc(struct pt_regs *regs) { - arm64_enter_from_user_mode(regs); + arm64_syscall_enter_from_user_mode(regs); cortex_a76_erratum_1463225_svc_handler(); fpsimd_syscall_enter(); local_daif_restore(DAIF_PROCCTX); do_el0_svc(regs); - arm64_exit_to_user_mode(regs); + arm64_syscall_exit_to_user_mode(regs); fpsimd_syscall_exit(); } @@ -868,11 +885,11 @@ static void noinstr el0_cp15(struct pt_regs *regs, unsigned long esr) static void noinstr el0_svc_compat(struct pt_regs *regs) { - arm64_enter_from_user_mode(regs); + arm64_syscall_enter_from_user_mode(regs); cortex_a76_erratum_1463225_svc_handler(); local_daif_restore(DAIF_PROCCTX); do_el0_svc_compat(regs); - arm64_exit_to_user_mode(regs); + arm64_syscall_exit_to_user_mode(regs); } static void noinstr el0_bkpt32(struct pt_regs *regs, unsigned long esr) diff --git a/arch/arm64/kernel/pi/patch-scs.c b/arch/arm64/kernel/pi/patch-scs.c index dac568e4a54f..3944ad899021 100644 --- a/arch/arm64/kernel/pi/patch-scs.c +++ b/arch/arm64/kernel/pi/patch-scs.c @@ -196,9 +196,9 @@ static int scs_handle_fde_frame(const struct eh_frame *frame, loc += *opcode++ * code_alignment_factor; loc += (*opcode++ << 8) * code_alignment_factor; loc += (*opcode++ << 16) * code_alignment_factor; - loc += (*opcode++ << 24) * code_alignment_factor; + loc += ((u64)*opcode++ << 24) * code_alignment_factor; size -= 4; - break; + break; case DW_CFA_def_cfa: case DW_CFA_offset_extended: diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index ba5eab23fd90..4d08598e2891 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -983,8 +983,8 @@ static int sve_set_common(struct task_struct *target, } /* Always zero V regs, FPSR, and FPCR */ - memset(¤t->thread.uw.fpsimd_state, 0, - sizeof(current->thread.uw.fpsimd_state)); + memset(&target->thread.uw.fpsimd_state, 0, + sizeof(target->thread.uw.fpsimd_state)); /* Registers: FPSIMD-only case */ diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 08ffc5a5aea4..38e6fa204c17 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -67,6 +67,9 @@ struct rt_sigframe_user_layout { unsigned long end_offset; }; +#define TERMINATOR_SIZE round_up(sizeof(struct _aarch64_ctx), 16) +#define EXTRA_CONTEXT_SIZE round_up(sizeof(struct extra_context), 16) + /* * Holds any EL0-controlled state that influences unprivileged memory accesses. * This includes both accesses done in userspace and uaccess done in the kernel. @@ -74,13 +77,35 @@ struct rt_sigframe_user_layout { * This state needs to be carefully managed to ensure that it doesn't cause * uaccess to fail when setting up the signal frame, and the signal handler * itself also expects a well-defined state when entered. + * + * The struct should be zero-initialised. Its members should only be accessed + * via the accessors below. __valid_fields tracks which of the fields are valid + * (have been set to some value). */ struct user_access_state { - u64 por_el0; + unsigned int __valid_fields; + u64 __por_el0; }; -#define TERMINATOR_SIZE round_up(sizeof(struct _aarch64_ctx), 16) -#define EXTRA_CONTEXT_SIZE round_up(sizeof(struct extra_context), 16) +#define UA_STATE_HAS_POR_EL0 BIT(0) + +static void set_ua_state_por_el0(struct user_access_state *ua_state, + u64 por_el0) +{ + ua_state->__por_el0 = por_el0; + ua_state->__valid_fields |= UA_STATE_HAS_POR_EL0; +} + +static int get_ua_state_por_el0(const struct user_access_state *ua_state, + u64 *por_el0) +{ + if (ua_state->__valid_fields & UA_STATE_HAS_POR_EL0) { + *por_el0 = ua_state->__por_el0; + return 0; + } + + return -ENOENT; +} /* * Save the user access state into ua_state and reset it to disable any @@ -94,7 +119,7 @@ static void save_reset_user_access_state(struct user_access_state *ua_state) for (int pkey = 0; pkey < arch_max_pkey(); pkey++) por_enable_all |= POR_ELx_PERM_PREP(pkey, POE_RWX); - ua_state->por_el0 = read_sysreg_s(SYS_POR_EL0); + set_ua_state_por_el0(ua_state, read_sysreg_s(SYS_POR_EL0)); write_sysreg_s(por_enable_all, SYS_POR_EL0); /* * No ISB required as we can tolerate spurious Overlay faults - @@ -122,8 +147,10 @@ static void set_handler_user_access_state(void) */ static void restore_user_access_state(const struct user_access_state *ua_state) { - if (system_supports_poe()) - write_sysreg_s(ua_state->por_el0, SYS_POR_EL0); + u64 por_el0; + + if (get_ua_state_por_el0(ua_state, &por_el0) == 0) + write_sysreg_s(por_el0, SYS_POR_EL0); } static void init_user_layout(struct rt_sigframe_user_layout *user) @@ -333,11 +360,16 @@ static int restore_fpmr_context(struct user_ctxs *user) static int preserve_poe_context(struct poe_context __user *ctx, const struct user_access_state *ua_state) { - int err = 0; + int err; + u64 por_el0; + + err = get_ua_state_por_el0(ua_state, &por_el0); + if (WARN_ON_ONCE(err)) + return err; __put_user_error(POE_MAGIC, &ctx->head.magic, err); __put_user_error(sizeof(*ctx), &ctx->head.size, err); - __put_user_error(ua_state->por_el0, &ctx->por_el0, err); + __put_user_error(por_el0, &ctx->por_el0, err); return err; } @@ -353,7 +385,7 @@ static int restore_poe_context(struct user_ctxs *user, __get_user_error(por_el0, &(user->poe->por_el0), err); if (!err) - ua_state->por_el0 = por_el0; + set_ua_state_por_el0(ua_state, por_el0); return err; } @@ -1095,7 +1127,7 @@ SYSCALL_DEFINE0(rt_sigreturn) { struct pt_regs *regs = current_pt_regs(); struct rt_sigframe __user *frame; - struct user_access_state ua_state; + struct user_access_state ua_state = {}; /* Always make any pending restarted system calls return -EINTR */ current->restart_block.fn = do_no_restart_syscall; @@ -1507,7 +1539,7 @@ static int setup_rt_frame(int usig, struct ksignal *ksig, sigset_t *set, { struct rt_sigframe_user_layout user; struct rt_sigframe __user *frame; - struct user_access_state ua_state; + struct user_access_state ua_state = {}; int err = 0; fpsimd_save_and_flush_current_state(); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 176cbe8baad3..9453321ef8c6 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -4,6 +4,7 @@ * Author: Christoffer Dall */ +#include #include #include #include @@ -554,8 +555,10 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) kvm_destroy_mpidr_data(vcpu->kvm); err = kvm_vgic_vcpu_init(vcpu); - if (err) + if (err) { + kvm_vgic_vcpu_destroy(vcpu); return err; + } err = kvm_share_hyp(vcpu, vcpu + 1); if (err) @@ -824,6 +827,10 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *v) { bool irq_lines = *vcpu_hcr(v) & (HCR_VI | HCR_VF | HCR_VSE); + irq_lines |= (!irqchip_in_kernel(v->kvm) && + (kvm_timer_should_notify_user(v) || + kvm_pmu_should_notify_user(v))); + return ((irq_lines || kvm_vgic_vcpu_pending_irq(v)) && !kvm_arm_vcpu_stopped(v) && !v->arch.pause); } @@ -2634,6 +2641,22 @@ static int init_pkvm_host_sve_state(void) return 0; } +static int pkvm_check_sme_dvmsync_fw_call(void) +{ + struct arm_smccc_res res; + + if (!cpus_have_final_cap(ARM64_WORKAROUND_4193714)) + return 0; + + arm_smccc_1_1_smc(ARM_SMCCC_CPU_WORKAROUND_4193714, &res); + if (res.a0) { + kvm_err("pKVM requires firmware support for C1-Pro erratum 4193714\n"); + return -ENODEV; + } + + return 0; +} + /* * Finalizes the initialization of hyp mode, once everything else is initialized * and the initialziation process cannot fail. @@ -2834,6 +2857,10 @@ static int __init init_hyp_mode(void) if (err) goto out_err; + err = pkvm_check_sme_dvmsync_fw_call(); + if (err) + goto out_err; + err = kvm_hyp_init_protection(hyp_va_bits); if (err) { kvm_err("Failed to init hyp memory protection\n"); diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index f35b8dddd7c1..0622162b089e 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -131,7 +131,6 @@ struct reg_feat_map_desc { } #define FEAT_SPE ID_AA64DFR0_EL1, PMSVer, IMP -#define FEAT_SPE_FnE ID_AA64DFR0_EL1, PMSVer, V1P2 #define FEAT_BRBE ID_AA64DFR0_EL1, BRBE, IMP #define FEAT_TRC_SR ID_AA64DFR0_EL1, TraceVer, IMP #define FEAT_PMUv3 ID_AA64DFR0_EL1, PMUVer, IMP @@ -192,7 +191,7 @@ struct reg_feat_map_desc { #define FEAT_SRMASK ID_AA64MMFR4_EL1, SRMASK, IMP #define FEAT_PoPS ID_AA64MMFR4_EL1, PoPS, IMP #define FEAT_PFAR ID_AA64PFR1_EL1, PFAR, IMP -#define FEAT_Debugv8p9 ID_AA64DFR0_EL1, PMUVer, V3P9 +#define FEAT_Debugv8p9 ID_AA64DFR0_EL1, DebugVer, V8P9 #define FEAT_PMUv3_SS ID_AA64DFR0_EL1, PMSS, IMP #define FEAT_SEBEP ID_AA64DFR0_EL1, SEBEP, IMP #define FEAT_EBEP ID_AA64DFR1_EL1, EBEP, IMP @@ -283,7 +282,7 @@ static bool feat_anerr(struct kvm *kvm) static bool feat_sme_smps(struct kvm *kvm) { /* - * Revists this if KVM ever supports SME -- this really should + * Revisit this if KVM ever supports SME -- this really should * look at the guest's view of SMIDR_EL1. Funnily enough, this * is not captured in the JSON file, but only as a note in the * ARM ARM. @@ -295,17 +294,27 @@ static bool feat_sme_smps(struct kvm *kvm) static bool feat_spe_fds(struct kvm *kvm) { /* - * Revists this if KVM ever supports SPE -- this really should + * Revisit this if KVM ever supports SPE -- this really should * look at the guest's view of PMSIDR_EL1. */ return (kvm_has_feat(kvm, FEAT_SPEv1p4) && (read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FDS)); } +static bool feat_spe_fne(struct kvm *kvm) +{ + /* + * Revisit this if KVM ever supports SPE -- this really should + * look at the guest's view of PMSIDR_EL1. + */ + return (kvm_has_feat(kvm, FEAT_SPEv1p2) && + (read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FnE)); +} + static bool feat_trbe_mpam(struct kvm *kvm) { /* - * Revists this if KVM ever supports both MPAM and TRBE -- + * Revisit this if KVM ever supports both MPAM and TRBE -- * this really should look at the guest's view of TRBIDR_EL1. */ return (kvm_has_feat(kvm, FEAT_TRBE) && @@ -537,7 +546,7 @@ static const struct reg_bits_to_feat_map hdfgrtr_feat_map[] = { HDFGRTR_EL2_PMBPTR_EL1 | HDFGRTR_EL2_PMBLIMITR_EL1, FEAT_SPE), - NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE), + NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, feat_spe_fne), NEEDS_FEAT(HDFGRTR_EL2_nBRBDATA | HDFGRTR_EL2_nBRBCTL | HDFGRTR_EL2_nBRBIDR, @@ -605,7 +614,7 @@ static const struct reg_bits_to_feat_map hdfgwtr_feat_map[] = { HDFGWTR_EL2_PMBPTR_EL1 | HDFGWTR_EL2_PMBLIMITR_EL1, FEAT_SPE), - NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE), + NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, feat_spe_fne), NEEDS_FEAT(HDFGWTR_EL2_nBRBDATA | HDFGWTR_EL2_nBRBCTL, FEAT_BRBE), diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index 98b2976837b1..bf0eb5e43427 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -245,7 +245,7 @@ static inline void __activate_traps_ich_hfgxtr(struct kvm_vcpu *vcpu) __activate_fgt(hctxt, vcpu, ICH_HFGITR_EL2); } -#define __deactivate_fgt(htcxt, vcpu, reg) \ +#define __deactivate_fgt(hctxt, vcpu, reg) \ do { \ write_sysreg_s(ctxt_sys_reg(hctxt, reg), \ SYS_ ## reg); \ diff --git a/arch/arm64/kvm/hyp/nvhe/clock.c b/arch/arm64/kvm/hyp/nvhe/clock.c index 32fc4313fe43..a7fc61976fd0 100644 --- a/arch/arm64/kvm/hyp/nvhe/clock.c +++ b/arch/arm64/kvm/hyp/nvhe/clock.c @@ -35,6 +35,9 @@ void trace_clock_update(u32 mult, u32 shift, u64 epoch_ns, u64 epoch_cyc) struct clock_data *clock = &trace_clock_data; u64 bank = clock->cur ^ 1; + if (!mult || shift >= 64) + return; + clock->data[bank].mult = mult; clock->data[bank].shift = shift; clock->data[bank].epoch_ns = epoch_ns; diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index 73f2e0221e70..06db299c37a8 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -709,6 +709,14 @@ static const hcall_t host_hcall[] = { HANDLE_FUNC(__kvm_tlb_flush_vmid_range), HANDLE_FUNC(__kvm_flush_cpu_context), HANDLE_FUNC(__kvm_timer_set_cntvoff), + HANDLE_FUNC(__tracing_load), + HANDLE_FUNC(__tracing_unload), + HANDLE_FUNC(__tracing_enable), + HANDLE_FUNC(__tracing_swap_reader), + HANDLE_FUNC(__tracing_update_clock), + HANDLE_FUNC(__tracing_reset), + HANDLE_FUNC(__tracing_enable_event), + HANDLE_FUNC(__tracing_write_event), HANDLE_FUNC(__vgic_v3_save_aprs), HANDLE_FUNC(__vgic_v3_restore_vmcr_aprs), HANDLE_FUNC(__vgic_v5_save_apr), @@ -735,22 +743,16 @@ static const hcall_t host_hcall[] = { HANDLE_FUNC(__pkvm_vcpu_load), HANDLE_FUNC(__pkvm_vcpu_put), HANDLE_FUNC(__pkvm_tlb_flush_vmid), - HANDLE_FUNC(__tracing_load), - HANDLE_FUNC(__tracing_unload), - HANDLE_FUNC(__tracing_enable), - HANDLE_FUNC(__tracing_swap_reader), - HANDLE_FUNC(__tracing_update_clock), - HANDLE_FUNC(__tracing_reset), - HANDLE_FUNC(__tracing_enable_event), - HANDLE_FUNC(__tracing_write_event), }; static void handle_host_hcall(struct kvm_cpu_context *host_ctxt) { DECLARE_REG(unsigned long, id, host_ctxt, 0); - unsigned long hcall_min = 0, hcall_max = -1; + unsigned long hcall_min = 0, hcall_max = __KVM_HOST_SMCCC_FUNC_MAX; hcall_t hfn; + BUILD_BUG_ON(ARRAY_SIZE(host_hcall) != __KVM_HOST_SMCCC_FUNC_MAX); + /* * If pKVM has been initialised then reject any calls to the * early "privileged" hypercalls. Note that we cannot reject @@ -763,16 +765,14 @@ static void handle_host_hcall(struct kvm_cpu_context *host_ctxt) if (static_branch_unlikely(&kvm_protected_mode_initialized)) { hcall_min = __KVM_HOST_SMCCC_FUNC_MIN_PKVM; } else { - hcall_max = __KVM_HOST_SMCCC_FUNC_MAX_NO_PKVM; + hcall_max = __KVM_HOST_SMCCC_FUNC_PKVM_ONLY; } id &= ~ARM_SMCCC_CALL_HINTS; id -= KVM_HOST_SMCCC_ID(0); - if (unlikely(id < hcall_min || id > hcall_max || - id >= ARRAY_SIZE(host_hcall))) { + if (unlikely(id < hcall_min || id >= hcall_max)) goto inval; - } hfn = host_hcall[id]; if (unlikely(!hfn)) @@ -805,6 +805,10 @@ static void handle_host_smc(struct kvm_cpu_context *host_ctxt) } func_id &= ~ARM_SMCCC_CALL_HINTS; + if (upper_32_bits(func_id)) { + cpu_reg(host_ctxt, 0) = SMCCC_RET_NOT_SUPPORTED; + goto exit_skip_instr; + } handled = kvm_host_psci_handler(host_ctxt, func_id); if (!handled) diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c index 28a471d1927c..25f04629014e 100644 --- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c +++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c @@ -5,6 +5,7 @@ */ #include + #include #include #include @@ -14,6 +15,7 @@ #include +#include #include #include #include @@ -29,6 +31,19 @@ static struct hyp_pool host_s2_pool; static DEFINE_PER_CPU(struct pkvm_hyp_vm *, __current_vm); #define current_vm (*this_cpu_ptr(&__current_vm)) +static void pkvm_sme_dvmsync_fw_call(void) +{ + if (alternative_has_cap_unlikely(ARM64_WORKAROUND_4193714)) { + struct arm_smccc_res res; + + /* + * Ignore the return value. Probing for the workaround + * availability took place in init_hyp_mode(). + */ + hyp_smccc_1_1_smc(ARM_SMCCC_CPU_WORKAROUND_4193714, &res); + } +} + static void guest_lock_component(struct pkvm_hyp_vm *vm) { hyp_spin_lock(&vm->lock); @@ -574,8 +589,14 @@ static int host_stage2_set_owner_metadata_locked(phys_addr_t addr, u64 size, ret = host_stage2_try(kvm_pgtable_stage2_annotate, &host_mmu.pgt, addr, size, &host_s2_pool, KVM_HOST_INVALID_PTE_TYPE_DONATION, annotation); - if (!ret) + if (!ret) { + /* + * After stage2 maintenance has happened, but before the page + * owner has changed. + */ + pkvm_sme_dvmsync_fw_call(); __host_update_page_state(addr, size, PKVM_NOPAGE); + } return ret; } @@ -1369,6 +1390,22 @@ int __pkvm_host_reclaim_page_guest(u64 gfn, struct pkvm_hyp_vm *vm) return ret && ret != -EHWPOISON ? ret : 0; } +/* + * share/donate install at most one stage-2 leaf (PAGE_SIZE, or one + * KVM_PGTABLE_LAST_LEVEL - 1 block for share). kvm_mmu_cache_min_pages() + * bounds the worst-case allocation: exact for the PAGE_SIZE leaf, + * conservative by one for the block. + */ +static int __guest_check_pgtable_memcache(struct pkvm_hyp_vcpu *vcpu) +{ + struct pkvm_hyp_vm *vm = pkvm_hyp_vcpu_to_hyp_vm(vcpu); + + if (vcpu->vcpu.arch.pkvm_memcache.nr_pages < kvm_mmu_cache_min_pages(vm->pgt.mmu)) + return -ENOMEM; + + return 0; +} + int __pkvm_host_donate_guest(u64 pfn, u64 gfn, struct pkvm_hyp_vcpu *vcpu) { struct pkvm_hyp_vm *vm = pkvm_hyp_vcpu_to_hyp_vm(vcpu); @@ -1388,6 +1425,10 @@ int __pkvm_host_donate_guest(u64 pfn, u64 gfn, struct pkvm_hyp_vcpu *vcpu) if (ret) goto unlock; + ret = __guest_check_pgtable_memcache(vcpu); + if (ret) + goto unlock; + meta = host_stage2_encode_gfn_meta(vm, gfn); WARN_ON(host_stage2_set_owner_metadata_locked(phys, PAGE_SIZE, PKVM_ID_GUEST, meta)); @@ -1453,6 +1494,10 @@ int __pkvm_host_share_guest(u64 pfn, u64 gfn, u64 nr_pages, struct pkvm_hyp_vcpu } } + ret = __guest_check_pgtable_memcache(vcpu); + if (ret) + goto unlock; + for_each_hyp_page(page, phys, size) { set_host_state(page, PKVM_PAGE_SHARED_OWNED); page->host_share_guest_count++; diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 7ed96d64d611..eb1c10120f9f 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -266,7 +266,8 @@ struct pkvm_hyp_vcpu *pkvm_load_hyp_vcpu(pkvm_handle_t handle, if (hyp_vm->kvm.created_vcpus <= vcpu_idx) goto unlock; - hyp_vcpu = hyp_vm->vcpus[vcpu_idx]; + /* Pairs with smp_store_release() in register_hyp_vcpu(). */ + hyp_vcpu = smp_load_acquire(&hyp_vm->vcpus[vcpu_idx]); if (!hyp_vcpu) goto unlock; @@ -751,16 +752,30 @@ static struct pkvm_hyp_vcpu selftest_vcpu = { struct pkvm_hyp_vcpu *init_selftest_vm(void *virt) { struct hyp_page *p = hyp_virt_to_page(virt); + unsigned long min_pages, seeded = 0; int i; selftest_vm.kvm.arch.mmu.vtcr = host_mmu.arch.mmu.vtcr; WARN_ON(kvm_guest_prepare_stage2(&selftest_vm, virt)); + /* + * Mirror pkvm_refill_memcache() for the share/donate pre-checks; + * the selftest invokes those functions directly and would + * otherwise see an empty memcache. + */ + min_pages = kvm_mmu_cache_min_pages(&selftest_vm.kvm.arch.mmu); + for (i = 0; i < pkvm_selftest_pages(); i++) { if (p[i].refcount) continue; p[i].refcount = 1; - hyp_put_page(&selftest_vm.pool, hyp_page_to_virt(&p[i])); + if (seeded < min_pages) { + push_hyp_memcache(&selftest_vcpu.vcpu.arch.pkvm_memcache, + hyp_page_to_virt(&p[i]), hyp_virt_to_phys); + seeded++; + } else { + hyp_put_page(&selftest_vm.pool, hyp_page_to_virt(&p[i])); + } } selftest_vm.kvm.arch.pkvm.handle = __pkvm_reserve_vm(); @@ -860,12 +875,30 @@ int __pkvm_init_vm(struct kvm *host_kvm, unsigned long vm_hva, * the page-aligned size of 'struct pkvm_hyp_vcpu'. * Return 0 on success, negative error code on failure. */ +static int register_hyp_vcpu(struct pkvm_hyp_vm *hyp_vm, + struct pkvm_hyp_vcpu *hyp_vcpu) +{ + unsigned int idx = hyp_vcpu->vcpu.vcpu_idx; + + if (idx >= hyp_vm->kvm.created_vcpus) + return -EINVAL; + + if (hyp_vm->vcpus[idx]) + return -EINVAL; + + /* + * Ensure the hyp_vcpu is initialised before publishing it to + * the vCPU-load path via 'hyp_vm->vcpus[]'. + */ + smp_store_release(&hyp_vm->vcpus[idx], hyp_vcpu); + return 0; +} + int __pkvm_init_vcpu(pkvm_handle_t handle, struct kvm_vcpu *host_vcpu, unsigned long vcpu_hva) { struct pkvm_hyp_vcpu *hyp_vcpu; struct pkvm_hyp_vm *hyp_vm; - unsigned int idx; int ret; hyp_vcpu = map_donated_memory(vcpu_hva, sizeof(*hyp_vcpu)); @@ -884,18 +917,11 @@ int __pkvm_init_vcpu(pkvm_handle_t handle, struct kvm_vcpu *host_vcpu, if (ret) goto unlock; - idx = hyp_vcpu->vcpu.vcpu_idx; - if (idx >= hyp_vm->kvm.created_vcpus) { - ret = -EINVAL; - goto unlock; + ret = register_hyp_vcpu(hyp_vm, hyp_vcpu); + if (ret) { + unpin_host_vcpu(host_vcpu); + unpin_host_sve_state(hyp_vcpu); } - - if (hyp_vm->vcpus[idx]) { - ret = -EINVAL; - goto unlock; - } - - hyp_vm->vcpus[idx] = hyp_vcpu; unlock: hyp_spin_unlock(&vm_table_lock); diff --git a/arch/arm64/kvm/hyp/nvhe/setup.c b/arch/arm64/kvm/hyp/nvhe/setup.c index d8e5b563fd3d..d461981616d9 100644 --- a/arch/arm64/kvm/hyp/nvhe/setup.c +++ b/arch/arm64/kvm/hyp/nvhe/setup.c @@ -312,10 +312,6 @@ void __noreturn __pkvm_init_finalise(void) }; pkvm_pgtable.mm_ops = &pkvm_pgtable_mm_ops; - ret = fix_host_ownership(); - if (ret) - goto out; - ret = fix_hyp_pgtable_refcnt(); if (ret) goto out; @@ -324,6 +320,10 @@ void __noreturn __pkvm_init_finalise(void) if (ret) goto out; + ret = fix_host_ownership(); + if (ret) + goto out; + ret = hyp_ffa_init(ffa_proxy_pages); if (ret) goto out; diff --git a/arch/arm64/kvm/hyp/nvhe/trace.c b/arch/arm64/kvm/hyp/nvhe/trace.c index a6ca27b18e15..e7e150ab265f 100644 --- a/arch/arm64/kvm/hyp/nvhe/trace.c +++ b/arch/arm64/kvm/hyp/nvhe/trace.c @@ -164,13 +164,16 @@ static int hyp_trace_buffer_load(struct hyp_trace_buffer *trace_buffer, return ret; } -static bool hyp_trace_desc_validate(struct hyp_trace_desc *desc, size_t desc_size) +static bool hyp_trace_desc_is_valid(struct hyp_trace_desc *desc, size_t desc_size) { struct ring_buffer_desc *rb_desc; unsigned int cpu; size_t nr_bpages; void *desc_end; + if (!is_protected_kvm_enabled()) + return true; + /* * Both desc_size and bpages_backing_size are untrusted host-provided * values. We rely on __pkvm_host_donate_hyp() to enforce their validity. @@ -212,8 +215,10 @@ int __tracing_load(unsigned long desc_hva, size_t desc_size) if (ret) return ret; - if (!hyp_trace_desc_validate(desc, desc_size)) + if (!hyp_trace_desc_is_valid(desc, desc_size)) { + ret = -EINVAL; goto err_release_desc; + } hyp_spin_lock(&trace_buffer.lock); diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c index 9db3f11a4754..1e8995add14f 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -663,7 +663,8 @@ static void __noreturn __hyp_call_panic(u64 spsr, u64 elr, u64 par) host_ctxt = host_data_ptr(host_ctxt); vcpu = host_ctxt->__hyp_running_vcpu; - __deactivate_traps(vcpu); + if (vcpu) + __deactivate_traps(vcpu); sysreg_restore_host_state_vhe(host_ctxt); panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n", diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index d089c107d9b7..4da9281312eb 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1576,21 +1576,24 @@ struct kvm_s2_fault_desc { static int gmem_abort(const struct kvm_s2_fault_desc *s2fd) { bool write_fault, exec_fault; + bool perm_fault = kvm_vcpu_trap_is_permission_fault(s2fd->vcpu); enum kvm_pgtable_walk_flags flags = KVM_PGTABLE_WALK_SHARED; enum kvm_pgtable_prot prot = KVM_PGTABLE_PROT_R; struct kvm_pgtable *pgt = s2fd->vcpu->arch.hw_mmu->pgt; unsigned long mmu_seq; struct page *page; struct kvm *kvm = s2fd->vcpu->kvm; - void *memcache; + void *memcache = NULL; kvm_pfn_t pfn; gfn_t gfn; int ret; - memcache = get_mmu_memcache(s2fd->vcpu); - ret = topup_mmu_memcache(s2fd->vcpu, memcache); - if (ret) - return ret; + if (!perm_fault) { + memcache = get_mmu_memcache(s2fd->vcpu); + ret = topup_mmu_memcache(s2fd->vcpu, memcache); + if (ret) + return ret; + } if (s2fd->nested) gfn = kvm_s2_trans_output(s2fd->nested) >> PAGE_SHIFT; @@ -1631,9 +1634,19 @@ static int gmem_abort(const struct kvm_s2_fault_desc *s2fd) goto out_unlock; } - ret = KVM_PGT_FN(kvm_pgtable_stage2_map)(pgt, s2fd->fault_ipa, PAGE_SIZE, - __pfn_to_phys(pfn), prot, - memcache, flags); + if (perm_fault) { + /* + * Drop the SW bits in favour of those stored in the + * PTE, which will be preserved. + */ + prot &= ~KVM_NV_GUEST_MAP_SZ; + ret = KVM_PGT_FN(kvm_pgtable_stage2_relax_perms)(pgt, s2fd->fault_ipa, + prot, flags); + } else { + ret = KVM_PGT_FN(kvm_pgtable_stage2_map)(pgt, s2fd->fault_ipa, PAGE_SIZE, + __pfn_to_phys(pfn), prot, + memcache, flags); + } out_unlock: kvm_release_faultin_page(kvm, page, !!ret, prot & KVM_PGTABLE_PROT_W); diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c index 2ea9f1c7ebcd..1d7e5d560af4 100644 --- a/arch/arm64/kvm/vgic/vgic-its.c +++ b/arch/arm64/kvm/vgic/vgic-its.c @@ -2307,6 +2307,10 @@ static int vgic_its_restore_dte(struct vgic_its *its, u32 id, /* dte entry is valid */ offset = (entry & KVM_ITS_DTE_NEXT_MASK) >> KVM_ITS_DTE_NEXT_SHIFT; + /* Mimic the MAPD behaviour and reject invalid EID bits. */ + if (num_eventid_bits > VITS_TYPER_IDBITS) + return -EINVAL; + if (!vgic_its_check_id(its, baser, id, NULL)) return -EINVAL; diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v2.c b/arch/arm64/kvm/vgic/vgic-mmio-v2.c index 406845b3117c..0643e333db35 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v2.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v2.c @@ -91,7 +91,7 @@ static int vgic_mmio_uaccess_write_v2_misc(struct kvm_vcpu *vcpu, * migration from old kernels to new kernels with legacy * userspace. */ - reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg); + reg = FIELD_GET(GICD_IIDR_REVISION_MASK, val); switch (reg) { case KVM_VGIC_IMP_REV_2: case KVM_VGIC_IMP_REV_3: diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c index 89edb84d1ac6..5913a20d8301 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -194,7 +194,7 @@ static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu, if ((reg ^ val) & ~GICD_IIDR_REVISION_MASK) return -EINVAL; - reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg); + reg = FIELD_GET(GICD_IIDR_REVISION_MASK, val); switch (reg) { case KVM_VGIC_IMP_REV_2: case KVM_VGIC_IMP_REV_3: diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 0f3c5c7ca054..739800835920 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -1018,7 +1018,7 @@ struct folio *vma_alloc_zeroed_movable_folio(struct vm_area_struct *vma, return vma_alloc_folio(flags, 0, vma, vaddr); } -bool tag_clear_highpages(struct page *page, int numpages) +bool tag_clear_highpages(struct page *page, int numpages, bool clear_pages) { /* * Check if MTE is supported and fall back to clear_highpage(). @@ -1026,13 +1026,16 @@ bool tag_clear_highpages(struct page *page, int numpages) * post_alloc_hook() will invoke tag_clear_highpages(). */ if (!system_supports_mte()) - return false; + return clear_pages; /* Newly allocated pages, shouldn't have been tagged yet */ for (int i = 0; i < numpages; i++, page++) { WARN_ON_ONCE(!try_page_mte_tagging(page)); - mte_zero_clear_page_tags(page_address(page)); + if (clear_pages) + mte_zero_clear_page_tags(page_address(page)); + else + mte_clear_page_tags(page_address(page)); set_page_mte_tagged(page); } - return true; + return false; } diff --git a/arch/csky/include/asm/Kbuild b/arch/csky/include/asm/Kbuild index 3a5c7f6e5aac..7dca0c6cdc84 100644 --- a/arch/csky/include/asm/Kbuild +++ b/arch/csky/include/asm/Kbuild @@ -9,6 +9,7 @@ generic-y += qrwlock.h generic-y += qrwlock_types.h generic-y += qspinlock.h generic-y += parport.h +generic-y += ring_buffer.h generic-y += user.h generic-y += vmlinux.lds.h generic-y += text-patching.h diff --git a/arch/hexagon/include/asm/Kbuild b/arch/hexagon/include/asm/Kbuild index 1efa1e993d4b..0f887d4238ed 100644 --- a/arch/hexagon/include/asm/Kbuild +++ b/arch/hexagon/include/asm/Kbuild @@ -5,4 +5,5 @@ generic-y += extable.h generic-y += iomap.h generic-y += kvm_para.h generic-y += mcs_spinlock.h +generic-y += ring_buffer.h generic-y += text-patching.h diff --git a/arch/loongarch/Kbuild b/arch/loongarch/Kbuild index beb8499dd8ed..1c7a0dbe5e72 100644 --- a/arch/loongarch/Kbuild +++ b/arch/loongarch/Kbuild @@ -3,7 +3,7 @@ obj-y += mm/ obj-y += net/ obj-y += vdso/ -obj-$(CONFIG_KVM) += kvm/ +obj-$(subst m,y,$(CONFIG_KVM)) += kvm/ # for cleaning subdir- += boot diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 3b042dbb2c41..606597da46b8 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -220,6 +220,7 @@ menu "Kernel type and options" choice prompt "Kernel type" + default 64BIT # Keep existing behavior config 32BIT bool "32-bit kernel" diff --git a/arch/loongarch/Makefile b/arch/loongarch/Makefile index 47516aeea9d2..54fcfa1eac1f 100644 --- a/arch/loongarch/Makefile +++ b/arch/loongarch/Makefile @@ -55,9 +55,11 @@ endif ifdef CONFIG_32BIT tool-archpref = $(32bit-tool-archpref) UTS_MACHINE := loongarch32 +cflags-y += $(call cc-option,-m32) else tool-archpref = $(64bit-tool-archpref) UTS_MACHINE := loongarch64 +cflags-y += $(call cc-option,-m64) endif ifneq ($(SUBARCH),$(ARCH)) diff --git a/arch/loongarch/include/asm/Kbuild b/arch/loongarch/include/asm/Kbuild index 9034b583a88a..7e92957baf6a 100644 --- a/arch/loongarch/include/asm/Kbuild +++ b/arch/loongarch/include/asm/Kbuild @@ -10,5 +10,6 @@ generic-y += qrwlock.h generic-y += user.h generic-y += ioctl.h generic-y += mmzone.h +generic-y += ring_buffer.h generic-y += statfs.h generic-y += text-patching.h diff --git a/arch/loongarch/include/asm/asm-prototypes.h b/arch/loongarch/include/asm/asm-prototypes.h index 704066b4f736..de0c17f3f49c 100644 --- a/arch/loongarch/include/asm/asm-prototypes.h +++ b/arch/loongarch/include/asm/asm-prototypes.h @@ -20,3 +20,23 @@ asmlinkage void noinstr __no_stack_protector ret_from_kernel_thread(struct task_ struct pt_regs *regs, int (*fn)(void *), void *fn_arg); + +struct kvm_run; +struct kvm_vcpu; +struct loongarch_fpu; + +void kvm_exc_entry(void); +int kvm_enter_guest(struct kvm_run *run, struct kvm_vcpu *vcpu); + +void kvm_save_fpu(struct loongarch_fpu *fpu); +void kvm_restore_fpu(struct loongarch_fpu *fpu); + +#ifdef CONFIG_CPU_HAS_LSX +void kvm_save_lsx(struct loongarch_fpu *fpu); +void kvm_restore_lsx(struct loongarch_fpu *fpu); +#endif + +#ifdef CONFIG_CPU_HAS_LASX +void kvm_save_lasx(struct loongarch_fpu *fpu); +void kvm_restore_lasx(struct loongarch_fpu *fpu); +#endif diff --git a/arch/loongarch/include/asm/efi.h b/arch/loongarch/include/asm/efi.h index eddc8e79b3fa..1ad764b18c3e 100644 --- a/arch/loongarch/include/asm/efi.h +++ b/arch/loongarch/include/asm/efi.h @@ -30,6 +30,8 @@ static inline unsigned long efi_get_kimg_min_align(void) return SZ_2M; } -#define EFI_KIMG_PREFERRED_ADDRESS PHYSADDR(VMLINUX_LOAD_ADDRESS) +unsigned long efi_get_kimg_kaslr_address(void); + +#define EFI_KIMG_PREFERRED_ADDRESS efi_get_kimg_kaslr_address() #endif /* _ASM_LOONGARCH_EFI_H */ diff --git a/arch/loongarch/include/asm/kvm_host.h b/arch/loongarch/include/asm/kvm_host.h index 130cedbb6b39..776bc487a705 100644 --- a/arch/loongarch/include/asm/kvm_host.h +++ b/arch/loongarch/include/asm/kvm_host.h @@ -87,7 +87,6 @@ struct kvm_context { struct kvm_world_switch { int (*exc_entry)(void); int (*enter_guest)(struct kvm_run *run, struct kvm_vcpu *vcpu); - unsigned long page_order; }; #define MAX_PGTABLE_LEVELS 4 @@ -359,8 +358,6 @@ void kvm_exc_entry(void); int kvm_enter_guest(struct kvm_run *run, struct kvm_vcpu *vcpu); extern unsigned long vpid_mask; -extern const unsigned long kvm_exception_size; -extern const unsigned long kvm_enter_guest_size; extern struct kvm_world_switch *kvm_loongarch_ops; #define SW_GCSR (1 << 0) diff --git a/arch/loongarch/include/asm/linkage.h b/arch/loongarch/include/asm/linkage.h index a1bd6a3ee03a..ae937d1708b2 100644 --- a/arch/loongarch/include/asm/linkage.h +++ b/arch/loongarch/include/asm/linkage.h @@ -69,7 +69,7 @@ 9, 10, 11, 12, 13, 14, 15, 16, \ 17, 18, 19, 20, 21, 22, 23, 24, \ 25, 26, 27, 28, 29, 30, 31; \ - .cfi_offset \num, SC_REGS + \num * SZREG; \ + .cfi_offset \num, SC_REGS + \num * 8; \ .endr; \ \ nop; \ diff --git a/arch/loongarch/include/asm/paravirt.h b/arch/loongarch/include/asm/paravirt.h index 0111f0ad5f73..acae1c5e5f88 100644 --- a/arch/loongarch/include/asm/paravirt.h +++ b/arch/loongarch/include/asm/paravirt.h @@ -4,6 +4,12 @@ #ifdef CONFIG_PARAVIRT +#include + +DECLARE_STATIC_KEY_FALSE(virt_preempt_key); +DECLARE_STATIC_KEY_FALSE(virt_spin_lock_key); +DECLARE_PER_CPU(struct kvm_steal_time, steal_time); + int __init pv_ipi_init(void); int __init pv_time_init(void); int __init pv_spinlock_init(void); diff --git a/arch/loongarch/include/asm/qspinlock.h b/arch/loongarch/include/asm/qspinlock.h index 0ee15b3b3937..fbfc6be82f26 100644 --- a/arch/loongarch/include/asm/qspinlock.h +++ b/arch/loongarch/include/asm/qspinlock.h @@ -3,12 +3,9 @@ #define _ASM_LOONGARCH_QSPINLOCK_H #include -#include +#include #ifdef CONFIG_PARAVIRT -DECLARE_STATIC_KEY_FALSE(virt_preempt_key); -DECLARE_STATIC_KEY_FALSE(virt_spin_lock_key); -DECLARE_PER_CPU(struct kvm_steal_time, steal_time); #define virt_spin_lock virt_spin_lock diff --git a/arch/loongarch/include/asm/vdso/gettimeofday.h b/arch/loongarch/include/asm/vdso/gettimeofday.h index bae76767c693..18ba403e1ed9 100644 --- a/arch/loongarch/include/asm/vdso/gettimeofday.h +++ b/arch/loongarch/include/asm/vdso/gettimeofday.h @@ -85,12 +85,6 @@ static __always_inline u64 __arch_get_hw_counter(s32 clock_mode, return count; } -static inline bool loongarch_vdso_hres_capable(void) -{ - return true; -} -#define __arch_vdso_hres_capable loongarch_vdso_hres_capable - #endif /* CONFIG_GENERIC_GETTIMEOFDAY */ #endif /* !__ASSEMBLER__ */ diff --git a/arch/loongarch/kernel/kprobes.c b/arch/loongarch/kernel/kprobes.c index 8ba391cfabb0..1985ed30dd16 100644 --- a/arch/loongarch/kernel/kprobes.c +++ b/arch/loongarch/kernel/kprobes.c @@ -60,16 +60,18 @@ NOKPROBE_SYMBOL(arch_prepare_kprobe); /* Install breakpoint in text */ void arch_arm_kprobe(struct kprobe *p) { - *p->addr = KPROBE_BP_INSN; - flush_insn_slot(p); + u32 insn = KPROBE_BP_INSN; + + larch_insn_text_copy(p->addr, &insn, LOONGARCH_INSN_SIZE); } NOKPROBE_SYMBOL(arch_arm_kprobe); /* Remove breakpoint from text */ void arch_disarm_kprobe(struct kprobe *p) { - *p->addr = p->opcode; - flush_insn_slot(p); + u32 insn = p->opcode; + + larch_insn_text_copy(p->addr, &insn, LOONGARCH_INSN_SIZE); } NOKPROBE_SYMBOL(arch_disarm_kprobe); @@ -184,16 +186,16 @@ static bool reenter_kprobe(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb) { switch (kcb->kprobe_status) { - case KPROBE_HIT_SS: case KPROBE_HIT_SSDONE: case KPROBE_HIT_ACTIVE: kprobes_inc_nmissed_count(p); setup_singlestep(p, regs, kcb, 1); break; + case KPROBE_HIT_SS: case KPROBE_REENTER: pr_warn("Failed to recover from reentered kprobes.\n"); dump_kprobe(p); - WARN_ON_ONCE(1); + BUG(); break; default: WARN_ON(1); diff --git a/arch/loongarch/kernel/relocate.c b/arch/loongarch/kernel/relocate.c index 16f6a9b39659..4b61a9632a98 100644 --- a/arch/loongarch/kernel/relocate.c +++ b/arch/loongarch/kernel/relocate.c @@ -134,11 +134,23 @@ early_param("nokaslr", nokaslr); #define KASLR_DISABLED_MESSAGE "KASLR is disabled by %s in %s cmdline.\n" +/* + * Note: strictly-defined KASLR means the kernel's final runtime address + * has a random offset from the kernel's load address, which is implemented + * in relocate.c; broadly-defined KALSR means the kernel's final runtime + * address has a random offset from the kernel's link address (a.k.a. + * VMLINUX_LOAD_ADDRESS), which also include the efistlub implementation, + * kexec_file implementation and QEMU direct kernel boot. kaslr_disabled() + * return true only means strictly-defined KASLR is disabled. + */ static inline __init bool kaslr_disabled(void) { char *str; const char *builtin_cmdline = CONFIG_CMDLINE; + if (kaslr_offset()) + return true; /* KASLR is performed during early boot. */ + str = strstr(builtin_cmdline, "nokaslr"); if (str == builtin_cmdline || (str > builtin_cmdline && *(str - 1) == ' ')) { pr_info(KASLR_DISABLED_MESSAGE, "\'nokaslr\'", "built-in"); @@ -210,14 +222,52 @@ static inline void __init *determine_relocation_address(void) return RELOCATED_KASLR(destination); } +static unsigned long __init determine_initrd_address(unsigned long *size) +{ + unsigned long start = 0; + unsigned long key_length; + char *p, *endp, *key = "initrd="; + + key_length = strlen(key); + p = strstr(boot_command_line, key); + + if (!p) { + key = "initrdmem="; + key_length = strlen(key); + p = strstr(boot_command_line, key); + } + + if (p == boot_command_line || (p > boot_command_line && *(p - 1) == ' ')) { + p += key_length; + start = memparse(p, &endp); + if (*endp == ',') + *size = memparse(endp + 1, NULL); + } + + return start; +} + static inline int __init relocation_addr_valid(void *location_new) { + unsigned long kernel_start, kernel_size; + unsigned long initrd_start, initrd_size = 0; + if ((unsigned long)location_new & 0x00000ffff) return 0; /* Inappropriately aligned new location */ if ((unsigned long)location_new < (unsigned long)_end) return 0; /* New location overlaps original kernel */ + initrd_start = determine_initrd_address(&initrd_size); + if (initrd_start && initrd_size) { + kernel_start = PHYSADDR(location_new); + kernel_size = (unsigned long)_end - (unsigned long)_text; + + if (kernel_start < (initrd_start + initrd_size) && + initrd_start < (kernel_start + kernel_size)) + return 0; /* initrd/initramfs overlaps kernel */ + } + return 1; } #endif diff --git a/arch/loongarch/kvm/Makefile b/arch/loongarch/kvm/Makefile index ae469edec99c..a4d044da3aa7 100644 --- a/arch/loongarch/kvm/Makefile +++ b/arch/loongarch/kvm/Makefile @@ -7,11 +7,12 @@ include $(srctree)/virt/kvm/Makefile.kvm obj-$(CONFIG_KVM) += kvm.o +obj-y += switch.o + kvm-y += exit.o kvm-y += interrupt.o kvm-y += main.o kvm-y += mmu.o -kvm-y += switch.o kvm-y += timer.o kvm-y += tlb.o kvm-y += vcpu.o diff --git a/arch/loongarch/kvm/exit.c b/arch/loongarch/kvm/exit.c index da0ad89f2eb7..3b95cd0f989b 100644 --- a/arch/loongarch/kvm/exit.c +++ b/arch/loongarch/kvm/exit.c @@ -390,6 +390,7 @@ int kvm_emu_mmio_read(struct kvm_vcpu *vcpu, larch_inst inst) run->mmio.len = 8; break; default: + ret = EMULATE_FAIL; break; } break; diff --git a/arch/loongarch/kvm/interrupt.c b/arch/loongarch/kvm/interrupt.c index 32930959f7c2..a18c60dffbba 100644 --- a/arch/loongarch/kvm/interrupt.c +++ b/arch/loongarch/kvm/interrupt.c @@ -28,23 +28,29 @@ static unsigned int priority_to_irq[EXCCODE_INT_NUM] = { static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority) { unsigned int irq = 0; + unsigned long old, new; clear_bit(priority, &vcpu->arch.irq_pending); if (priority < EXCCODE_INT_NUM) irq = priority_to_irq[priority]; - if (kvm_guest_has_msgint(&vcpu->arch) && (priority == INT_AVEC)) { - dmsintc_inject_irq(vcpu); - set_gcsr_estat(irq); - return 1; - } - switch (priority) { + case INT_AVEC: + if (!kvm_guest_has_msgint(&vcpu->arch)) + break; + dmsintc_inject_irq(vcpu); + fallthrough; case INT_TI: case INT_IPI: case INT_SWI0: case INT_SWI1: + old = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); set_gcsr_estat(irq); + new = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); + + /* Inject TI if TVAL inverted */ + if (new > old) + set_gcsr_estat(CPU_TIMER); break; case INT_HWI0 ... INT_HWI7: @@ -61,22 +67,28 @@ static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority) static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority) { unsigned int irq = 0; + unsigned long old, new; clear_bit(priority, &vcpu->arch.irq_clear); if (priority < EXCCODE_INT_NUM) irq = priority_to_irq[priority]; - if (kvm_guest_has_msgint(&vcpu->arch) && (priority == INT_AVEC)) { - clear_gcsr_estat(irq); - return 1; - } - switch (priority) { + case INT_AVEC: + if (!kvm_guest_has_msgint(&vcpu->arch)) + break; + fallthrough; case INT_TI: case INT_IPI: case INT_SWI0: case INT_SWI1: + old = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); clear_gcsr_estat(irq); + new = kvm_read_hw_gcsr(LOONGARCH_CSR_TVAL); + + /* Inject TI if TVAL inverted */ + if (new > old) + set_gcsr_estat(CPU_TIMER); break; case INT_HWI0 ... INT_HWI7: diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index 76ebff2faedd..f105a86143f5 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -348,8 +348,7 @@ void kvm_arch_disable_virtualization_cpu(void) static int kvm_loongarch_env_init(void) { - int cpu, order, ret; - void *addr; + int cpu, ret; struct kvm_context *context; vmcs = alloc_percpu(struct kvm_context); @@ -365,30 +364,8 @@ static int kvm_loongarch_env_init(void) return -ENOMEM; } - /* - * PGD register is shared between root kernel and kvm hypervisor. - * So world switch entry should be in DMW area rather than TLB area - * to avoid page fault reenter. - * - * In future if hardware pagetable walking is supported, we won't - * need to copy world switch code to DMW area. - */ - order = get_order(kvm_exception_size + kvm_enter_guest_size); - addr = (void *)__get_free_pages(GFP_KERNEL, order); - if (!addr) { - free_percpu(vmcs); - vmcs = NULL; - kfree(kvm_loongarch_ops); - kvm_loongarch_ops = NULL; - return -ENOMEM; - } - - memcpy(addr, kvm_exc_entry, kvm_exception_size); - memcpy(addr + kvm_exception_size, kvm_enter_guest, kvm_enter_guest_size); - flush_icache_range((unsigned long)addr, (unsigned long)addr + kvm_exception_size + kvm_enter_guest_size); - kvm_loongarch_ops->exc_entry = addr; - kvm_loongarch_ops->enter_guest = addr + kvm_exception_size; - kvm_loongarch_ops->page_order = order; + kvm_loongarch_ops->exc_entry = (void *)kvm_exc_entry; + kvm_loongarch_ops->enter_guest = (void *)kvm_enter_guest; vpid_mask = read_csr_gstat(); vpid_mask = (vpid_mask & CSR_GSTAT_GIDBIT) >> CSR_GSTAT_GIDBIT_SHIFT; @@ -428,16 +405,10 @@ static int kvm_loongarch_env_init(void) static void kvm_loongarch_env_exit(void) { - unsigned long addr; - if (vmcs) free_percpu(vmcs); if (kvm_loongarch_ops) { - if (kvm_loongarch_ops->exc_entry) { - addr = (unsigned long)kvm_loongarch_ops->exc_entry; - free_pages(addr, kvm_loongarch_ops->page_order); - } kfree(kvm_loongarch_ops); } diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c index a7fa458e3360..e104897aa532 100644 --- a/arch/loongarch/kvm/mmu.c +++ b/arch/loongarch/kvm/mmu.c @@ -95,7 +95,7 @@ static int kvm_flush_pte(kvm_pte_t *pte, phys_addr_t addr, kvm_ptw_ctx *ctx) else kvm->stat.pages--; - *pte = ctx->invalid_entry; + kvm_set_pte(pte, ctx->invalid_entry); return 1; } diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S index f1768b7a6194..936e4ae3e408 100644 --- a/arch/loongarch/kvm/switch.S +++ b/arch/loongarch/kvm/switch.S @@ -4,9 +4,11 @@ */ #include +#include #include #include #include +#include #include #include @@ -100,11 +102,16 @@ * - is still in guest mode, such as pgd table/vmid registers etc, * - will fix with hw page walk enabled in future * load kvm_vcpu from reserved CSR KVM_VCPU_KS, and save a2 to KVM_TEMP_KS + * + * PGD register is shared between root kernel and kvm hypervisor. + * So world switch entry should be in DMW area rather than TLB area + * to avoid page fault re-enter. */ .text + .p2align PAGE_SHIFT .cfi_sections .debug_frame SYM_CODE_START(kvm_exc_entry) - UNWIND_HINT_UNDEFINED + UNWIND_HINT_END_OF_STACK csrwr a2, KVM_TEMP_KS csrrd a2, KVM_VCPU_KS addi.d a2, a2, KVM_VCPU_ARCH @@ -190,8 +197,8 @@ ret_to_host: kvm_restore_host_gpr a2 jr ra -SYM_INNER_LABEL(kvm_exc_entry_end, SYM_L_LOCAL) SYM_CODE_END(kvm_exc_entry) +EXPORT_SYMBOL_FOR_KVM(kvm_exc_entry) /* * int kvm_enter_guest(struct kvm_run *run, struct kvm_vcpu *vcpu) @@ -215,8 +222,8 @@ SYM_FUNC_START(kvm_enter_guest) /* Save kvm_vcpu to kscratch */ csrwr a1, KVM_VCPU_KS kvm_switch_to_guest -SYM_INNER_LABEL(kvm_enter_guest_end, SYM_L_LOCAL) SYM_FUNC_END(kvm_enter_guest) +EXPORT_SYMBOL_FOR_KVM(kvm_enter_guest) SYM_FUNC_START(kvm_save_fpu) fpu_save_csr a0 t1 @@ -224,6 +231,7 @@ SYM_FUNC_START(kvm_save_fpu) fpu_save_cc a0 t1 t2 jr ra SYM_FUNC_END(kvm_save_fpu) +EXPORT_SYMBOL_FOR_KVM(kvm_save_fpu) SYM_FUNC_START(kvm_restore_fpu) fpu_restore_double a0 t1 @@ -231,6 +239,7 @@ SYM_FUNC_START(kvm_restore_fpu) fpu_restore_cc a0 t1 t2 jr ra SYM_FUNC_END(kvm_restore_fpu) +EXPORT_SYMBOL_FOR_KVM(kvm_restore_fpu) #ifdef CONFIG_CPU_HAS_LSX SYM_FUNC_START(kvm_save_lsx) @@ -239,6 +248,7 @@ SYM_FUNC_START(kvm_save_lsx) lsx_save_data a0 t1 jr ra SYM_FUNC_END(kvm_save_lsx) +EXPORT_SYMBOL_FOR_KVM(kvm_save_lsx) SYM_FUNC_START(kvm_restore_lsx) lsx_restore_data a0 t1 @@ -246,6 +256,7 @@ SYM_FUNC_START(kvm_restore_lsx) fpu_restore_csr a0 t1 t2 jr ra SYM_FUNC_END(kvm_restore_lsx) +EXPORT_SYMBOL_FOR_KVM(kvm_restore_lsx) #endif #ifdef CONFIG_CPU_HAS_LASX @@ -255,6 +266,7 @@ SYM_FUNC_START(kvm_save_lasx) lasx_save_data a0 t1 jr ra SYM_FUNC_END(kvm_save_lasx) +EXPORT_SYMBOL_FOR_KVM(kvm_save_lasx) SYM_FUNC_START(kvm_restore_lasx) lasx_restore_data a0 t1 @@ -262,10 +274,8 @@ SYM_FUNC_START(kvm_restore_lasx) fpu_restore_csr a0 t1 t2 jr ra SYM_FUNC_END(kvm_restore_lasx) +EXPORT_SYMBOL_FOR_KVM(kvm_restore_lasx) #endif - .section ".rodata" -SYM_DATA(kvm_exception_size, .quad kvm_exc_entry_end - kvm_exc_entry) -SYM_DATA(kvm_enter_guest_size, .quad kvm_enter_guest_end - kvm_enter_guest) #ifdef CONFIG_CPU_HAS_LBT STACK_FRAME_NON_STANDARD kvm_restore_fpu diff --git a/arch/loongarch/kvm/timer.c b/arch/loongarch/kvm/timer.c index 29c2aaba63c3..8356fce0043f 100644 --- a/arch/loongarch/kvm/timer.c +++ b/arch/loongarch/kvm/timer.c @@ -96,15 +96,21 @@ void kvm_restore_timer(struct kvm_vcpu *vcpu) * and set CSR TVAL with -1 */ write_gcsr_timertick(0); - __delay(2); /* Wait cycles until timer interrupt injected */ /* * Writing CSR_TINTCLR_TI to LOONGARCH_CSR_TINTCLR will clear * timer interrupt, and CSR TVAL keeps unchanged with -1, it * avoids spurious timer interrupt */ - if (!(estat & CPU_TIMER)) + if (!(estat & CPU_TIMER)) { + __delay(2); /* Wait cycles until timer interrupt injected */ + + /* Write TVAL with max value if no TI shot */ + estat = kvm_read_hw_gcsr(LOONGARCH_CSR_ESTAT); + if (!(estat & CPU_TIMER)) + write_gcsr_timertick(CSR_TCFG_VAL); gcsr_write(CSR_TINTCLR_TI, LOONGARCH_CSR_TINTCLR); + } return; } diff --git a/arch/loongarch/kvm/vm.c b/arch/loongarch/kvm/vm.c index 8cc5ee1c53ef..1317c718f896 100644 --- a/arch/loongarch/kvm/vm.c +++ b/arch/loongarch/kvm/vm.c @@ -125,7 +125,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) r = 1; break; case KVM_CAP_NR_VCPUS: - r = num_online_cpus(); + r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); break; case KVM_CAP_MAX_VCPUS: r = KVM_MAX_VCPUS; diff --git a/arch/loongarch/mm/init.c b/arch/loongarch/mm/init.c index 3f9ab54114c5..031b39eb081c 100644 --- a/arch/loongarch/mm/init.c +++ b/arch/loongarch/mm/init.c @@ -123,11 +123,7 @@ void arch_remove_memory(u64 start, u64 size, struct vmem_altmap *altmap) { unsigned long start_pfn = start >> PAGE_SHIFT; unsigned long nr_pages = size >> PAGE_SHIFT; - struct page *page = pfn_to_page(start_pfn); - /* With altmap the first mapped page is offset from @start */ - if (altmap) - page += vmem_altmap_offset(altmap); __remove_pages(start_pfn, nr_pages, altmap); } #endif diff --git a/arch/loongarch/pci/acpi.c b/arch/loongarch/pci/acpi.c index 0dde3ddcd544..b02698a338ee 100644 --- a/arch/loongarch/pci/acpi.c +++ b/arch/loongarch/pci/acpi.c @@ -61,11 +61,16 @@ static void acpi_release_root_info(struct acpi_pci_root_info *ci) static int acpi_prepare_root_resources(struct acpi_pci_root_info *ci) { int status; + unsigned long long pci_h = 0; struct resource_entry *entry, *tmp; struct acpi_device *device = ci->bridge; status = acpi_pci_probe_root_resources(ci); if (status > 0) { + acpi_evaluate_integer(device->handle, "PCIH", NULL, &pci_h); + if (pci_h) + return status; + resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { if (entry->res->flags & IORESOURCE_MEM) { entry->offset = ci->root->mcfg_addr & GENMASK_ULL(63, 40); diff --git a/arch/loongarch/pci/pci.c b/arch/loongarch/pci/pci.c index d233ea2218fe..f33c7ea1443d 100644 --- a/arch/loongarch/pci/pci.c +++ b/arch/loongarch/pci/pci.c @@ -132,6 +132,9 @@ static void loongson_gpu_fixup_dma_hang(struct pci_dev *pdev, bool on) crtc_reg = regbase; crtc_offset = 0x400; break; + default: + iounmap(regbase); + return; } for (i = 0; i < CRTC_NUM_MAX; i++, crtc_reg += crtc_offset) { diff --git a/arch/loongarch/vdso/Makefile b/arch/loongarch/vdso/Makefile index 42aa96249828..9c9181bb4071 100644 --- a/arch/loongarch/vdso/Makefile +++ b/arch/loongarch/vdso/Makefile @@ -12,6 +12,8 @@ obj-vdso-$(CONFIG_GENERIC_GETTIMEOFDAY) += vgettimeofday.o ccflags-vdso := \ $(filter -I%,$(KBUILD_CFLAGS)) \ $(filter -E%,$(KBUILD_CFLAGS)) \ + $(filter -m32,$(KBUILD_CFLAGS)) \ + $(filter -m64,$(KBUILD_CFLAGS)) \ $(filter -march=%,$(KBUILD_CFLAGS)) \ $(filter -m%-float,$(KBUILD_CFLAGS)) \ $(CLANG_FLAGS) \ diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild index b282e0dd8dc1..62543bf305ff 100644 --- a/arch/m68k/include/asm/Kbuild +++ b/arch/m68k/include/asm/Kbuild @@ -3,5 +3,6 @@ generated-y += syscall_table.h generic-y += extable.h generic-y += kvm_para.h generic-y += mcs_spinlock.h +generic-y += ring_buffer.h generic-y += spinlock.h generic-y += text-patching.h diff --git a/arch/microblaze/include/asm/Kbuild b/arch/microblaze/include/asm/Kbuild index 7178f990e8b3..0030309b47ad 100644 --- a/arch/microblaze/include/asm/Kbuild +++ b/arch/microblaze/include/asm/Kbuild @@ -5,6 +5,7 @@ generic-y += extable.h generic-y += kvm_para.h generic-y += mcs_spinlock.h generic-y += parport.h +generic-y += ring_buffer.h generic-y += syscalls.h generic-y += tlb.h generic-y += user.h diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild index 684569b2ecd6..9771c3d85074 100644 --- a/arch/mips/include/asm/Kbuild +++ b/arch/mips/include/asm/Kbuild @@ -12,5 +12,6 @@ generic-y += mcs_spinlock.h generic-y += parport.h generic-y += qrwlock.h generic-y += qspinlock.h +generic-y += ring_buffer.h generic-y += user.h generic-y += text-patching.h diff --git a/arch/nios2/include/asm/Kbuild b/arch/nios2/include/asm/Kbuild index 28004301c236..0a2530964413 100644 --- a/arch/nios2/include/asm/Kbuild +++ b/arch/nios2/include/asm/Kbuild @@ -5,6 +5,7 @@ generic-y += cmpxchg.h generic-y += extable.h generic-y += kvm_para.h generic-y += mcs_spinlock.h +generic-y += ring_buffer.h generic-y += spinlock.h generic-y += user.h generic-y += text-patching.h diff --git a/arch/nios2/include/asm/linkage.h b/arch/nios2/include/asm/linkage.h index 211302301a8a..c4073235852b 100644 --- a/arch/nios2/include/asm/linkage.h +++ b/arch/nios2/include/asm/linkage.h @@ -12,4 +12,6 @@ #define __ALIGN .align 4 #define __ALIGN_STR ".align 4" +#define _THIS_IP_ ({ unsigned long __ip; asm volatile("nextpc %0" : "=r" (__ip)); __ip; }) + #endif diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild index cef49d60d74c..8aa34621702d 100644 --- a/arch/openrisc/include/asm/Kbuild +++ b/arch/openrisc/include/asm/Kbuild @@ -8,4 +8,5 @@ generic-y += spinlock_types.h generic-y += spinlock.h generic-y += qrwlock_types.h generic-y += qrwlock.h +generic-y += ring_buffer.h generic-y += user.h diff --git a/arch/parisc/Makefile b/arch/parisc/Makefile index edab2a948352..4391783521bd 100644 --- a/arch/parisc/Makefile +++ b/arch/parisc/Makefile @@ -174,15 +174,21 @@ ifeq ($(KBUILD_EXTMOD),) # this hack. prepare: vdso_prepare vdso_prepare: prepare0 - $(if $(CONFIG_64BIT),$(Q)$(MAKE) \ - $(build)=arch/parisc/kernel/vdso64 include/generated/vdso64-offsets.h) - $(if $(CONFIG_PA11)$(CONFIG_COMPAT),$(Q)$(MAKE) \ +ifdef CONFIG_64BIT + $(Q)$(MAKE) $(build)=arch/parisc/kernel/vdso64 include/generated/vdso64-offsets.h + $(if $(CONFIG_COMPAT),$(Q)$(MAKE) \ $(build)=arch/parisc/kernel/vdso32 include/generated/vdso32-offsets.h) +else + $(Q)$(MAKE) $(build)=arch/parisc/kernel/vdso32 include/generated/vdso32-offsets.h +endif endif -vdso-install-$(CONFIG_PA11) += arch/parisc/kernel/vdso32/vdso32.so +ifdef CONFIG_64BIT +vdso-install-y += arch/parisc/kernel/vdso64/vdso64.so vdso-install-$(CONFIG_COMPAT) += arch/parisc/kernel/vdso32/vdso32.so -vdso-install-$(CONFIG_64BIT) += arch/parisc/kernel/vdso64/vdso64.so +else +vdso-install-y += arch/parisc/kernel/vdso32/vdso32.so +endif install: KBUILD_IMAGE := vmlinux zinstall: KBUILD_IMAGE := vmlinuz diff --git a/arch/parisc/include/asm/Kbuild b/arch/parisc/include/asm/Kbuild index 4fb596d94c89..d48d158f7241 100644 --- a/arch/parisc/include/asm/Kbuild +++ b/arch/parisc/include/asm/Kbuild @@ -4,4 +4,5 @@ generated-y += syscall_table_64.h generic-y += agp.h generic-y += kvm_para.h generic-y += mcs_spinlock.h +generic-y += ring_buffer.h generic-y += user.h diff --git a/arch/parisc/include/asm/vdso.h b/arch/parisc/include/asm/vdso.h index 5501560f5ffe..e5cca3c9c8e7 100644 --- a/arch/parisc/include/asm/vdso.h +++ b/arch/parisc/include/asm/vdso.h @@ -6,13 +6,14 @@ #ifdef CONFIG_64BIT #include +#define VDSO64_SYMBOL(tsk, name) ((tsk)->mm->context.vdso_base + (vdso64_offset_##name)) #endif #if !defined(CONFIG_64BIT) || defined(CONFIG_COMPAT) #include -#endif - -#define VDSO64_SYMBOL(tsk, name) ((tsk)->mm->context.vdso_base + (vdso64_offset_##name)) #define VDSO32_SYMBOL(tsk, name) ((tsk)->mm->context.vdso_base + (vdso32_offset_##name)) +#else +#define VDSO32_SYMBOL(tsk, name) 0UL +#endif #endif /* __ASSEMBLER__ */ diff --git a/arch/parisc/kernel/Makefile b/arch/parisc/kernel/Makefile index 2f3441769ac5..49f937c2abbe 100644 --- a/arch/parisc/kernel/Makefile +++ b/arch/parisc/kernel/Makefile @@ -46,6 +46,9 @@ obj-$(CONFIG_KEXEC_FILE) += kexec_file.o # vdso obj-y += vdso.o -obj-$(CONFIG_64BIT) += vdso64/ -obj-$(CONFIG_PA11) += vdso32/ +ifdef CONFIG_64BIT +obj-y += vdso64/ obj-$(CONFIG_COMPAT) += vdso32/ +else +obj-y += vdso32/ +endif diff --git a/arch/parisc/kernel/drivers.c b/arch/parisc/kernel/drivers.c index bc47bbe3026e..b52ad704ec8a 100644 --- a/arch/parisc/kernel/drivers.c +++ b/arch/parisc/kernel/drivers.c @@ -41,9 +41,7 @@ const struct dma_map_ops *hppa_dma_ops __ro_after_init; EXPORT_SYMBOL(hppa_dma_ops); -static struct device root = { - .init_name = "parisc", -}; +static struct device *root; static inline int check_dev(struct device *dev) { @@ -89,7 +87,7 @@ static int for_each_padev(int (*fn)(struct device *, void *), void * data) .obj = data, .fn = fn, }; - return device_for_each_child(&root, &recurse_data, descend_children); + return device_for_each_child(root, &recurse_data, descend_children); } /** @@ -290,7 +288,7 @@ const struct parisc_device * find_pa_parent_type(const struct parisc_device *padev, int type) { const struct device *dev = &padev->dev; - while (dev != &root) { + while (dev != root) { struct parisc_device *candidate = to_parisc_device(dev); if (candidate->id.hw_type == type) return candidate; @@ -319,7 +317,7 @@ static void get_node_path(struct device *dev, struct hardware_path *path) dev = dev->parent; } - while (dev != &root) { + while (dev != root) { if (dev_is_pci(dev)) { unsigned int devfn = to_pci_dev(dev)->devfn; path->bc[i--] = PCI_SLOT(devfn) | (PCI_FUNC(devfn)<< 5); @@ -482,7 +480,7 @@ static struct parisc_device * __init alloc_tree_node( static struct parisc_device *create_parisc_device(struct hardware_path *modpath) { int i; - struct device *parent = &root; + struct device *parent = root; for (i = 0; i < 6; i++) { if (modpath->bc[i] == -1) continue; @@ -755,7 +753,7 @@ parse_tree_node(struct device *parent, int index, struct hardware_path *modpath) struct device *hwpath_to_device(struct hardware_path *modpath) { int i; - struct device *parent = &root; + struct device *parent = root; for (i = 0; i < 6; i++) { if (modpath->bc[i] == -1) continue; @@ -880,7 +878,7 @@ void __init walk_central_bus(void) { walk_native_bus(CENTRAL_BUS_ADDR, CENTRAL_BUS_ADDR + (MAX_NATIVE_DEVICES * NATIVE_DEVICE_OFFSET), - &root); + root); } static __init void print_parisc_device(struct parisc_device *dev) @@ -907,9 +905,10 @@ void __init init_parisc_bus(void) { if (bus_register(&parisc_bus_type)) panic("Could not register PA-RISC bus type\n"); - if (device_register(&root)) + + root = root_device_register("parisc"); + if (IS_ERR(root)) panic("Could not register PA-RISC root device\n"); - get_device(&root); } static __init void qemu_header(void) diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug index f15e5920080b..e8718bc13eeb 100644 --- a/arch/powerpc/Kconfig.debug +++ b/arch/powerpc/Kconfig.debug @@ -83,11 +83,10 @@ config MSI_BITMAP_SELFTEST depends on DEBUG_KERNEL config GUEST_STATE_BUFFER_TEST - def_tristate n + def_tristate KUNIT_ALL_TESTS prompt "Enable Guest State Buffer unit tests" depends on KUNIT depends on KVM_BOOK3S_HV_POSSIBLE - default KUNIT_ALL_TESTS help The Guest State Buffer is a data format specified in the PAPR. It is by hcalls to communicate the state of L2 guests between diff --git a/arch/powerpc/configs/amigaone_defconfig b/arch/powerpc/configs/amigaone_defconfig index 69ef3dc31c4b..7a515390646b 100644 --- a/arch/powerpc/configs/amigaone_defconfig +++ b/arch/powerpc/configs/amigaone_defconfig @@ -76,7 +76,6 @@ CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y CONFIG_FB_TILEBLITTING=y CONFIG_FB_RADEON=y CONFIG_FB_3DFX=y diff --git a/arch/powerpc/configs/chrp32_defconfig b/arch/powerpc/configs/chrp32_defconfig index b799c95480ae..66eae5b7e16c 100644 --- a/arch/powerpc/configs/chrp32_defconfig +++ b/arch/powerpc/configs/chrp32_defconfig @@ -76,7 +76,6 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_NVRAM=y # CONFIG_HWMON is not set CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y CONFIG_FB_OF=y CONFIG_FB_MATROX=y CONFIG_FB_MATROX_MILLENIUM=y diff --git a/arch/powerpc/configs/g5_defconfig b/arch/powerpc/configs/g5_defconfig index 04bbb37f5978..5ca1676e6058 100644 --- a/arch/powerpc/configs/g5_defconfig +++ b/arch/powerpc/configs/g5_defconfig @@ -85,6 +85,8 @@ CONFIG_PMAC_SMU=y CONFIG_MAC_EMUMOUSEBTN=y CONFIG_WINDFARM=y CONFIG_WINDFARM_PM81=y +CONFIG_WINDFARM_PM72=y +CONFIG_WINDFARM_RM31=y CONFIG_WINDFARM_PM91=y CONFIG_WINDFARM_PM112=y CONFIG_WINDFARM_PM121=y @@ -121,7 +123,6 @@ CONFIG_I2C_CHARDEV=y CONFIG_AGP=m CONFIG_AGP_UNINORTH=m CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y CONFIG_FB_TILEBLITTING=y CONFIG_FB_OF=y CONFIG_FB_NVIDIA=y diff --git a/arch/powerpc/configs/pasemi_defconfig b/arch/powerpc/configs/pasemi_defconfig index 8bbf51b38480..89bcbeb05067 100644 --- a/arch/powerpc/configs/pasemi_defconfig +++ b/arch/powerpc/configs/pasemi_defconfig @@ -98,7 +98,6 @@ CONFIG_SENSORS_LM85=y CONFIG_SENSORS_LM90=y CONFIG_DRM=y CONFIG_DRM_RADEON=y -CONFIG_FIRMWARE_EDID=y CONFIG_FB_TILEBLITTING=y CONFIG_FB_VGA16=y CONFIG_FB_NVIDIA=y diff --git a/arch/powerpc/configs/powernv_defconfig b/arch/powerpc/configs/powernv_defconfig index cc9802420237..5d32c2767a65 100644 --- a/arch/powerpc/configs/powernv_defconfig +++ b/arch/powerpc/configs/powernv_defconfig @@ -196,7 +196,6 @@ CONFIG_I2C_CHARDEV=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_DRM=y CONFIG_DRM_AST=y -CONFIG_FIRMWARE_EDID=y CONFIG_FB_OF=y CONFIG_FB_MATROX=m CONFIG_FB_MATROX_MILLENIUM=y diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig index 3bf518e3a573..6316ca4df25d 100644 --- a/arch/powerpc/configs/ppc64_defconfig +++ b/arch/powerpc/configs/ppc64_defconfig @@ -249,7 +249,6 @@ CONFIG_I2C_CHARDEV=y CONFIG_I2C_AMD8111=y CONFIG_I2C_PASEMI=y CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y CONFIG_FB_OF=y CONFIG_FB_MATROX=y CONFIG_FB_MATROX_MILLENIUM=y diff --git a/arch/powerpc/configs/ppc64e_defconfig b/arch/powerpc/configs/ppc64e_defconfig index 0fd49f67331f..20cc17dce94d 100644 --- a/arch/powerpc/configs/ppc64e_defconfig +++ b/arch/powerpc/configs/ppc64e_defconfig @@ -118,7 +118,6 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_AMD8111=y CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y CONFIG_FB_OF=y CONFIG_FB_MATROX=y CONFIG_FB_MATROX_MILLENIUM=y diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index ccabc6e17168..eda1fec7ffd9 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig @@ -393,6 +393,7 @@ CONFIG_NETCONSOLE=m CONFIG_TUN=m CONFIG_VETH=m CONFIG_VIRTIO_NET=m +CONFIG_EL3=m CONFIG_VORTEX=m CONFIG_TYPHOON=m CONFIG_ADAPTEC_STARFIRE=m diff --git a/arch/powerpc/configs/skiroot_defconfig b/arch/powerpc/configs/skiroot_defconfig index ff1bed4b6d2c..005536ee75bb 100644 --- a/arch/powerpc/configs/skiroot_defconfig +++ b/arch/powerpc/configs/skiroot_defconfig @@ -214,7 +214,6 @@ CONFIG_SENSORS_IBMPOWERNV=m CONFIG_DRM=m CONFIG_DRM_AST=m CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild index 2e23533b67e3..805b5aeebb6f 100644 --- a/arch/powerpc/include/asm/Kbuild +++ b/arch/powerpc/include/asm/Kbuild @@ -5,4 +5,5 @@ generated-y += syscall_table_spu.h generic-y += agp.h generic-y += mcs_spinlock.h generic-y += qrwlock.h +generic-y += ring_buffer.h generic-y += early_ioremap.h diff --git a/arch/powerpc/include/asm/pmac_low_i2c.h b/arch/powerpc/include/asm/pmac_low_i2c.h index 21bd7297c87f..fead8fae08ab 100644 --- a/arch/powerpc/include/asm/pmac_low_i2c.h +++ b/arch/powerpc/include/asm/pmac_low_i2c.h @@ -79,10 +79,6 @@ extern int pmac_i2c_match_adapter(struct device_node *dev, struct i2c_adapter *adapter); -/* (legacy) Locking functions exposed to i2c-keywest */ -extern int pmac_low_i2c_lock(struct device_node *np); -extern int pmac_low_i2c_unlock(struct device_node *np); - /* Access functions for platform code */ extern int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled); extern void pmac_i2c_close(struct pmac_i2c_bus *bus); diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 4bbeb8644d3d..b4472288e0d4 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -458,6 +458,10 @@ DEFINE_PER_CPU(u8, irq_work_pending); #endif /* 32 vs 64 bit */ +/* + * Must be called with preemption disabled since it updates + * per-CPU irq_work state and programs the local CPU decrementer. + */ void arch_irq_work_raise(void) { /* @@ -471,10 +475,8 @@ void arch_irq_work_raise(void) * which could get tangled up if we're messing with the same state * here. */ - preempt_disable(); set_irq_work_pending_flag(); set_dec(1); - preempt_enable(); } static void set_dec_or_work(u64 val) diff --git a/arch/powerpc/kernel/vdso/Makefile b/arch/powerpc/kernel/vdso/Makefile index 8834dfe9d727..368759f81708 100644 --- a/arch/powerpc/kernel/vdso/Makefile +++ b/arch/powerpc/kernel/vdso/Makefile @@ -62,6 +62,12 @@ CC32FLAGSREMOVE += -fno-stack-clash-protection # 32-bit one. clang validates the values passed to these arguments during # parsing, even when -fno-stack-protector is passed afterwards. CC32FLAGSREMOVE += -mstack-protector-guard% +# ftrace is disabled for the vdso but arch/powerpc/Makefile adds this define to +# KBUILD_CPPFLAGS, which enables use of the 'patchable_function_entry' +# attribute in the 'inline' define via 'notrace'. This attribute is not +# supported for the powerpcle target, resulting in many instances of +# -Wunknown-attributes. +CC32FLAGSREMOVE += -DCC_USING_PATCHABLE_FUNCTION_ENTRY endif LD32FLAGS := -Wl,-soname=linux-vdso32.so.1 AS32FLAGS := -D__VDSO32__ diff --git a/arch/powerpc/kexec/Makefile b/arch/powerpc/kexec/Makefile index 470eb0453e17..ec7a0eed75dc 100644 --- a/arch/powerpc/kexec/Makefile +++ b/arch/powerpc/kexec/Makefile @@ -16,4 +16,4 @@ GCOV_PROFILE_core_$(BITS).o := n KCOV_INSTRUMENT_core_$(BITS).o := n UBSAN_SANITIZE_core_$(BITS).o := n KASAN_SANITIZE_core.o := n -KASAN_SANITIZE_core_$(BITS) := n +KASAN_SANITIZE_core_$(BITS).o := n diff --git a/arch/powerpc/lib/vmx-helper.c b/arch/powerpc/lib/vmx-helper.c index 554b248002b4..57e897b60db8 100644 --- a/arch/powerpc/lib/vmx-helper.c +++ b/arch/powerpc/lib/vmx-helper.c @@ -52,7 +52,14 @@ int exit_vmx_usercopy(void) } EXPORT_SYMBOL(exit_vmx_usercopy); -int enter_vmx_ops(void) +/* + * Can be called from kexec copy_page() path with MMU off. The kexec + * code sets preempt_count to HARDIRQ_OFFSET so we return early here. + * Since in_interrupt() is always inline, __no_sanitize_address on this + * function is sufficient to avoid KASAN shadow memory accesses in real + * mode. + */ +int __no_sanitize_address enter_vmx_ops(void) { if (in_interrupt()) return 0; diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 8b0081441f85..2e6adf5b95c4 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -2242,6 +2242,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val, const u64 last_period = event->hw.last_period; s64 prev, delta, left; int record = 0; + int mark_event = regs->dsisr & MMCRA_SAMPLE_ENABLE; if (event->hw.state & PERF_HES_STOPPED) { write_pmc(event->hw.idx, 0); @@ -2304,9 +2305,9 @@ static void record_and_restart(struct perf_event *event, unsigned long val, * In ISA v3.0 and before values "0" and "7" are considered reserved. * In ISA v3.1, value "7" has been used to indicate "larx/stcx". * Drop the sample if "type" has reserved values for this field with a - * ISA version check. + * ISA version check for marked events. */ - if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && + if (mark_event && event->attr.sample_type & PERF_SAMPLE_DATA_SRC && ppmu->get_mem_data_src) { val = (regs->dar & SIER_TYPE_MASK) >> SIER_TYPE_SHIFT; if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31))) { diff --git a/arch/powerpc/perf/hv-gpci.c b/arch/powerpc/perf/hv-gpci.c index 5cac2cf3bd1e..10c82cf8f5b3 100644 --- a/arch/powerpc/perf/hv-gpci.c +++ b/arch/powerpc/perf/hv-gpci.c @@ -210,7 +210,7 @@ static ssize_t processor_bus_topology_show(struct device *dev, struct device_att 0, 0, buf, &n, arg); if (!ret) - return n; + goto out_success; if (ret != H_PARAMETER) goto out; @@ -244,12 +244,14 @@ static ssize_t processor_bus_topology_show(struct device *dev, struct device_att starting_index, 0, buf, &n, arg); if (!ret) - return n; + goto out_success; if (ret != H_PARAMETER) goto out; } +out_success: + put_cpu_var(hv_gpci_reqb); return n; out: @@ -278,7 +280,7 @@ static ssize_t processor_config_show(struct device *dev, struct device_attribute 0, 0, buf, &n, arg); if (!ret) - return n; + goto out_success; if (ret != H_PARAMETER) goto out; @@ -312,12 +314,14 @@ static ssize_t processor_config_show(struct device *dev, struct device_attribute starting_index, 0, buf, &n, arg); if (!ret) - return n; + goto out_success; if (ret != H_PARAMETER) goto out; } +out_success: + put_cpu_var(hv_gpci_reqb); return n; out: @@ -346,7 +350,7 @@ static ssize_t affinity_domain_via_virtual_processor_show(struct device *dev, 0, 0, buf, &n, arg); if (!ret) - return n; + goto out_success; if (ret != H_PARAMETER) goto out; @@ -382,12 +386,14 @@ static ssize_t affinity_domain_via_virtual_processor_show(struct device *dev, starting_index, secondary_index, buf, &n, arg); if (!ret) - return n; + goto out_success; if (ret != H_PARAMETER) goto out; } +out_success: + put_cpu_var(hv_gpci_reqb); return n; out: @@ -416,7 +422,7 @@ static ssize_t affinity_domain_via_domain_show(struct device *dev, struct device 0, 0, buf, &n, arg); if (!ret) - return n; + goto out_success; if (ret != H_PARAMETER) goto out; @@ -448,12 +454,14 @@ static ssize_t affinity_domain_via_domain_show(struct device *dev, struct device starting_index, 0, buf, &n, arg); if (!ret) - return n; + goto out_success; if (ret != H_PARAMETER) goto out; } +out_success: + put_cpu_var(hv_gpci_reqb); return n; out: diff --git a/arch/powerpc/platforms/44x/warp.c b/arch/powerpc/platforms/44x/warp.c index a5001d32f978..6f674f86dc85 100644 --- a/arch/powerpc/platforms/44x/warp.c +++ b/arch/powerpc/platforms/44x/warp.c @@ -293,6 +293,8 @@ static int pika_dtm_thread(void __iomem *fpga) schedule_timeout(HZ); } + put_device(&client->dev); + return 0; } diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c index 99f0f0f41876..4ad223525e89 100644 --- a/arch/powerpc/platforms/82xx/km82xx.c +++ b/arch/powerpc/platforms/82xx/km82xx.c @@ -27,8 +27,8 @@ static void __init km82xx_pic_init(void) { - struct device_node *np __free(device_node); - np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic"); + struct device_node *np __free(device_node) = of_find_compatible_node(NULL, + NULL, "fsl,pq2-pic"); if (!np) { pr_err("PIC init: can not find cpm-pic node\n"); diff --git a/arch/powerpc/platforms/8xx/cpm1.c b/arch/powerpc/platforms/8xx/cpm1.c index 7433be7d66ee..f00734f0590c 100644 --- a/arch/powerpc/platforms/8xx/cpm1.c +++ b/arch/powerpc/platforms/8xx/cpm1.c @@ -477,7 +477,7 @@ int cpm1_gpiochip_add16(struct device *dev) struct device_node *np = dev->of_node; struct cpm1_gpio16_chip *cpm1_gc; struct gpio_chip *gc; - u16 mask; + u32 mask; cpm1_gc = devm_kzalloc(dev, sizeof(*cpm1_gc), GFP_KERNEL); if (!cpm1_gc) @@ -485,7 +485,7 @@ int cpm1_gpiochip_add16(struct device *dev) spin_lock_init(&cpm1_gc->lock); - if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) { + if (!of_property_read_u32(np, "fsl,cpm1-gpio-irq-mask", &mask)) { int i, j; for (i = 0, j = 0; i < 16; i++) diff --git a/arch/powerpc/platforms/pasemi/pci.c b/arch/powerpc/platforms/pasemi/pci.c index 60f990a336c4..2df955274652 100644 --- a/arch/powerpc/platforms/pasemi/pci.c +++ b/arch/powerpc/platforms/pasemi/pci.c @@ -272,13 +272,12 @@ void __init pas_pci_init(void) { struct device_node *root = of_find_node_by_path("/"); struct device_node *np; - int res; pci_set_flags(PCI_SCAN_ALL_PCIE_DEVS); np = of_find_compatible_node(root, NULL, "pasemi,rootbus"); if (np) { - res = pas_add_bridge(np); + pas_add_bridge(np); of_node_put(np); } of_node_put(root); diff --git a/arch/powerpc/platforms/powermac/low_i2c.c b/arch/powerpc/platforms/powermac/low_i2c.c index 73b7f4e8c047..da72a30ab865 100644 --- a/arch/powerpc/platforms/powermac/low_i2c.c +++ b/arch/powerpc/platforms/powermac/low_i2c.c @@ -1058,40 +1058,6 @@ int pmac_i2c_match_adapter(struct device_node *dev, struct i2c_adapter *adapter) } EXPORT_SYMBOL_GPL(pmac_i2c_match_adapter); -int pmac_low_i2c_lock(struct device_node *np) -{ - struct pmac_i2c_bus *bus, *found = NULL; - - list_for_each_entry(bus, &pmac_i2c_busses, link) { - if (np == bus->controller) { - found = bus; - break; - } - } - if (!found) - return -ENODEV; - return pmac_i2c_open(bus, 0); -} -EXPORT_SYMBOL_GPL(pmac_low_i2c_lock); - -int pmac_low_i2c_unlock(struct device_node *np) -{ - struct pmac_i2c_bus *bus, *found = NULL; - - list_for_each_entry(bus, &pmac_i2c_busses, link) { - if (np == bus->controller) { - found = bus; - break; - } - } - if (!found) - return -ENODEV; - pmac_i2c_close(bus); - return 0; -} -EXPORT_SYMBOL_GPL(pmac_low_i2c_unlock); - - int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled) { int rc; diff --git a/arch/powerpc/platforms/ps3/device-init.c b/arch/powerpc/platforms/ps3/device-init.c index 12c473768c39..9109c218a060 100644 --- a/arch/powerpc/platforms/ps3/device-init.c +++ b/arch/powerpc/platforms/ps3/device-init.c @@ -950,8 +950,6 @@ static int __init ps3_start_probe_thread(enum ps3_bus_type bus_type) static int __init ps3_register_devices(void) { - int result; - if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) return -ENODEV; @@ -959,7 +957,7 @@ static int __init ps3_register_devices(void) /* ps3_repository_dump_bus_info(); */ - result = ps3_start_probe_thread(PS3_BUS_TYPE_STORAGE); + ps3_start_probe_thread(PS3_BUS_TYPE_STORAGE); ps3_register_vuart_devices(); diff --git a/arch/powerpc/platforms/pseries/htmdump.c b/arch/powerpc/platforms/pseries/htmdump.c index 742ec52c9d4d..489a80e87082 100644 --- a/arch/powerpc/platforms/pseries/htmdump.c +++ b/arch/powerpc/platforms/pseries/htmdump.c @@ -16,6 +16,7 @@ static void *htm_buf; static void *htm_status_buf; static void *htm_info_buf; static void *htm_caps_buf; +static void *htm_mem_buf; static u32 nodeindex; static u32 nodalchipindex; static u32 coreindexonchip; @@ -86,7 +87,7 @@ static ssize_t htm_return_check(long rc) static ssize_t htmdump_read(struct file *filp, char __user *ubuf, size_t count, loff_t *ppos) { - void *htm_buf = filp->private_data; + void *htm_buf_data = filp->private_data; unsigned long page, read_size, available; loff_t offset; long rc, ret; @@ -100,7 +101,7 @@ static ssize_t htmdump_read(struct file *filp, char __user *ubuf, * - last three values are address, size and offset */ rc = htm_hcall_wrapper(htmflags, nodeindex, nodalchipindex, coreindexonchip, - htmtype, H_HTM_OP_DUMP_DATA, virt_to_phys(htm_buf), + htmtype, H_HTM_OP_DUMP_DATA, virt_to_phys(htm_buf_data), PAGE_SIZE, page); ret = htm_return_check(rc); @@ -112,7 +113,61 @@ static ssize_t htmdump_read(struct file *filp, char __user *ubuf, available = PAGE_SIZE; read_size = min(count, available); *ppos += read_size; - return simple_read_from_buffer(ubuf, count, &offset, htm_buf, available); + return simple_read_from_buffer(ubuf, count, &offset, htm_buf_data, available); +} + +static ssize_t htmsystem_mem_read(struct file *filp, char __user *ubuf, + size_t count, loff_t *ppos) +{ + void *htm_mem_data = filp->private_data; + long rc, ret; + u64 *num_entries; + u64 to_copy = 0; + loff_t offset = 0; + u64 mem_offset = 0; + + /* + * Invoke H_HTM call with: + * - operation as htm status (H_HTM_OP_STATUS) + * - last three values as addr, size and offset. "offset" + * is value from output buffer header that points to next + * entry to dump. 0 is the first entry to dump. next entry + * is read from the output bufferbyte offset 0x8. + * + * When first time hcall is invoked, mem_offset should be + * zero because zero is the first entry. + * In the next hcall, offset of next entry to read from is + * picked from output buffer header itself. So don't fill + * mem_offset for first read. + * + * If there is no further data to read in next iteration, + * offset value from output buffer header will point to -1. + */ + if (*ppos) { + mem_offset = *(u64 *)(htm_mem_data + 0x8); + if (mem_offset == -1) + return 0; + } + rc = htm_hcall_wrapper(htmflags, nodeindex, nodalchipindex, coreindexonchip, + htmtype, H_HTM_OP_DUMP_SYSMEM_CONF, virt_to_phys(htm_mem_data), + PAGE_SIZE, be64_to_cpu(mem_offset)); + ret = htm_return_check(rc); + if (ret <= 0) { + pr_debug("H_HTM hcall returned for op: H_HTM_OP_DUMP_SYSMEM_CONF with hcall returning %ld\n", ret); + return ret; + } + + /* + * HTM system mem buffer, start of buffer + 0x10 gives the + * number of HTM entries in the buffer. + * So total count to copy is: + * 32 bytes (for first 5 fields) + (number of HTM entries * entry size) + */ + num_entries = htm_mem_data + 0x10; + to_copy = 32 + (be64_to_cpu(*num_entries) * 32); + + *ppos += to_copy; + return simple_read_from_buffer(ubuf, count, &offset, htm_mem_data, to_copy); } static const struct file_operations htmdump_fops = { @@ -121,6 +176,12 @@ static const struct file_operations htmdump_fops = { .open = simple_open, }; +static const struct file_operations htmsystem_mem_fops = { + .llseek = NULL, + .read = htmsystem_mem_read, + .open = simple_open, +}; + static int htmconfigure_set(void *data, u64 val) { long rc, ret; @@ -226,20 +287,31 @@ static int htmstart_get(void *data, u64 *val) static ssize_t htmstatus_read(struct file *filp, char __user *ubuf, size_t count, loff_t *ppos) { - void *htm_status_buf = filp->private_data; + void *htm_status_data = filp->private_data; long rc, ret; u64 *num_entries; u64 to_copy; int htmstatus_flag; + loff_t offset = 0; + u64 status_offset = 0; /* * Invoke H_HTM call with: * - operation as htm status (H_HTM_OP_STATUS) - * - last three values as addr, size and offset + * - last three values as addr, size and offset. + * "offset" is value from output buffer header + * that points to next entry to dump. 0 is the first + * entry to dump. next entry is read from the output + * bufferbyte offset 0x8. */ + if (*ppos) { + status_offset = *(u64 *)(htm_status_data + 0x8); + if (status_offset == -1) + return 0; + } rc = htm_hcall_wrapper(htmflags, nodeindex, nodalchipindex, coreindexonchip, - htmtype, H_HTM_OP_STATUS, virt_to_phys(htm_status_buf), - PAGE_SIZE, 0); + htmtype, H_HTM_OP_STATUS, virt_to_phys(htm_status_data), + PAGE_SIZE, be64_to_cpu(status_offset)); ret = htm_return_check(rc); if (ret <= 0) { @@ -255,13 +327,15 @@ static ssize_t htmstatus_read(struct file *filp, char __user *ubuf, * So total count to copy is: * 32 bytes (for first 7 fields) + (number of HTM entries * entry size) */ - num_entries = htm_status_buf + 0x10; + num_entries = htm_status_data + 0x10; if (htmtype == 0x2) htmstatus_flag = 0x8; else htmstatus_flag = 0x6; to_copy = 32 + (be64_to_cpu(*num_entries) * htmstatus_flag); - return simple_read_from_buffer(ubuf, count, ppos, htm_status_buf, to_copy); + *ppos += to_copy; + + return simple_read_from_buffer(ubuf, count, &offset, htm_status_data, to_copy); } static const struct file_operations htmstatus_fops = { @@ -273,19 +347,30 @@ static const struct file_operations htmstatus_fops = { static ssize_t htminfo_read(struct file *filp, char __user *ubuf, size_t count, loff_t *ppos) { - void *htm_info_buf = filp->private_data; + void *htm_info_data = filp->private_data; long rc, ret; u64 *num_entries; u64 to_copy; + loff_t offset = 0; + u64 info_offset = 0; /* * Invoke H_HTM call with: * - operation as htm status (H_HTM_OP_STATUS) * - last three values as addr, size and offset + * "offset" is value from output buffer header + * that points to next entry to dump. 0 is the first + * entry to dump. next entry is read from the output + * bufferbyte offset 0x8. */ + if (*ppos) { + info_offset = *(u64 *)(htm_info_data + 0x8); + if (info_offset == -1) + return 0; + } rc = htm_hcall_wrapper(htmflags, nodeindex, nodalchipindex, coreindexonchip, - htmtype, H_HTM_OP_DUMP_SYSPROC_CONF, virt_to_phys(htm_info_buf), - PAGE_SIZE, 0); + htmtype, H_HTM_OP_DUMP_SYSPROC_CONF, virt_to_phys(htm_info_data), + PAGE_SIZE, be64_to_cpu(info_offset)); ret = htm_return_check(rc); if (ret <= 0) { @@ -301,15 +386,17 @@ static ssize_t htminfo_read(struct file *filp, char __user *ubuf, * So total count to copy is: * 32 bytes (for first 5 fields) + (number of HTM entries * entry size) */ - num_entries = htm_info_buf + 0x10; + num_entries = htm_info_data + 0x10; to_copy = 32 + (be64_to_cpu(*num_entries) * 16); - return simple_read_from_buffer(ubuf, count, ppos, htm_info_buf, to_copy); + + *ppos += to_copy; + return simple_read_from_buffer(ubuf, count, &offset, htm_info_data, to_copy); } static ssize_t htmcaps_read(struct file *filp, char __user *ubuf, size_t count, loff_t *ppos) { - void *htm_caps_buf = filp->private_data; + void *htm_caps_data = filp->private_data; long rc, ret; /* @@ -319,7 +406,7 @@ static ssize_t htmcaps_read(struct file *filp, char __user *ubuf, * and zero */ rc = htm_hcall_wrapper(htmflags, nodeindex, nodalchipindex, coreindexonchip, - htmtype, H_HTM_OP_CAPABILITIES, virt_to_phys(htm_caps_buf), + htmtype, H_HTM_OP_CAPABILITIES, virt_to_phys(htm_caps_data), 0x80, 0); ret = htm_return_check(rc); @@ -328,7 +415,7 @@ static ssize_t htmcaps_read(struct file *filp, char __user *ubuf, return ret; } - return simple_read_from_buffer(ubuf, count, ppos, htm_caps_buf, 0x80); + return simple_read_from_buffer(ubuf, count, ppos, htm_caps_data, 0x80); } static const struct file_operations htminfo_fops = { @@ -457,9 +544,17 @@ static int htmdump_init_debugfs(void) return -ENOMEM; } + /* Memory to present HTM system memory configuration */ + htm_mem_buf = kmalloc(PAGE_SIZE, GFP_KERNEL); + if (!htm_mem_buf) { + pr_err("Failed to allocate htm mem buf\n"); + return -ENOMEM; + } + debugfs_create_file("htmstatus", 0400, htmdump_debugfs_dir, htm_status_buf, &htmstatus_fops); debugfs_create_file("htminfo", 0400, htmdump_debugfs_dir, htm_info_buf, &htminfo_fops); debugfs_create_file("htmcaps", 0400, htmdump_debugfs_dir, htm_caps_buf, &htmcaps_fops); + debugfs_create_file("htmsystem_mem", 0400, htmdump_debugfs_dir, htm_mem_buf, &htmsystem_mem_fops); return 0; } @@ -482,6 +577,10 @@ static void __exit htmdump_exit(void) { debugfs_remove_recursive(htmdump_debugfs_dir); kfree(htm_buf); + kfree(htm_status_buf); + kfree(htm_info_buf); + kfree(htm_caps_buf); + kfree(htm_mem_buf); } module_init(htmdump_init); diff --git a/arch/powerpc/platforms/pseries/papr-hvpipe.c b/arch/powerpc/platforms/pseries/papr-hvpipe.c index 14ae480d060a..0c40bdde45e2 100644 --- a/arch/powerpc/platforms/pseries/papr-hvpipe.c +++ b/arch/powerpc/platforms/pseries/papr-hvpipe.c @@ -190,33 +190,34 @@ static int hvpipe_rtas_recv_msg(char __user *buf, int size) return -ENOMEM; } - ret = rtas_ibm_receive_hvpipe_msg(work_area, &srcID, - &bytes_written); - if (!ret) { - /* - * Recv HVPIPE RTAS is successful. - * When releasing FD or no one is waiting on the - * specific source, issue recv HVPIPE RTAS call - * so that pipe is not blocked - this func is called - * with NULL buf. - */ - if (buf) { - if (size < bytes_written) { - pr_err("Received the payload size = %d, but the buffer size = %d\n", - bytes_written, size); - bytes_written = size; - } - ret = copy_to_user(buf, - rtas_work_area_raw_buf(work_area), - bytes_written); - if (!ret) - ret = bytes_written; - } - } else { - pr_err("ibm,receive-hvpipe-msg failed with %d\n", - ret); + /* + * Recv HVPIPE RTAS is successful. + * When releasing FD or no one is waiting on the + * specific source, issue recv HVPIPE RTAS call + * so that pipe is not blocked - this func is called + * with NULL buf. + */ + ret = rtas_ibm_receive_hvpipe_msg(work_area, &srcID, &bytes_written); + if (ret) { + pr_err("ibm,receive-hvpipe-msg failed with %d\n", ret); + goto out; } + if (!buf) + goto out; + + if (size < bytes_written) { + pr_err("Received the payload size = %d, but the buffer size = %d\n", + bytes_written, size); + bytes_written = size; + } + + if (copy_to_user(buf, rtas_work_area_raw_buf(work_area), bytes_written)) + ret = -EFAULT; + else + ret = bytes_written; + +out: rtas_work_area_free(work_area); return ret; } @@ -327,8 +328,8 @@ static ssize_t papr_hvpipe_handle_read(struct file *file, { struct hvpipe_source_info *src_info = file->private_data; - struct papr_hvpipe_hdr hdr; - long ret; + struct papr_hvpipe_hdr hdr = {}; + ssize_t ret = 0; /* * Return -ENXIO during migration @@ -376,7 +377,7 @@ static ssize_t papr_hvpipe_handle_read(struct file *file, ret = copy_to_user(buf, &hdr, HVPIPE_HDR_LEN); if (ret) - return ret; + return -EFAULT; /* * Message event has payload, so get the payload with @@ -385,19 +386,23 @@ static ssize_t papr_hvpipe_handle_read(struct file *file, if (hdr.flags & HVPIPE_MSG_AVAILABLE) { ret = hvpipe_rtas_recv_msg(buf + HVPIPE_HDR_LEN, size - HVPIPE_HDR_LEN); - if (ret > 0) { + /* + * Always clear MSG_AVAILABLE once the RTAS call has drained + * the message, regardless of whether copy_to_user succeeded. + */ + if (ret >= 0 || ret == -EFAULT) src_info->hvpipe_status &= ~HVPIPE_MSG_AVAILABLE; - ret += HVPIPE_HDR_LEN; - } } else if (hdr.flags & HVPIPE_LOST_CONNECTION) { /* * Hypervisor is closing the pipe for the specific * source. So notify user space. */ src_info->hvpipe_status &= ~HVPIPE_LOST_CONNECTION; - ret = HVPIPE_HDR_LEN; } + if (ret >= 0) + ret += HVPIPE_HDR_LEN; + return ret; } @@ -444,16 +449,18 @@ static int papr_hvpipe_handle_release(struct inode *inode, struct file *file) { struct hvpipe_source_info *src_info; + unsigned long flags; /* * Hold the lock, remove source from src_list, reset the * hvpipe status and release the lock to prevent any race * with message event IRQ. */ - spin_lock(&hvpipe_src_list_lock); + spin_lock_irqsave(&hvpipe_src_list_lock, flags); src_info = file->private_data; list_del(&src_info->list); file->private_data = NULL; + spin_unlock_irqrestore(&hvpipe_src_list_lock, flags); /* * If the pipe for this specific source has any pending * payload, issue recv HVPIPE RTAS so that pipe will not @@ -461,10 +468,8 @@ static int papr_hvpipe_handle_release(struct inode *inode, */ if (src_info->hvpipe_status & HVPIPE_MSG_AVAILABLE) { src_info->hvpipe_status = 0; - spin_unlock(&hvpipe_src_list_lock); hvpipe_rtas_recv_msg(NULL, 0); - } else - spin_unlock(&hvpipe_src_list_lock); + } kfree(src_info); return 0; @@ -479,50 +484,53 @@ static const struct file_operations papr_hvpipe_handle_ops = { static int papr_hvpipe_dev_create_handle(u32 srcID) { - struct hvpipe_source_info *src_info __free(kfree) = NULL; - - spin_lock(&hvpipe_src_list_lock); - /* - * Do not allow more than one process communicates with - * each source. - */ - src_info = hvpipe_find_source(srcID); - if (src_info) { - spin_unlock(&hvpipe_src_list_lock); - pr_err("pid(%d) is already using the source(%d)\n", - src_info->tsk->pid, srcID); - return -EALREADY; - } - spin_unlock(&hvpipe_src_list_lock); + struct hvpipe_source_info *src_info; + int fd; + unsigned long flags; src_info = kzalloc_obj(*src_info, GFP_KERNEL_ACCOUNT); if (!src_info) return -ENOMEM; src_info->srcID = srcID; - src_info->tsk = current; init_waitqueue_head(&src_info->recv_wqh); - FD_PREPARE(fdf, O_RDONLY | O_CLOEXEC, - anon_inode_getfile("[papr-hvpipe]", &papr_hvpipe_handle_ops, - (void *)src_info, O_RDWR)); - if (fdf.err) - return fdf.err; - - retain_and_null_ptr(src_info); - spin_lock(&hvpipe_src_list_lock); /* - * If two processes are executing ioctl() for the same - * source ID concurrently, prevent the second process to - * acquire FD. + * Do not allow more than one process communicates with + * each source. */ + spin_lock_irqsave(&hvpipe_src_list_lock, flags); if (hvpipe_find_source(srcID)) { - spin_unlock(&hvpipe_src_list_lock); + spin_unlock_irqrestore(&hvpipe_src_list_lock, flags); + pr_err("pid(%s:%d) could not get the source(%d)\n", + current->comm, task_pid_nr(current), srcID); + kfree(src_info); return -EALREADY; } list_add(&src_info->list, &hvpipe_src_list); - spin_unlock(&hvpipe_src_list_lock); - return fd_publish(fdf); + spin_unlock_irqrestore(&hvpipe_src_list_lock, flags); + + fd = FD_ADD(O_RDONLY | O_CLOEXEC, + anon_inode_getfile("[papr-hvpipe]", &papr_hvpipe_handle_ops, + (void *)src_info, O_RDWR)); + if (fd < 0) { + spin_lock_irqsave(&hvpipe_src_list_lock, flags); + list_del(&src_info->list); + spin_unlock_irqrestore(&hvpipe_src_list_lock, flags); + /* + * if we fail to add FD, that means no userspace program is + * polling. In that case if there is a msg pending because the + * interrupt was fired after the src_info was added to the + * global list, then let's consume it here, to unblock the + * hvpipe + */ + if (src_info->hvpipe_status & HVPIPE_MSG_AVAILABLE) + hvpipe_rtas_recv_msg(NULL, 0); + kfree(src_info); + return fd; + } + + return fd; } /* @@ -685,20 +693,19 @@ static int __init enable_hvpipe_IRQ(void) struct device_node *np; hvpipe_check_exception_token = rtas_function_token(RTAS_FN_CHECK_EXCEPTION); - if (hvpipe_check_exception_token == RTAS_UNKNOWN_SERVICE) + if (hvpipe_check_exception_token == RTAS_UNKNOWN_SERVICE) return -ENODEV; /* hvpipe events */ np = of_find_node_by_path("/event-sources/ibm,hvpipe-msg-events"); - if (np != NULL) { - request_event_sources_irqs(np, hvpipe_event_interrupt, - "HPIPE_EVENT"); - of_node_put(np); - } else { - pr_err("Can not enable hvpipe event IRQ\n"); + if (!np) { + pr_err("No device node found, could not enable hvpipe event IRQ\n"); return -ENODEV; } + request_event_sources_irqs(np, hvpipe_event_interrupt, "HPIPE_EVENT"); + of_node_put(np); + return 0; } @@ -775,23 +782,29 @@ static int __init papr_hvpipe_init(void) } ret = enable_hvpipe_IRQ(); - if (!ret) { - ret = set_hvpipe_sys_param(1); - if (!ret) - ret = misc_register(&papr_hvpipe_dev); - } + if (ret) + goto out_wq; - if (!ret) { - pr_info("hvpipe feature is enabled\n"); - hvpipe_feature = true; - return 0; - } + ret = misc_register(&papr_hvpipe_dev); + if (ret) + goto out_wq; - pr_err("hvpipe feature is not enabled %d\n", ret); + ret = set_hvpipe_sys_param(1); + if (ret) + goto out_misc; + + pr_info("hvpipe feature is enabled\n"); + hvpipe_feature = true; + return 0; + +out_misc: + misc_deregister(&papr_hvpipe_dev); +out_wq: destroy_workqueue(papr_hvpipe_wq); out: kfree(papr_hvpipe_work); papr_hvpipe_work = NULL; + pr_err("hvpipe feature is not enabled %d\n", ret); return ret; } machine_device_initcall(pseries, papr_hvpipe_init); diff --git a/arch/powerpc/platforms/pseries/papr-hvpipe.h b/arch/powerpc/platforms/pseries/papr-hvpipe.h index c343f4230865..4bdf7bb2fc4d 100644 --- a/arch/powerpc/platforms/pseries/papr-hvpipe.h +++ b/arch/powerpc/platforms/pseries/papr-hvpipe.h @@ -21,7 +21,6 @@ struct hvpipe_source_info { u32 srcID; u32 hvpipe_status; wait_queue_head_t recv_wqh; /* wake up poll() waitq */ - struct task_struct *tsk; }; /* diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d235396c4514..c5754942cf85 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -937,6 +937,28 @@ config RISCV_VECTOR_MISALIGNED help Enable detecting support for vector misaligned loads and stores. +config RISCV_SBI_FWFT_DELEGATE_MISALIGNED + bool "Request firmware delegation of unaligned access exceptions" + depends on RISCV_SBI + depends on NONPORTABLE + help + Use SBI FWFT to request delegation of load address misaligned and + store address misaligned exceptions, if possible, and prefer Linux + kernel emulation of these accesses to firmware emulation. + + Unfortunately, Linux's emulation is still incomplete. Namely, it + currently does not handle vector instructions and KVM guest accesses. + On platforms where these accesses would have been handled by firmware, + enabling this causes unexpected kernel oopses, userspaces crashes and + KVM guest crashes. If you are sure that these are not a problem for + your platform, you can say Y here, which may improve performance. + + Saying N here will not worsen emulation support for unaligned accesses + even in the case where the firmware also has incomplete support. It + simply keeps the firmware's emulation enabled. + + If you don't know what to do here, say N. + choice prompt "Unaligned Accesses Support" default RISCV_PROBE_UNALIGNED_ACCESS diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 2d14e92f068d..9078e5b1e49c 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -101,16 +101,6 @@ &ccc_nw { status = "okay"; }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_fabric>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_mssio>; -}; - &mmuart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_fabric>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts index 8afedece89d1..636493f6584d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts @@ -14,6 +14,16 @@ / { "microchip,mpfs"; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_fabric>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_mssio>; +}; + &syscontroller { microchip,bitstream-flash = <&sys_ctrl_flash>; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index 556aa9638282..6fadce815c9a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -11,3 +11,22 @@ / { "microchip,mpfs-icicle-kit", "microchip,mpfs"; }; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_fabric>; +}; + +/* + * Due to silicon errata, routing via MSS IOs doesn't work on ES devices. + * Instead, i2c1, appearing on B1/C1, which are normally MSS IOs, is routed + * via the fabric and back to B1/C1 via "fabric-test" functionality. + * This is done silently by Libero, so the iomux0 setting for i2c1 has to + * be fabric IO, despite tooling etc saying that MSS IOs are used. + * + * See Section 3.3 of https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/Errata/polarfiresoc/microsemi_polarfire_soc_fpga_egineering_samples_errata_er0219_v1.pdf + */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_fabric>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 8cfe8033305d..a7a1c09a2c90 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -135,29 +135,6 @@ &tdm_ext { clock-frequency = <49152000>; }; -&camss { - assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, - <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>; - assigned-clock-rates = <49500000>, <198000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - camss_from_csi2rx: endpoint { - remote-endpoint = <&csi2rx_to_camss>; - }; - }; - }; -}; - &csi2rx { assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>; assigned-clock-rates = <297000000>; @@ -175,9 +152,7 @@ port@0 { port@1 { reg = <1>; - csi2rx_to_camss: endpoint { - remote-endpoint = <&camss_from_csi2rx>; - }; + /* remote CAMSS endpoint */ }; }; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 6e56e9d20bb0..9c3e4598747e 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -1199,34 +1199,6 @@ csi_phy: phy@19820000 { #phy-cells = <0>; }; - camss: isp@19840000 { - compatible = "starfive,jh7110-camss"; - reg = <0x0 0x19840000 0x0 0x10000>, - <0x0 0x19870000 0x0 0x30000>; - reg-names = "syscon", "isp"; - clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, - <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>, - <&ispcrg JH7110_ISPCLK_DVP_INV>, - <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>, - <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>, - <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, - <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>; - clock-names = "apb_func", "wrapper_clk_c", "dvp_inv", - "axiwr", "mipi_rx0_pxl", "ispcore_2x", - "isp_axi"; - resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>, - <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>, - <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>, - <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>, - <&syscrg JH7110_SYSRST_ISP_TOP>, - <&syscrg JH7110_SYSRST_ISP_TOP_AXI>; - reset-names = "wrapper_p", "wrapper_c", "axird", - "axiwr", "isp_top_n", "isp_top_axi"; - power-domains = <&pwrc JH7110_PD_ISP>; - interrupts = <92>, <87>, <90>, <88>; - status = "disabled"; - }; - voutcrg: clock-controller@295c0000 { compatible = "starfive,jh7110-voutcrg"; reg = <0x0 0x295c0000 0x0 0x10000>; diff --git a/arch/riscv/errata/mips/errata.c b/arch/riscv/errata/mips/errata.c index e984a8152208..2c3dc2259e93 100644 --- a/arch/riscv/errata/mips/errata.c +++ b/arch/riscv/errata/mips/errata.c @@ -57,7 +57,7 @@ void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, } tmp = (1U << alt->patch_id); - if (cpu_req_errata && tmp) { + if (cpu_req_errata & tmp) { mutex_lock(&text_mutex); patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt), alt->alt_len); diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index bd5fc9403295..7721b63642f4 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -14,5 +14,6 @@ generic-y += ticket_spinlock.h generic-y += qrwlock.h generic-y += qrwlock_types.h generic-y += qspinlock.h +generic-y += ring_buffer.h generic-y += user.h generic-y += vmlinux.lds.h diff --git a/arch/riscv/kernel/compat_signal.c b/arch/riscv/kernel/compat_signal.c index 6ec4e34255a9..cf3eb33a11e4 100644 --- a/arch/riscv/kernel/compat_signal.c +++ b/arch/riscv/kernel/compat_signal.c @@ -107,6 +107,8 @@ static long compat_restore_sigcontext(struct pt_regs *regs, /* sc_regs is structured the same as the start of pt_regs */ err = __copy_from_user(&cregs, &sc->sc_regs, sizeof(sc->sc_regs)); + if (unlikely(err)) + return err; cregs_to_regs(&cregs, regs); diff --git a/arch/riscv/kernel/copy-unaligned.S b/arch/riscv/kernel/copy-unaligned.S index 2b3d9398c113..90f3549621f7 100644 --- a/arch/riscv/kernel/copy-unaligned.S +++ b/arch/riscv/kernel/copy-unaligned.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (C) 2023 Rivos Inc. */ +#include #include #include @@ -9,7 +10,7 @@ /* void __riscv_copy_words_unaligned(void *, const void *, size_t) */ /* Performs a memcpy without aligning buffers, using word loads and stores. */ /* Note: The size is truncated to a multiple of 8 * SZREG */ -SYM_FUNC_START(__riscv_copy_words_unaligned) +SYM_TYPED_FUNC_START(__riscv_copy_words_unaligned) andi a4, a2, ~((8*SZREG)-1) beqz a4, 2f add a3, a1, a4 @@ -41,7 +42,7 @@ SYM_FUNC_END(__riscv_copy_words_unaligned) /* void __riscv_copy_bytes_unaligned(void *, const void *, size_t) */ /* Performs a memcpy without aligning buffers, using only byte accesses. */ /* Note: The size is truncated to a multiple of 8 */ -SYM_FUNC_START(__riscv_copy_bytes_unaligned) +SYM_TYPED_FUNC_START(__riscv_copy_bytes_unaligned) andi a4, a2, ~(8-1) beqz a4, 2f add a3, a1, a4 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1734f9a4c2fd..f46aa5602d74 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -896,10 +896,8 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) * CPU cores with the ratified spec will contain non-zero * marchid. */ - if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) { - this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v]; + if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) clear_bit(RISCV_ISA_EXT_v, source_isa); - } riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); @@ -1104,16 +1102,16 @@ early_param("riscv_isa_fallback", riscv_isa_fallback_setup); void __init riscv_fill_hwcap(void) { char print_str[NUM_ALPHA_EXTS + 1]; - unsigned long isa2hwcap[26] = {0}; + unsigned long isa2hwcap[RISCV_ISA_EXT_BASE] = {0}; int i, j; - isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; - isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; - isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; - isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; - isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; - isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; - isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; + isa2hwcap[RISCV_ISA_EXT_i] = COMPAT_HWCAP_ISA_I; + isa2hwcap[RISCV_ISA_EXT_m] = COMPAT_HWCAP_ISA_M; + isa2hwcap[RISCV_ISA_EXT_a] = COMPAT_HWCAP_ISA_A; + isa2hwcap[RISCV_ISA_EXT_f] = COMPAT_HWCAP_ISA_F; + isa2hwcap[RISCV_ISA_EXT_d] = COMPAT_HWCAP_ISA_D; + isa2hwcap[RISCV_ISA_EXT_c] = COMPAT_HWCAP_ISA_C; + isa2hwcap[RISCV_ISA_EXT_v] = COMPAT_HWCAP_ISA_V; if (!acpi_disabled) { riscv_fill_hwcap_from_isa_string(isa2hwcap); diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 93de2e7a3074..793bcee46182 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -577,8 +577,8 @@ static int compat_riscv_gpr_set(struct task_struct *target, struct compat_user_regs_struct cregs; ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &cregs, 0, -1); - - cregs_to_regs(&cregs, task_pt_regs(target)); + if (!ret) + cregs_to_regs(&cregs, task_pt_regs(target)); return ret; } diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 2a27d3ff4ac6..81b7682e6c6d 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -584,7 +584,7 @@ static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) static bool misaligned_traps_delegated; -#ifdef CONFIG_RISCV_SBI +#if defined(CONFIG_RISCV_SBI_FWFT_DELEGATE_MISALIGNED) static int cpu_online_sbi_unaligned_setup(unsigned int cpu) { diff --git a/arch/riscv/kernel/usercfi.c b/arch/riscv/kernel/usercfi.c index 6eaa0d94fdfe..cbfb4e495e9f 100644 --- a/arch/riscv/kernel/usercfi.c +++ b/arch/riscv/kernel/usercfi.c @@ -109,15 +109,16 @@ void set_indir_lp_lock(struct task_struct *task, bool lock) task->thread_info.user_cfi_state.ufcfi_locked = lock; } /* - * If size is 0, then to be compatible with regular stack we want it to be as big as - * regular stack. Else PAGE_ALIGN it and return back + * The shadow stack only stores the return address and not any variables + * this should be more than sufficient for most applications. + * Else PAGE_ALIGN it and return back */ static unsigned long calc_shstk_size(unsigned long size) { if (size) return PAGE_ALIGN(size); - return PAGE_ALIGN(min_t(unsigned long long, rlimit(RLIMIT_STACK), SZ_4G)); + return PAGE_ALIGN(min(rlimit(RLIMIT_STACK) / 2, SZ_2G)); } /* diff --git a/arch/riscv/kernel/vec-copy-unaligned.S b/arch/riscv/kernel/vec-copy-unaligned.S index 7ce4de6f6e69..361039f7b944 100644 --- a/arch/riscv/kernel/vec-copy-unaligned.S +++ b/arch/riscv/kernel/vec-copy-unaligned.S @@ -2,6 +2,7 @@ /* Copyright (C) 2024 Rivos Inc. */ #include +#include #include #include @@ -16,7 +17,7 @@ /* void __riscv_copy_vec_words_unaligned(void *, const void *, size_t) */ /* Performs a memcpy without aligning buffers, using word loads and stores. */ /* Note: The size is truncated to a multiple of WORD_EEW */ -SYM_FUNC_START(__riscv_copy_vec_words_unaligned) +SYM_TYPED_FUNC_START(__riscv_copy_vec_words_unaligned) andi a4, a2, ~(WORD_EEW-1) beqz a4, 2f add a3, a1, a4 @@ -38,7 +39,7 @@ SYM_FUNC_END(__riscv_copy_vec_words_unaligned) /* void __riscv_copy_vec_bytes_unaligned(void *, const void *, size_t) */ /* Performs a memcpy without aligning buffers, using only byte accesses. */ /* Note: The size is truncated to a multiple of 8 */ -SYM_FUNC_START(__riscv_copy_vec_bytes_unaligned) +SYM_TYPED_FUNC_START(__riscv_copy_vec_bytes_unaligned) andi a4, a2, ~(8-1) beqz a4, 2f add a3, a1, a4 diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index 4d89b94128ae..f09f9251d1f0 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -415,7 +415,6 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run, shift = 8 * (sizeof(ulong) - len); } else if ((insn & INSN_MASK_LBU) == INSN_MATCH_LBU) { len = 1; - shift = 8 * (sizeof(ulong) - len); #ifdef CONFIG_64BIT } else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) { len = 8; @@ -649,22 +648,22 @@ int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run) case 1: data8 = *((u8 *)run->mmio.data); SET_RD(insn, &vcpu->arch.guest_context, - (ulong)data8 << shift >> shift); + (long)((ulong)data8 << shift) >> shift); break; case 2: data16 = *((u16 *)run->mmio.data); SET_RD(insn, &vcpu->arch.guest_context, - (ulong)data16 << shift >> shift); + (long)((ulong)data16 << shift) >> shift); break; case 4: data32 = *((u32 *)run->mmio.data); SET_RD(insn, &vcpu->arch.guest_context, - (ulong)data32 << shift >> shift); + (long)((ulong)data32 << shift) >> shift); break; case 8: data64 = *((u64 *)run->mmio.data); SET_RD(insn, &vcpu->arch.guest_context, - (ulong)data64 << shift >> shift); + (long)((ulong)data64 << shift) >> shift); break; default: return -EOPNOTSUPP; diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index a935ed96bc17..bb46dcbfb24d 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -453,8 +453,10 @@ int kvm_riscv_vcpu_pmu_snapshot_set_shmem(struct kvm_vcpu *vcpu, unsigned long s } kvpmu->sdata = kzalloc(snapshot_area_size, GFP_ATOMIC); - if (!kvpmu->sdata) - return -ENOMEM; + if (!kvpmu->sdata) { + sbiret = SBI_ERR_FAILURE; + goto out; + } /* No need to check writable slot explicitly as kvm_vcpu_write_guest does it internally */ if (kvm_vcpu_write_guest(vcpu, saddr, kvpmu->sdata, snapshot_area_size)) { @@ -499,8 +501,10 @@ int kvm_riscv_vcpu_pmu_event_info(struct kvm_vcpu *vcpu, unsigned long saddr_low } einfo = kzalloc(shmem_size, GFP_KERNEL); - if (!einfo) - return -ENOMEM; + if (!einfo) { + ret = SBI_ERR_FAILURE; + goto out; + } ret = kvm_vcpu_read_guest(vcpu, shmem, einfo, shmem_size); if (ret) { diff --git a/arch/riscv/kvm/vcpu_sbi_sta.c b/arch/riscv/kvm/vcpu_sbi_sta.c index 3b834709b429..60e50296a008 100644 --- a/arch/riscv/kvm/vcpu_sbi_sta.c +++ b/arch/riscv/kvm/vcpu_sbi_sta.c @@ -46,7 +46,7 @@ void kvm_riscv_vcpu_record_steal_time(struct kvm_vcpu *vcpu) gfn = shmem >> PAGE_SHIFT; hva = kvm_vcpu_gfn_to_hva(vcpu, gfn); - if (WARN_ON(kvm_is_error_hva(hva))) { + if (kvm_is_error_hva(hva)) { vcpu->arch.sta.shmem = INVALID_GPA; return; } diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c index 188d5ea5b3b8..c9c323d4577a 100644 --- a/arch/riscv/kvm/vcpu_sbi_v01.c +++ b/arch/riscv/kvm/vcpu_sbi_v01.c @@ -55,6 +55,8 @@ static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, for_each_set_bit(i, &hmask, BITS_PER_LONG) { rvcpu = kvm_get_vcpu_by_id(vcpu->kvm, i); + if (!rvcpu) + continue; ret = kvm_riscv_vcpu_set_interrupt(rvcpu, IRQ_VS_SOFT); if (ret < 0) break; diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index decd7df40fa4..fa8d2f6f554b 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -792,6 +792,27 @@ static void __init set_mmap_rnd_bits_max(void) mmap_rnd_bits_max = MMAP_VA_BITS - PAGE_SHIFT - 3; } +static bool __init is_vaddr_valid(unsigned long va) +{ + unsigned long up = 0; + + switch (satp_mode) { + case SATP_MODE_39: + up = 1UL << 38; + break; + case SATP_MODE_48: + up = 1UL << 47; + break; + case SATP_MODE_57: + up = 1UL << 56; + break; + default: + return false; + } + + return (va < up) || (va >= (ULONG_MAX - up + 1)); +} + /* * There is a simple way to determine if 4-level is supported by the * underlying hardware: establish 1:1 mapping in 4-level page table mode @@ -833,6 +854,9 @@ static __init void set_satp_mode(uintptr_t dtb_pa) set_satp_mode_pmd + PMD_SIZE, PMD_SIZE, PAGE_KERNEL_EXEC); retry: + if (!is_vaddr_valid(set_satp_mode_pmd)) + goto out; + create_pgd_mapping(early_pg_dir, set_satp_mode_pmd, pgtable_l5_enabled ? @@ -855,6 +879,7 @@ static __init void set_satp_mode(uintptr_t dtb_pa) disable_pgtable_l4(); } +out: memset(early_pg_dir, 0, PAGE_SIZE); memset(early_p4d, 0, PAGE_SIZE); memset(early_pud, 0, PAGE_SIZE); diff --git a/arch/s390/include/asm/Kbuild b/arch/s390/include/asm/Kbuild index 80bad7de7a04..0c1fc47c3ba0 100644 --- a/arch/s390/include/asm/Kbuild +++ b/arch/s390/include/asm/Kbuild @@ -7,3 +7,4 @@ generated-y += unistd_nr.h generic-y += asm-offsets.h generic-y += mcs_spinlock.h generic-y += mmzone.h +generic-y += ring_buffer.h diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c index 31430e9bcfdd..7650f2adb5cf 100644 --- a/arch/s390/kernel/debug.c +++ b/arch/s390/kernel/debug.c @@ -1414,6 +1414,9 @@ static inline char *debug_get_user_string(const char __user *user_buf, { char *buffer; + if (!user_len) + return ERR_PTR(-EINVAL); + buffer = memdup_user_nul(user_buf, user_len); if (IS_ERR(buffer)) return buffer; @@ -1584,6 +1587,11 @@ static int debug_input_flush_fn(debug_info_t *id, struct debug_view *view, char input_buf[1]; int rc = user_len; + if (!user_len) { + rc = -EINVAL; + goto out; + } + if (user_len > 0x10000) user_len = 0x10000; if (*offset != 0) { diff --git a/arch/s390/kernel/perf_pai.c b/arch/s390/kernel/perf_pai.c index 86f71a3d1ef2..cdb8006220ca 100644 --- a/arch/s390/kernel/perf_pai.c +++ b/arch/s390/kernel/perf_pai.c @@ -186,6 +186,13 @@ static u64 pai_getctr(unsigned long *page, int nr, unsigned long offset) return page[nr]; } +static void pai_setctr(unsigned long *page, int nr, unsigned long offset, u64 v) +{ + if (offset) + nr += offset / sizeof(*page); + page[nr] = v; +} + /* Read the counter values. Return value from location in CMP. For base * event xxx_ALL sum up all events. Returns counter value. */ @@ -551,6 +558,8 @@ static void paicrypt_del(struct perf_event *event, int flags) /* Create raw data and save it in buffer. Calculate the delta for each * counter between this invocation and the last invocation. * Returns number of bytes copied. + * After reading from PAI counter page, save the read value to the old + * page to calculate PAI counter deltas. * Saves only entries with positive counter difference of the form * 2 bytes: Number of counter * 8 bytes: Value of counter @@ -562,16 +571,22 @@ static size_t pai_copy(struct pai_userdata *userdata, unsigned long *page, int i, outidx = 0; for (i = 1; i <= pp->num_avail; i++) { - u64 val = 0, val_old = 0; + u64 val = 0, val_old = 0, val_k = 0, val_old_k = 0; if (!exclude_kernel) { - val += pai_getctr(page, i, pp->kernel_offset); - val_old += pai_getctr(page_old, i, pp->kernel_offset); + val_k = pai_getctr(page, i, pp->kernel_offset); + val_old_k = pai_getctr(page_old, i, pp->kernel_offset); + if (val_k != val_old_k) + pai_setctr(page_old, i, pp->kernel_offset, val_k); } if (!exclude_user) { - val += pai_getctr(page, i, 0); - val_old += pai_getctr(page_old, i, 0); + val = pai_getctr(page, i, 0); + val_old = pai_getctr(page_old, i, 0); + if (val != val_old) + pai_setctr(page_old, i, 0, val); } + val += val_k; + val_old += val_old_k; if (val >= val_old) val -= val_old; else @@ -602,8 +617,6 @@ static size_t pai_copy(struct pai_userdata *userdata, unsigned long *page, static int pai_push_sample(size_t rawsize, struct pai_map *cpump, struct perf_event *event) { - int idx = PAI_PMU_IDX(event); - struct pai_pmu *pp = &pai_pmu[idx]; struct perf_sample_data data; struct perf_raw_record raw; struct pt_regs regs; @@ -634,8 +647,6 @@ static int pai_push_sample(size_t rawsize, struct pai_map *cpump, overflow = perf_event_overflow(event, &data, ®s); perf_event_update_userpage(event); - /* Save crypto counter lowcore page after reading event data. */ - memcpy((void *)PAI_SAVE_AREA(event), cpump->area, pp->area_size); return overflow; } @@ -651,7 +662,7 @@ static void pai_have_sample(struct perf_event *event, struct pai_map *cpump) rawsize = pai_copy(cpump->save, cpump->area, pp, (unsigned long *)PAI_SAVE_AREA(event), event->attr.exclude_user, - event->attr.exclude_kernel); + !pp->kernel_offset ? true : event->attr.exclude_kernel); if (rawsize) /* No incremented counters */ pai_push_sample(rawsize, cpump, event); } diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c index 1913a5566ac2..1377c6f3f670 100644 --- a/arch/s390/kernel/topology.c +++ b/arch/s390/kernel/topology.c @@ -192,17 +192,21 @@ static void tl_to_masks(struct sysinfo_15_1_x *info) end = (union topology_entry *)((unsigned long)info + info->length); while (tle < end) { switch (tle->nl) { + /* + * Adjust drawer_id, book_id, and socked_id so they match the + * numbering scheme of e.g. the hardware management console. + */ case 3: drawer = drawer->next; - drawer->id = tle->container.id; + drawer->id = tle->container.id - 1; break; case 2: book = book->next; - book->id = tle->container.id; + book->id = tle->container.id - 1; break; case 1: socket = socket->next; - socket->id = tle->container.id; + socket->id = tle->container.id - 1; break; case 0: add_cpus_to_mask(&tle->cpu, drawer, book, socket); diff --git a/arch/s390/kvm/dat.c b/arch/s390/kvm/dat.c index 7b8d70fe406d..4a41c0247ffa 100644 --- a/arch/s390/kvm/dat.c +++ b/arch/s390/kvm/dat.c @@ -267,6 +267,7 @@ static int dat_split_ste(struct kvm_s390_mmu_cache *mc, union pmd *pmdp, gfn_t g /* No need to take locks as the page table is not installed yet. */ pgste_init.prefix_notif = old.s.fc1.prefix_notif; pgste_init.vsie_notif = old.s.fc1.vsie_notif; + pgste_init.vsie_gmem = old.s.fc1.vsie_notif; pgste_init.pcl = uses_skeys && init.h.i; dat_init_pgstes(pt, pgste_init.val); } else { diff --git a/arch/s390/kvm/dat.h b/arch/s390/kvm/dat.h index 8f8278c44879..873e13ac5a27 100644 --- a/arch/s390/kvm/dat.h +++ b/arch/s390/kvm/dat.h @@ -145,7 +145,8 @@ union pgste { unsigned long cmma_d : 1; /* Dirty flag for CMMA bits */ unsigned long prefix_notif : 1; /* Guest prefix invalidation notification */ unsigned long vsie_notif : 1; /* Referenced in a shadow table */ - unsigned long : 5; + unsigned long vsie_gmem : 1; /* Contains nested guest memory */ + unsigned long : 4; unsigned long : 8; }; struct { diff --git a/arch/s390/kvm/gaccess.c b/arch/s390/kvm/gaccess.c index b07accd19618..4f8d5592c9a9 100644 --- a/arch/s390/kvm/gaccess.c +++ b/arch/s390/kvm/gaccess.c @@ -1445,6 +1445,7 @@ static int _do_shadow_pte(struct gmap *sg, gpa_t raddr, union pte *ptep_h, union } else { pgste = _gmap_ptep_xchg(sg->parent, ptep_h, newpte, pgste, f->gfn, false); pgste.vsie_notif = 1; + pgste.vsie_gmem = 1; } pgste_set_unlock(ptep_h, pgste); if (rc) diff --git a/arch/s390/kvm/gmap.c b/arch/s390/kvm/gmap.c index 3c26e35af0ef..957126ab991c 100644 --- a/arch/s390/kvm/gmap.c +++ b/arch/s390/kvm/gmap.c @@ -125,7 +125,7 @@ struct gmap *gmap_new_child(struct gmap *parent, gfn_t limit) int gmap_set_limit(struct gmap *gmap, gfn_t limit) { - struct kvm_s390_mmu_cache *mc; + struct kvm_s390_mmu_cache *mc __free(kvm_s390_mmu_cache) = NULL; int rc, type; type = gmap_limit_to_type(limit); @@ -142,7 +142,6 @@ int gmap_set_limit(struct gmap *gmap, gfn_t limit) rc = dat_set_asce_limit(mc, &gmap->asce, type); } while (rc == -ENOMEM); - kvm_s390_free_mmu_cache(mc); return 0; } @@ -822,8 +821,8 @@ int gmap_ucas_translate(struct kvm_s390_mmu_cache *mc, struct gmap *gmap, gpa_t int gmap_ucas_map(struct gmap *gmap, gfn_t p_gfn, gfn_t c_gfn, unsigned long count) { - struct kvm_s390_mmu_cache *mc; - int rc; + struct kvm_s390_mmu_cache *mc __free(kvm_s390_mmu_cache) = NULL; + int rc = 0; mc = kvm_s390_new_mmu_cache(); if (!mc) @@ -1026,13 +1025,15 @@ int gmap_insert_rmap(struct gmap *sg, gfn_t p_gfn, gfn_t r_gfn, int level) int gmap_protect_rmap(struct kvm_s390_mmu_cache *mc, struct gmap *sg, gfn_t p_gfn, gfn_t r_gfn, kvm_pfn_t pfn, int level, bool wr) { + unsigned long bitmask; union crste *crstep; union pgste pgste; union pte *ptep; union pte pte; int flags, rc; - KVM_BUG_ON(!is_shadow(sg), sg->kvm); + if (KVM_BUG_ON(!is_shadow(sg) || level <= TABLE_TYPE_PAGE_TABLE, sg->kvm)) + return -EINVAL; lockdep_assert_held(&sg->parent->children_lock); flags = DAT_WALK_SPLIT_ALLOC | (uses_skeys(sg->parent) ? DAT_WALK_USES_SKEYS : 0); @@ -1041,8 +1042,9 @@ int gmap_protect_rmap(struct kvm_s390_mmu_cache *mc, struct gmap *sg, gfn_t p_gf if (rc) return rc; if (level <= TABLE_TYPE_REGION1) { + bitmask = -1UL << (8 + 11 * level); scoped_guard(spinlock, &sg->host_to_rmap_lock) - rc = gmap_insert_rmap(sg, p_gfn, r_gfn, level); + rc = gmap_insert_rmap(sg, p_gfn, r_gfn & bitmask, level); } if (rc) return rc; @@ -1143,8 +1145,10 @@ void _gmap_handle_vsie_unshadow_event(struct gmap *parent, gfn_t gfn) } scoped_guard(spinlock, &sg->host_to_rmap_lock) head = radix_tree_delete(&sg->host_to_rmap, gfn); - gmap_for_each_rmap_safe(rmap, rnext, head) + gmap_for_each_rmap_safe(rmap, rnext, head) { gmap_unshadow_level(sg, rmap->r_gfn, rmap->level); + kfree(rmap); + } } } diff --git a/arch/s390/kvm/gmap.h b/arch/s390/kvm/gmap.h index 96ee1395a592..742e42a31744 100644 --- a/arch/s390/kvm/gmap.h +++ b/arch/s390/kvm/gmap.h @@ -167,6 +167,36 @@ static inline bool gmap_unmap_prefix(struct gmap *gmap, gfn_t gfn, gfn_t end) return _gmap_unmap_prefix(gmap, gfn, end, false); } +/** + * pte_needs_unshadow() -- Check if the pte operations triggers unshadowing. + * @oldpte: the previous value for the guest pte. + * @newpte: the new pte being set. + * @pgste: the pgste for the pte entry. + * + * If the pgste.vsie_notif bit is not set, return false: the page is not + * involved in vsie and thus should not trigger an unshadow operation. + * + * If the pgste.vsie_gmem bit is set, this pte represents shadowed guest + * memory. The access rights on g3's memory should be synchronized with g1's + * and g2's. Therefore unshadowing is triggered if the new and old pte + * differ in protection, or if the new pte is invalid. + * + * If the pgste.vsie_gmem bit is not set, this pte maps the g2 dat tables + * for g3. If the entry becomes writable or absent, it becomes impossible to + * guarantee that the shadow mapping will match g2's mapping. In that case, + * trigger an unshadow event. + * + * Return: true if an unshadow event should be triggered, otherwise false. + */ +static inline bool pte_needs_unshadow(union pte oldpte, union pte newpte, union pgste pgste) +{ + if (!pgste.vsie_notif) + return false; + if (pgste.vsie_gmem) + return (oldpte.h.p != newpte.h.p) || newpte.h.i; + return !newpte.h.p || !newpte.s.pr; +} + static inline union pgste _gmap_ptep_xchg(struct gmap *gmap, union pte *ptep, union pte newpte, union pgste pgste, gfn_t gfn, bool needs_lock) { @@ -180,8 +210,9 @@ static inline union pgste _gmap_ptep_xchg(struct gmap *gmap, union pte *ptep, un pgste.prefix_notif = 0; gmap_unmap_prefix(gmap, gfn, gfn + 1); } - if (pgste.vsie_notif && (ptep->h.p != newpte.h.p || newpte.h.i)) { + if (pte_needs_unshadow(*ptep, newpte, pgste)) { pgste.vsie_notif = 0; + pgste.vsie_gmem = 0; if (needs_lock) gmap_handle_vsie_unshadow_event(gmap, gfn); else @@ -189,6 +220,7 @@ static inline union pgste _gmap_ptep_xchg(struct gmap *gmap, union pte *ptep, un } if (!ptep->s.d && newpte.s.d && !newpte.s.s) SetPageDirty(pfn_to_page(newpte.h.pfra)); + pgste.zero = 0; return __dat_ptep_xchg(ptep, pgste, newpte, gfn, gmap->asce, uses_skeys(gmap)); } @@ -198,6 +230,30 @@ static inline union pgste gmap_ptep_xchg(struct gmap *gmap, union pte *ptep, uni return _gmap_ptep_xchg(gmap, ptep, newpte, pgste, gfn, true); } +/** + * crste_needs_unshadow() -- Check if the crste operations triggers unshadowing. + * @oldcrste: the previous value for the crste. + * @newcrste: the new value for the crste. + * + * If the old crste did not have the vsie_notif bit set, return false: the + * page is not involved in vsie and thus should not trigger an unshadow + * operation. Conversely, if the bit is set, it can only be g3 memory, since + * dat tables are never mapped using large pages. + * + * Similar to the pgste.vsie_gmem case of pte_needs_unshadow(), if the + * protection bit is changing or the new page is invalid, trigger an + * unshadow event. Also trigger an unshadow event if the new crste does not + * have the vsie_notif bit set. + * + * Return: true if an unshadow event should be triggered, otherwise false. + */ +static inline bool crste_needs_unshadow(union crste oldcrste, union crste newcrste) +{ + if (!oldcrste.s.fc1.vsie_notif) + return false; + return (newcrste.h.p != oldcrste.h.p) || newcrste.h.i || !newcrste.s.fc1.vsie_notif; +} + static inline bool __must_check _gmap_crstep_xchg_atomic(struct gmap *gmap, union crste *crstep, union crste oldcrste, union crste newcrste, gfn_t gfn, bool needs_lock) @@ -216,8 +272,7 @@ static inline bool __must_check _gmap_crstep_xchg_atomic(struct gmap *gmap, unio newcrste.s.fc1.prefix_notif = 0; gmap_unmap_prefix(gmap, gfn, gfn + align); } - if (crste_leaf(oldcrste) && oldcrste.s.fc1.vsie_notif && - (newcrste.h.p || newcrste.h.i || !newcrste.s.fc1.vsie_notif)) { + if (crste_leaf(oldcrste) && crste_needs_unshadow(oldcrste, newcrste)) { newcrste.s.fc1.vsie_notif = 0; if (needs_lock) gmap_handle_vsie_unshadow_event(gmap, gfn); diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index 07f59c3b9a7b..3bcdbbbb6891 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -3310,8 +3310,7 @@ static void aen_host_forward(unsigned long si) struct zpci_gaite *gaite; struct kvm *kvm; - gaite = (struct zpci_gaite *)aift->gait + - (si * sizeof(struct zpci_gaite)); + gaite = aift->gait + si; if (gaite->count == 0) return; if (gaite->aisb != 0) diff --git a/arch/s390/kvm/pci.c b/arch/s390/kvm/pci.c index 86d93e8dddae..5b075c38998e 100644 --- a/arch/s390/kvm/pci.c +++ b/arch/s390/kvm/pci.c @@ -166,7 +166,7 @@ static int kvm_zpci_set_airq(struct zpci_dev *zdev) fib.fmt0.noi = airq_iv_end(zdev->aibv); fib.fmt0.aibv = virt_to_phys(zdev->aibv->vector); fib.fmt0.aibvo = 0; - fib.fmt0.aisb = virt_to_phys(aift->sbv->vector + (zdev->aisb / 64) * 8); + fib.fmt0.aisb = virt_to_phys(aift->sbv->vector) + (zdev->aisb / 64) * 8; fib.fmt0.aisbo = zdev->aisb & 63; fib.gd = zdev->gisa; @@ -290,8 +290,7 @@ static int kvm_s390_pci_aif_enable(struct zpci_dev *zdev, struct zpci_fib *fib, phys_to_virt(fib->fmt0.aibv)); spin_lock_irq(&aift->gait_lock); - gaite = (struct zpci_gaite *)aift->gait + (zdev->aisb * - sizeof(struct zpci_gaite)); + gaite = aift->gait + zdev->aisb; /* If assist not requested, host will get all alerts */ if (assist) @@ -309,7 +308,7 @@ static int kvm_s390_pci_aif_enable(struct zpci_dev *zdev, struct zpci_fib *fib, /* Update guest FIB for re-issue */ fib->fmt0.aisbo = zdev->aisb & 63; - fib->fmt0.aisb = virt_to_phys(aift->sbv->vector + (zdev->aisb / 64) * 8); + fib->fmt0.aisb = virt_to_phys(aift->sbv->vector) + (zdev->aisb / 64) * 8; fib->fmt0.isc = gisc; /* Save some guest fib values in the host for later use */ @@ -357,8 +356,7 @@ static int kvm_s390_pci_aif_disable(struct zpci_dev *zdev, bool force) if (zdev->kzdev->fib.fmt0.aibv == 0) goto out; spin_lock_irq(&aift->gait_lock); - gaite = (struct zpci_gaite *)aift->gait + (zdev->aisb * - sizeof(struct zpci_gaite)); + gaite = aift->gait + zdev->aisb; isc = gaite->gisc; gaite->count--; if (gaite->count == 0) { diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index 191cc53caead..028aeb9c48d6 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -438,7 +438,7 @@ void do_secure_storage_access(struct pt_regs *regs) panic("Unexpected PGM 0x3d with TEID bit 61=0"); } if (is_kernel_fault(regs)) { - folio = phys_to_folio(addr); + folio = virt_to_folio((void *)addr); if (unlikely(!folio_try_get(folio))) return; rc = uv_convert_from_secure(folio_to_phys(folio)); diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild index 4d3f10ed8275..f0403d3ee8ab 100644 --- a/arch/sh/include/asm/Kbuild +++ b/arch/sh/include/asm/Kbuild @@ -3,4 +3,5 @@ generated-y += syscall_table.h generic-y += kvm_para.h generic-y += mcs_spinlock.h generic-y += parport.h +generic-y += ring_buffer.h generic-y += text-patching.h diff --git a/arch/sh/include/asm/setup.h b/arch/sh/include/asm/setup.h index 63c9efc06348..8488f76b48b4 100644 --- a/arch/sh/include/asm/setup.h +++ b/arch/sh/include/asm/setup.h @@ -7,7 +7,7 @@ /* * This is set up by the setup-routine at boot-time */ -extern unsigned char *boot_params_page; +extern unsigned char boot_params_page[]; #define PARAM boot_params_page #define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000)) diff --git a/arch/sparc/include/asm/Kbuild b/arch/sparc/include/asm/Kbuild index 17ee8a273aa6..49c6bb326b75 100644 --- a/arch/sparc/include/asm/Kbuild +++ b/arch/sparc/include/asm/Kbuild @@ -4,4 +4,5 @@ generated-y += syscall_table_64.h generic-y += agp.h generic-y += kvm_para.h generic-y += mcs_spinlock.h +generic-y += ring_buffer.h generic-y += text-patching.h diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild index 1b9b82bbe322..2a1629ba8140 100644 --- a/arch/um/include/asm/Kbuild +++ b/arch/um/include/asm/Kbuild @@ -17,6 +17,7 @@ generic-y += module.lds.h generic-y += parport.h generic-y += percpu.h generic-y += preempt.h +generic-y += ring_buffer.h generic-y += runtime-const.h generic-y += softirq_stack.h generic-y += switch_to.h diff --git a/arch/x86/entry/Makefile b/arch/x86/entry/Makefile index 72cae8e0ce85..83b4762d6ecb 100644 --- a/arch/x86/entry/Makefile +++ b/arch/x86/entry/Makefile @@ -13,7 +13,7 @@ CFLAGS_REMOVE_syscall_64.o = $(CC_FLAGS_FTRACE) CFLAGS_syscall_32.o += -fno-stack-protector CFLAGS_syscall_64.o += -fno-stack-protector -obj-y := entry.o entry_$(BITS).o syscall_$(BITS).o +obj-y := entry.o entry_$(BITS).o syscall_$(BITS).o common.o obj-y += vdso/ obj-y += vsyscall/ diff --git a/arch/x86/entry/common.c b/arch/x86/entry/common.c new file mode 100644 index 000000000000..06c7c6ebd6f9 --- /dev/null +++ b/arch/x86/entry/common.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_KVM_INTEL) +/* + * On VMX, NMIs and IRQs (as configured by KVM) are acknowledged by hardware as + * part of the VM-Exit, i.e. the event itself is consumed as part the VM-Exit. + * x86_entry_from_kvm() is invoked by KVM to effectively forward NMIs and IRQs + * to the kernel for servicing. On SVM, a.k.a. AMD, the NMI/IRQ VM-Exit is + * purely a signal that an NMI/IRQ is pending, i.e. the event that triggered + * the VM-Exit is held pending until it's unblocked in the host. + */ +noinstr void x86_entry_from_kvm(unsigned int event_type, unsigned int vector) +{ + if (event_type == EVENT_TYPE_EXTINT) { +#ifdef CONFIG_X86_64 + /* + * Use FRED dispatch, even when running IDT. The dispatch + * tables are kept in sync between FRED and IDT, and the FRED + * dispatch works well with CFI. + */ + fred_entry_from_kvm(event_type, vector); +#else + idt_entry_from_kvm(vector); +#endif + /* + * Strictly speaking, only the NMI path requires noinstr. + */ + instrumentation_begin(); + /* + * KVM/VMX will dispatch from IRQ-disabled but for a context + * that will have IRQs-enabled. This confuses the entry code + * and it will not have reprogrammed the timer. Do so now. + */ + hrtimer_rearm_deferred(); + instrumentation_end(); + + return; + } + + WARN_ON_ONCE(event_type != EVENT_TYPE_NMI); + +#ifdef CONFIG_X86_64 + if (cpu_feature_enabled(X86_FEATURE_FRED)) + return fred_entry_from_kvm(event_type, vector); +#endif + + /* + * Notably, we must use IDT dispatch for NMI when running in IDT mode. + * The FRED NMI context is significantly different and will not work + * right (specifically FRED fixed the NMI recursion issue). + */ + idt_entry_from_kvm(vector); +} +EXPORT_SYMBOL_FOR_KVM(x86_entry_from_kvm); +#endif diff --git a/arch/x86/entry/entry.S b/arch/x86/entry/entry.S index 6ba2b3adcef0..a56e043b266d 100644 --- a/arch/x86/entry/entry.S +++ b/arch/x86/entry/entry.S @@ -75,3 +75,49 @@ THUNK warn_thunk_thunk, __warn_thunk #if defined(CONFIG_STACKPROTECTOR) && defined(CONFIG_SMP) EXPORT_SYMBOL(__ref_stack_chk_guard); #endif + +#if IS_ENABLED(CONFIG_KVM_INTEL) +.macro IDT_DO_EVENT_IRQOFF call_insn call_target + /* + * Unconditionally create a stack frame, getting the correct RSP on the + * stack (for x86-64) would take two instructions anyways, and RBP can + * be used to restore RSP to make objtool happy (see below). + */ + push %_ASM_BP + mov %_ASM_SP, %_ASM_BP + +#ifdef CONFIG_X86_64 + /* + * Align RSP to a 16-byte boundary (to emulate CPU behavior) before + * creating the synthetic interrupt stack frame for the IRQ/NMI. + */ + and $-16, %rsp + push $__KERNEL_DS + push %rbp +#endif + pushf + push $__KERNEL_CS + \call_insn \call_target + + /* + * "Restore" RSP from RBP, even though IRET has already unwound RSP to + * the correct value. objtool doesn't know the callee will IRET and, + * without the explicit restore, thinks the stack is getting walloped. + * Using an unwind hint is problematic due to x86-64's dynamic alignment. + */ + leave + RET +.endm + +.pushsection .text, "ax" +SYM_FUNC_START(idt_do_interrupt_irqoff) + IDT_DO_EVENT_IRQOFF CALL_NOSPEC _ASM_ARG1 +SYM_FUNC_END(idt_do_interrupt_irqoff) +.popsection + +.pushsection .noinstr.text, "ax" +SYM_FUNC_START(idt_do_nmi_irqoff) + IDT_DO_EVENT_IRQOFF call asm_exc_nmi_kvm_vmx +SYM_FUNC_END(idt_do_nmi_irqoff) +.popsection +#endif diff --git a/arch/x86/entry/entry_64_fred.S b/arch/x86/entry/entry_64_fred.S index 894f7f16eb80..0d2768ab836c 100644 --- a/arch/x86/entry/entry_64_fred.S +++ b/arch/x86/entry/entry_64_fred.S @@ -147,5 +147,4 @@ SYM_FUNC_START(asm_fred_entry_from_kvm) RET SYM_FUNC_END(asm_fred_entry_from_kvm) -EXPORT_SYMBOL_FOR_KVM(asm_fred_entry_from_kvm); #endif diff --git a/arch/x86/entry/vdso/vma.c b/arch/x86/entry/vdso/vma.c index a6bfcc8243cd..d903bce24f15 100644 --- a/arch/x86/entry/vdso/vma.c +++ b/arch/x86/entry/vdso/vma.c @@ -178,7 +178,7 @@ static int map_vdso(const struct vdso_image *image, unsigned long addr) if (IS_ERR(vma)) { ret = PTR_ERR(vma); do_munmap(mm, text_start, image->size, NULL); - do_munmap(mm, addr, image->size, NULL); + do_munmap(mm, addr, VDSO_NR_PAGES * PAGE_SIZE, NULL); goto up_fail; } diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 810ab21ffd99..4b9e105309c6 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1294,13 +1294,16 @@ int x86_perf_rdpmc_index(struct perf_event *event) return event->hw.event_base_rdpmc; } -static inline int match_prev_assignment(struct hw_perf_event *hwc, +static inline int match_prev_assignment(struct perf_event *event, struct cpu_hw_events *cpuc, int i) { + struct hw_perf_event *hwc = &event->hw; + return hwc->idx == cpuc->assign[i] && - hwc->last_cpu == smp_processor_id() && - hwc->last_tag == cpuc->tags[i]; + hwc->last_cpu == smp_processor_id() && + hwc->last_tag == cpuc->tags[i] && + !is_acr_event_group(event); } static void x86_pmu_start(struct perf_event *event, int flags); @@ -1346,7 +1349,7 @@ static void x86_pmu_enable(struct pmu *pmu) * - no other event has used the counter since */ if (hwc->idx == -1 || - match_prev_assignment(hwc, cpuc, i)) + match_prev_assignment(event, cpuc, i)) continue; /* @@ -1367,7 +1370,7 @@ static void x86_pmu_enable(struct pmu *pmu) event = cpuc->event_list[i]; hwc = &event->hw; - if (!match_prev_assignment(hwc, cpuc, i)) + if (!match_prev_assignment(event, cpuc, i)) x86_assign_hw_event(event, cpuc, i); else if (i < n_running) continue; diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index d9488ade0f8e..dd1e3aa75ee9 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3118,11 +3118,11 @@ static void intel_pmu_enable_fixed(struct perf_event *event) intel_set_masks(event, idx); /* - * Enable IRQ generation (0x8), if not PEBS, - * and enable ring-3 counting (0x2) and ring-0 counting (0x1) - * if requested: + * Enable IRQ generation (0x8), if not PEBS or self-reloaded + * ACR event, and enable ring-3 counting (0x2) and ring-0 + * counting (0x1) if requested: */ - if (!event->attr.precise_ip) + if (!event->attr.precise_ip && !is_acr_self_reload_event(event)) bits |= INTEL_FIXED_0_ENABLE_PMI; if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) bits |= INTEL_FIXED_0_USER; @@ -3306,6 +3306,15 @@ static void intel_pmu_enable_event(struct perf_event *event) intel_set_masks(event, idx); static_call_cond(intel_pmu_enable_acr_event)(event); static_call_cond(intel_pmu_enable_event_ext)(event); + /* + * For self-reloaded ACR event, don't enable PMI since + * HW won't set overflow bit in GLOBAL_STATUS. Otherwise, + * the PMI would be recognized as a suspicious NMI. + */ + if (is_acr_self_reload_event(event)) + hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; + else if (!event->attr.precise_ip) + hwc->config |= ARCH_PERFMON_EVENTSEL_INT; __x86_pmu_enable_event(hwc, enable_mask); break; case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: @@ -3332,23 +3341,41 @@ static void intel_pmu_enable_event(struct perf_event *event) static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc) { struct perf_event *event, *leader; - int i, j, idx; + int i, j, k, bit, idx; + /* + * FIXME: ACR mask parsing relies on cpuc->event_list[] (active events only). + * Disabling an ACR event causes bit-shifting errors in the acr_mask of + * remaining group members. As ACR sampling requires all events to be active, + * this limitation is acceptable for now. Revisit if independent event toggling + * is required. + */ for (i = 0; i < cpuc->n_events; i++) { leader = cpuc->event_list[i]; if (!is_acr_event_group(leader)) continue; - /* The ACR events must be contiguous. */ + /* Find the last event of the ACR group. */ for (j = i; j < cpuc->n_events; j++) { event = cpuc->event_list[j]; if (event->group_leader != leader->group_leader) break; - for_each_set_bit(idx, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) { - if (i + idx >= cpuc->n_events || - !is_acr_event_group(cpuc->event_list[i + idx])) - return; - __set_bit(cpuc->assign[i + idx], (unsigned long *)&event->hw.config1); + } + + /* + * Translate the user-space ACR mask (attr.config2) into the physical + * counter bitmask (hw.config1) for each ACR event in the group. + * NOTE: ACR event contiguity is guaranteed by intel_pmu_hw_config(). + */ + for (k = i; k < j; k++) { + event = cpuc->event_list[k]; + event->hw.config1 = 0; + for_each_set_bit(bit, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) { + idx = i + bit; + /* Event index of ACR group must locate in [i, j). */ + if (idx >= j || !is_acr_event_group(cpuc->event_list[idx])) + continue; + __set_bit(cpuc->assign[idx], (unsigned long *)&event->hw.config1); } } i = j - 1; @@ -7504,6 +7531,7 @@ static __always_inline void intel_pmu_init_pnc(struct pmu *pmu) hybrid(pmu, event_constraints) = intel_pnc_event_constraints; hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints; hybrid(pmu, extra_regs) = intel_pnc_extra_regs; + static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); } static __always_inline void intel_pmu_init_skt(struct pmu *pmu) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index fad87d3c8b2c..524668dcf4cc 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -137,6 +137,16 @@ static inline bool is_acr_event_group(struct perf_event *event) return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR); } +static inline bool is_acr_self_reload_event(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + + if (hwc->idx < 0) + return false; + + return test_bit(hwc->idx, (unsigned long *)&hwc->config1); +} + struct amd_nb { int nb_id; /* NorthBridge id */ int refcnt; /* reference count */ diff --git a/arch/x86/include/asm/Kbuild b/arch/x86/include/asm/Kbuild index 4566000e15c4..078fd2c0d69d 100644 --- a/arch/x86/include/asm/Kbuild +++ b/arch/x86/include/asm/Kbuild @@ -14,3 +14,4 @@ generic-y += early_ioremap.h generic-y += fprobe.h generic-y += mcs_spinlock.h generic-y += mmzone.h +generic-y += ring_buffer.h diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h index ec95fe44fa3a..00aeae843529 100644 --- a/arch/x86/include/asm/desc.h +++ b/arch/x86/include/asm/desc.h @@ -438,6 +438,10 @@ extern void idt_setup_traps(void); extern void idt_setup_apic_and_irq_gates(void); extern bool idt_is_f00f_address(unsigned long address); +extern void idt_do_interrupt_irqoff(unsigned long address); +extern void idt_do_nmi_irqoff(void); +extern void idt_entry_from_kvm(unsigned int vector); + #ifdef CONFIG_X86_64 extern void idt_setup_early_pf(void); #else diff --git a/arch/x86/include/asm/desc_defs.h b/arch/x86/include/asm/desc_defs.h index 7e6b9314758a..2f2ce8aadf07 100644 --- a/arch/x86/include/asm/desc_defs.h +++ b/arch/x86/include/asm/desc_defs.h @@ -145,7 +145,7 @@ struct gate_struct { typedef struct gate_struct gate_desc; #ifndef _SETUP -static inline unsigned long gate_offset(const gate_desc *g) +static __always_inline unsigned long gate_offset(const gate_desc *g) { #ifdef CONFIG_X86_64 return g->offset_low | ((unsigned long)g->offset_middle << 16) | diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h index dc8fe1361c18..be58b7f5c806 100644 --- a/arch/x86/include/asm/efi.h +++ b/arch/x86/include/asm/efi.h @@ -137,7 +137,8 @@ extern void __init efi_dump_pagetable(void); extern void __init efi_apply_memmap_quirks(void); extern int __init efi_reuse_config(u64 tables, int nr_tables); extern void efi_delete_dummy_variable(void); -extern void efi_crash_gracefully_on_page_fault(unsigned long phys_addr); +extern void efi_crash_gracefully_on_page_fault(unsigned long phys_addr, + const struct pt_regs *regs); extern void efi_unmap_boot_services(void); void arch_efi_call_virt_setup(void); diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/entry-common.h index 7535131c711b..eca24b5e07f4 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -97,4 +97,6 @@ static __always_inline void arch_exit_to_user_mode(void) } #define arch_exit_to_user_mode arch_exit_to_user_mode +extern void x86_entry_from_kvm(unsigned int entry_type, unsigned int vector); + #endif diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 2bb65677c079..18a2f811c358 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -110,7 +110,6 @@ static __always_inline unsigned long fred_event_data(struct pt_regs *regs) { ret static inline void cpu_init_fred_exceptions(void) { } static inline void cpu_init_fred_rsps(void) { } static inline void fred_complete_exception_setup(void) { } -static inline void fred_entry_from_kvm(unsigned int type, unsigned int vector) { } static inline void fred_sync_rsp0(unsigned long rsp0) { } static inline void fred_update_rsp0(void) { } #endif /* CONFIG_X86_FRED */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a14a0f43e04a..86554de9a3f5 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -803,9 +803,10 @@ #define MSR_AMD64_LBR_SELECT 0xc000010e /* Zen4 */ -#define MSR_ZEN4_BP_CFG 0xc001102e +#define MSR_ZEN4_BP_CFG 0xc001102e #define MSR_ZEN4_BP_CFG_BP_SPEC_REDUCE_BIT 4 #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 +#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT 33 /* Fam 19h MSRs */ #define MSR_F19H_UMC_PERF_CTL 0xc0010800 diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index d7c8ef1e354d..be4c5e9e5ff6 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -88,19 +88,19 @@ static void amd_set_max_freq_ratio(void) rc = cppc_get_perf_caps(0, &perf_caps); if (rc) { - pr_warn("Could not retrieve perf counters (%d)\n", rc); + pr_debug("Could not retrieve perf counters (%d)\n", rc); return; } rc = amd_get_boost_ratio_numerator(0, &numerator); if (rc) { - pr_warn("Could not retrieve highest performance (%d)\n", rc); + pr_debug("Could not retrieve highest performance (%d)\n", rc); return; } nominal_perf = perf_caps.nominal_perf; if (!nominal_perf) { - pr_warn("Could not retrieve nominal performance\n"); + pr_debug("Could not retrieve nominal performance\n"); return; } diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 2d9ae6ab1701..2f8e8ff2d000 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -989,6 +989,9 @@ static void init_amd_zen2(struct cpuinfo_x86 *c) /* Correct misconfigured CPUID on some clients. */ clear_cpu_cap(c, X86_FEATURE_INVLPGB); + + if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) + msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN2_BP_CFG_BUG_FIX_BIT); } static void init_amd_zen3(struct cpuinfo_x86 *c) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index 146f6f8b0650..99801e844b30 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -92,6 +92,7 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_FRED, X86_FEATURE_LKGS }, { X86_FEATURE_SPEC_CTRL_SSBD, X86_FEATURE_SPEC_CTRL }, { X86_FEATURE_LASS, X86_FEATURE_SMAP }, + { X86_FEATURE_INVLPGB, X86_FEATURE_PCID }, {} }; diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 8dd424ac5de8..f3a793e3a6c8 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -90,7 +90,6 @@ struct mca_config mca_cfg __read_mostly = { }; static DEFINE_PER_CPU(struct mce_hw_err, hw_errs_seen); -static unsigned long mce_need_notify; /* * MCA banks polled by the period polling timer for corrected events. @@ -152,8 +151,10 @@ EXPORT_PER_CPU_SYMBOL_GPL(injectm); void mce_log(struct mce_hw_err *err) { - if (mce_gen_pool_add(err)) + if (mce_gen_pool_add(err)) { + pr_info(HW_ERR "Machine check events logged\n"); irq_work_queue(&mce_irq_work); + } } EXPORT_SYMBOL_GPL(mce_log); @@ -585,28 +586,6 @@ bool mce_is_correctable(struct mce *m) } EXPORT_SYMBOL_GPL(mce_is_correctable); -/* - * Notify the user(s) about new machine check events. - * Can be called from interrupt context, but not from machine check/NMI - * context. - */ -static bool mce_notify_irq(void) -{ - /* Not more than two messages every minute */ - static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); - - if (test_and_clear_bit(0, &mce_need_notify)) { - mce_work_trigger(); - - if (__ratelimit(&ratelimit)) - pr_info(HW_ERR "Machine check events logged\n"); - - return true; - } - - return false; -} - static int mce_early_notifier(struct notifier_block *nb, unsigned long val, void *data) { @@ -618,9 +597,7 @@ static int mce_early_notifier(struct notifier_block *nb, unsigned long val, /* Emit the trace record: */ trace_mce_record(err); - set_bit(0, &mce_need_notify); - - mce_notify_irq(); + mce_work_trigger(); return NOTIFY_DONE; } @@ -1804,7 +1781,7 @@ static void mce_timer_fn(struct timer_list *t) * Alert userspace if needed. If we logged an MCE, reduce the polling * interval, otherwise increase the polling interval. */ - if (mce_notify_irq()) + if (!mce_gen_pool_empty()) iv = max(iv / 2, (unsigned long) HZ/100); else iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index 2a9992758933..eb72537bc0b1 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -450,6 +450,10 @@ __init static int append_e820_table(struct boot_e820_entry *entries, u32 nr_entr { struct boot_e820_entry *entry = entries; + /* If there aren't any entries, we'll want to fall back to another source: */ + if (!nr_entries) + return -ENOENT; + while (nr_entries) { u64 start = entry->addr; u64 size = entry->size; @@ -458,7 +462,7 @@ __init static int append_e820_table(struct boot_e820_entry *entries, u32 nr_entr /* Ignore the remaining entries on 64-bit overflow: */ if (start > end && likely(size)) - return -1; + return -EINVAL; e820__range_add(start, size, type); diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index 260456588756..7bcf1decc034 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -268,6 +268,21 @@ void __init idt_setup_early_pf(void) } #endif +#if IS_ENABLED(CONFIG_KVM_INTEL) +noinstr void idt_entry_from_kvm(unsigned int vector) +{ + if (vector == NMI_VECTOR) + return idt_do_nmi_irqoff(); + + /* + * Only the NMI path requires noinstr. + */ + instrumentation_begin(); + idt_do_interrupt_irqoff(gate_offset(idt_table + vector)); + instrumentation_end(); +} +#endif + static void __init idt_map_in_cea(void) { /* diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 3d239ed12744..52a3afb1b79e 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -614,7 +614,6 @@ DEFINE_IDTENTRY_RAW(exc_nmi_kvm_vmx) { exc_nmi(regs); } -EXPORT_SYMBOL_FOR_KVM(asm_exc_nmi_kvm_vmx); #endif #ifdef CONFIG_NMI_CHECK_CPU diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S index 4ffba68dc57b..eaeb77464c06 100644 --- a/arch/x86/kernel/relocate_kernel_64.S +++ b/arch/x86/kernel/relocate_kernel_64.S @@ -136,6 +136,14 @@ SYM_CODE_START_LOCAL_NOALIGN(identity_mapped) * %r13 original CR4 when relocate_kernel() was invoked */ + /* + * Set return address to 0 if not preserving context. The purgatory + * shipped in kexec-tools will unconditionally look for the return + * address on the stack and set a kexec_jump_back_entry= command + * line option if it's non-zero. There's no other way that it can + * tell a preserve-context (kjump) kexec from a normal one. + */ + pushq $0 /* store the start address on the stack */ pushq %rdx diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index c8c6cc0406d6..8013dccb3110 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -4481,7 +4481,7 @@ static const struct opcode opcode_map_0f_38[256] = { X16(N), X16(N), /* 0x20 - 0x2f */ X8(N), - X2(N), GP(SrcReg | DstMem | ModRM | Mov | Aligned, &pfx_0f_e7_0f_38_2a), N, N, N, N, N, + X2(N), GP(SrcMem | DstReg | ModRM | Mov | Aligned, &pfx_0f_e7_0f_38_2a), N, N, N, N, N, /* 0x30 - 0x7f */ X16(N), X16(N), X16(N), X16(N), X16(N), /* 0x80 - 0xef */ diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c index 9b140bbdc1d8..4438ecac9a89 100644 --- a/arch/x86/kvm/hyperv.c +++ b/arch/x86/kvm/hyperv.c @@ -2040,7 +2040,7 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc) * flush). Translate the address here so the memory can be uniformly * read with kvm_read_guest(). */ - if (!hc->fast && is_guest_mode(vcpu)) { + if (!hc->fast && mmu_is_nested(vcpu)) { hc->ingpa = translate_nested_gpa(vcpu, hc->ingpa, 0, NULL); if (unlikely(hc->ingpa == INVALID_GPA)) return HV_STATUS_INVALID_HYPERCALL_INPUT; diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index e3ec4d8607c1..4078e624ca66 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -667,13 +667,15 @@ bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr) u32 *__pir = (void *)pir_vals; u32 i, vec; u32 irr_val, prev_irr_val; - int max_updated_irr; + int max_new_irr; - max_updated_irr = -1; - *max_irr = -1; - - if (!pi_harvest_pir(pir, pir_vals)) + if (!pi_harvest_pir(pir, pir_vals)) { + *max_irr = apic_find_highest_vector(regs + APIC_IRR); return false; + } + + max_new_irr = -1; + *max_irr = -1; for (i = vec = 0; i <= 7; i++, vec += 32) { u32 *p_irr = (u32 *)(regs + APIC_IRR + i * 0x10); @@ -688,25 +690,25 @@ bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr) !try_cmpxchg(p_irr, &prev_irr_val, irr_val)); if (prev_irr_val != irr_val) - max_updated_irr = __fls(irr_val ^ prev_irr_val) + vec; + max_new_irr = __fls(irr_val ^ prev_irr_val) + vec; } if (irr_val) *max_irr = __fls(irr_val) + vec; } - return ((max_updated_irr != -1) && - (max_updated_irr == *max_irr)); + return max_new_irr != -1 && max_new_irr == *max_irr; } EXPORT_SYMBOL_FOR_KVM_INTERNAL(__kvm_apic_update_irr); bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, unsigned long *pir, int *max_irr) { struct kvm_lapic *apic = vcpu->arch.apic; - bool irr_updated = __kvm_apic_update_irr(pir, apic->regs, max_irr); + bool max_irr_is_from_pir; - if (unlikely(!apic->apicv_active && irr_updated)) + max_irr_is_from_pir = __kvm_apic_update_irr(pir, apic->regs, max_irr); + if (unlikely(!apic->apicv_active && max_irr_is_from_pir)) apic->irr_pending = true; - return irr_updated; + return max_irr_is_from_pir; } EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_apic_update_irr); diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 24fbc9ea502a..f0144ae8d891 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -182,6 +182,8 @@ static struct kmem_cache *pte_list_desc_cache; struct kmem_cache *mmu_page_header_cache; static void mmu_spte_set(u64 *sptep, u64 spte); +static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, + u64 *spte, struct list_head *invalid_list); struct kvm_mmu_role_regs { const unsigned long cr0; @@ -1287,19 +1289,6 @@ static void drop_spte(struct kvm *kvm, u64 *sptep) rmap_remove(kvm, sptep); } -static void drop_large_spte(struct kvm *kvm, u64 *sptep, bool flush) -{ - struct kvm_mmu_page *sp; - - sp = sptep_to_sp(sptep); - WARN_ON_ONCE(sp->role.level == PG_LEVEL_4K); - - drop_spte(kvm, sptep); - - if (flush) - kvm_flush_remote_tlbs_sptep(kvm, sptep); -} - /* * Write-protect on the specified @sptep, @pt_protect indicates whether * spte write-protection is caused by protecting shadow page table. @@ -2466,7 +2455,8 @@ static struct kvm_mmu_page *kvm_mmu_get_child_sp(struct kvm_vcpu *vcpu, { union kvm_mmu_page_role role; - if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) + if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep) && + spte_to_child_sp(*sptep) && spte_to_child_sp(*sptep)->gfn == gfn) return ERR_PTR(-EEXIST); role = kvm_mmu_child_role(sptep, direct, access); @@ -2536,6 +2526,23 @@ static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) __shadow_walk_next(iterator, *iterator->sptep); } +/* + * Note: while normally KVM uses a "bool flush" return value to let + * the caller batch flushes, __link_shadow_page() flushes immediately + * before populating the parent PTE with the new shadow page. The + * typical callers, direct_map() and FNAME(fetch)(), are not going + * to zap more than one huge SPTE anyway. + * + * The only exception, where @flush can be false, is when a huge SPTE + * is replaced with a shadow page SPTE with a fully populated page table, + * which can happen from shadow_mmu_split_huge_page(). In this case, + * no memory is unmapped across the change to the page tables and no + * immediate flush is needed for correctness. + * + * Even in that case, calls to kvm_mmu_commit_zap_page() are not + * batched. Doing so would require adding an invalid_list argument + * all the way down to __walk_slot_rmaps(). + */ static void __link_shadow_page(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, u64 *sptep, struct kvm_mmu_page *sp, bool flush) @@ -2544,13 +2551,18 @@ static void __link_shadow_page(struct kvm *kvm, BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); - /* - * If an SPTE is present already, it must be a leaf and therefore - * a large one. Drop it, and flush the TLB if needed, before - * installing sp. - */ - if (is_shadow_present_pte(*sptep)) - drop_large_spte(kvm, sptep, flush); + if (is_shadow_present_pte(*sptep)) { + struct kvm_mmu_page *parent_sp; + LIST_HEAD(invalid_list); + + parent_sp = sptep_to_sp(sptep); + WARN_ON_ONCE(parent_sp->role.level == PG_LEVEL_4K); + + if (mmu_page_zap_pte(kvm, parent_sp, sptep, &invalid_list)) + kvm_mmu_commit_zap_page(kvm, &invalid_list); + else if (flush) + kvm_flush_remote_tlbs_sptep(kvm, sptep); + } spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp)); diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index adf211860949..993b551180fe 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -1300,12 +1300,14 @@ bool __init avic_hardware_setup(void) } /* - * Disable IPI virtualization for AMD Family 17h CPUs (Zen1 and Zen2) - * due to erratum 1235, which results in missed VM-Exits on the sender - * and thus missed wake events for blocking vCPUs due to the CPU - * failing to see a software update to clear IsRunning. + * Disable IPI virtualization for AMD Family 17h (Zen1 and Zen2) and + * Hygon Family 18h (derived from AMD Zen1) CPUs due to erratum 1235, + * which results in missed VM-Exits on the sender and thus missed wake + * events for blocking vCPUs due to the CPU failing to see a software + * update to clear IsRunning. */ - enable_ipiv = enable_ipiv && boot_cpu_data.x86 != 0x17; + if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) + enable_ipiv = false; amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 961804df5f45..b340dc9991ad 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -160,6 +160,16 @@ void nested_vmcb02_recalc_intercepts(struct vcpu_svm *svm) if (!intercept_smi) vmcb_clr_intercept(&vmcb02->control, INTERCEPT_SMI); + /* + * Intercept PAUSE if and only if L1 wants to. KVM intercepts PAUSE so + * that a vCPU that may be spinning waiting for a lock can be scheduled + * out in favor of the vCPU that holds said lock. KVM doesn't support + * yielding across L2 vCPUs, as KVM has limited visilibity into which + * L2 vCPUs are in the same L2 VM, i.e. may be contending for locks. + */ + if (!vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_PAUSE)) + vmcb_clr_intercept(&vmcb02->control, INTERCEPT_PAUSE); + if (nested_vmcb_needs_vls_intercept(svm)) { /* * If the virtual VMLOAD/VMSAVE is not enabled for the L2, @@ -819,7 +829,6 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm) struct vmcb *vmcb02 = svm->nested.vmcb02.ptr; struct vmcb *vmcb01 = svm->vmcb01.ptr; struct kvm_vcpu *vcpu = &svm->vcpu; - u32 pause_count12, pause_thresh12; nested_svm_transition_tlb_flush(vcpu); @@ -947,31 +956,13 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm) vmcb02->control.misc_ctl2 |= SVM_MISC2_ENABLE_V_VMLOAD_VMSAVE; if (guest_cpu_cap_has(vcpu, X86_FEATURE_PAUSEFILTER)) - pause_count12 = vmcb12_ctrl->pause_filter_count; + vmcb02->control.pause_filter_count = vmcb12_ctrl->pause_filter_count; else - pause_count12 = 0; + vmcb02->control.pause_filter_count = 0; if (guest_cpu_cap_has(vcpu, X86_FEATURE_PFTHRESHOLD)) - pause_thresh12 = vmcb12_ctrl->pause_filter_thresh; + vmcb02->control.pause_filter_thresh = vmcb12_ctrl->pause_filter_thresh; else - pause_thresh12 = 0; - if (kvm_pause_in_guest(svm->vcpu.kvm)) { - /* use guest values since host doesn't intercept PAUSE */ - vmcb02->control.pause_filter_count = pause_count12; - vmcb02->control.pause_filter_thresh = pause_thresh12; - - } else { - /* start from host values otherwise */ - vmcb02->control.pause_filter_count = vmcb01->control.pause_filter_count; - vmcb02->control.pause_filter_thresh = vmcb01->control.pause_filter_thresh; - - /* ... but ensure filtering is disabled if so requested. */ - if (vmcb12_is_intercept(vmcb12_ctrl, INTERCEPT_PAUSE)) { - if (!pause_count12) - vmcb02->control.pause_filter_count = 0; - if (!pause_thresh12) - vmcb02->control.pause_filter_thresh = 0; - } - } + vmcb02->control.pause_filter_thresh = 0; /* * Take ALLOW_LARGER_RAP from vmcb12 even though it should be safe to @@ -1298,12 +1289,6 @@ void nested_svm_vmexit(struct vcpu_svm *svm) /* in case we halted in L2 */ kvm_set_mp_state(vcpu, KVM_MP_STATE_RUNNABLE); - if (!kvm_pause_in_guest(vcpu->kvm)) { - vmcb01->control.pause_filter_count = vmcb02->control.pause_filter_count; - vmcb_mark_dirty(vmcb01, VMCB_INTERCEPTS); - - } - /* * Invalidate last_bus_lock_rip unless KVM is still waiting for the * guest to make forward progress before re-enabling bus lock detection. diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index e7fdd7a9c280..e02a38da5296 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -913,7 +913,15 @@ static void grow_ple_window(struct kvm_vcpu *vcpu) struct vmcb_control_area *control = &svm->vmcb->control; int old = control->pause_filter_count; - if (kvm_pause_in_guest(vcpu->kvm)) + /* Adjusting pause_filter_count makes no sense if PLE is disabled. */ + WARN_ON_ONCE(kvm_pause_in_guest(vcpu->kvm)); + + /* + * While running L2, KVM should intercept PAUSE if and only if L1 wants + * to intercept PAUSE, and L1's intercept should take priority, i.e. + * KVM should never handle a PAUSE intercept from L2. + */ + if (WARN_ON_ONCE(is_guest_mode(vcpu))) return; control->pause_filter_count = __grow_ple_window(old, @@ -934,7 +942,10 @@ static void shrink_ple_window(struct kvm_vcpu *vcpu) struct vmcb_control_area *control = &svm->vmcb->control; int old = control->pause_filter_count; - if (kvm_pause_in_guest(vcpu->kvm)) + /* Adjusting pause_filter_count makes no sense if PLE is disabled. */ + WARN_ON_ONCE(kvm_pause_in_guest(vcpu->kvm)); + + if (is_guest_mode(vcpu)) return; control->pause_filter_count = diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index e7fdbe9efc90..0db25bba17f6 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h @@ -154,7 +154,7 @@ TRACE_EVENT(kvm_xen_hypercall, __entry->a2 = a2; __entry->a3 = a3; __entry->a4 = a4; - __entry->a4 = a5; + __entry->a5 = a5; ), TP_printk("cpl %d nr 0x%lx a0 0x%lx a1 0x%lx a2 0x%lx a3 0x%lx a4 0x%lx a5 %lx", diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h index 56cacc06225e..31568274d8bb 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -14,6 +14,7 @@ extern bool __read_mostly flexpriority_enabled; extern bool __read_mostly enable_ept; extern bool __read_mostly enable_unrestricted_guest; extern bool __read_mostly enable_ept_ad_bits; +extern bool __read_mostly enable_cet; extern bool __read_mostly enable_pml; extern int __read_mostly pt_mode; diff --git a/arch/x86/kvm/vmx/vmenter.S b/arch/x86/kvm/vmx/vmenter.S index 8a481dae9cae..ff1f254a0ef4 100644 --- a/arch/x86/kvm/vmx/vmenter.S +++ b/arch/x86/kvm/vmx/vmenter.S @@ -31,38 +31,6 @@ #define VCPU_R15 __VCPU_REGS_R15 * WORD_SIZE #endif -.macro VMX_DO_EVENT_IRQOFF call_insn call_target - /* - * Unconditionally create a stack frame, getting the correct RSP on the - * stack (for x86-64) would take two instructions anyways, and RBP can - * be used to restore RSP to make objtool happy (see below). - */ - push %_ASM_BP - mov %_ASM_SP, %_ASM_BP - -#ifdef CONFIG_X86_64 - /* - * Align RSP to a 16-byte boundary (to emulate CPU behavior) before - * creating the synthetic interrupt stack frame for the IRQ/NMI. - */ - and $-16, %rsp - push $__KERNEL_DS - push %rbp -#endif - pushf - push $__KERNEL_CS - \call_insn \call_target - - /* - * "Restore" RSP from RBP, even though IRET has already unwound RSP to - * the correct value. objtool doesn't know the callee will IRET and, - * without the explicit restore, thinks the stack is getting walloped. - * Using an unwind hint is problematic due to x86-64's dynamic alignment. - */ - leave - RET -.endm - .section .noinstr.text, "ax" /** @@ -320,10 +288,6 @@ SYM_INNER_LABEL_ALIGN(vmx_vmexit, SYM_L_GLOBAL) SYM_FUNC_END(__vmx_vcpu_run) -SYM_FUNC_START(vmx_do_nmi_irqoff) - VMX_DO_EVENT_IRQOFF call asm_exc_nmi_kvm_vmx -SYM_FUNC_END(vmx_do_nmi_irqoff) - #ifndef CONFIG_CC_HAS_ASM_GOTO_OUTPUT /** @@ -375,13 +339,3 @@ SYM_FUNC_START(vmread_error_trampoline) RET SYM_FUNC_END(vmread_error_trampoline) #endif - -.section .text, "ax" - -#ifndef CONFIG_X86_FRED - -SYM_FUNC_START(vmx_do_interrupt_irqoff) - VMX_DO_EVENT_IRQOFF CALL_NOSPEC _ASM_ARG1 -SYM_FUNC_END(vmx_do_interrupt_irqoff) - -#endif diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index a29896a9ef14..b9103de01428 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -108,6 +108,9 @@ module_param_named(unrestricted_guest, bool __read_mostly enable_ept_ad_bits = 1; module_param_named(eptad, enable_ept_ad_bits, bool, 0444); +bool __read_mostly enable_cet = 1; +module_param_named(cet, enable_cet, bool, 0444); + static bool __read_mostly emulate_invalid_guest_state = true; module_param(emulate_invalid_guest_state, bool, 0444); @@ -4476,7 +4479,7 @@ void vmx_set_constant_host_state(struct vcpu_vmx *vmx) * SSP is reloaded from IA32_PL3_SSP. Check SDM Vol.2A/B Chapter * 3 and 4 for details. */ - if (cpu_has_load_cet_ctrl()) { + if (enable_cet) { vmcs_writel(HOST_S_CET, kvm_host.s_cet); vmcs_writel(HOST_SSP, 0); vmcs_writel(HOST_INTR_SSP_TABLE, 0); @@ -4532,6 +4535,10 @@ static u32 vmx_get_initial_vmentry_ctrl(void) if (vmx_pt_mode_is_system()) vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP | VM_ENTRY_LOAD_IA32_RTIT_CTL); + + if (!enable_cet) + vmentry_ctrl &= ~VM_ENTRY_LOAD_CET_STATE; + /* * IA32e mode, and loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically. */ @@ -4546,6 +4553,9 @@ static u32 vmx_get_initial_vmexit_ctrl(void) { u32 vmexit_ctrl = vmcs_config.vmexit_ctrl; + if (!enable_cet) + vmexit_ctrl &= ~VM_EXIT_LOAD_CET_STATE; + /* * Not used by KVM and never set in vmcs01 or vmcs02, but emulated for * nested virtualization and thus allowed to be set in vmcs12. @@ -7029,8 +7039,8 @@ static void vmx_set_rvi(int vector) int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) { struct vcpu_vt *vt = to_vt(vcpu); + bool max_irr_is_from_pir; int max_irr; - bool got_posted_interrupt; if (KVM_BUG_ON(!enable_apicv, vcpu->kvm)) return -EIO; @@ -7042,17 +7052,22 @@ int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) * But on x86 this is just a compiler barrier anyway. */ smp_mb__after_atomic(); - got_posted_interrupt = - kvm_apic_update_irr(vcpu, vt->pi_desc.pir, &max_irr); + max_irr_is_from_pir = kvm_apic_update_irr(vcpu, vt->pi_desc.pir, + &max_irr); } else { max_irr = kvm_lapic_find_highest_irr(vcpu); - got_posted_interrupt = false; + max_irr_is_from_pir = false; } /* - * Newly recognized interrupts are injected via either virtual interrupt - * delivery (RVI) or KVM_REQ_EVENT. Virtual interrupt delivery is - * disabled in two cases: + * If APICv is enabled and L2 is not active, then update the Requesting + * Virtual Interrupt (RVI) portion of vmcs01.GUEST_INTR_STATUS with the + * highest priority IRR to deliver the IRQ via Virtual Interrupt + * Delivery. Note, this is required even if the highest priority IRQ + * was already pending in the IRR, as RVI isn't updated in lockstep with + * the IRR (unlike apic->irr_pending). + * + * For the cases where Virtual Interrupt Delivery can't be used: * * 1) If L2 is running and the vCPU has a new pending interrupt. If L1 * wants to exit on interrupts, KVM_REQ_EVENT is needed to synthesize a @@ -7063,10 +7078,29 @@ int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) * 2) If APICv is disabled for this vCPU, assigned devices may still * attempt to post interrupts. The posted interrupt vector will cause * a VM-Exit and the subsequent entry will call sync_pir_to_irr. + * + * In both cases, set KVM_REQ_EVENT if and only if the highest priority + * pending IRQ came from the PIR, as setting KVM_REQ_EVENT if any IRQ + * is pending may put the vCPU into an infinite loop, e.g. if the IRQ + * is blocked, then it will stay pending until an IRQ window is opened. + * + * Note! It's possible that one or more IRQs were moved from the PIR + * to the IRR _without_ max_irr_is_from_pir being true! I.e. if there + * was a higher priority IRQ already pending in the IRR. Not setting + * KVM_REQ_EVENT in this case is intentional and safe. If APICv is + * inactive, or L2 is running with exit-on-interrupt off (in vmcs12), + * i.e. without nested virtual interrupt delivery, then there's no need + * to request an IRQ window as the lower priority IRQ only needs to be + * delivered when the higher priority IRQ is dismissed from the ISR, + * i.e. on the next EOI, and EOIs are always intercepted if APICv is + * disabled or if L2 is running without nested VID. If L2 is running + * exit-on-interrupt on (in vmcs12), then the higher priority IRQ will + * trigger a nested VM-Exit, at which point KVM will re-evaluate L1's + * pending IRQs. */ if (!is_guest_mode(vcpu) && kvm_vcpu_apicv_active(vcpu)) vmx_set_rvi(max_irr); - else if (got_posted_interrupt) + else if (max_irr_is_from_pir) kvm_make_request(KVM_REQ_EVENT, vcpu); return max_irr; @@ -7083,9 +7117,6 @@ void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); } -void vmx_do_interrupt_irqoff(unsigned long entry); -void vmx_do_nmi_irqoff(void); - static void handle_nm_fault_irqoff(struct kvm_vcpu *vcpu) { /* @@ -7127,17 +7158,8 @@ static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu, "unexpected VM-Exit interrupt info: 0x%x", intr_info)) return; - /* - * Invoke the kernel's IRQ handler for the vector. Use the FRED path - * when it's available even if FRED isn't fully enabled, e.g. even if - * FRED isn't supported in hardware, in order to avoid the indirect - * CALL in the non-FRED path. - */ kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); - if (IS_ENABLED(CONFIG_X86_FRED)) - fred_entry_from_kvm(EVENT_TYPE_EXTINT, vector); - else - vmx_do_interrupt_irqoff(gate_offset((gate_desc *)host_idt_base + vector)); + x86_entry_from_kvm(EVENT_TYPE_EXTINT, vector); kvm_after_interrupt(vcpu); vcpu->arch.at_instruction_boundary = true; @@ -7447,10 +7469,7 @@ noinstr void vmx_handle_nmi(struct kvm_vcpu *vcpu) return; kvm_before_interrupt(vcpu, KVM_HANDLING_NMI); - if (cpu_feature_enabled(X86_FEATURE_FRED)) - fred_entry_from_kvm(EVENT_TYPE_NMI, NMI_VECTOR); - else - vmx_do_nmi_irqoff(); + x86_entry_from_kvm(EVENT_TYPE_NMI, NMI_VECTOR); kvm_after_interrupt(vcpu); } @@ -8131,7 +8150,7 @@ static __init void vmx_set_cpu_caps(void) * VMX_BASIC[bit56] == 0, inject #CP at VMX entry with error code * fails, so disable CET in this case too. */ - if (!cpu_has_load_cet_ctrl() || !enable_unrestricted_guest || + if (!enable_cet || !enable_unrestricted_guest || !cpu_has_vmx_basic_no_hw_errcode_cc()) { kvm_cpu_cap_clear(X86_FEATURE_SHSTK); kvm_cpu_cap_clear(X86_FEATURE_IBT); @@ -8606,6 +8625,9 @@ __init int vmx_hardware_setup(void) !cpu_has_vmx_invept_global()) enable_ept = 0; + if (!cpu_has_load_cet_ctrl()) + enable_cet = 0; + /* NX support is required for shadow paging. */ if (!enable_ept && !boot_cpu_has(X86_FEATURE_NX)) { pr_err_ratelimited("NX (Execute Disable) not supported\n"); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 0a1b63c63d1a..c1a72d749084 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4876,7 +4876,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) r = tdp_enabled; break; case KVM_CAP_X86_APIC_BUS_CYCLES_NS: - r = APIC_BUS_CYCLE_NS_DEFAULT; + r = kvm ? kvm->arch.apic_bus_cycle_ns : APIC_BUS_CYCLE_NS_DEFAULT; break; case KVM_CAP_EXIT_HYPERCALL: r = KVM_EXIT_HYPERCALL_VALID_MASK; diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index f0e77e084482..63de8e8684f2 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -686,7 +686,7 @@ page_fault_oops(struct pt_regs *regs, unsigned long error_code, * avoid hanging the system. */ if (IS_ENABLED(CONFIG_EFI)) - efi_crash_gracefully_on_page_fault(address); + efi_crash_gracefully_on_page_fault(address, regs); /* Only not-present faults should be handled by KFENCE. */ if (!(error_code & X86_PF_PROT) && diff --git a/arch/x86/platform/efi/quirks.c b/arch/x86/platform/efi/quirks.c index df24ffc6105d..90a065fcb1fa 100644 --- a/arch/x86/platform/efi/quirks.c +++ b/arch/x86/platform/efi/quirks.c @@ -761,7 +761,8 @@ int efi_capsule_setup_info(struct capsule_info *cap_info, void *kbuff, * @return: Returns, if the page fault is not handled. This function * will never return if the page fault is handled successfully. */ -void efi_crash_gracefully_on_page_fault(unsigned long phys_addr) +void efi_crash_gracefully_on_page_fault(unsigned long phys_addr, + const struct pt_regs *regs) { if (!IS_ENABLED(CONFIG_X86_64)) return; @@ -770,7 +771,7 @@ void efi_crash_gracefully_on_page_fault(unsigned long phys_addr) * If we get an interrupt/NMI while processing an EFI runtime service * then this is a regular OOPS, not an EFI failure. */ - if (in_interrupt()) + if (!in_task()) return; /* @@ -810,6 +811,14 @@ void efi_crash_gracefully_on_page_fault(unsigned long phys_addr) return; } + /* + * The API does not permit entering a kernel mode FPU section with + * interrupts enabled and leaving it with interrupts disabled. So + * re-enable interrupts now if they were enabled when the page fault + * occurred. + */ + local_irq_restore(regs->flags); + /* * Before calling EFI Runtime Service, the kernel has switched the * calling process to efi_mm. Hence, switch back to task_mm. diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c index c80d0058efd1..3eee5f84f8a7 100644 --- a/arch/x86/xen/mmu_pv.c +++ b/arch/x86/xen/mmu_pv.c @@ -2145,7 +2145,10 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot) static void xen_enter_lazy_mmu(void) { - enter_lazy(XEN_LAZY_MMU); + preempt_disable(); + if (xen_get_lazy_mode() != XEN_LAZY_MMU) + enter_lazy(XEN_LAZY_MMU); + preempt_enable(); } static void xen_flush_lazy_mmu(void) @@ -2182,7 +2185,8 @@ static void xen_leave_lazy_mmu(void) { preempt_disable(); xen_mc_flush(); - leave_lazy(XEN_LAZY_MMU); + if (xen_get_lazy_mode() != XEN_LAZY_NONE) + leave_lazy(XEN_LAZY_MMU); preempt_enable(); } diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index ac8021c3a997..41251d4cf953 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -655,7 +655,7 @@ static void __init xen_e820_swap_entry_with_ram(struct e820_entry *swap_entry) /* Fill new entry (keep size and page offset). */ entry->type = swap_entry->type; entry->addr = entry_end - swap_size + - swap_addr - swap_entry->addr; + swap_entry->addr - swap_addr; entry->size = swap_entry->size; /* Convert old entry to RAM, align to pages. */ @@ -695,17 +695,22 @@ static void __init xen_e820_resolve_conflicts(phys_addr_t start, return; end = start + size; - entry = xen_e820_table.entries; + mapcnt = 0; - for (mapcnt = 0; mapcnt < xen_e820_table.nr_entries; mapcnt++) { + while (mapcnt < xen_e820_table.nr_entries) { + entry = xen_e820_table.entries + mapcnt; if (entry->addr >= end) return; if (entry->addr + entry->size > start && - entry->type == E820_TYPE_NVS) + entry->type == E820_TYPE_NVS) { xen_e820_swap_entry_with_ram(entry); + /* E820 map has been changed, restart loop! */ + mapcnt = 0; + continue; + } - entry++; + mapcnt++; } } diff --git a/arch/xtensa/include/asm/Kbuild b/arch/xtensa/include/asm/Kbuild index 13fe45dea296..e57af619263a 100644 --- a/arch/xtensa/include/asm/Kbuild +++ b/arch/xtensa/include/asm/Kbuild @@ -6,5 +6,6 @@ generic-y += mcs_spinlock.h generic-y += parport.h generic-y += qrwlock.h generic-y += qspinlock.h +generic-y += ring_buffer.h generic-y += user.h generic-y += text-patching.h diff --git a/block/bio-integrity-fs.c b/block/bio-integrity-fs.c index acb1e5f270d2..0daa42d9ead7 100644 --- a/block/bio-integrity-fs.c +++ b/block/bio-integrity-fs.c @@ -55,6 +55,10 @@ int fs_bio_integrity_verify(struct bio *bio, sector_t sector, unsigned int size) { struct blk_integrity *bi = blk_get_integrity(bio->bi_bdev->bd_disk); struct bio_integrity_payload *bip = bio_integrity(bio); + struct bvec_iter data_iter = { + .bi_sector = sector, + .bi_size = size, + }; /* * Reinitialize bip->bip_iter. @@ -65,7 +69,7 @@ int fs_bio_integrity_verify(struct bio *bio, sector_t sector, unsigned int size) memset(&bip->bip_iter, 0, sizeof(bip->bip_iter)); bip->bip_iter.bi_sector = sector; bip->bip_iter.bi_size = bio_integrity_bytes(bi, size >> SECTOR_SHIFT); - return blk_status_to_errno(bio_integrity_verify(bio, &bip->bip_iter)); + return blk_status_to_errno(bio_integrity_verify(bio, &data_iter)); } static int __init fs_bio_integrity_init(void) diff --git a/block/bio-integrity.c b/block/bio-integrity.c index e54c6e06e1cb..e796de1a749e 100644 --- a/block/bio-integrity.c +++ b/block/bio-integrity.c @@ -308,7 +308,6 @@ static int bio_integrity_copy_user(struct bio *bio, struct bio_vec *bvec, } bip->bip_flags |= BIP_COPY_USER; - bip->bip_vcnt = nr_vecs; return 0; free_bip: bio_integrity_free(bio); @@ -403,6 +402,24 @@ int bio_integrity_map_user(struct bio *bio, struct iov_iter *iter) if (unlikely(ret < 0)) goto free_bvec; + /* + * Handle partial pinning. This can happen when pin_user_pages_fast() + * returns fewer pages than requested. + */ + if (user_backed_iter(iter) && unlikely(ret != bytes)) { + if (ret > 0) { + int npinned = DIV_ROUND_UP(offset + ret, PAGE_SIZE); + int i; + + for (i = 0; i < npinned; i++) + unpin_user_page(pages[i]); + } + if (pages != stack_pages) + kvfree(pages); + ret = -EFAULT; + goto free_bvec; + } + nr_bvecs = bvec_from_pages(bvec, pages, nr_vecs, bytes, offset, &is_p2p); if (pages != stack_pages) diff --git a/block/bio.c b/block/bio.c index b8972dba68a0..5f10900b3f42 100644 --- a/block/bio.c +++ b/block/bio.c @@ -1279,11 +1279,12 @@ int bio_iov_iter_get_pages(struct bio *bio, struct iov_iter *iter, return bio_iov_iter_align_down(bio, iter, len_align_mask); } -static struct folio *folio_alloc_greedy(gfp_t gfp, size_t *size) +static struct folio *folio_alloc_greedy(gfp_t gfp, size_t *size, + size_t minsize) { struct folio *folio; - while (*size > PAGE_SIZE) { + while (*size > minsize) { folio = folio_alloc(gfp | __GFP_NORETRY, get_order(*size)); if (folio) return folio; @@ -1307,7 +1308,7 @@ static void bio_free_folios(struct bio *bio) } static int bio_iov_iter_bounce_write(struct bio *bio, struct iov_iter *iter, - size_t maxlen) + size_t maxlen, size_t minsize) { size_t total_len = min(maxlen, iov_iter_count(iter)); @@ -1322,13 +1323,13 @@ static int bio_iov_iter_bounce_write(struct bio *bio, struct iov_iter *iter, size_t this_len = min(total_len, SZ_1M); struct folio *folio; - if (this_len > PAGE_SIZE * 2) + if (this_len > minsize * 2) this_len = rounddown_pow_of_two(this_len); if (bio->bi_iter.bi_size > BIO_MAX_SIZE - this_len) break; - folio = folio_alloc_greedy(GFP_KERNEL, &this_len); + folio = folio_alloc_greedy(GFP_KERNEL, &this_len, minsize); if (!folio) break; bio_add_folio_nofail(bio, folio, this_len, 0); @@ -1344,16 +1345,16 @@ static int bio_iov_iter_bounce_write(struct bio *bio, struct iov_iter *iter, if (!bio->bi_iter.bi_size) return -ENOMEM; - return 0; + return bio_iov_iter_align_down(bio, iter, minsize - 1); } static int bio_iov_iter_bounce_read(struct bio *bio, struct iov_iter *iter, - size_t maxlen) + size_t maxlen, size_t minsize) { size_t len = min3(iov_iter_count(iter), maxlen, SZ_1M); struct folio *folio; - folio = folio_alloc_greedy(GFP_KERNEL, &len); + folio = folio_alloc_greedy(GFP_KERNEL, &len, minsize); if (!folio) return -ENOMEM; @@ -1382,7 +1383,7 @@ static int bio_iov_iter_bounce_read(struct bio *bio, struct iov_iter *iter, bvec_set_folio(&bio->bi_io_vec[0], folio, bio->bi_iter.bi_size, 0); if (iov_iter_extract_will_pin(iter)) bio_set_flag(bio, BIO_PAGE_PINNED); - return 0; + return bio_iov_iter_align_down(bio, iter, minsize - 1); } /** @@ -1390,6 +1391,7 @@ static int bio_iov_iter_bounce_read(struct bio *bio, struct iov_iter *iter, * @bio: bio to send * @iter: iter to read from / write into * @maxlen: maximum size to bounce + * @minsize: minimum folio allocation size * * Helper for direct I/O implementations that need to bounce buffer because * we need to checksum the data or perform other operations that require @@ -1397,11 +1399,12 @@ static int bio_iov_iter_bounce_read(struct bio *bio, struct iov_iter *iter, * copies the data into it. Needs to be paired with bio_iov_iter_unbounce() * called on completion. */ -int bio_iov_iter_bounce(struct bio *bio, struct iov_iter *iter, size_t maxlen) +int bio_iov_iter_bounce(struct bio *bio, struct iov_iter *iter, size_t maxlen, + size_t minsize) { if (op_is_write(bio_op(bio))) - return bio_iov_iter_bounce_write(bio, iter, maxlen); - return bio_iov_iter_bounce_read(bio, iter, maxlen); + return bio_iov_iter_bounce_write(bio, iter, maxlen, minsize); + return bio_iov_iter_bounce_read(bio, iter, maxlen, minsize); } static void bvec_unpin(struct bio_vec *bv, bool mark_dirty) diff --git a/block/blk-cgroup.c b/block/blk-cgroup.c index 554c87bb4a86..bc63bd220865 100644 --- a/block/blk-cgroup.c +++ b/block/blk-cgroup.c @@ -2241,7 +2241,7 @@ void blk_cgroup_bio_start(struct bio *bio) } u64_stats_update_end_irqrestore(&bis->sync, flags); - css_rstat_updated(&blkcg->css, cpu); + __css_rstat_updated(&blkcg->css, cpu); put_cpu(); } diff --git a/block/blk-mq.c b/block/blk-mq.c index 4c5c16cce4f8..28c2d931e75e 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -3077,7 +3077,7 @@ static struct request *blk_mq_get_new_requests(struct request_queue *q, /* * Check if there is a suitable cached request and return it. */ -static struct request *blk_mq_peek_cached_request(struct blk_plug *plug, +static struct request *blk_mq_get_cached_request(struct blk_plug *plug, struct request_queue *q, blk_opf_t opf) { enum hctx_type type = blk_mq_get_hctx_type(opf); @@ -3093,27 +3093,10 @@ static struct request *blk_mq_peek_cached_request(struct blk_plug *plug, return NULL; if (op_is_flush(rq->cmd_flags) != op_is_flush(opf)) return NULL; + rq_list_pop(&plug->cached_rqs); return rq; } -static void blk_mq_use_cached_rq(struct request *rq, struct blk_plug *plug, - struct bio *bio) -{ - if (rq_list_pop(&plug->cached_rqs) != rq) - WARN_ON_ONCE(1); - - /* - * If any qos ->throttle() end up blocking, we will have flushed the - * plug and hence killed the cached_rq list as well. Pop this entry - * before we throttle. - */ - rq_qos_throttle(rq->q, bio); - - blk_mq_rq_time_init(rq, blk_time_get_ns()); - rq->cmd_flags = bio->bi_opf; - INIT_LIST_HEAD(&rq->queuelist); -} - static bool bio_unaligned(const struct bio *bio, struct request_queue *q) { unsigned int bs_mask = queue_logical_block_size(q) - 1; @@ -3152,7 +3135,7 @@ void blk_mq_submit_bio(struct bio *bio) /* * If the plug has a cached request for this queue, try to use it. */ - rq = blk_mq_peek_cached_request(plug, q, bio->bi_opf); + rq = blk_mq_get_cached_request(plug, q, bio->bi_opf); /* * A BIO that was released from a zone write plug has already been @@ -3211,7 +3194,10 @@ void blk_mq_submit_bio(struct bio *bio) new_request: if (rq) { - blk_mq_use_cached_rq(rq, plug, bio); + rq_qos_throttle(rq->q, bio); + blk_mq_rq_time_init(rq, blk_time_get_ns()); + rq->cmd_flags = bio->bi_opf; + INIT_LIST_HEAD(&rq->queuelist); } else { rq = blk_mq_get_new_requests(q, plug, bio); if (unlikely(!rq)) { @@ -3257,12 +3243,10 @@ void blk_mq_submit_bio(struct bio *bio) return; queue_exit: - /* - * Don't drop the queue reference if we were trying to use a cached - * request and thus didn't acquire one. - */ if (!rq) blk_queue_exit(q); + else + blk_mq_free_request(rq); } #ifdef CONFIG_BLK_MQ_STACKING @@ -3307,6 +3291,25 @@ blk_status_t blk_insert_cloned_request(struct request *rq) return BLK_STS_IOERR; } + /* + * Integrity segment counting depends on the same queue limits + * (virt_boundary_mask, seg_boundary_mask, max_segment_size) that + * vary across stacked queues, so recompute against the bottom + * queue just like nr_phys_segments above. + */ + if (blk_integrity_rq(rq) && rq->bio) { + unsigned short max_int_segs = queue_max_integrity_segments(q); + + rq->nr_integrity_segments = + blk_rq_count_integrity_sg(rq->q, rq->bio); + if (rq->nr_integrity_segments > max_int_segs) { + printk(KERN_ERR "%s: over max integrity segments limit. (%u > %u)\n", + __func__, rq->nr_integrity_segments, + max_int_segs); + return BLK_STS_IOERR; + } + } + if (q->disk && should_fail_request(q->disk->part0, blk_rq_bytes(rq))) return BLK_STS_IOERR; diff --git a/block/blk-zoned.c b/block/blk-zoned.c index 30cad2bb9291..6a221c180889 100644 --- a/block/blk-zoned.c +++ b/block/blk-zoned.c @@ -623,6 +623,28 @@ static void disk_mark_zone_wplug_dead(struct blk_zone_wplug *zwplug) } } +static inline bool disk_check_zone_wplug_dead(struct blk_zone_wplug *zwplug) +{ + if (!(zwplug->flags & BLK_ZONE_WPLUG_DEAD)) + return false; + + /* + * If a new write is received right after a zone reset completes and + * while the disk_zone_wplugs_worker() thread has not yet released the + * reference on the zone write plug after processing the last write to + * the zone, then the new write BIO will see the zone write plug marked + * as dead. This case is however a false positive and a perfectly valid + * pattern. In such case, restore the zone write plug to a live one. + */ + if (!zwplug->wp_offset && bio_list_empty(&zwplug->bio_list)) { + zwplug->flags &= ~BLK_ZONE_WPLUG_DEAD; + refcount_inc(&zwplug->ref); + return false; + } + + return true; +} + static bool disk_zone_wplug_submit_bio(struct gendisk *disk, struct blk_zone_wplug *zwplug); @@ -1444,12 +1466,12 @@ static bool blk_zone_wplug_handle_write(struct bio *bio, unsigned int nr_segs) spin_lock_irqsave(&zwplug->lock, flags); /* - * If we got a zone write plug marked as dead, then the user is issuing - * writes to a full zone, or without synchronizing with zone reset or - * zone finish operations. In such case, fail the BIO to signal this - * invalid usage. + * Check if we got a zone write plug marked as dead. If yes, then the + * user is likely issuing writes to a full zone, or without + * synchronizing with zone reset or zone finish operations. In such + * case, fail the BIO to signal this invalid usage. */ - if (zwplug->flags & BLK_ZONE_WPLUG_DEAD) { + if (disk_check_zone_wplug_dead(zwplug)) { spin_unlock_irqrestore(&zwplug->lock, flags); disk_put_zone_wplug(zwplug); bio_io_error(bio); @@ -1979,8 +2001,10 @@ static void disk_set_zones_cond_array(struct gendisk *disk, u8 *zones_cond) void disk_free_zone_resources(struct gendisk *disk) { - if (disk->zone_wplugs_worker) + if (disk->zone_wplugs_worker) { kthread_stop(disk->zone_wplugs_worker); + disk->zone_wplugs_worker = NULL; + } WARN_ON_ONCE(!list_empty(&disk->zone_wplugs_list)); if (disk->zone_wplugs_wq) { @@ -2113,9 +2137,6 @@ static int disk_update_zone_resources(struct gendisk *disk, ret = queue_limits_commit_update(q, &lim); unfreeze: - if (ret) - disk_free_zone_resources(disk); - blk_mq_unfreeze_queue(q, memflags); return ret; diff --git a/block/ioctl.c b/block/ioctl.c index fc3be0549aa7..ab2c9ed79946 100644 --- a/block/ioctl.c +++ b/block/ioctl.c @@ -857,6 +857,8 @@ long compat_blkdev_ioctl(struct file *file, unsigned cmd, unsigned long arg) #endif struct blk_iou_cmd { + u64 start; + u64 len; int res; bool nowait; }; @@ -946,23 +948,27 @@ int blkdev_uring_cmd(struct io_uring_cmd *cmd, unsigned int issue_flags) { struct block_device *bdev = I_BDEV(cmd->file->f_mapping->host); struct blk_iou_cmd *bic = io_uring_cmd_to_pdu(cmd, struct blk_iou_cmd); - const struct io_uring_sqe *sqe = cmd->sqe; u32 cmd_op = cmd->cmd_op; - uint64_t start, len; - if (unlikely(sqe->ioprio || sqe->__pad1 || sqe->len || - sqe->rw_flags || sqe->file_index)) - return -EINVAL; + /* Read what we need from the SQE on the first issue */ + if (!(issue_flags & IORING_URING_CMD_REISSUE)) { + const struct io_uring_sqe *sqe = cmd->sqe; + + if (unlikely(sqe->ioprio || sqe->__pad1 || sqe->len || + sqe->rw_flags || sqe->file_index)) + return -EINVAL; + + bic->start = READ_ONCE(sqe->addr); + bic->len = READ_ONCE(sqe->addr3); + } bic->res = 0; bic->nowait = issue_flags & IO_URING_F_NONBLOCK; - start = READ_ONCE(sqe->addr); - len = READ_ONCE(sqe->addr3); - switch (cmd_op) { case BLOCK_URING_CMD_DISCARD: - return blkdev_cmd_discard(cmd, bdev, start, len, bic->nowait); + return blkdev_cmd_discard(cmd, bdev, bic->start, bic->len, + bic->nowait); } return -EINVAL; } diff --git a/crypto/authencesn.c b/crypto/authencesn.c index af3d584e584f..522df41365d8 100644 --- a/crypto/authencesn.c +++ b/crypto/authencesn.c @@ -390,6 +390,11 @@ static int crypto_authenc_esn_create(struct crypto_template *tmpl, auth = crypto_spawn_ahash_alg(&ctx->auth); auth_base = &auth->base; + if (auth->digestsize > 0 && auth->digestsize < 4) { + err = -EINVAL; + goto err_free_inst; + } + err = crypto_grab_skcipher(&ctx->enc, aead_crypto_instance(inst), crypto_attr_alg_name(tb[2]), 0, mask); if (err) diff --git a/crypto/krb5/krb5_api.c b/crypto/krb5/krb5_api.c index 23026d4206c8..c7ea40f900a7 100644 --- a/crypto/krb5/krb5_api.c +++ b/crypto/krb5/krb5_api.c @@ -134,27 +134,69 @@ EXPORT_SYMBOL(crypto_krb5_how_much_data); * Find the offset and size of the data in a secure message so that this * information can be used in the metadata buffer which will get added to the * digest by crypto_krb5_verify_mic(). + * + * Return: 0 if successful, -EBADMSG if the message is too short or -EINVAL if + * the mode is unsupported. */ -void crypto_krb5_where_is_the_data(const struct krb5_enctype *krb5, - enum krb5_crypto_mode mode, - size_t *_offset, size_t *_len) +int crypto_krb5_where_is_the_data(const struct krb5_enctype *krb5, + enum krb5_crypto_mode mode, + size_t *_offset, size_t *_len) { switch (mode) { case KRB5_CHECKSUM_MODE: + if (*_len < krb5->cksum_len) + return -EBADMSG; *_offset += krb5->cksum_len; *_len -= krb5->cksum_len; - return; + return 0; case KRB5_ENCRYPT_MODE: + if (*_len < krb5->conf_len + krb5->cksum_len) + return -EBADMSG; *_offset += krb5->conf_len; *_len -= krb5->conf_len + krb5->cksum_len; - return; + return 0; default: WARN_ON_ONCE(1); - return; + return -EINVAL; } } EXPORT_SYMBOL(crypto_krb5_where_is_the_data); +/** + * crypto_krb5_check_data_len - Check a message is big enough + * @krb5: The encoding to use. + * @mode: Mode of operation. + * @len: The length of the secure blob. + * @min_content: Minimum length of the content inside the blob. + * + * Check that a message is large enough to hold whatever bits the encryption + * type wants to glue on (nonce, checksum) plus a minimum amount of content. + * + * Return: 0 if successful, -EBADMSG if the message is too short or -EINVAL if + * the mode is unsupported. + */ +int crypto_krb5_check_data_len(const struct krb5_enctype *krb5, + enum krb5_crypto_mode mode, + size_t len, size_t min_content) +{ + switch (mode) { + case KRB5_CHECKSUM_MODE: + if (len < krb5->cksum_len || + len - krb5->cksum_len < min_content) + return -EBADMSG; + return 0; + case KRB5_ENCRYPT_MODE: + if (len < krb5->conf_len + krb5->cksum_len || + len - (krb5->conf_len + krb5->cksum_len) < min_content) + return -EBADMSG; + return 0; + default: + WARN_ON_ONCE(1); + return -EINVAL; + } +} +EXPORT_SYMBOL(crypto_krb5_check_data_len); + /* * Prepare the encryption with derived key data. */ diff --git a/drivers/accel/amdxdna/Makefile b/drivers/accel/amdxdna/Makefile index cf9bf19dedb9..05cce0a38692 100644 --- a/drivers/accel/amdxdna/Makefile +++ b/drivers/accel/amdxdna/Makefile @@ -1,14 +1,19 @@ # SPDX-License-Identifier: GPL-2.0-only amdxdna-y := \ + aie.o \ + aie_psp.o \ + aie_smu.o \ aie2_ctx.o \ aie2_error.o \ aie2_message.o \ aie2_pci.o \ aie2_pm.o \ - aie2_psp.o \ - aie2_smu.o \ aie2_solver.o \ + aie4_ctx.o \ + aie4_message.o \ + aie4_pci.o \ + amdxdna_cbuf.o \ amdxdna_ctx.o \ amdxdna_gem.o \ amdxdna_iommu.o \ @@ -19,7 +24,11 @@ amdxdna-y := \ amdxdna_sysfs.o \ amdxdna_ubuf.o \ npu1_regs.o \ + npu3_regs.o \ npu4_regs.o \ npu5_regs.o \ npu6_regs.o + +amdxdna-$(CONFIG_PCI_IOV) += aie4_sriov.o +amdxdna-$(CONFIG_DEBUG_FS) += amdxdna_debugfs.o obj-$(CONFIG_DRM_ACCEL_AMDXDNA) = amdxdna.o diff --git a/drivers/accel/amdxdna/aie.c b/drivers/accel/amdxdna/aie.c new file mode 100644 index 000000000000..dd6f36f222c7 --- /dev/null +++ b/drivers/accel/amdxdna/aie.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include + +#include "aie.h" +#include "amdxdna_mailbox_helper.h" +#include "amdxdna_mailbox.h" +#include "amdxdna_pci_drv.h" + +void aie_dump_mgmt_chann_debug(struct aie_device *aie) +{ + struct amdxdna_dev *xdna = aie->xdna; + + XDNA_DBG(xdna, "i2x tail 0x%x", aie->mgmt_i2x.mb_tail_ptr_reg); + XDNA_DBG(xdna, "i2x head 0x%x", aie->mgmt_i2x.mb_head_ptr_reg); + XDNA_DBG(xdna, "i2x ringbuf 0x%x", aie->mgmt_i2x.rb_start_addr); + XDNA_DBG(xdna, "i2x rsize 0x%x", aie->mgmt_i2x.rb_size); + XDNA_DBG(xdna, "x2i tail 0x%x", aie->mgmt_x2i.mb_tail_ptr_reg); + XDNA_DBG(xdna, "x2i head 0x%x", aie->mgmt_x2i.mb_head_ptr_reg); + XDNA_DBG(xdna, "x2i ringbuf 0x%x", aie->mgmt_x2i.rb_start_addr); + XDNA_DBG(xdna, "x2i rsize 0x%x", aie->mgmt_x2i.rb_size); + XDNA_DBG(xdna, "x2i chann index 0x%x", aie->mgmt_chan_idx); + XDNA_DBG(xdna, "mailbox protocol major 0x%x", aie->mgmt_prot_major); + XDNA_DBG(xdna, "mailbox protocol minor 0x%x", aie->mgmt_prot_minor); +} + +void aie_destroy_chann(struct aie_device *aie, struct mailbox_channel **chann) +{ + struct amdxdna_dev *xdna = aie->xdna; + + drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); + + if (!*chann) + return; + + xdna_mailbox_stop_channel(*chann); + xdna_mailbox_free_channel(*chann); + *chann = NULL; +} + +int aie_send_mgmt_msg_wait(struct aie_device *aie, struct xdna_mailbox_msg *msg) +{ + struct amdxdna_dev *xdna = aie->xdna; + struct xdna_notify *hdl = msg->handle; + int ret; + + drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); + + if (!aie->mgmt_chann) + return -ENODEV; + + ret = xdna_send_msg_wait(xdna, aie->mgmt_chann, msg); + if (ret == -ETIME) + aie_destroy_chann(aie, &aie->mgmt_chann); + + if (!ret && *hdl->status) { + XDNA_ERR(xdna, "command opcode 0x%x failed, status 0x%x", + msg->opcode, *hdl->data); + ret = -EINVAL; + } + + return ret; +} + +int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor) +{ + const struct amdxdna_fw_feature_tbl *feature; + bool found = false; + + for (feature = aie->xdna->dev_info->fw_feature_tbl; + feature->major; feature++) { + if (feature->major != fw_major) + continue; + if (fw_minor < feature->min_minor) + continue; + if (feature->max_minor > 0 && fw_minor > feature->max_minor) + continue; + + aie->feature_mask |= feature->features; + + /* firmware version matches one of the driver support entry */ + found = true; + } + + return found ? 0 : -EOPNOTSUPP; +} + +static void amdxdna_update_vbnv(struct amdxdna_dev *xdna, + const struct amdxdna_rev_vbnv *tbl, + u32 rev) +{ + int i; + + for (i = 0; tbl[i].vbnv; i++) { + if (tbl[i].revision == rev) { + xdna->vbnv = tbl[i].vbnv; + break; + } + } +} + +void amdxdna_vbnv_init(struct amdxdna_dev *xdna) +{ + const struct amdxdna_dev_info *info = xdna->dev_info; + u32 rev; + + xdna->vbnv = info->default_vbnv; + + if (!info->ops->get_dev_revision || !info->rev_vbnv_tbl) + return; + + if (info->ops->get_dev_revision(xdna, &rev)) + return; + + amdxdna_update_vbnv(xdna, info->rev_vbnv_tbl, rev); +} + +int amdxdna_get_metadata(struct aie_device *aie, + struct amdxdna_client *client, + struct amdxdna_drm_get_info *args) +{ + int ret = 0; + u32 buf_sz; + + buf_sz = min(args->buffer_size, sizeof(aie->metadata)); + if (copy_to_user(u64_to_user_ptr(args->buffer), &aie->metadata, buf_sz)) + ret = -EFAULT; + + return ret; +} + +void *amdxdna_alloc_msg_buffer(struct amdxdna_dev *xdna, u32 *size, + dma_addr_t *dma_addr) +{ + void *vaddr; + int order; + + *size = max_t(u32, *size, SZ_8K); + order = get_order(*size); + if (order > MAX_PAGE_ORDER) + return ERR_PTR(-EINVAL); + *size = PAGE_SIZE << order; + + if (amdxdna_iova_on(xdna)) + return amdxdna_iommu_alloc(xdna, *size, dma_addr); + + vaddr = dma_alloc_noncoherent(xdna->ddev.dev, *size, dma_addr, + DMA_FROM_DEVICE, GFP_KERNEL); + if (!vaddr) + return ERR_PTR(-ENOMEM); + + return vaddr; +} + +void amdxdna_free_msg_buffer(struct amdxdna_dev *xdna, size_t size, + void *cpu_addr, dma_addr_t dma_addr) +{ + if (amdxdna_iova_on(xdna)) { + amdxdna_iommu_free(xdna, size, cpu_addr, dma_addr); + return; + } + + dma_free_noncoherent(xdna->ddev.dev, size, cpu_addr, dma_addr, DMA_FROM_DEVICE); +} diff --git a/drivers/accel/amdxdna/aie.h b/drivers/accel/amdxdna/aie.h new file mode 100644 index 000000000000..0483d582b7f8 --- /dev/null +++ b/drivers/accel/amdxdna/aie.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ +#ifndef _AIE_H_ +#define _AIE_H_ + +#include +#include "amdxdna_pci_drv.h" +#include "amdxdna_mailbox.h" + +#define AIE_INTERVAL 20000 /* us */ +#define AIE_TIMEOUT 1000000 /* us */ + +struct psp_device; +struct smu_device; + +struct aie_device { + struct amdxdna_dev *xdna; + struct mailbox_channel *mgmt_chann; + struct xdna_mailbox_chann_res mgmt_x2i; + struct xdna_mailbox_chann_res mgmt_i2x; + u32 mgmt_chan_idx; + u32 mgmt_prot_major; + u32 mgmt_prot_minor; + unsigned long feature_mask; + + struct psp_device *psp_hdl; + struct smu_device *smu_hdl; + + struct amdxdna_drm_query_aie_metadata metadata; +}; + +#define DECLARE_AIE_MSG(name, op) \ + DECLARE_XDNA_MSG_COMMON(name, op, -1) +#define AIE_FEATURE_ON(aie, feature) test_bit(feature, &(aie)->feature_mask) + +#define PSP_REG_BAR(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].bar_idx) +#define PSP_REG_OFF(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].offset) + +#define SMU_REG_BAR(ndev, idx) ((ndev)->priv->smu_regs_off[(idx)].bar_idx) +#define SMU_REG_OFF(ndev, idx) ((ndev)->priv->smu_regs_off[(idx)].offset) + +#define DEFINE_BAR_OFFSET(reg_name, bar, reg_addr) \ + [reg_name] = {bar##_BAR_INDEX, (reg_addr) - bar##_BAR_BASE} + +enum smu_reg_idx { + SMU_CMD_REG = 0, + SMU_ARG_REG, + SMU_INTR_REG, + SMU_RESP_REG, + SMU_OUT_REG, + SMU_MAX_REGS /* Keep this at the end */ +}; + +enum psp_reg_idx { + PSP_CMD_REG = 0, + PSP_ARG0_REG, + PSP_ARG1_REG, + PSP_ARG2_REG, + PSP_NUM_IN_REGS, /* number of input registers */ + PSP_INTR_REG = PSP_NUM_IN_REGS, + PSP_STATUS_REG, + PSP_RESP_REG, + PSP_PWAITMODE_REG, + PSP_MAX_REGS /* Keep this at the end */ +}; + +struct aie_bar_off_pair { + int bar_idx; + u32 offset; +}; + +struct smu_config { + void __iomem *smu_regs[SMU_MAX_REGS]; +}; + +struct psp_config { + const void *fw_buf; + u32 fw_size; + const void *certfw_buf; + u32 certfw_size; + void __iomem *psp_regs[PSP_MAX_REGS]; + u32 arg2_mask; + u32 notify_val; +}; + +/* Device revision to VBNV string mapping table entry */ +struct amdxdna_rev_vbnv { + u32 revision; + const char *vbnv; +}; + +/* aie.c */ +void aie_dump_mgmt_chann_debug(struct aie_device *aie); +void aie_destroy_chann(struct aie_device *aie, struct mailbox_channel **chann); +int aie_send_mgmt_msg_wait(struct aie_device *aie, struct xdna_mailbox_msg *msg); +int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor); +void amdxdna_vbnv_init(struct amdxdna_dev *xdna); +int amdxdna_get_metadata(struct aie_device *aie, struct amdxdna_client *client, + struct amdxdna_drm_get_info *args); +void *amdxdna_alloc_msg_buffer(struct amdxdna_dev *xdna, u32 *size, + dma_addr_t *dma_addr); +void amdxdna_free_msg_buffer(struct amdxdna_dev *xdna, size_t size, + void *cpu_addr, dma_addr_t dma_addr); + +/* aie_psp.c */ +struct psp_device *aiem_psp_create(struct drm_device *ddev, struct psp_config *conf); +int aie_psp_start(struct psp_device *psp); +void aie_psp_stop(struct psp_device *psp); +int aie_psp_waitmode_poll(struct psp_device *psp); + +/* aie_smu.c */ +struct smu_device *aiem_smu_create(struct drm_device *ddev, struct smu_config *conf); +int aie_smu_init(struct smu_device *smu); +void aie_smu_fini(struct smu_device *smu); +int aie_smu_set_clocks(struct smu_device *smu, u32 *npuclk, u32 *hclk); +int aie_smu_set_dpm(struct smu_device *smu, u32 dpm_level); + +#endif /* _AIE_H_ */ diff --git a/drivers/accel/amdxdna/aie2_ctx.c b/drivers/accel/amdxdna/aie2_ctx.c index 286379d9511d..658a5fb1fda6 100644 --- a/drivers/accel/amdxdna/aie2_ctx.c +++ b/drivers/accel/amdxdna/aie2_ctx.c @@ -27,7 +27,9 @@ static bool force_cmdlist = true; module_param(force_cmdlist, bool, 0600); MODULE_PARM_DESC(force_cmdlist, "Force use command list (Default true)"); -#define HWCTX_MAX_TIMEOUT 60000 /* milliseconds */ +uint tdr_timeout_ms = 2000; +module_param(tdr_timeout_ms, int, 0400); +MODULE_PARM_DESC(tdr_timeout_ms, "TDR (Timeout Detection and Recovery) timeout in milliseconds (0 = disable)"); struct aie2_ctx_health { struct amdxdna_ctx_health header; @@ -39,11 +41,30 @@ struct aie2_ctx_health { u32 fatal_error_app_module; }; +static inline void aie2_tdr_signal(struct amdxdna_dev *xdna) +{ + WRITE_ONCE(xdna->dev_handle->tdr_status, AIE2_TDR_SIGNALED); +} + +static bool aie2_tdr_detect(struct amdxdna_dev *xdna) +{ + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; + + if (READ_ONCE(ndev->tdr_status) == AIE2_TDR_WAIT) { + XDNA_ERR(xdna, "TDR timeout detected"); + return true; + } + + WRITE_ONCE(ndev->tdr_status, AIE2_TDR_WAIT); + return false; +} + static void aie2_job_release(struct kref *ref) { struct amdxdna_sched_job *job; job = container_of(ref, struct amdxdna_sched_job, refcnt); + amdxdna_sched_job_cleanup(job); atomic64_inc(&job->hwctx->job_free_cnt); wake_up(&job->hwctx->priv->job_free_wq); @@ -70,6 +91,7 @@ static void aie2_hwctx_stop(struct amdxdna_dev *xdna, struct amdxdna_hwctx *hwct static int aie2_hwctx_restart(struct amdxdna_dev *xdna, struct amdxdna_hwctx *hwctx) { struct amdxdna_gem_obj *heap = hwctx->priv->heap; + unsigned long heap_id; int ret; ret = aie2_create_context(xdna->dev_handle, hwctx); @@ -86,6 +108,17 @@ static int aie2_hwctx_restart(struct amdxdna_dev *xdna, struct amdxdna_hwctx *hw goto out; } + xa_for_each_range(&hwctx->client->dev_heap_xa, heap_id, heap, 1, + hwctx->last_attached_heap) { + ret = aie2_add_host_buf(xdna->dev_handle, hwctx->fw_ctx_id, + amdxdna_obj_dma_addr(heap), + heap->mem.size); + if (ret) { + XDNA_ERR(xdna, "Add heap %ld failed ret %d", heap_id, ret); + goto out; + } + } + ret = aie2_config_cu(hwctx, NULL); if (ret) { XDNA_ERR(xdna, "Config cu failed, ret %d", ret); @@ -175,8 +208,10 @@ aie2_sched_notify(struct amdxdna_sched_job *job) { struct dma_fence *fence = job->fence; - trace_xdna_job(&job->base, job->hwctx->name, "signaled fence", job->seq); + trace_xdna_job(&job->base, job->hwctx->name, "signaling fence", + job->seq, job->drv_cmd ? job->drv_cmd->opcode : DEFAULT_IO); + aie2_tdr_signal(job->hwctx->client->xdna); job->hwctx->priv->completed++; dma_fence_signal(fence); @@ -345,6 +380,9 @@ aie2_sched_job_run(struct drm_sched_job *sched_job) struct dma_fence *fence; int ret; + trace_xdna_job(sched_job, hwctx->name, "job run", + job->seq, job->drv_cmd ? job->drv_cmd->opcode : DEFAULT_IO); + if (!hwctx->priv->mbox_chann) return NULL; @@ -360,6 +398,7 @@ aie2_sched_job_run(struct drm_sched_job *sched_job) ret = aie2_sync_bo(hwctx, job, aie2_sched_drvcmd_resp_handler); break; case ATTACH_DEBUG_BO: + case DETACH_DEBUG_BO: ret = aie2_config_debug_bo(hwctx, job, aie2_sched_drvcmd_resp_handler); break; default: @@ -384,8 +423,11 @@ aie2_sched_job_run(struct drm_sched_job *sched_job) aie2_job_put(job); mmput(job->mm); fence = ERR_PTR(ret); + } else { + aie2_tdr_signal(hwctx->client->xdna); } - trace_xdna_job(sched_job, hwctx->name, "sent to device", job->seq); + trace_xdna_job(sched_job, hwctx->name, "sent to device", + job->seq, job->drv_cmd ? job->drv_cmd->opcode : DEFAULT_IO); return fence; } @@ -395,7 +437,8 @@ static void aie2_sched_job_free(struct drm_sched_job *sched_job) struct amdxdna_sched_job *job = drm_job_to_xdna_job(sched_job); struct amdxdna_hwctx *hwctx = job->hwctx; - trace_xdna_job(sched_job, hwctx->name, "job free", job->seq); + trace_xdna_job(sched_job, hwctx->name, "job free", + job->seq, job->drv_cmd ? job->drv_cmd->opcode : DEFAULT_IO); if (!job->job_done) up(&hwctx->priv->job_sem); @@ -413,10 +456,12 @@ aie2_sched_job_timedout(struct drm_sched_job *sched_job) int ret; xdna = hwctx->client->xdna; - trace_xdna_job(sched_job, hwctx->name, "job timedout", job->seq); - job->job_timeout = true; - mutex_lock(&xdna->dev_lock); + guard(mutex)(&xdna->dev_lock); + + if (!aie2_tdr_detect(xdna)) + return DRM_GPU_SCHED_STAT_NO_HANG; + report = kzalloc_obj(*report); if (!report) goto reset_hwctx; @@ -428,10 +473,10 @@ aie2_sched_job_timedout(struct drm_sched_job *sched_job) job->aie2_job_health = report; reset_hwctx: + job->job_timeout = true; aie2_hwctx_stop(xdna, hwctx, sched_job); aie2_hwctx_restart(xdna, hwctx); - mutex_unlock(&xdna->dev_lock); return DRM_GPU_SCHED_STAT_RESET; } @@ -456,12 +501,12 @@ static int aie2_hwctx_col_list(struct amdxdna_hwctx *hwctx) } ndev = xdna->dev_handle; - if (unlikely(!ndev->metadata.core.row_count)) { + if (unlikely(!ndev->aie.metadata.core.row_count)) { XDNA_WARN(xdna, "Core tile row count is zero"); return -EINVAL; } - hwctx->num_col = hwctx->num_tiles / ndev->metadata.core.row_count; + hwctx->num_col = hwctx->num_tiles / ndev->aie.metadata.core.row_count; if (!hwctx->num_col || hwctx->num_col > ndev->total_col) { XDNA_ERR(xdna, "Invalid num_col %d", hwctx->num_col); return -EINVAL; @@ -513,22 +558,24 @@ static int aie2_alloc_resource(struct amdxdna_hwctx *hwctx) { struct amdxdna_dev *xdna = hwctx->client->xdna; struct alloc_requests *xrs_req; + u32 temporal_only_col = 0; int ret; - if (AIE2_FEATURE_ON(xdna->dev_handle, AIE2_TEMPORAL_ONLY)) { - hwctx->num_unused_col = xdna->dev_handle->total_col - hwctx->num_col; - hwctx->num_col = xdna->dev_handle->total_col; - return aie2_create_context(xdna->dev_handle, hwctx); - } - xrs_req = kzalloc_obj(*xrs_req); if (!xrs_req) return -ENOMEM; - xrs_req->cdo.start_cols = hwctx->col_list; - xrs_req->cdo.cols_len = hwctx->col_list_len; - xrs_req->cdo.ncols = hwctx->num_col; - xrs_req->cdo.qos_cap.opc = hwctx->max_opc; + if (AIE_FEATURE_ON(&xdna->dev_handle->aie, AIE2_TEMPORAL_ONLY)) { + xrs_req->cdo.start_cols = &temporal_only_col; + xrs_req->cdo.cols_len = 1; + xrs_req->cdo.ncols = xdna->dev_handle->total_col; + } else { + xrs_req->cdo.start_cols = hwctx->col_list; + xrs_req->cdo.cols_len = hwctx->col_list_len; + xrs_req->cdo.ncols = hwctx->num_col; + } + /* Use platform opc */ + xrs_req->cdo.qos_cap.opc = xdna->dev_handle->priv->col_opc * hwctx->num_col; xrs_req->rqos.gops = hwctx->qos.gops; xrs_req->rqos.fps = hwctx->qos.fps; @@ -552,15 +599,9 @@ static void aie2_release_resource(struct amdxdna_hwctx *hwctx) struct amdxdna_dev *xdna = hwctx->client->xdna; int ret; - if (AIE2_FEATURE_ON(xdna->dev_handle, AIE2_TEMPORAL_ONLY)) { - ret = aie2_destroy_context(xdna->dev_handle, hwctx); - if (ret && ret != -ENODEV) - XDNA_ERR(xdna, "Destroy temporal only context failed, ret %d", ret); - } else { - ret = xrs_release_resource(xdna->xrs_hdl, (uintptr_t)hwctx); - if (ret) - XDNA_ERR(xdna, "Release AIE resource failed, ret %d", ret); - } + ret = xrs_release_resource(xdna->xrs_hdl, (uintptr_t)hwctx); + if (ret) + XDNA_ERR(xdna, "Release AIE resource failed, ret %d", ret); } static int aie2_ctx_syncobj_create(struct amdxdna_hwctx *hwctx) @@ -605,9 +646,8 @@ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx) struct amdxdna_dev *xdna = client->xdna; const struct drm_sched_init_args args = { .ops = &sched_ops, - .num_rqs = DRM_SCHED_PRIORITY_COUNT, .credit_limit = HWCTX_MAX_CMDS, - .timeout = msecs_to_jiffies(HWCTX_MAX_TIMEOUT), + .timeout = msecs_to_jiffies(tdr_timeout_ms), .name = "amdxdna_js", .dev = xdna->ddev.dev, }; @@ -622,7 +662,7 @@ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx) hwctx->priv = priv; mutex_lock(&client->mm_lock); - heap = client->dev_heap; + heap = xa_load(&client->dev_heap_xa, 0); if (!heap) { XDNA_ERR(xdna, "The client dev heap object not exist"); mutex_unlock(&client->mm_lock); @@ -704,6 +744,12 @@ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx) goto release_resource; } + ret = amdxdna_update_heap(client, hwctx); + if (ret) { + XDNA_ERR(xdna, "Update heap failed, ret %d", ret); + goto release_resource; + } + ret = aie2_ctx_syncobj_create(hwctx); if (ret) { XDNA_ERR(xdna, "Create syncobj failed, ret %d", ret); @@ -1133,3 +1179,28 @@ void aie2_hmm_invalidate(struct amdxdna_gem_obj *abo, else if (ret == -ERESTARTSYS) XDNA_DBG(xdna, "Wait for bo interrupted by signal"); } + +int aie2_hwctx_heap_expand(struct amdxdna_hwctx *hwctx, + struct amdxdna_gem_obj *heap) +{ + struct amdxdna_client *client = hwctx->client; + struct amdxdna_dev *xdna = client->xdna; + u64 addr; + int ret; + + ret = amdxdna_pm_resume_get_locked(xdna); + if (ret) + return ret; + + addr = amdxdna_obj_dma_addr(heap); + ret = aie2_add_host_buf(xdna->dev_handle, hwctx->fw_ctx_id, + addr, heap->mem.size); + if (ret) { + XDNA_ERR(xdna, "Add heap failed hwctx %s 0x%lx ret %d", + hwctx->name, heap->mem.size, ret); + } + + amdxdna_pm_suspend_put(xdna); + + return ret; +} diff --git a/drivers/accel/amdxdna/aie2_error.c b/drivers/accel/amdxdna/aie2_error.c index 58abb59b6153..babdac0157ab 100644 --- a/drivers/accel/amdxdna/aie2_error.c +++ b/drivers/accel/amdxdna/aie2_error.c @@ -11,6 +11,7 @@ #include #include +#include "aie.h" #include "aie2_msg_priv.h" #include "aie2_pci.h" #include "amdxdna_error.h" @@ -249,12 +250,12 @@ static u32 aie2_error_backtrack(struct amdxdna_dev_hdl *ndev, void *err_info, u3 enum aie_error_category cat; cat = aie_get_error_category(err->row, err->event_id, err->mod_type); - XDNA_ERR(ndev->xdna, "Row: %d, Col: %d, module %d, event ID %d, category %d", + XDNA_ERR(ndev->aie.xdna, "Row: %d, Col: %d, module %d, event ID %d, category %d", err->row, err->col, err->mod_type, err->event_id, cat); if (err->col >= 32) { - XDNA_WARN(ndev->xdna, "Invalid column number"); + XDNA_WARN(ndev->aie.xdna, "Invalid column number"); break; } @@ -294,7 +295,7 @@ static void aie2_error_worker(struct work_struct *err_work) e = container_of(err_work, struct async_event, work); - xdna = e->ndev->xdna; + xdna = e->ndev->aie.xdna; if (e->resp.status == MAX_AIE2_STATUS_CODE) return; @@ -329,7 +330,7 @@ static void aie2_error_worker(struct work_struct *err_work) void aie2_error_async_events_free(struct amdxdna_dev_hdl *ndev) { - struct amdxdna_dev *xdna = ndev->xdna; + struct amdxdna_dev *xdna = ndev->aie.xdna; struct async_events *events; events = ndev->async_events; @@ -338,13 +339,13 @@ void aie2_error_async_events_free(struct amdxdna_dev_hdl *ndev) destroy_workqueue(events->wq); mutex_lock(&xdna->dev_lock); - aie2_free_msg_buffer(ndev, events->size, events->buf, events->addr); + amdxdna_free_msg_buffer(xdna, events->size, events->buf, events->addr); kfree(events); } int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev) { - struct amdxdna_dev *xdna = ndev->xdna; + struct amdxdna_dev *xdna = ndev->aie.xdna; u32 total_col = ndev->total_col; u32 total_size = ASYNC_BUF_SIZE * total_col; struct async_events *events; @@ -354,7 +355,7 @@ int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev) if (!events) return -ENOMEM; - events->buf = aie2_alloc_msg_buffer(ndev, &total_size, &events->addr); + events->buf = amdxdna_alloc_msg_buffer(xdna, &total_size, &events->addr); if (IS_ERR(events->buf)) { ret = PTR_ERR(events->buf); goto free_events; @@ -394,7 +395,7 @@ int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev) free_wq: destroy_workqueue(events->wq); free_buf: - aie2_free_msg_buffer(ndev, events->size, events->buf, events->addr); + amdxdna_free_msg_buffer(xdna, events->size, events->buf, events->addr); free_events: kfree(events); return ret; @@ -402,12 +403,15 @@ int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev) int aie2_get_array_async_error(struct amdxdna_dev_hdl *ndev, struct amdxdna_drm_get_array *args) { - struct amdxdna_dev *xdna = ndev->xdna; + struct amdxdna_dev *xdna = ndev->aie.xdna; drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); + if (!args->num_element) + return -EINVAL; + args->num_element = 1; - args->element_size = sizeof(ndev->last_async_err); + args->element_size = min(args->element_size, sizeof(ndev->last_async_err)); if (copy_to_user(u64_to_user_ptr(args->buffer), &ndev->last_async_err, args->element_size)) return -EFAULT; diff --git a/drivers/accel/amdxdna/aie2_message.c b/drivers/accel/amdxdna/aie2_message.c index a1c546c3e81c..c4b364801cc0 100644 --- a/drivers/accel/amdxdna/aie2_message.c +++ b/drivers/accel/amdxdna/aie2_message.c @@ -16,6 +16,7 @@ #include #include +#include "aie.h" #include "aie2_msg_priv.h" #include "aie2_pci.h" #include "amdxdna_ctx.h" @@ -24,103 +25,40 @@ #include "amdxdna_mailbox_helper.h" #include "amdxdna_pci_drv.h" -#define DECLARE_AIE2_MSG(name, op) \ - DECLARE_XDNA_MSG_COMMON(name, op, MAX_AIE2_STATUS_CODE) - #define EXEC_MSG_OPS(xdna) ((xdna)->dev_handle->exec_msg_ops) -static int aie2_send_mgmt_msg_wait(struct amdxdna_dev_hdl *ndev, - struct xdna_mailbox_msg *msg) -{ - struct amdxdna_dev *xdna = ndev->xdna; - struct xdna_notify *hdl = msg->handle; - int ret; - - if (!ndev->mgmt_chann) - return -ENODEV; - - ret = xdna_send_msg_wait(xdna, ndev->mgmt_chann, msg); - if (ret == -ETIME) - aie2_destroy_mgmt_chann(ndev); - - if (!ret && *hdl->status != AIE2_STATUS_SUCCESS) { - XDNA_ERR(xdna, "command opcode 0x%x failed, status 0x%x", - msg->opcode, *hdl->data); - ret = -EINVAL; - } - - return ret; -} - -void *aie2_alloc_msg_buffer(struct amdxdna_dev_hdl *ndev, u32 *size, - dma_addr_t *dma_addr) -{ - struct amdxdna_dev *xdna = ndev->xdna; - void *vaddr; - int order; - - *size = max(*size, SZ_8K); - order = get_order(*size); - if (order > MAX_PAGE_ORDER) - return ERR_PTR(-EINVAL); - *size = PAGE_SIZE << order; - - if (amdxdna_iova_on(xdna)) - return amdxdna_iommu_alloc(xdna, *size, dma_addr); - - vaddr = dma_alloc_noncoherent(xdna->ddev.dev, *size, dma_addr, - DMA_FROM_DEVICE, GFP_KERNEL); - if (!vaddr) - return ERR_PTR(-ENOMEM); - - return vaddr; -} - -void aie2_free_msg_buffer(struct amdxdna_dev_hdl *ndev, size_t size, - void *cpu_addr, dma_addr_t dma_addr) -{ - struct amdxdna_dev *xdna = ndev->xdna; - - if (amdxdna_iova_on(xdna)) { - amdxdna_iommu_free(xdna, size, cpu_addr, dma_addr); - return; - } - - dma_free_noncoherent(xdna->ddev.dev, size, cpu_addr, dma_addr, DMA_FROM_DEVICE); -} - int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev) { - DECLARE_AIE2_MSG(suspend, MSG_OP_SUSPEND); + DECLARE_AIE_MSG(suspend, MSG_OP_SUSPEND); int ret; - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret) { - XDNA_ERR(ndev->xdna, "Failed to suspend fw, ret %d", ret); + XDNA_ERR(ndev->aie.xdna, "Failed to suspend fw, ret %d", ret); return ret; } - return aie2_psp_waitmode_poll(ndev->psp_hdl); + return aie_psp_waitmode_poll(ndev->aie.psp_hdl); } int aie2_resume_fw(struct amdxdna_dev_hdl *ndev) { - DECLARE_AIE2_MSG(suspend, MSG_OP_RESUME); + DECLARE_AIE_MSG(suspend, MSG_OP_RESUME); - return aie2_send_mgmt_msg_wait(ndev, &msg); + return aie_send_mgmt_msg_wait(&ndev->aie, &msg); } int aie2_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 value) { - DECLARE_AIE2_MSG(set_runtime_cfg, MSG_OP_SET_RUNTIME_CONFIG); + DECLARE_AIE_MSG(set_runtime_cfg, MSG_OP_SET_RUNTIME_CONFIG); int ret; req.type = type; req.value = value; - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret) { - XDNA_ERR(ndev->xdna, "Failed to set runtime config, ret %d", ret); + XDNA_ERR(ndev->aie.xdna, "Failed to set runtime config, ret %d", ret); return ret; } @@ -129,13 +67,13 @@ int aie2_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 value) int aie2_get_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 *value) { - DECLARE_AIE2_MSG(get_runtime_cfg, MSG_OP_GET_RUNTIME_CONFIG); + DECLARE_AIE_MSG(get_runtime_cfg, MSG_OP_GET_RUNTIME_CONFIG); int ret; req.type = type; - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret) { - XDNA_ERR(ndev->xdna, "Failed to get runtime config, ret %d", ret); + XDNA_ERR(ndev->aie.xdna, "Failed to get runtime config, ret %d", ret); return ret; } @@ -145,20 +83,21 @@ int aie2_get_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 *value) int aie2_assign_mgmt_pasid(struct amdxdna_dev_hdl *ndev, u16 pasid) { - DECLARE_AIE2_MSG(assign_mgmt_pasid, MSG_OP_ASSIGN_MGMT_PASID); + DECLARE_AIE_MSG(assign_mgmt_pasid, MSG_OP_ASSIGN_MGMT_PASID); req.pasid = pasid; - return aie2_send_mgmt_msg_wait(ndev, &msg); + return aie_send_mgmt_msg_wait(&ndev->aie, &msg); } -int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, struct aie_version *version) +int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, + struct amdxdna_drm_query_aie_version *version) { - DECLARE_AIE2_MSG(aie_version_info, MSG_OP_QUERY_AIE_VERSION); - struct amdxdna_dev *xdna = ndev->xdna; + DECLARE_AIE_MSG(aie_version_info, MSG_OP_QUERY_AIE_VERSION); + struct amdxdna_dev *xdna = ndev->aie.xdna; int ret; - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret) return ret; @@ -171,16 +110,17 @@ int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, struct aie_version *ver return 0; } -int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, struct aie_metadata *metadata) +int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, + struct amdxdna_drm_query_aie_metadata *metadata) { - DECLARE_AIE2_MSG(aie_tile_info, MSG_OP_QUERY_AIE_TILE_INFO); + DECLARE_AIE_MSG(aie_tile_info, MSG_OP_QUERY_AIE_TILE_INFO); int ret; - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret) return ret; - metadata->size = resp.info.size; + metadata->col_size = resp.info.size; metadata->cols = resp.info.cols; metadata->rows = resp.info.rows; @@ -211,10 +151,10 @@ int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, struct aie_metadata *m int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev, struct amdxdna_fw_ver *fw_ver) { - DECLARE_AIE2_MSG(firmware_version, MSG_OP_GET_FIRMWARE_VERSION); + DECLARE_AIE_MSG(firmware_version, MSG_OP_GET_FIRMWARE_VERSION); int ret; - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret) return ret; @@ -228,12 +168,12 @@ int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev, static int aie2_destroy_context_req(struct amdxdna_dev_hdl *ndev, u32 id) { - DECLARE_AIE2_MSG(destroy_ctx, MSG_OP_DESTROY_CONTEXT); - struct amdxdna_dev *xdna = ndev->xdna; + DECLARE_AIE_MSG(destroy_ctx, MSG_OP_DESTROY_CONTEXT); + struct amdxdna_dev *xdna = ndev->aie.xdna; int ret; req.context_id = id; - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret && ret != -ENODEV) XDNA_WARN(xdna, "Destroy context failed, ret %d", ret); else if (ret == -ENODEV) @@ -245,7 +185,7 @@ static int aie2_destroy_context_req(struct amdxdna_dev_hdl *ndev, u32 id) static u32 aie2_get_context_priority(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) { - if (!AIE2_FEATURE_ON(ndev, AIE2_PREEMPT)) + if (!AIE_FEATURE_ON(&ndev->aie, AIE2_PREEMPT)) return PRIORITY_HIGH; switch (hwctx->qos.priority) { @@ -264,8 +204,8 @@ static u32 aie2_get_context_priority(struct amdxdna_dev_hdl *ndev, int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) { - DECLARE_AIE2_MSG(create_ctx, MSG_OP_CREATE_CONTEXT); - struct amdxdna_dev *xdna = ndev->xdna; + DECLARE_AIE_MSG(create_ctx, MSG_OP_CREATE_CONTEXT); + struct amdxdna_dev *xdna = ndev->aie.xdna; struct xdna_mailbox_chann_res x2i; struct xdna_mailbox_chann_res i2x; struct cq_pair *cq_pair; @@ -280,7 +220,7 @@ int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwct req.pasid = amdxdna_pasid_on(hwctx->client) ? hwctx->client->pasid : 0; req.context_priority = aie2_get_context_priority(ndev, hwctx); - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret) return ret; @@ -344,7 +284,7 @@ int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwct int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) { - struct amdxdna_dev *xdna = ndev->xdna; + struct amdxdna_dev *xdna = ndev->aie.xdna; int ret; if (!hwctx->priv->mbox_chann) @@ -361,25 +301,59 @@ int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwc return ret; } -int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size) +static int aie2_send_host_buf_msgs(struct amdxdna_dev_hdl *ndev, u32 context_id, + u64 addr, u64 size, u32 initial_opcode) { - DECLARE_AIE2_MSG(map_host_buffer, MSG_OP_MAP_HOST_BUFFER); - struct amdxdna_dev *xdna = ndev->xdna; + DECLARE_AIE_MSG(map_host_buffer, MSG_OP_MAP_HOST_BUFFER); + struct amdxdna_dev *xdna = ndev->aie.xdna; + size_t chunk_size; int ret; - req.context_id = context_id; - req.buf_addr = addr; - req.buf_size = size; - ret = aie2_send_mgmt_msg_wait(ndev, &msg); - if (ret) - return ret; + chunk_size = xdna->dev_info->dev_mem_size; + if (!size || !IS_ALIGNED(size, chunk_size)) { + XDNA_ERR(xdna, "Invalid size 0x%llx for chunk 0x%lx", + size, chunk_size); + return -EINVAL; + } - XDNA_DBG(xdna, "fw ctx %d map host buf addr 0x%llx size 0x%llx", - context_id, addr, size); + msg.opcode = initial_opcode; + do { + req.context_id = context_id; + req.buf_addr = addr; + req.buf_size = chunk_size; + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) { + XDNA_ERR(xdna, "fw ctx %d addr 0x%llx size 0x%lx", + context_id, addr, chunk_size); + return ret; + } + + XDNA_DBG(xdna, "fw ctx %d host buf op 0x%x addr 0x%llx size 0x%lx", + context_id, msg.opcode, addr, chunk_size); + + addr += chunk_size; + size -= chunk_size; + msg.opcode = MSG_OP_ADD_HOST_BUFFER; + } while (size); return 0; } +int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size) +{ + return aie2_send_host_buf_msgs(ndev, context_id, addr, size, + MSG_OP_MAP_HOST_BUFFER); +} + +int aie2_add_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size) +{ + if (!AIE_FEATURE_ON(&ndev->aie, AIE2_ADD_HOST_BUFFER)) + return -EOPNOTSUPP; + + return aie2_send_host_buf_msgs(ndev, context_id, addr, size, + MSG_OP_ADD_HOST_BUFFER); +} + static int amdxdna_hwctx_col_map(struct amdxdna_hwctx *hwctx, void *arg) { u32 *bitmap = arg; @@ -392,15 +366,16 @@ static int amdxdna_hwctx_col_map(struct amdxdna_hwctx *hwctx, void *arg) int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, u32 size, u32 *cols_filled) { - DECLARE_AIE2_MSG(aie_column_info, MSG_OP_QUERY_COL_STATUS); - struct amdxdna_dev *xdna = ndev->xdna; - u32 buf_sz = size, aie_bitmap = 0; + DECLARE_AIE_MSG(aie_column_info, MSG_OP_QUERY_COL_STATUS); + struct amdxdna_dev *xdna = ndev->aie.xdna; + u32 buf_sz, aie_bitmap = 0; struct amdxdna_client *client; dma_addr_t dma_addr; u8 *buff_addr; int ret; - buff_addr = aie2_alloc_msg_buffer(ndev, &buf_sz, &dma_addr); + buf_sz = ndev->aie.metadata.cols * ndev->aie.metadata.col_size; + buff_addr = amdxdna_alloc_msg_buffer(xdna, &buf_sz, &dma_addr); if (IS_ERR(buff_addr)) return PTR_ERR(buff_addr); @@ -414,8 +389,8 @@ int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, req.num_cols = hweight32(aie_bitmap); req.aie_bitmap = aie_bitmap; - drm_clflush_virt_range(buff_addr, size); /* device can access */ - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + drm_clflush_virt_range(buff_addr, req.dump_buff_size); /* device can access */ + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret) { XDNA_ERR(xdna, "Error during NPU query, status %d", ret); goto fail; @@ -423,13 +398,14 @@ int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, XDNA_DBG(xdna, "Query NPU status completed"); - if (size < resp.size) { + if (buf_sz < resp.size) { ret = -EINVAL; - XDNA_ERR(xdna, "Bad buffer size. Available: %u. Needs: %u", size, resp.size); + XDNA_ERR(xdna, "Bad buffer size. Available: %u. Needs: %u", buf_sz, resp.size); goto fail; } - if (copy_to_user(buf, buff_addr, resp.size)) { + size = min(size, resp.size); + if (copy_to_user(buf, buff_addr, size)) { ret = -EFAULT; XDNA_ERR(xdna, "Failed to copy NPU status to user space"); goto fail; @@ -438,7 +414,7 @@ int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, *cols_filled = aie_bitmap; fail: - aie2_free_msg_buffer(ndev, buf_sz, buff_addr, dma_addr); + amdxdna_free_msg_buffer(xdna, buf_sz, buff_addr, dma_addr); return ret; } @@ -446,17 +422,18 @@ int aie2_query_telemetry(struct amdxdna_dev_hdl *ndev, char __user *buf, u32 size, struct amdxdna_drm_query_telemetry_header *header) { - DECLARE_AIE2_MSG(get_telemetry, MSG_OP_GET_TELEMETRY); - struct amdxdna_dev *xdna = ndev->xdna; + DECLARE_AIE_MSG(get_telemetry, MSG_OP_GET_TELEMETRY); + struct amdxdna_dev *xdna = ndev->aie.xdna; dma_addr_t dma_addr; - u32 buf_sz = size; + u32 buf_sz; u8 *addr; int ret; if (header->type >= MAX_TELEMETRY_TYPE) return -EINVAL; - addr = aie2_alloc_msg_buffer(ndev, &buf_sz, &dma_addr); + buf_sz = min(size, SZ_4M); + addr = amdxdna_alloc_msg_buffer(xdna, &buf_sz, &dma_addr); if (IS_ERR(addr)) return PTR_ERR(addr); @@ -464,20 +441,21 @@ int aie2_query_telemetry(struct amdxdna_dev_hdl *ndev, req.buf_size = buf_sz; req.type = header->type; - drm_clflush_virt_range(addr, size); /* device can access */ - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + drm_clflush_virt_range(addr, req.buf_size); /* device can access */ + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret) { XDNA_ERR(xdna, "Query telemetry failed, status %d", ret); goto free_buf; } - if (size < resp.size) { + if (buf_sz < resp.size) { ret = -EINVAL; - XDNA_ERR(xdna, "Bad buffer size. Available: %u. Needs: %u", size, resp.size); + XDNA_ERR(xdna, "Bad buffer size. Available: %u. Needs: %u", buf_sz, resp.size); goto free_buf; } - if (copy_to_user(buf, addr, resp.size)) { + size = min(size, resp.size); + if (copy_to_user(buf, addr, size)) { ret = -EFAULT; XDNA_ERR(xdna, "Failed to copy telemetry to user space"); goto free_buf; @@ -487,7 +465,7 @@ int aie2_query_telemetry(struct amdxdna_dev_hdl *ndev, header->minor = resp.minor; free_buf: - aie2_free_msg_buffer(ndev, buf_sz, addr, dma_addr); + amdxdna_free_msg_buffer(xdna, buf_sz, addr, dma_addr); return ret; } @@ -506,8 +484,8 @@ int aie2_register_asyn_event_msg(struct amdxdna_dev_hdl *ndev, dma_addr_t addr, req.buf_addr = addr; req.buf_size = size; - XDNA_DBG(ndev->xdna, "Register addr 0x%llx size 0x%x", addr, size); - return xdna_mailbox_send_msg(ndev->mgmt_chann, &msg, TX_TIMEOUT); + XDNA_DBG(ndev->aie.xdna, "Register addr 0x%llx size 0x%x", addr, size); + return xdna_mailbox_send_msg(ndev->aie.mgmt_chann, &msg, TX_TIMEOUT); } int aie2_config_cu(struct amdxdna_hwctx *hwctx, @@ -866,7 +844,6 @@ static int aie2_init_exec_req(void *req, struct amdxdna_gem_obj *cmd_abo, int ret; u32 op; - op = amdxdna_cmd_get_op(cmd_abo); switch (op) { case ERT_START_CU: @@ -915,12 +892,12 @@ aie2_cmdlist_fill_slot(void *slot, struct amdxdna_gem_obj *cmd_abo, ret = EXEC_MSG_OPS(xdna)->fill_dpu_slot(cmd_abo, slot, size); break; case ERT_START_NPU_PREEMPT: - if (!AIE2_FEATURE_ON(xdna->dev_handle, AIE2_PREEMPT)) + if (!AIE_FEATURE_ON(&xdna->dev_handle->aie, AIE2_PREEMPT)) return -EOPNOTSUPP; ret = EXEC_MSG_OPS(xdna)->fill_preempt_slot(cmd_abo, slot, size); break; case ERT_START_NPU_PREEMPT_ELF: - if (!AIE2_FEATURE_ON(xdna->dev_handle, AIE2_PREEMPT)) + if (!AIE_FEATURE_ON(&xdna->dev_handle->aie, AIE2_PREEMPT)) return -EOPNOTSUPP; ret = EXEC_MSG_OPS(xdna)->fill_elf_slot(cmd_abo, slot, size); break; @@ -935,26 +912,12 @@ aie2_cmdlist_fill_slot(void *slot, struct amdxdna_gem_obj *cmd_abo, void aie2_msg_init(struct amdxdna_dev_hdl *ndev) { - if (AIE2_FEATURE_ON(ndev, AIE2_NPU_COMMAND)) + if (AIE_FEATURE_ON(&ndev->aie, AIE2_NPU_COMMAND)) ndev->exec_msg_ops = &npu_exec_message_ops; else ndev->exec_msg_ops = &legacy_exec_message_ops; } -void aie2_destroy_mgmt_chann(struct amdxdna_dev_hdl *ndev) -{ - struct amdxdna_dev *xdna = ndev->xdna; - - drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); - - if (!ndev->mgmt_chann) - return; - - xdna_mailbox_stop_channel(ndev->mgmt_chann); - xdna_mailbox_free_channel(ndev->mgmt_chann); - ndev->mgmt_chann = NULL; -} - static inline struct amdxdna_gem_obj * aie2_cmdlist_get_cmd_buf(struct amdxdna_sched_job *job) { @@ -1199,20 +1162,20 @@ int aie2_config_debug_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job * int aie2_query_app_health(struct amdxdna_dev_hdl *ndev, u32 context_id, struct app_health_report *report) { - DECLARE_AIE2_MSG(get_app_health, MSG_OP_GET_APP_HEALTH); - struct amdxdna_dev *xdna = ndev->xdna; + DECLARE_AIE_MSG(get_app_health, MSG_OP_GET_APP_HEALTH); + struct amdxdna_dev *xdna = ndev->aie.xdna; struct app_health_report *buf; dma_addr_t dma_addr; u32 buf_size; int ret; - if (!AIE2_FEATURE_ON(ndev, AIE2_APP_HEALTH)) { + if (!AIE_FEATURE_ON(&ndev->aie, AIE2_APP_HEALTH)) { XDNA_DBG(xdna, "App health feature not supported"); return -EOPNOTSUPP; } buf_size = sizeof(*report); - buf = aie2_alloc_msg_buffer(ndev, &buf_size, &dma_addr); + buf = amdxdna_alloc_msg_buffer(xdna, &buf_size, &dma_addr); if (IS_ERR(buf)) { XDNA_ERR(xdna, "Failed to allocate buffer for app health"); return PTR_ERR(buf); @@ -1222,8 +1185,8 @@ int aie2_query_app_health(struct amdxdna_dev_hdl *ndev, u32 context_id, req.context_id = context_id; req.buf_size = buf_size; - drm_clflush_virt_range(buf, sizeof(*report)); - ret = aie2_send_mgmt_msg_wait(ndev, &msg); + drm_clflush_virt_range(buf, req.buf_size); + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); if (ret) { XDNA_ERR(xdna, "Get app health failed, ret %d status 0x%x", ret, resp.status); goto free_buf; @@ -1233,6 +1196,75 @@ int aie2_query_app_health(struct amdxdna_dev_hdl *ndev, u32 context_id, memcpy(report, buf, sizeof(*report)); free_buf: - aie2_free_msg_buffer(ndev, buf_size, buf, dma_addr); + amdxdna_free_msg_buffer(xdna, buf_size, buf, dma_addr); return ret; } + +static int +aie2_runtime_update_ctx_prop(struct amdxdna_dev_hdl *ndev, + struct amdxdna_hwctx *ctx, u32 type, u32 value) +{ + DECLARE_AIE_MSG(update_property, MSG_OP_UPDATE_PROPERTY); + struct amdxdna_dev *xdna = ndev->aie.xdna; + int ret; + + if (!AIE_FEATURE_ON(&ndev->aie, AIE2_UPDATE_PROPERTY)) + return -EOPNOTSUPP; + + if (ctx) + req.context_id = ctx->fw_ctx_id; + else + req.context_id = AIE2_UPDATE_PROPERTY_ALL_CTX; + + req.time_quota_us = value; + req.type = type; + + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) { + XDNA_ERR(xdna, "%s update property failed, type %d ret %d", + ctx ? ctx->name : "ctx.all", type, ret); + return ret; + } + + return 0; +} + +int aie2_update_prop_time_quota(struct amdxdna_dev_hdl *ndev, u32 us) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + int ret; + + ret = aie2_runtime_update_ctx_prop(ndev, NULL, UPDATE_PROPERTY_TIME_QUOTA, us); + if (ret == -EOPNOTSUPP) { + XDNA_DBG(xdna, "update time quota not support, skipped"); + ret = 0; + } else if (!ret) { + XDNA_DBG(xdna, "Ctx exec time quantum updated to %u us", us); + } + return ret; +} + +int aie2_get_dev_revision(struct amdxdna_dev_hdl *ndev, enum aie2_dev_revision *rev) +{ + DECLARE_AIE_MSG(get_dev_revision, MSG_OP_GET_DEV_REVISION); + struct amdxdna_dev *xdna = ndev->aie.xdna; + int ret; + + if (!AIE_FEATURE_ON(&ndev->aie, AIE2_GET_DEV_REVISION)) + return -EOPNOTSUPP; + + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) + return ret; + + *rev = resp.rev; + + if (*rev < AIE2_DEV_REVISION_STXA || *rev >= AIE2_DEV_REVISION_UNKN) { + XDNA_ERR(xdna, "Unknown device revision: %d (raw fuse: 0x%x)", + *rev, resp.raw_fuse_data); + return -EINVAL; + } + + XDNA_DBG(xdna, "Device revision: %d (raw fuse: 0x%x)", *rev, resp.raw_fuse_data); + return 0; +} diff --git a/drivers/accel/amdxdna/aie2_msg_priv.h b/drivers/accel/amdxdna/aie2_msg_priv.h index f18e89a39e35..fd65a4236d49 100644 --- a/drivers/accel/amdxdna/aie2_msg_priv.h +++ b/drivers/accel/amdxdna/aie2_msg_priv.h @@ -31,7 +31,10 @@ enum aie2_msg_opcode { MSG_OP_SET_RUNTIME_CONFIG = 0x10A, MSG_OP_GET_RUNTIME_CONFIG = 0x10B, MSG_OP_REGISTER_ASYNC_EVENT_MSG = 0x10C, + MSG_OP_UPDATE_PROPERTY = 0x113, MSG_OP_GET_APP_HEALTH = 0x114, + MSG_OP_ADD_HOST_BUFFER = 0x115, + MSG_OP_GET_DEV_REVISION = 0x117, MSG_OP_MAX_DRV_OPCODE, MSG_OP_GET_PROTOCOL_VERSION = 0x301, MSG_OP_MAX_OPCODE @@ -460,7 +463,7 @@ struct fatal_error_info { __u32 exception_pc; /* Program Counter at the time of the exception */ __u32 app_module; /* Error module name */ __u32 task_index; /* Index of the task in which the error occurred */ - __u32 reserved[128]; + __u32 reserved[127]; }; struct app_health_report { @@ -503,4 +506,41 @@ struct get_app_health_resp { __u32 required_buffer_size; __u32 reserved[7]; } __packed; + +struct update_property_req { +#define UPDATE_PROPERTY_TIME_QUOTA 0 + __u32 type; +#define AIE2_UPDATE_PROPERTY_ALL_CTX 0xFF + __u8 context_id; + __u8 reserved[7]; + __u32 time_quota_us; + __u32 reserved1; +} __packed; + +struct update_property_resp { + enum aie2_msg_status status; +} __packed; + +enum aie2_dev_revision { + AIE2_DEV_REVISION_STXA = 1, + AIE2_DEV_REVISION_STXB, + AIE2_DEV_REVISION_KRK1, + AIE2_DEV_REVISION_KRK2, + AIE2_DEV_REVISION_HALO, + AIE2_DEV_REVISION_GPT1, + AIE2_DEV_REVISION_GPT2, + AIE2_DEV_REVISION_GPT3, + AIE2_DEV_REVISION_UNKN, +}; + +struct get_dev_revision_req { + __u32 place_holder; +} __packed; + +struct get_dev_revision_resp { + enum aie2_msg_status status; + enum aie2_dev_revision rev; + __u32 raw_fuse_data; +} __packed; + #endif /* _AIE2_MSG_PRIV_H_ */ diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c index f1ac4e00bd9f..c4d345d4c76b 100644 --- a/drivers/accel/amdxdna/aie2_pci.c +++ b/drivers/accel/amdxdna/aie2_pci.c @@ -33,6 +33,8 @@ static int aie2_max_col = XRS_MAX_COL; module_param(aie2_max_col, uint, 0600); MODULE_PARM_DESC(aie2_max_col, "Maximum column could be used"); +#define DEFAULT_TIME_QUANTUM 30000 /* microseconds */ + static char *npu_fw[] = { "npu_7.sbin", "npu.sbin" @@ -60,45 +62,6 @@ struct mgmt_mbox_chann_info { __u32 rsvd[4]; }; -static int aie2_check_protocol(struct amdxdna_dev_hdl *ndev, u32 fw_major, u32 fw_minor) -{ - const struct aie2_fw_feature_tbl *feature; - bool found = false; - - for (feature = ndev->priv->fw_feature_tbl; feature->major; feature++) { - if (feature->major != fw_major) - continue; - if (fw_minor < feature->min_minor) - continue; - if (feature->max_minor > 0 && fw_minor > feature->max_minor) - continue; - - ndev->feature_mask |= feature->features; - - /* firmware version matches one of the driver support entry */ - found = true; - } - - return found ? 0 : -EOPNOTSUPP; -} - -static void aie2_dump_chann_info_debug(struct amdxdna_dev_hdl *ndev) -{ - struct amdxdna_dev *xdna = ndev->xdna; - - XDNA_DBG(xdna, "i2x tail 0x%x", ndev->mgmt_i2x.mb_tail_ptr_reg); - XDNA_DBG(xdna, "i2x head 0x%x", ndev->mgmt_i2x.mb_head_ptr_reg); - XDNA_DBG(xdna, "i2x ringbuf 0x%x", ndev->mgmt_i2x.rb_start_addr); - XDNA_DBG(xdna, "i2x rsize 0x%x", ndev->mgmt_i2x.rb_size); - XDNA_DBG(xdna, "x2i tail 0x%x", ndev->mgmt_x2i.mb_tail_ptr_reg); - XDNA_DBG(xdna, "x2i head 0x%x", ndev->mgmt_x2i.mb_head_ptr_reg); - XDNA_DBG(xdna, "x2i ringbuf 0x%x", ndev->mgmt_x2i.rb_start_addr); - XDNA_DBG(xdna, "x2i rsize 0x%x", ndev->mgmt_x2i.rb_size); - XDNA_DBG(xdna, "x2i chann index 0x%x", ndev->mgmt_chan_idx); - XDNA_DBG(xdna, "mailbox protocol major 0x%x", ndev->mgmt_prot_major); - XDNA_DBG(xdna, "mailbox protocol minor 0x%x", ndev->mgmt_prot_minor); -} - static int aie2_get_mgmt_chann_info(struct amdxdna_dev_hdl *ndev) { struct mgmt_mbox_chann_info info_regs; @@ -118,7 +81,7 @@ static int aie2_get_mgmt_chann_info(struct amdxdna_dev_hdl *ndev) * is alive. */ ret = readx_poll_timeout(readl, SRAM_GET_ADDR(ndev, FW_ALIVE_OFF), - addr, addr, AIE2_INTERVAL, AIE2_TIMEOUT); + addr, addr, AIE_INTERVAL, AIE_TIMEOUT); if (ret || !addr) return -ETIME; @@ -128,13 +91,13 @@ static int aie2_get_mgmt_chann_info(struct amdxdna_dev_hdl *ndev) reg[i] = readl(ndev->sram_base + off + i * sizeof(u32)); if (info_regs.magic != MGMT_MBOX_MAGIC) { - XDNA_ERR(ndev->xdna, "Invalid mbox magic 0x%x", info_regs.magic); + XDNA_ERR(ndev->aie.xdna, "Invalid mbox magic 0x%x", info_regs.magic); ret = -EINVAL; goto done; } - i2x = &ndev->mgmt_i2x; - x2i = &ndev->mgmt_x2i; + i2x = &ndev->aie.mgmt_i2x; + x2i = &ndev->aie.mgmt_x2i; i2x->mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, info_regs.i2x_head); i2x->mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, info_regs.i2x_tail); @@ -146,14 +109,15 @@ static int aie2_get_mgmt_chann_info(struct amdxdna_dev_hdl *ndev) x2i->rb_start_addr = AIE2_SRAM_OFF(ndev, info_regs.x2i_buf); x2i->rb_size = info_regs.x2i_buf_sz; - ndev->mgmt_chan_idx = info_regs.msi_id; - ndev->mgmt_prot_major = info_regs.prot_major; - ndev->mgmt_prot_minor = info_regs.prot_minor; + ndev->aie.mgmt_chan_idx = info_regs.msi_id; + ndev->aie.mgmt_prot_major = info_regs.prot_major; + ndev->aie.mgmt_prot_minor = info_regs.prot_minor; - ret = aie2_check_protocol(ndev, ndev->mgmt_prot_major, ndev->mgmt_prot_minor); + ret = aie_check_protocol(&ndev->aie, ndev->aie.mgmt_prot_major, + ndev->aie.mgmt_prot_minor); done: - aie2_dump_chann_info_debug(ndev); + aie_dump_mgmt_chann_debug(&ndev->aie); /* Must clear address at FW_ALIVE_OFF */ writel(0, SRAM_GET_ADDR(ndev, FW_ALIVE_OFF)); @@ -173,13 +137,14 @@ int aie2_runtime_cfg(struct amdxdna_dev_hdl *ndev, continue; if (cfg->feature_mask && - bitmap_subset(&cfg->feature_mask, &ndev->feature_mask, AIE2_FEATURE_MAX)) + bitmap_subset(&cfg->feature_mask, &ndev->aie.feature_mask, + AIE2_FEATURE_MAX)) continue; value = val ? *val : cfg->value; ret = aie2_set_runtime_cfg(ndev, cfg->type, value); if (ret) { - XDNA_ERR(ndev->xdna, "Set type %d value %d failed", + XDNA_ERR(ndev->aie.xdna, "Set type %d value %d failed", cfg->type, value); return ret; } @@ -194,13 +159,13 @@ static int aie2_xdna_reset(struct amdxdna_dev_hdl *ndev) ret = aie2_suspend_fw(ndev); if (ret) { - XDNA_ERR(ndev->xdna, "Suspend firmware failed"); + XDNA_ERR(ndev->aie.xdna, "Suspend firmware failed"); return ret; } ret = aie2_resume_fw(ndev); if (ret) { - XDNA_ERR(ndev->xdna, "Resume firmware failed"); + XDNA_ERR(ndev->aie.xdna, "Resume firmware failed"); return ret; } @@ -213,19 +178,25 @@ static int aie2_mgmt_fw_init(struct amdxdna_dev_hdl *ndev) ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_INIT, NULL); if (ret) { - XDNA_ERR(ndev->xdna, "Runtime config failed"); + XDNA_ERR(ndev->aie.xdna, "Runtime config failed"); return ret; } ret = aie2_assign_mgmt_pasid(ndev, 0); if (ret) { - XDNA_ERR(ndev->xdna, "Can not assign PASID"); + XDNA_ERR(ndev->aie.xdna, "Can not assign PASID"); + return ret; + } + + ret = aie2_update_prop_time_quota(ndev, DEFAULT_TIME_QUANTUM); + if (ret) { + XDNA_ERR(ndev->aie.xdna, "Failed to update execution time quantum"); return ret; } ret = aie2_xdna_reset(ndev); if (ret) { - XDNA_ERR(ndev->xdna, "Reset firmware failed"); + XDNA_ERR(ndev->aie.xdna, "Reset firmware failed"); return ret; } @@ -236,25 +207,25 @@ static int aie2_mgmt_fw_query(struct amdxdna_dev_hdl *ndev) { int ret; - ret = aie2_query_firmware_version(ndev, &ndev->xdna->fw_ver); + ret = aie2_query_firmware_version(ndev, &ndev->aie.xdna->fw_ver); if (ret) { - XDNA_ERR(ndev->xdna, "query firmware version failed"); + XDNA_ERR(ndev->aie.xdna, "query firmware version failed"); return ret; } ret = aie2_query_aie_version(ndev, &ndev->version); if (ret) { - XDNA_ERR(ndev->xdna, "Query AIE version failed"); + XDNA_ERR(ndev->aie.xdna, "Query AIE version failed"); return ret; } - ret = aie2_query_aie_metadata(ndev, &ndev->metadata); + ret = aie2_query_aie_metadata(ndev, &ndev->aie.metadata); if (ret) { - XDNA_ERR(ndev->xdna, "Query AIE metadata failed"); + XDNA_ERR(ndev->aie.xdna, "Query AIE metadata failed"); return ret; } - ndev->total_col = min(aie2_max_col, ndev->metadata.cols); + ndev->total_col = min(aie2_max_col, ndev->aie.metadata.cols); return 0; } @@ -262,8 +233,8 @@ static int aie2_mgmt_fw_query(struct amdxdna_dev_hdl *ndev) static void aie2_mgmt_fw_fini(struct amdxdna_dev_hdl *ndev) { if (aie2_suspend_fw(ndev)) - XDNA_ERR(ndev->xdna, "Suspend_fw failed"); - XDNA_DBG(ndev->xdna, "Firmware suspended"); + XDNA_ERR(ndev->aie.xdna, "Suspend_fw failed"); + XDNA_DBG(ndev->aie.xdna, "Firmware suspended"); } static int aie2_xrs_load(void *cb_arg, struct xrs_action_load *action) @@ -275,6 +246,7 @@ static int aie2_xrs_load(void *cb_arg, struct xrs_action_load *action) xdna = hwctx->client->xdna; hwctx->start_col = action->part.start_col; + hwctx->num_unused_col = action->part.ncols - hwctx->num_col; hwctx->num_col = action->part.ncols; ret = aie2_create_context(xdna->dev_handle, hwctx); if (ret) @@ -319,6 +291,12 @@ static struct xrs_action_ops aie2_xrs_actions = { .set_dft_dpm_level = aie2_xrs_set_dft_dpm_level, }; +static void aie2_smu_fini(struct amdxdna_dev_hdl *ndev) +{ + ndev->priv->hw_ops->set_dpm(ndev, 0); + aie_smu_fini(ndev->aie.smu_hdl); +} + static void aie2_hw_stop(struct amdxdna_dev *xdna) { struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev); @@ -331,10 +309,10 @@ static void aie2_hw_stop(struct amdxdna_dev *xdna) aie2_runtime_cfg(ndev, AIE2_RT_CFG_CLK_GATING, NULL); aie2_mgmt_fw_fini(ndev); - aie2_destroy_mgmt_chann(ndev); + aie_destroy_chann(&ndev->aie, &ndev->aie.mgmt_chann); drmm_kfree(&xdna->ddev, ndev->mbox); ndev->mbox = NULL; - aie2_psp_stop(ndev->psp_hdl); + aie_psp_stop(ndev->aie.psp_hdl); aie2_smu_fini(ndev); aie2_error_async_events_free(ndev); pci_disable_device(pdev); @@ -374,20 +352,20 @@ static int aie2_hw_start(struct amdxdna_dev *xdna) goto disable_dev; } - ndev->mgmt_chann = xdna_mailbox_alloc_channel(ndev->mbox); - if (!ndev->mgmt_chann) { + ndev->aie.mgmt_chann = xdna_mailbox_alloc_channel(ndev->mbox); + if (!ndev->aie.mgmt_chann) { XDNA_ERR(xdna, "failed to alloc channel"); ret = -ENODEV; goto disable_dev; } - ret = aie2_smu_init(ndev); + ret = aie_smu_init(ndev->aie.smu_hdl); if (ret) { XDNA_ERR(xdna, "failed to init smu, ret %d", ret); goto free_channel; } - ret = aie2_psp_start(ndev->psp_hdl); + ret = aie_psp_start(ndev->aie.psp_hdl); if (ret) { XDNA_ERR(xdna, "failed to start psp, ret %d", ret); goto fini_smu; @@ -399,17 +377,17 @@ static int aie2_hw_start(struct amdxdna_dev *xdna) goto stop_psp; } - mgmt_mb_irq = pci_irq_vector(pdev, ndev->mgmt_chan_idx); + mgmt_mb_irq = pci_irq_vector(pdev, ndev->aie.mgmt_chan_idx); if (mgmt_mb_irq < 0) { ret = mgmt_mb_irq; XDNA_ERR(xdna, "failed to alloc irq vector, ret %d", ret); goto stop_psp; } - xdna_mailbox_intr_reg = ndev->mgmt_i2x.mb_head_ptr_reg + 4; - ret = xdna_mailbox_start_channel(ndev->mgmt_chann, - &ndev->mgmt_x2i, - &ndev->mgmt_i2x, + xdna_mailbox_intr_reg = ndev->aie.mgmt_i2x.mb_head_ptr_reg + 4; + ret = xdna_mailbox_start_channel(ndev->aie.mgmt_chann, + &ndev->aie.mgmt_x2i, + &ndev->aie.mgmt_i2x, xdna_mailbox_intr_reg, mgmt_mb_irq); if (ret) { @@ -448,14 +426,14 @@ static int aie2_hw_start(struct amdxdna_dev *xdna) stop_fw: aie2_suspend_fw(ndev); - xdna_mailbox_stop_channel(ndev->mgmt_chann); + xdna_mailbox_stop_channel(ndev->aie.mgmt_chann); stop_psp: - aie2_psp_stop(ndev->psp_hdl); + aie_psp_stop(ndev->aie.psp_hdl); fini_smu: aie2_smu_fini(ndev); free_channel: - xdna_mailbox_free_channel(ndev->mgmt_chann); - ndev->mgmt_chann = NULL; + xdna_mailbox_free_channel(ndev->aie.mgmt_chann); + ndev->aie.mgmt_chann = NULL; disable_dev: pci_disable_device(pdev); @@ -500,7 +478,8 @@ static int aie2_init(struct amdxdna_dev *xdna) void __iomem *tbl[PCI_NUM_RESOURCES] = {0}; struct init_config xrs_cfg = { 0 }; struct amdxdna_dev_hdl *ndev; - struct psp_config psp_conf; + struct psp_config psp_conf = { 0 }; + struct smu_config smu_conf; const struct firmware *fw; unsigned long bars = 0; char *fw_full_path; @@ -516,7 +495,7 @@ static int aie2_init(struct amdxdna_dev *xdna) return -ENOMEM; ndev->priv = xdna->dev_info->dev_priv; - ndev->xdna = xdna; + ndev->aie.xdna = xdna; for (i = 0; i < ARRAY_SIZE(npu_fw); i++) { fw_full_path = kasprintf(GFP_KERNEL, "%s%s", ndev->priv->fw_path, npu_fw[i]); @@ -545,9 +524,10 @@ static int aie2_init(struct amdxdna_dev *xdna) for (i = 0; i < PSP_MAX_REGS; i++) set_bit(PSP_REG_BAR(ndev, i), &bars); + for (i = 0; i < SMU_MAX_REGS; i++) + set_bit(SMU_REG_BAR(ndev, i), &bars); set_bit(xdna->dev_info->sram_bar, &bars); - set_bit(xdna->dev_info->smu_bar, &bars); set_bit(xdna->dev_info->mbox_bar, &bars); for (i = 0; i < PCI_NUM_RESOURCES; i++) { @@ -562,7 +542,6 @@ static int aie2_init(struct amdxdna_dev *xdna) } ndev->sram_base = tbl[xdna->dev_info->sram_bar]; - ndev->smu_base = tbl[xdna->dev_info->smu_bar]; ndev->mbox_base = tbl[xdna->dev_info->mbox_bar]; ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); @@ -586,14 +565,25 @@ static int aie2_init(struct amdxdna_dev *xdna) psp_conf.fw_size = fw->size; psp_conf.fw_buf = fw->data; + psp_conf.arg2_mask = GENMASK(23, 0); + psp_conf.notify_val = 1; for (i = 0; i < PSP_MAX_REGS; i++) psp_conf.psp_regs[i] = tbl[PSP_REG_BAR(ndev, i)] + PSP_REG_OFF(ndev, i); - ndev->psp_hdl = aie2m_psp_create(&xdna->ddev, &psp_conf); - if (!ndev->psp_hdl) { + ndev->aie.psp_hdl = aiem_psp_create(&xdna->ddev, &psp_conf); + if (!ndev->aie.psp_hdl) { XDNA_ERR(xdna, "failed to create psp"); ret = -ENOMEM; goto release_fw; } + + for (i = 0; i < SMU_MAX_REGS; i++) + smu_conf.smu_regs[i] = tbl[SMU_REG_BAR(ndev, i)] + SMU_REG_OFF(ndev, i); + ndev->aie.smu_hdl = aiem_smu_create(&xdna->ddev, &smu_conf); + if (!ndev->aie.smu_hdl) { + XDNA_ERR(xdna, "failed to create smu"); + ret = -ENOMEM; + goto release_fw; + } xdna->dev_handle = ndev; ret = aie2_hw_start(xdna); @@ -605,7 +595,7 @@ static int aie2_init(struct amdxdna_dev *xdna) xrs_cfg.clk_list.num_levels = ndev->max_dpm_level + 1; for (i = 0; i < xrs_cfg.clk_list.num_levels; i++) xrs_cfg.clk_list.cu_clk_list[i] = ndev->priv->dpm_clk_tbl[i].hclk; - xrs_cfg.sys_eff_factor = 1; + xrs_cfg.sys_eff_factor = 2; xrs_cfg.ddev = &xdna->ddev; xrs_cfg.actions = &aie2_xrs_actions; xrs_cfg.total_col = ndev->total_col; @@ -619,6 +609,7 @@ static int aie2_init(struct amdxdna_dev *xdna) release_firmware(fw); aie2_msg_init(ndev); + amdxdna_vbnv_init(xdna); amdxdna_pm_init(xdna); return 0; @@ -639,23 +630,19 @@ static void aie2_fini(struct amdxdna_dev *xdna) static int aie2_get_aie_status(struct amdxdna_client *client, struct amdxdna_drm_get_info *args) { - struct amdxdna_drm_query_aie_status status; + struct amdxdna_drm_query_aie_status status = {}; struct amdxdna_dev *xdna = client->xdna; struct amdxdna_dev_hdl *ndev; + u32 buf_sz; int ret; ndev = xdna->dev_handle; - if (copy_from_user(&status, u64_to_user_ptr(args->buffer), sizeof(status))) { + buf_sz = min(args->buffer_size, sizeof(status)); + if (copy_from_user(&status, u64_to_user_ptr(args->buffer), buf_sz)) { XDNA_ERR(xdna, "Failed to copy AIE request into kernel"); return -EFAULT; } - if (ndev->metadata.cols * ndev->metadata.size < status.buffer_size) { - XDNA_ERR(xdna, "Invalid buffer size. Given Size: %u. Need Size: %u.", - status.buffer_size, ndev->metadata.cols * ndev->metadata.size); - return -EINVAL; - } - ret = aie2_query_status(ndev, u64_to_user_ptr(status.buffer), status.buffer_size, &status.cols_filled); if (ret) { @@ -663,7 +650,7 @@ static int aie2_get_aie_status(struct amdxdna_client *client, return ret; } - if (copy_to_user(u64_to_user_ptr(args->buffer), &status, sizeof(status))) { + if (copy_to_user(u64_to_user_ptr(args->buffer), &status, buf_sz)) { XDNA_ERR(xdna, "Failed to copy AIE request info to user space"); return -EFAULT; } @@ -671,63 +658,20 @@ static int aie2_get_aie_status(struct amdxdna_client *client, return 0; } -static int aie2_get_aie_metadata(struct amdxdna_client *client, - struct amdxdna_drm_get_info *args) -{ - struct amdxdna_drm_query_aie_metadata *meta; - struct amdxdna_dev *xdna = client->xdna; - struct amdxdna_dev_hdl *ndev; - int ret = 0; - - ndev = xdna->dev_handle; - meta = kzalloc_obj(*meta); - if (!meta) - return -ENOMEM; - - meta->col_size = ndev->metadata.size; - meta->cols = ndev->metadata.cols; - meta->rows = ndev->metadata.rows; - - meta->version.major = ndev->metadata.version.major; - meta->version.minor = ndev->metadata.version.minor; - - meta->core.row_count = ndev->metadata.core.row_count; - meta->core.row_start = ndev->metadata.core.row_start; - meta->core.dma_channel_count = ndev->metadata.core.dma_channel_count; - meta->core.lock_count = ndev->metadata.core.lock_count; - meta->core.event_reg_count = ndev->metadata.core.event_reg_count; - - meta->mem.row_count = ndev->metadata.mem.row_count; - meta->mem.row_start = ndev->metadata.mem.row_start; - meta->mem.dma_channel_count = ndev->metadata.mem.dma_channel_count; - meta->mem.lock_count = ndev->metadata.mem.lock_count; - meta->mem.event_reg_count = ndev->metadata.mem.event_reg_count; - - meta->shim.row_count = ndev->metadata.shim.row_count; - meta->shim.row_start = ndev->metadata.shim.row_start; - meta->shim.dma_channel_count = ndev->metadata.shim.dma_channel_count; - meta->shim.lock_count = ndev->metadata.shim.lock_count; - meta->shim.event_reg_count = ndev->metadata.shim.event_reg_count; - - if (copy_to_user(u64_to_user_ptr(args->buffer), meta, sizeof(*meta))) - ret = -EFAULT; - - kfree(meta); - return ret; -} - static int aie2_get_aie_version(struct amdxdna_client *client, struct amdxdna_drm_get_info *args) { struct amdxdna_drm_query_aie_version version; struct amdxdna_dev *xdna = client->xdna; struct amdxdna_dev_hdl *ndev; + u32 buf_sz; ndev = xdna->dev_handle; version.major = ndev->version.major; version.minor = ndev->version.minor; - if (copy_to_user(u64_to_user_ptr(args->buffer), &version, sizeof(version))) + buf_sz = min(args->buffer_size, sizeof(version)); + if (copy_to_user(u64_to_user_ptr(args->buffer), &version, buf_sz)) return -EFAULT; return 0; @@ -738,13 +682,15 @@ static int aie2_get_firmware_version(struct amdxdna_client *client, { struct amdxdna_drm_query_firmware_version version; struct amdxdna_dev *xdna = client->xdna; + u32 buf_sz; version.major = xdna->fw_ver.major; version.minor = xdna->fw_ver.minor; version.patch = xdna->fw_ver.sub; version.build = xdna->fw_ver.build; - if (copy_to_user(u64_to_user_ptr(args->buffer), &version, sizeof(version))) + buf_sz = min(args->buffer_size, sizeof(version)); + if (copy_to_user(u64_to_user_ptr(args->buffer), &version, buf_sz)) return -EFAULT; return 0; @@ -756,11 +702,13 @@ static int aie2_get_power_mode(struct amdxdna_client *client, struct amdxdna_drm_get_power_mode mode = {}; struct amdxdna_dev *xdna = client->xdna; struct amdxdna_dev_hdl *ndev; + u32 buf_sz; ndev = xdna->dev_handle; mode.power_mode = ndev->pw_mode; - if (copy_to_user(u64_to_user_ptr(args->buffer), &mode, sizeof(mode))) + buf_sz = min(args->buffer_size, sizeof(mode)); + if (copy_to_user(u64_to_user_ptr(args->buffer), &mode, buf_sz)) return -EFAULT; return 0; @@ -773,19 +721,22 @@ static int aie2_get_clock_metadata(struct amdxdna_client *client, struct amdxdna_dev *xdna = client->xdna; struct amdxdna_dev_hdl *ndev; int ret = 0; + u32 buf_sz; ndev = xdna->dev_handle; clock = kzalloc_obj(*clock); if (!clock) return -ENOMEM; + aie2_update_counters(ndev); snprintf(clock->mp_npu_clock.name, sizeof(clock->mp_npu_clock.name), "MP-NPU Clock"); clock->mp_npu_clock.freq_mhz = ndev->npuclk_freq; snprintf(clock->h_clock.name, sizeof(clock->h_clock.name), "H Clock"); clock->h_clock.freq_mhz = ndev->hclk_freq; - if (copy_to_user(u64_to_user_ptr(args->buffer), clock, sizeof(*clock))) + buf_sz = min(args->buffer_size, sizeof(*clock)); + if (copy_to_user(u64_to_user_ptr(args->buffer), clock, buf_sz)) ret = -EFAULT; kfree(clock); @@ -811,12 +762,14 @@ static int aie2_get_sensors(struct amdxdna_client *client, scnprintf(sensor.label, sizeof(sensor.label), "Total Power"); scnprintf(sensor.units, sizeof(sensor.units), "mW"); + if (args->buffer_size < sizeof(sensor)) + goto out; + if (copy_to_user(u64_to_user_ptr(args->buffer), &sensor, sizeof(sensor))) return -EFAULT; + args->buffer_size -= sizeof(sensor); sensors_count++; - if (args->buffer_size <= sensors_count * sizeof(sensor)) - goto out; for (i = 0; i < min_t(u32, ndev->total_col, 8); i++) { memset(&sensor, 0, sizeof(sensor)); @@ -826,13 +779,15 @@ static int aie2_get_sensors(struct amdxdna_client *client, scnprintf(sensor.label, sizeof(sensor.label), "Column %d Utilization", i); scnprintf(sensor.units, sizeof(sensor.units), "%%"); + if (args->buffer_size < sizeof(sensor)) + goto out; + if (copy_to_user(u64_to_user_ptr(args->buffer) + sensors_count * sizeof(sensor), &sensor, sizeof(sensor))) return -EFAULT; + args->buffer_size -= sizeof(sensor); sensors_count++; - if (args->buffer_size <= sensors_count * sizeof(sensor)) - goto out; } out: @@ -928,18 +883,21 @@ static int aie2_query_resource_info(struct amdxdna_client *client, const struct amdxdna_dev_priv *priv; struct amdxdna_dev_hdl *ndev; struct amdxdna_dev *xdna; + u32 buf_sz; xdna = client->xdna; ndev = xdna->dev_handle; priv = ndev->priv; + aie2_update_counters(ndev); res_info.npu_clk_max = priv->dpm_clk_tbl[ndev->max_dpm_level].hclk; res_info.npu_tops_max = ndev->max_tops; res_info.npu_task_max = priv->hwctx_limit; res_info.npu_tops_curr = ndev->curr_tops; res_info.npu_task_curr = ndev->hwctx_num; - if (copy_to_user(u64_to_user_ptr(args->buffer), &res_info, sizeof(res_info))) + buf_sz = min(args->buffer_size, sizeof(res_info)); + if (copy_to_user(u64_to_user_ptr(args->buffer), &res_info, buf_sz)) return -EFAULT; return 0; @@ -975,12 +933,7 @@ static int aie2_get_telemetry(struct amdxdna_client *client, XDNA_ERR(xdna, "Invalid buffer size"); return -EINVAL; } - telemetry_data_sz = args->buffer_size - header_sz; - if (telemetry_data_sz > SZ_4M) { - XDNA_ERR(xdna, "Buffer size is too big, %d", telemetry_data_sz); - return -EINVAL; - } header = kzalloc(header_sz, GFP_KERNEL); if (!header) @@ -1021,6 +974,7 @@ static int aie2_get_preempt_state(struct amdxdna_client *client, struct amdxdna_drm_attribute_state state = {}; struct amdxdna_dev *xdna = client->xdna; struct amdxdna_dev_hdl *ndev; + u32 buf_sz; ndev = xdna->dev_handle; if (args->param == DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE) @@ -1028,7 +982,8 @@ static int aie2_get_preempt_state(struct amdxdna_client *client, else if (args->param == DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE) state.state = ndev->frame_boundary_preempt; - if (copy_to_user(u64_to_user_ptr(args->buffer), &state, sizeof(state))) + buf_sz = min(args->buffer_size, sizeof(state)); + if (copy_to_user(u64_to_user_ptr(args->buffer), &state, buf_sz)) return -EFAULT; return 0; @@ -1037,6 +992,7 @@ static int aie2_get_preempt_state(struct amdxdna_client *client, static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args) { struct amdxdna_dev *xdna = client->xdna; + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; int ret, idx; if (!drm_dev_enter(&xdna->ddev, &idx)) @@ -1051,7 +1007,7 @@ static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i ret = aie2_get_aie_status(client, args); break; case DRM_AMDXDNA_QUERY_AIE_METADATA: - ret = aie2_get_aie_metadata(client, args); + ret = amdxdna_get_metadata(&ndev->aie, client, args); break; case DRM_AMDXDNA_QUERY_AIE_VERSION: ret = aie2_get_aie_version(client, args); @@ -1255,6 +1211,21 @@ static int aie2_set_state(struct amdxdna_client *client, return ret; } +static int aie2_get_dev_rev(struct amdxdna_dev *xdna, u32 *rev) +{ + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; + enum aie2_dev_revision aie2_rev; + int ret; + + drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); + ret = aie2_get_dev_revision(ndev, &aie2_rev); + + if (!ret) + *rev = (u32)aie2_rev; + + return ret; +} + const struct amdxdna_dev_ops aie2_ops = { .init = aie2_init, .fini = aie2_fini, @@ -1269,4 +1240,6 @@ const struct amdxdna_dev_ops aie2_ops = { .cmd_submit = aie2_cmd_submit, .hmm_invalidate = aie2_hmm_invalidate, .get_array = aie2_get_array, + .get_dev_revision = aie2_get_dev_rev, + .hwctx_heap_expand = aie2_hwctx_heap_expand, }; diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h index efcf4be035f0..77648cc548b6 100644 --- a/drivers/accel/amdxdna/aie2_pci.h +++ b/drivers/accel/amdxdna/aie2_pci.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2023-2024, Advanced Micro Devices, Inc. + * Copyright (C) 2023-2026, Advanced Micro Devices, Inc. */ #ifndef _AIE2_PCI_H_ @@ -10,30 +10,22 @@ #include #include +#include "aie.h" #include "aie2_msg_priv.h" #include "amdxdna_mailbox.h" -#define AIE2_INTERVAL 20000 /* us */ -#define AIE2_TIMEOUT 1000000 /* us */ - /* Firmware determines device memory base address and size */ -#define AIE2_DEVM_BASE 0x4000000 -#define AIE2_DEVM_SIZE SZ_64M +#define AIE2_DEVM_BASE 0x4000000 +#define AIE2_DEVM_SIZE SZ_64M +#define AIE2_DEVM_MAX_SIZE SZ_512M -#define NDEV2PDEV(ndev) (to_pci_dev((ndev)->xdna->ddev.dev)) +#define NDEV2PDEV(ndev) (to_pci_dev((ndev)->aie.xdna->ddev.dev)) #define AIE2_SRAM_OFF(ndev, addr) ((addr) - (ndev)->priv->sram_dev_addr) #define AIE2_MBOX_OFF(ndev, addr) ((addr) - (ndev)->priv->mbox_dev_addr) -#define PSP_REG_BAR(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].bar_idx) -#define PSP_REG_OFF(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].offset) #define SRAM_REG_OFF(ndev, idx) ((ndev)->priv->sram_offs[(idx)].offset) -#define SMU_REG(ndev, idx) \ -({ \ - typeof(ndev) _ndev = ndev; \ - ((_ndev)->smu_base + (_ndev)->priv->smu_regs_off[(idx)].offset); \ -}) #define SRAM_GET_ADDR(ndev, idx) \ ({ \ typeof(ndev) _ndev = ndev; \ @@ -45,7 +37,7 @@ ({ \ typeof(ndev) _ndev = (ndev); \ ((_ndev)->priv->mbox_size) ? (_ndev)->priv->mbox_size : \ - pci_resource_len(NDEV2PDEV(_ndev), (_ndev)->xdna->dev_info->mbox_bar); \ + pci_resource_len(NDEV2PDEV(_ndev), (_ndev)->aie.xdna->dev_info->mbox_bar); \ }) #if IS_ENABLED(CONFIG_AMD_PMF) @@ -75,68 +67,17 @@ }) #endif -enum aie2_smu_reg_idx { - SMU_CMD_REG = 0, - SMU_ARG_REG, - SMU_INTR_REG, - SMU_RESP_REG, - SMU_OUT_REG, - SMU_MAX_REGS /* Keep this at the end */ -}; - enum aie2_sram_reg_idx { MBOX_CHANN_OFF = 0, FW_ALIVE_OFF, SRAM_MAX_INDEX /* Keep this at the end */ }; -enum psp_reg_idx { - PSP_CMD_REG = 0, - PSP_ARG0_REG, - PSP_ARG1_REG, - PSP_ARG2_REG, - PSP_NUM_IN_REGS, /* number of input registers */ - PSP_INTR_REG = PSP_NUM_IN_REGS, - PSP_STATUS_REG, - PSP_RESP_REG, - PSP_PWAITMODE_REG, - PSP_MAX_REGS /* Keep this at the end */ -}; - struct amdxdna_client; struct amdxdna_fw_ver; struct amdxdna_hwctx; struct amdxdna_sched_job; -struct psp_config { - const void *fw_buf; - u32 fw_size; - void __iomem *psp_regs[PSP_MAX_REGS]; -}; - -struct aie_version { - u16 major; - u16 minor; -}; - -struct aie_tile_metadata { - u16 row_count; - u16 row_start; - u16 dma_channel_count; - u16 lock_count; - u16 event_reg_count; -}; - -struct aie_metadata { - u32 size; - u16 cols; - u16 rows; - struct aie_version version; - struct aie_tile_metadata core; - struct aie_tile_metadata mem; - struct aie_tile_metadata shim; -}; - enum rt_config_category { AIE2_RT_CFG_INIT, AIE2_RT_CFG_CLK_GATING, @@ -202,24 +143,19 @@ struct aie2_exec_msg_ops { u32 (*get_chain_msg_op)(u32 cmd_op); }; +enum aie2_tdr_status { + AIE2_TDR_WAIT, + AIE2_TDR_SIGNALED, +}; + struct amdxdna_dev_hdl { - struct amdxdna_dev *xdna; + struct aie_device aie; const struct amdxdna_dev_priv *priv; void __iomem *sram_base; - void __iomem *smu_base; void __iomem *mbox_base; - struct psp_device *psp_hdl; - - struct xdna_mailbox_chann_res mgmt_x2i; - struct xdna_mailbox_chann_res mgmt_i2x; - u32 mgmt_chan_idx; - u32 mgmt_prot_major; - u32 mgmt_prot_minor; u32 total_col; - struct aie_version version; - struct aie_metadata metadata; - unsigned long feature_mask; + struct amdxdna_drm_query_aie_version version; struct aie2_exec_msg_ops *exec_msg_ops; /* power management and clock*/ @@ -237,63 +173,58 @@ struct amdxdna_dev_hdl { /* Mailbox and the management channel */ struct mailbox *mbox; - struct mailbox_channel *mgmt_chann; struct async_events *async_events; enum aie2_dev_status dev_status; u32 hwctx_num; struct amdxdna_async_error last_async_err; -}; - -#define DEFINE_BAR_OFFSET(reg_name, bar, reg_addr) \ - [reg_name] = {bar##_BAR_INDEX, (reg_addr) - bar##_BAR_BASE} - -struct aie2_bar_off_pair { - int bar_idx; - u32 offset; + enum aie2_tdr_status tdr_status; }; struct aie2_hw_ops { int (*set_dpm)(struct amdxdna_dev_hdl *ndev, u32 dpm_level); + int (*update_counters)(struct amdxdna_dev_hdl *ndev); }; +#define aie2_update_counters(ndev) \ +({ \ + typeof(ndev) _ndev = ndev; \ + if (_ndev->priv->hw_ops->update_counters) \ + _ndev->priv->hw_ops->update_counters(_ndev); \ +}) + enum aie2_fw_feature { AIE2_NPU_COMMAND, AIE2_PREEMPT, AIE2_TEMPORAL_ONLY, AIE2_APP_HEALTH, + AIE2_ADD_HOST_BUFFER, + AIE2_UPDATE_PROPERTY, + AIE2_GET_DEV_REVISION, AIE2_FEATURE_MAX }; -struct aie2_fw_feature_tbl { - u64 features; - u32 major; - u32 max_minor; - u32 min_minor; -}; - #define AIE2_ALL_FEATURES GENMASK_ULL(AIE2_FEATURE_MAX - 1, AIE2_NPU_COMMAND) -#define AIE2_FEATURE_ON(ndev, feature) test_bit(feature, &(ndev)->feature_mask) struct amdxdna_dev_priv { const char *fw_path; const struct rt_config *rt_config; const struct dpm_clk_freq *dpm_clk_tbl; - const struct aie2_fw_feature_tbl *fw_feature_tbl; #define COL_ALIGN_NONE 0 #define COL_ALIGN_NATURE 1 u32 col_align; + u32 col_opc; u32 mbox_dev_addr; /* If mbox_size is 0, use BAR size. See MBOX_SIZE macro */ u32 mbox_size; u32 hwctx_limit; u32 sram_dev_addr; - struct aie2_bar_off_pair sram_offs[SRAM_MAX_INDEX]; - struct aie2_bar_off_pair psp_regs_off[PSP_MAX_REGS]; - struct aie2_bar_off_pair smu_regs_off[SMU_MAX_REGS]; - struct aie2_hw_ops hw_ops; + struct aie_bar_off_pair sram_offs[SRAM_MAX_INDEX]; + struct aie_bar_off_pair psp_regs_off[PSP_MAX_REGS]; + struct aie_bar_off_pair smu_regs_off[SMU_MAX_REGS]; + const struct aie2_hw_ops *hw_ops; }; extern const struct amdxdna_dev_ops aie2_ops; @@ -306,25 +237,15 @@ extern const struct dpm_clk_freq npu1_dpm_clk_table[]; extern const struct dpm_clk_freq npu4_dpm_clk_table[]; extern const struct rt_config npu1_default_rt_cfg[]; extern const struct rt_config npu4_default_rt_cfg[]; -extern const struct aie2_fw_feature_tbl npu4_fw_feature_table[]; - -/* aie2_smu.c */ -int aie2_smu_init(struct amdxdna_dev_hdl *ndev); -void aie2_smu_fini(struct amdxdna_dev_hdl *ndev); -int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level); -int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level); +extern const struct amdxdna_fw_feature_tbl npu4_fw_feature_table[]; +extern const struct amdxdna_rev_vbnv npu4_rev_vbnv_tbl[]; +extern const struct aie2_hw_ops npu4_hw_ops; /* aie2_pm.c */ int aie2_pm_init(struct amdxdna_dev_hdl *ndev); int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type target); int aie2_pm_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level); -/* aie2_psp.c */ -struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config *conf); -int aie2_psp_start(struct psp_device *psp); -void aie2_psp_stop(struct psp_device *psp); -int aie2_psp_waitmode_poll(struct psp_device *psp); - /* aie2_error.c */ int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev); void aie2_error_async_events_free(struct amdxdna_dev_hdl *ndev); @@ -340,15 +261,19 @@ int aie2_resume_fw(struct amdxdna_dev_hdl *ndev); int aie2_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 value); int aie2_get_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 *value); int aie2_assign_mgmt_pasid(struct amdxdna_dev_hdl *ndev, u16 pasid); -int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, struct aie_version *version); -int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, struct aie_metadata *metadata); +int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, + struct amdxdna_drm_query_aie_version *version); +int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, + struct amdxdna_drm_query_aie_metadata *metadata); int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev, struct amdxdna_fw_ver *fw_ver); int aie2_query_app_health(struct amdxdna_dev_hdl *ndev, u32 context_id, struct app_health_report *report); +int aie2_get_dev_revision(struct amdxdna_dev_hdl *ndev, enum aie2_dev_revision *rev); int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx); int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx); int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size); +int aie2_add_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size); int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, u32 size, u32 *cols_filled); int aie2_query_telemetry(struct amdxdna_dev_hdl *ndev, char __user *buf, u32 size, @@ -369,10 +294,7 @@ int aie2_sync_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, int (*notify_cb)(void *, void __iomem *, size_t)); int aie2_config_debug_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, int (*notify_cb)(void *, void __iomem *, size_t)); -void *aie2_alloc_msg_buffer(struct amdxdna_dev_hdl *ndev, u32 *size, - dma_addr_t *dma_addr); -void aie2_free_msg_buffer(struct amdxdna_dev_hdl *ndev, size_t size, - void *cpu_addr, dma_addr_t dma_addr); +int aie2_update_prop_time_quota(struct amdxdna_dev_hdl *ndev, u32 us); /* aie2_hwctx.c */ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx); @@ -383,5 +305,6 @@ void aie2_hwctx_suspend(struct amdxdna_client *client); int aie2_hwctx_resume(struct amdxdna_client *client); int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq); void aie2_hmm_invalidate(struct amdxdna_gem_obj *abo, unsigned long cur_seq); +int aie2_hwctx_heap_expand(struct amdxdna_hwctx *hwctx, struct amdxdna_gem_obj *heap); #endif /* _AIE2_PCI_H_ */ diff --git a/drivers/accel/amdxdna/aie2_pm.c b/drivers/accel/amdxdna/aie2_pm.c index 29bd4403a94d..4fe6030d2c41 100644 --- a/drivers/accel/amdxdna/aie2_pm.c +++ b/drivers/accel/amdxdna/aie2_pm.c @@ -31,14 +31,14 @@ int aie2_pm_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) { int ret; - ret = amdxdna_pm_resume_get_locked(ndev->xdna); + ret = amdxdna_pm_resume_get_locked(ndev->aie.xdna); if (ret) return ret; - ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level); + ret = ndev->priv->hw_ops->set_dpm(ndev, dpm_level); if (!ret) ndev->dpm_level = dpm_level; - amdxdna_pm_suspend_put(ndev->xdna); + amdxdna_pm_suspend_put(ndev->aie.xdna); return ret; } @@ -49,7 +49,7 @@ int aie2_pm_init(struct amdxdna_dev_hdl *ndev) if (ndev->dev_status != AIE2_DEV_UNINIT) { /* Resume device */ - ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->dpm_level); + ret = ndev->priv->hw_ops->set_dpm(ndev, ndev->dpm_level); if (ret) return ret; @@ -64,7 +64,7 @@ int aie2_pm_init(struct amdxdna_dev_hdl *ndev) ndev->max_dpm_level++; ndev->max_dpm_level--; - ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->max_dpm_level); + ret = ndev->priv->hw_ops->set_dpm(ndev, ndev->max_dpm_level); if (ret) return ret; ndev->dpm_level = ndev->max_dpm_level; @@ -74,14 +74,14 @@ int aie2_pm_init(struct amdxdna_dev_hdl *ndev) return ret; ndev->pw_mode = POWER_MODE_DEFAULT; - ndev->dft_dpm_level = ndev->max_dpm_level; + ndev->dft_dpm_level = 0; return 0; } int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type target) { - struct amdxdna_dev *xdna = ndev->xdna; + struct amdxdna_dev *xdna = ndev->aie.xdna; u32 clk_gating, dpm_level; int ret; @@ -108,6 +108,14 @@ int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type clk_gating = AIE2_CLK_GATING_ENABLE; dpm_level = ndev->dft_dpm_level; break; + case POWER_MODE_LOW: + clk_gating = AIE2_CLK_GATING_ENABLE; + dpm_level = 0; + break; + case POWER_MODE_MEDIUM: + clk_gating = AIE2_CLK_GATING_ENABLE; + dpm_level = ndev->max_dpm_level / 2; + break; default: return -EOPNOTSUPP; } diff --git a/drivers/accel/amdxdna/aie2_psp.c b/drivers/accel/amdxdna/aie2_psp.c deleted file mode 100644 index 3a7130577e3e..000000000000 --- a/drivers/accel/amdxdna/aie2_psp.c +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "aie2_pci.h" -#include "amdxdna_mailbox.h" -#include "amdxdna_pci_drv.h" - -#define PSP_STATUS_READY BIT(31) - -/* PSP commands */ -#define PSP_VALIDATE 1 -#define PSP_START 2 -#define PSP_RELEASE_TMR 3 - -/* PSP special arguments */ -#define PSP_START_COPY_FW 1 - -/* PSP response error code */ -#define PSP_ERROR_CANCEL 0xFFFF0002 -#define PSP_ERROR_BAD_STATE 0xFFFF0007 - -#define PSP_FW_ALIGN 0x10000 -#define PSP_POLL_INTERVAL 20000 /* us */ -#define PSP_POLL_TIMEOUT 1000000 /* us */ - -#define PSP_REG(p, reg) ((p)->psp_regs[reg]) - -struct psp_device { - struct drm_device *ddev; - struct psp_config conf; - u32 fw_buf_sz; - u64 fw_paddr; - void *fw_buffer; - void __iomem *psp_regs[PSP_MAX_REGS]; -}; - -static int psp_exec(struct psp_device *psp, u32 *reg_vals) -{ - u32 resp_code; - int ret, i; - u32 ready; - - /* Write command and argument registers */ - for (i = 0; i < PSP_NUM_IN_REGS; i++) - writel(reg_vals[i], PSP_REG(psp, i)); - - /* clear and set PSP INTR register to kick off */ - writel(0, PSP_REG(psp, PSP_INTR_REG)); - writel(1, PSP_REG(psp, PSP_INTR_REG)); - - /* PSP should be busy. Wait for ready, so we know task is done. */ - ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_STATUS_REG), ready, - FIELD_GET(PSP_STATUS_READY, ready), - PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT); - if (ret) { - drm_err(psp->ddev, "PSP is not ready, ret 0x%x", ret); - return ret; - } - - resp_code = readl(PSP_REG(psp, PSP_RESP_REG)); - if (resp_code) { - drm_err(psp->ddev, "fw return error 0x%x", resp_code); - return -EIO; - } - - return 0; -} - -int aie2_psp_waitmode_poll(struct psp_device *psp) -{ - struct amdxdna_dev *xdna = to_xdna_dev(psp->ddev); - u32 mode_reg; - int ret; - - ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_PWAITMODE_REG), mode_reg, - (mode_reg & 0x1) == 1, - PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT); - if (ret) - XDNA_ERR(xdna, "fw waitmode reg error, ret %d", ret); - - return ret; -} - -void aie2_psp_stop(struct psp_device *psp) -{ - u32 reg_vals[PSP_NUM_IN_REGS] = { PSP_RELEASE_TMR, }; - int ret; - - ret = psp_exec(psp, reg_vals); - if (ret) - drm_err(psp->ddev, "release tmr failed, ret %d", ret); -} - -int aie2_psp_start(struct psp_device *psp) -{ - u32 reg_vals[PSP_NUM_IN_REGS]; - int ret; - - reg_vals[0] = PSP_VALIDATE; - reg_vals[1] = lower_32_bits(psp->fw_paddr); - reg_vals[2] = upper_32_bits(psp->fw_paddr); - reg_vals[3] = psp->fw_buf_sz; - - ret = psp_exec(psp, reg_vals); - if (ret) { - drm_err(psp->ddev, "failed to validate fw, ret %d", ret); - return ret; - } - - memset(reg_vals, 0, sizeof(reg_vals)); - reg_vals[0] = PSP_START; - reg_vals[1] = PSP_START_COPY_FW; - ret = psp_exec(psp, reg_vals); - if (ret) { - drm_err(psp->ddev, "failed to start fw, ret %d", ret); - return ret; - } - - return 0; -} - -struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config *conf) -{ - struct psp_device *psp; - u64 offset; - - psp = drmm_kzalloc(ddev, sizeof(*psp), GFP_KERNEL); - if (!psp) - return NULL; - - psp->ddev = ddev; - memcpy(psp->psp_regs, conf->psp_regs, sizeof(psp->psp_regs)); - - psp->fw_buf_sz = ALIGN(conf->fw_size, PSP_FW_ALIGN); - psp->fw_buffer = drmm_kmalloc(ddev, psp->fw_buf_sz + PSP_FW_ALIGN, GFP_KERNEL); - if (!psp->fw_buffer) { - drm_err(ddev, "no memory for fw buffer"); - return NULL; - } - - /* - * AMD Platform Security Processor(PSP) requires host physical - * address to load NPU firmware. - */ - psp->fw_paddr = virt_to_phys(psp->fw_buffer); - offset = ALIGN(psp->fw_paddr, PSP_FW_ALIGN) - psp->fw_paddr; - psp->fw_paddr += offset; - memcpy(psp->fw_buffer + offset, conf->fw_buf, conf->fw_size); - - return psp; -} diff --git a/drivers/accel/amdxdna/aie2_smu.c b/drivers/accel/amdxdna/aie2_smu.c deleted file mode 100644 index d8c31924e501..000000000000 --- a/drivers/accel/amdxdna/aie2_smu.c +++ /dev/null @@ -1,156 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. - */ - -#include -#include -#include -#include -#include - -#include "aie2_pci.h" -#include "amdxdna_pci_drv.h" - -#define SMU_RESULT_OK 1 - -/* SMU commands */ -#define AIE2_SMU_POWER_ON 0x3 -#define AIE2_SMU_POWER_OFF 0x4 -#define AIE2_SMU_SET_MPNPUCLK_FREQ 0x5 -#define AIE2_SMU_SET_HCLK_FREQ 0x6 -#define AIE2_SMU_SET_SOFT_DPMLEVEL 0x7 -#define AIE2_SMU_SET_HARD_DPMLEVEL 0x8 - -#define NPU4_DPM_TOPS(ndev, dpm_level) \ -({ \ - typeof(ndev) _ndev = ndev; \ - (4096 * (_ndev)->total_col * \ - (_ndev)->priv->dpm_clk_tbl[dpm_level].hclk / 1000000); \ -}) - -static int aie2_smu_exec(struct amdxdna_dev_hdl *ndev, u32 reg_cmd, - u32 reg_arg, u32 *out) -{ - u32 resp; - int ret; - - writel(0, SMU_REG(ndev, SMU_RESP_REG)); - writel(reg_arg, SMU_REG(ndev, SMU_ARG_REG)); - writel(reg_cmd, SMU_REG(ndev, SMU_CMD_REG)); - - /* Clear and set SMU_INTR_REG to kick off */ - writel(0, SMU_REG(ndev, SMU_INTR_REG)); - writel(1, SMU_REG(ndev, SMU_INTR_REG)); - - ret = readx_poll_timeout(readl, SMU_REG(ndev, SMU_RESP_REG), resp, - resp, AIE2_INTERVAL, AIE2_TIMEOUT); - if (ret) { - XDNA_ERR(ndev->xdna, "smu cmd %d timed out", reg_cmd); - return ret; - } - - if (out) - *out = readl(SMU_REG(ndev, SMU_OUT_REG)); - - if (resp != SMU_RESULT_OK) { - XDNA_ERR(ndev->xdna, "smu cmd %d failed, 0x%x", reg_cmd, resp); - return -EINVAL; - } - - return 0; -} - -int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) -{ - u32 freq; - int ret; - - ret = aie2_smu_exec(ndev, AIE2_SMU_SET_MPNPUCLK_FREQ, - ndev->priv->dpm_clk_tbl[dpm_level].npuclk, &freq); - if (ret) { - XDNA_ERR(ndev->xdna, "Set npu clock to %d failed, ret %d\n", - ndev->priv->dpm_clk_tbl[dpm_level].npuclk, ret); - return ret; - } - ndev->npuclk_freq = freq; - - ret = aie2_smu_exec(ndev, AIE2_SMU_SET_HCLK_FREQ, - ndev->priv->dpm_clk_tbl[dpm_level].hclk, &freq); - if (ret) { - XDNA_ERR(ndev->xdna, "Set h clock to %d failed, ret %d\n", - ndev->priv->dpm_clk_tbl[dpm_level].hclk, ret); - return ret; - } - - ndev->hclk_freq = freq; - ndev->max_tops = 2 * ndev->total_col; - ndev->curr_tops = ndev->max_tops * freq / 1028; - - XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n", - ndev->npuclk_freq, ndev->hclk_freq); - - return 0; -} - -int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) -{ - int ret; - - ret = aie2_smu_exec(ndev, AIE2_SMU_SET_HARD_DPMLEVEL, dpm_level, NULL); - if (ret) { - XDNA_ERR(ndev->xdna, "Set hard dpm level %d failed, ret %d ", - dpm_level, ret); - return ret; - } - - ret = aie2_smu_exec(ndev, AIE2_SMU_SET_SOFT_DPMLEVEL, dpm_level, NULL); - if (ret) { - XDNA_ERR(ndev->xdna, "Set soft dpm level %d failed, ret %d", - dpm_level, ret); - return ret; - } - - ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk; - ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk; - ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->max_dpm_level); - ndev->curr_tops = NPU4_DPM_TOPS(ndev, dpm_level); - - XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n", - ndev->npuclk_freq, ndev->hclk_freq); - - return 0; -} - -int aie2_smu_init(struct amdxdna_dev_hdl *ndev) -{ - int ret; - - /* - * Failing to set power off indicates an unrecoverable hardware or - * firmware error. - */ - ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_OFF, 0, NULL); - if (ret) { - XDNA_ERR(ndev->xdna, "Access power failed, ret %d", ret); - return ret; - } - - ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_ON, 0, NULL); - if (ret) { - XDNA_ERR(ndev->xdna, "Power on failed, ret %d", ret); - return ret; - } - - return 0; -} - -void aie2_smu_fini(struct amdxdna_dev_hdl *ndev) -{ - int ret; - - ndev->priv->hw_ops.set_dpm(ndev, 0); - ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_OFF, 0, NULL); - if (ret) - XDNA_ERR(ndev->xdna, "Power off failed, ret %d", ret); -} diff --git a/drivers/accel/amdxdna/aie2_solver.c b/drivers/accel/amdxdna/aie2_solver.c index 3611e3268d79..6f3ee77d5264 100644 --- a/drivers/accel/amdxdna/aie2_solver.c +++ b/drivers/accel/amdxdna/aie2_solver.c @@ -52,7 +52,7 @@ static u32 calculate_gops(struct aie_qos *rqos) u32 service_rate = 0; if (rqos->latency) - service_rate = (1000 / rqos->latency); + service_rate = max_t(u32, 1000 / rqos->latency, 1); if (rqos->fps > service_rate) return rqos->fps * rqos->gops; @@ -348,6 +348,7 @@ int xrs_release_resource(void *hdl, u64 rid) { struct solver_state *xrs = hdl; struct solver_node *node; + u32 level = 0; node = rg_search_node(&xrs->rgp, rid); if (!node) { @@ -358,6 +359,13 @@ int xrs_release_resource(void *hdl, u64 rid) xrs->cfg.actions->unload(node->cb_arg); remove_solver_node(&xrs->rgp, node); + /* set the dpm level which fits all the sessions */ + list_for_each_entry(node, &xrs->rgp.node_list, list) { + if (node->dpm_level > level) + level = node->dpm_level; + } + xrs->cfg.actions->set_dft_dpm_level(xrs->cfg.ddev, level); + return 0; } diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c new file mode 100644 index 000000000000..8408b0d2696f --- /dev/null +++ b/drivers/accel/amdxdna/aie4_ctx.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "aie.h" +#include "aie4_host_queue.h" +#include "aie4_msg_priv.h" +#include "aie4_pci.h" +#include "amdxdna_ctx.h" +#include "amdxdna_gem.h" +#include "amdxdna_mailbox.h" +#include "amdxdna_mailbox_helper.h" +#include "amdxdna_pci_drv.h" + +static irqreturn_t cert_comp_isr(int irq, void *p) +{ + struct cert_comp *cert_comp = p; + + wake_up_all(&cert_comp->waitq); + return IRQ_HANDLED; +} + +static struct cert_comp *aie4_lookup_cert_comp(struct amdxdna_dev_hdl *ndev, u32 msix_idx) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev); + struct cert_comp *cert_comp; + int ret; + + guard(mutex)(&ndev->cert_comp_lock); + + cert_comp = xa_load(&ndev->cert_comp_xa, msix_idx); + if (cert_comp) { + kref_get(&cert_comp->kref); + return cert_comp; + } + + cert_comp = kzalloc_obj(*cert_comp); + if (!cert_comp) + return NULL; + + cert_comp->ndev = ndev; + cert_comp->msix_idx = msix_idx; + init_waitqueue_head(&cert_comp->waitq); + kref_init(&cert_comp->kref); + + ret = pci_irq_vector(pdev, cert_comp->msix_idx); + if (ret < 0) { + XDNA_ERR(xdna, "MSI-X idx %u is invalid, ret:%d", msix_idx, ret); + goto free_cert_comp; + } + cert_comp->irq = ret; + + ret = request_irq(cert_comp->irq, cert_comp_isr, 0, "xdna_hsa", cert_comp); + if (ret) { + XDNA_ERR(xdna, "request irq %d failed %d", cert_comp->irq, ret); + goto free_cert_comp; + } + + ret = xa_err(xa_store(&ndev->cert_comp_xa, msix_idx, cert_comp, GFP_KERNEL)); + if (ret) { + XDNA_ERR(xdna, "store cert_comp for msix idx %d failed %d", msix_idx, ret); + goto free_irq; + } + + return cert_comp; + +free_irq: + free_irq(cert_comp->irq, cert_comp); +free_cert_comp: + kfree(cert_comp); + return NULL; +} + +static void cert_comp_release(struct kref *kref) +{ + struct cert_comp *cert_comp = container_of(kref, struct cert_comp, kref); + struct amdxdna_dev_hdl *ndev = cert_comp->ndev; + + drm_WARN_ON(&ndev->aie.xdna->ddev, !mutex_is_locked(&ndev->cert_comp_lock)); + + xa_erase(&ndev->cert_comp_xa, cert_comp->msix_idx); + free_irq(cert_comp->irq, cert_comp); + kfree(cert_comp); +} + +static void aie4_put_cert_comp(struct cert_comp *cert_comp) +{ + struct amdxdna_dev_hdl *ndev; + + ndev = cert_comp->ndev; + guard(mutex)(&ndev->cert_comp_lock); + kref_put(&cert_comp->kref, cert_comp_release); +} + +static int aie4_msg_destroy_context(struct amdxdna_dev_hdl *ndev, u32 hw_context_id) +{ + DECLARE_AIE_MSG(aie4_msg_destroy_hw_context, AIE4_MSG_OP_DESTROY_HW_CONTEXT); + + req.hw_context_id = hw_context_id; + return aie_send_mgmt_msg_wait(&ndev->aie, &msg); +} + +static int aie4_hwctx_create(struct amdxdna_hwctx *hwctx) +{ + DECLARE_AIE_MSG(aie4_msg_create_hw_context, AIE4_MSG_OP_CREATE_HW_CONTEXT); + struct amdxdna_client *client = hwctx->client; + struct amdxdna_hwctx_priv *priv = hwctx->priv; + struct amdxdna_dev *xdna = hwctx->client->xdna; + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; + int ret; + + drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); + + if (!ndev->partition_id || !hwctx->num_tiles) { + XDNA_ERR(xdna, "invalid request partition_id %d, num_tiles %d", + ndev->partition_id, hwctx->num_tiles); + return -EINVAL; + } + + req.partition_id = ndev->partition_id; + req.request_num_tiles = hwctx->num_tiles; + req.pasid = FIELD_PREP(AIE4_MSG_PASID, client->pasid) | + FIELD_PREP(AIE4_MSG_PASID_VLD, 1); + req.priority_band = hwctx->qos.priority; + + req.hsa_addr_high = upper_32_bits(amdxdna_gem_dev_addr(priv->umq_bo)); + req.hsa_addr_low = lower_32_bits(amdxdna_gem_dev_addr(priv->umq_bo)); + + XDNA_DBG(xdna, "pasid 0x%x, num_tiles %d, hsa[0x%x 0x%x]", + req.pasid, req.request_num_tiles, req.hsa_addr_high, req.hsa_addr_low); + + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) { + XDNA_ERR(xdna, "create ctx failed: %d", ret); + return ret; + } + + XDNA_DBG(xdna, "resp msix: %d, ctx id: %d, doorbell: %d", + resp.job_complete_msix_idx, + resp.hw_context_id, + resp.doorbell_offset); + + /* setup interrupt completion per msix index */ + priv->cert_comp = aie4_lookup_cert_comp(ndev, resp.job_complete_msix_idx); + if (!priv->cert_comp) { + aie4_msg_destroy_context(ndev, resp.hw_context_id); + return -EINVAL; + } + + priv->hw_ctx_id = resp.hw_context_id; + hwctx->doorbell_offset = resp.doorbell_offset; + + return 0; +} + +static void aie4_hwctx_destroy(struct amdxdna_hwctx *hwctx) +{ + struct amdxdna_client *client = hwctx->client; + struct amdxdna_hwctx_priv *priv = hwctx->priv; + struct amdxdna_dev *xdna = client->xdna; + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; + + drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); + + aie4_msg_destroy_context(ndev, priv->hw_ctx_id); + aie4_put_cert_comp(priv->cert_comp); +} + +static void aie4_hwctx_umq_fini(struct amdxdna_hwctx *hwctx) +{ + if (hwctx->priv && hwctx->priv->umq_bo) + amdxdna_gem_put_obj(hwctx->priv->umq_bo); +} + +static int aie4_hwctx_umq_init(struct amdxdna_hwctx *hwctx) +{ + struct amdxdna_hwctx_priv *priv = hwctx->priv; + struct amdxdna_dev *xdna = hwctx->client->xdna; + struct amdxdna_gem_obj *umq_bo; + struct host_queue_header *qhdr; + int ret; + + umq_bo = amdxdna_gem_get_obj(hwctx->client, hwctx->umq_bo_hdl, AMDXDNA_BO_SHARE); + if (!umq_bo) { + XDNA_ERR(xdna, "cannot find umq_bo handle %d", hwctx->umq_bo_hdl); + return -ENOENT; + } + if (umq_bo->mem.size < sizeof(*qhdr)) { + XDNA_ERR(xdna, "umq_bo size is too small"); + ret = -EINVAL; + goto put_umq_bo; + } + + /* get kva address for host queue read index and write index */ + qhdr = amdxdna_gem_vmap(umq_bo); + if (!qhdr) { + ret = -ENOMEM; + goto put_umq_bo; + } + + priv->umq_bo = umq_bo; + priv->umq_read_index = &qhdr->read_index; + priv->umq_write_index = &qhdr->write_index; + + return 0; + +put_umq_bo: + amdxdna_gem_put_obj(umq_bo); + return ret; +} + +int aie4_hwctx_init(struct amdxdna_hwctx *hwctx) +{ + struct amdxdna_client *client = hwctx->client; + struct amdxdna_dev *xdna = client->xdna; + struct amdxdna_hwctx_priv *priv; + int ret; + + priv = kzalloc_obj(*priv); + if (!priv) + return -ENOMEM; + hwctx->priv = priv; + + ret = aie4_hwctx_umq_init(hwctx); + if (ret) + goto free_priv; + + ret = aie4_hwctx_create(hwctx); + if (ret) + goto umq_fini; + + XDNA_DBG(xdna, "hwctx %s init completed", hwctx->name); + return 0; + +umq_fini: + aie4_hwctx_umq_fini(hwctx); +free_priv: + kfree(priv); + hwctx->priv = NULL; + return ret; +} + +void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx) +{ + aie4_hwctx_destroy(hwctx); + aie4_hwctx_umq_fini(hwctx); + kfree(hwctx->priv); +} + +static inline bool valid_queue_index(u64 read, u64 write, u32 capacity) +{ + return (write >= read) && ((write - read) <= capacity); +} + +static u64 get_read_index(struct amdxdna_hwctx *hwctx) +{ + u64 wi = READ_ONCE(*hwctx->priv->umq_write_index); + u64 ri = READ_ONCE(*hwctx->priv->umq_read_index); + struct amdxdna_dev *xdna = hwctx->client->xdna; + + /* + * CERT cannot update read index as uint64 atomically. Driver may read + * half-updated read index when it has bits in high 32bit. In case read + * index is not valid, wait for some time and retry once. It should + * allow CERT to complete the read index update. + */ + if (!valid_queue_index(ri, wi, CTX_MAX_CMDS)) { + XDNA_WARN(xdna, "Invalid index, ri %llu, wi %llu", ri, wi); + usleep_range(100, 200); + ri = READ_ONCE(*hwctx->priv->umq_read_index); + if (!valid_queue_index(ri, wi, CTX_MAX_CMDS)) { + XDNA_ERR(xdna, "Invalid index after retry, ri %llu, wi %llu", ri, wi); + ri = 0; + } + } + + return ri; +} + +static inline bool check_cmd_done(struct amdxdna_hwctx *hwctx, u64 seq) +{ + u64 read_idx = get_read_index(hwctx); + + return read_idx > seq; +} + +int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout) +{ + unsigned long wait_jifs = MAX_SCHEDULE_TIMEOUT; + struct amdxdna_hwctx_priv *priv = hwctx->priv; + struct cert_comp *cert_comp = priv->cert_comp; + long ret; + + if (timeout) + wait_jifs = msecs_to_jiffies(timeout); + + ret = wait_event_interruptible_timeout(cert_comp->waitq, + (check_cmd_done(hwctx, seq)), + wait_jifs); + + if (!ret) + ret = -ETIME; + + return ret <= 0 ? ret : 0; +} + +int aie4_hwctx_valid_doorbell(struct amdxdna_client *client, u32 vm_pgoff) +{ + struct amdxdna_hwctx *hwctx; + unsigned long hwctx_id; + int idx; + + idx = srcu_read_lock(&client->hwctx_srcu); + amdxdna_for_each_hwctx(client, hwctx_id, hwctx) { + if (vm_pgoff == (hwctx->doorbell_offset >> PAGE_SHIFT)) { + srcu_read_unlock(&client->hwctx_srcu, idx); + return 1; + } + } + srcu_read_unlock(&client->hwctx_srcu, idx); + + return 0; +} diff --git a/drivers/accel/amdxdna/aie4_host_queue.h b/drivers/accel/amdxdna/aie4_host_queue.h new file mode 100644 index 000000000000..1b33eda3f727 --- /dev/null +++ b/drivers/accel/amdxdna/aie4_host_queue.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _AIE4_HOST_QUEUE_H_ +#define _AIE4_HOST_QUEUE_H_ + +#include + +#define CTX_MAX_CMDS 32 + +struct host_queue_header { + __u64 read_index; + struct { + __u16 major; + __u16 minor; + } version; + __u32 capacity; /* Queue capacity, must be power of two. */ + __u64 write_index; + __u64 data_address; /* The xdna dev addr for payload. */ +}; + +#endif /* _AIE4_HOST_QUEUE_H_ */ diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c new file mode 100644 index 000000000000..88037edbb02a --- /dev/null +++ b/drivers/accel/amdxdna/aie4_message.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include +#include +#include + +#include "aie.h" +#include "aie4_msg_priv.h" +#include "aie4_pci.h" +#include "amdxdna_mailbox.h" +#include "amdxdna_mailbox_helper.h" +#include "amdxdna_pci_drv.h" + +int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev) +{ + DECLARE_AIE_MSG(aie4_msg_suspend, AIE4_MSG_OP_SUSPEND); + int ret; + + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) + XDNA_ERR(ndev->aie.xdna, "Failed to suspend fw, ret %d", ret); + + return ret; +} + +int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev, + struct amdxdna_drm_query_aie_metadata *metadata) +{ + DECLARE_AIE_MSG(aie4_msg_aie4_tile_info, AIE4_MSG_OP_AIE_TILE_INFO); + int ret; + + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) + return ret; + + metadata->col_size = resp.info.size; + metadata->cols = resp.info.cols; + metadata->rows = resp.info.rows; + + metadata->version.major = resp.info.major; + metadata->version.minor = resp.info.minor; + + metadata->core.row_count = resp.info.core_rows; + metadata->core.row_start = resp.info.core_row_start; + metadata->core.dma_channel_count = resp.info.core_dma_channels; + metadata->core.lock_count = resp.info.core_locks; + metadata->core.event_reg_count = resp.info.core_events; + + metadata->mem.row_count = resp.info.mem_rows; + metadata->mem.row_start = resp.info.mem_row_start; + metadata->mem.dma_channel_count = resp.info.mem_dma_channels; + metadata->mem.lock_count = resp.info.mem_locks; + metadata->mem.event_reg_count = resp.info.mem_events; + + metadata->shim.row_count = resp.info.shim_rows; + metadata->shim.row_start = resp.info.shim_row_start; + metadata->shim.dma_channel_count = resp.info.shim_dma_channels; + metadata->shim.lock_count = resp.info.shim_locks; + metadata->shim.event_reg_count = resp.info.shim_events; + + return 0; +} + +int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev) +{ + DECLARE_AIE_MSG(aie4_msg_attach_work_buffer, AIE4_MSG_OP_ATTACH_WORK_BUFFER); + struct amdxdna_dev *xdna = ndev->aie.xdna; + int ret; + + req.buff_addr = ndev->work_buf_addr; + req.buff_size = AIE4_WORK_BUFFER_MIN_SIZE; + + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) + XDNA_ERR(xdna, "Failed to attach work buffer, ret %d", ret); + else + XDNA_DBG(xdna, "Attached work buffer"); + + return ret; +} diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h new file mode 100644 index 000000000000..af0866045b91 --- /dev/null +++ b/drivers/accel/amdxdna/aie4_msg_priv.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _AIE4_MSG_PRIV_H_ +#define _AIE4_MSG_PRIV_H_ + +#include +#include + +enum aie4_msg_opcode { + AIE4_MSG_OP_SUSPEND = 0x10003, + AIE4_MSG_OP_ATTACH_WORK_BUFFER = 0x1000D, + + AIE4_MSG_OP_CREATE_VFS = 0x20001, + AIE4_MSG_OP_DESTROY_VFS = 0x20002, + + AIE4_MSG_OP_CREATE_PARTITION = 0x30001, + AIE4_MSG_OP_DESTROY_PARTITION = 0x30002, + AIE4_MSG_OP_CREATE_HW_CONTEXT = 0x30003, + AIE4_MSG_OP_DESTROY_HW_CONTEXT = 0x30004, + AIE4_MSG_OP_AIE_TILE_INFO = 0x30006, +}; + +enum aie4_msg_status { + AIE4_MSG_STATUS_SUCCESS = 0x0, + AIE4_MSG_STATUS_ERROR = 0x1, + AIE4_MSG_STATUS_NOTSUPP = 0x2, + MAX_AIE4_MSG_STATUS_CODE = 0x4, +}; + +struct aie4_msg_suspend_req { + __u32 rsvd; +} __packed; + +struct aie4_msg_suspend_resp { + enum aie4_msg_status status; +} __packed; + +struct aie4_msg_create_vfs_req { + __u32 vf_cnt; +} __packed; + +struct aie4_msg_create_vfs_resp { + enum aie4_msg_status status; +} __packed; + +struct aie4_msg_destroy_vfs_req { + __u32 rsvd; +} __packed; + +struct aie4_msg_destroy_vfs_resp { + enum aie4_msg_status status; +} __packed; + +struct aie4_msg_create_partition_req { + __u32 partition_col_start; + __u32 partition_col_count; +} __packed; + +struct aie4_msg_create_partition_resp { + enum aie4_msg_status status; + __u32 partition_id; +} __packed; + +struct aie4_msg_destroy_partition_req { + __u32 partition_id; +} __packed; + +struct aie4_msg_destroy_partition_resp { + enum aie4_msg_status status; +} __packed; + +struct aie4_msg_create_hw_context_req { + __u32 partition_id; + __u32 request_num_tiles; + __u32 hsa_addr_high; + __u32 hsa_addr_low; +#define AIE4_MSG_PASID GENMASK(19, 0) +#define AIE4_MSG_PASID_VLD GENMASK(31, 31) + __u32 pasid; + __u32 priority_band; +} __packed; + +struct aie4_msg_create_hw_context_resp { + enum aie4_msg_status status; + __u32 hw_context_id; + __u32 doorbell_offset; + __u32 job_complete_msix_idx; +} __packed; + +struct aie4_msg_destroy_hw_context_req { + __u32 hw_context_id; + __u32 resvd1; +} __packed; + +struct aie4_msg_destroy_hw_context_resp { + enum aie4_msg_status status; +} __packed; + +struct aie4_tile_info { + __u32 size; + __u16 major; + __u16 minor; + __u16 cols; + __u16 rows; + __u16 core_rows; + __u16 mem_rows; + __u16 shim_rows; + __u16 core_row_start; + __u16 mem_row_start; + __u16 shim_row_start; + __u16 core_dma_channels; + __u16 mem_dma_channels; + __u16 shim_dma_channels; + __u16 core_locks; + __u16 mem_locks; + __u16 shim_locks; + __u16 core_events; + __u16 mem_events; + __u16 shim_events; + __u16 resvd; +} __packed; + +struct aie4_msg_aie4_tile_info_req { + __u32 resvd; +} __packed; + +struct aie4_msg_aie4_tile_info_resp { + enum aie4_msg_status status; + struct aie4_tile_info info; +} __packed; + +#define AIE4_WORK_BUFFER_MIN_SIZE SZ_4M + +struct aie4_msg_attach_work_buffer_req { + __u64 buff_addr; + __u32 reserved; + __u32 buff_size; +} __packed; + +struct aie4_msg_attach_work_buffer_resp { + enum aie4_msg_status status; +} __packed; + +#endif /* _AIE4_MSG_PRIV_H_ */ diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c new file mode 100644 index 000000000000..a58a83af42a4 --- /dev/null +++ b/drivers/accel/amdxdna/aie4_pci.c @@ -0,0 +1,667 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include + +#include "aie.h" +#include "aie4_msg_priv.h" +#include "aie4_pci.h" +#include "amdxdna_mailbox.h" +#include "amdxdna_mailbox_helper.h" +#include "amdxdna_pci_drv.h" + +#define NO_IOHUB 0 +#define PSP_NOTIFY_INTR 0xD007BE11 +#define AIE4_TOTAL_COLUMN 3 + +/* + * The management mailbox channel is allocated by firmware. + * The related register and ring buffer information is on SRAM BAR. + * This struct is the register layout. + */ +struct mailbox_info { + __u32 valid; + __u32 protocol_major; + __u32 protocol_minor; + __u32 x2i_tail_offset; + __u32 x2i_head_offset; + __u32 x2i_buffer_addr; + __u32 x2i_buffer_size; + __u32 i2x_tail_offset; + __u32 i2x_head_offset; + __u32 i2x_buffer_addr; + __u32 i2x_buffer_size; + __u32 i2x_msi_idx; + __u32 reserved[4]; +}; + +static int aie4_fw_is_alive(struct amdxdna_dev *xdna) +{ + const struct amdxdna_dev_priv *npriv = xdna->dev_info->dev_priv; + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; + u32 __iomem *src; + u32 fw_is_valid; + int ret; + + src = ndev->rbuf_base + npriv->mbox_info_off; + + ret = readx_poll_timeout(readl, src + offsetof(struct mailbox_info, valid), + fw_is_valid, (fw_is_valid == 0x1), + AIE_INTERVAL, AIE_TIMEOUT); + if (ret) + XDNA_ERR(xdna, "fw_is_valid=%d after %d ms", + fw_is_valid, DIV_ROUND_CLOSEST(AIE_TIMEOUT, 1000000)); + + return ret; +} + +static void aie4_read_mbox_info(struct amdxdna_dev *xdna, + struct mailbox_info *mbox_info) +{ + const struct amdxdna_dev_priv *npriv = xdna->dev_info->dev_priv; + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; + u32 *dst = (u32 *)mbox_info; + u32 __iomem *src; + int i; + + src = ndev->rbuf_base + npriv->mbox_info_off; + + for (i = 0; i < sizeof(*mbox_info) / sizeof(u32); i++) + dst[i] = readl(&src[i]); +} + +static int aie4_mailbox_info(struct amdxdna_dev *xdna, + struct mailbox_info *mbox_info) +{ + int ret; + + ret = aie4_fw_is_alive(xdna); + if (ret) + return ret; + + aie4_read_mbox_info(xdna, mbox_info); + + ret = aie_check_protocol(&xdna->dev_handle->aie, + mbox_info->protocol_major, + mbox_info->protocol_minor); + if (ret) + XDNA_ERR(xdna, "mailbox major.minor %d.%d is not supported", + mbox_info->protocol_major, mbox_info->protocol_minor); + + return ret; +} + +static void aie4_mailbox_fini(struct amdxdna_dev_hdl *ndev) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + + aie_destroy_chann(&ndev->aie, &ndev->aie.mgmt_chann); + drmm_kfree(&xdna->ddev, ndev->mbox); + ndev->mbox = NULL; +} + +static int aie4_irq_init(struct amdxdna_dev *xdna) +{ + struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev); + int ret, nvec; + + nvec = pci_msix_vec_count(pdev); + XDNA_DBG(xdna, "irq vectors:%d", nvec); + if (nvec <= 0) { + XDNA_ERR(xdna, "does not get number of interrupt vector"); + return -EINVAL; + } + + ret = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); + if (ret < 0) { + XDNA_ERR(xdna, "failed to alloc irq vector, ret: %d", ret); + return ret; + } + + return 0; +} + +static int aie4_mailbox_start(struct amdxdna_dev *xdna, + struct mailbox_info *mbi) +{ + struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev); + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; + const struct amdxdna_dev_priv *npriv = xdna->dev_info->dev_priv; + struct xdna_mailbox_chann_res *i2x; + struct xdna_mailbox_chann_res *x2i; + int mgmt_mb_irq; + int ret; + + struct xdna_mailbox_res mbox_res = { + .ringbuf_base = ndev->rbuf_base, + .ringbuf_size = pci_resource_len(pdev, npriv->mbox_rbuf_bar), + .mbox_base = ndev->mbox_base, + .mbox_size = pci_resource_len(pdev, npriv->mbox_bar), + .name = "xdna_aie4_mailbox", + }; + + i2x = &ndev->aie.mgmt_i2x; + x2i = &ndev->aie.mgmt_x2i; + + x2i->mb_head_ptr_reg = mbi->x2i_head_offset; + x2i->mb_tail_ptr_reg = mbi->x2i_tail_offset; + x2i->rb_start_addr = mbi->x2i_buffer_addr; + x2i->rb_size = mbi->x2i_buffer_size; + + i2x->rb_start_addr = mbi->i2x_buffer_addr; + i2x->rb_size = mbi->i2x_buffer_size; + i2x->mb_head_ptr_reg = mbi->i2x_head_offset; + i2x->mb_tail_ptr_reg = mbi->i2x_tail_offset; + + ndev->aie.mgmt_chan_idx = mbi->i2x_msi_idx; + aie_dump_mgmt_chann_debug(&ndev->aie); + + ndev->mbox = xdnam_mailbox_create(&xdna->ddev, &mbox_res); + if (!ndev->mbox) { + XDNA_ERR(xdna, "failed to create mailbox device"); + return -ENODEV; + } + + ndev->aie.mgmt_chann = xdna_mailbox_alloc_channel(ndev->mbox); + if (!ndev->aie.mgmt_chann) { + XDNA_ERR(xdna, "failed to alloc mailbox channel"); + return -ENODEV; + } + + mgmt_mb_irq = pci_irq_vector(pdev, ndev->aie.mgmt_chan_idx); + if (mgmt_mb_irq < 0) { + XDNA_ERR(xdna, "failed to alloc irq vector, return %d", mgmt_mb_irq); + ret = mgmt_mb_irq; + goto free_channel; + } + + ret = xdna_mailbox_start_channel(ndev->aie.mgmt_chann, + &ndev->aie.mgmt_x2i, + &ndev->aie.mgmt_i2x, + NO_IOHUB, + mgmt_mb_irq); + if (ret) { + XDNA_ERR(xdna, "failed to start management mailbox channel"); + ret = -EINVAL; + goto free_channel; + } + + XDNA_DBG(xdna, "Mailbox management channel created"); + return 0; + +free_channel: + xdna_mailbox_free_channel(ndev->aie.mgmt_chann); + ndev->aie.mgmt_chann = NULL; + return ret; +} + +static int aie4_mailbox_init(struct amdxdna_dev_hdl *ndev) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + struct mailbox_info mbox_info; + int ret; + + ret = aie4_mailbox_info(xdna, &mbox_info); + if (ret) + return ret; + + return aie4_mailbox_start(xdna, &mbox_info); +} + +static void aie4_fw_stop(struct amdxdna_dev_hdl *ndev) +{ + aie_psp_stop(ndev->aie.psp_hdl); + aie_smu_fini(ndev->aie.smu_hdl); +} + +static int aie4_fw_start(struct amdxdna_dev_hdl *ndev) +{ + int ret; + + ret = aie_smu_init(ndev->aie.smu_hdl); + if (ret) { + XDNA_ERR(ndev->aie.xdna, "failed to init smu, ret %d", ret); + return ret; + } + + ret = aie_psp_start(ndev->aie.psp_hdl); + if (ret) { + XDNA_ERR(ndev->aie.xdna, "failed to start psp, ret %d", ret); + aie_smu_fini(ndev->aie.smu_hdl); + } + + return ret; +} + +static int aie4_partition_init(struct amdxdna_dev_hdl *ndev) +{ + DECLARE_AIE_MSG(aie4_msg_create_partition, AIE4_MSG_OP_CREATE_PARTITION); + struct amdxdna_dev *xdna = ndev->aie.xdna; + int ret; + + req.partition_col_start = 0; + req.partition_col_count = AIE4_TOTAL_COLUMN; + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) { + XDNA_ERR(xdna, "partition init failed: %d", ret); + return ret; + } + + ndev->partition_id = resp.partition_id; + return 0; +} + +static void aie4_partition_fini(struct amdxdna_dev_hdl *ndev) +{ + DECLARE_AIE_MSG(aie4_msg_destroy_partition, AIE4_MSG_OP_DESTROY_PARTITION); + struct amdxdna_dev *xdna = ndev->aie.xdna; + int ret; + + req.partition_id = ndev->partition_id; + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) + XDNA_ERR(xdna, "partition fini failed: %d", ret); +} + +static int aie4_query(struct amdxdna_dev_hdl *ndev) +{ + return aie4_query_aie_metadata(ndev, &ndev->aie.metadata); +} + +static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev) +{ + int ret; + + ret = aie4_fw_start(ndev); + if (ret) + return ret; + + ret = aie4_mailbox_init(ndev); + if (ret) + goto stop_fw; + + ret = aie4_attach_work_buffer(ndev); + if (ret) + goto mbox_fini; + + return 0; + +mbox_fini: + aie4_mailbox_fini(ndev); +stop_fw: + aie4_fw_stop(ndev); + + return ret; +} + +static void aie4_pf_hw_stop(struct amdxdna_dev_hdl *ndev) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + + drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); + + aie4_suspend_fw(ndev); + aie4_mailbox_fini(ndev); + aie4_fw_stop(ndev); +} + +static int aie4_vf_hw_start(struct amdxdna_dev_hdl *ndev) +{ + int ret; + + ret = aie4_mailbox_init(ndev); + if (ret) + return ret; + + ret = aie4_query(ndev); + if (ret) + goto mailbox_fini; + + ret = aie4_partition_init(ndev); + if (ret) + goto mailbox_fini; + + return 0; + +mailbox_fini: + aie4_mailbox_fini(ndev); + return ret; +} + +static void aie4_vf_hw_stop(struct amdxdna_dev_hdl *ndev) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + + drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); + + aie4_partition_fini(ndev); + aie4_mailbox_fini(ndev); +} + +static int aie4_request_firmware(struct amdxdna_dev_hdl *ndev, + const struct firmware **npufw, + const struct firmware **certfw) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev); + char fw_name[128]; + int ret; + + ret = snprintf(fw_name, sizeof(fw_name), "amdnpu/%04x_%02x/%s", + pdev->device, pdev->revision, ndev->priv->npufw_path); + if (ret >= sizeof(fw_name)) { + XDNA_ERR(xdna, "npu firmware path is truncated"); + return -EINVAL; + } + + ret = request_firmware(npufw, fw_name, &pdev->dev); + if (ret) { + XDNA_ERR(xdna, "failed to request_firmware %s, ret %d", fw_name, ret); + return ret; + } + + ret = snprintf(fw_name, sizeof(fw_name), "amdnpu/%04x_%02x/%s", + pdev->device, pdev->revision, ndev->priv->certfw_path); + if (ret >= sizeof(fw_name)) { + XDNA_ERR(xdna, "cert firmware path is truncated"); + ret = -EINVAL; + goto release_npufw; + } + + ret = request_firmware(certfw, fw_name, &pdev->dev); + if (ret) { + XDNA_ERR(xdna, "failed to request_firmware %s, ret %d", fw_name, ret); + goto release_npufw; + } + + return 0; + +release_npufw: + release_firmware(*npufw); + + return ret; +} + +static void aie4_release_firmware(struct amdxdna_dev_hdl *ndev, + const struct firmware *npufw, + const struct firmware *certfw) +{ + release_firmware(certfw); + release_firmware(npufw); +} + +static int aie4_prepare_firmware(struct amdxdna_dev_hdl *ndev, + const struct firmware *npufw, + const struct firmware *certfw, + void __iomem *tbl[PCI_NUM_RESOURCES]) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + struct psp_config psp_conf; + struct smu_config smu_conf; + int i; + + psp_conf.fw_size = npufw->size; + psp_conf.fw_buf = npufw->data; + psp_conf.certfw_size = certfw->size; + psp_conf.certfw_buf = certfw->data; + psp_conf.arg2_mask = ~0; + psp_conf.notify_val = PSP_NOTIFY_INTR; + for (i = 0; i < PSP_MAX_REGS; i++) + psp_conf.psp_regs[i] = tbl[PSP_REG_BAR(ndev, i)] + PSP_REG_OFF(ndev, i); + ndev->aie.psp_hdl = aiem_psp_create(&xdna->ddev, &psp_conf); + if (!ndev->aie.psp_hdl) { + XDNA_ERR(xdna, "failed to create psp"); + return -ENOMEM; + } + + for (i = 0; i < SMU_MAX_REGS; i++) + smu_conf.smu_regs[i] = tbl[SMU_REG_BAR(ndev, i)] + SMU_REG_OFF(ndev, i); + ndev->aie.smu_hdl = aiem_smu_create(&xdna->ddev, &smu_conf); + if (!ndev->aie.smu_hdl) { + XDNA_ERR(xdna, "failed to create smu"); + return -ENOMEM; + } + + return 0; +} + +static int aie4_load_fw(struct amdxdna_dev_hdl *ndev, + void __iomem *tbl[PCI_NUM_RESOURCES]) +{ + const struct firmware *npufw, *certfw; + int ret; + + if (!ndev->priv->npufw_path && !ndev->priv->certfw_path) + return 0; + + ret = aie4_request_firmware(ndev, &npufw, &certfw); + if (ret) + return ret; + + ret = aie4_prepare_firmware(ndev, npufw, certfw, tbl); + aie4_release_firmware(ndev, npufw, certfw); + + return ret; +} + +static int aie4m_pcidev_init(struct amdxdna_dev *xdna) +{ + struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev); + struct amdxdna_dev_hdl *ndev; + void __iomem *tbl[PCI_NUM_RESOURCES] = {0}; + unsigned long bars = 0; + int ret, i; + + ndev = drmm_kzalloc(&xdna->ddev, sizeof(*ndev), GFP_KERNEL); + if (!ndev) + return -ENOMEM; + + ndev->priv = xdna->dev_info->dev_priv; + ndev->aie.xdna = xdna; + xdna->dev_handle = ndev; + + xa_init_flags(&ndev->cert_comp_xa, XA_FLAGS_ALLOC); + mutex_init(&ndev->cert_comp_lock); + + /* Enable managed PCI device */ + ret = pcim_enable_device(pdev); + if (ret) { + XDNA_ERR(xdna, "pcim enable device failed, ret %d", ret); + return ret; + } + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (ret) { + XDNA_ERR(xdna, "failed to set DMA mask to 64:%d", ret); + return ret; + } + + for (i = 0; i < PSP_MAX_REGS; i++) + set_bit(PSP_REG_BAR(ndev, i), &bars); + for (i = 0; i < SMU_MAX_REGS; i++) + set_bit(SMU_REG_BAR(ndev, i), &bars); + set_bit(xdna->dev_info->mbox_bar, &bars); + set_bit(xdna->dev_info->sram_bar, &bars); + + for (i = 0; i < PCI_NUM_RESOURCES; i++) { + if (!test_bit(i, &bars)) + continue; + tbl[i] = pcim_iomap(pdev, i, 0); + if (!tbl[i]) { + XDNA_ERR(xdna, "map bar %d failed", i); + return -ENOMEM; + } + } + + ndev->mbox_base = tbl[xdna->dev_info->mbox_bar]; + ndev->rbuf_base = tbl[xdna->dev_info->sram_bar]; + + pci_set_master(pdev); + + ret = aie4_load_fw(ndev, tbl); + if (ret) + return ret; + + ret = aie4_irq_init(xdna); + if (ret) + return ret; + + amdxdna_vbnv_init(xdna); + XDNA_DBG(xdna, "init finished"); + + return 0; +} + +static int aie4_doorbell_mmap(struct amdxdna_client *client, struct vm_area_struct *vma) +{ + struct amdxdna_dev *xdna = client->xdna; + struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev); + const struct amdxdna_dev_priv *npriv = xdna->dev_info->dev_priv; + phys_addr_t res_start; + unsigned long pfn; + int ret; + + if (!aie4_hwctx_valid_doorbell(client, vma->vm_pgoff)) { + XDNA_ERR(xdna, "Invalid doorbell page offset 0x%lx", vma->vm_pgoff); + return -EINVAL; + } + + if (vma_pages(vma) != 1) { + XDNA_ERR(xdna, "can only map one page, got %ld", vma_pages(vma)); + return -EINVAL; + } + + res_start = pci_resource_start(pdev, xdna->dev_info->doorbell_bar) + npriv->doorbell_off; + pfn = PHYS_PFN(res_start) + vma->vm_pgoff; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + vm_flags_set(vma, VM_IO | VM_DONTEXPAND | VM_DONTDUMP); + ret = io_remap_pfn_range(vma, vma->vm_start, + pfn, + PAGE_SIZE, + vma->vm_page_prot); + + XDNA_DBG(xdna, "doorbell ret %d", ret); + return ret; +} + +static int aie4_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args) +{ + struct amdxdna_dev *xdna = client->xdna; + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; + int ret; + + switch (args->param) { + case DRM_AMDXDNA_QUERY_AIE_METADATA: + ret = amdxdna_get_metadata(&ndev->aie, client, args); + break; + default: + XDNA_ERR(xdna, "Not supported request parameter %u", args->param); + ret = -EOPNOTSUPP; + } + + XDNA_DBG(xdna, "Got param %d", args->param); + + return ret; +} + +static int aie4_alloc_work_buffer(struct amdxdna_dev_hdl *ndev) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + u32 buf_size = AIE4_WORK_BUFFER_MIN_SIZE; + + ndev->work_buf = amdxdna_alloc_msg_buffer(xdna, &buf_size, + &ndev->work_buf_addr); + if (IS_ERR(ndev->work_buf)) { + int ret = PTR_ERR(ndev->work_buf); + + XDNA_ERR(xdna, "Failed to alloc work buffer, size 0x%x", + AIE4_WORK_BUFFER_MIN_SIZE); + ndev->work_buf = NULL; + return ret; + } + + ndev->work_buf_size = buf_size; + XDNA_DBG(xdna, "Work buffer allocated: size 0x%x", buf_size); + + return 0; +} + +static void aie4_free_work_buffer(struct amdxdna_dev_hdl *ndev) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + + if (!ndev->work_buf) + return; + + amdxdna_free_msg_buffer(xdna, ndev->work_buf_size, ndev->work_buf, + ndev->work_buf_addr); + ndev->work_buf = NULL; +} + +static int aie4_pf_init(struct amdxdna_dev *xdna) +{ + int ret; + + ret = aie4m_pcidev_init(xdna); + if (ret) + return ret; + + ret = aie4_alloc_work_buffer(xdna->dev_handle); + if (ret) + return ret; + + ret = aie4_pf_hw_start(xdna->dev_handle); + if (ret) + goto free_work_buf; + + return 0; + +free_work_buf: + aie4_free_work_buffer(xdna->dev_handle); + return ret; +} + +static int aie4_vf_init(struct amdxdna_dev *xdna) +{ + int ret; + + ret = aie4m_pcidev_init(xdna); + if (ret) + return ret; + + return aie4_vf_hw_start(xdna->dev_handle); +} + +static void aie4_pf_fini(struct amdxdna_dev *xdna) +{ + aie4_sriov_stop(xdna->dev_handle); + aie4_pf_hw_stop(xdna->dev_handle); + aie4_free_work_buffer(xdna->dev_handle); +} + +static void aie4_vf_fini(struct amdxdna_dev *xdna) +{ + aie4_vf_hw_stop(xdna->dev_handle); +} + +const struct amdxdna_dev_ops aie4_pf_ops = { + .init = aie4_pf_init, + .fini = aie4_pf_fini, + .sriov_configure = aie4_sriov_configure, +}; + +const struct amdxdna_dev_ops aie4_vf_ops = { + .init = aie4_vf_init, + .fini = aie4_vf_fini, + .hwctx_init = aie4_hwctx_init, + .hwctx_fini = aie4_hwctx_fini, + .mmap = aie4_doorbell_mmap, + .cmd_wait = aie4_cmd_wait, + .get_aie_info = aie4_get_info, +}; diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h new file mode 100644 index 000000000000..3fd5eace3ed7 --- /dev/null +++ b/drivers/accel/amdxdna/aie4_pci.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _AIE4_PCI_H_ +#define _AIE4_PCI_H_ + +#include +#include +#include + +#include "aie.h" +#include "amdxdna_mailbox.h" + +struct cert_comp { + struct amdxdna_dev_hdl *ndev; + u32 msix_idx; + int irq; + struct kref kref; + wait_queue_head_t waitq; +}; + +struct amdxdna_hwctx_priv { + struct amdxdna_gem_obj *umq_bo; + u64 *umq_read_index; + u64 *umq_write_index; + + struct cert_comp *cert_comp; + u32 hw_ctx_id; +}; + +struct amdxdna_dev_priv { + const char *npufw_path; + const char *certfw_path; + u32 mbox_bar; + u32 mbox_rbuf_bar; + u64 mbox_info_off; + u32 doorbell_off; + + struct aie_bar_off_pair psp_regs_off[PSP_MAX_REGS]; + struct aie_bar_off_pair smu_regs_off[SMU_MAX_REGS]; +}; + +struct amdxdna_dev_hdl { + struct aie_device aie; + const struct amdxdna_dev_priv *priv; + void __iomem *mbox_base; + void __iomem *rbuf_base; + + struct mailbox *mbox; + u32 partition_id; + + struct xarray cert_comp_xa; /* device level indexed by msix id */ + struct mutex cert_comp_lock; /* protects cert_comp operations*/ + + void *work_buf; + dma_addr_t work_buf_addr; + u32 work_buf_size; +}; + +/* aie4_message.c */ +int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev, + struct amdxdna_drm_query_aie_metadata *metadata); +int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev); +int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev); + +/* aie4_ctx.c */ +int aie4_hwctx_init(struct amdxdna_hwctx *hwctx); +void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx); +int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout); +int aie4_hwctx_valid_doorbell(struct amdxdna_client *client, u32 vm_pgoff); + +/* aie4_sriov.c */ +#if IS_ENABLED(CONFIG_PCI_IOV) +int aie4_sriov_configure(struct amdxdna_dev *xdna, int num_vfs); +int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev); +#else +#define aie4_sriov_configure NULL +static inline int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev) +{ + return 0; +} +#endif + +extern const struct amdxdna_dev_ops aie4_pf_ops; +extern const struct amdxdna_dev_ops aie4_vf_ops; + +#endif /* _AIE4_PCI_H_ */ diff --git a/drivers/accel/amdxdna/aie4_sriov.c b/drivers/accel/amdxdna/aie4_sriov.c new file mode 100644 index 000000000000..e1ce633768a5 --- /dev/null +++ b/drivers/accel/amdxdna/aie4_sriov.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include +#include +#include + +#include "aie.h" +#include "aie4_msg_priv.h" +#include "aie4_pci.h" +#include "amdxdna_mailbox.h" +#include "amdxdna_mailbox_helper.h" +#include "amdxdna_pci_drv.h" + +static int aie4_destroy_vfs(struct amdxdna_dev_hdl *ndev) +{ + DECLARE_AIE_MSG(aie4_msg_destroy_vfs, AIE4_MSG_OP_DESTROY_VFS); + int ret; + + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) + XDNA_ERR(ndev->aie.xdna, "destroy vfs op failed: %d", ret); + + return ret; +} + +static int aie4_create_vfs(struct amdxdna_dev_hdl *ndev, int num_vfs) +{ + DECLARE_AIE_MSG(aie4_msg_create_vfs, AIE4_MSG_OP_CREATE_VFS); + int ret; + + req.vf_cnt = num_vfs; + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) + XDNA_ERR(ndev->aie.xdna, "create vfs op failed: %d", ret); + + return ret; +} + +int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev); + int ret; + + if (!pci_num_vf(pdev)) + return 0; + + ret = pci_vfs_assigned(pdev); + if (ret) { + XDNA_ERR(xdna, "VFs are still assigned to VMs"); + return -EPERM; + } + + pci_disable_sriov(pdev); + return aie4_destroy_vfs(ndev); +} + +static int aie4_sriov_start(struct amdxdna_dev_hdl *ndev, int num_vfs) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev); + int ret; + + ret = aie4_create_vfs(ndev, num_vfs); + if (ret) + return ret; + + ret = pci_enable_sriov(pdev, num_vfs); + if (ret) { + XDNA_ERR(xdna, "configure VFs failed, ret: %d", ret); + aie4_destroy_vfs(ndev); + return ret; + } + + return num_vfs; +} + +int aie4_sriov_configure(struct amdxdna_dev *xdna, int num_vfs) +{ + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; + + drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); + + return (num_vfs) ? aie4_sriov_start(ndev, num_vfs) : aie4_sriov_stop(ndev); +} diff --git a/drivers/accel/amdxdna/aie_psp.c b/drivers/accel/amdxdna/aie_psp.c new file mode 100644 index 000000000000..458dca7cc5a0 --- /dev/null +++ b/drivers/accel/amdxdna/aie_psp.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include "aie.h" + +#define PSP_STATUS_READY BIT(31) + +/* PSP commands */ +#define PSP_VALIDATE 1 +#define PSP_START 2 +#define PSP_RELEASE_TMR 3 +#define PSP_VALIDATE_CERT 4 + +/* PSP special arguments */ +#define PSP_START_COPY_FW 1 + +/* PSP response error code */ +#define PSP_ERROR_CANCEL 0xFFFF0002 +#define PSP_ERROR_BAD_STATE 0xFFFF0007 + +#define PSP_FW_ALIGN 0x10000 +#define PSP_CFW_ALIGN 0x8000 +#define PSP_POLL_INTERVAL 20000 /* us */ +#define PSP_POLL_TIMEOUT 1000000 /* us */ + +#define PSP_REG(p, reg) ((p)->conf.psp_regs[reg]) +#define PSP_SET_CMD(psp, reg_vals, cmd, arg0, arg1, arg2) \ +({ \ + u32 *_regs = reg_vals; \ + u32 _cmd = cmd; \ + _regs[0] = _cmd; \ + _regs[1] = arg0; \ + _regs[2] = arg1; \ + _regs[3] = ((arg2) | ((_cmd) << 24)) & (psp)->conf.arg2_mask; \ +}) + +struct psp_device { + struct drm_device *ddev; + struct psp_config conf; + u32 fw_buf_sz; + u64 fw_paddr; + void *fw_buffer; + u32 certfw_buf_sz; + u64 certfw_paddr; + void *certfw_buffer; +}; + +static int psp_exec(struct psp_device *psp, u32 *reg_vals) +{ + u32 resp_code; + int ret, i; + u32 ready; + + /* Check for PSP ready before any write */ + ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_STATUS_REG), ready, + FIELD_GET(PSP_STATUS_READY, ready), + PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT); + if (ret) { + drm_err(psp->ddev, "PSP is not ready, ret 0x%x", ret); + return ret; + } + + /* Write command and argument registers */ + for (i = 0; i < PSP_NUM_IN_REGS; i++) + writel(reg_vals[i], PSP_REG(psp, i)); + + /* clear and set PSP INTR register to kick off */ + writel(0, PSP_REG(psp, PSP_INTR_REG)); + writel(psp->conf.notify_val, PSP_REG(psp, PSP_INTR_REG)); + + /* PSP should be busy. Wait for ready, so we know task is done. */ + ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_STATUS_REG), ready, + FIELD_GET(PSP_STATUS_READY, ready), + PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT); + if (ret) { + drm_err(psp->ddev, "PSP is not ready, ret 0x%x", ret); + return ret; + } + + resp_code = readl(PSP_REG(psp, PSP_RESP_REG)); + if (resp_code) { + drm_err(psp->ddev, "fw return error 0x%x", resp_code); + return -EIO; + } + + return 0; +} + +int aie_psp_waitmode_poll(struct psp_device *psp) +{ + struct amdxdna_dev *xdna = to_xdna_dev(psp->ddev); + u32 mode_reg; + int ret; + + ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_PWAITMODE_REG), mode_reg, + (mode_reg & 0x1) == 1, + PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT); + if (ret) + XDNA_ERR(xdna, "fw waitmode reg error, ret %d", ret); + + return ret; +} + +void aie_psp_stop(struct psp_device *psp) +{ + u32 reg_vals[PSP_NUM_IN_REGS]; + int ret; + + PSP_SET_CMD(psp, reg_vals, PSP_RELEASE_TMR, 0, 0, 0); + + ret = psp_exec(psp, reg_vals); + if (ret) + drm_err(psp->ddev, "release tmr failed, ret %d", ret); +} + +static int psp_validate_fw(struct psp_device *psp, u8 cmd, u64 paddr, u32 buf_sz) +{ + u32 reg_vals[PSP_NUM_IN_REGS]; + int ret; + + PSP_SET_CMD(psp, reg_vals, cmd, lower_32_bits(paddr), + upper_32_bits(paddr), buf_sz); + + ret = psp_exec(psp, reg_vals); + if (ret) + drm_err(psp->ddev, "failed to validate fw, ret %d", ret); + + return ret; +} + +static int psp_start(struct psp_device *psp) +{ + u32 reg_vals[PSP_NUM_IN_REGS]; + int ret; + + PSP_SET_CMD(psp, reg_vals, PSP_START, PSP_START_COPY_FW, 0, 0); + + ret = psp_exec(psp, reg_vals); + if (ret) + drm_err(psp->ddev, "failed to start fw, ret %d", ret); + + return ret; +} + +int aie_psp_start(struct psp_device *psp) +{ + int ret; + + ret = psp_validate_fw(psp, PSP_VALIDATE, + psp->fw_paddr, psp->fw_buf_sz); + if (ret) + return ret; + + if (!psp->certfw_buf_sz) + goto psp_start; + + ret = psp_validate_fw(psp, PSP_VALIDATE_CERT, + psp->certfw_paddr, psp->certfw_buf_sz); + if (ret) + return ret; +psp_start: + return psp_start(psp); +} + +/* + * PSP requires host physical address to load firmware. + * Allocate a buffer, obtain its physical address, align, and copy data in. + */ +static void *psp_alloc_fw_buf(struct psp_device *psp, const void *fw_data, + u32 fw_size, u32 align, u32 *buf_sz, + u64 *paddr) +{ + u32 alloc_sz; + void *buffer; + u64 offset; + + *buf_sz = ALIGN(fw_size, align); + alloc_sz = *buf_sz + align; + + buffer = drmm_kmalloc(psp->ddev, alloc_sz, GFP_KERNEL); + if (!buffer) + return NULL; + + *paddr = virt_to_phys(buffer); + offset = ALIGN(*paddr, align) - *paddr; + *paddr += offset; + memcpy(buffer + offset, fw_data, fw_size); + + return buffer; +} + +struct psp_device *aiem_psp_create(struct drm_device *ddev, struct psp_config *conf) +{ + struct psp_device *psp; + + psp = drmm_kzalloc(ddev, sizeof(*psp), GFP_KERNEL); + if (!psp) + return NULL; + + psp->ddev = ddev; + psp->fw_buffer = psp_alloc_fw_buf(psp, conf->fw_buf, conf->fw_size, + PSP_FW_ALIGN, &psp->fw_buf_sz, + &psp->fw_paddr); + if (!psp->fw_buffer) + return NULL; + + if (!conf->certfw_size) { + drm_dbg(ddev, "no cert fw"); + goto done; + } + + /* CERT firmware */ + psp->certfw_buffer = psp_alloc_fw_buf(psp, conf->certfw_buf, + conf->certfw_size, PSP_CFW_ALIGN, + &psp->certfw_buf_sz, + &psp->certfw_paddr); + if (!psp->certfw_buffer) { + drm_err(ddev, "no memory for cert fw buffer"); + return NULL; + } + +done: + memcpy(&psp->conf, conf, sizeof(psp->conf)); + + return psp; +} diff --git a/drivers/accel/amdxdna/aie_smu.c b/drivers/accel/amdxdna/aie_smu.c new file mode 100644 index 000000000000..62aea550aabc --- /dev/null +++ b/drivers/accel/amdxdna/aie_smu.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include "drm/amdxdna_accel.h" +#include +#include +#include +#include +#include + +#include "aie.h" + +#define SMU_RESULT_OK 1 + +/* SMU commands */ +#define AIE_SMU_POWER_ON 0x3 +#define AIE_SMU_POWER_OFF 0x4 +#define AIE_SMU_SET_MPNPUCLK_FREQ 0x5 +#define AIE_SMU_SET_HCLK_FREQ 0x6 +#define AIE_SMU_SET_SOFT_DPMLEVEL 0x7 +#define AIE_SMU_SET_HARD_DPMLEVEL 0x8 + +#define SMU_REG(s, reg) ((s)->smu_regs[reg]) + +struct smu_device { + struct drm_device *ddev; + struct smu_config conf; + void __iomem *smu_regs[SMU_MAX_REGS]; +}; + +static int aie_smu_exec(struct smu_device *smu, u32 reg_cmd, u32 reg_arg, u32 *out) +{ + u32 resp; + int ret; + + writel(0, SMU_REG(smu, SMU_RESP_REG)); + writel(reg_arg, SMU_REG(smu, SMU_ARG_REG)); + writel(reg_cmd, SMU_REG(smu, SMU_CMD_REG)); + + /* Clear and set SMU_INTR_REG to kick off */ + writel(0, SMU_REG(smu, SMU_INTR_REG)); + writel(1, SMU_REG(smu, SMU_INTR_REG)); + + ret = readx_poll_timeout(readl, SMU_REG(smu, SMU_RESP_REG), resp, + resp, AIE_INTERVAL, AIE_TIMEOUT); + if (ret) { + drm_err(smu->ddev, "smu cmd %d timed out", reg_cmd); + return ret; + } + + if (out) + *out = readl(SMU_REG(smu, SMU_OUT_REG)); + + if (resp != SMU_RESULT_OK) { + drm_err(smu->ddev, "smu cmd %d failed, 0x%x", reg_cmd, resp); + return -EINVAL; + } + + return 0; +} + +int aie_smu_init(struct smu_device *smu) +{ + int ret; + + /* + * Failing to set power off indicates an unrecoverable hardware or + * firmware error. + */ + ret = aie_smu_exec(smu, AIE_SMU_POWER_OFF, 0, NULL); + if (ret) { + drm_err(smu->ddev, "Access power failed, ret %d", ret); + return ret; + } + + ret = aie_smu_exec(smu, AIE_SMU_POWER_ON, 0, NULL); + if (ret) { + drm_err(smu->ddev, "Power on failed, ret %d", ret); + return ret; + } + + return 0; +} + +void aie_smu_fini(struct smu_device *smu) +{ + int ret; + + ret = aie_smu_exec(smu, AIE_SMU_POWER_OFF, 0, NULL); + if (ret) + drm_err(smu->ddev, "Power off failed, ret %d", ret); +} + +int aie_smu_set_clocks(struct smu_device *smu, u32 *npuclk, u32 *hclk) +{ + int ret; + + if (npuclk) { + ret = aie_smu_exec(smu, AIE_SMU_SET_MPNPUCLK_FREQ, *npuclk, npuclk); + if (ret) { + drm_err(smu->ddev, "Set mpnpu clock to %d failed, ret %d", *npuclk, ret); + return ret; + } + } + + if (hclk) { + ret = aie_smu_exec(smu, AIE_SMU_SET_HCLK_FREQ, *hclk, hclk); + if (ret) { + drm_err(smu->ddev, "Set hclock to %d failed, ret %d", + *hclk, ret); + return ret; + } + } + + return 0; +} + +int aie_smu_set_dpm(struct smu_device *smu, u32 dpm_level) +{ + int ret; + + ret = aie_smu_exec(smu, AIE_SMU_SET_HARD_DPMLEVEL, dpm_level, NULL); + if (ret) { + drm_err(smu->ddev, "Set hard dpm level %d failed, ret %d", + dpm_level, ret); + return ret; + } + + ret = aie_smu_exec(smu, AIE_SMU_SET_SOFT_DPMLEVEL, dpm_level, NULL); + if (ret) { + drm_err(smu->ddev, "Set soft dpm level %d failed, ret %d", + dpm_level, ret); + return ret; + } + + return 0; +} + +struct smu_device *aiem_smu_create(struct drm_device *ddev, struct smu_config *conf) +{ + struct smu_device *smu; + + smu = drmm_kzalloc(ddev, sizeof(*smu), GFP_KERNEL); + if (!smu) + return NULL; + + smu->ddev = ddev; + memcpy(smu->smu_regs, conf->smu_regs, sizeof(smu->smu_regs)); + + return smu; +} diff --git a/drivers/accel/amdxdna/amdxdna_cbuf.c b/drivers/accel/amdxdna/amdxdna_cbuf.c new file mode 100644 index 000000000000..a504560aae98 --- /dev/null +++ b/drivers/accel/amdxdna/amdxdna_cbuf.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include +#include + +#include "amdxdna_cbuf.h" +#include "amdxdna_pci_drv.h" + +/* + * Carveout memory is a chunk of memory which is physically contiguous and + * is reserved during early boot time. There is only one chunk of such memory + * per device. Once available, all BOs accessible from device should be + * allocated from this memory. This is a platform debug/bringup feature. + */ +struct amdxdna_carveout { + u64 addr; + u64 size; + struct drm_mm mm; + struct mutex lock; /* protect mm */ +}; + +bool amdxdna_use_carveout(struct amdxdna_dev *xdna) +{ + return !!xdna->carveout; +} + +void amdxdna_get_carveout_conf(struct amdxdna_dev *xdna, u64 *addr, u64 *size) +{ + if (amdxdna_use_carveout(xdna)) { + *addr = xdna->carveout->addr; + *size = xdna->carveout->size; + } else { + *addr = 0; + *size = 0; + } +} + +int amdxdna_carveout_init(struct amdxdna_dev *xdna, u64 carveout_addr, u64 carveout_size) +{ + struct amdxdna_carveout *carveout; + + /* Only allow carveout memory to be set up once. */ + if (amdxdna_use_carveout(xdna)) { + XDNA_ERR(xdna, "Carveout memory has already been set up."); + return -EBUSY; + } + + carveout = kzalloc_obj(*carveout); + if (!carveout) + return -ENOMEM; + + carveout->addr = carveout_addr; + carveout->size = carveout_size; + mutex_init(&carveout->lock); + drm_mm_init(&carveout->mm, carveout->addr, carveout->size); + + xdna->carveout = carveout; + XDNA_INFO(xdna, "Use carveout mem: 0x%llx@0x%llx\n", carveout->size, carveout->addr); + return 0; +} + +void amdxdna_carveout_fini(struct amdxdna_dev *xdna) +{ + struct amdxdna_carveout *carveout = xdna->carveout; + + if (!amdxdna_use_carveout(xdna)) + return; + + XDNA_INFO(xdna, "Cleanup carveout mem: 0x%llx@0x%llx\n", carveout->size, carveout->addr); + drm_mm_takedown(&carveout->mm); + mutex_destroy(&carveout->lock); + kfree(carveout); + xdna->carveout = NULL; +} + +struct amdxdna_cbuf_priv { + struct amdxdna_dev *xdna; + struct drm_mm_node node; +}; + +static struct sg_table *amdxdna_cbuf_map(struct dma_buf_attachment *attach, + enum dma_data_direction direction) +{ + struct amdxdna_cbuf_priv *cbuf = attach->dmabuf->priv; + struct device *dev = attach->dev; + struct scatterlist *sgl, *sg; + int ret, n_entries, i; + struct sg_table *sgt; + dma_addr_t dma_addr; + size_t dma_size; + size_t max_seg; + + sgt = kzalloc_obj(*sgt); + if (!sgt) + return ERR_PTR(-ENOMEM); + + max_seg = min_t(size_t, UINT_MAX, dma_max_mapping_size(dev)); + n_entries = (cbuf->node.size + max_seg - 1) / max_seg; + sgl = kzalloc_objs(*sg, n_entries); + if (!sgl) { + ret = -ENOMEM; + goto free_sgt; + } + sg_init_table(sgl, n_entries); + sgt->orig_nents = n_entries; + sgt->nents = n_entries; + sgt->sgl = sgl; + + dma_size = cbuf->node.size; + dma_addr = dma_map_resource(dev, cbuf->node.start, dma_size, + direction, DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(dev, dma_addr); + if (ret) { + pr_err("Failed to dma_map_resource carveout dma buf, ret %d\n", ret); + goto free_sgl; + } + + for_each_sgtable_dma_sg(sgt, sg, i) { + size_t len = min_t(size_t, max_seg, dma_size); + + sg_dma_address(sg) = dma_addr; + sg_dma_len(sg) = len; + dma_addr += len; + dma_size -= len; + } + + return sgt; + +free_sgl: + kfree(sgl); +free_sgt: + kfree(sgt); + return ERR_PTR(ret); +} + +static void amdxdna_cbuf_unmap(struct dma_buf_attachment *attach, + struct sg_table *sgt, + enum dma_data_direction direction) +{ + dma_unmap_resource(attach->dev, sg_dma_address(sgt->sgl), + drm_prime_get_contiguous_size(sgt), direction, + DMA_ATTR_SKIP_CPU_SYNC); + sg_free_table(sgt); + kfree(sgt); +} + +static void amdxdna_cbuf_release(struct dma_buf *dbuf) +{ + struct amdxdna_cbuf_priv *cbuf = dbuf->priv; + struct amdxdna_carveout *carveout; + + carveout = cbuf->xdna->carveout; + mutex_lock(&carveout->lock); + drm_mm_remove_node(&cbuf->node); + mutex_unlock(&carveout->lock); + + kfree(cbuf); +} + +static vm_fault_t amdxdna_cbuf_vm_fault(struct vm_fault *vmf) +{ + struct vm_area_struct *vma = vmf->vma; + struct amdxdna_cbuf_priv *cbuf; + unsigned long pfn; + pgoff_t pgoff; + + cbuf = vma->vm_private_data; + pgoff = (vmf->address - vma->vm_start) >> PAGE_SHIFT; + pfn = (cbuf->node.start >> PAGE_SHIFT) + pgoff; + + return vmf_insert_pfn(vma, vmf->address, pfn); +} + +static const struct vm_operations_struct amdxdna_cbuf_vm_ops = { + .fault = amdxdna_cbuf_vm_fault, +}; + +static int amdxdna_cbuf_mmap(struct dma_buf *dbuf, struct vm_area_struct *vma) +{ + struct amdxdna_cbuf_priv *cbuf = dbuf->priv; + + vma->vm_ops = &amdxdna_cbuf_vm_ops; + vma->vm_private_data = cbuf; + vm_flags_set(vma, VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP); + + return 0; +} + +static int amdxdna_cbuf_vmap(struct dma_buf *dbuf, struct iosys_map *map) +{ + struct amdxdna_cbuf_priv *cbuf = dbuf->priv; + void *kva; + + kva = memremap(cbuf->node.start, cbuf->node.size, MEMREMAP_WB); + if (!kva) { + pr_err("Failed to vmap carveout dma buf\n"); + return -ENOMEM; + } + + iosys_map_set_vaddr(map, kva); + return 0; +} + +static void amdxdna_cbuf_vunmap(struct dma_buf *dbuf, struct iosys_map *map) +{ + memunmap(map->vaddr); +} + +static const struct dma_buf_ops amdxdna_cbuf_dmabuf_ops = { + .map_dma_buf = amdxdna_cbuf_map, + .unmap_dma_buf = amdxdna_cbuf_unmap, + .release = amdxdna_cbuf_release, + .mmap = amdxdna_cbuf_mmap, + .vmap = amdxdna_cbuf_vmap, + .vunmap = amdxdna_cbuf_vunmap, +}; + +static int amdxdna_cbuf_clear(struct dma_buf *dbuf) +{ + struct iosys_map vmap = IOSYS_MAP_INIT_VADDR(NULL); + + dma_buf_vmap(dbuf, &vmap); + if (!vmap.vaddr) + return -EFAULT; + + memset(vmap.vaddr, 0, dbuf->size); + dma_buf_vunmap(dbuf, &vmap); + + return 0; +} + +struct dma_buf *amdxdna_get_cbuf(struct drm_device *dev, size_t size, u64 alignment) +{ + struct amdxdna_dev *xdna = to_xdna_dev(dev); + DEFINE_DMA_BUF_EXPORT_INFO(exp_info); + struct amdxdna_carveout *carveout; + struct amdxdna_cbuf_priv *cbuf; + struct dma_buf *dbuf; + int ret; + + cbuf = kzalloc_obj(*cbuf); + if (!cbuf) + return ERR_PTR(-ENOMEM); + cbuf->xdna = xdna; + + carveout = xdna->carveout; + mutex_lock(&carveout->lock); + ret = drm_mm_insert_node_generic(&carveout->mm, &cbuf->node, size, + alignment, 0, DRM_MM_INSERT_BEST); + mutex_unlock(&carveout->lock); + if (ret) + goto free_cbuf; + + exp_info.size = size; + exp_info.ops = &amdxdna_cbuf_dmabuf_ops; + exp_info.priv = cbuf; + exp_info.flags = O_RDWR; + dbuf = dma_buf_export(&exp_info); + if (IS_ERR(dbuf)) { + ret = PTR_ERR(dbuf); + goto remove_node; + } + + ret = amdxdna_cbuf_clear(dbuf); + if (ret) { + dma_buf_put(dbuf); + goto out; + } + return dbuf; + +remove_node: + drm_mm_remove_node(&cbuf->node); +free_cbuf: + kfree(cbuf); +out: + return ERR_PTR(ret); +} diff --git a/drivers/accel/amdxdna/amdxdna_cbuf.h b/drivers/accel/amdxdna/amdxdna_cbuf.h new file mode 100644 index 000000000000..8e89336ffd50 --- /dev/null +++ b/drivers/accel/amdxdna/amdxdna_cbuf.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ +#ifndef _AMDXDNA_CBUF_H_ +#define _AMDXDNA_CBUF_H_ + +#include "amdxdna_pci_drv.h" +#include +#include + +bool amdxdna_use_carveout(struct amdxdna_dev *xdna); +int amdxdna_carveout_init(struct amdxdna_dev *xdna, u64 carveout_addr, u64 carveout_size); +void amdxdna_carveout_fini(struct amdxdna_dev *xdna); +void amdxdna_get_carveout_conf(struct amdxdna_dev *xdna, u64 *addr, u64 *size); +struct dma_buf *amdxdna_get_cbuf(struct drm_device *dev, size_t size, u64 alignment); + +#endif diff --git a/drivers/accel/amdxdna/amdxdna_ctx.c b/drivers/accel/amdxdna/amdxdna_ctx.c index ff6c3e8e5a15..855da8c79a1c 100644 --- a/drivers/accel/amdxdna/amdxdna_ctx.c +++ b/drivers/accel/amdxdna/amdxdna_ctx.c @@ -61,16 +61,35 @@ static struct dma_fence *amdxdna_fence_create(struct amdxdna_hwctx *hwctx) return &fence->base; } +static void amdxdna_hwctx_release_expanded_heap(struct amdxdna_hwctx *hwctx) +{ + struct amdxdna_client *client = hwctx->client; + struct amdxdna_gem_obj *heap; + unsigned long heap_id; + + mutex_lock(&client->mm_lock); + if (hwctx->last_attached_heap) { + xa_for_each_range(&client->dev_heap_xa, heap_id, heap, 1, + hwctx->last_attached_heap) { + amdxdna_gem_unpin(heap); + drm_gem_object_put(to_gobj(heap)); + } + } + mutex_unlock(&client->mm_lock); +} + static void amdxdna_hwctx_destroy_rcu(struct amdxdna_hwctx *hwctx, struct srcu_struct *ss) { - struct amdxdna_dev *xdna = hwctx->client->xdna; + struct amdxdna_client *client = hwctx->client; + struct amdxdna_dev *xdna = client->xdna; synchronize_srcu(ss); /* At this point, user is not able to submit new commands */ xdna->dev_info->ops->hwctx_fini(hwctx); + amdxdna_hwctx_release_expanded_heap(hwctx); kfree(hwctx->name); kfree(hwctx); } @@ -207,6 +226,9 @@ int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct dr if (args->ext || args->ext_flags) return -EINVAL; + if (!xdna->dev_info->ops->hwctx_init) + return -EOPNOTSUPP; + hwctx = kzalloc_obj(*hwctx); if (!hwctx) return -ENOMEM; @@ -220,6 +242,8 @@ int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct dr hwctx->client = client; hwctx->fw_ctx_id = -1; hwctx->num_tiles = args->num_tiles; + hwctx->umq_bo_hdl = args->umq_bo; + hwctx->doorbell_offset = AMDXDNA_INVALID_DOORBELL_OFFSET; hwctx->mem_size = args->mem_size; hwctx->max_opc = args->max_opc; @@ -233,7 +257,7 @@ int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct dr ret = xdna->dev_info->ops->hwctx_init(hwctx); if (ret) { XDNA_ERR(xdna, "Init hwctx failed, ret %d", ret); - goto dev_exit; + goto release_expanded_heap; } hwctx->name = kasprintf(GFP_KERNEL, "hwctx.%d.%d", client->pid, hwctx->fw_ctx_id); @@ -252,6 +276,7 @@ int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct dr args->handle = hwctx->id; args->syncobj_handle = hwctx->syncobj_hdl; + args->umq_doorbell = hwctx->doorbell_offset; atomic64_set(&hwctx->job_submit_cnt, 0); atomic64_set(&hwctx->job_free_cnt, 0); @@ -263,7 +288,8 @@ int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct dr kfree(hwctx->name); fini_hwctx: xdna->dev_info->ops->hwctx_fini(hwctx); -dev_exit: +release_expanded_heap: + amdxdna_hwctx_release_expanded_heap(hwctx); drm_dev_exit(idx); free_hwctx: kfree(hwctx); @@ -401,6 +427,62 @@ int amdxdna_hwctx_sync_debug_bo(struct amdxdna_client *client, u32 debug_bo_hdl) return ret; } +static int amdxdna_hwctx_expand_heap(struct amdxdna_hwctx *hwctx) +{ + struct amdxdna_client *client = hwctx->client; + struct amdxdna_dev *xdna = client->xdna; + struct amdxdna_gem_obj *heap; + unsigned long heap_id, nid; + int ret = 0; + + nid = hwctx->last_attached_heap + 1; + if (nid == client->dev_heap_nid) + goto out; + + xa_for_each_range(&client->dev_heap_xa, heap_id, heap, + nid, client->dev_heap_nid) { + drm_gem_object_get(to_gobj(heap)); + ret = amdxdna_gem_pin(heap); + if (ret) { + drm_gem_object_put(to_gobj(heap)); + break; + } + + mutex_unlock(&client->mm_lock); + ret = xdna->dev_info->ops->hwctx_heap_expand(hwctx, heap); + mutex_lock(&client->mm_lock); + if (ret) { + amdxdna_gem_unpin(heap); + drm_gem_object_put(to_gobj(heap)); + break; + } + + hwctx->last_attached_heap = heap_id; + } + +out: + return ret; +} + +int amdxdna_update_heap(struct amdxdna_client *client, struct amdxdna_hwctx *hwctx) +{ + unsigned long hwctx_id; + int ret; + + guard(mutex)(&client->mm_lock); + + if (hwctx) + return amdxdna_hwctx_expand_heap(hwctx); + + amdxdna_for_each_hwctx(client, hwctx_id, hwctx) { + ret = amdxdna_hwctx_expand_heap(hwctx); + if (ret) + return ret; + } + + return 0; +} + static void amdxdna_arg_bos_put(struct amdxdna_sched_job *job) { @@ -514,7 +596,6 @@ int amdxdna_cmd_submit(struct amdxdna_client *client, goto unlock_srcu; } - job->hwctx = hwctx; job->mm = current->mm; @@ -612,6 +693,8 @@ int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_ if (args->ext || args->ext_flags) return -EINVAL; + trace_amdxdna_debug_point(current->comm, args->type, "job received"); + switch (args->type) { case AMDXDNA_CMD_SUBMIT_EXEC_BUF: return amdxdna_drm_submit_execbuf(client, args); @@ -620,3 +703,37 @@ int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_ XDNA_ERR(client->xdna, "Invalid command type %d", args->type); return -EINVAL; } + +int amdxdna_drm_wait_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +{ + struct amdxdna_client *client = filp->driver_priv; + struct amdxdna_dev *xdna = to_xdna_dev(dev); + struct amdxdna_drm_wait_cmd *args = data; + struct amdxdna_hwctx *hwctx; + int ret, idx; + + XDNA_DBG(xdna, "PID %d ctx %d timeout set %d ms for cmd %llu", + client->pid, args->hwctx, args->timeout, args->seq); + + if (!xdna->dev_info->ops->cmd_wait) + return -EOPNOTSUPP; + + idx = srcu_read_lock(&client->hwctx_srcu); + hwctx = xa_load(&client->hwctx_xa, args->hwctx); + if (!hwctx) { + XDNA_DBG(xdna, "PID %d failed to get ctx %d", client->pid, args->hwctx); + ret = -EINVAL; + goto unlock_ctx_srcu; + } + + ret = xdna->dev_info->ops->cmd_wait(hwctx, args->seq, args->timeout); + + XDNA_DBG(xdna, "PID %d ctx %d cmd %lld wait finished, ret %d", + client->pid, args->hwctx, args->seq, ret); + + trace_amdxdna_debug_point(current->comm, args->seq, "job returned to user"); + +unlock_ctx_srcu: + srcu_read_unlock(&client->hwctx_srcu, idx); + return ret; +} diff --git a/drivers/accel/amdxdna/amdxdna_ctx.h b/drivers/accel/amdxdna/amdxdna_ctx.h index a8557d7e8923..aaae16430466 100644 --- a/drivers/accel/amdxdna/amdxdna_ctx.h +++ b/drivers/accel/amdxdna/amdxdna_ctx.h @@ -14,6 +14,7 @@ struct amdxdna_hwctx_priv; enum ert_cmd_opcode { ERT_START_CU = 0, + ERT_START_DPU = 18, ERT_CMD_CHAIN = 19, ERT_START_NPU = 20, ERT_START_NPU_PREEMPT = 21, @@ -105,7 +106,10 @@ struct amdxdna_hwctx { u32 *col_list; u32 start_col; u32 num_col; + u32 umq_bo_hdl; + u32 doorbell_offset; u32 num_unused_col; + u32 last_attached_heap; struct amdxdna_qos_info qos; struct amdxdna_hwctx_param_config_cu *cus; @@ -119,6 +123,7 @@ struct amdxdna_hwctx { container_of(j, struct amdxdna_sched_job, base) enum amdxdna_job_opcode { + DEFAULT_IO, SYNC_DEBUG_BO, ATTACH_DEBUG_BO, DETACH_DEBUG_BO, @@ -201,18 +206,17 @@ void amdxdna_hwctx_remove_all(struct amdxdna_client *client); int amdxdna_hwctx_walk(struct amdxdna_client *client, void *arg, int (*walk)(struct amdxdna_hwctx *hwctx, void *arg)); int amdxdna_hwctx_sync_debug_bo(struct amdxdna_client *client, u32 debug_bo_hdl); +int amdxdna_update_heap(struct amdxdna_client *client, struct amdxdna_hwctx *hwctx); int amdxdna_cmd_submit(struct amdxdna_client *client, struct amdxdna_drv_cmd *drv_cmd, u32 cmd_bo_hdls, u32 *arg_bo_hdls, u32 arg_bo_cnt, u32 hwctx_hdl, u64 *seq); -int amdxdna_cmd_wait(struct amdxdna_client *client, u32 hwctx_hdl, - u64 seq, u32 timeout); - int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdxdna_drm_config_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdxdna_drm_destroy_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +int amdxdna_drm_wait_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); #endif /* _AMDXDNA_CTX_H_ */ diff --git a/drivers/accel/amdxdna/amdxdna_debugfs.c b/drivers/accel/amdxdna/amdxdna_debugfs.c new file mode 100644 index 000000000000..a6ec17c63629 --- /dev/null +++ b/drivers/accel/amdxdna/amdxdna_debugfs.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include "amdxdna_cbuf.h" +#include "amdxdna_debugfs.h" + +#include +#include +#include +#include +#include +#include + +#define _DBGFS_FOPS(_open, _release, _write) \ +{ \ + .owner = THIS_MODULE, \ + .open = _open, \ + .read = seq_read, \ + .llseek = seq_lseek, \ + .release = _release, \ + .write = _write, \ +} + +#define AMDXDNA_DBGFS_FOPS(_name, _show, _write) \ + static int amdxdna_dbgfs_##_name##_open(struct inode *inode, struct file *file) \ + { \ + return single_open(file, _show, inode->i_private); \ + } \ + static int amdxdna_dbgfs_##_name##_release(struct inode *inode, struct file *file) \ + { \ + return single_release(inode, file); \ + } \ + static const struct file_operations amdxdna_fops_##_name = \ + _DBGFS_FOPS(amdxdna_dbgfs_##_name##_open, amdxdna_dbgfs_##_name##_release, _write) + +#define AMDXDNA_DBGFS_FILE(_name, _mode) { #_name, &amdxdna_fops_##_name, _mode } + +#define file_to_xdna(file) (((struct seq_file *)(file)->private_data)->private) + +static ssize_t amdxdna_carveout_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct amdxdna_dev *xdna = file_to_xdna(file); + char kbuf[128]; + u64 size, addr; + char *sep; + int ret; + + if (count == 0 || count >= sizeof(kbuf)) + return -EINVAL; + + if (copy_from_user(kbuf, buf, count)) + return -EFAULT; + kbuf[count] = '\0'; + strim(kbuf); + XDNA_DBG(xdna, "Trying to set carveout to %s", kbuf); + + sep = strchr(kbuf, '@'); + if (!sep) + return -EINVAL; + *sep = '\0'; + sep++; + + ret = kstrtou64(kbuf, 0, &size); + if (ret) + return ret; + + ret = kstrtou64(sep, 0, &addr); + if (ret) + return ret; + + /* Sanity check the addr and size. */ + if (!size) + return -EINVAL; + if (!IS_ALIGNED(addr, PAGE_SIZE) || !IS_ALIGNED(size, PAGE_SIZE)) + return -EINVAL; + + guard(mutex)(&xdna->dev_lock); + + ret = amdxdna_carveout_init(xdna, addr, size); + if (ret) + return ret; + + return count; +} + +static int amdxdna_carveout_show(struct seq_file *m, void *unused) +{ + struct amdxdna_dev *xdna = m->private; + u64 addr, size; + + guard(mutex)(&xdna->dev_lock); + amdxdna_get_carveout_conf(xdna, &addr, &size); + seq_printf(m, "0x%llx@0x%llx\n", size, addr); + return 0; +} + +/* + * Input/output format: @ + */ +AMDXDNA_DBGFS_FOPS(carveout, amdxdna_carveout_show, amdxdna_carveout_write); + +static const struct { + const char *name; + const struct file_operations *fops; + umode_t mode; +} amdxdna_dbgfs_files[] = { + AMDXDNA_DBGFS_FILE(carveout, 0600), +}; + +void amdxdna_debugfs_init(struct amdxdna_dev *xdna) +{ + struct drm_minor *minor = xdna->ddev.accel; + int i; + + /* + * It should be okay that debugfs fails to init. + * We rely on DRM framework to finish debugfs. + */ + for (i = 0; i < ARRAY_SIZE(amdxdna_dbgfs_files); i++) { + debugfs_create_file(amdxdna_dbgfs_files[i].name, + amdxdna_dbgfs_files[i].mode, + minor->debugfs_root, + xdna, + amdxdna_dbgfs_files[i].fops); + } +} diff --git a/drivers/accel/amdxdna/amdxdna_debugfs.h b/drivers/accel/amdxdna/amdxdna_debugfs.h new file mode 100644 index 000000000000..2abb45de3f7e --- /dev/null +++ b/drivers/accel/amdxdna/amdxdna_debugfs.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ +#ifndef _AMDXDNA_DEBUGFS_H_ +#define _AMDXDNA_DEBUGFS_H_ + +#include "amdxdna_pci_drv.h" + +#if defined(CONFIG_DEBUG_FS) +void amdxdna_debugfs_init(struct amdxdna_dev *xdna); +#else +static inline void amdxdna_debugfs_init(struct amdxdna_dev *xdna) +{ +} +#endif /* CONFIG_DEBUG_FS */ + +#endif diff --git a/drivers/accel/amdxdna/amdxdna_gem.c b/drivers/accel/amdxdna/amdxdna_gem.c index 238ee244d4a6..00efa8abfeea 100644 --- a/drivers/accel/amdxdna/amdxdna_gem.c +++ b/drivers/accel/amdxdna/amdxdna_gem.c @@ -16,6 +16,7 @@ #include #include +#include "amdxdna_cbuf.h" #include "amdxdna_ctx.h" #include "amdxdna_gem.h" #include "amdxdna_pci_drv.h" @@ -23,6 +24,77 @@ MODULE_IMPORT_NS("DMA_BUF"); +/* + * The dev BO could be across multiple heap BO chunks. The heap chunks should + * be mapped to userspace and the userspace virtual address should be + * contiguous. + */ +static int +amdxdna_init_dev_bo(struct amdxdna_gem_obj *dev_bo) +{ + struct amdxdna_client *client = dev_bo->client; + struct amdxdna_dev *xdna = client->xdna; + struct amdxdna_gem_obj *heap; + u64 heap_addr, exp_heap_uva; + u32 heap_id; + + if (xa_empty(&client->dev_heap_xa)) { + XDNA_DBG(xdna, "Empty heap xa"); + return -EAGAIN; + } + + for (heap_id = 0; heap_id < client->dev_heap_nid; heap_id++) { + heap = xa_load(&client->dev_heap_xa, heap_id); + if (!heap) { + XDNA_ERR(xdna, "Failed to load heap %d", heap_id); + return -EINVAL; + } + heap_addr = amdxdna_gem_dev_addr(heap); + if (heap_addr > dev_bo->mm_node.start) + break; + } + + heap_id--; + heap = xa_load(&client->dev_heap_xa, heap_id); + exp_heap_uva = amdxdna_gem_uva(heap); + heap_addr = amdxdna_gem_dev_addr(heap); + dev_bo->heap_start_id = heap_id; + dev_bo->mem.uva = dev_bo->mm_node.start - heap_addr + exp_heap_uva; + + for (; heap_id < client->dev_heap_nid; heap_id++) { + heap = xa_load(&client->dev_heap_xa, heap_id); + if (!heap) { + XDNA_ERR(xdna, "Failed to load heap %d", heap_id); + return -EINVAL; + } + heap_addr = amdxdna_gem_uva(heap); + if (heap_addr == AMDXDNA_INVALID_ADDR) { + XDNA_ERR(xdna, "Heap %d is not mapped", heap_id); + return -EAGAIN; + } + + if (heap_addr != exp_heap_uva) { + XDNA_ERR(xdna, "Heap %d uva is not contiguous", heap_id); + return -EINVAL; + } + + if (heap->dev_addr + heap->mem.size >= + dev_bo->mm_node.start + dev_bo->mem.size) + break; + + exp_heap_uva += heap->mem.size; + } + + if (heap_id == client->dev_heap_nid) { + XDNA_DBG(xdna, "Can not find heap end"); + return -EAGAIN; + } + + dev_bo->heap_end_id = heap_id; + + return 0; +} + static int amdxdna_gem_heap_alloc(struct amdxdna_gem_obj *abo) { @@ -30,32 +102,22 @@ amdxdna_gem_heap_alloc(struct amdxdna_gem_obj *abo) struct amdxdna_dev *xdna = client->xdna; struct amdxdna_mem *mem = &abo->mem; struct amdxdna_gem_obj *heap; + unsigned long heap_id; u32 align; int ret; mutex_lock(&client->mm_lock); - heap = client->dev_heap; - if (!heap) { - ret = -EINVAL; - goto unlock_out; - } - - if (amdxdna_gem_uva(heap) == AMDXDNA_INVALID_ADDR) { - XDNA_ERR(xdna, "Invalid dev heap userptr"); - ret = -EINVAL; - goto unlock_out; - } - - if (mem->size == 0 || mem->size > heap->mem.size) { - XDNA_ERR(xdna, "Invalid dev bo size 0x%lx, limit 0x%lx", - mem->size, heap->mem.size); + if (!mem->size || mem->size > xdna->dev_info->dev_heap_max_size) { + XDNA_ERR(xdna, "Invalid dev bo size 0x%lx, max heap 0x%lx", + mem->size, xdna->dev_info->dev_heap_max_size); ret = -EINVAL; goto unlock_out; } align = 1 << max(PAGE_SHIFT, xdna->dev_info->dev_mem_buf_shift); - ret = drm_mm_insert_node_generic(&heap->mm, &abo->mm_node, + ret = drm_mm_insert_node_generic(&client->dev_heap_mm, + &abo->mm_node, mem->size, align, 0, DRM_MM_INSERT_BEST); if (ret) { @@ -63,9 +125,16 @@ amdxdna_gem_heap_alloc(struct amdxdna_gem_obj *abo) goto unlock_out; } - client->heap_usage += mem->size; + ret = amdxdna_init_dev_bo(abo); + if (ret) { + drm_mm_remove_node(&abo->mm_node); + goto unlock_out; + } - drm_gem_object_get(to_gobj(heap)); + client->heap_usage += mem->size; + xa_for_each_range(&client->dev_heap_xa, heap_id, heap, + abo->heap_start_id, abo->heap_end_id) + drm_gem_object_get(to_gobj(heap)); unlock_out: mutex_unlock(&client->mm_lock); @@ -78,13 +147,16 @@ amdxdna_gem_heap_free(struct amdxdna_gem_obj *abo) { struct amdxdna_client *client = abo->client; struct amdxdna_gem_obj *heap; + unsigned long heap_id; mutex_lock(&client->mm_lock); drm_mm_remove_node(&abo->mm_node); client->heap_usage -= abo->mem.size; - heap = client->dev_heap; - drm_gem_object_put(to_gobj(heap)); + + xa_for_each_range(&client->dev_heap_xa, heap_id, heap, + abo->heap_start_id, abo->heap_end_id) + drm_gem_object_put(to_gobj(heap)); mutex_unlock(&client->mm_lock); } @@ -160,31 +232,13 @@ static void amdxdna_gem_vunmap(struct amdxdna_gem_obj *abo) } } -/* - * Obtain the user virtual address for accessing the BO. - * It can be used for device to access the BO when PASID is enabled. - */ -u64 amdxdna_gem_uva(struct amdxdna_gem_obj *abo) -{ - if (abo->type == AMDXDNA_BO_DEV) { - struct amdxdna_gem_obj *heap = abo->client->dev_heap; - u64 off = amdxdna_dev_bo_offset(abo); - - if (amdxdna_gem_uva(heap) != AMDXDNA_INVALID_ADDR) - return amdxdna_gem_uva(heap) + off; - return AMDXDNA_INVALID_ADDR; - } - - return abo->mem.uva; -} - /* * Obtain the address for device to access the BO. */ u64 amdxdna_gem_dev_addr(struct amdxdna_gem_obj *abo) { if (abo->type == AMDXDNA_BO_DEV_HEAP) - return abo->client->xdna->dev_info->dev_mem_base; + return abo->dev_addr; if (abo->type == AMDXDNA_BO_DEV) return abo->mm_node.start; return amdxdna_obj_dma_addr(abo); @@ -211,7 +265,8 @@ static bool amdxdna_hmm_invalidate(struct mmu_interval_notifier *mni, mmu_interval_set_seq(&mapp->notifier, cur_seq); up_write(&xdna->notifier_lock); - xdna->dev_info->ops->hmm_invalidate(abo, cur_seq); + if (xdna->dev_info->ops->hmm_invalidate) + xdna->dev_info->ops->hmm_invalidate(abo, cur_seq); if (range->event == MMU_NOTIFY_UNMAP) { down_write(&xdna->notifier_lock); @@ -294,7 +349,7 @@ static int amdxdna_hmm_register(struct amdxdna_gem_obj *abo, u32 nr_pages; int ret; - if (!xdna->dev_info->ops->hmm_invalidate) + if (!amdxdna_pasid_on(abo->client)) return 0; mapp = kzalloc_obj(*mapp); @@ -490,6 +545,9 @@ static struct dma_buf *amdxdna_gem_prime_export(struct drm_gem_object *gobj, int struct amdxdna_gem_obj *abo = to_xdna_obj(gobj); DEFINE_DMA_BUF_EXPORT_INFO(exp_info); + if (abo->private_buffer) + return ERR_PTR(-EOPNOTSUPP); + if (abo->dma_buf) { get_dma_buf(abo->dma_buf); return abo->dma_buf; @@ -516,10 +574,6 @@ static void amdxdna_imported_obj_free(struct amdxdna_gem_obj *abo) static inline bool amdxdna_gem_skip_bo_usage(struct amdxdna_gem_obj *abo) { - /* Do not count imported BOs since the buffer is not allocated by us. */ - if (is_import_bo(abo)) - return true; - /* Already counted as part of HEAP BO */ if (abo->type == AMDXDNA_BO_DEV) return true; @@ -568,12 +622,7 @@ static void amdxdna_gem_obj_free(struct drm_gem_object *gobj) if (abo->pinned) amdxdna_gem_unpin(abo); - if (abo->type == AMDXDNA_BO_DEV_HEAP) - drm_mm_takedown(&abo->mm); - - if (amdxdna_iova_on(xdna)) - amdxdna_iommu_unmap_bo(xdna, abo); - + amdxdna_dma_unmap_bo(xdna, abo); amdxdna_gem_vunmap(abo); mutex_destroy(&abo->lock); @@ -591,18 +640,20 @@ static int amdxdna_gem_obj_open(struct drm_gem_object *gobj, struct drm_file *fi guard(mutex)(&abo->lock); abo->open_ref++; + if (abo->open_ref > 1) + return 0; - if (abo->open_ref == 1) { - /* Attached to the client when first opened by it. */ - abo->client = filp->driver_priv; - amdxdna_gem_add_bo_usage(abo); - } - if (amdxdna_iova_on(xdna)) { - ret = amdxdna_iommu_map_bo(xdna, abo); + /* Attached to the client when first opened by it. */ + abo->client = filp->driver_priv; + + /* No need to set up dma addr mapping in PASID mode. */ + if (!amdxdna_pasid_on(abo->client)) { + ret = amdxdna_dma_map_bo(xdna, abo); if (ret) return ret; } + amdxdna_gem_add_bo_usage(abo); return 0; } @@ -620,14 +671,59 @@ static void amdxdna_gem_obj_close(struct drm_gem_object *gobj, struct drm_file * } } +static int amdxdna_gem_obj_vmap(struct drm_gem_object *obj, struct iosys_map *map) +{ + struct amdxdna_gem_obj *abo = to_xdna_obj(obj); + int ret; + + iosys_map_clear(map); + + dma_resv_assert_held(obj->resv); + + if (is_import_bo(abo)) + ret = dma_buf_vmap(abo->dma_buf, map); + else + ret = drm_gem_shmem_object_vmap(obj, map); + if (ret) + return ret; + if (!map->vaddr) + return -ENOMEM; + + return 0; +} + +static void amdxdna_gem_obj_vunmap(struct drm_gem_object *obj, struct iosys_map *map) +{ + struct amdxdna_gem_obj *abo = to_xdna_obj(obj); + + dma_resv_assert_held(obj->resv); + + if (is_import_bo(abo)) + dma_buf_vunmap(abo->dma_buf, map); + else + drm_gem_shmem_object_vunmap(obj, map); +} + static int amdxdna_gem_dev_obj_vmap(struct drm_gem_object *obj, struct iosys_map *map) { struct amdxdna_gem_obj *abo = to_xdna_obj(obj); - void *base = amdxdna_gem_vmap(abo->client->dev_heap); - u64 offset = amdxdna_dev_bo_offset(abo); + struct amdxdna_gem_obj *heap; + void *base; + u64 offset; + /* vmap dev bo which is across more than 1 heap is not allowed */ + if (abo->heap_start_id != abo->heap_end_id) + return -ENOMEM; + + heap = xa_load(&abo->client->dev_heap_xa, abo->heap_start_id); + if (!heap) + return -ENOMEM; + + base = amdxdna_gem_vmap(heap); if (!base) return -ENOMEM; + + offset = amdxdna_gem_dev_addr(abo) - amdxdna_gem_dev_addr(heap); iosys_map_set_vaddr(map, base + offset); return 0; } @@ -645,8 +741,8 @@ static const struct drm_gem_object_funcs amdxdna_gem_shmem_funcs = { .pin = drm_gem_shmem_object_pin, .unpin = drm_gem_shmem_object_unpin, .get_sg_table = drm_gem_shmem_object_get_sg_table, - .vmap = drm_gem_shmem_object_vmap, - .vunmap = drm_gem_shmem_object_vunmap, + .vmap = amdxdna_gem_obj_vmap, + .vunmap = amdxdna_gem_obj_vunmap, .mmap = amdxdna_gem_obj_mmap, .vm_ops = &drm_gem_shmem_vm_ops, .export = amdxdna_gem_prime_export, @@ -685,6 +781,7 @@ amdxdna_gem_create_ubuf_object(struct drm_device *dev, struct amdxdna_drm_create { struct amdxdna_dev *xdna = to_xdna_dev(dev); struct amdxdna_drm_va_tbl va_tbl; + struct amdxdna_gem_obj *abo; struct drm_gem_object *gobj; struct dma_buf *dma_buf; @@ -711,7 +808,40 @@ amdxdna_gem_create_ubuf_object(struct drm_device *dev, struct amdxdna_drm_create dma_buf_put(dma_buf); - return to_xdna_obj(gobj); + abo = to_xdna_obj(gobj); + abo->private_buffer = true; + + return abo; +} + +static struct amdxdna_gem_obj * +amdxdna_gem_create_cbuf_object(struct drm_device *dev, struct amdxdna_drm_create_bo *args) +{ + struct amdxdna_dev *xdna = to_xdna_dev(dev); + size_t size = PAGE_ALIGN(args->size); + struct drm_gem_object *gobj; + struct amdxdna_gem_obj *ret; + struct dma_buf *dma_buf; + u64 align; + + if (!size) { + XDNA_ERR(xdna, "Invalid BO size 0x%llx", args->size); + return ERR_PTR(-EINVAL); + } + + align = (args->type == AMDXDNA_BO_DEV_HEAP) ? xdna->dev_info->dev_mem_size : 0; + dma_buf = amdxdna_get_cbuf(dev, size, align); + if (IS_ERR(dma_buf)) + return ERR_CAST(dma_buf); + + gobj = amdxdna_gem_prime_import(dev, dma_buf); + if (IS_ERR(gobj)) + ret = ERR_CAST(gobj); + else + ret = to_xdna_obj(gobj); + + dma_buf_put(dma_buf); + return ret; } struct drm_gem_object * @@ -769,6 +899,8 @@ amdxdna_drm_create_share_bo(struct drm_device *dev, if (args->vaddr) abo = amdxdna_gem_create_ubuf_object(dev, args); + else if (amdxdna_use_carveout(to_xdna_dev(dev))) + abo = amdxdna_gem_create_cbuf_object(dev, args); else abo = amdxdna_gem_create_shmem_object(dev, args); if (IS_ERR(abo)) @@ -810,15 +942,32 @@ amdxdna_drm_create_dev_heap_bo(struct drm_device *dev, /* Set up heap for this client. */ mutex_lock(&client->mm_lock); - if (client->dev_heap) { - XDNA_DBG(client->xdna, "dev heap is already created"); - ret = -EBUSY; + if (!xdna->dev_info->ops->hwctx_heap_expand && + client->dev_heap_nid > 0) { + XDNA_ERR(xdna, "Heap expansion is not supported"); + ret = -EOPNOTSUPP; goto mm_unlock; } - client->dev_heap = abo; - drm_gem_object_get(to_gobj(abo)); - drm_mm_init(&abo->mm, xdna->dev_info->dev_mem_base, abo->mem.size); + if (client->total_heap_size + abo->mem.size > + xdna->dev_info->dev_heap_max_size) { + XDNA_ERR(xdna, "Heap size 0x%lx + 0x%lx exceeds max 0x%lx", + client->total_heap_size, abo->mem.size, + xdna->dev_info->dev_heap_max_size); + ret = -ENOSPC; + goto mm_unlock; + } + + ret = xa_insert(&client->dev_heap_xa, client->dev_heap_nid, abo, GFP_KERNEL); + if (ret) { + XDNA_ERR(xdna, "Add heap failed %d", ret); + goto mm_unlock; + } + + abo->dev_addr = xdna->dev_info->dev_mem_base + client->total_heap_size; + client->total_heap_size += abo->mem.size; + client->dev_heap_nid++; + drm_gem_object_get(to_gobj(abo)); mutex_unlock(&client->mm_lock); @@ -861,10 +1010,10 @@ amdxdna_drm_create_dev_bo(struct drm_device *dev, ret = amdxdna_gem_heap_alloc(abo); if (ret) { - XDNA_ERR(xdna, "Failed to alloc dev bo memory, ret %d", ret); amdxdna_gem_destroy_obj(abo); return ERR_PTR(ret); } + drm_gem_private_object_init(dev, gobj, aligned_sz); return abo; @@ -872,6 +1021,7 @@ amdxdna_drm_create_dev_bo(struct drm_device *dev, int amdxdna_drm_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { + struct amdxdna_client *client = filp->driver_priv; struct amdxdna_dev *xdna = to_xdna_dev(dev); struct amdxdna_drm_create_bo *args = data; struct amdxdna_gem_obj *abo; @@ -884,7 +1034,6 @@ int amdxdna_drm_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_f args->type, args->vaddr, args->size, args->flags); switch (args->type) { case AMDXDNA_BO_CMD: - fallthrough; case AMDXDNA_BO_SHARE: abo = amdxdna_drm_create_share_bo(dev, args, filp); break; @@ -893,6 +1042,13 @@ int amdxdna_drm_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_f break; case AMDXDNA_BO_DEV: abo = amdxdna_drm_create_dev_bo(dev, args, filp); + if (!IS_ERR(abo)) { + mutex_lock(&xdna->dev_lock); + ret = amdxdna_update_heap(client, NULL); + mutex_unlock(&xdna->dev_lock); + if (ret) + goto put_obj; + } break; default: return -EINVAL; @@ -916,14 +1072,11 @@ int amdxdna_drm_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_f return ret; } -int amdxdna_gem_pin_nolock(struct amdxdna_gem_obj *abo) +static int amdxdna_bo_pin(struct amdxdna_gem_obj *abo) { struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev); int ret; - if (abo->type == AMDXDNA_BO_DEV) - abo = abo->client->dev_heap; - if (is_import_bo(abo)) return 0; @@ -933,6 +1086,45 @@ int amdxdna_gem_pin_nolock(struct amdxdna_gem_obj *abo) return ret; } +static void amdxdna_bo_unpin(struct amdxdna_gem_obj *abo) +{ + struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev); + + if (is_import_bo(abo)) + return; + + drm_gem_shmem_unpin(&abo->base); + + XDNA_DBG(xdna, "BO type %d", abo->type); +} + +int amdxdna_gem_pin_nolock(struct amdxdna_gem_obj *abo) +{ + struct amdxdna_client *client = abo->client; + struct amdxdna_gem_obj *heap; + unsigned long heap_id, last = ULONG_MAX; + int ret = 0; + + if (abo->type != AMDXDNA_BO_DEV) + return amdxdna_bo_pin(abo); + + xa_for_each_range(&client->dev_heap_xa, heap_id, heap, + abo->heap_start_id, abo->heap_end_id) { + ret = amdxdna_bo_pin(heap); + if (ret) + break; + last = heap_id; + } + + if (ret && last <= abo->heap_end_id) { + xa_for_each_range(&client->dev_heap_xa, heap_id, heap, + abo->heap_start_id, last) + amdxdna_bo_unpin(heap); + } + + return ret; +} + int amdxdna_gem_pin(struct amdxdna_gem_obj *abo) { int ret; @@ -946,14 +1138,18 @@ int amdxdna_gem_pin(struct amdxdna_gem_obj *abo) void amdxdna_gem_unpin(struct amdxdna_gem_obj *abo) { - if (abo->type == AMDXDNA_BO_DEV) - abo = abo->client->dev_heap; - - if (is_import_bo(abo)) - return; - mutex_lock(&abo->lock); - drm_gem_shmem_unpin(&abo->base); + if (abo->type == AMDXDNA_BO_DEV) { + struct amdxdna_gem_obj *heap; + unsigned long heap_id; + + xa_for_each_range(&abo->client->dev_heap_xa, heap_id, heap, + abo->heap_start_id, abo->heap_end_id) + amdxdna_bo_unpin(heap); + } else { + amdxdna_bo_unpin(abo); + } + mutex_unlock(&abo->lock); } @@ -1010,6 +1206,29 @@ int amdxdna_drm_get_bo_info_ioctl(struct drm_device *dev, void *data, struct drm return ret; } +static int amdxdna_flush_bo(struct amdxdna_gem_obj *abo, u64 offset, u64 size) +{ + u64 end; + + if (offset >= abo->mem.size) + return -EINVAL; + + if (check_add_overflow(offset, size, &end)) + return -EINVAL; + + size = min(abo->mem.size, end) - offset; + if (is_import_bo(abo)) + drm_clflush_sg(abo->base.sgt); + else if (amdxdna_gem_vmap(abo)) + drm_clflush_virt_range(amdxdna_gem_vmap(abo) + offset, size); + else if (abo->base.pages) + drm_clflush_pages(abo->base.pages, abo->mem.size >> PAGE_SHIFT); + else + return -EINVAL; + + return 0; +} + /* * The sync bo ioctl is to make sure the CPU cache is in sync with memory. * This is required because NPU is not cache coherent device. CPU cache @@ -1020,11 +1239,12 @@ int amdxdna_drm_get_bo_info_ioctl(struct drm_device *dev, void *data, struct drm int amdxdna_drm_sync_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { + struct amdxdna_client *client = filp->driver_priv; struct amdxdna_dev *xdna = to_xdna_dev(dev); struct amdxdna_drm_sync_bo *args = data; struct amdxdna_gem_obj *abo; struct drm_gem_object *gobj; - int ret; + int ret = 0; gobj = drm_gem_object_lookup(filp, args->handle); if (!gobj) { @@ -1033,23 +1253,46 @@ int amdxdna_drm_sync_bo_ioctl(struct drm_device *dev, } abo = to_xdna_obj(gobj); - ret = amdxdna_gem_pin(abo); - if (ret) { - XDNA_ERR(xdna, "Pin BO %d failed, ret %d", args->handle, ret); - goto put_obj; + if (abo->type == AMDXDNA_BO_DEV) { + struct amdxdna_gem_obj *heap; + unsigned long heap_id; + u64 bo_start = amdxdna_gem_dev_addr(abo); + u64 flush_start = bo_start + args->offset; + u64 flush_end = flush_start + args->size; + + xa_for_each_range(&client->dev_heap_xa, heap_id, heap, + abo->heap_start_id, abo->heap_end_id) { + u64 heap_start = amdxdna_gem_dev_addr(heap); + u64 heap_end = heap_start + heap->mem.size; + u64 start = max(flush_start, heap_start); + u64 end = min(flush_end, heap_end); + + if (start >= end) + continue; + + ret = amdxdna_flush_bo(heap, start - heap_start, end - start); + if (ret) { + XDNA_ERR(xdna, "Failed to flush heap %ld ret %d", + heap_id, ret); + goto put_obj; + } + } + } else { + ret = amdxdna_gem_pin(abo); + if (ret) { + XDNA_ERR(xdna, "Pin BO %d failed, ret %d", args->handle, ret); + goto put_obj; + } + + ret = amdxdna_flush_bo(abo, args->offset, args->size); + amdxdna_gem_unpin(abo); + + if (ret) { + drm_WARN(&xdna->ddev, 1, "Can not get flush memory"); + goto put_obj; + } } - if (is_import_bo(abo)) - drm_clflush_sg(abo->base.sgt); - else if (amdxdna_gem_vmap(abo)) - drm_clflush_virt_range(amdxdna_gem_vmap(abo) + args->offset, args->size); - else if (abo->base.pages) - drm_clflush_pages(abo->base.pages, gobj->size >> PAGE_SHIFT); - else - drm_WARN(&xdna->ddev, 1, "Can not get flush memory"); - - amdxdna_gem_unpin(abo); - XDNA_DBG(xdna, "Sync bo %d offset 0x%llx, size 0x%llx\n", args->handle, args->offset, args->size); diff --git a/drivers/accel/amdxdna/amdxdna_gem.h b/drivers/accel/amdxdna/amdxdna_gem.h index 4fc48a1189d2..a3e44c7a2395 100644 --- a/drivers/accel/amdxdna/amdxdna_gem.h +++ b/drivers/accel/amdxdna/amdxdna_gem.h @@ -46,14 +46,18 @@ struct amdxdna_gem_obj { int open_ref; /* Below members are initialized when needed */ - struct drm_mm mm; /* For AMDXDNA_BO_DEV_HEAP */ struct drm_mm_node mm_node; /* For AMDXDNA_BO_DEV */ + u32 heap_start_id; + u32 heap_end_id; + u64 dev_addr; /* For heap bo */ u32 assigned_hwctx; struct dma_buf *dma_buf; struct dma_buf_attachment *attach; /* True, if BO is managed by XRT, not application */ bool internal; + /* True, if BO is not exportable */ + bool private_buffer; }; #define to_gobj(obj) (&(obj)->base.base) @@ -71,13 +75,21 @@ static inline void amdxdna_gem_put_obj(struct amdxdna_gem_obj *abo) drm_gem_object_put(to_gobj(abo)); } +/* + * Obtain the user virtual address for accessing the BO. + * It can be used for device to access the BO when PASID is enabled. + */ +static inline u64 amdxdna_gem_uva(struct amdxdna_gem_obj *abo) +{ + return abo->mem.uva; +} + void *amdxdna_gem_vmap(struct amdxdna_gem_obj *abo); -u64 amdxdna_gem_uva(struct amdxdna_gem_obj *abo); u64 amdxdna_gem_dev_addr(struct amdxdna_gem_obj *abo); static inline u64 amdxdna_dev_bo_offset(struct amdxdna_gem_obj *abo) { - return amdxdna_gem_dev_addr(abo) - amdxdna_gem_dev_addr(abo->client->dev_heap); + return amdxdna_gem_dev_addr(abo) - abo->client->xdna->dev_info->dev_mem_base; } static inline u64 amdxdna_obj_dma_addr(struct amdxdna_gem_obj *abo) diff --git a/drivers/accel/amdxdna/amdxdna_iommu.c b/drivers/accel/amdxdna/amdxdna_iommu.c index 4626434d4180..eff00131d0f8 100644 --- a/drivers/accel/amdxdna/amdxdna_iommu.c +++ b/drivers/accel/amdxdna/amdxdna_iommu.c @@ -35,14 +35,15 @@ static struct iova *amdxdna_iommu_alloc_iova(struct amdxdna_dev *xdna, return iova; } -int amdxdna_iommu_map_bo(struct amdxdna_dev *xdna, struct amdxdna_gem_obj *abo) +int amdxdna_dma_map_bo(struct amdxdna_dev *xdna, struct amdxdna_gem_obj *abo) { + unsigned long contig_sz; struct sg_table *sgt; dma_addr_t dma_addr; struct iova *iova; - size_t size; + ssize_t size; - if (abo->type != AMDXDNA_BO_DEV_HEAP && abo->type != AMDXDNA_BO_SHMEM) + if (abo->type != AMDXDNA_BO_DEV_HEAP && abo->type != AMDXDNA_BO_SHARE) return 0; sgt = drm_gem_shmem_get_pages_sgt(&abo->base); @@ -51,40 +52,63 @@ int amdxdna_iommu_map_bo(struct amdxdna_dev *xdna, struct amdxdna_gem_obj *abo) return PTR_ERR(sgt); } - if (!sgt->orig_nents || !sg_page(sgt->sgl)) { - XDNA_ERR(xdna, "sgl is zero length or not page backed"); + if (!sgt->orig_nents) { + XDNA_ERR(xdna, "sgl is zero length"); return -EOPNOTSUPP; } - iova = amdxdna_iommu_alloc_iova(xdna, abo->mem.size, &dma_addr, - (abo->type == AMDXDNA_BO_DEV_HEAP)); - if (IS_ERR(iova)) { - XDNA_ERR(xdna, "Alloc iova failed, ret %ld", PTR_ERR(iova)); - return PTR_ERR(iova); + if (amdxdna_iova_on(xdna)) { + if (!sg_page(sgt->sgl)) { + XDNA_ERR(xdna, "sgl is not page backed"); + return -EOPNOTSUPP; + } + + iova = amdxdna_iommu_alloc_iova(xdna, abo->mem.size, &dma_addr, + (abo->type == AMDXDNA_BO_DEV_HEAP)); + if (IS_ERR(iova)) { + XDNA_ERR(xdna, "Alloc iova failed, ret %ld", PTR_ERR(iova)); + return PTR_ERR(iova); + } + + size = iommu_map_sgtable(xdna->domain, dma_addr, sgt, + IOMMU_READ | IOMMU_WRITE); + if (size < 0) { + XDNA_ERR(xdna, "iommu_map_sgtable failed: %zd", size); + __free_iova(&xdna->iovad, iova); + return size; + } + if (size < abo->mem.size) { + iommu_unmap(xdna->domain, dma_addr, size); + __free_iova(&xdna->iovad, iova); + return -ENXIO; + } + abo->mem.dma_addr = dma_addr; + } else { + /* Device doesn't support scatter/gather list, fail non-contiguous mapping. */ + contig_sz = drm_prime_get_contiguous_size(sgt); + if (contig_sz < abo->mem.size) { + XDNA_ERR(xdna, + "noncontiguous dma addr, contig size:%ld, expected size:%ld", + contig_sz, abo->mem.size); + return -EINVAL; + } + abo->mem.dma_addr = sg_dma_address(sgt->sgl); } - - size = iommu_map_sgtable(xdna->domain, dma_addr, sgt, - IOMMU_READ | IOMMU_WRITE); - if (size < abo->mem.size) { - __free_iova(&xdna->iovad, iova); - return -ENXIO; - } - - abo->mem.dma_addr = dma_addr; - return 0; } -void amdxdna_iommu_unmap_bo(struct amdxdna_dev *xdna, struct amdxdna_gem_obj *abo) +void amdxdna_dma_unmap_bo(struct amdxdna_dev *xdna, struct amdxdna_gem_obj *abo) { size_t size; if (abo->mem.dma_addr == AMDXDNA_INVALID_ADDR) return; - size = iova_align(&xdna->iovad, abo->mem.size); - iommu_unmap(xdna->domain, abo->mem.dma_addr, size); - free_iova(&xdna->iovad, iova_pfn(&xdna->iovad, abo->mem.dma_addr)); + if (amdxdna_iova_on(xdna)) { + size = iova_align(&xdna->iovad, abo->mem.size); + iommu_unmap(xdna->domain, abo->mem.dma_addr, size); + free_iova(&xdna->iovad, iova_pfn(&xdna->iovad, abo->mem.dma_addr)); + } abo->mem.dma_addr = AMDXDNA_INVALID_ADDR; } @@ -110,10 +134,12 @@ void *amdxdna_iommu_alloc(struct amdxdna_dev *xdna, size_t size, dma_addr_t *dma iova_align(&xdna->iovad, size), IOMMU_READ | IOMMU_WRITE, GFP_KERNEL); if (ret) - goto free_iova; + goto free_cpu_addr; return cpu_addr; +free_cpu_addr: + free_pages((unsigned long)cpu_addr, get_order(size)); free_iova: __free_iova(&xdna->iovad, iova); return ERR_PTR(ret); diff --git a/drivers/accel/amdxdna/amdxdna_mailbox.c b/drivers/accel/amdxdna/amdxdna_mailbox.c index e681a090752d..cc8865f4e79c 100644 --- a/drivers/accel/amdxdna/amdxdna_mailbox.c +++ b/drivers/accel/amdxdna/amdxdna_mailbox.c @@ -112,6 +112,18 @@ static u32 mailbox_reg_read(struct mailbox_channel *mb_chann, u32 mbox_reg) return readl(ringbuf_addr); } +static inline void mailbox_irq_acknowledge(struct mailbox_channel *mb_chann) +{ + if (mb_chann->iohub_int_addr) + mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0); +} + +static inline u32 mailbox_irq_status(struct mailbox_channel *mb_chann) +{ + return (mb_chann->iohub_int_addr) ? + mailbox_reg_read(mb_chann, mb_chann->iohub_int_addr) : 0; +} + static inline void mailbox_set_headptr(struct mailbox_channel *mb_chann, u32 headptr_val) { @@ -199,7 +211,6 @@ mailbox_send_msg(struct mailbox_channel *mb_chann, struct mailbox_msg *mb_msg) start_addr = mb_chann->res[CHAN_RES_X2I].rb_start_addr; tmp_tail = tail + mb_msg->pkg_size; - check_again: if (tail >= head && tmp_tail > ringbuf_size) { write_addr = mb_chann->mb->res.ringbuf_base + start_addr + tail; @@ -350,6 +361,7 @@ static void mailbox_rx_worker(struct work_struct *rx_work) int ret; mb_chann = container_of(rx_work, struct mailbox_channel, rx_work); + trace_mbox_rx_worker(MAILBOX_NAME, mb_chann->msix_irq); if (READ_ONCE(mb_chann->bad_state)) { MB_ERR(mb_chann, "Channel in bad state, work aborted"); @@ -357,7 +369,7 @@ static void mailbox_rx_worker(struct work_struct *rx_work) } again: - mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0); + mailbox_irq_acknowledge(mb_chann); while (1) { /* @@ -382,7 +394,7 @@ static void mailbox_rx_worker(struct work_struct *rx_work) * the interrupt register to make sure there is not any new response * before exiting. */ - if (mailbox_reg_read(mb_chann, mb_chann->iohub_int_addr)) + if (mailbox_irq_status(mb_chann)) goto again; } @@ -485,6 +497,9 @@ struct mailbox_channel *xdna_mailbox_alloc_channel(struct mailbox *mb) void xdna_mailbox_free_channel(struct mailbox_channel *mb_chann) { + if (!mb_chann) + return; + destroy_workqueue(mb_chann->work_q); kfree(mb_chann); } @@ -520,7 +535,7 @@ xdna_mailbox_start_channel(struct mailbox_channel *mb_chann, } mb_chann->bad_state = false; - mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0); + mailbox_irq_acknowledge(mb_chann); MB_DBG(mb_chann, "Mailbox channel started (irq: %d)", mb_chann->msix_irq); return 0; @@ -531,6 +546,9 @@ void xdna_mailbox_stop_channel(struct mailbox_channel *mb_chann) struct mailbox_msg *mb_msg; unsigned long msg_id; + if (!mb_chann) + return; + /* Disable an irq and wait. This might sleep. */ free_irq(mb_chann->msix_irq, mb_chann); @@ -538,7 +556,9 @@ void xdna_mailbox_stop_channel(struct mailbox_channel *mb_chann) drain_workqueue(mb_chann->work_q); /* We can clean up and release resources */ - xa_for_each(&mb_chann->chan_xa, msg_id, mb_msg) + xa_for_each_start(&mb_chann->chan_xa, msg_id, mb_msg, mb_chann->next_msgid) + mailbox_release_msg(mb_chann, mb_msg); + xa_for_each_range(&mb_chann->chan_xa, msg_id, mb_msg, 0, mb_chann->next_msgid - 1) mailbox_release_msg(mb_chann, mb_msg); xa_destroy(&mb_chann->chan_xa); diff --git a/drivers/accel/amdxdna/amdxdna_mailbox.h b/drivers/accel/amdxdna/amdxdna_mailbox.h index 8b1e00945da4..2908404303ae 100644 --- a/drivers/accel/amdxdna/amdxdna_mailbox.h +++ b/drivers/accel/amdxdna/amdxdna_mailbox.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. + * Copyright (C) 2022-2026, Advanced Micro Devices, Inc. */ -#ifndef _AIE2_MAILBOX_H_ -#define _AIE2_MAILBOX_H_ +#ifndef _AIE_MAILBOX_H_ +#define _AIE_MAILBOX_H_ struct mailbox; struct mailbox_channel; @@ -124,4 +124,4 @@ void xdna_mailbox_stop_channel(struct mailbox_channel *mailbox_chann); int xdna_mailbox_send_msg(struct mailbox_channel *mailbox_chann, const struct xdna_mailbox_msg *msg, u64 tx_timeout); -#endif /* _AIE2_MAILBOX_ */ +#endif /* _AIE_MAILBOX_ */ diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c index b50a7d1f8a11..c677293c1ae7 100644 --- a/drivers/accel/amdxdna/amdxdna_pci_drv.c +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c @@ -14,7 +14,9 @@ #include #include +#include "amdxdna_cbuf.h" #include "amdxdna_ctx.h" +#include "amdxdna_debugfs.h" #include "amdxdna_gem.h" #include "amdxdna_pci_drv.h" #include "amdxdna_pm.h" @@ -37,9 +39,11 @@ MODULE_FIRMWARE("amdnpu/17f0_11/npu_7.sbin"); * 0.6: Support preemption * 0.7: Support getting power and utilization data * 0.8: Support BO usage query + * 0.9: Add new device type AMDXDNA_DEV_TYPE_PF + * 0.10: Support AIE4 UMQ */ #define AMDXDNA_DRIVER_MAJOR 0 -#define AMDXDNA_DRIVER_MINOR 8 +#define AMDXDNA_DRIVER_MINOR 10 /* * Bind the driver base on (vendor_id, device_id) pair and later use the @@ -49,6 +53,10 @@ MODULE_FIRMWARE("amdnpu/17f0_11/npu_7.sbin"); static const struct pci_device_id pci_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1502) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f0) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f2) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f3) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1B0B) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1B0C) }, {0} }; @@ -59,14 +67,47 @@ static const struct amdxdna_device_id amdxdna_ids[] = { { 0x17f0, 0x10, &dev_npu4_info }, { 0x17f0, 0x11, &dev_npu5_info }, { 0x17f0, 0x20, &dev_npu6_info }, + { 0x17f2, 0x10, &dev_npu3_pf_info }, + { 0x17f3, 0x10, &dev_npu3_vf_info }, + { 0x1B0B, 0x10, &dev_npu3_pf_info }, + { 0x1B0C, 0x10, &dev_npu3_vf_info }, {0} }; +static int amdxdna_sva_init(struct amdxdna_client *client) +{ + struct amdxdna_dev *xdna = client->xdna; + + client->sva = iommu_sva_bind_device(xdna->ddev.dev, client->mm); + if (IS_ERR(client->sva)) { + XDNA_ERR(xdna, "SVA bind device failed, ret %ld", PTR_ERR(client->sva)); + return PTR_ERR(client->sva); + } + + client->pasid = iommu_sva_get_pasid(client->sva); + if (client->pasid == IOMMU_PASID_INVALID) { + iommu_sva_unbind_device(client->sva); + XDNA_ERR(xdna, "SVA get pasid failed"); + return -ENODEV; + } + + return 0; +} + +static void amdxdna_sva_fini(struct amdxdna_client *client) +{ + if (IS_ERR_OR_NULL(client->sva)) + return; + + iommu_sva_unbind_device(client->sva); + client->sva = NULL; + client->pasid = IOMMU_PASID_INVALID; +} + static int amdxdna_drm_open(struct drm_device *ddev, struct drm_file *filp) { struct amdxdna_dev *xdna = to_xdna_dev(ddev); struct amdxdna_client *client; - int ret; client = kzalloc_obj(*client); if (!client) @@ -75,25 +116,19 @@ static int amdxdna_drm_open(struct drm_device *ddev, struct drm_file *filp) client->pid = pid_nr(rcu_access_pointer(filp->pid)); client->xdna = xdna; client->pasid = IOMMU_PASID_INVALID; + client->mm = current->mm; if (!amdxdna_iova_on(xdna)) { - client->sva = iommu_sva_bind_device(xdna->ddev.dev, current->mm); - if (IS_ERR(client->sva)) { - ret = PTR_ERR(client->sva); - XDNA_ERR(xdna, "SVA bind device failed, ret %d", ret); - goto failed; - } - client->pasid = iommu_sva_get_pasid(client->sva); - if (client->pasid == IOMMU_PASID_INVALID) { - XDNA_ERR(xdna, "SVA get pasid failed"); - ret = -ENODEV; - goto unbind_sva; - } + /* No need to fail open since user may use pa + carveout later. */ + if (amdxdna_sva_init(client)) + XDNA_WARN(xdna, "PASID not available for pid %d", client->pid); } - client->mm = current->mm; mmgrab(client->mm); init_srcu_struct(&client->hwctx_srcu); xa_init_flags(&client->hwctx_xa, XA_FLAGS_ALLOC); + xa_init_flags(&client->dev_heap_xa, XA_FLAGS_ALLOC); + drm_mm_init(&client->dev_heap_mm, xdna->dev_info->dev_mem_base, + xdna->dev_info->dev_heap_max_size); mutex_init(&client->mm_lock); mutex_lock(&xdna->dev_lock); @@ -105,32 +140,26 @@ static int amdxdna_drm_open(struct drm_device *ddev, struct drm_file *filp) XDNA_DBG(xdna, "pid %d opened", client->pid); return 0; - -unbind_sva: - if (!IS_ERR_OR_NULL(client->sva)) - iommu_sva_unbind_device(client->sva); -failed: - kfree(client); - - return ret; } static void amdxdna_client_cleanup(struct amdxdna_client *client) { + struct amdxdna_gem_obj *heap; + unsigned long heap_id; + list_del(&client->node); amdxdna_hwctx_remove_all(client); xa_destroy(&client->hwctx_xa); cleanup_srcu_struct(&client->hwctx_srcu); - if (client->dev_heap) - drm_gem_object_put(to_gobj(client->dev_heap)); + xa_for_each(&client->dev_heap_xa, heap_id, heap) + drm_gem_object_put(to_gobj(heap)); + xa_destroy(&client->dev_heap_xa); + drm_mm_takedown(&client->dev_heap_mm); mutex_destroy(&client->mm_lock); - - if (!IS_ERR_OR_NULL(client->sva)) - iommu_sva_unbind_device(client->sva); mmdrop(client->mm); - + amdxdna_sva_fini(client); kfree(client); } @@ -204,6 +233,21 @@ static int amdxdna_drm_set_state_ioctl(struct drm_device *dev, void *data, struc return ret; } +static int amdxdna_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct drm_file *drm_filp = filp->private_data; + struct amdxdna_client *client = drm_filp->driver_priv; + struct amdxdna_dev *xdna = client->xdna; + + if (likely(vma->vm_pgoff >= DRM_FILE_PAGE_OFFSET_START)) + return drm_gem_mmap(filp, vma); + + if (!xdna->dev_info->ops->mmap) + return -EOPNOTSUPP; + + return xdna->dev_info->ops->mmap(client, vma); +} + static const struct drm_ioctl_desc amdxdna_drm_ioctls[] = { /* Context */ DRM_IOCTL_DEF_DRV(AMDXDNA_CREATE_HWCTX, amdxdna_drm_create_hwctx_ioctl, 0), @@ -215,12 +259,44 @@ static const struct drm_ioctl_desc amdxdna_drm_ioctls[] = { DRM_IOCTL_DEF_DRV(AMDXDNA_SYNC_BO, amdxdna_drm_sync_bo_ioctl, 0), /* Execution */ DRM_IOCTL_DEF_DRV(AMDXDNA_EXEC_CMD, amdxdna_drm_submit_cmd_ioctl, 0), + DRM_IOCTL_DEF_DRV(AMDXDNA_WAIT_CMD, amdxdna_drm_wait_cmd_ioctl, 0), /* AIE hardware */ DRM_IOCTL_DEF_DRV(AMDXDNA_GET_INFO, amdxdna_drm_get_info_ioctl, 0), DRM_IOCTL_DEF_DRV(AMDXDNA_GET_ARRAY, amdxdna_drm_get_array_ioctl, 0), DRM_IOCTL_DEF_DRV(AMDXDNA_SET_STATE, amdxdna_drm_set_state_ioctl, DRM_ROOT_ONLY), }; +static void amdxdna_show_fdinfo(struct drm_printer *p, struct drm_file *filp) +{ + struct amdxdna_client *client = filp->driver_priv; + size_t heap_usage, external_usage, internal_usage; + char *drv_name = filp->minor->dev->driver->name; + + mutex_lock(&client->mm_lock); + + heap_usage = client->heap_usage; + internal_usage = client->total_int_bo_usage; + external_usage = client->total_bo_usage - internal_usage; + + mutex_unlock(&client->mm_lock); + + /* + * Note for driver specific BO memory usage stat. + * Total memory in use = amdxdna-internal-alloc + amdxdna-external-alloc, which + * includes both imported and created BOs. To avoid double counts, it includes + * HEAP BO, but not DEV BO. DEV BO is counted by amdxdna-heap-alloc. + */ + drm_fdinfo_print_size(p, drv_name, "heap", "alloc", heap_usage); + drm_fdinfo_print_size(p, drv_name, "internal", "alloc", internal_usage); + drm_fdinfo_print_size(p, drv_name, "external", "alloc", external_usage); + /* + * Note for DRM standard BO memory stat. + * drm-total-memory counts both DEV BO and HEAP BO. The DEV BO size is double counted. + * drm-shared-memory counts BO shared with other processes/devices. + */ + drm_show_memory_stats(p, filp); +} + static const struct file_operations amdxdna_fops = { .owner = THIS_MODULE, .open = accel_open, @@ -230,7 +306,8 @@ static const struct file_operations amdxdna_fops = { .poll = drm_poll, .read = drm_read, .llseek = noop_llseek, - .mmap = drm_gem_mmap, + .mmap = amdxdna_drm_gem_mmap, + .show_fdinfo = drm_show_fdinfo, .fop_flags = FOP_UNSIGNED_OFFSET, }; @@ -246,7 +323,7 @@ const struct drm_driver amdxdna_drm_drv = { .postclose = amdxdna_drm_close, .ioctls = amdxdna_drm_ioctls, .num_ioctls = ARRAY_SIZE(amdxdna_drm_ioctls), - + .show_fdinfo = amdxdna_show_fdinfo, .gem_create_object = amdxdna_gem_create_shmem_object_cb, .gem_prime_import = amdxdna_gem_prime_import, }; @@ -264,25 +341,38 @@ amdxdna_get_dev_info(struct pci_dev *pdev) return NULL; } +static void amdxdna_xdna_drm_release(struct drm_device *drm, void *res) +{ + struct amdxdna_dev *xdna = res; + + amdxdna_carveout_fini(xdna); +} + static int amdxdna_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct device *dev = &pdev->dev; struct amdxdna_dev *xdna; + struct drm_device *ddev; int ret; xdna = devm_drm_dev_alloc(dev, &amdxdna_drm_drv, typeof(*xdna), ddev); if (IS_ERR(xdna)) return PTR_ERR(xdna); + ddev = &xdna->ddev; xdna->dev_info = amdxdna_get_dev_info(pdev); if (!xdna->dev_info) return -ENODEV; - drmm_mutex_init(&xdna->ddev, &xdna->dev_lock); + drmm_mutex_init(ddev, &xdna->dev_lock); init_rwsem(&xdna->notifier_lock); INIT_LIST_HEAD(&xdna->client_list); pci_set_drvdata(pdev, xdna); + ret = drmm_add_action(ddev, amdxdna_xdna_drm_release, xdna); + if (ret) + return ret; + if (IS_ENABLED(CONFIG_LOCKDEP)) { fs_reclaim_acquire(GFP_KERNEL); might_lock(&xdna->notifier_lock); @@ -313,12 +403,13 @@ static int amdxdna_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto failed_dev_fini; } - ret = drm_dev_register(&xdna->ddev, 0); + ret = drm_dev_register(ddev, 0); if (ret) { XDNA_ERR(xdna, "DRM register failed, ret %d", ret); goto failed_sysfs_fini; } + amdxdna_debugfs_init(xdna); return 0; failed_sysfs_fini: @@ -365,12 +456,24 @@ static const struct dev_pm_ops amdxdna_pm_ops = { RUNTIME_PM_OPS(amdxdna_pm_suspend, amdxdna_pm_resume, NULL) }; +static int amdxdna_sriov_configure(struct pci_dev *pdev, int num_vfs) +{ + struct amdxdna_dev *xdna = pci_get_drvdata(pdev); + + guard(mutex)(&xdna->dev_lock); + if (xdna->dev_info->ops->sriov_configure) + return xdna->dev_info->ops->sriov_configure(xdna, num_vfs); + + return -ENOENT; +} + static struct pci_driver amdxdna_pci_driver = { .name = KBUILD_MODNAME, .id_table = pci_ids, .probe = amdxdna_probe, .remove = amdxdna_remove, .driver.pm = &amdxdna_pm_ops, + .sriov_configure = amdxdna_sriov_configure, }; module_pci_driver(amdxdna_pci_driver); diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h index 0661749917d6..34271c14d359 100644 --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h @@ -7,6 +7,7 @@ #define _AMDXDNA_PCI_DRV_H_ #include +#include #include #include #include @@ -55,15 +56,27 @@ struct amdxdna_dev_ops { void (*fini)(struct amdxdna_dev *xdna); int (*resume)(struct amdxdna_dev *xdna); int (*suspend)(struct amdxdna_dev *xdna); + int (*sriov_configure)(struct amdxdna_dev *xdna, int num_vfs); + int (*mmap)(struct amdxdna_client *client, struct vm_area_struct *vma); int (*hwctx_init)(struct amdxdna_hwctx *hwctx); void (*hwctx_fini)(struct amdxdna_hwctx *hwctx); int (*hwctx_config)(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size); int (*hwctx_sync_debug_bo)(struct amdxdna_hwctx *hwctx, u32 debug_bo_hdl); + int (*hwctx_heap_expand)(struct amdxdna_hwctx *hwctx, struct amdxdna_gem_obj *heap); void (*hmm_invalidate)(struct amdxdna_gem_obj *abo, unsigned long cur_seq); int (*cmd_submit)(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq); + int (*cmd_wait)(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout); int (*get_aie_info)(struct amdxdna_client *client, struct amdxdna_drm_get_info *args); int (*set_aie_state)(struct amdxdna_client *client, struct amdxdna_drm_set_state *args); int (*get_array)(struct amdxdna_client *client, struct amdxdna_drm_get_array *args); + int (*get_dev_revision)(struct amdxdna_dev *xdna, u32 *rev); +}; + +struct amdxdna_fw_feature_tbl { + u64 features; + u32 major; + u32 max_minor; + u32 min_minor; }; /* @@ -76,13 +89,17 @@ struct amdxdna_dev_info { int sram_bar; int psp_bar; int smu_bar; + int doorbell_bar; int device_type; int first_col; u32 dev_mem_buf_shift; u64 dev_mem_base; size_t dev_mem_size; - char *vbnv; + const char *default_vbnv; + const struct amdxdna_rev_vbnv *rev_vbnv_tbl; + size_t dev_heap_max_size; const struct amdxdna_dev_priv *dev_priv; + const struct amdxdna_fw_feature_tbl *fw_feature_tbl; const struct amdxdna_dev_ops *ops; }; @@ -93,6 +110,8 @@ struct amdxdna_fw_ver { u32 build; }; +struct amdxdna_carveout; + struct amdxdna_dev { struct drm_device ddev; struct amdxdna_dev_hdl *dev_handle; @@ -108,6 +127,10 @@ struct amdxdna_dev { struct iommu_group *group; struct iommu_domain *domain; struct iova_domain iovad; + /* Accurate board name queried from firmware, or default_vbnv as fallback */ + const char *vbnv; + + struct amdxdna_carveout *carveout; }; /* @@ -133,7 +156,10 @@ struct amdxdna_client { struct drm_file *filp; struct mutex mm_lock; /* protect memory related */ - struct amdxdna_gem_obj *dev_heap; + struct xarray dev_heap_xa; + struct drm_mm dev_heap_mm; + u32 dev_heap_nid; + size_t total_heap_size; struct iommu_sva *sva; int pasid; @@ -149,6 +175,8 @@ struct amdxdna_client { /* Add device info below */ extern const struct amdxdna_dev_info dev_npu1_info; +extern const struct amdxdna_dev_info dev_npu3_pf_info; +extern const struct amdxdna_dev_info dev_npu3_vf_info; extern const struct amdxdna_dev_info dev_npu4_info; extern const struct amdxdna_dev_info dev_npu5_info; extern const struct amdxdna_dev_info dev_npu6_info; @@ -158,11 +186,11 @@ void amdxdna_sysfs_fini(struct amdxdna_dev *xdna); int amdxdna_iommu_init(struct amdxdna_dev *xdna); void amdxdna_iommu_fini(struct amdxdna_dev *xdna); -int amdxdna_iommu_map_bo(struct amdxdna_dev *xdna, struct amdxdna_gem_obj *abo); -void amdxdna_iommu_unmap_bo(struct amdxdna_dev *xdna, struct amdxdna_gem_obj *abo); void *amdxdna_iommu_alloc(struct amdxdna_dev *xdna, size_t size, dma_addr_t *dma_addr); void amdxdna_iommu_free(struct amdxdna_dev *xdna, size_t size, void *cpu_addr, dma_addr_t dma_addr); +int amdxdna_dma_map_bo(struct amdxdna_dev *xdna, struct amdxdna_gem_obj *abo); +void amdxdna_dma_unmap_bo(struct amdxdna_dev *xdna, struct amdxdna_gem_obj *abo); static inline bool amdxdna_iova_on(struct amdxdna_dev *xdna) { diff --git a/drivers/accel/amdxdna/amdxdna_sysfs.c b/drivers/accel/amdxdna/amdxdna_sysfs.c index f27e4ee960a0..d9e359ee8182 100644 --- a/drivers/accel/amdxdna/amdxdna_sysfs.c +++ b/drivers/accel/amdxdna/amdxdna_sysfs.c @@ -17,7 +17,10 @@ static ssize_t vbnv_show(struct device *dev, struct device_attribute *attr, char { struct amdxdna_dev *xdna = dev_get_drvdata(dev); - return sprintf(buf, "%s\n", xdna->dev_info->vbnv); + if (!xdna->vbnv) + return sprintf(buf, "\n"); + + return sprintf(buf, "%s\n", xdna->vbnv); } static DEVICE_ATTR_RO(vbnv); diff --git a/drivers/accel/amdxdna/amdxdna_ubuf.c b/drivers/accel/amdxdna/amdxdna_ubuf.c index fb999aa25318..bb60fb80467e 100644 --- a/drivers/accel/amdxdna/amdxdna_ubuf.c +++ b/drivers/accel/amdxdna/amdxdna_ubuf.c @@ -69,62 +69,32 @@ static void amdxdna_ubuf_release(struct dma_buf *dbuf) kfree(ubuf); } -static vm_fault_t amdxdna_ubuf_vm_fault(struct vm_fault *vmf) -{ - struct vm_area_struct *vma = vmf->vma; - struct amdxdna_ubuf_priv *ubuf; - unsigned long pfn; - pgoff_t pgoff; - - ubuf = vma->vm_private_data; - pgoff = (vmf->address - vma->vm_start) >> PAGE_SHIFT; - - pfn = page_to_pfn(ubuf->pages[pgoff]); - return vmf_insert_pfn(vma, vmf->address, pfn); -} - -static const struct vm_operations_struct amdxdna_ubuf_vm_ops = { - .fault = amdxdna_ubuf_vm_fault, -}; - -static int amdxdna_ubuf_mmap(struct dma_buf *dbuf, struct vm_area_struct *vma) -{ - struct amdxdna_ubuf_priv *ubuf = dbuf->priv; - - vma->vm_ops = &amdxdna_ubuf_vm_ops; - vma->vm_private_data = ubuf; - vm_flags_set(vma, VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP); - - return 0; -} - -static int amdxdna_ubuf_vmap(struct dma_buf *dbuf, struct iosys_map *map) -{ - struct amdxdna_ubuf_priv *ubuf = dbuf->priv; - void *kva; - - kva = vmap(ubuf->pages, ubuf->nr_pages, VM_MAP, PAGE_KERNEL); - if (!kva) - return -EINVAL; - - iosys_map_set_vaddr(map, kva); - return 0; -} - -static void amdxdna_ubuf_vunmap(struct dma_buf *dbuf, struct iosys_map *map) -{ - vunmap(map->vaddr); -} - static const struct dma_buf_ops amdxdna_ubuf_dmabuf_ops = { .map_dma_buf = amdxdna_ubuf_map, .unmap_dma_buf = amdxdna_ubuf_unmap, .release = amdxdna_ubuf_release, - .mmap = amdxdna_ubuf_mmap, - .vmap = amdxdna_ubuf_vmap, - .vunmap = amdxdna_ubuf_vunmap, }; +static int readonly_va_entry(struct amdxdna_drm_va_entry *va_ent) +{ + struct mm_struct *mm = current->mm; + struct vm_area_struct *vma; + int ret; + + mmap_read_lock(mm); + + vma = find_vma(mm, va_ent->vaddr); + if (!vma || + vma->vm_start > va_ent->vaddr || + vma->vm_end - va_ent->vaddr < va_ent->len) + ret = -ENOENT; + else + ret = vma->vm_flags & VM_WRITE ? 0 : 1; + + mmap_read_unlock(mm); + return ret; +} + struct dma_buf *amdxdna_get_ubuf(struct drm_device *dev, u32 num_entries, void __user *va_entries) { @@ -134,6 +104,7 @@ struct dma_buf *amdxdna_get_ubuf(struct drm_device *dev, struct amdxdna_ubuf_priv *ubuf; u32 npages, start = 0; struct dma_buf *dbuf; + bool readonly = true; int i, ret; DEFINE_DMA_BUF_EXPORT_INFO(exp_info); @@ -172,6 +143,10 @@ struct dma_buf *amdxdna_get_ubuf(struct drm_device *dev, ret = -EINVAL; goto free_ent; } + + /* Pin pages as writable as long as not all entries are read-only. */ + if (readonly && readonly_va_entry(&va_ent[i]) != 1) + readonly = false; } ubuf->nr_pages = exp_info.size >> PAGE_SHIFT; @@ -194,20 +169,24 @@ struct dma_buf *amdxdna_get_ubuf(struct drm_device *dev, npages = va_ent[i].len >> PAGE_SHIFT; ret = pin_user_pages_fast(va_ent[i].vaddr, npages, - FOLL_WRITE | FOLL_LONGTERM, + (readonly ? 0 : FOLL_WRITE) | FOLL_LONGTERM, &ubuf->pages[start]); - if (ret < 0 || ret != npages) { - ret = -ENOMEM; + if (ret >= 0) { + start += ret; + if (ret != npages) { + XDNA_ERR(xdna, "Partially pinned pages %d/%u", ret, npages); + ret = -ENOMEM; + goto destroy_pages; + } + } else { XDNA_ERR(xdna, "Failed to pin pages ret %d", ret); goto destroy_pages; } - - start += ret; } exp_info.ops = &amdxdna_ubuf_dmabuf_ops; exp_info.priv = ubuf; - exp_info.flags = O_RDWR | O_CLOEXEC; + exp_info.flags = (readonly ? O_RDONLY : O_RDWR) | O_CLOEXEC; dbuf = dma_buf_export(&exp_info); if (IS_ERR(dbuf)) { diff --git a/drivers/accel/amdxdna/npu1_regs.c b/drivers/accel/amdxdna/npu1_regs.c index 1320e924e548..ca779674017a 100644 --- a/drivers/accel/amdxdna/npu1_regs.c +++ b/drivers/accel/amdxdna/npu1_regs.c @@ -65,18 +65,39 @@ const struct dpm_clk_freq npu1_dpm_clk_table[] = { { 0 } }; -static const struct aie2_fw_feature_tbl npu1_fw_feature_table[] = { +static const struct amdxdna_fw_feature_tbl npu1_fw_feature_table[] = { { .major = 5, .min_minor = 7 }, { .features = BIT_U64(AIE2_NPU_COMMAND), .major = 5, .min_minor = 8 }, { 0 } }; +static int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) +{ + u32 npuclk, hclk; + int ret; + + npuclk = ndev->priv->dpm_clk_tbl[dpm_level].npuclk; + hclk = ndev->priv->dpm_clk_tbl[dpm_level].hclk; + ret = aie_smu_set_clocks(ndev->aie.smu_hdl, &npuclk, &hclk); + if (ret) + return ret; + + ndev->npuclk_freq = npuclk; + ndev->hclk_freq = hclk; + ndev->max_tops = 2 * ndev->total_col; + ndev->curr_tops = ndev->max_tops * hclk / 1028; + + XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n", + ndev->npuclk_freq, ndev->hclk_freq); + return 0; +} + static const struct amdxdna_dev_priv npu1_dev_priv = { .fw_path = "amdnpu/1502_00/", .rt_config = npu1_default_rt_cfg, .dpm_clk_tbl = npu1_dpm_clk_table, - .fw_feature_tbl = npu1_fw_feature_table, .col_align = COL_ALIGN_NONE, + .col_opc = 2048, .mbox_dev_addr = NPU1_MBOX_BAR_BASE, .mbox_size = 0, /* Use BAR size */ .sram_dev_addr = NPU1_SRAM_BAR_BASE, @@ -102,7 +123,7 @@ static const struct amdxdna_dev_priv npu1_dev_priv = { DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU1_SMU, MPNPU_PUB_SCRATCH6), DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU1_SMU, MPNPU_PUB_SCRATCH7), }, - .hw_ops = { + .hw_ops = &(const struct aie2_hw_ops) { .set_dpm = npu1_set_dpm, }, }; @@ -117,8 +138,10 @@ const struct amdxdna_dev_info dev_npu1_info = { .dev_mem_buf_shift = 15, /* 32 KiB aligned */ .dev_mem_base = AIE2_DEVM_BASE, .dev_mem_size = AIE2_DEVM_SIZE, - .vbnv = "RyzenAI-npu1", + .default_vbnv = "RyzenAI-npu1", + .dev_heap_max_size = AIE2_DEVM_SIZE, .device_type = AMDXDNA_DEV_TYPE_KMQ, .dev_priv = &npu1_dev_priv, + .fw_feature_tbl = npu1_fw_feature_table, .ops = &aie2_ops, }; diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c new file mode 100644 index 000000000000..d76b2e99c308 --- /dev/null +++ b/drivers/accel/amdxdna/npu3_regs.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include +#include + +#include "aie4_pci.h" +#include "amdxdna_pci_drv.h" + +#define NPU3_MBOX_BAR 0 + +#define NPU3_MBOX_BUFFER_BAR 2 +#define NPU3_MBOX_INFO_OFF 0x0 + +#define NPU3_DOORBELL_BAR 2 +#define NPU3_DOORBELL_OFF 0x0 + +/* PCIe BAR Index for NPU3 */ +#define NPU3_REG_BAR_INDEX 0 +#define NPU3_PSP_BAR_INDEX 4 +#define NPU3_SMU_BAR_INDEX 5 + +#define MMNPU_APERTURE3_BASE 0x3810000 +#define MMNPU_APERTURE4_BASE 0x3B10000 + +#define NPU3_PSP_BAR_BASE MMNPU_APERTURE3_BASE +#define NPU3_SMU_BAR_BASE MMNPU_APERTURE4_BASE + +#define MPASP_C2PMSG_123_ALT_1 0x3810AEC +#define MPASP_C2PMSG_156_ALT_1 0x3810B70 +#define MPASP_C2PMSG_157_ALT_1 0x3810B74 +#define MPASP_C2PMSG_73_ALT_1 0x3810A24 + +#define MP1_C2PMSG_59_ALT_1 0x3B109EC +#define MP1_C2PMSG_61_ALT_1 0x3B109F4 +#define MP1_C2PMSG_60_ALT_1 0x3B109F0 + +static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = { + { .major = 5, .min_minor = 10 }, + { 0 } +}; + +static const struct amdxdna_dev_priv npu3_dev_priv = { + .npufw_path = "npu.dev.sbin", + .certfw_path = "cert.dev.sbin", + .mbox_bar = NPU3_MBOX_BAR, + .mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR, + .mbox_info_off = NPU3_MBOX_INFO_OFF, + .doorbell_off = NPU3_DOORBELL_OFF, + .psp_regs_off = { + DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1), + DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU3_PSP, MPASP_C2PMSG_156_ALT_1), + DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU3_PSP, MPASP_C2PMSG_157_ALT_1), + DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1), + DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU3_PSP, MPASP_C2PMSG_73_ALT_1), + DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1), + DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU3_PSP, MPASP_C2PMSG_156_ALT_1), + /* npu3 doesn't use 8th pwaitmode register */ + }, + .smu_regs_off = { + DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU3_SMU, MP1_C2PMSG_59_ALT_1), + DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU3_SMU, MP1_C2PMSG_61_ALT_1), + DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU3_SMU, MMNPU_APERTURE4_BASE), + DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU3_SMU, MP1_C2PMSG_60_ALT_1), + DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU3_SMU, MP1_C2PMSG_61_ALT_1), + }, +}; + +static const struct amdxdna_dev_priv npu3_dev_vf_priv = { + /* vf device does not load firmware */ + .mbox_bar = NPU3_MBOX_BAR, + .mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR, + .mbox_info_off = NPU3_MBOX_INFO_OFF, + /* vf device does not have smu and psp */ +}; + +const struct amdxdna_dev_info dev_npu3_pf_info = { + .mbox_bar = NPU3_MBOX_BAR, + .sram_bar = NPU3_MBOX_BUFFER_BAR, + .psp_bar = NPU3_PSP_BAR_INDEX, + .smu_bar = NPU3_SMU_BAR_INDEX, + .default_vbnv = "RyzenAI-npu3-pf", + .device_type = AMDXDNA_DEV_TYPE_PF, + .dev_priv = &npu3_dev_priv, + .fw_feature_tbl = npu3_fw_feature_table, + .ops = &aie4_pf_ops, +}; + +const struct amdxdna_dev_info dev_npu3_vf_info = { + .mbox_bar = NPU3_MBOX_BAR, + .sram_bar = NPU3_MBOX_BUFFER_BAR, + .doorbell_bar = NPU3_DOORBELL_BAR, + .default_vbnv = "RyzenAI-npu3-vf", + .device_type = AMDXDNA_DEV_TYPE_UMQ, + .dev_priv = &npu3_dev_vf_priv, + .fw_feature_tbl = npu3_fw_feature_table, + .ops = &aie4_vf_ops, +}; diff --git a/drivers/accel/amdxdna/npu4_regs.c b/drivers/accel/amdxdna/npu4_regs.c index 619bff042e52..15a161384625 100644 --- a/drivers/accel/amdxdna/npu4_regs.c +++ b/drivers/accel/amdxdna/npu4_regs.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -63,6 +64,8 @@ #define NPU4_SMU_BAR_BASE MMNPU_APERTURE4_BASE #define NPU4_SRAM_BAR_BASE MMNPU_APERTURE1_BASE +#define NPU4_DPM_TOPS(ndev, hclk) (4096 * (ndev)->total_col * (hclk) / 1000000) + const struct rt_config npu4_default_rt_cfg[] = { { 5, 1, AIE2_RT_CFG_INIT }, /* PDI APP LOAD MODE */ { 10, 1, AIE2_RT_CFG_INIT }, /* DEBUG BUF */ @@ -88,22 +91,77 @@ const struct dpm_clk_freq npu4_dpm_clk_table[] = { { 0 } }; -const struct aie2_fw_feature_tbl npu4_fw_feature_table[] = { +const struct amdxdna_fw_feature_tbl npu4_fw_feature_table[] = { { .major = 6, .min_minor = 12 }, - { .features = BIT_U64(AIE2_NPU_COMMAND), .major = 6, .min_minor = 15 }, { .features = BIT_U64(AIE2_PREEMPT), .major = 6, .min_minor = 12 }, { .features = BIT_U64(AIE2_TEMPORAL_ONLY), .major = 6, .min_minor = 12 }, + { .features = BIT_U64(AIE2_NPU_COMMAND), .major = 6, .min_minor = 15 }, + { .features = BIT_U64(AIE2_UPDATE_PROPERTY), .major = 6, .min_minor = 15 }, { .features = BIT_U64(AIE2_APP_HEALTH), .major = 6, .min_minor = 18 }, + { .features = BIT_U64(AIE2_ADD_HOST_BUFFER), .major = 6, .min_minor = 18 }, + { .features = BIT_U64(AIE2_GET_DEV_REVISION), .major = 6, .min_minor = 24 }, { .features = AIE2_ALL_FEATURES, .major = 7 }, { 0 } }; +static int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) +{ + int ret; + + ret = aie_smu_set_dpm(ndev->aie.smu_hdl, dpm_level); + if (ret) + return ret; + + ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk; + ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk; + ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk); + ndev->curr_tops = NPU4_DPM_TOPS(ndev, ndev->hclk_freq); + + XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n", + ndev->npuclk_freq, ndev->hclk_freq); + + return 0; +} + +static int npu4_update_counters(struct amdxdna_dev_hdl *ndev) +{ + struct amd_pmf_npu_metrics npu_metrics; + int ret; + + ret = AIE2_GET_PMF_NPU_METRICS(&npu_metrics); + if (ret) + return ret; + + ndev->npuclk_freq = npu_metrics.mpnpuclk_freq; + ndev->hclk_freq = npu_metrics.npuclk_freq; + ndev->curr_tops = NPU4_DPM_TOPS(ndev, ndev->hclk_freq); + + return 0; +} + +const struct aie2_hw_ops npu4_hw_ops = { + .set_dpm = npu4_set_dpm, + .update_counters = npu4_update_counters, +}; + +const struct amdxdna_rev_vbnv npu4_rev_vbnv_tbl[] = { + { AIE2_DEV_REVISION_STXA, "NPU Strix" }, + { AIE2_DEV_REVISION_STXB, "NPU Strix" }, + { AIE2_DEV_REVISION_KRK1, "NPU Krackan 1" }, + { AIE2_DEV_REVISION_KRK2, "NPU Krackan 2" }, + { AIE2_DEV_REVISION_HALO, "NPU Strix Halo" }, + { AIE2_DEV_REVISION_GPT1, "NPU Gorgon Point 1" }, + { AIE2_DEV_REVISION_GPT2, "NPU Gorgon Point 2" }, + { AIE2_DEV_REVISION_GPT3, "NPU Gorgon Point 3" }, + { 0 } +}; + static const struct amdxdna_dev_priv npu4_dev_priv = { .fw_path = "amdnpu/17f0_10/", .rt_config = npu4_default_rt_cfg, .dpm_clk_tbl = npu4_dpm_clk_table, - .fw_feature_tbl = npu4_fw_feature_table, .col_align = COL_ALIGN_NATURE, + .col_opc = 4096, .mbox_dev_addr = NPU4_MBOX_BAR_BASE, .mbox_size = 0, /* Use BAR size */ .sram_dev_addr = NPU4_SRAM_BAR_BASE, @@ -129,9 +187,7 @@ static const struct amdxdna_dev_priv npu4_dev_priv = { DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU4_SMU, MP1_C2PMSG_61), DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU4_SMU, MP1_C2PMSG_60), }, - .hw_ops = { - .set_dpm = npu4_set_dpm, - }, + .hw_ops = &npu4_hw_ops }; const struct amdxdna_dev_info dev_npu4_info = { @@ -144,8 +200,11 @@ const struct amdxdna_dev_info dev_npu4_info = { .dev_mem_buf_shift = 15, /* 32 KiB aligned */ .dev_mem_base = AIE2_DEVM_BASE, .dev_mem_size = AIE2_DEVM_SIZE, - .vbnv = "RyzenAI-npu4", + .default_vbnv = "RyzenAI-npu4", + .dev_heap_max_size = AIE2_DEVM_MAX_SIZE, .device_type = AMDXDNA_DEV_TYPE_KMQ, + .rev_vbnv_tbl = npu4_rev_vbnv_tbl, .dev_priv = &npu4_dev_priv, + .fw_feature_tbl = npu4_fw_feature_table, .ops = &aie2_ops, /* NPU4 can share NPU1's callback */ }; diff --git a/drivers/accel/amdxdna/npu5_regs.c b/drivers/accel/amdxdna/npu5_regs.c index c0ac5daf32ee..306b359d0cd3 100644 --- a/drivers/accel/amdxdna/npu5_regs.c +++ b/drivers/accel/amdxdna/npu5_regs.c @@ -66,8 +66,8 @@ static const struct amdxdna_dev_priv npu5_dev_priv = { .fw_path = "amdnpu/17f0_11/", .rt_config = npu4_default_rt_cfg, .dpm_clk_tbl = npu4_dpm_clk_table, - .fw_feature_tbl = npu4_fw_feature_table, .col_align = COL_ALIGN_NATURE, + .col_opc = 4096, .mbox_dev_addr = NPU5_MBOX_BAR_BASE, .mbox_size = 0, /* Use BAR size */ .sram_dev_addr = NPU5_SRAM_BAR_BASE, @@ -93,9 +93,7 @@ static const struct amdxdna_dev_priv npu5_dev_priv = { DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU5_SMU, MP1_C2PMSG_61), DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU5_SMU, MP1_C2PMSG_60), }, - .hw_ops = { - .set_dpm = npu4_set_dpm, - }, + .hw_ops = &npu4_hw_ops }; const struct amdxdna_dev_info dev_npu5_info = { @@ -108,8 +106,11 @@ const struct amdxdna_dev_info dev_npu5_info = { .dev_mem_buf_shift = 15, /* 32 KiB aligned */ .dev_mem_base = AIE2_DEVM_BASE, .dev_mem_size = AIE2_DEVM_SIZE, - .vbnv = "RyzenAI-npu5", + .default_vbnv = "RyzenAI-npu5", + .dev_heap_max_size = AIE2_DEVM_MAX_SIZE, .device_type = AMDXDNA_DEV_TYPE_KMQ, + .rev_vbnv_tbl = npu4_rev_vbnv_tbl, .dev_priv = &npu5_dev_priv, + .fw_feature_tbl = npu4_fw_feature_table, .ops = &aie2_ops, }; diff --git a/drivers/accel/amdxdna/npu6_regs.c b/drivers/accel/amdxdna/npu6_regs.c index ce591ed0d483..e68637d2a228 100644 --- a/drivers/accel/amdxdna/npu6_regs.c +++ b/drivers/accel/amdxdna/npu6_regs.c @@ -66,8 +66,8 @@ static const struct amdxdna_dev_priv npu6_dev_priv = { .fw_path = "amdnpu/17f0_10/", .rt_config = npu4_default_rt_cfg, .dpm_clk_tbl = npu4_dpm_clk_table, - .fw_feature_tbl = npu4_fw_feature_table, .col_align = COL_ALIGN_NATURE, + .col_opc = 4096, .mbox_dev_addr = NPU6_MBOX_BAR_BASE, .mbox_size = 0, /* Use BAR size */ .sram_dev_addr = NPU6_SRAM_BAR_BASE, @@ -93,9 +93,7 @@ static const struct amdxdna_dev_priv npu6_dev_priv = { DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU6_SMU, MP1_C2PMSG_61), DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU6_SMU, MP1_C2PMSG_60), }, - .hw_ops = { - .set_dpm = npu4_set_dpm, - }, + .hw_ops = &npu4_hw_ops }; @@ -109,8 +107,11 @@ const struct amdxdna_dev_info dev_npu6_info = { .dev_mem_buf_shift = 15, /* 32 KiB aligned */ .dev_mem_base = AIE2_DEVM_BASE, .dev_mem_size = AIE2_DEVM_SIZE, - .vbnv = "RyzenAI-npu6", + .default_vbnv = "RyzenAI-npu6", + .dev_heap_max_size = AIE2_DEVM_MAX_SIZE, .device_type = AMDXDNA_DEV_TYPE_KMQ, + .rev_vbnv_tbl = npu4_rev_vbnv_tbl, .dev_priv = &npu6_dev_priv, + .fw_feature_tbl = npu4_fw_feature_table, .ops = &aie2_ops, }; diff --git a/drivers/accel/ethosu/ethosu_job.c b/drivers/accel/ethosu/ethosu_job.c index ec85f4156744..b76924645aaa 100644 --- a/drivers/accel/ethosu/ethosu_job.c +++ b/drivers/accel/ethosu/ethosu_job.c @@ -296,7 +296,6 @@ int ethosu_job_init(struct ethosu_device *edev) struct device *dev = edev->base.dev; struct drm_sched_init_args args = { .ops = ðosu_sched_ops, - .num_rqs = DRM_SCHED_PRIORITY_COUNT, .credit_limit = 1, .timeout = msecs_to_jiffies(JOB_TIMEOUT_MS), .name = dev_name(dev), @@ -417,9 +416,21 @@ static int ethosu_ioctl_submit_job(struct drm_device *dev, struct drm_file *file struct drm_gem_object *gem; /* Can only omit a BO handle if the region is not used or used for SRAM */ - if (!job->region_bo_handles[i] && - (!cmd_info->region_size[i] || (i == ETHOSU_SRAM_REGION && job->sram_size))) - continue; + if (!job->region_bo_handles[i]) { + if (!cmd_info->region_size[i]) + continue; + if (i == ETHOSU_SRAM_REGION) { + if (cmd_info->region_size[i] <= edev->npu_info.sram_size) + continue; + + dev_err(dev->dev, + "cmd stream region %d size greater than SRAM size (%llu > %u)\n", + i, cmd_info->region_size[i], + edev->npu_info.sram_size); + ret = -EINVAL; + goto out_cleanup_job; + } + } if (job->region_bo_handles[i] && !cmd_info->region_size[i]) { dev_err(dev->dev, diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c index 2801378e3e19..35e506074d5f 100644 --- a/drivers/accel/ivpu/ivpu_drv.c +++ b/drivers/accel/ivpu/ivpu_drv.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2020-2025 Intel Corporation + * Copyright (C) 2020-2026 Intel Corporation */ #include @@ -234,7 +234,7 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_f args->value = vdev->platform; break; case DRM_IVPU_PARAM_CORE_CLOCK_RATE: - args->value = ivpu_hw_dpu_max_freq_get(vdev); + args->value = ivpu_hw_btrs_pll_ratio_to_hz(vdev, vdev->hw->pll.max_ratio); break; case DRM_IVPU_PARAM_NUM_CONTEXTS: args->value = file_priv->user_limits->max_ctx_count; @@ -487,6 +487,10 @@ int ivpu_boot(struct ivpu_device *vdev) ret = ivpu_hw_sched_init(vdev); if (ret) goto err_disable_ipc; + + ret = ivpu_hw_btrs_cfg_freq_init(vdev); + if (ret) + goto err_disable_ipc; } return 0; @@ -537,6 +541,26 @@ static const struct file_operations ivpu_fops = { #endif }; +static int ivpu_gem_prime_handle_to_fd(struct drm_device *dev, struct drm_file *file_priv, + u32 handle, u32 flags, int *prime_fd) +{ + struct drm_gem_object *obj; + + obj = drm_gem_object_lookup(file_priv, handle); + if (!obj) + return -ENOENT; + + if (drm_gem_is_imported(obj)) { + /* Do not allow re-exporting */ + drm_gem_object_put(obj); + return -EOPNOTSUPP; + } + + drm_gem_object_put(obj); + + return drm_gem_prime_handle_to_fd(dev, file_priv, handle, flags, prime_fd); +} + static const struct drm_driver driver = { .driver_features = DRIVER_GEM | DRIVER_COMPUTE_ACCEL, @@ -545,6 +569,7 @@ static const struct drm_driver driver = { .gem_create_object = ivpu_gem_create_object, .gem_prime_import = ivpu_gem_prime_import, + .prime_handle_to_fd = ivpu_gem_prime_handle_to_fd, .ioctls = ivpu_drm_ioctls, .num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls), diff --git a/drivers/accel/ivpu/ivpu_hw.h b/drivers/accel/ivpu/ivpu_hw.h index b6d0f0d0dccc..487a918e2fa9 100644 --- a/drivers/accel/ivpu/ivpu_hw.h +++ b/drivers/accel/ivpu/ivpu_hw.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2020-2025 Intel Corporation + * Copyright (C) 2020-2026 Intel Corporation */ #ifndef __IVPU_HW_H__ @@ -28,6 +28,7 @@ struct ivpu_hw_info { struct ivpu_addr_range dma; } ranges; struct { + /* Hardware min and max pll ratio */ u8 min_ratio; u8 max_ratio; /* @@ -35,6 +36,9 @@ struct ivpu_hw_info { * performance to power ratio at this frequency. */ u8 pn_ratio; + /* Pll ratios configured via sysfs interface */ + u8 cfg_min_ratio; + u8 cfg_max_ratio; u32 profiling_freq; } pll; struct { @@ -80,16 +84,6 @@ static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range) return range->end - range->start; } -static inline u32 ivpu_hw_dpu_max_freq_get(struct ivpu_device *vdev) -{ - return ivpu_hw_btrs_dpu_max_freq_get(vdev); -} - -static inline u32 ivpu_hw_dpu_freq_get(struct ivpu_device *vdev) -{ - return ivpu_hw_btrs_dpu_freq_get(vdev); -} - static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev) { ivpu_hw_ip_irq_clear(vdev); diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.c b/drivers/accel/ivpu/ivpu_hw_btrs.c index 06e65c592618..dac935164e11 100644 --- a/drivers/accel/ivpu/ivpu_hw_btrs.c +++ b/drivers/accel/ivpu/ivpu_hw_btrs.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2020-2025 Intel Corporation + * Copyright (C) 2020-2026 Intel Corporation */ #include @@ -11,6 +11,7 @@ #include "ivpu_hw_btrs_lnl_reg.h" #include "ivpu_hw_btrs_mtl_reg.h" #include "ivpu_hw_reg_io.h" +#include "ivpu_jsm_msg.h" #include "ivpu_pm.h" #define BTRS_MTL_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR)) | \ @@ -33,8 +34,7 @@ #define PLL_CDYN_DEFAULT 0x80 #define PLL_EPP_DEFAULT 0x80 -#define PLL_REF_CLK_FREQ 50000000ull -#define PLL_RATIO_TO_FREQ(x) ((x) * PLL_REF_CLK_FREQ) +#define PLL_REF_CLK_FREQ_MHZ 50 #define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC) #define IDLE_TIMEOUT_US (5 * USEC_PER_MSEC) @@ -59,8 +59,6 @@ #define DCT_ENABLE 0x1 #define DCT_DISABLE 0x0 -static u32 pll_ratio_to_dpu_freq(struct ivpu_device *vdev, u32 ratio); - int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev) { REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, BTRS_MTL_ALL_IRQ_MASK); @@ -111,6 +109,8 @@ void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev) hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, hw->pll.min_ratio, hw->pll.max_ratio); hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, hw->pll.max_ratio); hw->pll.pn_ratio = clamp_t(u8, hw->pll.pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio); + hw->pll.cfg_max_ratio = hw->pll.max_ratio; + hw->pll.cfg_min_ratio = hw->pll.min_ratio; } static bool tile_disable_check(u32 config) @@ -341,8 +341,8 @@ int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable) prepare_wp_request(vdev, &wp, enable); - ivpu_dbg(vdev, PM, "PLL workpoint request: %lu MHz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n", - pll_ratio_to_dpu_freq(vdev, wp.target) / HZ_PER_MHZ, wp.cfg, wp.epp, wp.cdyn); + ivpu_dbg(vdev, PM, "PLL workpoint request: %u MHz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n", + ivpu_hw_btrs_pll_ratio_to_mhz(vdev, wp.target), wp.cfg, wp.epp, wp.cdyn); ret = wp_request_send(vdev, &wp); if (ret) { @@ -598,35 +598,101 @@ static u32 pll_config_get_lnl(struct ivpu_device *vdev) return REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ); } -static u32 pll_ratio_to_dpu_freq_mtl(u16 ratio) +static u32 pll_ratio_to_mhz_mtl(u8 pll_ratio) { - return (PLL_RATIO_TO_FREQ(ratio) * 2) / 3; + return (pll_ratio * PLL_REF_CLK_FREQ_MHZ * 2) / 3; } -static u32 pll_ratio_to_dpu_freq_lnl(u16 ratio) +static u32 pll_ratio_to_mhz_lnl(u8 pll_ratio) { - return PLL_RATIO_TO_FREQ(ratio) / 2; + return (pll_ratio * PLL_REF_CLK_FREQ_MHZ) / 2; } -static u32 pll_ratio_to_dpu_freq(struct ivpu_device *vdev, u32 ratio) +u32 ivpu_hw_btrs_pll_ratio_to_mhz(struct ivpu_device *vdev, u8 pll_ratio) { if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) - return pll_ratio_to_dpu_freq_mtl(ratio); + return pll_ratio_to_mhz_mtl(pll_ratio); else - return pll_ratio_to_dpu_freq_lnl(ratio); + return pll_ratio_to_mhz_lnl(pll_ratio); } -u32 ivpu_hw_btrs_dpu_max_freq_get(struct ivpu_device *vdev) +u32 ivpu_hw_btrs_pll_ratio_to_hz(struct ivpu_device *vdev, u8 pll_ratio) { - return pll_ratio_to_dpu_freq(vdev, vdev->hw->pll.max_ratio); + return ivpu_hw_btrs_pll_ratio_to_mhz(vdev, pll_ratio) * HZ_PER_MHZ; } -u32 ivpu_hw_btrs_dpu_freq_get(struct ivpu_device *vdev) +u32 ivpu_hw_btrs_current_freq_get(struct ivpu_device *vdev) { if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) - return pll_ratio_to_dpu_freq_mtl(pll_config_get_mtl(vdev)); + return pll_ratio_to_mhz_mtl(pll_config_get_mtl(vdev)); else - return pll_ratio_to_dpu_freq_lnl(pll_config_get_lnl(vdev)); + return pll_ratio_to_mhz_lnl(pll_config_get_lnl(vdev)); +} + +static int ivpu_hw_btrs_cfg_freq_set(struct ivpu_device *vdev, u8 cfg_min_ratio, u8 cfg_max_ratio) +{ + u8 min_ratio = clamp_t(u8, cfg_min_ratio, vdev->hw->pll.min_ratio, cfg_max_ratio); + u8 pn_ratio = clamp_t(u8, vdev->hw->pll.pn_ratio, min_ratio, cfg_max_ratio); + int ret; + + ivpu_dbg(vdev, PM, "Set frequency range to min: %u, pn: %u, max: %u MHz\n", + ivpu_hw_btrs_pll_ratio_to_mhz(vdev, min_ratio), + ivpu_hw_btrs_pll_ratio_to_mhz(vdev, pn_ratio), + ivpu_hw_btrs_pll_ratio_to_mhz(vdev, cfg_max_ratio)); + + ret = ivpu_rpm_get(vdev); + if (ret < 0) + return ret; + + ret = ivpu_jsm_msg_freq_config(vdev, min_ratio, pn_ratio, cfg_max_ratio); + ivpu_rpm_put(vdev); + + if (ret) { + ivpu_warn(vdev, + "Failed to set frequency to min: %u, pn: %u, max: %u MHz, ret %d\n", + ivpu_hw_btrs_pll_ratio_to_mhz(vdev, min_ratio), + ivpu_hw_btrs_pll_ratio_to_mhz(vdev, pn_ratio), + ivpu_hw_btrs_pll_ratio_to_mhz(vdev, cfg_max_ratio), + ret); + return ret; + } + + vdev->hw->pll.cfg_min_ratio = cfg_min_ratio; + vdev->hw->pll.cfg_max_ratio = cfg_max_ratio; + + return 0; +} + +static u8 dpu_mhz_to_pll_ratio_lnl(u32 freq_mhz) +{ + return clamp_t(u32, freq_mhz / (PLL_REF_CLK_FREQ_MHZ / 2), 0, U8_MAX); +} + +int ivpu_hw_btrs_cfg_max_freq_set(struct ivpu_device *vdev, u32 max_freq_mhz) +{ + u8 ratio = dpu_mhz_to_pll_ratio_lnl(max_freq_mhz); + u8 cfg_max_ratio = clamp_t(u8, ratio, vdev->hw->pll.min_ratio, vdev->hw->pll.max_ratio); + + return ivpu_hw_btrs_cfg_freq_set(vdev, vdev->hw->pll.cfg_min_ratio, cfg_max_ratio); +} + +int ivpu_hw_btrs_cfg_min_freq_set(struct ivpu_device *vdev, u32 min_freq_mhz) +{ + u8 ratio = dpu_mhz_to_pll_ratio_lnl(min_freq_mhz); + u8 cfg_min_ratio = clamp_t(u8, ratio, vdev->hw->pll.min_ratio, vdev->hw->pll.max_ratio); + + return ivpu_hw_btrs_cfg_freq_set(vdev, cfg_min_ratio, vdev->hw->pll.cfg_max_ratio); +} + +int ivpu_hw_btrs_cfg_freq_init(struct ivpu_device *vdev) +{ + if (vdev->hw->pll.min_ratio == vdev->hw->pll.cfg_min_ratio && + vdev->hw->pll.max_ratio == vdev->hw->pll.cfg_max_ratio) + return 0; + + return ivpu_hw_btrs_cfg_freq_set(vdev, + vdev->hw->pll.cfg_min_ratio, + vdev->hw->pll.cfg_max_ratio); } /* Handler for IRQs from Buttress core (irqB) */ @@ -641,8 +707,8 @@ bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq) if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, status)) { u32 pll = pll_config_get_mtl(vdev); - ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz", - pll, pll_ratio_to_dpu_freq_mtl(pll) / HZ_PER_MHZ); + ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %u MHz", + pll, pll_ratio_to_mhz_mtl(pll)); } if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, status)) { @@ -695,8 +761,8 @@ bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq) if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, status)) { u32 pll = pll_config_get_lnl(vdev); - ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz", - pll, pll_ratio_to_dpu_freq_lnl(pll) / HZ_PER_MHZ); + ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %u MHz", + pll, pll_ratio_to_mhz_lnl(pll)); } if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, status)) { diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.h b/drivers/accel/ivpu/ivpu_hw_btrs.h index c4c10e22f30f..d6343d734570 100644 --- a/drivers/accel/ivpu/ivpu_hw_btrs.h +++ b/drivers/accel/ivpu/ivpu_hw_btrs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2020-2025 Intel Corporation + * Copyright (C) 2020-2026 Intel Corporation */ #ifndef __IVPU_HW_BTRS_H__ @@ -31,8 +31,12 @@ int ivpu_hw_btrs_ip_reset(struct ivpu_device *vdev); void ivpu_hw_btrs_profiling_freq_reg_set_lnl(struct ivpu_device *vdev); void ivpu_hw_btrs_ats_print_lnl(struct ivpu_device *vdev); void ivpu_hw_btrs_clock_relinquish_disable_lnl(struct ivpu_device *vdev); -u32 ivpu_hw_btrs_dpu_max_freq_get(struct ivpu_device *vdev); -u32 ivpu_hw_btrs_dpu_freq_get(struct ivpu_device *vdev); +u32 ivpu_hw_btrs_pll_ratio_to_mhz(struct ivpu_device *vdev, u8 pll_ratio); +u32 ivpu_hw_btrs_pll_ratio_to_hz(struct ivpu_device *vdev, u8 pll_ratio); +u32 ivpu_hw_btrs_current_freq_get(struct ivpu_device *vdev); +int ivpu_hw_btrs_cfg_min_freq_set(struct ivpu_device *vdev, u32 freq_mhz); +int ivpu_hw_btrs_cfg_max_freq_set(struct ivpu_device *vdev, u32 freq_mhz); +int ivpu_hw_btrs_cfg_freq_init(struct ivpu_device *vdev); bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq); bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq); int ivpu_hw_btrs_dct_get_request(struct ivpu_device *vdev, bool *enable); diff --git a/drivers/accel/ivpu/ivpu_hw_ip.c b/drivers/accel/ivpu/ivpu_hw_ip.c index 37f95a0551ed..81f0b1f8f5a6 100644 --- a/drivers/accel/ivpu/ivpu_hw_ip.c +++ b/drivers/accel/ivpu/ivpu_hw_ip.c @@ -307,18 +307,6 @@ static void pwr_island_trickle_drive_40xx(struct ivpu_device *vdev, bool enable) } static void pwr_island_drive_37xx(struct ivpu_device *vdev, bool enable) -{ - u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0); - - if (enable) - val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); - else - val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); - - REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val); -} - -static void pwr_island_drive_40xx(struct ivpu_device *vdev, bool enable) { u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0); @@ -330,6 +318,18 @@ static void pwr_island_drive_40xx(struct ivpu_device *vdev, bool enable) REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val); } +static void pwr_island_drive_40xx(struct ivpu_device *vdev, bool enable) +{ + u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0); + + if (enable) + val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); + else + val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); + + REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val); +} + static void pwr_island_enable(struct ivpu_device *vdev) { if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { diff --git a/drivers/accel/ivpu/ivpu_jsm_msg.c b/drivers/accel/ivpu/ivpu_jsm_msg.c index 07b1d6f615a9..17b42a76aef9 100644 --- a/drivers/accel/ivpu/ivpu_jsm_msg.c +++ b/drivers/accel/ivpu/ivpu_jsm_msg.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2020-2024 Intel Corporation + * Copyright (C) 2020-2026 Intel Corporation */ #include "ivpu_drv.h" @@ -86,6 +86,9 @@ const char *ivpu_jsm_msg_type_to_str(enum vpu_ipc_msg_type type) IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_ENABLE_DONE); IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_DISABLE); IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_DISABLE_DONE); + IVPU_CASE_TO_STR(VPU_JSM_MSG_FREQ_CONFIG); + IVPU_CASE_TO_STR(VPU_JSM_MSG_FREQ_CONFIG_RSP); + IVPU_CASE_TO_STR(VPU_JSM_MSG_RESERVED_111E); } #undef IVPU_CASE_TO_STR @@ -571,3 +574,16 @@ int ivpu_jsm_state_dump_no_reply(struct ivpu_device *vdev) return ivpu_ipc_send_and_wait(vdev, &req, VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.state_dump_msg); } + +int ivpu_jsm_msg_freq_config(struct ivpu_device *vdev, u16 min_ratio, u16 pn_ratio, u16 max_ratio) +{ + struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_FREQ_CONFIG}; + struct vpu_jsm_msg resp; + + req.payload.freq_config.min_freq_pll_ratio = min_ratio; + req.payload.freq_config.pn_freq_pll_ratio = pn_ratio; + req.payload.freq_config.max_freq_pll_ratio = max_ratio; + + return ivpu_ipc_send_receive_internal(vdev, &req, VPU_JSM_MSG_FREQ_CONFIG_RSP, &resp, + VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm); +} diff --git a/drivers/accel/ivpu/ivpu_jsm_msg.h b/drivers/accel/ivpu/ivpu_jsm_msg.h index a74f5a0b0d93..28ffe07422b0 100644 --- a/drivers/accel/ivpu/ivpu_jsm_msg.h +++ b/drivers/accel/ivpu/ivpu_jsm_msg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2020-2024 Intel Corporation + * Copyright (C) 2020-2026 Intel Corporation */ #ifndef __IVPU_JSM_MSG_H__ @@ -45,5 +45,6 @@ int ivpu_jsm_dct_enable(struct ivpu_device *vdev, u32 active_us, u32 inactive_us int ivpu_jsm_dct_disable(struct ivpu_device *vdev); int ivpu_jsm_state_dump(struct ivpu_device *vdev); int ivpu_jsm_state_dump_no_reply(struct ivpu_device *vdev); +int ivpu_jsm_msg_freq_config(struct ivpu_device *vdev, u16 min_ratio, u16 pn_ratio, u16 max_ratio); #endif diff --git a/drivers/accel/ivpu/ivpu_sysfs.c b/drivers/accel/ivpu/ivpu_sysfs.c index d250a10caca9..95d201b3b8aa 100644 --- a/drivers/accel/ivpu/ivpu_sysfs.c +++ b/drivers/accel/ivpu/ivpu_sysfs.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2024-2025 Intel Corporation + * Copyright (C) 2024-2026 Intel Corporation */ #include @@ -82,8 +82,7 @@ static DEVICE_ATTR_RO(npu_memory_utilization); * - "OS" - Operating System Scheduler mode * */ -static ssize_t -sched_mode_show(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t sched_mode_show(struct device *dev, struct device_attribute *attr, char *buf) { struct drm_device *drm = dev_get_drvdata(dev); struct ivpu_device *vdev = to_ivpu_device(drm); @@ -94,47 +93,162 @@ sched_mode_show(struct device *dev, struct device_attribute *attr, char *buf) static DEVICE_ATTR_RO(sched_mode); /** - * DOC: npu_max_frequency + * DOC: NPU frequency control and information * - * The npu_max_frequency shows maximum frequency in MHz of the NPU's data - * processing unit + * Hardware frequency capabilities: + * freq/hw_min_freq - Minimum frequency supported by the NPU hardware. + * freq/hw_max_freq - Maximum frequency supported by the NPU hardware. + * freq/hw_efficient_freq - Most efficient operating frequency for the NPU. + * + * Configurable frequency limits (50XX devices and newer): + * freq/set_min_freq - Configured minimum operating frequency. + * freq/set_max_freq - Configured maximum operating frequency. + * + * Clamping behavior: Values written to set_min_freq and set_max_freq are + * clamped to hardware limits. If set_min_freq exceeds set_max_freq, the driver + * clamps set_min_freq to set_max_freq when selecting the operating frequency. + * + * Current operating frequency: + * freq/current_freq - Current frequency in MHz. Valid only when the device is + * active; returns 0 when idle. May be lower than the requested range due to + * power or thermal constraints. + * + * Legacy attributes (backward compatibility): + * npu_max_frequency_mhz - Alias for freq/hw_max_freq. + * npu_current_frequency_mhz - Alias for freq/current_freq. */ -static ssize_t -npu_max_frequency_mhz_show(struct device *dev, struct device_attribute *attr, char *buf) + +static ssize_t hw_min_freq_show(struct device *dev, struct device_attribute *attr, char *buf) { struct drm_device *drm = dev_get_drvdata(dev); struct ivpu_device *vdev = to_ivpu_device(drm); - u32 freq = ivpu_hw_dpu_max_freq_get(vdev); + u32 freq_mhz = ivpu_hw_btrs_pll_ratio_to_mhz(vdev, vdev->hw->pll.min_ratio); - return sysfs_emit(buf, "%lu\n", freq / HZ_PER_MHZ); + return sysfs_emit(buf, "%u\n", freq_mhz); } -static DEVICE_ATTR_RO(npu_max_frequency_mhz); +static DEVICE_ATTR_RO(hw_min_freq); -/** - * DOC: npu_current_frequency_mhz - * - * The npu_current_frequency_mhz shows current frequency in MHz of the NPU's - * data processing unit - */ -static ssize_t -npu_current_frequency_mhz_show(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t hw_efficient_freq_show(struct device *dev, struct device_attribute *attr, char *buf) { struct drm_device *drm = dev_get_drvdata(dev); struct ivpu_device *vdev = to_ivpu_device(drm); - u32 freq = 0; + u32 freq_mhz = ivpu_hw_btrs_pll_ratio_to_mhz(vdev, vdev->hw->pll.pn_ratio); + + return sysfs_emit(buf, "%u\n", freq_mhz); +} + +static DEVICE_ATTR_RO(hw_efficient_freq); + +static ssize_t hw_max_freq_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct ivpu_device *vdev = to_ivpu_device(drm); + u32 freq_mhz = ivpu_hw_btrs_pll_ratio_to_mhz(vdev, vdev->hw->pll.max_ratio); + + return sysfs_emit(buf, "%u\n", freq_mhz); +} + +static DEVICE_ATTR_RO(hw_max_freq); + +static ssize_t set_min_freq_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct ivpu_device *vdev = to_ivpu_device(drm); + u32 freq_mhz = ivpu_hw_btrs_pll_ratio_to_mhz(vdev, vdev->hw->pll.cfg_min_ratio); + + return sysfs_emit(buf, "%u\n", freq_mhz); +} + +static ssize_t +set_min_freq_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct ivpu_device *vdev = to_ivpu_device(drm); + u32 freq_mhz; + int ret; + + ret = kstrtou32(buf, 10, &freq_mhz); + if (ret) + return ret; + + ret = ivpu_hw_btrs_cfg_min_freq_set(vdev, freq_mhz); + if (ret) + return ret; + + return count; +} + +static DEVICE_ATTR_RW(set_min_freq); + +static ssize_t set_max_freq_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct ivpu_device *vdev = to_ivpu_device(drm); + u32 freq_mhz = ivpu_hw_btrs_pll_ratio_to_mhz(vdev, vdev->hw->pll.cfg_max_ratio); + + return sysfs_emit(buf, "%u\n", freq_mhz); +} + +static ssize_t +set_max_freq_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct ivpu_device *vdev = to_ivpu_device(drm); + u32 freq_mhz; + int ret; + + ret = kstrtou32(buf, 10, &freq_mhz); + if (ret) + return ret; + + /* Convert MHz to Hz and set max frequency */ + ret = ivpu_hw_btrs_cfg_max_freq_set(vdev, freq_mhz); + if (ret) + return ret; + + return count; +} + +static DEVICE_ATTR_RW(set_max_freq); + +static ssize_t current_freq_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct ivpu_device *vdev = to_ivpu_device(drm); + u32 freq_mhz = 0; /* Read frequency only if device is active, otherwise frequency is 0 */ if (pm_runtime_get_if_active(vdev->drm.dev) > 0) { - freq = ivpu_hw_dpu_freq_get(vdev); + freq_mhz = ivpu_hw_btrs_current_freq_get(vdev); pm_runtime_put_autosuspend(vdev->drm.dev); } - return sysfs_emit(buf, "%lu\n", freq / HZ_PER_MHZ); + return sysfs_emit(buf, "%u\n", freq_mhz); } -static DEVICE_ATTR_RO(npu_current_frequency_mhz); +static DEVICE_ATTR_RO(current_freq); + +/* Alias to current_freq for legacy compat */ +static struct device_attribute dev_attr_npu_max_frequency_mhz = + __ATTR(npu_max_frequency_mhz, 0444, hw_max_freq_show, NULL); + +static struct device_attribute dev_attr_npu_current_frequency_mhz = + __ATTR(npu_current_frequency_mhz, 0444, current_freq_show, NULL); + +static struct attribute *ivpu_freq_attrs[] = { + &dev_attr_hw_min_freq.attr, + &dev_attr_hw_efficient_freq.attr, + &dev_attr_hw_max_freq.attr, + &dev_attr_current_freq.attr, + NULL, +}; + +static struct attribute_group ivpu_freq_attr_group = { + .name = "freq", + .attrs = ivpu_freq_attrs, +}; static struct attribute *ivpu_dev_attrs[] = { &dev_attr_npu_busy_time_us.attr, @@ -154,6 +268,32 @@ void ivpu_sysfs_init(struct ivpu_device *vdev) int ret; ret = devm_device_add_group(vdev->drm.dev, &ivpu_dev_attr_group); - if (ret) - ivpu_warn(vdev, "Failed to add group to device, ret %d", ret); + if (ret) { + ivpu_warn(vdev, "Failed to add sysfs group to device, ret %d", ret); + return; + } + + ret = devm_device_add_group(vdev->drm.dev, &ivpu_freq_attr_group); + if (ret) { + ivpu_warn(vdev, "Failed to add sysfs freq group, ret %d", ret); + return; + } + + if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_50XX) { + ret = sysfs_add_file_to_group(&vdev->drm.dev->kobj, + &dev_attr_set_min_freq.attr, + "freq"); + if (ret) { + ivpu_warn(vdev, "Failed to add sysfs set_min_freq to device, ret %d", ret); + return; + } + + ret = sysfs_add_file_to_group(&vdev->drm.dev->kobj, + &dev_attr_set_max_freq.attr, + "freq"); + if (ret) { + ivpu_warn(vdev, "Failed to add sysfs set_max_freq to device, ret %d", ret); + return; + } + } } diff --git a/drivers/accel/ivpu/vpu_jsm_api.h b/drivers/accel/ivpu/vpu_jsm_api.h index bca6a44dc041..6d58d04cc0c4 100644 --- a/drivers/accel/ivpu/vpu_jsm_api.h +++ b/drivers/accel/ivpu/vpu_jsm_api.h @@ -23,7 +23,7 @@ /* * Minor version changes when API backward compatibility is preserved. */ -#define VPU_JSM_API_VER_MINOR 33 +#define VPU_JSM_API_VER_MINOR 34 /* * API header changed (field names, documentation, formatting) but API itself has not been changed @@ -604,6 +604,16 @@ enum vpu_ipc_msg_type { * This command has no payload */ VPU_JSM_MSG_DCT_DISABLE = 0x111d, + /** + * Reserved command ID to ensure that the following command requests / + * responses have the same lower byte value. + */ + VPU_JSM_MSG_RESERVED_111E = 0x111e, + /** + * Control command: Configure VPU frequency scaling parameters. + * @see vpu_ipc_msg_payload_freq_config + */ + VPU_JSM_MSG_FREQ_CONFIG = 0x111f, /** * Dump VPU state. To be used for debug purposes only. * This command has no payload. @@ -766,6 +776,11 @@ enum vpu_ipc_msg_type { * This command has no payload */ VPU_JSM_MSG_DCT_DISABLE_DONE = 0x221e, + /** + * Response to control command: Configure VPU frequency scaling parameters. + * @see vpu_ipc_msg_payload_freq_config + */ + VPU_JSM_MSG_FREQ_CONFIG_RSP = 0x221f, /** * Response to state dump control command. * This command has no payload. @@ -1650,6 +1665,22 @@ struct vpu_ipc_msg_payload_pwr_dct_control { u32 dct_inactive_us; }; +/** + * Payload for @ref VPU_JSM_MSG_FREQ_CONFIG message. + * + * This payload allows the host to configure the VPU frequency scaling parameters. + */ +struct vpu_ipc_msg_payload_freq_config { + /** Minimum frequency PLL ratio */ + u32 min_freq_pll_ratio; + /** Efficiency frequency PLL ratio */ + u32 pn_freq_pll_ratio; + /** Maximum frequency PLL ratio */ + u32 max_freq_pll_ratio; + /** Reserved for 64-bit alignment */ + u32 reserved_0; +}; + /* * Payloads union, used to define complete message format. */ @@ -1692,6 +1723,7 @@ union vpu_ipc_msg_payload { struct vpu_ipc_msg_payload_hws_resume_engine hws_resume_engine; struct vpu_ipc_msg_payload_pwr_d0i3_enter pwr_d0i3_enter; struct vpu_ipc_msg_payload_pwr_dct_control pwr_dct_control; + struct vpu_ipc_msg_payload_freq_config freq_config; }; /** diff --git a/drivers/accel/qaic/mhi_controller.c b/drivers/accel/qaic/mhi_controller.c index 4d787f77ce41..40e6d262ef21 100644 --- a/drivers/accel/qaic/mhi_controller.c +++ b/drivers/accel/qaic/mhi_controller.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ -/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include #include diff --git a/drivers/accel/qaic/mhi_controller.h b/drivers/accel/qaic/mhi_controller.h index 8939f6ae185e..c1940c839246 100644 --- a/drivers/accel/qaic/mhi_controller.h +++ b/drivers/accel/qaic/mhi_controller.h @@ -1,8 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0-only - * - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef MHICONTROLLERQAIC_H_ #define MHICONTROLLERQAIC_H_ diff --git a/drivers/accel/qaic/qaic.h b/drivers/accel/qaic/qaic.h index fa7a8155658c..02ca99000e2a 100644 --- a/drivers/accel/qaic/qaic.h +++ b/drivers/accel/qaic/qaic.h @@ -1,8 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0-only - * - * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef _QAIC_H_ #define _QAIC_H_ @@ -152,8 +151,6 @@ struct qaic_device { struct list_head cntl_xfer_list; /* Synchronizes MHI control device transactions and its xfer list */ struct mutex cntl_mutex; - /* Array of DBC struct of this device */ - struct dma_bridge_chan *dbc; /* Work queue for tasks related to MHI control device */ struct workqueue_struct *cntl_wq; /* Synchronizes all the users of device during cleanup */ @@ -206,6 +203,8 @@ struct qaic_device { void *ssr_mhi_buf; /* DBC which is under SSR. Sentinel U32_MAX would mean that no SSR in progress */ u32 ssr_dbc; + /* Array of DBC struct of this device */ + struct dma_bridge_chan dbc[] __counted_by(num_dbc); }; struct qaic_drm_device { diff --git a/drivers/accel/qaic/qaic_control.c b/drivers/accel/qaic/qaic_control.c index 43f84d438960..bb94d3556904 100644 --- a/drivers/accel/qaic/qaic_control.c +++ b/drivers/accel/qaic/qaic_control.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ -/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include #include diff --git a/drivers/accel/qaic/qaic_data.c b/drivers/accel/qaic/qaic_data.c index 95300c2f7d8a..ef0351b6dc9b 100644 --- a/drivers/accel/qaic/qaic_data.c +++ b/drivers/accel/qaic/qaic_data.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ -/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include #include @@ -606,8 +606,11 @@ static const struct vm_operations_struct drm_vm_ops = { static int qaic_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { struct qaic_bo *bo = to_qaic_bo(obj); + unsigned long remap_start; unsigned long offset = 0; + unsigned long remap_end; struct scatterlist *sg; + unsigned long length; int ret = 0; if (drm_gem_is_imported(obj)) @@ -615,11 +618,27 @@ static int qaic_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struc for (sg = bo->sgt->sgl; sg; sg = sg_next(sg)) { if (sg_page(sg)) { + /* if sg is too large for the VMA, so truncate it to fit */ + if (check_add_overflow(vma->vm_start, offset, &remap_start)) + return -EINVAL; + if (check_add_overflow(remap_start, sg->length, &remap_end)) + return -EINVAL; + + if (remap_end > vma->vm_end) { + if (check_sub_overflow(vma->vm_end, remap_start, &length)) + return -EINVAL; + } else { + length = sg->length; + } + + if (length == 0) + goto out; + ret = remap_pfn_range(vma, vma->vm_start + offset, page_to_pfn(sg_page(sg)), - sg->length, vma->vm_page_prot); + length, vma->vm_page_prot); if (ret) goto out; - offset += sg->length; + offset += length; } } diff --git a/drivers/accel/qaic/qaic_debugfs.c b/drivers/accel/qaic/qaic_debugfs.c index 8dc4fe5bb560..95c78e12dd61 100644 --- a/drivers/accel/qaic/qaic_debugfs.c +++ b/drivers/accel/qaic/qaic_debugfs.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2020, The Linux Foundation. All rights reserved. */ -/* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include #include @@ -27,6 +27,8 @@ struct bootlog_msg { /* Buffer for bootlog messages */ char str[BOOTLOG_MSG_SIZE]; + /* Length of bootlog message */ + size_t len; /* Root struct of device, used to access device resources */ struct qaic_device *qdev; /* Work struct to schedule work coming on QAIC_LOGGING channel */ @@ -46,18 +48,15 @@ static int bootlog_show(struct seq_file *s, void *unused) { struct bootlog_page *page; struct qaic_device *qdev; - void *page_end; + size_t len; void *log; qdev = s->private; mutex_lock(&qdev->bootlog_mutex); list_for_each_entry(page, &qdev->bootlog, node) { log = page + 1; - page_end = (void *)page + page->offset; - while (log < page_end) { - seq_printf(s, "%s", (char *)log); - log += strlen(log) + 1; - } + len = page->offset - sizeof(*page); + seq_write(s, log, len); } mutex_unlock(&qdev->bootlog_mutex); @@ -182,15 +181,14 @@ static void bootlog_commit(struct qaic_device *qdev, unsigned int size) static void bootlog_log(struct work_struct *work) { struct bootlog_msg *msg = container_of(work, struct bootlog_msg, work); - unsigned int len = strlen(msg->str) + 1; struct qaic_device *qdev = msg->qdev; void *log; mutex_lock(&qdev->bootlog_mutex); - log = bootlog_get_space(qdev, len); + log = bootlog_get_space(qdev, msg->len); if (log) { - memcpy(log, msg, len); - bootlog_commit(qdev, len); + memcpy(log, msg, msg->len); + bootlog_commit(qdev, msg->len); } mutex_unlock(&qdev->bootlog_mutex); @@ -265,14 +263,18 @@ static void qaic_bootlog_mhi_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_r { struct qaic_device *qdev = dev_get_drvdata(&mhi_dev->dev); struct bootlog_msg *msg = mhi_result->buf_addr; + int status = mhi_result->transaction_status; - if (mhi_result->transaction_status) { + if (status && status != -EOVERFLOW) { devm_kfree(&qdev->pdev->dev, msg); return; } - /* Force a null at the end of the transferred string */ - msg->str[mhi_result->bytes_xferd - 1] = 0; + msg->len = mhi_result->bytes_xferd; + + /* Exclude trailing null to normalize AIC100/AIC200 line endings */ + if (msg->len && msg->str[msg->len - 1] == '\0') + msg->len--; queue_work(qdev->bootlog_wq, &msg->work); } diff --git a/drivers/accel/qaic/qaic_debugfs.h b/drivers/accel/qaic/qaic_debugfs.h index 05e74f84cf9f..59a002bab07c 100644 --- a/drivers/accel/qaic/qaic_debugfs.h +++ b/drivers/accel/qaic/qaic_debugfs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2020, The Linux Foundation. All rights reserved. */ -/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef __QAIC_DEBUGFS_H__ #define __QAIC_DEBUGFS_H__ diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c index 63fb8c7b4abc..0acf6cdd44f8 100644 --- a/drivers/accel/qaic/qaic_drv.c +++ b/drivers/accel/qaic/qaic_drv.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ -/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include #include @@ -43,6 +43,7 @@ MODULE_IMPORT_NS("DMA_BUF"); #define QAIC_DESC "Qualcomm Cloud AI Accelerators" #define CNTL_MAJOR 5 #define CNTL_MINOR 0 +#define DBC_NUM 16 struct qaic_device_config { /* Indicates the AIC family the device belongs to */ @@ -405,15 +406,12 @@ static struct qaic_device *create_qdev(struct pci_dev *pdev, struct drm_device *drm; int i, ret; - qdev = devm_kzalloc(dev, sizeof(*qdev), GFP_KERNEL); + qdev = devm_kzalloc(dev, struct_size(qdev, dbc, DBC_NUM), GFP_KERNEL); if (!qdev) return NULL; + qdev->num_dbc = DBC_NUM; qdev->dev_state = QAIC_OFFLINE; - qdev->num_dbc = 16; - qdev->dbc = devm_kcalloc(dev, qdev->num_dbc, sizeof(*qdev->dbc), GFP_KERNEL); - if (!qdev->dbc) - return NULL; qddev = devm_drm_dev_alloc(&pdev->dev, &qaic_accel_driver, struct qaic_drm_device, drm); if (IS_ERR(qddev)) diff --git a/drivers/accel/qaic/qaic_ras.c b/drivers/accel/qaic/qaic_ras.c index cc0b75461e1a..e0205c2cda3d 100644 --- a/drivers/accel/qaic/qaic_ras.c +++ b/drivers/accel/qaic/qaic_ras.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ -/* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -497,11 +496,11 @@ static void decode_ras_msg(struct qaic_device *qdev, struct ras_data *msg) qdev->ce_count++; break; case UE: - if (qdev->ce_count != UINT_MAX) + if (qdev->ue_count != UINT_MAX) qdev->ue_count++; break; case UE_NF: - if (qdev->ce_count != UINT_MAX) + if (qdev->ue_nf_count != UINT_MAX) qdev->ue_nf_count++; break; default: diff --git a/drivers/accel/qaic/qaic_ras.h b/drivers/accel/qaic/qaic_ras.h index d44a4eeeb060..7b3fe9585ed9 100644 --- a/drivers/accel/qaic/qaic_ras.h +++ b/drivers/accel/qaic/qaic_ras.h @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + /* Copyright (c) 2020, The Linux Foundation. All rights reserved. */ #ifndef __QAIC_RAS_H__ diff --git a/drivers/accel/qaic/qaic_ssr.c b/drivers/accel/qaic/qaic_ssr.c index a5bb6078824b..a98928654959 100644 --- a/drivers/accel/qaic/qaic_ssr.c +++ b/drivers/accel/qaic/qaic_ssr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ -/* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include #include diff --git a/drivers/accel/qaic/qaic_ssr.h b/drivers/accel/qaic/qaic_ssr.h index 97ccff305750..af074edbf967 100644 --- a/drivers/accel/qaic/qaic_ssr.h +++ b/drivers/accel/qaic/qaic_ssr.h @@ -1,8 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0-only - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Copyright (c) 2020, The Linux Foundation. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef __QAIC_SSR_H__ #define __QAIC_SSR_H__ diff --git a/drivers/accel/qaic/qaic_timesync.c b/drivers/accel/qaic/qaic_timesync.c index 939462b9958d..9faf71f47bdc 100644 --- a/drivers/accel/qaic/qaic_timesync.c +++ b/drivers/accel/qaic/qaic_timesync.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ + +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include #include diff --git a/drivers/accel/qaic/qaic_timesync.h b/drivers/accel/qaic/qaic_timesync.h index 77b9c2b55057..6aeda1d62a35 100644 --- a/drivers/accel/qaic/qaic_timesync.h +++ b/drivers/accel/qaic/qaic_timesync.h @@ -1,7 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0-only - * - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef __QAIC_TIMESYNC_H__ #define __QAIC_TIMESYNC_H__ diff --git a/drivers/accel/qaic/sahara.c b/drivers/accel/qaic/sahara.c index fd3c3b2d1fd3..9fea294e1d7b 100644 --- a/drivers/accel/qaic/sahara.c +++ b/drivers/accel/qaic/sahara.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include #include diff --git a/drivers/accel/qaic/sahara.h b/drivers/accel/qaic/sahara.h index 640208acc0d1..08037281c80e 100644 --- a/drivers/accel/qaic/sahara.h +++ b/drivers/accel/qaic/sahara.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef __SAHARA_H__ #define __SAHARA_H__ diff --git a/drivers/accel/rocket/rocket_gem.c b/drivers/accel/rocket/rocket_gem.c index b6a385d2edfc..c8084719208a 100644 --- a/drivers/accel/rocket/rocket_gem.c +++ b/drivers/accel/rocket/rocket_gem.c @@ -145,6 +145,8 @@ int rocket_ioctl_prep_bo(struct drm_device *dev, void *data, struct drm_file *fi ret = dma_resv_wait_timeout(gem_obj->resv, DMA_RESV_USAGE_WRITE, true, timeout); if (!ret) ret = timeout ? -ETIMEDOUT : -EBUSY; + else if (ret > 0) + ret = 0; shmem_obj = &to_rocket_bo(gem_obj)->base; diff --git a/drivers/accel/rocket/rocket_job.c b/drivers/accel/rocket/rocket_job.c index ac51bff39833..2f1861f960cc 100644 --- a/drivers/accel/rocket/rocket_job.c +++ b/drivers/accel/rocket/rocket_job.c @@ -437,7 +437,6 @@ int rocket_job_init(struct rocket_core *core) { struct drm_sched_init_args args = { .ops = &rocket_sched_ops, - .num_rqs = DRM_SCHED_PRIORITY_COUNT, .credit_limit = 1, .timeout = msecs_to_jiffies(JOB_TIMEOUT_MS), .name = dev_name(core->dev), diff --git a/drivers/acpi/ac.c b/drivers/acpi/ac.c index e9e970fd8f33..27f31744f29e 100644 --- a/drivers/acpi/ac.c +++ b/drivers/acpi/ac.c @@ -192,11 +192,15 @@ static const struct dmi_system_id ac_dmi_table[] __initconst = { static int acpi_ac_probe(struct platform_device *pdev) { - struct acpi_device *adev = ACPI_COMPANION(&pdev->dev); struct power_supply_config psy_cfg = {}; + struct acpi_device *adev; struct acpi_ac *ac; int result; + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) + return -ENODEV; + ac = kzalloc_obj(struct acpi_ac); if (!ac) return -ENOMEM; diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c index 0a8e02bc8c8b..ec94b09bb747 100644 --- a/drivers/acpi/acpi_pad.c +++ b/drivers/acpi/acpi_pad.c @@ -423,7 +423,11 @@ static void acpi_pad_notify(acpi_handle handle, u32 event, void *data) static int acpi_pad_probe(struct platform_device *pdev) { - struct acpi_device *adev = ACPI_COMPANION(&pdev->dev); + struct acpi_device *adev; + + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) + return -ENODEV; return acpi_dev_install_notify_handler(adev, ACPI_DEVICE_NOTIFY, acpi_pad_notify, adev); diff --git a/drivers/acpi/acpi_tad.c b/drivers/acpi/acpi_tad.c index b406d7a98996..386fc1abcbdc 100644 --- a/drivers/acpi/acpi_tad.c +++ b/drivers/acpi/acpi_tad.c @@ -605,15 +605,12 @@ static umode_t acpi_tad_attr_is_visible(struct kobject *kobj, return 0; } -static const struct attribute_group acpi_tad_attr_group = { +static const struct attribute_group acpi_tad_group = { .attrs = acpi_tad_attrs, .is_visible = acpi_tad_attr_is_visible, }; -static const struct attribute_group *acpi_tad_attr_groups[] = { - &acpi_tad_attr_group, - NULL, -}; +__ATTRIBUTE_GROUPS(acpi_tad); #ifdef CONFIG_RTC_CLASS /* RTC class device interface */ @@ -683,9 +680,8 @@ static int acpi_tad_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t) acpi_tad_rt_to_tm(&rt, &tm_now); - value = ktime_divns(ktime_sub(rtc_tm_to_ktime(t->time), - rtc_tm_to_ktime(tm_now)), NSEC_PER_SEC); - if (value <= 0 || value > U32_MAX) + value = rtc_tm_to_time64(&t->time) - rtc_tm_to_time64(&tm_now); + if (value <= 0 || value >= U32_MAX) return -EINVAL; } @@ -748,8 +744,7 @@ static int acpi_tad_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *t) if (retval != ACPI_TAD_WAKE_DISABLED) { t->enabled = 1; - t->time = rtc_ktime_to_tm(ktime_add_ns(rtc_tm_to_ktime(tm_now), - (u64)retval * NSEC_PER_SEC)); + rtc_time64_to_tm(rtc_tm_to_time64(&tm_now) + retval, &t->time); } else { t->enabled = 0; t->time = tm_now; @@ -795,9 +790,9 @@ static int acpi_tad_disable_timer(struct device *dev, u32 timer_id) return acpi_tad_wake_set(dev, "_STV", timer_id, ACPI_TAD_WAKE_DISABLED); } -static void acpi_tad_remove(struct platform_device *pdev) +static void acpi_tad_remove(void *data) { - struct device *dev = &pdev->dev; + struct device *dev = data; struct acpi_tad_driver_data *dd = dev_get_drvdata(dev); device_init_wakeup(dev, false); @@ -820,10 +815,15 @@ static void acpi_tad_remove(struct platform_device *pdev) static int acpi_tad_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - acpi_handle handle = ACPI_HANDLE(dev); struct acpi_tad_driver_data *dd; + acpi_handle handle; acpi_status status; unsigned long long caps; + int ret; + + handle = ACPI_HANDLE(dev); + if (!handle) + return -ENODEV; /* * Initialization failure messages are mostly about firmware issues, so @@ -863,13 +863,21 @@ static int acpi_tad_probe(struct platform_device *pdev) } /* - * The platform bus type layer tells the ACPI PM domain powers up the - * device, so set the runtime PM status of it to "active". + * The platform bus type probe callback tells the ACPI PM domain to + * power up the device, so set the runtime PM status of it to "active". */ pm_runtime_set_active(dev); pm_runtime_enable(dev); pm_runtime_suspend(dev); + /* + * acpi_tad_remove() needs to run after unregistering the RTC class + * device to avoid racing with the latter's callbacks. + */ + ret = devm_add_action_or_reset(&pdev->dev, acpi_tad_remove, &pdev->dev); + if (ret) + return ret; + if (caps & ACPI_TAD_RT) acpi_tad_register_rtc(dev, caps); @@ -885,10 +893,9 @@ static struct platform_driver acpi_tad_driver = { .driver = { .name = "acpi-tad", .acpi_match_table = acpi_tad_ids, - .dev_groups = acpi_tad_attr_groups, + .dev_groups = acpi_tad_groups, }, .probe = acpi_tad_probe, - .remove = acpi_tad_remove, }; MODULE_DEVICE_TABLE(acpi, acpi_tad_ids); diff --git a/drivers/acpi/apei/einj-core.c b/drivers/acpi/apei/einj-core.c index a9248af078f6..1f3fa2278584 100644 --- a/drivers/acpi/apei/einj-core.c +++ b/drivers/acpi/apei/einj-core.c @@ -401,8 +401,18 @@ static struct acpi_generic_address *einj_get_trigger_parameter_region( return NULL; } + +static bool is_memory_injection(u32 type, u32 flags) +{ + if (flags & SETWA_FLAGS_EINJV2) + return !!(type & ACPI_EINJV2_MEMORY); + if (type & ACPI5_VENDOR_BIT) + return !!(vendor_flags & SETWA_FLAGS_MEM); + return !!(type & MEM_ERROR_MASK) || !!(flags & SETWA_FLAGS_MEM); +} + /* Execute instructions in trigger error action table */ -static int __einj_error_trigger(u64 trigger_paddr, u32 type, +static int __einj_error_trigger(u64 trigger_paddr, u32 type, u32 flags, u64 param1, u64 param2) { struct acpi_einj_trigger trigger_tab; @@ -480,7 +490,7 @@ static int __einj_error_trigger(u64 trigger_paddr, u32 type, * This will cause resource conflict with regular memory. So * remove it from trigger table resources. */ - if ((param_extension || acpi5) && (type & MEM_ERROR_MASK) && param2) { + if ((param_extension || acpi5) && is_memory_injection(type, flags)) { struct apei_resources addr_resources; apei_resources_init(&addr_resources); @@ -660,7 +670,7 @@ static int __einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, return rc; trigger_paddr = apei_exec_ctx_get_output(&ctx); if (notrigger == 0) { - rc = __einj_error_trigger(trigger_paddr, type, param1, param2); + rc = __einj_error_trigger(trigger_paddr, type, flags, param1, param2); if (rc) return rc; } @@ -718,28 +728,6 @@ int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, u64 param3, SETWA_FLAGS_PCIE_SBDF | SETWA_FLAGS_EINJV2))) return -EINVAL; - /* check if type is a valid EINJv2 error type */ - if (is_v2) { - if (!(type & available_error_type_v2)) - return -EINVAL; - } - /* - * We need extra sanity checks for memory errors. - * Other types leap directly to injection. - */ - - /* ensure param1/param2 existed */ - if (!(param_extension || acpi5)) - goto inject; - - /* ensure injection is memory related */ - if (type & ACPI5_VENDOR_BIT) { - if (vendor_flags != SETWA_FLAGS_MEM) - goto inject; - } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) { - goto inject; - } - /* * Injections targeting a CXL 1.0/1.1 port have to be injected * via the einj_cxl_rch_error_inject() path as that does the proper @@ -748,6 +736,23 @@ int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, u64 param3, if (einj_is_cxl_error_type(type) && (flags & SETWA_FLAGS_MEM)) return -EINVAL; + /* check if type is a valid EINJv2 error type */ + if (is_v2) { + if (!(type & available_error_type_v2)) + return -EINVAL; + } + + /* ensure param1/param2 existed */ + if (!(param_extension || acpi5)) + goto inject; + + /* + * We need extra sanity checks for memory errors. + * Other types leap directly to injection. + */ + if (!is_memory_injection(type, flags)) + goto inject; + /* * Disallow crazy address masks that give BIOS leeway to pick * injection address almost anywhere. Insist on page or diff --git a/drivers/acpi/arm64/cpuidle.c b/drivers/acpi/arm64/cpuidle.c index 801f9c450142..c68a5db8ebba 100644 --- a/drivers/acpi/arm64/cpuidle.c +++ b/drivers/acpi/arm64/cpuidle.c @@ -16,7 +16,7 @@ static int psci_acpi_cpu_init_idle(unsigned int cpu) { - int i, count; + int i; struct acpi_lpi_state *lpi; struct acpi_processor *pr = per_cpu(processors, cpu); @@ -30,14 +30,10 @@ static int psci_acpi_cpu_init_idle(unsigned int cpu) if (!psci_ops.cpu_suspend) return -EOPNOTSUPP; - count = pr->power.count - 1; - if (count <= 0) - return -ENODEV; - - for (i = 0; i < count; i++) { + for (i = 1; i < pr->power.count; i++) { u32 state; - lpi = &pr->power.lpi_states[i + 1]; + lpi = &pr->power.lpi_states[i]; /* * Only bits[31:0] represent a PSCI power_state while * bits[63:32] must be 0x0 as per ARM ACPI FFH Specification diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index b4c25474f42f..b82dd67d98c9 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -94,6 +94,7 @@ struct acpi_battery { struct power_supply *bat; struct power_supply_desc bat_desc; struct acpi_device *device; + struct device *phys_dev; struct notifier_block pm_nb; struct list_head list; unsigned long update_time; @@ -1033,7 +1034,7 @@ static int acpi_battery_update(struct acpi_battery *battery, bool resume) if ((battery->state & ACPI_BATTERY_STATE_CRITICAL) || (test_bit(ACPI_BATTERY_ALARM_PRESENT, &battery->flags) && (battery->capacity_now <= battery->alarm))) - acpi_pm_wakeup_event(&battery->device->dev); + acpi_pm_wakeup_event(battery->phys_dev); return result; } @@ -1214,10 +1215,14 @@ static void sysfs_battery_cleanup(struct acpi_battery *battery) static int acpi_battery_probe(struct platform_device *pdev) { - struct acpi_device *device = ACPI_COMPANION(&pdev->dev); struct acpi_battery *battery; + struct acpi_device *device; int result; + device = ACPI_COMPANION(&pdev->dev); + if (!device) + return -ENODEV; + if (device->dep_unmet) return -EPROBE_DEFER; @@ -1227,6 +1232,7 @@ static int acpi_battery_probe(struct platform_device *pdev) platform_set_drvdata(pdev, battery); + battery->phys_dev = &pdev->dev; battery->device = device; result = devm_mutex_init(&pdev->dev, &battery->update_lock); diff --git a/drivers/acpi/button.c b/drivers/acpi/button.c index dc064a388c23..b47301ee4c8a 100644 --- a/drivers/acpi/button.c +++ b/drivers/acpi/button.c @@ -531,15 +531,20 @@ static int acpi_lid_input_open(struct input_dev *input) static int acpi_button_probe(struct platform_device *pdev) { - struct acpi_device *device = ACPI_COMPANION(&pdev->dev); acpi_notify_handler handler; + struct acpi_device *device; struct acpi_button *button; struct input_dev *input; - const char *hid = acpi_device_hid(device); acpi_status status; char *name, *class; + const char *hid; int error = 0; + device = ACPI_COMPANION(&pdev->dev); + if (!device) + return -ENODEV; + + hid = acpi_device_hid(device); if (!strcmp(hid, ACPI_BUTTON_HID_LID) && lid_init_state == ACPI_BUTTON_LID_INIT_DISABLED) return -ENODEV; diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 2e91c5a97761..f370be8715ae 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -362,7 +362,7 @@ static int send_pcc_cmd(int pcc_ss_id, u16 cmd) end: if (cmd == CMD_WRITE) { if (unlikely(ret)) { - for_each_online_cpu(i) { + for_each_possible_cpu(i) { struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); if (!desc) @@ -524,13 +524,13 @@ int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data) else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY; - for_each_online_cpu(i) { + for_each_possible_cpu(i) { if (i == cpu) continue; match_cpc_ptr = per_cpu(cpc_desc_ptr, i); if (!match_cpc_ptr) - goto err_fault; + continue; match_pdomain = &(match_cpc_ptr->domain_info); if (match_pdomain->domain != pdomain->domain) diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 45204538ed87..64ad4cfa6208 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -1676,10 +1676,14 @@ static int acpi_ec_setup(struct acpi_ec *ec, struct acpi_device *device, bool ca static int acpi_ec_probe(struct platform_device *pdev) { - struct acpi_device *device = ACPI_COMPANION(&pdev->dev); + struct acpi_device *device; struct acpi_ec *ec; int ret; + device = ACPI_COMPANION(&pdev->dev); + if (!device) + return -ENODEV; + if (boot_ec && (boot_ec->handle == device->handle || !strcmp(acpi_device_hid(device), ACPI_ECDT_HID))) { /* Fast path: this device corresponds to the boot EC. */ diff --git a/drivers/acpi/hed.c b/drivers/acpi/hed.c index 4d5e12ed6f3c..060e8d670f5d 100644 --- a/drivers/acpi/hed.c +++ b/drivers/acpi/hed.c @@ -50,9 +50,13 @@ static void acpi_hed_notify(acpi_handle handle, u32 event, void *data) static int acpi_hed_probe(struct platform_device *pdev) { - struct acpi_device *device = ACPI_COMPANION(&pdev->dev); + struct acpi_device *device; int err; + device = ACPI_COMPANION(&pdev->dev); + if (!device) + return -ENODEV; + /* Only one hardware error device */ if (hed_handle) return -EINVAL; diff --git a/drivers/acpi/nfit/core.c b/drivers/acpi/nfit/core.c index d13264fb9e02..9304ac996d41 100644 --- a/drivers/acpi/nfit/core.c +++ b/drivers/acpi/nfit/core.c @@ -3341,12 +3341,16 @@ static int acpi_nfit_probe(struct platform_device *pdev) struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER, NULL }; struct acpi_nfit_desc *acpi_desc; struct device *dev = &pdev->dev; - struct acpi_device *adev = ACPI_COMPANION(dev); struct acpi_table_header *tbl; + struct acpi_device *adev; acpi_status status = AE_OK; acpi_size sz; int rc = 0; + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) + return -ENODEV; + rc = acpi_dev_install_notify_handler(adev, ACPI_DEVICE_NOTIFY, acpi_nfit_notify, dev); if (rc) diff --git a/drivers/acpi/pfr_telemetry.c b/drivers/acpi/pfr_telemetry.c index 32bdf8cbe8f2..2387376832a1 100644 --- a/drivers/acpi/pfr_telemetry.c +++ b/drivers/acpi/pfr_telemetry.c @@ -360,10 +360,14 @@ static void pfrt_log_put_idx(void *data) static int acpi_pfrt_log_probe(struct platform_device *pdev) { - acpi_handle handle = ACPI_HANDLE(&pdev->dev); struct pfrt_log_device *pfrt_log_dev; + acpi_handle handle; int ret; + handle = ACPI_HANDLE(&pdev->dev); + if (!handle) + return -ENODEV; + if (!acpi_has_method(handle, "_DSM")) { dev_dbg(&pdev->dev, "Missing _DSM\n"); return -ENODEV; diff --git a/drivers/acpi/pfr_update.c b/drivers/acpi/pfr_update.c index 11b1c2828005..6283105bb0e8 100644 --- a/drivers/acpi/pfr_update.c +++ b/drivers/acpi/pfr_update.c @@ -538,10 +538,14 @@ static void pfru_put_idx(void *data) static int acpi_pfru_probe(struct platform_device *pdev) { - acpi_handle handle = ACPI_HANDLE(&pdev->dev); struct pfru_device *pfru_dev; + acpi_handle handle; int ret; + handle = ACPI_HANDLE(&pdev->dev); + if (!handle) + return -ENODEV; + if (!acpi_has_method(handle, "_DSM")) { dev_dbg(&pdev->dev, "Missing _DSM\n"); return -ENODEV; diff --git a/drivers/acpi/sbs.c b/drivers/acpi/sbs.c index 440f1d69aca8..86b7c7975852 100644 --- a/drivers/acpi/sbs.c +++ b/drivers/acpi/sbs.c @@ -629,11 +629,15 @@ static void acpi_sbs_callback(void *context) static int acpi_sbs_probe(struct platform_device *pdev) { - struct acpi_device *device = ACPI_COMPANION(&pdev->dev); + struct acpi_device *device; struct acpi_sbs *sbs; int result = 0; int id; + device = ACPI_COMPANION(&pdev->dev); + if (!device) + return -ENODEV; + sbs = kzalloc_obj(struct acpi_sbs); if (!sbs) { result = -ENOMEM; diff --git a/drivers/acpi/sbshc.c b/drivers/acpi/sbshc.c index f413270415b6..c0ffa267f96c 100644 --- a/drivers/acpi/sbshc.c +++ b/drivers/acpi/sbshc.c @@ -237,11 +237,15 @@ static int smbus_alarm(void *context) static int acpi_smbus_hc_probe(struct platform_device *pdev) { - struct acpi_device *device = ACPI_COMPANION(&pdev->dev); + struct acpi_device *device; int status; unsigned long long val; struct acpi_smb_hc *hc; + device = ACPI_COMPANION(&pdev->dev); + if (!device) + return -ENODEV; + status = acpi_evaluate_integer(device->handle, "_EC", NULL, &val); if (ACPI_FAILURE(status)) { pr_err("error obtaining _EC.\n"); diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c index b8b487d89d25..dfc7daa809b5 100644 --- a/drivers/acpi/thermal.c +++ b/drivers/acpi/thermal.c @@ -789,7 +789,7 @@ static int acpi_thermal_probe(struct platform_device *pdev) int i; if (!device) - return -EINVAL; + return -ENODEV; tz = kzalloc_obj(struct acpi_thermal); if (!tz) diff --git a/drivers/acpi/tiny-power-button.c b/drivers/acpi/tiny-power-button.c index 531e65b01bcb..92516ef84b02 100644 --- a/drivers/acpi/tiny-power-button.c +++ b/drivers/acpi/tiny-power-button.c @@ -38,9 +38,13 @@ static u32 acpi_tiny_power_button_event(void *not_used) static int acpi_tiny_power_button_probe(struct platform_device *pdev) { - struct acpi_device *device = ACPI_COMPANION(&pdev->dev); + struct acpi_device *device; acpi_status status; + device = ACPI_COMPANION(&pdev->dev); + if (!device) + return -ENODEV; + if (device->device_type == ACPI_BUS_TYPE_POWER_BUTTON) { status = acpi_install_fixed_event_handler(ACPI_EVENT_POWER_BUTTON, acpi_tiny_power_button_event, diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c index 0a3c8232d15d..458efa4fe9d4 100644 --- a/drivers/acpi/video_detect.c +++ b/drivers/acpi/video_detect.c @@ -916,6 +916,14 @@ static const struct dmi_system_id video_detect_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "82K8"), }, }, + { + .callback = video_detect_force_native, + /* HP OMEN Gaming Laptop 16-n0xxx */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "HP"), + DMI_MATCH(DMI_PRODUCT_NAME, "OMEN by HP Gaming Laptop 16-n0xxx"), + }, + }, /* * x86 android tablets which directly control the backlight through diff --git a/drivers/android/binder/range_alloc/array.rs b/drivers/android/binder/range_alloc/array.rs index ada1d1b4302e..081d19b09d4b 100644 --- a/drivers/android/binder/range_alloc/array.rs +++ b/drivers/android/binder/range_alloc/array.rs @@ -204,7 +204,6 @@ pub(crate) fn reservation_abort(&mut self, offset: usize) -> Result // caller will mark them as unused, which means that they can be freed if the system comes // under memory pressure. let mut freed_range = FreedRange::interior_pages(offset, size); - #[expect(clippy::collapsible_if)] // reads better like this if offset % PAGE_SIZE != 0 { if i == 0 || self.ranges[i - 1].endpoint() <= (offset & PAGE_MASK) { freed_range.start_page_idx -= 1; diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index e76d15411e2a..3d0027ec33c2 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -5584,6 +5584,7 @@ void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp) link->pmp = pmp; link->active_tag = ATA_TAG_POISON; link->hw_sata_spd_limit = UINT_MAX; + INIT_WORK(&link->deferred_qc_work, ata_scsi_deferred_qc_work); /* can't use iterator, ap isn't initialized yet */ for (i = 0; i < ATA_MAX_DEVICES; i++) { @@ -5666,7 +5667,6 @@ struct ata_port *ata_port_alloc(struct ata_host *host) mutex_init(&ap->scsi_scan_mutex); INIT_DELAYED_WORK(&ap->hotplug_task, ata_scsi_hotplug); INIT_DELAYED_WORK(&ap->scsi_rescan_task, ata_scsi_dev_rescan); - INIT_WORK(&ap->deferred_qc_work, ata_scsi_deferred_qc_work); INIT_LIST_HEAD(&ap->eh_done_q); init_waitqueue_head(&ap->eh_wait_q); init_completion(&ap->park_req_pending); @@ -6291,12 +6291,15 @@ static void ata_port_detach(struct ata_port *ap) /* It better be dead now and not have any remaining deferred qc. */ WARN_ON(!(ap->pflags & ATA_PFLAG_UNLOADED)); - WARN_ON(ap->deferred_qc); - cancel_work_sync(&ap->deferred_qc_work); cancel_delayed_work_sync(&ap->hotplug_task); cancel_delayed_work_sync(&ap->scsi_rescan_task); + ata_for_each_link(link, ap, PMP_FIRST) { + WARN_ON(link->deferred_qc); + cancel_work_sync(&link->deferred_qc_work); + } + /* Delete port multiplier link transport devices */ if (ap->pmp_link) { int i; diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c index 9a4b67b90b17..d623eb32ed8b 100644 --- a/drivers/ata/libata-eh.c +++ b/drivers/ata/libata-eh.c @@ -651,11 +651,11 @@ int ata_scsi_cmd_error_handler(struct Scsi_Host *host, struct ata_port *ap, if (qc->scsicmd != scmd) continue; if ((qc->flags & ATA_QCFLAG_ACTIVE) || - qc == ap->deferred_qc) + qc == qc->dev->link->deferred_qc) break; } - if (i < ATA_MAX_QUEUE && qc == ap->deferred_qc) { + if (i < ATA_MAX_QUEUE && qc == qc->dev->link->deferred_qc) { /* * This is a deferred command that timed out while * waiting for the command queue to drain. Since the qc @@ -666,8 +666,8 @@ int ata_scsi_cmd_error_handler(struct Scsi_Host *host, struct ata_port *ap, * deferred qc work from issuing this qc. */ WARN_ON_ONCE(qc->flags & ATA_QCFLAG_ACTIVE); - ap->deferred_qc = NULL; - cancel_work(&ap->deferred_qc_work); + qc->dev->link->deferred_qc = NULL; + cancel_work(&qc->dev->link->deferred_qc_work); set_host_byte(scmd, DID_TIME_OUT); scsi_eh_finish_cmd(scmd, &ap->eh_done_q); } else if (i < ATA_MAX_QUEUE) { diff --git a/drivers/ata/libata-pmp.c b/drivers/ata/libata-pmp.c index e3adc008fed1..e8540931b4a1 100644 --- a/drivers/ata/libata-pmp.c +++ b/drivers/ata/libata-pmp.c @@ -110,13 +110,24 @@ int sata_pmp_qc_defer_cmd_switch(struct ata_queued_cmd *qc) { struct ata_link *link = qc->dev->link; struct ata_port *ap = link->ap; + int ret; if (ap->excl_link == NULL || ap->excl_link == link) { if (ap->nr_active_links == 0 || ata_link_active(link)) { qc->flags |= ATA_QCFLAG_CLEAR_EXCL; - return ata_std_qc_defer(qc); + ret = ata_std_qc_defer(qc); + if (ret == ATA_DEFER_LINK) + return ATA_DEFER_LINK_EXCL; + return ret; } + /* + * Note: ap->excl_link contains the link that is next in line, + * i.e. implicit round robin. If there is only one link + * dispatching, ap->excl_link will be left unclaimed, allowing + * other links to set ap->excl_link, ensuring that the currently + * active link cannot queue any more. + */ ap->excl_link = link; } @@ -571,8 +582,11 @@ static void sata_pmp_detach(struct ata_device *dev) if (ap->ops->pmp_detach) ap->ops->pmp_detach(ap); - ata_for_each_link(tlink, ap, EDGE) + ata_for_each_link(tlink, ap, EDGE) { + WARN_ON(tlink->deferred_qc); + cancel_work_sync(&tlink->deferred_qc_work); ata_eh_detach_dev(tlink->device); + } spin_lock_irqsave(ap->lock, flags); ap->nr_pmp_links = 0; diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index f44612e269a4..d43207c6e467 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -1664,8 +1664,9 @@ static void ata_scsi_qc_done(struct ata_queued_cmd *qc, bool set_result, void ata_scsi_deferred_qc_work(struct work_struct *work) { - struct ata_port *ap = - container_of(work, struct ata_port, deferred_qc_work); + struct ata_link *link = + container_of(work, struct ata_link, deferred_qc_work); + struct ata_port *ap = link->ap; struct ata_queued_cmd *qc; unsigned long flags; @@ -1676,10 +1677,10 @@ void ata_scsi_deferred_qc_work(struct work_struct *work) * such case, we should not need any more deferring the qc, so warn if * qc_defer() says otherwise. */ - qc = ap->deferred_qc; + qc = link->deferred_qc; if (qc && !ata_port_eh_scheduled(ap)) { WARN_ON_ONCE(ap->ops->qc_defer(qc)); - ap->deferred_qc = NULL; + link->deferred_qc = NULL; ata_qc_issue(qc); } @@ -1688,7 +1689,7 @@ void ata_scsi_deferred_qc_work(struct work_struct *work) void ata_scsi_requeue_deferred_qc(struct ata_port *ap) { - struct ata_queued_cmd *qc = ap->deferred_qc; + struct ata_link *link; lockdep_assert_held(ap->lock); @@ -1697,16 +1698,21 @@ void ata_scsi_requeue_deferred_qc(struct ata_port *ap) * do not try to be smart about what to do with this deferred command * and simply requeue it by completing it with DID_REQUEUE. */ - if (qc) { - ap->deferred_qc = NULL; - cancel_work(&ap->deferred_qc_work); - ata_scsi_qc_done(qc, true, DID_REQUEUE << 16); + ata_for_each_link(link, ap, PMP_FIRST) { + struct ata_queued_cmd *qc = link->deferred_qc; + + if (qc) { + link->deferred_qc = NULL; + cancel_work(&link->deferred_qc_work); + ata_scsi_qc_done(qc, true, DID_REQUEUE << 16); + } } } -static void ata_scsi_schedule_deferred_qc(struct ata_port *ap) +static void ata_scsi_schedule_deferred_qc(struct ata_link *link) { - struct ata_queued_cmd *qc = ap->deferred_qc; + struct ata_queued_cmd *qc = link->deferred_qc; + struct ata_port *ap = link->ap; lockdep_assert_held(ap->lock); @@ -1723,12 +1729,12 @@ static void ata_scsi_schedule_deferred_qc(struct ata_port *ap) return; } if (!ap->ops->qc_defer(qc)) - queue_work(system_highpri_wq, &ap->deferred_qc_work); + queue_work(system_highpri_wq, &link->deferred_qc_work); } static void ata_scsi_qc_complete(struct ata_queued_cmd *qc) { - struct ata_port *ap = qc->ap; + struct ata_link *link = qc->dev->link; struct scsi_cmnd *cmd = qc->scsicmd; u8 *cdb = cmd->cmnd; bool have_sense = qc->flags & ATA_QCFLAG_SENSE_VALID; @@ -1759,22 +1765,23 @@ static void ata_scsi_qc_complete(struct ata_queued_cmd *qc) ata_scsi_qc_done(qc, false, 0); - ata_scsi_schedule_deferred_qc(ap); + ata_scsi_schedule_deferred_qc(link); } static int ata_scsi_qc_issue(struct ata_port *ap, struct ata_queued_cmd *qc) { + struct ata_link *link = qc->dev->link; int ret; if (!ap->ops->qc_defer) - goto issue; + goto issue_qc; /* * If we already have a deferred qc, then rely on the SCSI layer to * requeue and defer all incoming commands until the deferred qc is * processed, once all on-going commands complete. */ - if (ap->deferred_qc) { + if (link->deferred_qc) { ata_qc_free(qc); return SCSI_MLQUEUE_DEVICE_BUSY; } @@ -1786,38 +1793,46 @@ static int ata_scsi_qc_issue(struct ata_port *ap, struct ata_queued_cmd *qc) break; case ATA_DEFER_LINK: ret = SCSI_MLQUEUE_DEVICE_BUSY; - break; + goto defer_qc; + case ATA_DEFER_LINK_EXCL: + /* + * Drivers making use of ap->excl_link cannot store the QC in + * link->deferred_qc, because the ap->excl_link handling is + * incompatible with the link->deferred_qc workqueue handling. + */ + ret = SCSI_MLQUEUE_DEVICE_BUSY; + goto free_qc; case ATA_DEFER_PORT: ret = SCSI_MLQUEUE_HOST_BUSY; - break; + goto free_qc; default: WARN_ON_ONCE(1); ret = SCSI_MLQUEUE_HOST_BUSY; - break; + goto free_qc; } - if (ret) { - /* - * We must defer this qc: if this is not an NCQ command, keep - * this qc as a deferred one and report to the SCSI layer that - * we issued it so that it is not requeued. The deferred qc will - * be issued with the port deferred_qc_work once all on-going - * commands complete. - */ - if (!ata_is_ncq(qc->tf.protocol)) { - ap->deferred_qc = qc; - return 0; - } - - /* Force a requeue of the command to defer its execution. */ - ata_qc_free(qc); - return ret; - } - -issue: +issue_qc: ata_qc_issue(qc); - return 0; + +defer_qc: + /* + * We must defer this qc: if this is not an NCQ command, keep + * this qc as a deferred one and report to the SCSI layer that + * we issued it so that it is not requeued. The deferred qc will + * be issued with the port deferred_qc_work once all on-going + * commands complete. + */ + if (!ata_is_ncq(qc->tf.protocol)) { + link->deferred_qc = qc; + return 0; + } + +free_qc: + /* Force a requeue of the command to defer its execution. */ + ata_qc_free(qc); + + return ret; } /** diff --git a/drivers/ata/pata_parport/pata_parport.c b/drivers/ata/pata_parport/pata_parport.c index a5b959891cb7..40baeac594a9 100644 --- a/drivers/ata/pata_parport/pata_parport.c +++ b/drivers/ata/pata_parport/pata_parport.c @@ -459,19 +459,11 @@ static void pata_parport_dev_release(struct device *dev) kfree(pi); } -static void pata_parport_bus_release(struct device *dev) -{ - /* nothing to do here but required to avoid warning on device removal */ -} - static const struct bus_type pata_parport_bus_type = { .name = DRV_NAME, }; -static struct device pata_parport_bus = { - .init_name = DRV_NAME, - .release = pata_parport_bus_release, -}; +static struct device *pata_parport_bus; static const struct scsi_host_template pata_parport_sht = { PATA_PARPORT_SHT("pata_parport") @@ -518,7 +510,7 @@ static struct pi_adapter *pi_init_one(struct parport *parport, } /* set up pi->dev before pi_probe_unit() so it can use dev_printk() */ - pi->dev.parent = &pata_parport_bus; + pi->dev.parent = pata_parport_bus; pi->dev.bus = &pata_parport_bus_type; pi->dev.driver = &pr->driver; pi->dev.release = pata_parport_dev_release; @@ -780,8 +772,9 @@ static __init int pata_parport_init(void) return error; } - error = device_register(&pata_parport_bus); - if (error) { + pata_parport_bus = root_device_register(DRV_NAME); + if (IS_ERR(pata_parport_bus)) { + error = PTR_ERR(pata_parport_bus); pr_err("failed to register pata_parport bus, error: %d\n", error); goto out_unregister_bus; } @@ -811,7 +804,7 @@ static __init int pata_parport_init(void) out_remove_new: bus_remove_file(&pata_parport_bus_type, &bus_attr_new_device); out_unregister_dev: - device_unregister(&pata_parport_bus); + root_device_unregister(pata_parport_bus); out_unregister_bus: bus_unregister(&pata_parport_bus_type); return error; @@ -822,7 +815,7 @@ static __exit void pata_parport_exit(void) parport_unregister_driver(&pata_parport_driver); bus_remove_file(&pata_parport_bus_type, &bus_attr_new_device); bus_remove_file(&pata_parport_bus_type, &bus_attr_delete_device); - device_unregister(&pata_parport_bus); + root_device_unregister(pata_parport_bus); bus_unregister(&pata_parport_bus_type); } diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c index d642ece9f07a..57f1081b86db 100644 --- a/drivers/ata/sata_sil24.c +++ b/drivers/ata/sata_sil24.c @@ -789,6 +789,7 @@ static int sil24_qc_defer(struct ata_queued_cmd *qc) struct ata_link *link = qc->dev->link; struct ata_port *ap = link->ap; u8 prot = qc->tf.protocol; + int ret; /* * There is a bug in the chip: @@ -826,7 +827,10 @@ static int sil24_qc_defer(struct ata_queued_cmd *qc) qc->flags |= ATA_QCFLAG_CLEAR_EXCL; } - return ata_std_qc_defer(qc); + ret = ata_std_qc_defer(qc); + if (ret == ATA_DEFER_LINK) + return ATA_DEFER_LINK_EXCL; + return ret; } static enum ata_completion_errors sil24_qc_prep(struct ata_queued_cmd *qc) diff --git a/drivers/base/memory.c b/drivers/base/memory.c index f806a683b767..6981b55d582a 100644 --- a/drivers/base/memory.c +++ b/drivers/base/memory.c @@ -1230,8 +1230,10 @@ void memblk_nr_poison_inc(unsigned long pfn) const unsigned long block_id = pfn_to_block_id(pfn); struct memory_block *mem = find_memory_block_by_id(block_id); - if (mem) + if (mem) { atomic_long_inc(&mem->nr_hwpoison); + put_device(&mem->dev); + } } void memblk_nr_poison_sub(unsigned long pfn, long i) @@ -1239,8 +1241,10 @@ void memblk_nr_poison_sub(unsigned long pfn, long i) const unsigned long block_id = pfn_to_block_id(pfn); struct memory_block *mem = find_memory_block_by_id(block_id); - if (mem) + if (mem) { atomic_long_sub(i, &mem->nr_hwpoison); + put_device(&mem->dev); + } } static unsigned long memblk_nr_poison(struct memory_block *mem) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 75b4698d0e58..a19dd22deef2 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -606,6 +606,12 @@ static void platform_device_release(struct device *dev) kfree(pa); } +static void platform_device_release_full(struct device *dev) +{ + device_remove_software_node(dev); + platform_device_release(dev); +} + /** * platform_device_alloc - create a platform device * @name: base name of the device we're adding @@ -848,7 +854,13 @@ struct platform_device *platform_device_register_full(const struct platform_devi int ret; struct platform_device *pdev; - if (pdevinfo->swnode && pdevinfo->properties) + /* + * Only one software node per device is allowed. Make sure we don't + * accept or create two. + */ + if ((pdevinfo->swnode && pdevinfo->properties) || + (pdevinfo->swnode && is_software_node(pdevinfo->fwnode)) || + (pdevinfo->properties && is_software_node(pdevinfo->fwnode))) return ERR_PTR(-EINVAL); pdev = platform_device_alloc(pdevinfo->name, pdevinfo->id); @@ -878,6 +890,8 @@ struct platform_device *platform_device_register_full(const struct platform_devi ret = device_add_software_node(&pdev->dev, pdevinfo->swnode); if (ret) goto err; + + pdev->dev.release = platform_device_release_full; } else if (pdevinfo->properties) { ret = device_create_managed_software_node(&pdev->dev, pdevinfo->properties, NULL); diff --git a/drivers/base/regmap/regmap-sdw-mbq.c b/drivers/base/regmap/regmap-sdw-mbq.c index 4533fe793c5f..2585933d4946 100644 --- a/drivers/base/regmap/regmap-sdw-mbq.c +++ b/drivers/base/regmap/regmap-sdw-mbq.c @@ -172,7 +172,7 @@ static int regmap_sdw_mbq_read(void *context, unsigned int reg, unsigned int *va ret = regmap_sdw_mbq_read_impl(slave, reg, val, mbq_size); if (ret == -ENODATA) { if (!deferrable) - dev_warn(dev, "Defer on undeferable control: %x\n", reg); + dev_warn(dev, "Defer on undeferrable control: %x\n", reg); ret = regmap_sdw_mbq_poll_busy(slave, reg, ctx); if (ret) diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c index 4065336ebd1f..6c1e7347e6a7 100644 --- a/drivers/block/rbd.c +++ b/drivers/block/rbd.c @@ -4565,24 +4565,12 @@ static int rbd_register_watch(struct rbd_device *rbd_dev) return ret; } -static void cancel_tasks_sync(struct rbd_device *rbd_dev) -{ - dout("%s rbd_dev %p\n", __func__, rbd_dev); - - cancel_work_sync(&rbd_dev->acquired_lock_work); - cancel_work_sync(&rbd_dev->released_lock_work); - cancel_delayed_work_sync(&rbd_dev->lock_dwork); - cancel_work_sync(&rbd_dev->unlock_work); -} - /* * header_rwsem must not be held to avoid a deadlock with * rbd_dev_refresh() when flushing notifies. */ static void rbd_unregister_watch(struct rbd_device *rbd_dev) { - cancel_tasks_sync(rbd_dev); - mutex_lock(&rbd_dev->watch_mutex); if (rbd_dev->watch_state == RBD_WATCH_STATE_REGISTERED) __rbd_unregister_watch(rbd_dev); @@ -6548,10 +6536,18 @@ static int rbd_add_parse_args(const char *buf, static void rbd_dev_image_unlock(struct rbd_device *rbd_dev) { + dout("%s rbd_dev %p\n", __func__, rbd_dev); + + disable_delayed_work_sync(&rbd_dev->lock_dwork); + disable_work_sync(&rbd_dev->unlock_work); + down_write(&rbd_dev->lock_rwsem); if (__rbd_is_lock_owner(rbd_dev)) __rbd_release_lock(rbd_dev); up_write(&rbd_dev->lock_rwsem); + + flush_work(&rbd_dev->acquired_lock_work); + flush_work(&rbd_dev->released_lock_work); } /* diff --git a/drivers/block/ublk_drv.c b/drivers/block/ublk_drv.c index 8e5f3738c203..6c041eaebdb9 100644 --- a/drivers/block/ublk_drv.c +++ b/drivers/block/ublk_drv.c @@ -900,12 +900,29 @@ static int ublk_validate_params(const struct ublk_device *ub) if (p->logical_bs_shift > PAGE_SHIFT || p->logical_bs_shift < 9) return -EINVAL; + /* + * 256M is a reasonable upper bound for physical block size, + * io_min and io_opt; it aligns with the maximum physical + * block size possible in NVMe. + */ + if (p->physical_bs_shift > ilog2(SZ_256M)) + return -EINVAL; + + if (p->io_min_shift > ilog2(SZ_256M)) + return -EINVAL; + + if (p->io_opt_shift > ilog2(SZ_256M)) + return -EINVAL; + if (p->logical_bs_shift > p->physical_bs_shift) return -EINVAL; if (p->max_sectors > (ub->dev_info.max_io_buf_bytes >> 9)) return -EINVAL; + if (p->max_sectors < PAGE_SECTORS) + return -EINVAL; + if (ublk_dev_is_zoned(ub) && !p->chunk_sectors) return -EINVAL; } else @@ -2397,8 +2414,14 @@ static void ublk_reset_ch_dev(struct ublk_device *ub) { int i; - for (i = 0; i < ub->dev_info.nr_hw_queues; i++) - ublk_queue_reinit(ub, ublk_get_queue(ub, i)); + for (i = 0; i < ub->dev_info.nr_hw_queues; i++) { + struct ublk_queue *ubq = ublk_get_queue(ub, i); + + /* Sync with ublk_cancel_cmd() */ + spin_lock(&ubq->cancel_lock); + ublk_queue_reinit(ub, ubq); + spin_unlock(&ubq->cancel_lock); + } /* set to NULL, otherwise new tasks cannot mmap io_cmd_buf */ ub->mm = NULL; @@ -2739,6 +2762,7 @@ static void ublk_cancel_cmd(struct ublk_queue *ubq, unsigned tag, { struct ublk_io *io = &ubq->ios[tag]; struct ublk_device *ub = ubq->dev; + struct io_uring_cmd *cmd = NULL; struct request *req; bool done; @@ -2761,12 +2785,15 @@ static void ublk_cancel_cmd(struct ublk_queue *ubq, unsigned tag, spin_lock(&ubq->cancel_lock); done = !!(io->flags & UBLK_IO_FLAG_CANCELED); - if (!done) + if (!done) { io->flags |= UBLK_IO_FLAG_CANCELED; + cmd = io->cmd; + io->cmd = NULL; + } spin_unlock(&ubq->cancel_lock); - if (!done) - io_uring_cmd_done(io->cmd, UBLK_IO_RES_ABORT, issue_flags); + if (!done && cmd) + io_uring_cmd_done(cmd, UBLK_IO_RES_ABORT, issue_flags); } /* @@ -3496,8 +3523,10 @@ static void ublk_ch_uring_cmd_cb(struct io_tw_req tw_req, io_tw_token_t tw) { unsigned int issue_flags = IO_URING_CMD_TASK_WORK_ISSUE_FLAGS; struct io_uring_cmd *cmd = io_uring_cmd_from_tw(tw_req); - int ret = ublk_ch_uring_cmd_local(cmd, issue_flags); + int ret = -ECANCELED; + if (!tw.cancel) + ret = ublk_ch_uring_cmd_local(cmd, issue_flags); if (ret != -EIOCBQUEUED) io_uring_cmd_done(cmd, ret, issue_flags); } @@ -4990,13 +5019,15 @@ static int ublk_ctrl_set_params(struct ublk_device *ub, */ ret = -EACCES; } else if (copy_from_user(&ub->params, argp, ph.len)) { + /* zero out partial copy so no stale params survive */ + memset(&ub->params, 0, sizeof(ub->params)); ret = -EFAULT; } else { /* clear all we don't support yet */ ub->params.types &= UBLK_PARAM_TYPE_ALL; ret = ublk_validate_params(ub); if (ret) - ub->params.types = 0; + memset(&ub->params, 0, sizeof(ub->params)); } mutex_unlock(&ub->mutex); diff --git a/drivers/bluetooth/btintel_pcie.c b/drivers/bluetooth/btintel_pcie.c index 2f59c0d6f9ec..37e050763633 100644 --- a/drivers/bluetooth/btintel_pcie.c +++ b/drivers/bluetooth/btintel_pcie.c @@ -289,6 +289,9 @@ static inline void btintel_pcie_dump_debug_registers(struct hci_dev *hdev) skb_put_data(skb, buf, strlen(buf)); data->boot_stage_cache = reg; + if (reg & BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING) + bt_dev_warn(hdev, "Controller device warning (boot_stage: 0x%8.8x)", reg); + reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_IPC_STATUS_REG); snprintf(buf, sizeof(buf), "ipc status: 0x%8.8x", reg); skb_put_data(skb, buf, strlen(buf)); @@ -579,12 +582,10 @@ static int btintel_pcie_get_mac_access(struct btintel_pcie_data *data) reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); - reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS; - reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ; - if ((reg & BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS) == 0) + if (!(reg & BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ)) { reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ; - - btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg); + btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg); + } do { reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); @@ -604,16 +605,10 @@ static void btintel_pcie_release_mac_access(struct btintel_pcie_data *data) reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); - if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ) + if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ) { reg &= ~BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ; - - if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS) - reg &= ~BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS; - - if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ) - reg &= ~BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ; - - btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg); + btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg); + } } static void *btintel_pcie_copy_tlv(void *dest, enum btintel_pcie_tlv_type type, @@ -880,8 +875,11 @@ static inline bool btintel_pcie_in_lockdown(struct btintel_pcie_data *data) static inline bool btintel_pcie_in_error(struct btintel_pcie_data *data) { - return (data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_ERR) || - (data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER); + if (data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING) + bt_dev_warn(data->hdev, "Controller device warning (boot_stage: 0x%8.8x)", + data->boot_stage_cache); + + return data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER; } static void btintel_pcie_msix_gp1_handler(struct btintel_pcie_data *data) @@ -914,7 +912,8 @@ static void btintel_pcie_msix_gp0_handler(struct btintel_pcie_data *data) data->img_resp_cache = reg; if (btintel_pcie_in_error(data)) { - bt_dev_err(data->hdev, "Controller in error state"); + bt_dev_err(data->hdev, "Controller in error state (boot_stage: 0x%8.8x)", + data->boot_stage_cache); btintel_pcie_dump_debug_registers(data->hdev); return; } diff --git a/drivers/bluetooth/btintel_pcie.h b/drivers/bluetooth/btintel_pcie.h index 3c7bb708362d..13efef499e4e 100644 --- a/drivers/bluetooth/btintel_pcie.h +++ b/drivers/bluetooth/btintel_pcie.h @@ -34,9 +34,6 @@ #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS (BIT(20)) #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ (BIT(21)) -/* Stop MAC Access disconnection request */ -#define BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS (BIT(22)) -#define BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ (BIT(23)) #define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_STS (BIT(28)) #define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON (BIT(29)) @@ -48,7 +45,7 @@ #define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW (BIT(2)) #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN (BIT(10)) #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN (BIT(11)) -#define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_ERR (BIT(12)) +#define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING (BIT(12)) #define BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER (BIT(13)) #define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_HALTED (BIT(14)) #define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON (BIT(16)) diff --git a/drivers/bluetooth/btmtk.c b/drivers/bluetooth/btmtk.c index 6fb6ca274808..8ff66b276af0 100644 --- a/drivers/bluetooth/btmtk.c +++ b/drivers/bluetooth/btmtk.c @@ -537,6 +537,7 @@ static void btmtk_usb_wmt_recv(struct urb *urb) return; } else if (urb->status == -ENOENT) { /* Avoid suspend failed when usb_kill_urb */ + kfree(urb->setup_packet); return; } @@ -610,6 +611,7 @@ static int btmtk_usb_submit_wmt_recv_urb(struct hci_dev *hdev) if (err != -EPERM && err != -ENODEV) bt_dev_err(hdev, "urb %p submission failed (%d)", urb, -err); + kfree(dr); usb_unanchor_urb(urb); } @@ -695,8 +697,13 @@ static int btmtk_usb_hci_wmt_sync(struct hci_dev *hdev, if (data->evt_skb == NULL) goto err_free_wc; - /* Parse and handle the return WMT event */ - wmt_evt = (struct btmtk_hci_wmt_evt *)data->evt_skb->data; + wmt_evt = skb_pull_data(data->evt_skb, sizeof(*wmt_evt)); + if (!wmt_evt) { + bt_dev_err(hdev, "WMT event too short (%u bytes)", + data->evt_skb->len); + err = -EINVAL; + goto err_free_skb; + } if (wmt_evt->whdr.op != hdr->op) { bt_dev_err(hdev, "Wrong op received %d expected %d", wmt_evt->whdr.op, hdr->op); @@ -712,6 +719,12 @@ static int btmtk_usb_hci_wmt_sync(struct hci_dev *hdev, status = BTMTK_WMT_PATCH_DONE; break; case BTMTK_WMT_FUNC_CTRL: + if (!skb_pull_data(data->evt_skb, + sizeof(wmt_evt_funcc->status))) { + status = BTMTK_WMT_ON_UNDONE; + break; + } + wmt_evt_funcc = (struct btmtk_hci_wmt_evt_funcc *)wmt_evt; if (be16_to_cpu(wmt_evt_funcc->status) == 0x404) status = BTMTK_WMT_ON_DONE; diff --git a/drivers/bluetooth/hci_ath.c b/drivers/bluetooth/hci_ath.c index fa679ad0acdf..8201fa7f61e8 100644 --- a/drivers/bluetooth/hci_ath.c +++ b/drivers/bluetooth/hci_ath.c @@ -191,6 +191,9 @@ static int ath_recv(struct hci_uart *hu, const void *data, int count) { struct ath_struct *ath = hu->priv; + if (!ath) + return -ENODEV; + ath->rx_skb = h4_recv_buf(hu, ath->rx_skb, data, count, ath_recv_pkts, ARRAY_SIZE(ath_recv_pkts)); if (IS_ERR(ath->rx_skb)) { diff --git a/drivers/bluetooth/hci_bcsp.c b/drivers/bluetooth/hci_bcsp.c index b386f91d8b46..db56eead27ce 100644 --- a/drivers/bluetooth/hci_bcsp.c +++ b/drivers/bluetooth/hci_bcsp.c @@ -585,6 +585,9 @@ static int bcsp_recv(struct hci_uart *hu, const void *data, int count) if (!test_bit(HCI_UART_REGISTERED, &hu->flags)) return -EUNATCH; + if (!bcsp) + return -ENODEV; + BT_DBG("hu %p count %d rx_state %d rx_count %ld", hu, count, bcsp->rx_state, bcsp->rx_count); diff --git a/drivers/bluetooth/hci_h4.c b/drivers/bluetooth/hci_h4.c index a889a66a326f..767372707498 100644 --- a/drivers/bluetooth/hci_h4.c +++ b/drivers/bluetooth/hci_h4.c @@ -109,6 +109,9 @@ static int h4_recv(struct hci_uart *hu, const void *data, int count) { struct h4_struct *h4 = hu->priv; + if (!h4) + return -ENODEV; + h4->rx_skb = h4_recv_buf(hu, h4->rx_skb, data, count, h4_recv_pkts, ARRAY_SIZE(h4_recv_pkts)); if (IS_ERR(h4->rx_skb)) { diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c index cfdf75dc2847..d35383718212 100644 --- a/drivers/bluetooth/hci_h5.c +++ b/drivers/bluetooth/hci_h5.c @@ -587,6 +587,9 @@ static int h5_recv(struct hci_uart *hu, const void *data, int count) struct h5 *h5 = hu->priv; const unsigned char *ptr = data; + if (!h5) + return -ENODEV; + BT_DBG("%s pending %zu count %d", hu->hdev->name, h5->rx_pending, count); diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c index 275ea865bc29..47f4902b40b4 100644 --- a/drivers/bluetooth/hci_ldisc.c +++ b/drivers/bluetooth/hci_ldisc.c @@ -194,7 +194,15 @@ void hci_uart_init_work(struct work_struct *work) err = hci_register_dev(hu->hdev); if (err < 0) { BT_ERR("Can't register HCI device"); + + percpu_down_write(&hu->proto_lock); clear_bit(HCI_UART_PROTO_READY, &hu->flags); + percpu_up_write(&hu->proto_lock); + + /* Safely cancel work after clearing flags */ + cancel_work_sync(&hu->write_work); + + /* Close protocol before freeing hdev */ hu->proto->close(hu); hdev = hu->hdev; hu->hdev = NULL; @@ -263,8 +271,12 @@ static int hci_uart_open(struct hci_dev *hdev) /* Close device */ static int hci_uart_close(struct hci_dev *hdev) { + struct hci_uart *hu = hci_get_drvdata(hdev); + BT_DBG("hdev %p", hdev); + cancel_work_sync(&hu->write_work); + hci_uart_flush(hdev); hdev->flush = NULL; return 0; @@ -531,6 +543,7 @@ static void hci_uart_tty_close(struct tty_struct *tty) { struct hci_uart *hu = tty->disc_data; struct hci_dev *hdev; + bool proto_ready; BT_DBG("tty %p", tty); @@ -540,24 +553,38 @@ static void hci_uart_tty_close(struct tty_struct *tty) if (!hu) return; - hdev = hu->hdev; - if (hdev) - hci_uart_close(hdev); + /* Wait for init_ready to finish to prevent registration races */ + cancel_work_sync(&hu->init_ready); - if (test_bit(HCI_UART_PROTO_READY, &hu->flags)) { + proto_ready = test_bit(HCI_UART_PROTO_READY, &hu->flags); + if (proto_ready) { percpu_down_write(&hu->proto_lock); clear_bit(HCI_UART_PROTO_READY, &hu->flags); percpu_up_write(&hu->proto_lock); + } - cancel_work_sync(&hu->init_ready); - cancel_work_sync(&hu->write_work); + /* + * Unconditionally cancel write_work AFTER clearing PROTO_READY. + * This ensures that concurrent protocol timers cannot requeue + * write_work via hci_uart_tx_wakeup(), permanently preventing + * double-free races and UAFs. + */ + cancel_work_sync(&hu->write_work); + hdev = hu->hdev; + if (hdev) + hci_uart_close(hdev); /* proto->flush is safely skipped */ + + if (proto_ready) { if (hdev) { if (test_bit(HCI_UART_REGISTERED, &hu->flags)) hci_unregister_dev(hdev); - hci_free_dev(hdev); } + /* Close protocol before freeing hdev (intrinsically purges queues) */ hu->proto->close(hu); + + if (hdev) + hci_free_dev(hdev); } clear_bit(HCI_UART_PROTO_SET, &hu->flags); @@ -625,11 +652,12 @@ static void hci_uart_tty_receive(struct tty_struct *tty, const u8 *data, * tty caller */ hu->proto->recv(hu, data, count); - percpu_up_read(&hu->proto_lock); if (hu->hdev) hu->hdev->stat.byte_rx += count; + percpu_up_read(&hu->proto_lock); + tty_unthrottle(tty); } @@ -695,6 +723,10 @@ static int hci_uart_register_dev(struct hci_uart *hu) percpu_down_write(&hu->proto_lock); clear_bit(HCI_UART_PROTO_INIT, &hu->flags); percpu_up_write(&hu->proto_lock); + /* Cancel work after clearing flags */ + cancel_work_sync(&hu->write_work); + + /* Close protocol before freeing hdev */ hu->proto->close(hu); hu->hdev = NULL; hci_free_dev(hdev); diff --git a/drivers/bluetooth/hci_qca.c b/drivers/bluetooth/hci_qca.c index cd1834246b47..ed280399bf47 100644 --- a/drivers/bluetooth/hci_qca.c +++ b/drivers/bluetooth/hci_qca.c @@ -48,13 +48,12 @@ #define HCI_MAX_IBS_SIZE 10 #define IBS_WAKE_RETRANS_TIMEOUT_MS 100 -#define IBS_BTSOC_TX_IDLE_TIMEOUT_MS 200 +#define IBS_BTSOC_TX_IDLE_TIMEOUT msecs_to_jiffies(200) #define IBS_HOST_TX_IDLE_TIMEOUT_MS 2000 -#define CMD_TRANS_TIMEOUT_MS 100 -#define MEMDUMP_TIMEOUT_MS 8000 -#define IBS_DISABLE_SSR_TIMEOUT_MS \ - (MEMDUMP_TIMEOUT_MS + FW_DOWNLOAD_TIMEOUT_MS) -#define FW_DOWNLOAD_TIMEOUT_MS 3000 +#define CMD_TRANS_TIMEOUT msecs_to_jiffies(100) +#define MEMDUMP_TIMEOUT msecs_to_jiffies(8000) +#define FW_DOWNLOAD_TIMEOUT msecs_to_jiffies(3000) +#define IBS_DISABLE_SSR_TIMEOUT (MEMDUMP_TIMEOUT + FW_DOWNLOAD_TIMEOUT) /* susclk rate */ #define SUSCLK_RATE_32KHZ 32768 @@ -1096,7 +1095,7 @@ static void qca_controller_memdump(struct work_struct *work) queue_delayed_work(qca->workqueue, &qca->ctrl_memdump_timeout, - msecs_to_jiffies(MEMDUMP_TIMEOUT_MS)); + MEMDUMP_TIMEOUT); skb_pull(skb, sizeof(qca_memdump->ram_dump_size)); qca_memdump->current_seq_no = 0; qca_memdump->received_dump = 0; @@ -1369,7 +1368,7 @@ static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate) if (hu->serdev) serdev_device_wait_until_sent(hu->serdev, - msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS)); + CMD_TRANS_TIMEOUT); /* Give the controller time to process the request */ switch (qca_soc_type(hu)) { @@ -1401,8 +1400,8 @@ static inline void host_set_baudrate(struct hci_uart *hu, unsigned int speed) static int qca_send_power_pulse(struct hci_uart *hu, bool on) { + int timeout = CMD_TRANS_TIMEOUT; int ret; - int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS); u8 cmd = on ? QCA_WCN3990_POWERON_PULSE : QCA_WCN3990_POWEROFF_PULSE; /* These power pulses are single byte command which are sent @@ -1607,7 +1606,7 @@ static void qca_wait_for_dump_collection(struct hci_dev *hdev) struct qca_data *qca = hu->priv; wait_on_bit_timeout(&qca->flags, QCA_MEMDUMP_COLLECTION, - TASK_UNINTERRUPTIBLE, MEMDUMP_TIMEOUT_MS); + TASK_UNINTERRUPTIBLE, MEMDUMP_TIMEOUT); clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags); } @@ -2591,7 +2590,7 @@ static void qca_serdev_remove(struct serdev_device *serdev) static void qca_serdev_shutdown(struct serdev_device *serdev) { int ret; - int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS); + int timeout = CMD_TRANS_TIMEOUT; struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev); struct hci_uart *hu = &qcadev->serdev_hu; struct hci_dev *hdev = hu->hdev; @@ -2648,7 +2647,7 @@ static int __maybe_unused qca_suspend(struct device *dev) bool tx_pending = false; int ret = 0; u8 cmd; - u32 wait_timeout = 0; + unsigned long wait_timeout = 0; set_bit(QCA_SUSPENDING, &qca->flags); @@ -2669,15 +2668,15 @@ static int __maybe_unused qca_suspend(struct device *dev) if (test_bit(QCA_IBS_DISABLED, &qca->flags) || test_bit(QCA_SSR_TRIGGERED, &qca->flags)) { wait_timeout = test_bit(QCA_SSR_TRIGGERED, &qca->flags) ? - IBS_DISABLE_SSR_TIMEOUT_MS : - FW_DOWNLOAD_TIMEOUT_MS; + IBS_DISABLE_SSR_TIMEOUT : + FW_DOWNLOAD_TIMEOUT; /* QCA_IBS_DISABLED flag is set to true, During FW download * and during memory dump collection. It is reset to false, * After FW download complete. */ wait_on_bit_timeout(&qca->flags, QCA_IBS_DISABLED, - TASK_UNINTERRUPTIBLE, msecs_to_jiffies(wait_timeout)); + TASK_UNINTERRUPTIBLE, wait_timeout); if (test_bit(QCA_IBS_DISABLED, &qca->flags)) { bt_dev_err(hu->hdev, "SSR or FW download time out"); @@ -2729,7 +2728,7 @@ static int __maybe_unused qca_suspend(struct device *dev) if (tx_pending) { serdev_device_wait_until_sent(hu->serdev, - msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS)); + CMD_TRANS_TIMEOUT); serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu); } @@ -2738,7 +2737,7 @@ static int __maybe_unused qca_suspend(struct device *dev) */ ret = wait_event_interruptible_timeout(qca->suspend_wait_q, qca->rx_ibs_state == HCI_IBS_RX_ASLEEP, - msecs_to_jiffies(IBS_BTSOC_TX_IDLE_TIMEOUT_MS)); + IBS_BTSOC_TX_IDLE_TIMEOUT); if (ret == 0) { ret = -ETIMEDOUT; goto error; diff --git a/drivers/bluetooth/virtio_bt.c b/drivers/bluetooth/virtio_bt.c index 76d61af8a275..140ab55c9fc5 100644 --- a/drivers/bluetooth/virtio_bt.c +++ b/drivers/bluetooth/virtio_bt.c @@ -12,6 +12,7 @@ #include #define VERSION "0.1" +#define VIRTBT_RX_BUF_SIZE 1000 enum { VIRTBT_VQ_TX, @@ -33,11 +34,11 @@ static int virtbt_add_inbuf(struct virtio_bluetooth *vbt) struct sk_buff *skb; int err; - skb = alloc_skb(1000, GFP_KERNEL); + skb = alloc_skb(VIRTBT_RX_BUF_SIZE, GFP_KERNEL); if (!skb) return -ENOMEM; - sg_init_one(sg, skb->data, 1000); + sg_init_one(sg, skb->data, VIRTBT_RX_BUF_SIZE); err = virtqueue_add_inbuf(vq, sg, 1, skb, GFP_KERNEL); if (err < 0) { @@ -197,6 +198,7 @@ static int virtbt_shutdown_generic(struct hci_dev *hdev) static void virtbt_rx_handle(struct virtio_bluetooth *vbt, struct sk_buff *skb) { + size_t min_hdr; __u8 pkt_type; pkt_type = *((__u8 *) skb->data); @@ -204,16 +206,32 @@ static void virtbt_rx_handle(struct virtio_bluetooth *vbt, struct sk_buff *skb) switch (pkt_type) { case HCI_EVENT_PKT: + min_hdr = sizeof(struct hci_event_hdr); + break; case HCI_ACLDATA_PKT: + min_hdr = sizeof(struct hci_acl_hdr); + break; case HCI_SCODATA_PKT: + min_hdr = sizeof(struct hci_sco_hdr); + break; case HCI_ISODATA_PKT: - hci_skb_pkt_type(skb) = pkt_type; - hci_recv_frame(vbt->hdev, skb); + min_hdr = sizeof(struct hci_iso_hdr); break; default: kfree_skb(skb); - break; + return; } + + if (skb->len < min_hdr) { + bt_dev_err_ratelimited(vbt->hdev, + "rx pkt_type 0x%02x payload %u < hdr %zu\n", + pkt_type, skb->len, min_hdr); + kfree_skb(skb); + return; + } + + hci_skb_pkt_type(skb) = pkt_type; + hci_recv_frame(vbt->hdev, skb); } static void virtbt_rx_work(struct work_struct *work) @@ -227,8 +245,15 @@ static void virtbt_rx_work(struct work_struct *work) if (!skb) return; - skb_put(skb, len); - virtbt_rx_handle(vbt, skb); + if (!len || len > VIRTBT_RX_BUF_SIZE) { + bt_dev_err_ratelimited(vbt->hdev, + "rx reply len %u outside [1, %u]\n", + len, VIRTBT_RX_BUF_SIZE); + kfree_skb(skb); + } else { + skb_put(skb, len); + virtbt_rx_handle(vbt, skb); + } if (virtbt_add_inbuf(vbt) < 0) return; diff --git a/drivers/cdrom/cdrom.c b/drivers/cdrom/cdrom.c index fc049612d6dc..62934cf4b10d 100644 --- a/drivers/cdrom/cdrom.c +++ b/drivers/cdrom/cdrom.c @@ -631,6 +631,16 @@ int register_cdrom(struct gendisk *disk, struct cdrom_device_info *cdi) WARN_ON(!cdo->generic_packet); + /* + * Propagate the drive's write support to the block layer so BLKROGET + * reflects actual write capability. Drivers that use GET CONFIGURATION + * features (CDC_MRW_W, CDC_RAM) must have called + * cdrom_probe_write_features() before register_cdrom() so the mask is + * complete here. + */ + set_disk_ro(disk, !CDROM_CAN(CDC_DVD_RAM | CDC_MRW_W | CDC_RAM | + CDC_CD_RW)); + cd_dbg(CD_REG_UNREG, "drive \"/dev/%s\" registered\n", cdi->name); mutex_lock(&cdrom_mutex); list_add(&cdi->list, &cdrom_list); @@ -742,6 +752,44 @@ static int cdrom_is_random_writable(struct cdrom_device_info *cdi, int *write) return 0; } +/* + * Probe write-related MMC features via GET CONFIGURATION and update + * cdi->mask accordingly. Drivers that populate cdi->mask from the MODE SENSE + * capabilities page (e.g. sr) should call this after those MODE SENSE bits + * have been set but before register_cdrom(), so that the full set of + * write-capability bits is known by the time register_cdrom() decides on the + * initial read-only state of the disk. + */ +void cdrom_probe_write_features(struct cdrom_device_info *cdi) +{ + int mrw, mrw_write, ram_write; + + mrw = 0; + if (!cdrom_is_mrw(cdi, &mrw_write)) + mrw = 1; + + if (CDROM_CAN(CDC_MO_DRIVE)) + ram_write = 1; + else + (void) cdrom_is_random_writable(cdi, &ram_write); + + if (mrw) + cdi->mask &= ~CDC_MRW; + else + cdi->mask |= CDC_MRW; + + if (mrw_write) + cdi->mask &= ~CDC_MRW_W; + else + cdi->mask |= CDC_MRW_W; + + if (ram_write) + cdi->mask &= ~CDC_RAM; + else + cdi->mask |= CDC_RAM; +} +EXPORT_SYMBOL(cdrom_probe_write_features); + static int cdrom_media_erasable(struct cdrom_device_info *cdi) { disc_information di; @@ -894,33 +942,8 @@ static int cdrom_is_dvd_rw(struct cdrom_device_info *cdi) */ static int cdrom_open_write(struct cdrom_device_info *cdi) { - int mrw, mrw_write, ram_write; int ret = 1; - mrw = 0; - if (!cdrom_is_mrw(cdi, &mrw_write)) - mrw = 1; - - if (CDROM_CAN(CDC_MO_DRIVE)) - ram_write = 1; - else - (void) cdrom_is_random_writable(cdi, &ram_write); - - if (mrw) - cdi->mask &= ~CDC_MRW; - else - cdi->mask |= CDC_MRW; - - if (mrw_write) - cdi->mask &= ~CDC_MRW_W; - else - cdi->mask |= CDC_MRW_W; - - if (ram_write) - cdi->mask &= ~CDC_RAM; - else - cdi->mask |= CDC_RAM; - if (CDROM_CAN(CDC_MRW_W)) ret = cdrom_mrw_open_write(cdi); else if (CDROM_CAN(CDC_DVD_RAM)) diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c index 4a9e9de4d684..9a9d12be9bf7 100644 --- a/drivers/char/ipmi/ipmi_si_intf.c +++ b/drivers/char/ipmi/ipmi_si_intf.c @@ -168,6 +168,10 @@ struct smi_info { OEM2_DATA_AVAIL) unsigned char msg_flags; + /* When requesting events and messages, don't do it forever. */ + unsigned int num_requests_in_a_row; + bool last_was_flag_fetch; + /* Does the BMC have an event buffer? */ bool has_event_buffer; @@ -410,7 +414,10 @@ static void start_getting_msg_queue(struct smi_info *smi_info) start_new_msg(smi_info, smi_info->curr_msg->data, smi_info->curr_msg->data_size); - smi_info->si_state = SI_GETTING_MESSAGES; + if (smi_info->si_state != SI_GETTING_MESSAGES) { + smi_info->num_requests_in_a_row = 0; + smi_info->si_state = SI_GETTING_MESSAGES; + } } static void start_getting_events(struct smi_info *smi_info) @@ -421,7 +428,10 @@ static void start_getting_events(struct smi_info *smi_info) start_new_msg(smi_info, smi_info->curr_msg->data, smi_info->curr_msg->data_size); - smi_info->si_state = SI_GETTING_EVENTS; + if (smi_info->si_state != SI_GETTING_EVENTS) { + smi_info->num_requests_in_a_row = 0; + smi_info->si_state = SI_GETTING_EVENTS; + } } /* @@ -487,15 +497,19 @@ static void handle_flags(struct smi_info *smi_info) } else if (smi_info->msg_flags & RECEIVE_MSG_AVAIL) { /* Messages available. */ smi_info->curr_msg = alloc_msg_handle_irq(smi_info); - if (!smi_info->curr_msg) + if (!smi_info->curr_msg) { + smi_info->si_state = SI_NORMAL; return; + } start_getting_msg_queue(smi_info); } else if (smi_info->msg_flags & EVENT_MSG_BUFFER_FULL) { /* Events available. */ smi_info->curr_msg = alloc_msg_handle_irq(smi_info); - if (!smi_info->curr_msg) + if (!smi_info->curr_msg) { + smi_info->si_state = SI_NORMAL; return; + } start_getting_events(smi_info); } else if (smi_info->msg_flags & OEM_DATA_AVAIL && @@ -595,6 +609,7 @@ static void handle_transaction_done(struct smi_info *smi_info) smi_info->si_state = SI_NORMAL; } else { smi_info->msg_flags = msg[3]; + smi_info->last_was_flag_fetch = true; handle_flags(smi_info); } break; @@ -630,7 +645,13 @@ static void handle_transaction_done(struct smi_info *smi_info) */ msg = smi_info->curr_msg; smi_info->curr_msg = NULL; - if (msg->rsp[2] != 0) { + /* + * It appears some BMCs, with no event data, return no + * data in the message and not a 0x80 error as the + * spec says they should. Shut down processing if + * the data is not the right length. + */ + if (msg->rsp[2] != 0 || msg->rsp_size != 19) { /* Error getting event, probably done. */ msg->done(msg); @@ -640,6 +661,11 @@ static void handle_transaction_done(struct smi_info *smi_info) } else { smi_inc_stat(smi_info, events); + smi_info->num_requests_in_a_row++; + if (smi_info->num_requests_in_a_row > 10) + /* Stop if we do this too many times. */ + smi_info->msg_flags &= ~EVENT_MSG_BUFFER_FULL; + /* * Do this before we deliver the message * because delivering the message releases the @@ -678,6 +704,11 @@ static void handle_transaction_done(struct smi_info *smi_info) } else { smi_inc_stat(smi_info, incoming_messages); + smi_info->num_requests_in_a_row++; + if (smi_info->num_requests_in_a_row > 10) + /* Stop if we do this too many times. */ + smi_info->msg_flags &= ~RECEIVE_MSG_AVAIL; + /* * Do this before we deliver the message * because delivering the message releases the @@ -819,6 +850,26 @@ static enum si_sm_result smi_event_handler(struct smi_info *smi_info, goto out; } + /* + * If we are currently idle, or if the last thing that was + * done was a flag fetch and there is a message pending, try + * to start the next message. + * + * We do the waiting message check to avoid a stuck flag + * completely wedging the driver. Let a message through + * in between flag operations if that happens. + */ + if (si_sm_result == SI_SM_IDLE || + (si_sm_result == SI_SM_ATTN && smi_info->waiting_msg && + smi_info->last_was_flag_fetch)) { + smi_info->last_was_flag_fetch = false; + smi_inc_stat(smi_info, idles); + + si_sm_result = start_next_msg(smi_info); + if (si_sm_result != SI_SM_IDLE) + goto restart; + } + /* * We prefer handling attn over new messages. But don't do * this if there is not yet an upper layer to handle anything. @@ -846,15 +897,6 @@ static enum si_sm_result smi_event_handler(struct smi_info *smi_info, } } - /* If we are currently idle, try to start the next message. */ - if (si_sm_result == SI_SM_IDLE) { - smi_inc_stat(smi_info, idles); - - si_sm_result = start_next_msg(smi_info); - if (si_sm_result != SI_SM_IDLE) - goto restart; - } - if ((si_sm_result == SI_SM_IDLE) && (atomic_read(&smi_info->req_events))) { /* diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c index b49500a1bd36..f419b46bf002 100644 --- a/drivers/char/ipmi/ipmi_ssif.c +++ b/drivers/char/ipmi/ipmi_ssif.c @@ -225,6 +225,9 @@ struct ssif_info { bool has_event_buffer; bool supports_alert; + /* When requesting events and messages, don't do it forever. */ + unsigned int num_requests_in_a_row; + /* * Used to tell what we should do with alerts. If we are * waiting on a response, read the data immediately. @@ -413,7 +416,10 @@ static void start_event_fetch(struct ssif_info *ssif_info, unsigned long *flags) } ssif_info->curr_msg = msg; - ssif_info->ssif_state = SSIF_GETTING_EVENTS; + if (ssif_info->ssif_state != SSIF_GETTING_EVENTS) { + ssif_info->num_requests_in_a_row = 0; + ssif_info->ssif_state = SSIF_GETTING_EVENTS; + } ipmi_ssif_unlock_cond(ssif_info, flags); msg->data[0] = (IPMI_NETFN_APP_REQUEST << 2); @@ -436,7 +442,10 @@ static void start_recv_msg_fetch(struct ssif_info *ssif_info, } ssif_info->curr_msg = msg; - ssif_info->ssif_state = SSIF_GETTING_MESSAGES; + if (ssif_info->ssif_state != SSIF_GETTING_MESSAGES) { + ssif_info->num_requests_in_a_row = 0; + ssif_info->ssif_state = SSIF_GETTING_MESSAGES; + } ipmi_ssif_unlock_cond(ssif_info, flags); msg->data[0] = (IPMI_NETFN_APP_REQUEST << 2); @@ -843,6 +852,11 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, ssif_info->msg_flags &= ~EVENT_MSG_BUFFER_FULL; handle_flags(ssif_info, flags); } else { + ssif_info->num_requests_in_a_row++; + if (ssif_info->num_requests_in_a_row > 10) + /* Stop if we do this too many times. */ + ssif_info->msg_flags &= ~EVENT_MSG_BUFFER_FULL; + handle_flags(ssif_info, flags); ssif_inc_stat(ssif_info, events); deliver_recv_msg(ssif_info, msg); @@ -876,6 +890,11 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, ssif_info->msg_flags &= ~RECEIVE_MSG_AVAIL; handle_flags(ssif_info, flags); } else { + ssif_info->num_requests_in_a_row++; + if (ssif_info->num_requests_in_a_row > 10) + /* Stop if we do this too many times. */ + ssif_info->msg_flags &= ~RECEIVE_MSG_AVAIL; + ssif_inc_stat(ssif_info, incoming_messages); handle_flags(ssif_info, flags); deliver_recv_msg(ssif_info, msg); @@ -1886,6 +1905,7 @@ static int ssif_probe(struct i2c_client *client) "kssif%4.4x", thread_num); if (IS_ERR(ssif_info->thread)) { rv = PTR_ERR(ssif_info->thread); + ssif_info->thread = NULL; dev_notice(&ssif_info->client->dev, "Could not start kernel thread: error %d\n", rv); diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index c1dccedf8d5b..d9303c2c7aa5 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -110,6 +110,7 @@ struct eqc_match_data { const char *reset_auxdev_name; const char *pinctrl_auxdev_name; + const char *eth_phy_auxdev_name; unsigned int early_clk_count; }; @@ -321,38 +322,18 @@ static void eqc_probe_init_fixed_factors(struct device *dev, } } -static void eqc_auxdev_release(struct device *dev) -{ - struct auxiliary_device *adev = to_auxiliary_dev(dev); - - kfree(adev); -} - -static int eqc_auxdev_create(struct device *dev, void __iomem *base, - const char *name, u32 id) +static void eqc_auxdev_create_optional(struct device *dev, void __iomem *base, + const char *name) { struct auxiliary_device *adev; - int ret; - adev = kzalloc_obj(*adev); - if (!adev) - return -ENOMEM; - - adev->name = name; - adev->dev.parent = dev; - adev->dev.platform_data = (void __force *)base; - adev->dev.release = eqc_auxdev_release; - adev->id = id; - - ret = auxiliary_device_init(adev); - if (ret) - return ret; - - ret = auxiliary_device_add(adev); - if (ret) - auxiliary_device_uninit(adev); - - return ret; + if (name) { + adev = devm_auxiliary_device_create(dev, name, + (void __force *)base); + if (!adev) + dev_warn(dev, "failed creating auxiliary device %s.%s\n", + KBUILD_MODNAME, name); + } } static int eqc_probe(struct platform_device *pdev) @@ -364,7 +345,6 @@ static int eqc_probe(struct platform_device *pdev) unsigned int i, clk_count; struct resource *res; void __iomem *base; - int ret; data = device_get_match_data(dev); if (!data) @@ -378,21 +358,10 @@ static int eqc_probe(struct platform_device *pdev) if (!base) return -ENOMEM; - /* Init optional reset auxiliary device. */ - if (data->reset_auxdev_name) { - ret = eqc_auxdev_create(dev, base, data->reset_auxdev_name, 0); - if (ret) - dev_warn(dev, "failed creating auxiliary device %s.%s: %d\n", - KBUILD_MODNAME, data->reset_auxdev_name, ret); - } - - /* Init optional pinctrl auxiliary device. */ - if (data->pinctrl_auxdev_name) { - ret = eqc_auxdev_create(dev, base, data->pinctrl_auxdev_name, 0); - if (ret) - dev_warn(dev, "failed creating auxiliary device %s.%s: %d\n", - KBUILD_MODNAME, data->pinctrl_auxdev_name, ret); - } + /* Init optional auxiliary devices. */ + eqc_auxdev_create_optional(dev, base, data->reset_auxdev_name); + eqc_auxdev_create_optional(dev, base, data->pinctrl_auxdev_name); + eqc_auxdev_create_optional(dev, base, data->eth_phy_auxdev_name); if (data->pll_count + data->div_count + data->fixed_factor_count == 0) return 0; /* Zero clocks, we are done. */ @@ -553,6 +522,7 @@ static const struct eqc_match_data eqc_eyeq5_match_data = { .reset_auxdev_name = "reset", .pinctrl_auxdev_name = "pinctrl", + .eth_phy_auxdev_name = "phy", .early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_plls) + ARRAY_SIZE(eqc_eyeq5_early_fixed_factors), diff --git a/drivers/clk/clk-rk808.c b/drivers/clk/clk-rk808.c index f7412b137e5e..5a75b5c91555 100644 --- a/drivers/clk/clk-rk808.c +++ b/drivers/clk/clk-rk808.c @@ -153,7 +153,7 @@ static int rk808_clkout_probe(struct platform_device *pdev) struct rk808_clkout *rk808_clkout; int ret; - dev->of_node = pdev->dev.parent->of_node; + device_set_of_node_from_dev(dev, dev->parent); rk808_clkout = devm_kzalloc(dev, sizeof(*rk808_clkout), GFP_KERNEL); diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c index e98afd59f05c..bb8b75bdbdb3 100644 --- a/drivers/clk/spacemit/ccu-k3.c +++ b/drivers/clk/spacemit/ccu-k3.c @@ -846,7 +846,7 @@ static const struct clk_parent_data top_parents[] = { CCU_PARENT_HW(pll6_d3), }; CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, - BIT(8), 2, 3, BIT(1), 0); + BIT(8), 2, 3, BIT(1), CLK_IS_CRITICAL); static const struct clk_parent_data ucie_parents[] = { CCU_PARENT_HW(pll1_d8_307p2), diff --git a/drivers/cpufreq/Kconfig.x86 b/drivers/cpufreq/Kconfig.x86 index 027e6ea2e038..a9093cd5e5d1 100644 --- a/drivers/cpufreq/Kconfig.x86 +++ b/drivers/cpufreq/Kconfig.x86 @@ -70,18 +70,6 @@ config X86_AMD_PSTATE_DEFAULT_MODE For details, take a look at: . -config X86_AMD_PSTATE_DYNAMIC_EPP - bool "AMD Processor P-State dynamic EPP support" - depends on X86_AMD_PSTATE - default n - help - Allow the kernel to dynamically change the energy performance - value from events like ACPI platform profile and AC adapter plug - events. - - This feature can also be changed at runtime, this configuration - option only sets the kernel default value behavior. - config X86_AMD_PSTATE_UT tristate "selftest for AMD Processor P-State driver" depends on X86 && ACPI_PROCESSOR diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c index aa8a464fab47..13a23dac477d 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -274,20 +274,21 @@ static int amd_pstate_set_mode(enum amd_pstate_mode mode) static int amd_pstate_ut_epp(u32 index) { - struct cpufreq_policy *policy __free(put_cpufreq_policy) = NULL; - char *buf __free(cleanup_page) = NULL; static const char * const epp_strings[] = { - "performance", - "balance_performance", - "balance_power", "power", + "balance_power", + "balance_performance", + "performance", }; - struct amd_cpudata *cpudata; + char *buf __free(cleanup_page) = NULL; + struct cpufreq_policy *policy = NULL; enum amd_pstate_mode orig_mode; + struct amd_cpudata *cpudata; + unsigned long orig_policy; bool orig_dynamic_epp; int ret, cpu = 0; - int i; u16 epp; + int i; policy = cpufreq_cpu_get(cpu); if (!policy) @@ -297,6 +298,10 @@ static int amd_pstate_ut_epp(u32 index) orig_mode = amd_pstate_get_status(); orig_dynamic_epp = cpudata->dynamic_epp; + /* Drop reference before potential driver change. */ + cpufreq_cpu_put(policy); + policy = NULL; + /* disable dynamic EPP before running test */ if (cpudata->dynamic_epp) { pr_debug("Dynamic EPP is enabled, disabling it\n"); @@ -311,6 +316,17 @@ static int amd_pstate_ut_epp(u32 index) if (ret) goto out; + policy = cpufreq_cpu_get(cpu); + if (!policy) { + ret = -ENODEV; + goto out; + } + + down_write(&policy->rwsem); + cpudata = policy->driver_data; + orig_policy = cpudata->policy; + cpudata->policy = CPUFREQ_POLICY_POWERSAVE; + for (epp = 0; epp <= U8_MAX; epp++) { u8 val; @@ -358,6 +374,12 @@ static int amd_pstate_ut_epp(u32 index) ret = 0; out: + if (policy) { + cpudata->policy = orig_policy; + up_write(&policy->rwsem); + cpufreq_cpu_put(policy); + } + if (orig_dynamic_epp) { int ret2; diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 453084c67327..62b5d995281d 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -87,11 +87,7 @@ static struct cpufreq_driver amd_pstate_driver; static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool amd_pstate_prefcore = true; -#ifdef CONFIG_X86_AMD_PSTATE_DYNAMIC_EPP -static bool dynamic_epp = CONFIG_X86_AMD_PSTATE_DYNAMIC_EPP; -#else static bool dynamic_epp; -#endif static struct quirk_entry *quirks; /* @@ -1291,6 +1287,8 @@ static int amd_pstate_set_dynamic_epp(struct cpufreq_policy *policy) return ret; cpudata->profile_name = kasprintf(GFP_KERNEL, "amd-pstate-epp-cpu%d", cpudata->cpu); + if (!cpudata->profile_name) + return -ENOMEM; cpudata->ppdev = platform_profile_register(get_cpu_device(policy->cpu), cpudata->profile_name, @@ -1427,7 +1425,7 @@ ssize_t store_energy_performance_preference(struct cpufreq_policy *policy, if (ret) epp = epp_values[ret]; else - epp = amd_pstate_get_balanced_epp(policy); + epp = cpudata->epp_default_dc; } if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { @@ -1707,6 +1705,8 @@ static int amd_pstate_change_driver_mode(int mode) { int ret; + lockdep_assert_held(&amd_pstate_driver_lock); + ret = amd_pstate_unregister_driver(0); if (ret) return ret; @@ -1821,8 +1821,16 @@ static ssize_t dynamic_epp_store(struct device *a, struct device_attribute *b, if (ret) return ret; - if (dynamic_epp == enabled) + guard(mutex)(&amd_pstate_driver_lock); + + if (cppc_state != AMD_PSTATE_ACTIVE) { + pr_debug("dynamic_epp can only be toggled in active mode\n"); return -EINVAL; + } + + /* Nothing to do */ + if (dynamic_epp == enabled) + return count; /* reinitialize with desired dynamic EPP value */ dynamic_epp = enabled; @@ -1942,7 +1950,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) if (dynamic_epp) ret = amd_pstate_set_dynamic_epp(policy); else - ret = amd_pstate_set_epp(policy, amd_pstate_get_balanced_epp(policy)); + ret = amd_pstate_set_epp(policy, cpudata->epp_default_dc); if (ret) goto free_cpudata1; @@ -1970,12 +1978,13 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) if (cpudata) { union perf_cached perf = READ_ONCE(cpudata->perf); + if (cpudata->dynamic_epp) + amd_pstate_clear_dynamic_epp(policy); + /* Reset CPPC_REQ MSR to the BIOS value */ amd_pstate_update_perf(policy, perf.bios_min_perf, 0U, 0U, 0U, false); amd_pstate_set_floor_perf(policy, cpudata->bios_floor_perf); - if (cpudata->dynamic_epp) - amd_pstate_clear_dynamic_epp(policy); kfree(cpudata); policy->driver_data = NULL; } diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 1292da53e5fc..1f093e346430 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -2279,7 +2279,7 @@ static int hwp_get_cpu_scaling(int cpu) * Return the hybrid scaling factor for P-cores and use the * default core scaling for E-cores. */ - if (hybrid_get_cpu_type(cpu) == INTEL_CPU_TYPE_CORE) + if (hybrid_get_cpu_type(cpu) != INTEL_CPU_TYPE_ATOM) return hybrid_scaling_factor; return core_get_scaling(); @@ -3734,6 +3734,7 @@ static const struct x86_cpu_id intel_hybrid_scaling_factor[] = { X86_MATCH_VFM(INTEL_RAPTORLAKE, HYBRID_SCALING_FACTOR_ADL), X86_MATCH_VFM(INTEL_RAPTORLAKE_P, HYBRID_SCALING_FACTOR_ADL), X86_MATCH_VFM(INTEL_RAPTORLAKE_S, HYBRID_SCALING_FACTOR_ADL), + X86_MATCH_VFM(INTEL_BARTLETTLAKE, HYBRID_SCALING_FACTOR_ADL), X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL), X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL), {} diff --git a/drivers/dma-buf/.kunitconfig b/drivers/dma-buf/.kunitconfig new file mode 100644 index 000000000000..1ce5fb7e6cf9 --- /dev/null +++ b/drivers/dma-buf/.kunitconfig @@ -0,0 +1,2 @@ +CONFIG_KUNIT=y +CONFIG_DMABUF_KUNIT_TEST=y diff --git a/drivers/dma-buf/Kconfig b/drivers/dma-buf/Kconfig index 8d4f2f89f24e..7efc0f0d0712 100644 --- a/drivers/dma-buf/Kconfig +++ b/drivers/dma-buf/Kconfig @@ -49,10 +49,13 @@ config DMABUF_DEBUG exporters. Specifically it validates that importers do not peek at the underlying struct page when they import a buffer. -config DMABUF_SELFTESTS - tristate "Selftests for the dma-buf interfaces" - default n - depends on DMA_SHARED_BUFFER +config DMABUF_KUNIT_TEST + tristate "KUnit tests for DMA-BUF" if !KUNIT_ALL_TESTS + depends on KUNIT + select DMA_SHARED_BUFFER + default KUNIT_ALL_TESTS + help + Enable kunit tests for DMA-BUF menuconfig DMABUF_HEAPS bool "DMA-BUF Userland Memory Heaps" diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile index 7a85565d906b..b25d7550bacf 100644 --- a/drivers/dma-buf/Makefile +++ b/drivers/dma-buf/Makefile @@ -7,11 +7,10 @@ obj-$(CONFIG_SYNC_FILE) += sync_file.o obj-$(CONFIG_SW_SYNC) += sw_sync.o sync_debug.o obj-$(CONFIG_UDMABUF) += udmabuf.o -dmabuf_selftests-y := \ - selftest.o \ +dmabuf_kunit-y := \ st-dma-fence.o \ st-dma-fence-chain.o \ st-dma-fence-unwrap.o \ st-dma-resv.o -obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o +obj-$(CONFIG_DMABUF_KUNIT_TEST) += dmabuf_kunit.o diff --git a/drivers/dma-buf/dma-fence-array.c b/drivers/dma-buf/dma-fence-array.c index 089f69469524..5e10e8df372f 100644 --- a/drivers/dma-buf/dma-fence-array.c +++ b/drivers/dma-buf/dma-fence-array.c @@ -190,15 +190,13 @@ EXPORT_SYMBOL(dma_fence_array_alloc); * @fences: [in] array containing the fences * @context: [in] fence context to use * @seqno: [in] sequence number to use - * @signal_on_any: [in] signal on any fence in the array * * Implementation of @dma_fence_array_create without allocation. Useful to init * a preallocated dma fence array in the path of reclaim or dma fence signaling. */ void dma_fence_array_init(struct dma_fence_array *array, int num_fences, struct dma_fence **fences, - u64 context, unsigned seqno, - bool signal_on_any) + u64 context, unsigned seqno) { static struct lock_class_key dma_fence_array_lock_key; @@ -222,7 +220,7 @@ void dma_fence_array_init(struct dma_fence_array *array, */ lockdep_set_class(&array->base.inline_lock, &dma_fence_array_lock_key); - atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences); + atomic_set(&array->num_pending, num_fences); array->fences = fences; array->base.error = PENDING_ERROR; @@ -249,7 +247,6 @@ EXPORT_SYMBOL(dma_fence_array_init); * @fences: [in] array containing the fences * @context: [in] fence context to use * @seqno: [in] sequence number to use - * @signal_on_any: [in] signal on any fence in the array * * Allocate a dma_fence_array object and initialize the base fence with * dma_fence_init(). @@ -264,8 +261,7 @@ EXPORT_SYMBOL(dma_fence_array_init); */ struct dma_fence_array *dma_fence_array_create(int num_fences, struct dma_fence **fences, - u64 context, unsigned seqno, - bool signal_on_any) + u64 context, unsigned seqno) { struct dma_fence_array *array; @@ -273,8 +269,7 @@ struct dma_fence_array *dma_fence_array_create(int num_fences, if (!array) return NULL; - dma_fence_array_init(array, num_fences, fences, - context, seqno, signal_on_any); + dma_fence_array_init(array, num_fences, fences, context, seqno); return array; } diff --git a/drivers/dma-buf/dma-fence-unwrap.c b/drivers/dma-buf/dma-fence-unwrap.c index 07fe9bf45aea..53bb40e70b27 100644 --- a/drivers/dma-buf/dma-fence-unwrap.c +++ b/drivers/dma-buf/dma-fence-unwrap.c @@ -180,8 +180,7 @@ struct dma_fence *__dma_fence_unwrap_merge(unsigned int num_fences, if (count > 1) { result = dma_fence_array_create(count, array, - dma_fence_context_alloc(1), - 1, false); + dma_fence_context_alloc(1), 1); if (!result) { for (i = 0; i < count; i++) dma_fence_put(array[i]); diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index a2aa82f4eedd..b3bfa6943a8e 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -363,6 +363,8 @@ void dma_fence_signal_timestamp_locked(struct dma_fence *fence, &fence->flags))) return; + trace_dma_fence_signaled(fence); + /* * When neither a release nor a wait operation is specified set the ops * pointer to NULL to allow the fence structure to become independent @@ -377,7 +379,6 @@ void dma_fence_signal_timestamp_locked(struct dma_fence *fence, fence->timestamp = timestamp; set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags); - trace_dma_fence_signaled(fence); list_for_each_entry_safe(cur, tmp, &cb_list, node) { INIT_LIST_HEAD(&cur->node); diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index ce9e6c04897f..39a92d9f2413 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -648,8 +648,7 @@ int dma_resv_get_singleton(struct dma_resv *obj, enum dma_resv_usage usage, } array = dma_fence_array_create(count, fences, - dma_fence_context_alloc(1), - 1, false); + dma_fence_context_alloc(1), 1); if (!array) { while (count--) dma_fence_put(fences[count]); diff --git a/drivers/dma-buf/selftest.c b/drivers/dma-buf/selftest.c deleted file mode 100644 index c60b6944b4bd..000000000000 --- a/drivers/dma-buf/selftest.c +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: MIT */ - -/* - * Copyright © 2019 Intel Corporation - */ - -#include -#include -#include -#include -#include - -#include "selftest.h" - -enum { -#define selftest(n, func) __idx_##n, -#include "selftests.h" -#undef selftest -}; - -#define selftest(n, f) [__idx_##n] = { .name = #n, .func = f }, -static struct selftest { - bool enabled; - const char *name; - int (*func)(void); -} selftests[] = { -#include "selftests.h" -}; -#undef selftest - -/* Embed the line number into the parameter name so that we can order tests */ -#define param(n) __PASTE(igt__, __PASTE(__PASTE(__LINE__, __), n)) -#define selftest_0(n, func, id) \ -module_param_named(id, selftests[__idx_##n].enabled, bool, 0400); -#define selftest(n, func) selftest_0(n, func, param(n)) -#include "selftests.h" -#undef selftest - -int __sanitycheck__(void) -{ - pr_debug("Hello World!\n"); - return 0; -} - -static char *__st_filter; - -static bool apply_subtest_filter(const char *caller, const char *name) -{ - char *filter, *sep, *tok; - bool result = true; - - filter = kstrdup(__st_filter, GFP_KERNEL); - for (sep = filter; (tok = strsep(&sep, ","));) { - bool allow = true; - char *sl; - - if (*tok == '!') { - allow = false; - tok++; - } - - if (*tok == '\0') - continue; - - sl = strchr(tok, '/'); - if (sl) { - *sl++ = '\0'; - if (strcmp(tok, caller)) { - if (allow) - result = false; - continue; - } - tok = sl; - } - - if (strcmp(tok, name)) { - if (allow) - result = false; - continue; - } - - result = allow; - break; - } - kfree(filter); - - return result; -} - -int -__subtests(const char *caller, const struct subtest *st, int count, void *data) -{ - int err; - - for (; count--; st++) { - cond_resched(); - if (signal_pending(current)) - return -EINTR; - - if (!apply_subtest_filter(caller, st->name)) - continue; - - pr_info("dma-buf: Running %s/%s\n", caller, st->name); - - err = st->func(data); - if (err && err != -EINTR) { - pr_err("dma-buf/%s: %s failed with error %d\n", - caller, st->name, err); - return err; - } - } - - return 0; -} - -static void set_default_test_all(struct selftest *st, unsigned long count) -{ - unsigned long i; - - for (i = 0; i < count; i++) - if (st[i].enabled) - return; - - for (i = 0; i < count; i++) - st[i].enabled = true; -} - -static int run_selftests(struct selftest *st, unsigned long count) -{ - int err = 0; - - set_default_test_all(st, count); - - /* Tests are listed in natural order in selftests.h */ - for (; count--; st++) { - if (!st->enabled) - continue; - - pr_info("dma-buf: Running %s\n", st->name); - err = st->func(); - if (err) - break; - } - - if (WARN(err > 0 || err == -ENOTTY, - "%s returned %d, conflicting with selftest's magic values!\n", - st->name, err)) - err = -1; - - return err; -} - -static int __init st_init(void) -{ - return run_selftests(selftests, ARRAY_SIZE(selftests)); -} - -static void __exit st_exit(void) -{ -} - -module_param_named(st_filter, __st_filter, charp, 0400); -module_init(st_init); -module_exit(st_exit); - -MODULE_DESCRIPTION("Self-test harness for dma-buf"); -MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/dma-buf/selftest.h b/drivers/dma-buf/selftest.h deleted file mode 100644 index 45793aff6142..000000000000 --- a/drivers/dma-buf/selftest.h +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: MIT - -/* - * Copyright © 2019 Intel Corporation - */ - -#ifndef __SELFTEST_H__ -#define __SELFTEST_H__ - -#include - -#define selftest(name, func) int func(void); -#include "selftests.h" -#undef selftest - -struct subtest { - int (*func)(void *data); - const char *name; -}; - -int __subtests(const char *caller, - const struct subtest *st, - int count, - void *data); -#define subtests(T, data) \ - __subtests(__func__, T, ARRAY_SIZE(T), data) - -#define SUBTEST(x) { x, #x } - -#endif /* __SELFTEST_H__ */ diff --git a/drivers/dma-buf/selftests.h b/drivers/dma-buf/selftests.h deleted file mode 100644 index 851965867d9c..000000000000 --- a/drivers/dma-buf/selftests.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* List each unit test as selftest(name, function) - * - * The name is used as both an enum and expanded as subtest__name to create - * a module parameter. It must be unique and legal for a C identifier. - * - * The function should be of type int function(void). It may be conditionally - * compiled using #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST). - * - * Tests are executed in order by igt/dmabuf_selftest - */ -selftest(sanitycheck, __sanitycheck__) /* keep first (igt selfcheck) */ -selftest(dma_fence, dma_fence) -selftest(dma_fence_chain, dma_fence_chain) -selftest(dma_fence_unwrap, dma_fence_unwrap) -selftest(dma_resv, dma_resv) diff --git a/drivers/dma-buf/st-dma-fence-chain.c b/drivers/dma-buf/st-dma-fence-chain.c index 821023dd34df..a3023d3fedc9 100644 --- a/drivers/dma-buf/st-dma-fence-chain.c +++ b/drivers/dma-buf/st-dma-fence-chain.c @@ -4,6 +4,7 @@ * Copyright © 2019 Intel Corporation */ +#include #include #include #include @@ -15,8 +16,6 @@ #include #include -#include "selftest.h" - #define CHAIN_SZ (4 << 10) static struct kmem_cache *slab_fences; @@ -74,27 +73,23 @@ static struct dma_fence *mock_chain(struct dma_fence *prev, return &f->base; } -static int sanitycheck(void *arg) +static void test_sanitycheck(struct kunit *test) { struct dma_fence *f, *chain; - int err = 0; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); chain = mock_chain(NULL, f, 1); if (chain) dma_fence_enable_sw_signaling(chain); else - err = -ENOMEM; + KUNIT_FAIL(test, "Failed to create chain"); dma_fence_signal(f); dma_fence_put(f); dma_fence_put(chain); - - return err; } struct fence_chains { @@ -176,7 +171,7 @@ static void fence_chains_fini(struct fence_chains *fc) kvfree(fc->chains); } -static int find_seqno(void *arg) +static void test_find_seqno(struct kunit *test) { struct fence_chains fc; struct dma_fence *fence; @@ -184,14 +179,13 @@ static int find_seqno(void *arg) int i; err = fence_chains_init(&fc, 64, seqno_inc); - if (err) - return err; + KUNIT_ASSERT_EQ_MSG(test, err, 0, "Failed to init fence chains"); fence = dma_fence_get(fc.tail); err = dma_fence_chain_find_seqno(&fence, 0); dma_fence_put(fence); if (err) { - pr_err("Reported %d for find_seqno(0)!\n", err); + KUNIT_FAIL(test, "Reported %d for find_seqno(0)!", err); goto err; } @@ -200,14 +194,13 @@ static int find_seqno(void *arg) err = dma_fence_chain_find_seqno(&fence, i + 1); dma_fence_put(fence); if (err) { - pr_err("Reported %d for find_seqno(%d:%d)!\n", - err, fc.chain_length + 1, i + 1); + KUNIT_FAIL(test, "Reported %d for find_seqno(%d:%d)!", + err, fc.chain_length + 1, i + 1); goto err; } if (fence != fc.chains[i]) { - pr_err("Incorrect fence reported by find_seqno(%d:%d)\n", - fc.chain_length + 1, i + 1); - err = -EINVAL; + KUNIT_FAIL(test, "Incorrect fence reported by find_seqno(%d:%d)", + fc.chain_length + 1, i + 1); goto err; } @@ -215,12 +208,11 @@ static int find_seqno(void *arg) err = dma_fence_chain_find_seqno(&fence, i + 1); dma_fence_put(fence); if (err) { - pr_err("Error reported for finding self\n"); + KUNIT_FAIL(test, "Error reported for finding self"); goto err; } if (fence != fc.chains[i]) { - pr_err("Incorrect fence reported by find self\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Incorrect fence reported by find self"); goto err; } @@ -228,9 +220,8 @@ static int find_seqno(void *arg) err = dma_fence_chain_find_seqno(&fence, i + 2); dma_fence_put(fence); if (!err) { - pr_err("Error not reported for future fence: find_seqno(%d:%d)!\n", - i + 1, i + 2); - err = -EINVAL; + KUNIT_FAIL(test, "Error not reported for future fence: find_seqno(%d:%d)!", + i + 1, i + 2); goto err; } @@ -238,31 +229,28 @@ static int find_seqno(void *arg) err = dma_fence_chain_find_seqno(&fence, i); dma_fence_put(fence); if (err) { - pr_err("Error reported for previous fence!\n"); + KUNIT_FAIL(test, "Error reported for previous fence!"); goto err; } if (i > 0 && fence != fc.chains[i - 1]) { - pr_err("Incorrect fence reported by find_seqno(%d:%d)\n", - i + 1, i); - err = -EINVAL; + KUNIT_FAIL(test, "Incorrect fence reported by find_seqno(%d:%d)", + i + 1, i); goto err; } } err: fence_chains_fini(&fc); - return err; } -static int find_signaled(void *arg) +static void test_find_signaled(struct kunit *test) { struct fence_chains fc; struct dma_fence *fence; int err; err = fence_chains_init(&fc, 2, seqno_inc); - if (err) - return err; + KUNIT_ASSERT_EQ_MSG(test, err, 0, "Failed to init fence chains"); dma_fence_signal(fc.fences[0]); @@ -270,37 +258,33 @@ static int find_signaled(void *arg) err = dma_fence_chain_find_seqno(&fence, 1); dma_fence_put(fence); if (err) { - pr_err("Reported %d for find_seqno()!\n", err); + KUNIT_FAIL(test, "Reported %d for find_seqno()!", err); goto err; } if (fence && fence != fc.chains[0]) { - pr_err("Incorrect chain-fence.seqno:%lld reported for completed seqno:1\n", - fence->seqno); + KUNIT_FAIL(test, "Incorrect chain-fence.seqno:%lld reported for completed seqno:1", + fence->seqno); dma_fence_get(fence); err = dma_fence_chain_find_seqno(&fence, 1); dma_fence_put(fence); if (err) - pr_err("Reported %d for finding self!\n", err); - - err = -EINVAL; + KUNIT_FAIL(test, "Reported %d for finding self!", err); } err: fence_chains_fini(&fc); - return err; } -static int find_out_of_order(void *arg) +static void test_find_out_of_order(struct kunit *test) { struct fence_chains fc; struct dma_fence *fence; int err; err = fence_chains_init(&fc, 3, seqno_inc); - if (err) - return err; + KUNIT_ASSERT_EQ_MSG(test, err, 0, "Failed to init fence chains"); dma_fence_signal(fc.fences[1]); @@ -308,7 +292,7 @@ static int find_out_of_order(void *arg) err = dma_fence_chain_find_seqno(&fence, 2); dma_fence_put(fence); if (err) { - pr_err("Reported %d for find_seqno()!\n", err); + KUNIT_FAIL(test, "Reported %d for find_seqno()!", err); goto err; } @@ -319,16 +303,12 @@ static int find_out_of_order(void *arg) * we should get as fence to wait upon (fence 2 being garbage * collected during the traversal of the chain). */ - if (fence != fc.chains[0]) { - pr_err("Incorrect chain-fence.seqno:%lld reported for completed seqno:2\n", - fence ? fence->seqno : 0); - - err = -EINVAL; - } + if (fence != fc.chains[0]) + KUNIT_FAIL(test, "Incorrect chain-fence.seqno:%lld reported for completed seqno:2", + fence ? fence->seqno : 0); err: fence_chains_fini(&fc); - return err; } static uint64_t seqno_inc2(unsigned int i) @@ -336,7 +316,7 @@ static uint64_t seqno_inc2(unsigned int i) return 2 * i + 2; } -static int find_gap(void *arg) +static void test_find_gap(struct kunit *test) { struct fence_chains fc; struct dma_fence *fence; @@ -344,24 +324,22 @@ static int find_gap(void *arg) int i; err = fence_chains_init(&fc, 64, seqno_inc2); - if (err) - return err; + KUNIT_ASSERT_EQ_MSG(test, err, 0, "Failed to init fence chains"); for (i = 0; i < fc.chain_length; i++) { fence = dma_fence_get(fc.tail); err = dma_fence_chain_find_seqno(&fence, 2 * i + 1); dma_fence_put(fence); if (err) { - pr_err("Reported %d for find_seqno(%d:%d)!\n", - err, fc.chain_length + 1, 2 * i + 1); + KUNIT_FAIL(test, "Reported %d for find_seqno(%d:%d)!", + err, fc.chain_length + 1, 2 * i + 1); goto err; } if (fence != fc.chains[i]) { - pr_err("Incorrect fence.seqno:%lld reported by find_seqno(%d:%d)\n", - fence->seqno, - fc.chain_length + 1, - 2 * i + 1); - err = -EINVAL; + KUNIT_FAIL(test, "Incorrect fence.seqno:%lld reported by find_seqno(%d:%d)", + fence->seqno, + fc.chain_length + 1, + 2 * i + 1); goto err; } @@ -369,19 +347,17 @@ static int find_gap(void *arg) err = dma_fence_chain_find_seqno(&fence, 2 * i + 2); dma_fence_put(fence); if (err) { - pr_err("Error reported for finding self\n"); + KUNIT_FAIL(test, "Error reported for finding self"); goto err; } if (fence != fc.chains[i]) { - pr_err("Incorrect fence reported by find self\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Incorrect fence reported by find self"); goto err; } } err: fence_chains_fini(&fc); - return err; } struct find_race { @@ -437,7 +413,7 @@ static int __find_race(void *arg) return err; } -static int find_race(void *arg) +static void test_find_race(struct kunit *test) { struct find_race data; int ncpus = num_online_cpus(); @@ -447,12 +423,11 @@ static int find_race(void *arg) int i; err = fence_chains_init(&data.fc, CHAIN_SZ, seqno_inc); - if (err) - return err; + KUNIT_ASSERT_EQ_MSG(test, err, 0, "Failed to init fence chains"); threads = kmalloc_objs(*threads, ncpus); if (!threads) { - err = -ENOMEM; + KUNIT_FAIL(test, "Failed to allocate threads array"); goto err; } @@ -486,74 +461,67 @@ static int find_race(void *arg) count++; pr_info("Completed %lu cycles\n", count); + KUNIT_EXPECT_EQ(test, err, 0); + err: fence_chains_fini(&data.fc); - return err; } -static int signal_forward(void *arg) +static void test_signal_forward(struct kunit *test) { struct fence_chains fc; int err; int i; err = fence_chains_init(&fc, 64, seqno_inc); - if (err) - return err; + KUNIT_ASSERT_EQ_MSG(test, err, 0, "Failed to init fence chains"); for (i = 0; i < fc.chain_length; i++) { dma_fence_signal(fc.fences[i]); if (!dma_fence_is_signaled(fc.chains[i])) { - pr_err("chain[%d] not signaled!\n", i); - err = -EINVAL; + KUNIT_FAIL(test, "chain[%d] not signaled!", i); goto err; } if (i + 1 < fc.chain_length && dma_fence_is_signaled(fc.chains[i + 1])) { - pr_err("chain[%d] is signaled!\n", i); - err = -EINVAL; + KUNIT_FAIL(test, "chain[%d] is signaled!", i); goto err; } } err: fence_chains_fini(&fc); - return err; } -static int signal_backward(void *arg) +static void test_signal_backward(struct kunit *test) { struct fence_chains fc; int err; int i; err = fence_chains_init(&fc, 64, seqno_inc); - if (err) - return err; + KUNIT_ASSERT_EQ_MSG(test, err, 0, "Failed to init fence chains"); for (i = fc.chain_length; i--; ) { dma_fence_signal(fc.fences[i]); if (i > 0 && dma_fence_is_signaled(fc.chains[i])) { - pr_err("chain[%d] is signaled!\n", i); - err = -EINVAL; + KUNIT_FAIL(test, "chain[%d] is signaled!", i); goto err; } } for (i = 0; i < fc.chain_length; i++) { if (!dma_fence_is_signaled(fc.chains[i])) { - pr_err("chain[%d] was not signaled!\n", i); - err = -EINVAL; + KUNIT_FAIL(test, "chain[%d] was not signaled!", i); goto err; } } err: fence_chains_fini(&fc); - return err; } static int __wait_fence_chains(void *arg) @@ -566,7 +534,7 @@ static int __wait_fence_chains(void *arg) return 0; } -static int wait_forward(void *arg) +static void test_wait_forward(struct kunit *test) { struct fence_chains fc; struct task_struct *tsk; @@ -574,12 +542,11 @@ static int wait_forward(void *arg) int i; err = fence_chains_init(&fc, CHAIN_SZ, seqno_inc); - if (err) - return err; + KUNIT_ASSERT_EQ_MSG(test, err, 0, "Failed to init fence chains"); tsk = kthread_run(__wait_fence_chains, &fc, "dmabuf/wait"); if (IS_ERR(tsk)) { - err = PTR_ERR(tsk); + KUNIT_FAIL(test, "Failed to create kthread"); goto err; } get_task_struct(tsk); @@ -589,13 +556,13 @@ static int wait_forward(void *arg) dma_fence_signal(fc.fences[i]); err = kthread_stop_put(tsk); + KUNIT_EXPECT_EQ(test, err, 0); err: fence_chains_fini(&fc); - return err; } -static int wait_backward(void *arg) +static void test_wait_backward(struct kunit *test) { struct fence_chains fc; struct task_struct *tsk; @@ -603,12 +570,11 @@ static int wait_backward(void *arg) int i; err = fence_chains_init(&fc, CHAIN_SZ, seqno_inc); - if (err) - return err; + KUNIT_ASSERT_EQ_MSG(test, err, 0, "Failed to init fence chains"); tsk = kthread_run(__wait_fence_chains, &fc, "dmabuf/wait"); if (IS_ERR(tsk)) { - err = PTR_ERR(tsk); + KUNIT_FAIL(test, "Failed to create kthread"); goto err; } get_task_struct(tsk); @@ -618,10 +584,10 @@ static int wait_backward(void *arg) dma_fence_signal(fc.fences[i]); err = kthread_stop_put(tsk); + KUNIT_EXPECT_EQ(test, err, 0); err: fence_chains_fini(&fc); - return err; } static void randomise_fences(struct fence_chains *fc) @@ -640,7 +606,7 @@ static void randomise_fences(struct fence_chains *fc) } } -static int wait_random(void *arg) +static void test_wait_random(struct kunit *test) { struct fence_chains fc; struct task_struct *tsk; @@ -648,14 +614,13 @@ static int wait_random(void *arg) int i; err = fence_chains_init(&fc, CHAIN_SZ, seqno_inc); - if (err) - return err; + KUNIT_ASSERT_EQ_MSG(test, err, 0, "Failed to init fence chains"); randomise_fences(&fc); tsk = kthread_run(__wait_fence_chains, &fc, "dmabuf/wait"); if (IS_ERR(tsk)) { - err = PTR_ERR(tsk); + KUNIT_FAIL(test, "Failed to create kthread"); goto err; } get_task_struct(tsk); @@ -665,29 +630,14 @@ static int wait_random(void *arg) dma_fence_signal(fc.fences[i]); err = kthread_stop_put(tsk); + KUNIT_EXPECT_EQ(test, err, 0); err: fence_chains_fini(&fc); - return err; } -int dma_fence_chain(void) +static int dma_fence_chain_suite_init(struct kunit_suite *suite) { - static const struct subtest tests[] = { - SUBTEST(sanitycheck), - SUBTEST(find_seqno), - SUBTEST(find_signaled), - SUBTEST(find_out_of_order), - SUBTEST(find_gap), - SUBTEST(find_race), - SUBTEST(signal_forward), - SUBTEST(signal_backward), - SUBTEST(wait_forward), - SUBTEST(wait_backward), - SUBTEST(wait_random), - }; - int ret; - pr_info("sizeof(dma_fence_chain)=%zu\n", sizeof(struct dma_fence_chain)); @@ -696,9 +646,34 @@ int dma_fence_chain(void) SLAB_HWCACHE_ALIGN); if (!slab_fences) return -ENOMEM; - - ret = subtests(tests, NULL); - - kmem_cache_destroy(slab_fences); - return ret; + return 0; } + +static void dma_fence_chain_suite_exit(struct kunit_suite *suite) +{ + kmem_cache_destroy(slab_fences); +} + +static struct kunit_case dma_fence_chain_cases[] = { + KUNIT_CASE(test_sanitycheck), + KUNIT_CASE(test_find_seqno), + KUNIT_CASE(test_find_signaled), + KUNIT_CASE(test_find_out_of_order), + KUNIT_CASE(test_find_gap), + KUNIT_CASE(test_find_race), + KUNIT_CASE(test_signal_forward), + KUNIT_CASE(test_signal_backward), + KUNIT_CASE(test_wait_forward), + KUNIT_CASE(test_wait_backward), + KUNIT_CASE(test_wait_random), + {} +}; + +static struct kunit_suite dma_fence_chain_test_suite = { + .name = "dma-buf-fence-chain", + .suite_init = dma_fence_chain_suite_init, + .suite_exit = dma_fence_chain_suite_exit, + .test_cases = dma_fence_chain_cases, +}; + +kunit_test_suite(dma_fence_chain_test_suite); diff --git a/drivers/dma-buf/st-dma-fence-unwrap.c b/drivers/dma-buf/st-dma-fence-unwrap.c index 9c74195f47fd..4e7ee25372ba 100644 --- a/drivers/dma-buf/st-dma-fence-unwrap.c +++ b/drivers/dma-buf/st-dma-fence-unwrap.c @@ -4,13 +4,12 @@ * Copyright (C) 2022 Advanced Micro Devices, Inc. */ +#include #include #include #include #include -#include "selftest.h" - #define CHAIN_SZ (4 << 10) struct mock_fence { @@ -65,7 +64,7 @@ static struct dma_fence *mock_array(unsigned int num_fences, ...) array = dma_fence_array_create(num_fences, fences, dma_fence_context_alloc(1), - 1, false); + 1); if (!array) goto error_free; return &array->base; @@ -97,52 +96,45 @@ static struct dma_fence *mock_chain(struct dma_fence *prev, return &f->base; } -static int sanitycheck(void *arg) +static void test_sanitycheck(struct kunit *test) { struct dma_fence *f, *chain, *array; - int err = 0; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); array = mock_array(1, f); - if (!array) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, array); chain = mock_chain(NULL, array); - if (!chain) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, chain); dma_fence_put(chain); - return err; } -static int unwrap_array(void *arg) +static void test_unwrap_array(struct kunit *test) { struct dma_fence *fence, *f1, *f2, *array; struct dma_fence_unwrap iter; - int err = 0; f1 = mock_fence(); - if (!f1) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f1); dma_fence_enable_sw_signaling(f1); f2 = mock_fence(); if (!f2) { + KUNIT_FAIL(test, "Failed to create mock fence"); dma_fence_put(f1); - return -ENOMEM; + return; } dma_fence_enable_sw_signaling(f2); array = mock_array(2, f1, f2); - if (!array) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, array); dma_fence_unwrap_for_each(fence, &iter, array) { if (fence == f1) { @@ -150,43 +142,37 @@ static int unwrap_array(void *arg) } else if (fence == f2) { f2 = NULL; } else { - pr_err("Unexpected fence!\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Unexpected fence!"); } } - if (f1 || f2) { - pr_err("Not all fences seen!\n"); - err = -EINVAL; - } + if (f1 || f2) + KUNIT_FAIL(test, "Not all fences seen!"); dma_fence_put(array); - return err; } -static int unwrap_chain(void *arg) +static void test_unwrap_chain(struct kunit *test) { struct dma_fence *fence, *f1, *f2, *chain; struct dma_fence_unwrap iter; - int err = 0; f1 = mock_fence(); - if (!f1) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f1); dma_fence_enable_sw_signaling(f1); f2 = mock_fence(); if (!f2) { + KUNIT_FAIL(test, "Failed to create mock fence"); dma_fence_put(f1); - return -ENOMEM; + return; } dma_fence_enable_sw_signaling(f2); chain = mock_chain(f1, f2); - if (!chain) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, chain); dma_fence_unwrap_for_each(fence, &iter, chain) { if (fence == f1) { @@ -194,47 +180,40 @@ static int unwrap_chain(void *arg) } else if (fence == f2) { f2 = NULL; } else { - pr_err("Unexpected fence!\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Unexpected fence!"); } } - if (f1 || f2) { - pr_err("Not all fences seen!\n"); - err = -EINVAL; - } + if (f1 || f2) + KUNIT_FAIL(test, "Not all fences seen!"); dma_fence_put(chain); - return err; } -static int unwrap_chain_array(void *arg) +static void test_unwrap_chain_array(struct kunit *test) { struct dma_fence *fence, *f1, *f2, *array, *chain; struct dma_fence_unwrap iter; - int err = 0; f1 = mock_fence(); - if (!f1) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f1); dma_fence_enable_sw_signaling(f1); f2 = mock_fence(); if (!f2) { + KUNIT_FAIL(test, "Failed to create mock fence"); dma_fence_put(f1); - return -ENOMEM; + return; } dma_fence_enable_sw_signaling(f2); array = mock_array(2, f1, f2); - if (!array) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, array); chain = mock_chain(NULL, array); - if (!chain) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, chain); dma_fence_unwrap_for_each(fence, &iter, chain) { if (fence == f1) { @@ -242,35 +221,29 @@ static int unwrap_chain_array(void *arg) } else if (fence == f2) { f2 = NULL; } else { - pr_err("Unexpected fence!\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Unexpected fence!"); } } - if (f1 || f2) { - pr_err("Not all fences seen!\n"); - err = -EINVAL; - } + if (f1 || f2) + KUNIT_FAIL(test, "Not all fences seen!"); dma_fence_put(chain); - return err; } -static int unwrap_merge(void *arg) +static void test_unwrap_merge(struct kunit *test) { struct dma_fence *fence, *f1, *f2, *f3; struct dma_fence_unwrap iter; - int err = 0; f1 = mock_fence(); - if (!f1) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f1); dma_fence_enable_sw_signaling(f1); f2 = mock_fence(); if (!f2) { - err = -ENOMEM; + KUNIT_FAIL(test, "Failed to create mock fence"); goto error_put_f1; } @@ -278,7 +251,7 @@ static int unwrap_merge(void *arg) f3 = dma_fence_unwrap_merge(f1, f2); if (!f3) { - err = -ENOMEM; + KUNIT_FAIL(test, "Failed to merge fences"); goto error_put_f2; } @@ -290,39 +263,33 @@ static int unwrap_merge(void *arg) dma_fence_put(f2); f2 = NULL; } else { - pr_err("Unexpected fence!\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Unexpected fence!"); } } - if (f1 || f2) { - pr_err("Not all fences seen!\n"); - err = -EINVAL; - } + if (f1 || f2) + KUNIT_FAIL(test, "Not all fences seen!"); dma_fence_put(f3); error_put_f2: dma_fence_put(f2); error_put_f1: dma_fence_put(f1); - return err; } -static int unwrap_merge_duplicate(void *arg) +static void test_unwrap_merge_duplicate(struct kunit *test) { struct dma_fence *fence, *f1, *f2; struct dma_fence_unwrap iter; - int err = 0; f1 = mock_fence(); - if (!f1) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f1); dma_fence_enable_sw_signaling(f1); f2 = dma_fence_unwrap_merge(f1, f1); if (!f2) { - err = -ENOMEM; + KUNIT_FAIL(test, "Failed to merge fences"); goto error_put_f1; } @@ -331,41 +298,35 @@ static int unwrap_merge_duplicate(void *arg) dma_fence_put(f1); f1 = NULL; } else { - pr_err("Unexpected fence!\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Unexpected fence!"); } } - if (f1) { - pr_err("Not all fences seen!\n"); - err = -EINVAL; - } + if (f1) + KUNIT_FAIL(test, "Not all fences seen!"); dma_fence_put(f2); error_put_f1: dma_fence_put(f1); - return err; } -static int unwrap_merge_seqno(void *arg) +static void test_unwrap_merge_seqno(struct kunit *test) { struct dma_fence *fence, *f1, *f2, *f3, *f4; struct dma_fence_unwrap iter; - int err = 0; u64 ctx[2]; ctx[0] = dma_fence_context_alloc(1); ctx[1] = dma_fence_context_alloc(1); f1 = __mock_fence(ctx[1], 1); - if (!f1) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f1); dma_fence_enable_sw_signaling(f1); f2 = __mock_fence(ctx[1], 2); if (!f2) { - err = -ENOMEM; + KUNIT_FAIL(test, "Failed to create mock fence"); goto error_put_f1; } @@ -373,7 +334,7 @@ static int unwrap_merge_seqno(void *arg) f3 = __mock_fence(ctx[0], 1); if (!f3) { - err = -ENOMEM; + KUNIT_FAIL(test, "Failed to create mock fence"); goto error_put_f2; } @@ -381,7 +342,7 @@ static int unwrap_merge_seqno(void *arg) f4 = dma_fence_unwrap_merge(f1, f2, f3); if (!f4) { - err = -ENOMEM; + KUNIT_FAIL(test, "Failed to merge fences"); goto error_put_f3; } @@ -393,15 +354,12 @@ static int unwrap_merge_seqno(void *arg) dma_fence_put(f2); f2 = NULL; } else { - pr_err("Unexpected fence!\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Unexpected fence!"); } } - if (f2 || f3) { - pr_err("Not all fences seen!\n"); - err = -EINVAL; - } + if (f2 || f3) + KUNIT_FAIL(test, "Not all fences seen!"); dma_fence_put(f4); error_put_f3: @@ -410,40 +368,41 @@ static int unwrap_merge_seqno(void *arg) dma_fence_put(f2); error_put_f1: dma_fence_put(f1); - return err; } -static int unwrap_merge_order(void *arg) +static void test_unwrap_merge_order(struct kunit *test) { struct dma_fence *fence, *f1, *f2, *a1, *a2, *c1, *c2; struct dma_fence_unwrap iter; - int err = 0; f1 = mock_fence(); - if (!f1) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f1); dma_fence_enable_sw_signaling(f1); f2 = mock_fence(); if (!f2) { + KUNIT_FAIL(test, "Failed to create mock fence"); dma_fence_put(f1); - return -ENOMEM; + return; } dma_fence_enable_sw_signaling(f2); a1 = mock_array(2, f1, f2); - if (!a1) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, a1); c1 = mock_chain(NULL, dma_fence_get(f1)); - if (!c1) + if (!c1) { + KUNIT_FAIL(test, "Failed to create chain"); goto error_put_a1; + } c2 = mock_chain(c1, dma_fence_get(f2)); - if (!c2) + if (!c2) { + KUNIT_FAIL(test, "Failed to create chain"); goto error_put_a1; + } /* * The fences in the chain are the same as in a1 but in oposite order, @@ -455,63 +414,64 @@ static int unwrap_merge_order(void *arg) if (fence == f1) { f1 = NULL; if (!f2) - pr_err("Unexpected order!\n"); + KUNIT_FAIL(test, "Unexpected order!"); } else if (fence == f2) { f2 = NULL; if (f1) - pr_err("Unexpected order!\n"); + KUNIT_FAIL(test, "Unexpected order!"); } else { - pr_err("Unexpected fence!\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Unexpected fence!"); } } - if (f1 || f2) { - pr_err("Not all fences seen!\n"); - err = -EINVAL; - } + if (f1 || f2) + KUNIT_FAIL(test, "Not all fences seen!"); dma_fence_put(a2); - return err; + return; error_put_a1: dma_fence_put(a1); - return -ENOMEM; } -static int unwrap_merge_complex(void *arg) +static void test_unwrap_merge_complex(struct kunit *test) { struct dma_fence *fence, *f1, *f2, *f3, *f4, *f5; struct dma_fence_unwrap iter; - int err = -ENOMEM; f1 = mock_fence(); - if (!f1) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f1); dma_fence_enable_sw_signaling(f1); f2 = mock_fence(); - if (!f2) + if (!f2) { + KUNIT_FAIL(test, "Failed to create mock fence"); goto error_put_f1; + } dma_fence_enable_sw_signaling(f2); f3 = dma_fence_unwrap_merge(f1, f2); - if (!f3) + if (!f3) { + KUNIT_FAIL(test, "Failed to merge fences"); goto error_put_f2; + } /* The resulting array has the fences in reverse */ f4 = mock_array(2, dma_fence_get(f2), dma_fence_get(f1)); - if (!f4) + if (!f4) { + KUNIT_FAIL(test, "Failed to create array"); goto error_put_f3; + } /* Signaled fences should be filtered, the two arrays merged. */ f5 = dma_fence_unwrap_merge(f3, f4, dma_fence_get_stub()); - if (!f5) + if (!f5) { + KUNIT_FAIL(test, "Failed to merge fences"); goto error_put_f4; + } - err = 0; dma_fence_unwrap_for_each(fence, &iter, f5) { if (fence == f1) { dma_fence_put(f1); @@ -520,15 +480,12 @@ static int unwrap_merge_complex(void *arg) dma_fence_put(f2); f2 = NULL; } else { - pr_err("Unexpected fence!\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Unexpected fence!"); } } - if (f1 || f2) { - pr_err("Not all fences seen!\n"); - err = -EINVAL; - } + if (f1 || f2) + KUNIT_FAIL(test, "Not all fences seen!"); dma_fence_put(f5); error_put_f4: @@ -539,56 +496,64 @@ static int unwrap_merge_complex(void *arg) dma_fence_put(f2); error_put_f1: dma_fence_put(f1); - return err; } -static int unwrap_merge_complex_seqno(void *arg) +static void test_unwrap_merge_complex_seqno(struct kunit *test) { struct dma_fence *fence, *f1, *f2, *f3, *f4, *f5, *f6, *f7; struct dma_fence_unwrap iter; - int err = -ENOMEM; u64 ctx[2]; ctx[0] = dma_fence_context_alloc(1); ctx[1] = dma_fence_context_alloc(1); f1 = __mock_fence(ctx[0], 2); - if (!f1) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f1); dma_fence_enable_sw_signaling(f1); f2 = __mock_fence(ctx[1], 1); - if (!f2) + if (!f2) { + KUNIT_FAIL(test, "Failed to create mock fence"); goto error_put_f1; + } dma_fence_enable_sw_signaling(f2); f3 = __mock_fence(ctx[0], 1); - if (!f3) + if (!f3) { + KUNIT_FAIL(test, "Failed to create mock fence"); goto error_put_f2; + } dma_fence_enable_sw_signaling(f3); f4 = __mock_fence(ctx[1], 2); - if (!f4) + if (!f4) { + KUNIT_FAIL(test, "Failed to create mock fence"); goto error_put_f3; + } dma_fence_enable_sw_signaling(f4); f5 = mock_array(2, dma_fence_get(f1), dma_fence_get(f2)); - if (!f5) + if (!f5) { + KUNIT_FAIL(test, "Failed to create array"); goto error_put_f4; + } f6 = mock_array(2, dma_fence_get(f3), dma_fence_get(f4)); - if (!f6) + if (!f6) { + KUNIT_FAIL(test, "Failed to create array"); goto error_put_f5; + } f7 = dma_fence_unwrap_merge(f5, f6); - if (!f7) + if (!f7) { + KUNIT_FAIL(test, "Failed to merge fences"); goto error_put_f6; + } - err = 0; dma_fence_unwrap_for_each(fence, &iter, f7) { if (fence == f1 && f4) { dma_fence_put(f1); @@ -597,15 +562,12 @@ static int unwrap_merge_complex_seqno(void *arg) dma_fence_put(f4); f4 = NULL; } else { - pr_err("Unexpected fence!\n"); - err = -EINVAL; + KUNIT_FAIL(test, "Unexpected fence!"); } } - if (f1 || f4) { - pr_err("Not all fences seen!\n"); - err = -EINVAL; - } + if (f1 || f4) + KUNIT_FAIL(test, "Not all fences seen!"); dma_fence_put(f7); error_put_f6: @@ -620,23 +582,25 @@ static int unwrap_merge_complex_seqno(void *arg) dma_fence_put(f2); error_put_f1: dma_fence_put(f1); - return err; } -int dma_fence_unwrap(void) -{ - static const struct subtest tests[] = { - SUBTEST(sanitycheck), - SUBTEST(unwrap_array), - SUBTEST(unwrap_chain), - SUBTEST(unwrap_chain_array), - SUBTEST(unwrap_merge), - SUBTEST(unwrap_merge_duplicate), - SUBTEST(unwrap_merge_seqno), - SUBTEST(unwrap_merge_order), - SUBTEST(unwrap_merge_complex), - SUBTEST(unwrap_merge_complex_seqno), - }; +static struct kunit_case dma_fence_unwrap_cases[] = { + KUNIT_CASE(test_sanitycheck), + KUNIT_CASE(test_unwrap_array), + KUNIT_CASE(test_unwrap_chain), + KUNIT_CASE(test_unwrap_chain_array), + KUNIT_CASE(test_unwrap_merge), + KUNIT_CASE(test_unwrap_merge_duplicate), + KUNIT_CASE(test_unwrap_merge_seqno), + KUNIT_CASE(test_unwrap_merge_order), + KUNIT_CASE(test_unwrap_merge_complex), + KUNIT_CASE(test_unwrap_merge_complex_seqno), + {} +}; - return subtests(tests, NULL); -} +static struct kunit_suite dma_fence_unwrap_test_suite = { + .name = "dma-buf-fence-unwrap", + .test_cases = dma_fence_unwrap_cases, +}; + +kunit_test_suite(dma_fence_unwrap_test_suite); diff --git a/drivers/dma-buf/st-dma-fence.c b/drivers/dma-buf/st-dma-fence.c index 0d9d524d79b6..499272229696 100644 --- a/drivers/dma-buf/st-dma-fence.c +++ b/drivers/dma-buf/st-dma-fence.c @@ -4,6 +4,7 @@ * Copyright © 2019 Intel Corporation */ +#include #include #include #include @@ -12,8 +13,6 @@ #include #include -#include "selftest.h" - static const char *mock_name(struct dma_fence *f) { return "mock"; @@ -36,62 +35,55 @@ static struct dma_fence *mock_fence(void) return f; } -static int sanitycheck(void *arg) +static void test_sanitycheck(struct kunit *test) { struct dma_fence *f; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); dma_fence_signal(f); dma_fence_put(f); - - return 0; } -static int test_signaling(void *arg) +static void test_signaling(struct kunit *test) { struct dma_fence *f; - int err = -EINVAL; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); if (dma_fence_is_signaled(f)) { - pr_err("Fence unexpectedly signaled on creation\n"); + KUNIT_FAIL(test, "Fence unexpectedly signaled on creation"); goto err_free; } if (dma_fence_check_and_signal(f)) { - pr_err("Fence reported being already signaled\n"); + KUNIT_FAIL(test, "Fence reported being already signaled"); goto err_free; } if (!dma_fence_is_signaled(f)) { - pr_err("Fence not reporting signaled\n"); + KUNIT_FAIL(test, "Fence not reporting signaled"); goto err_free; } if (!dma_fence_test_signaled_flag(f)) { - pr_err("Fence reported not being already signaled\n"); + KUNIT_FAIL(test, "Fence reported not being already signaled"); goto err_free; } if (rcu_dereference_protected(f->ops, true)) { - pr_err("Fence ops not cleared on signal\n"); + KUNIT_FAIL(test, "Fence ops not cleared on signal"); goto err_free; } - err = 0; err_free: dma_fence_put(f); - return err; } struct simple_cb { @@ -104,215 +96,187 @@ static void simple_callback(struct dma_fence *f, struct dma_fence_cb *cb) smp_store_mb(container_of(cb, struct simple_cb, cb)->seen, true); } -static int test_add_callback(void *arg) +static void test_add_callback(struct kunit *test) { struct simple_cb cb = {}; struct dma_fence *f; - int err = -EINVAL; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); if (dma_fence_add_callback(f, &cb.cb, simple_callback)) { - pr_err("Failed to add callback, fence already signaled!\n"); + KUNIT_FAIL(test, "Failed to add callback, fence already signaled!"); goto err_free; } dma_fence_signal(f); if (!cb.seen) { - pr_err("Callback failed!\n"); + KUNIT_FAIL(test, "Callback failed!"); goto err_free; } - err = 0; err_free: dma_fence_put(f); - return err; } -static int test_late_add_callback(void *arg) +static void test_late_add_callback(struct kunit *test) { struct simple_cb cb = {}; struct dma_fence *f; - int err = -EINVAL; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); dma_fence_signal(f); if (!dma_fence_add_callback(f, &cb.cb, simple_callback)) { - pr_err("Added callback, but fence was already signaled!\n"); + KUNIT_FAIL(test, "Added callback, but fence was already signaled!"); goto err_free; } dma_fence_signal(f); if (cb.seen) { - pr_err("Callback called after failed attachment !\n"); + KUNIT_FAIL(test, "Callback called after failed attachment!"); goto err_free; } - err = 0; err_free: dma_fence_put(f); - return err; } -static int test_rm_callback(void *arg) +static void test_rm_callback(struct kunit *test) { struct simple_cb cb = {}; struct dma_fence *f; - int err = -EINVAL; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); if (dma_fence_add_callback(f, &cb.cb, simple_callback)) { - pr_err("Failed to add callback, fence already signaled!\n"); + KUNIT_FAIL(test, "Failed to add callback, fence already signaled!"); goto err_free; } if (!dma_fence_remove_callback(f, &cb.cb)) { - pr_err("Failed to remove callback!\n"); + KUNIT_FAIL(test, "Failed to remove callback!"); goto err_free; } dma_fence_signal(f); if (cb.seen) { - pr_err("Callback still signaled after removal!\n"); + KUNIT_FAIL(test, "Callback still signaled after removal!"); goto err_free; } - err = 0; err_free: dma_fence_put(f); - return err; } -static int test_late_rm_callback(void *arg) +static void test_late_rm_callback(struct kunit *test) { struct simple_cb cb = {}; struct dma_fence *f; - int err = -EINVAL; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); if (dma_fence_add_callback(f, &cb.cb, simple_callback)) { - pr_err("Failed to add callback, fence already signaled!\n"); + KUNIT_FAIL(test, "Failed to add callback, fence already signaled!"); goto err_free; } dma_fence_signal(f); if (!cb.seen) { - pr_err("Callback failed!\n"); + KUNIT_FAIL(test, "Callback failed!"); goto err_free; } if (dma_fence_remove_callback(f, &cb.cb)) { - pr_err("Callback removal succeed after being executed!\n"); + KUNIT_FAIL(test, "Callback removal succeeded after being executed!"); goto err_free; } - err = 0; err_free: dma_fence_put(f); - return err; } -static int test_status(void *arg) +static void test_status(struct kunit *test) { struct dma_fence *f; - int err = -EINVAL; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); if (dma_fence_get_status(f)) { - pr_err("Fence unexpectedly has signaled status on creation\n"); + KUNIT_FAIL(test, "Fence unexpectedly has signaled status on creation"); goto err_free; } dma_fence_signal(f); if (!dma_fence_get_status(f)) { - pr_err("Fence not reporting signaled status\n"); + KUNIT_FAIL(test, "Fence not reporting signaled status"); goto err_free; } - err = 0; err_free: dma_fence_put(f); - return err; } -static int test_error(void *arg) +static void test_error(struct kunit *test) { struct dma_fence *f; - int err = -EINVAL; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); dma_fence_set_error(f, -EIO); if (dma_fence_get_status(f)) { - pr_err("Fence unexpectedly has error status before signal\n"); + KUNIT_FAIL(test, "Fence unexpectedly has error status before signal"); goto err_free; } dma_fence_signal(f); if (dma_fence_get_status(f) != -EIO) { - pr_err("Fence not reporting error status, got %d\n", - dma_fence_get_status(f)); + KUNIT_FAIL(test, "Fence not reporting error status, got %d", + dma_fence_get_status(f)); goto err_free; } - err = 0; err_free: dma_fence_put(f); - return err; } -static int test_wait(void *arg) +static void test_wait(struct kunit *test) { struct dma_fence *f; - int err = -EINVAL; f = mock_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); if (dma_fence_wait_timeout(f, false, 0) != 0) { - pr_err("Wait reported complete before being signaled\n"); + KUNIT_FAIL(test, "Wait reported complete before being signaled"); goto err_free; } dma_fence_signal(f); if (dma_fence_wait_timeout(f, false, 0) != 1) { - pr_err("Wait reported incomplete after being signaled\n"); + KUNIT_FAIL(test, "Wait reported incomplete after being signaled"); goto err_free; } - err = 0; err_free: dma_fence_signal(f); dma_fence_put(f); - return err; } struct wait_timer { @@ -327,21 +291,19 @@ static void wait_timer(struct timer_list *timer) dma_fence_signal(wt->f); } -static int test_wait_timeout(void *arg) +static void test_wait_timeout(struct kunit *test) { struct wait_timer wt; - int err = -EINVAL; timer_setup_on_stack(&wt.timer, wait_timer, 0); wt.f = mock_fence(); - if (!wt.f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, wt.f); dma_fence_enable_sw_signaling(wt.f); if (dma_fence_wait_timeout(wt.f, false, 1) != 0) { - pr_err("Wait reported complete before being signaled\n"); + KUNIT_FAIL(test, "Wait reported complete before being signaled"); goto err_free; } @@ -349,42 +311,38 @@ static int test_wait_timeout(void *arg) if (dma_fence_wait_timeout(wt.f, false, HZ) == 0) { if (timer_pending(&wt.timer)) { - pr_notice("Timer did not fire within one HZ!\n"); - err = 0; /* not our fault! */ + kunit_mark_skipped( + test, "Timer did not fire within on HZ!\n"); } else { - pr_err("Wait reported incomplete after timeout\n"); + KUNIT_FAIL(test, + "Wait reported incomplete after timeout"); } goto err_free; } - err = 0; err_free: timer_delete_sync(&wt.timer); timer_destroy_on_stack(&wt.timer); dma_fence_signal(wt.f); dma_fence_put(wt.f); - return err; } -static int test_stub(void *arg) +static void test_stub(struct kunit *test) { struct dma_fence *f[64]; - int err = -EINVAL; int i; for (i = 0; i < ARRAY_SIZE(f); i++) { f[i] = dma_fence_get_stub(); if (!dma_fence_is_signaled(f[i])) { - pr_err("Obtained unsignaled stub fence!\n"); + KUNIT_FAIL(test, "Obtained unsignaled stub fence!"); goto err; } } - err = 0; err: while (i--) dma_fence_put(f[i]); - return err; } /* Now off to the races! */ @@ -473,12 +431,19 @@ static int thread_signal_callback(void *arg) return err; } -static int race_signal_callback(void *arg) +static void test_race_signal_callback(struct kunit *test) { struct dma_fence __rcu *f[2] = {}; int ret = 0; int pass; + /* + * thread_signal_callback() spins under RCU and it cannot make forward + * progress unless the threads are truly running concurrently. + */ + if (num_online_cpus() < 2) + kunit_skip(test, "requires at least 2 CPUs"); + for (pass = 0; !ret && pass <= 1; pass++) { struct race_thread t[2]; int i; @@ -490,10 +455,10 @@ static int race_signal_callback(void *arg) t[i].task = kthread_run(thread_signal_callback, &t[i], "dma-fence:%d", i); if (IS_ERR(t[i].task)) { - ret = PTR_ERR(t[i].task); + KUNIT_FAIL(test, "Failed to create kthread"); while (--i >= 0) kthread_stop_put(t[i].task); - return ret; + return; } get_task_struct(t[i].task); } @@ -509,26 +474,35 @@ static int race_signal_callback(void *arg) } } - return ret; + KUNIT_EXPECT_EQ(test, ret, 0); } -int dma_fence(void) +static int dma_fence_suite_init(struct kunit_suite *suite) { - static const struct subtest tests[] = { - SUBTEST(sanitycheck), - SUBTEST(test_signaling), - SUBTEST(test_add_callback), - SUBTEST(test_late_add_callback), - SUBTEST(test_rm_callback), - SUBTEST(test_late_rm_callback), - SUBTEST(test_status), - SUBTEST(test_error), - SUBTEST(test_wait), - SUBTEST(test_wait_timeout), - SUBTEST(test_stub), - SUBTEST(race_signal_callback), - }; - pr_info("sizeof(dma_fence)=%zu\n", sizeof(struct dma_fence)); - return subtests(tests, NULL); + return 0; } + +static struct kunit_case dma_fence_cases[] = { + KUNIT_CASE(test_sanitycheck), + KUNIT_CASE(test_signaling), + KUNIT_CASE(test_add_callback), + KUNIT_CASE(test_late_add_callback), + KUNIT_CASE(test_rm_callback), + KUNIT_CASE(test_late_rm_callback), + KUNIT_CASE(test_status), + KUNIT_CASE(test_error), + KUNIT_CASE(test_wait), + KUNIT_CASE(test_wait_timeout), + KUNIT_CASE(test_stub), + KUNIT_CASE(test_race_signal_callback), + {} +}; + +static struct kunit_suite dma_fence_test_suite = { + .name = "dma-buf-fence", + .suite_init = dma_fence_suite_init, + .test_cases = dma_fence_cases, +}; + +kunit_test_suite(dma_fence_test_suite); diff --git a/drivers/dma-buf/st-dma-resv.c b/drivers/dma-buf/st-dma-resv.c index ad4dfb49dcd9..95a4becdb892 100644 --- a/drivers/dma-buf/st-dma-resv.c +++ b/drivers/dma-buf/st-dma-resv.c @@ -5,13 +5,17 @@ * Copyright © 2021 Advanced Micro Devices, Inc. */ +#include #include #include #include -#include "selftest.h" +static DEFINE_SPINLOCK(fence_lock); -static struct spinlock fence_lock; +struct dma_resv_usage_param { + enum dma_resv_usage usage; + const char *desc; +}; static const char *fence_name(struct dma_fence *f) { @@ -35,15 +39,14 @@ static struct dma_fence *alloc_fence(void) return f; } -static int sanitycheck(void *arg) +static void test_sanitycheck(struct kunit *test) { struct dma_resv resv; struct dma_fence *f; int r; f = alloc_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); @@ -53,49 +56,46 @@ static int sanitycheck(void *arg) dma_resv_init(&resv); r = dma_resv_lock(&resv, NULL); if (r) - pr_err("Resv locking failed\n"); + KUNIT_FAIL(test, "Resv locking failed\n"); else dma_resv_unlock(&resv); dma_resv_fini(&resv); - return r; } -static int test_signaling(void *arg) +static void test_signaling(struct kunit *test) { - enum dma_resv_usage usage = (unsigned long)arg; + const struct dma_resv_usage_param *param = test->param_value; + enum dma_resv_usage usage = param->usage; struct dma_resv resv; struct dma_fence *f; int r; f = alloc_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); dma_resv_init(&resv); r = dma_resv_lock(&resv, NULL); if (r) { - pr_err("Resv locking failed\n"); + KUNIT_FAIL(test, "Resv locking failed"); goto err_free; } r = dma_resv_reserve_fences(&resv, 1); if (r) { - pr_err("Resv shared slot allocation failed\n"); + KUNIT_FAIL(test, "Resv shared slot allocation failed"); goto err_unlock; } dma_resv_add_fence(&resv, f, usage); if (dma_resv_test_signaled(&resv, usage)) { - pr_err("Resv unexpectedly signaled\n"); - r = -EINVAL; + KUNIT_FAIL(test, "Resv unexpectedly signaled"); goto err_unlock; } dma_fence_signal(f); if (!dma_resv_test_signaled(&resv, usage)) { - pr_err("Resv not reporting signaled\n"); - r = -EINVAL; + KUNIT_FAIL(test, "Resv not reporting signaled"); goto err_unlock; } err_unlock: @@ -103,33 +103,32 @@ static int test_signaling(void *arg) err_free: dma_resv_fini(&resv); dma_fence_put(f); - return r; } -static int test_for_each(void *arg) +static void test_for_each(struct kunit *test) { - enum dma_resv_usage usage = (unsigned long)arg; + const struct dma_resv_usage_param *param = test->param_value; + enum dma_resv_usage usage = param->usage; struct dma_resv_iter cursor; struct dma_fence *f, *fence; struct dma_resv resv; int r; f = alloc_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); dma_resv_init(&resv); r = dma_resv_lock(&resv, NULL); if (r) { - pr_err("Resv locking failed\n"); + KUNIT_FAIL(test, "Resv locking failed"); goto err_free; } r = dma_resv_reserve_fences(&resv, 1); if (r) { - pr_err("Resv shared slot allocation failed\n"); + KUNIT_FAIL(test, "Resv shared slot allocation failed"); goto err_unlock; } @@ -138,24 +137,23 @@ static int test_for_each(void *arg) r = -ENOENT; dma_resv_for_each_fence(&cursor, &resv, usage, fence) { if (!r) { - pr_err("More than one fence found\n"); - r = -EINVAL; + KUNIT_FAIL(test, "More than one fence found"); goto err_unlock; } if (f != fence) { - pr_err("Unexpected fence\n"); + KUNIT_FAIL(test, "Unexpected fence"); r = -EINVAL; goto err_unlock; } if (dma_resv_iter_usage(&cursor) != usage) { - pr_err("Unexpected fence usage\n"); + KUNIT_FAIL(test, "Unexpected fence usage"); r = -EINVAL; goto err_unlock; } r = 0; } if (r) { - pr_err("No fence found\n"); + KUNIT_FAIL(test, "No fence found"); goto err_unlock; } dma_fence_signal(f); @@ -164,33 +162,32 @@ static int test_for_each(void *arg) err_free: dma_resv_fini(&resv); dma_fence_put(f); - return r; } -static int test_for_each_unlocked(void *arg) +static void test_for_each_unlocked(struct kunit *test) { - enum dma_resv_usage usage = (unsigned long)arg; + const struct dma_resv_usage_param *param = test->param_value; + enum dma_resv_usage usage = param->usage; struct dma_resv_iter cursor; struct dma_fence *f, *fence; struct dma_resv resv; int r; f = alloc_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); dma_resv_init(&resv); r = dma_resv_lock(&resv, NULL); if (r) { - pr_err("Resv locking failed\n"); + KUNIT_FAIL(test, "Resv locking failed"); goto err_free; } r = dma_resv_reserve_fences(&resv, 1); if (r) { - pr_err("Resv shared slot allocation failed\n"); + KUNIT_FAIL(test, "Resv shared slot allocation failed"); dma_resv_unlock(&resv); goto err_free; } @@ -202,21 +199,20 @@ static int test_for_each_unlocked(void *arg) dma_resv_iter_begin(&cursor, &resv, usage); dma_resv_for_each_fence_unlocked(&cursor, fence) { if (!r) { - pr_err("More than one fence found\n"); - r = -EINVAL; + KUNIT_FAIL(test, "More than one fence found"); goto err_iter_end; } if (!dma_resv_iter_is_restarted(&cursor)) { - pr_err("No restart flag\n"); + KUNIT_FAIL(test, "No restart flag"); goto err_iter_end; } if (f != fence) { - pr_err("Unexpected fence\n"); + KUNIT_FAIL(test, "Unexpected fence"); r = -EINVAL; goto err_iter_end; } if (dma_resv_iter_usage(&cursor) != usage) { - pr_err("Unexpected fence usage\n"); + KUNIT_FAIL(test, "Unexpected fence usage"); r = -EINVAL; goto err_iter_end; } @@ -230,40 +226,38 @@ static int test_for_each_unlocked(void *arg) r = 0; } } - if (r) - pr_err("No fence found\n"); + KUNIT_EXPECT_EQ(test, r, 0); err_iter_end: dma_resv_iter_end(&cursor); dma_fence_signal(f); err_free: dma_resv_fini(&resv); dma_fence_put(f); - return r; } -static int test_get_fences(void *arg) +static void test_get_fences(struct kunit *test) { - enum dma_resv_usage usage = (unsigned long)arg; + const struct dma_resv_usage_param *param = test->param_value; + enum dma_resv_usage usage = param->usage; struct dma_fence *f, **fences = NULL; struct dma_resv resv; int r, i; f = alloc_fence(); - if (!f) - return -ENOMEM; + KUNIT_ASSERT_NOT_NULL(test, f); dma_fence_enable_sw_signaling(f); dma_resv_init(&resv); r = dma_resv_lock(&resv, NULL); if (r) { - pr_err("Resv locking failed\n"); + KUNIT_FAIL(test, "Resv locking failed"); goto err_resv; } r = dma_resv_reserve_fences(&resv, 1); if (r) { - pr_err("Resv shared slot allocation failed\n"); + KUNIT_FAIL(test, "Resv shared slot allocation failed"); dma_resv_unlock(&resv); goto err_resv; } @@ -273,12 +267,12 @@ static int test_get_fences(void *arg) r = dma_resv_get_fences(&resv, usage, &i, &fences); if (r) { - pr_err("get_fences failed\n"); + KUNIT_FAIL(test, "get_fences failed"); goto err_free; } if (i != 1 || fences[0] != f) { - pr_err("get_fences returned unexpected fence\n"); + KUNIT_FAIL(test, "get_fences returned unexpected fence"); goto err_free; } @@ -290,27 +284,32 @@ static int test_get_fences(void *arg) err_resv: dma_resv_fini(&resv); dma_fence_put(f); - return r; } -int dma_resv(void) -{ - static const struct subtest tests[] = { - SUBTEST(sanitycheck), - SUBTEST(test_signaling), - SUBTEST(test_for_each), - SUBTEST(test_for_each_unlocked), - SUBTEST(test_get_fences), - }; - enum dma_resv_usage usage; - int r; +static const struct dma_resv_usage_param dma_resv_usage_params[] = { + { DMA_RESV_USAGE_KERNEL, "kernel" }, + { DMA_RESV_USAGE_WRITE, "write" }, + { DMA_RESV_USAGE_READ, "read" }, + { DMA_RESV_USAGE_BOOKKEEP, "bookkeep" }, +}; - spin_lock_init(&fence_lock); - for (usage = DMA_RESV_USAGE_KERNEL; usage <= DMA_RESV_USAGE_BOOKKEEP; - ++usage) { - r = subtests(tests, (void *)(unsigned long)usage); - if (r) - return r; - } - return 0; -} +KUNIT_ARRAY_PARAM_DESC(dma_resv_usage, dma_resv_usage_params, desc); + +static struct kunit_case dma_resv_cases[] = { + KUNIT_CASE(test_sanitycheck), + KUNIT_CASE_PARAM(test_signaling, dma_resv_usage_gen_params), + KUNIT_CASE_PARAM(test_for_each, dma_resv_usage_gen_params), + KUNIT_CASE_PARAM(test_for_each_unlocked, dma_resv_usage_gen_params), + KUNIT_CASE_PARAM(test_get_fences, dma_resv_usage_gen_params), + {} +}; + +static struct kunit_suite dma_resv_test_suite = { + .name = "dma-buf-resv", + .test_cases = dma_resv_cases, +}; + +kunit_test_suite(dma_resv_test_suite); + +MODULE_DESCRIPTION("KUnit tests for DMA-BUF"); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma-buf/udmabuf.c b/drivers/dma-buf/udmabuf.c index 94b8ecb892bb..bced421c0d65 100644 --- a/drivers/dma-buf/udmabuf.c +++ b/drivers/dma-buf/udmabuf.c @@ -26,10 +26,10 @@ MODULE_PARM_DESC(size_limit_mb, "Max size of a dmabuf, in megabytes. Default is struct udmabuf { pgoff_t pagecount; - struct folio **folios; + struct page **pages; /** - * Unlike folios, pinned_folios is only used for unpin. + * Unlike pages, pinned_folios is only used for unpin. * So, nr_pinned is not the same to pagecount, the pinned_folios * only set each folio which already pinned when udmabuf_create. * Note that, since a folio may be pinned multiple times, each folio @@ -40,8 +40,8 @@ struct udmabuf { struct folio **pinned_folios; struct sg_table *sg; + enum dma_data_direction sg_dir; struct miscdevice *device; - pgoff_t *offsets; }; static vm_fault_t udmabuf_vm_fault(struct vm_fault *vmf) @@ -55,8 +55,7 @@ static vm_fault_t udmabuf_vm_fault(struct vm_fault *vmf) if (pgoff >= ubuf->pagecount) return VM_FAULT_SIGBUS; - pfn = folio_pfn(ubuf->folios[pgoff]); - pfn += ubuf->offsets[pgoff] >> PAGE_SHIFT; + pfn = page_to_pfn(ubuf->pages[pgoff]); ret = vmf_insert_pfn(vma, vmf->address, pfn); if (ret & VM_FAULT_ERROR) @@ -73,8 +72,7 @@ static vm_fault_t udmabuf_vm_fault(struct vm_fault *vmf) if (WARN_ON(pgoff >= ubuf->pagecount)) break; - pfn = folio_pfn(ubuf->folios[pgoff]); - pfn += ubuf->offsets[pgoff] >> PAGE_SHIFT; + pfn = page_to_pfn(ubuf->pages[pgoff]); /** * If the below vmf_insert_pfn() fails, we do not return an @@ -109,22 +107,11 @@ static int mmap_udmabuf(struct dma_buf *buf, struct vm_area_struct *vma) static int vmap_udmabuf(struct dma_buf *buf, struct iosys_map *map) { struct udmabuf *ubuf = buf->priv; - struct page **pages; void *vaddr; - pgoff_t pg; dma_resv_assert_held(buf->resv); - pages = kvmalloc_objs(*pages, ubuf->pagecount); - if (!pages) - return -ENOMEM; - - for (pg = 0; pg < ubuf->pagecount; pg++) - pages[pg] = folio_page(ubuf->folios[pg], - ubuf->offsets[pg] >> PAGE_SHIFT); - - vaddr = vm_map_ram(pages, ubuf->pagecount, -1); - kvfree(pages); + vaddr = vm_map_ram(ubuf->pages, ubuf->pagecount, -1); if (!vaddr) return -EINVAL; @@ -146,23 +133,19 @@ static struct sg_table *get_sg_table(struct device *dev, struct dma_buf *buf, { struct udmabuf *ubuf = buf->priv; struct sg_table *sg; - struct scatterlist *sgl; - unsigned int i = 0; int ret; sg = kzalloc_obj(*sg); if (!sg) return ERR_PTR(-ENOMEM); - ret = sg_alloc_table(sg, ubuf->pagecount, GFP_KERNEL); + ret = sg_alloc_table_from_pages(sg, ubuf->pages, ubuf->pagecount, 0, + ubuf->pagecount << PAGE_SHIFT, + GFP_KERNEL); if (ret < 0) goto err_alloc; - for_each_sg(sg->sgl, sgl, ubuf->pagecount, i) - sg_set_folio(sgl, ubuf->folios[i], PAGE_SIZE, - ubuf->offsets[i]); - - ret = dma_map_sgtable(dev, sg, direction, 0); + ret = dma_map_sgtable(dev, sg, direction, DMA_ATTR_SKIP_CPU_SYNC); if (ret < 0) goto err_map; return sg; @@ -177,7 +160,7 @@ static struct sg_table *get_sg_table(struct device *dev, struct dma_buf *buf, static void put_sg_table(struct device *dev, struct sg_table *sg, enum dma_data_direction direction) { - dma_unmap_sgtable(dev, sg, direction, 0); + dma_unmap_sgtable(dev, sg, direction, DMA_ATTR_SKIP_CPU_SYNC); sg_free_table(sg); kfree(sg); } @@ -207,12 +190,8 @@ static void unpin_all_folios(struct udmabuf *ubuf) static __always_inline int init_udmabuf(struct udmabuf *ubuf, pgoff_t pgcnt) { - ubuf->folios = kvmalloc_objs(*ubuf->folios, pgcnt); - if (!ubuf->folios) - return -ENOMEM; - - ubuf->offsets = kvzalloc_objs(*ubuf->offsets, pgcnt); - if (!ubuf->offsets) + ubuf->pages = kvmalloc_objs(*ubuf->pages, pgcnt); + if (!ubuf->pages) return -ENOMEM; ubuf->pinned_folios = kvmalloc_objs(*ubuf->pinned_folios, pgcnt); @@ -225,8 +204,7 @@ static __always_inline int init_udmabuf(struct udmabuf *ubuf, pgoff_t pgcnt) static __always_inline void deinit_udmabuf(struct udmabuf *ubuf) { unpin_all_folios(ubuf); - kvfree(ubuf->offsets); - kvfree(ubuf->folios); + kvfree(ubuf->pages); } static void release_udmabuf(struct dma_buf *buf) @@ -235,7 +213,7 @@ static void release_udmabuf(struct dma_buf *buf) struct device *dev = ubuf->device->this_device; if (ubuf->sg) - put_sg_table(dev, ubuf->sg, DMA_BIDIRECTIONAL); + put_sg_table(dev, ubuf->sg, ubuf->sg_dir); deinit_udmabuf(ubuf); kfree(ubuf); @@ -253,6 +231,8 @@ static int begin_cpu_udmabuf(struct dma_buf *buf, if (IS_ERR(ubuf->sg)) { ret = PTR_ERR(ubuf->sg); ubuf->sg = NULL; + } else { + ubuf->sg_dir = direction; } } else { dma_sync_sgtable_for_cpu(dev, ubuf->sg, direction); @@ -344,8 +324,8 @@ static long udmabuf_pin_folios(struct udmabuf *ubuf, struct file *memfd, ubuf->pinned_folios[nr_pinned++] = folios[cur_folio]; for (; subpgoff < fsize; subpgoff += PAGE_SIZE) { - ubuf->folios[upgcnt] = folios[cur_folio]; - ubuf->offsets[upgcnt] = subpgoff; + ubuf->pages[upgcnt] = folio_page(folios[cur_folio], + subpgoff >> PAGE_SHIFT); ++upgcnt; if (++cur_pgcnt >= pgcnt) diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index af7ce62ec55c..0ff1658c2dc1 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -900,11 +900,21 @@ int dpll_pin_delete_ntf(struct dpll_pin *pin) return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin); } +/** + * __dpll_pin_change_ntf - notify that the pin has been changed + * @pin: registered pin pointer + * + * Context: caller must hold dpll_lock. Suitable for use inside pin + * callbacks which are already invoked under dpll_lock. + * Return: 0 if succeeds, error code otherwise. + */ int __dpll_pin_change_ntf(struct dpll_pin *pin) { + lockdep_assert_held(&dpll_lock); dpll_pin_notify(pin, DPLL_PIN_CHANGED); return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin); } +EXPORT_SYMBOL_GPL(__dpll_pin_change_ntf); /** * dpll_pin_change_ntf - notify that the pin has been changed diff --git a/drivers/dpll/dpll_netlink.h b/drivers/dpll/dpll_netlink.h index dd28b56d27c5..a9cfd55f57fc 100644 --- a/drivers/dpll/dpll_netlink.h +++ b/drivers/dpll/dpll_netlink.h @@ -11,5 +11,3 @@ int dpll_device_delete_ntf(struct dpll_device *dpll); int dpll_pin_create_ntf(struct dpll_pin *pin); int dpll_pin_delete_ntf(struct dpll_pin *pin); - -int __dpll_pin_change_ntf(struct dpll_pin *pin); diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index c95e93ef3ab0..64b4e9e3e8fe 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -1394,8 +1394,8 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index) err_register: dpll_pin_put(pin->dpll_pin, &pin->tracker); - pin->dpll_pin = NULL; err_pin_get: + pin->dpll_pin = NULL; fwnode_handle_put(pin->fwnode); pin->fwnode = NULL; zl3073x_pin_props_put(props); @@ -1563,8 +1563,10 @@ zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll) } rc = zl3073x_dpll_pin_register(pin, index); - if (rc) + if (rc) { + zl3073x_dpll_pin_free(pin); goto error; + } list_add(&pin->list, &zldpll->pins); } diff --git a/drivers/edac/versalnet_edac.c b/drivers/edac/versalnet_edac.c index ec1315582414..97ec05d68bbb 100644 --- a/drivers/edac/versalnet_edac.c +++ b/drivers/edac/versalnet_edac.c @@ -777,9 +777,9 @@ static int init_one_mc(struct mc_priv *priv, struct platform_device *pdev, int i u32 num_chans, rank, dwidth, config; struct edac_mc_layer layers[2]; struct mem_ctl_info *mci; + char name[MC_NAME_LEN]; struct device *dev; enum dev_type dt; - char *name; int rc; config = priv->adec[CONF + i * ADEC_NUM]; @@ -813,13 +813,9 @@ static int init_one_mc(struct mc_priv *priv, struct platform_device *pdev, int i layers[1].is_virt_csrow = false; rc = -ENOMEM; - name = kzalloc(MC_NAME_LEN, GFP_KERNEL); - if (!name) - return rc; - dev = kzalloc(sizeof(*dev), GFP_KERNEL); if (!dev) - goto err_name_free; + return rc; mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers, sizeof(struct mc_priv)); if (!mci) { @@ -858,8 +854,6 @@ static int init_one_mc(struct mc_priv *priv, struct platform_device *pdev, int i edac_mc_free(mci); err_dev_free: kfree(dev); -err_name_free: - kfree(name); return rc; } diff --git a/drivers/firmware/arm_ffa/bus.c b/drivers/firmware/arm_ffa/bus.c index 9576862d89c4..601c3418e0d9 100644 --- a/drivers/firmware/arm_ffa/bus.c +++ b/drivers/firmware/arm_ffa/bus.c @@ -26,6 +26,8 @@ static int ffa_device_match(struct device *dev, const struct device_driver *drv) id_table = to_ffa_driver(drv)->id_table; ffa_dev = to_ffa_dev(dev); + if (!id_table) + return 0; while (!uuid_is_null(&id_table->uuid)) { /* @@ -123,7 +125,7 @@ int ffa_driver_register(struct ffa_driver *driver, struct module *owner, { int ret; - if (!driver->probe) + if (!driver->probe || !driver->id_table) return -EINVAL; driver->driver.bus = &ffa_bus_type; diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index eb2782848283..b9f17fda7243 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -87,6 +87,7 @@ static inline int ffa_to_linux_errno(int errno) struct ffa_pcpu_irq { struct ffa_drv_info *info; + struct work_struct notif_pcpu_work; }; struct ffa_drv_info { @@ -100,13 +101,13 @@ struct ffa_drv_info { bool mem_ops_native; bool msg_direct_req2_supp; bool bitmap_created; + bool bus_notifier_registered; bool notif_enabled; unsigned int sched_recv_irq; unsigned int notif_pend_irq; unsigned int cpuhp_state; struct ffa_pcpu_irq __percpu *irq_pcpu; struct workqueue_struct *notif_pcpu_wq; - struct work_struct notif_pcpu_work; struct work_struct sched_recv_irq_work; struct xarray partition_info; DECLARE_HASHTABLE(notifier_hash, ilog2(FFA_MAX_NOTIFICATIONS)); @@ -322,6 +323,12 @@ __ffa_partition_info_get(u32 uuid0, u32 uuid1, u32 uuid2, u32 uuid3, #define PART_INFO_ID_MASK GENMASK(15, 0) #define PART_INFO_EXEC_CXT_MASK GENMASK(31, 16) #define PART_INFO_PROPS_MASK GENMASK(63, 32) +#define FFA_PART_INFO_GET_REGS_FIRST_REG 3 +#define FFA_PART_INFO_GET_REGS_REGS_PER_DESC 3 +#define FFA_PART_INFO_GET_REGS_MAX_DESC \ + (((sizeof(ffa_value_t) / sizeof_field(ffa_value_t, a0)) - \ + FFA_PART_INFO_GET_REGS_FIRST_REG) / \ + FFA_PART_INFO_GET_REGS_REGS_PER_DESC) #define PART_INFO_ID(x) ((u16)(FIELD_GET(PART_INFO_ID_MASK, (x)))) #define PART_INFO_EXEC_CXT(x) ((u16)(FIELD_GET(PART_INFO_EXEC_CXT_MASK, (x)))) #define PART_INFO_PROPERTIES(x) ((u32)(FIELD_GET(PART_INFO_PROPS_MASK, (x)))) @@ -329,15 +336,13 @@ static int __ffa_partition_info_get_regs(u32 uuid0, u32 uuid1, u32 uuid2, u32 uuid3, struct ffa_partition_info *buffer, int num_parts) { - u16 buf_sz, start_idx, cur_idx, count = 0, prev_idx = 0, tag = 0; + u16 buf_sz, start_idx = 0, cur_idx, count = 0, tag = 0; struct ffa_partition_info *buf = buffer; ffa_value_t partition_info; do { __le64 *regs; - int idx; - - start_idx = prev_idx ? prev_idx + 1 : 0; + int idx, nr_desc, buf_idx; invoke_ffa_fn((ffa_value_t){ .a0 = FFA_PARTITION_INFO_GET_REGS, @@ -353,15 +358,28 @@ __ffa_partition_info_get_regs(u32 uuid0, u32 uuid1, u32 uuid2, u32 uuid3, count = PARTITION_COUNT(partition_info.a2); if (!buffer || !num_parts) /* count only */ return count; + if (count > num_parts) + return -EINVAL; cur_idx = CURRENT_INDEX(partition_info.a2); + if (cur_idx < start_idx || cur_idx >= count) + return -EINVAL; + + nr_desc = cur_idx - start_idx + 1; + if (nr_desc > FFA_PART_INFO_GET_REGS_MAX_DESC) + return -EINVAL; + + buf_idx = buf - buffer; + if (buf_idx + nr_desc > num_parts) + return -EINVAL; + tag = UUID_INFO_TAG(partition_info.a2); buf_sz = PARTITION_INFO_SZ(partition_info.a2); if (buf_sz > sizeof(*buffer)) buf_sz = sizeof(*buffer); regs = (void *)&partition_info.a3; - for (idx = 0; idx < cur_idx - start_idx + 1; idx++, buf++) { + for (idx = 0; idx < nr_desc; idx++, buf++) { union { uuid_t uuid; u64 regs[2]; @@ -379,7 +397,7 @@ __ffa_partition_info_get_regs(u32 uuid0, u32 uuid1, u32 uuid2, u32 uuid3, uuid_copy(&buf->uuid, &uuid_regs.uuid); regs += 3; } - prev_idx = cur_idx; + start_idx = cur_idx + 1; } while (cur_idx < (count - 1)); @@ -1189,7 +1207,7 @@ static int ffa_sched_recv_cb_update(struct ffa_device *dev, ffa_sched_recv_cb callback, void *cb_data, bool is_registration) { - struct ffa_dev_part_info *partition = NULL, *tmp; + struct ffa_dev_part_info *partition = NULL; struct list_head *phead; bool cb_valid; @@ -1202,11 +1220,11 @@ ffa_sched_recv_cb_update(struct ffa_device *dev, ffa_sched_recv_cb callback, return -EINVAL; } - list_for_each_entry_safe(partition, tmp, phead, node) + list_for_each_entry(partition, phead, node) if (partition->dev == dev) break; - if (!partition) { + if (&partition->node == phead) { pr_err("%s: No such partition ID 0x%x\n", __func__, dev->vm_id); return -EINVAL; } @@ -1445,20 +1463,25 @@ static int ffa_notify_send(struct ffa_device *dev, int notify_id, static void handle_notif_callbacks(u64 bitmap, enum notify_type type) { + ffa_notifier_cb cb; + void *cb_data; int notify_id; - struct notifier_cb_info *cb_info = NULL; for (notify_id = 0; notify_id <= FFA_MAX_NOTIFICATIONS && bitmap; notify_id++, bitmap >>= 1) { if (!(bitmap & 1)) continue; - read_lock(&drv_info->notify_lock); - cb_info = notifier_hnode_get_by_type(notify_id, type); - read_unlock(&drv_info->notify_lock); + scoped_guard(read_lock, &drv_info->notify_lock) { + struct notifier_cb_info *cb_info; - if (cb_info && cb_info->cb) - cb_info->cb(notify_id, cb_info->cb_data); + cb_info = notifier_hnode_get_by_type(notify_id, type); + cb = cb_info ? cb_info->cb : NULL; + cb_data = cb_info ? cb_info->cb_data : NULL; + } + + if (cb) + cb(notify_id, cb_data); } } @@ -1466,39 +1489,56 @@ static void handle_fwk_notif_callbacks(u32 bitmap) { void *buf; uuid_t uuid; + void *fwk_cb_data; int notify_id = 0, target; + ffa_fwk_notifier_cb fwk_cb; struct ffa_indirect_msg_hdr *msg; - struct notifier_cb_info *cb_info = NULL; + size_t min_offset = offsetof(struct ffa_indirect_msg_hdr, uuid); /* Only one framework notification defined and supported for now */ if (!(bitmap & FRAMEWORK_NOTIFY_RX_BUFFER_FULL)) return; - mutex_lock(&drv_info->rx_lock); + scoped_guard(mutex, &drv_info->rx_lock) { + u32 offset, size; - msg = drv_info->rx_buffer; - buf = kmemdup((void *)msg + msg->offset, msg->size, GFP_KERNEL); - if (!buf) { - mutex_unlock(&drv_info->rx_lock); - return; + msg = drv_info->rx_buffer; + offset = msg->offset; + size = msg->size; + + if (!size || (offset != min_offset && offset < sizeof(*msg)) || + offset > drv_info->rxtx_bufsz || + size > drv_info->rxtx_bufsz - offset) { + pr_err("invalid framework notification message\n"); + ffa_rx_release(); + return; + } + + buf = kmemdup((void *)msg + offset, size, GFP_KERNEL); + if (!buf) { + ffa_rx_release(); + return; + } + + target = SENDER_ID(msg->send_recv_id); + if (offset >= sizeof(*msg)) + uuid_copy(&uuid, &msg->uuid); + else + uuid_copy(&uuid, &uuid_null); + ffa_rx_release(); } - target = SENDER_ID(msg->send_recv_id); - if (msg->offset >= sizeof(*msg)) - uuid_copy(&uuid, &msg->uuid); - else - uuid_copy(&uuid, &uuid_null); + scoped_guard(read_lock, &drv_info->notify_lock) { + struct notifier_cb_info *cb_info; - mutex_unlock(&drv_info->rx_lock); + cb_info = notifier_hnode_get_by_vmid_uuid(notify_id, target, + &uuid); + fwk_cb = cb_info ? cb_info->fwk_cb : NULL; + fwk_cb_data = cb_info ? cb_info->cb_data : NULL; + } - ffa_rx_release(); - - read_lock(&drv_info->notify_lock); - cb_info = notifier_hnode_get_by_vmid_uuid(notify_id, target, &uuid); - read_unlock(&drv_info->notify_lock); - - if (cb_info && cb_info->fwk_cb) - cb_info->fwk_cb(notify_id, cb_info->cb_data, buf); + if (fwk_cb) + fwk_cb(notify_id, fwk_cb_data, buf); kfree(buf); } @@ -1539,10 +1579,11 @@ ffa_self_notif_handle(u16 vcpu, bool is_per_vcpu, void *cb_data) static void notif_pcpu_irq_work_fn(struct work_struct *work) { - struct ffa_drv_info *info = container_of(work, struct ffa_drv_info, + struct ffa_pcpu_irq *pcpu = container_of(work, struct ffa_pcpu_irq, notif_pcpu_work); + struct ffa_drv_info *info = pcpu->info; - ffa_self_notif_handle(smp_processor_id(), true, info); + notif_get_and_handle(info); } static const struct ffa_info_ops ffa_drv_info_ops = { @@ -1629,6 +1670,15 @@ static struct notifier_block ffa_bus_nb = { .notifier_call = ffa_bus_notifier, }; +static void ffa_bus_notifier_unregister(void) +{ + if (!drv_info->bus_notifier_registered) + return; + + bus_unregister_notifier(&ffa_bus_type, &ffa_bus_nb); + drv_info->bus_notifier_registered = false; +} + static int ffa_xa_add_partition_info(struct ffa_device *dev) { struct ffa_dev_part_info *info; @@ -1712,6 +1762,8 @@ static void ffa_partitions_cleanup(void) struct list_head *phead; unsigned long idx; + ffa_bus_notifier_unregister(); + /* Clean up/free all registered devices */ ffa_devices_unregister(); @@ -1739,11 +1791,14 @@ static int ffa_setup_partitions(void) ret = bus_register_notifier(&ffa_bus_type, &ffa_bus_nb); if (ret) pr_err("Failed to register FF-A bus notifiers\n"); + else + drv_info->bus_notifier_registered = true; } count = ffa_partition_probe(&uuid_null, &pbuf); if (count <= 0) { pr_info("%s: No partitions found, error %d\n", __func__, count); + ffa_bus_notifier_unregister(); return -EINVAL; } @@ -1811,7 +1866,7 @@ static irqreturn_t notif_pend_irq_handler(int irq, void *irq_data) struct ffa_drv_info *info = pcpu->info; queue_work_on(smp_processor_id(), info->notif_pcpu_wq, - &info->notif_pcpu_work); + &pcpu->notif_pcpu_work); return IRQ_HANDLED; } @@ -1928,8 +1983,11 @@ static int ffa_init_pcpu_irq(void) if (!irq_pcpu) return -ENOMEM; - for_each_present_cpu(cpu) + for_each_present_cpu(cpu) { per_cpu_ptr(irq_pcpu, cpu)->info = drv_info; + INIT_WORK(&per_cpu_ptr(irq_pcpu, cpu)->notif_pcpu_work, + notif_pcpu_irq_work_fn); + } drv_info->irq_pcpu = irq_pcpu; @@ -1958,7 +2016,6 @@ static int ffa_init_pcpu_irq(void) } INIT_WORK(&drv_info->sched_recv_irq_work, ffa_sched_recv_irq_work_fn); - INIT_WORK(&drv_info->notif_pcpu_work, notif_pcpu_irq_work_fn); drv_info->notif_pcpu_wq = create_workqueue("ffa_pcpu_irq_notification"); if (!drv_info->notif_pcpu_wq) return -EINVAL; @@ -2063,11 +2120,12 @@ static int __init ffa_init(void) rxtx_bufsz = SZ_4K; } + rxtx_bufsz = PAGE_ALIGN(rxtx_bufsz); drv_info->rxtx_bufsz = rxtx_bufsz; drv_info->rx_buffer = alloc_pages_exact(rxtx_bufsz, GFP_KERNEL); if (!drv_info->rx_buffer) { ret = -ENOMEM; - goto free_pages; + goto free_drv_info; } drv_info->tx_buffer = alloc_pages_exact(rxtx_bufsz, GFP_KERNEL); @@ -2078,7 +2136,7 @@ static int __init ffa_init(void) ret = ffa_rxtx_map(virt_to_phys(drv_info->tx_buffer), virt_to_phys(drv_info->rx_buffer), - PAGE_ALIGN(rxtx_bufsz) / FFA_PAGE_SIZE); + rxtx_bufsz / FFA_PAGE_SIZE); if (ret) { pr_err("failed to register FFA RxTx buffers\n"); goto free_pages; diff --git a/drivers/firmware/efi/efi-pstore.c b/drivers/firmware/efi/efi-pstore.c index a253b6144945..a5db3534f0a6 100644 --- a/drivers/firmware/efi/efi-pstore.c +++ b/drivers/firmware/efi/efi-pstore.c @@ -60,8 +60,10 @@ static int efi_pstore_open(struct pstore_info *psi) return err; psi->data = kzalloc(record_size, GFP_KERNEL); - if (!psi->data) + if (!psi->data) { + efivar_unlock(); return -ENOMEM; + } return 0; } diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c index d04be38f1750..318d1cc9a066 100644 --- a/drivers/firmware/efi/efi.c +++ b/drivers/firmware/efi/efi.c @@ -402,21 +402,11 @@ static void __init efi_debugfs_init(void) static inline void efi_debugfs_init(void) {} #endif -/* - * We register the efi subsystem with the firmware subsystem and the - * efivars subsystem with the efi subsystem, if the system was booted with - * EFI. - */ -static int __init efisubsys_init(void) +static int __init efipostcore_init(void) { - int error; - if (!efi_enabled(EFI_RUNTIME_SERVICES)) efi.runtime_supported_mask = 0; - if (!efi_enabled(EFI_BOOT)) - return 0; - if (efi.runtime_supported_mask) { /* * Since we process only one efi_runtime_service() at a time, an @@ -428,9 +418,23 @@ static int __init efisubsys_init(void) pr_err("Creating efi_rts_wq failed, EFI runtime services disabled.\n"); clear_bit(EFI_RUNTIME_SERVICES, &efi.flags); efi.runtime_supported_mask = 0; - return 0; } } + return 0; +} +postcore_initcall(efipostcore_init); + +/* + * We register the efi subsystem with the firmware subsystem and the + * efivars subsystem with the efi subsystem, if the system was booted with + * EFI. + */ +static int __init efisubsys_init(void) +{ + int error; + + if (!efi_enabled(EFI_BOOT)) + return 0; if (efi_rt_services_supported(EFI_RT_SUPPORTED_TIME_SERVICES)) platform_device_register_simple("rtc-efi", 0, NULL, 0); diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile index 983a438e35f3..cfedb3025c26 100644 --- a/drivers/firmware/efi/libstub/Makefile +++ b/drivers/firmware/efi/libstub/Makefile @@ -66,7 +66,7 @@ KBUILD_AFLAGS := $(KBUILD_CFLAGS) -D__ASSEMBLY__ lib-y := efi-stub-helper.o gop.o secureboot.o tpm.o \ file.o mem.o random.o randomalloc.o pci.o \ skip_spaces.o lib-cmdline.o lib-ctype.o \ - alignedmem.o relocate.o printk.o vsprintf.o + alignedmem.o printk.o vsprintf.o # include the stub's libfdt dependencies from lib/ when needed libfdt-deps := fdt_rw.c fdt_ro.c fdt_wip.c fdt.c \ diff --git a/drivers/firmware/efi/libstub/efi-stub-helper.c b/drivers/firmware/efi/libstub/efi-stub-helper.c index 7aa2f9ad2935..f27f2e1f0019 100644 --- a/drivers/firmware/efi/libstub/efi-stub-helper.c +++ b/drivers/firmware/efi/libstub/efi-stub-helper.c @@ -79,6 +79,10 @@ efi_status_t efi_parse_options(char const *cmdline) efi_noinitrd = true; } else if (IS_ENABLED(CONFIG_X86_64) && !strcmp(param, "no5lvl")) { efi_no5lvl = true; + } else if (IS_ENABLED(CONFIG_LOONGARCH) && + IS_ENABLED(CONFIG_HIBERNATION) && + !strcmp(param, "resume") && val) { + efi_nokaslr = true; /* LoongArch can't KASLR for hibernation */ } else if (IS_ENABLED(CONFIG_ARCH_HAS_MEM_ENCRYPT) && !strcmp(param, "mem_encrypt") && val) { if (parse_option_str(val, "on")) diff --git a/drivers/firmware/efi/libstub/efistub.h b/drivers/firmware/efi/libstub/efistub.h index 979a21818cc1..fd91fc15ec81 100644 --- a/drivers/firmware/efi/libstub/efistub.h +++ b/drivers/firmware/efi/libstub/efistub.h @@ -1104,13 +1104,6 @@ efi_status_t efi_allocate_pages_aligned(unsigned long size, unsigned long *addr, efi_status_t efi_low_alloc_above(unsigned long size, unsigned long align, unsigned long *addr, unsigned long min); -efi_status_t efi_relocate_kernel(unsigned long *image_addr, - unsigned long image_size, - unsigned long alloc_size, - unsigned long preferred_addr, - unsigned long alignment, - unsigned long min_addr); - efi_status_t efi_parse_options(char const *cmdline); void efi_parse_option_graphics(char *option); diff --git a/drivers/firmware/efi/libstub/loongarch-stub.c b/drivers/firmware/efi/libstub/loongarch-stub.c index 736b6aae323d..c87ac7025107 100644 --- a/drivers/firmware/efi/libstub/loongarch-stub.c +++ b/drivers/firmware/efi/libstub/loongarch-stub.c @@ -14,6 +14,86 @@ extern int kernel_asize; extern int kernel_fsize; extern int kernel_entry; +/** + * efi_relocate_kernel() - copy memory area + * @image_addr: pointer to address of memory area to copy + * @image_size: size of memory area to copy + * @alloc_size: minimum size of memory to allocate, must be greater or + * equal to image_size + * @preferred_addr: preferred target address + * @alignment: minimum alignment of the allocated memory area. It + * should be a power of two. + * @min_addr: minimum target address + * + * Copy a memory area to a newly allocated memory area aligned according + * to @alignment but at least EFI_ALLOC_ALIGN. If the preferred address + * is not available, the allocated address will not be below @min_addr. + * On exit, @image_addr is updated to the target copy address that was used. + * + * This function is used to copy the Linux kernel verbatim. It does not apply + * any relocation changes. + * + * Return: status code + */ +static +efi_status_t efi_relocate_kernel(unsigned long *image_addr, + unsigned long image_size, + unsigned long alloc_size, + unsigned long preferred_addr, + unsigned long alignment, + unsigned long min_addr) +{ + unsigned long cur_image_addr; + unsigned long new_addr = 0; + efi_status_t status; + unsigned long nr_pages; + efi_physical_addr_t efi_addr = preferred_addr; + + if (!image_addr || !image_size || !alloc_size) + return EFI_INVALID_PARAMETER; + if (alloc_size < image_size) + return EFI_INVALID_PARAMETER; + + cur_image_addr = *image_addr; + + /* + * The EFI firmware loader could have placed the kernel image + * anywhere in memory, but the kernel has restrictions on the + * max physical address it can run at. Some architectures + * also have a preferred address, so first try to relocate + * to the preferred address. If that fails, allocate as low + * as possible while respecting the required alignment. + */ + nr_pages = round_up(alloc_size, EFI_ALLOC_ALIGN) / EFI_PAGE_SIZE; + status = efi_bs_call(allocate_pages, EFI_ALLOCATE_ADDRESS, + EFI_LOADER_DATA, nr_pages, &efi_addr); + new_addr = efi_addr; + /* + * If preferred address allocation failed allocate as low as + * possible. + */ + if (status != EFI_SUCCESS) { + status = efi_low_alloc_above(alloc_size, alignment, &new_addr, + min_addr); + } + if (status != EFI_SUCCESS) { + efi_err("Failed to allocate usable memory for kernel.\n"); + return status; + } + + /* + * We know source/dest won't overlap since both memory ranges + * have been allocated by UEFI, so we can safely use memcpy. + */ + memcpy((void *)new_addr, (void *)cur_image_addr, image_size); + efi_cache_sync_image(new_addr, image_size); + + /* Return the new address of the relocated image. */ + *image_addr = new_addr; + + return status; +} + efi_status_t handle_kernel_image(unsigned long *image_addr, unsigned long *image_size, unsigned long *reserve_addr, diff --git a/drivers/firmware/efi/libstub/loongarch.c b/drivers/firmware/efi/libstub/loongarch.c index 9825f5218137..2b0c87dc9908 100644 --- a/drivers/firmware/efi/libstub/loongarch.c +++ b/drivers/firmware/efi/libstub/loongarch.c @@ -18,6 +18,27 @@ efi_status_t check_platform_features(void) return EFI_SUCCESS; } +void efi_cache_sync_image(unsigned long image_base, unsigned long alloc_size) +{ + asm volatile ("ibar 0" ::: "memory"); +} + +unsigned long efi_get_kimg_kaslr_address(void) +{ + unsigned int random_offset = 0; + +#ifdef CONFIG_RANDOMIZE_BASE + if (!efi_nokaslr) { + efi_get_random_bytes(sizeof(random_offset), (u8 *)&random_offset); + random_offset ^= (random_get_entropy() << 16); + random_offset &= (CONFIG_RANDOMIZE_BASE_MAX_OFFSET - 1); + random_offset = ALIGN(random_offset + SZ_64K, SZ_64K); + } +#endif + + return PHYSADDR(VMLINUX_LOAD_ADDRESS) + random_offset; +} + struct exit_boot_struct { efi_memory_desc_t *runtime_map; int runtime_entry_count; diff --git a/drivers/firmware/efi/libstub/mem.c b/drivers/firmware/efi/libstub/mem.c index 9c82259eea81..59f3f83de50c 100644 --- a/drivers/firmware/efi/libstub/mem.c +++ b/drivers/firmware/efi/libstub/mem.c @@ -124,3 +124,85 @@ void efi_free(unsigned long size, unsigned long addr) nr_pages = round_up(size, EFI_ALLOC_ALIGN) / EFI_PAGE_SIZE; efi_bs_call(free_pages, addr, nr_pages); } + +/** + * efi_low_alloc_above() - allocate pages at or above given address + * @size: size of the memory area to allocate + * @align: minimum alignment of the allocated memory area. It should + * a power of two. + * @addr: on exit the address of the allocated memory + * @min: minimum address to used for the memory allocation + * + * Allocate at the lowest possible address that is not below @min as + * EFI_LOADER_DATA. The allocated pages are aligned according to @align but at + * least EFI_ALLOC_ALIGN. The first allocated page will not below the address + * given by @min. + * + * Return: status code + */ +efi_status_t efi_low_alloc_above(unsigned long size, unsigned long align, + unsigned long *addr, unsigned long min) +{ + struct efi_boot_memmap *map __free(efi_pool) = NULL; + efi_status_t status; + unsigned long nr_pages; + int i; + + status = efi_get_memory_map(&map, false); + if (status != EFI_SUCCESS) + return status; + + /* + * Enforce minimum alignment that EFI or Linux requires when + * requesting a specific address. We are doing page-based (or + * larger) allocations, and both the address and size must meet + * alignment constraints. + */ + if (align < EFI_ALLOC_ALIGN) + align = EFI_ALLOC_ALIGN; + + size = round_up(size, EFI_ALLOC_ALIGN); + nr_pages = size / EFI_PAGE_SIZE; + for (i = 0; i < map->map_size / map->desc_size; i++) { + efi_memory_desc_t *desc; + unsigned long m = (unsigned long)map->map; + u64 start, end; + + desc = efi_memdesc_ptr(m, map->desc_size, i); + + if (desc->type != EFI_CONVENTIONAL_MEMORY) + continue; + + if (desc->attribute & EFI_MEMORY_HOT_PLUGGABLE) + continue; + + if (efi_soft_reserve_enabled() && + (desc->attribute & EFI_MEMORY_SP)) + continue; + + if (desc->num_pages < nr_pages) + continue; + + start = desc->phys_addr; + end = start + desc->num_pages * EFI_PAGE_SIZE; + + if (start < min) + start = min; + + start = round_up(start, align); + if ((start + size) > end) + continue; + + status = efi_bs_call(allocate_pages, EFI_ALLOCATE_ADDRESS, + EFI_LOADER_DATA, nr_pages, &start); + if (status == EFI_SUCCESS) { + *addr = start; + break; + } + } + + if (i == map->map_size / map->desc_size) + return EFI_NOT_FOUND; + + return EFI_SUCCESS; +} diff --git a/drivers/firmware/efi/libstub/relocate.c b/drivers/firmware/efi/libstub/relocate.c deleted file mode 100644 index d4264bfb6dc1..000000000000 --- a/drivers/firmware/efi/libstub/relocate.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include - -#include "efistub.h" - -/** - * efi_low_alloc_above() - allocate pages at or above given address - * @size: size of the memory area to allocate - * @align: minimum alignment of the allocated memory area. It should - * a power of two. - * @addr: on exit the address of the allocated memory - * @min: minimum address to used for the memory allocation - * - * Allocate at the lowest possible address that is not below @min as - * EFI_LOADER_DATA. The allocated pages are aligned according to @align but at - * least EFI_ALLOC_ALIGN. The first allocated page will not below the address - * given by @min. - * - * Return: status code - */ -efi_status_t efi_low_alloc_above(unsigned long size, unsigned long align, - unsigned long *addr, unsigned long min) -{ - struct efi_boot_memmap *map __free(efi_pool) = NULL; - efi_status_t status; - unsigned long nr_pages; - int i; - - status = efi_get_memory_map(&map, false); - if (status != EFI_SUCCESS) - return status; - - /* - * Enforce minimum alignment that EFI or Linux requires when - * requesting a specific address. We are doing page-based (or - * larger) allocations, and both the address and size must meet - * alignment constraints. - */ - if (align < EFI_ALLOC_ALIGN) - align = EFI_ALLOC_ALIGN; - - size = round_up(size, EFI_ALLOC_ALIGN); - nr_pages = size / EFI_PAGE_SIZE; - for (i = 0; i < map->map_size / map->desc_size; i++) { - efi_memory_desc_t *desc; - unsigned long m = (unsigned long)map->map; - u64 start, end; - - desc = efi_memdesc_ptr(m, map->desc_size, i); - - if (desc->type != EFI_CONVENTIONAL_MEMORY) - continue; - - if (desc->attribute & EFI_MEMORY_HOT_PLUGGABLE) - continue; - - if (efi_soft_reserve_enabled() && - (desc->attribute & EFI_MEMORY_SP)) - continue; - - if (desc->num_pages < nr_pages) - continue; - - start = desc->phys_addr; - end = start + desc->num_pages * EFI_PAGE_SIZE; - - if (start < min) - start = min; - - start = round_up(start, align); - if ((start + size) > end) - continue; - - status = efi_bs_call(allocate_pages, EFI_ALLOCATE_ADDRESS, - EFI_LOADER_DATA, nr_pages, &start); - if (status == EFI_SUCCESS) { - *addr = start; - break; - } - } - - if (i == map->map_size / map->desc_size) - return EFI_NOT_FOUND; - - return EFI_SUCCESS; -} - -/** - * efi_relocate_kernel() - copy memory area - * @image_addr: pointer to address of memory area to copy - * @image_size: size of memory area to copy - * @alloc_size: minimum size of memory to allocate, must be greater or - * equal to image_size - * @preferred_addr: preferred target address - * @alignment: minimum alignment of the allocated memory area. It - * should be a power of two. - * @min_addr: minimum target address - * - * Copy a memory area to a newly allocated memory area aligned according - * to @alignment but at least EFI_ALLOC_ALIGN. If the preferred address - * is not available, the allocated address will not be below @min_addr. - * On exit, @image_addr is updated to the target copy address that was used. - * - * This function is used to copy the Linux kernel verbatim. It does not apply - * any relocation changes. - * - * Return: status code - */ -efi_status_t efi_relocate_kernel(unsigned long *image_addr, - unsigned long image_size, - unsigned long alloc_size, - unsigned long preferred_addr, - unsigned long alignment, - unsigned long min_addr) -{ - unsigned long cur_image_addr; - unsigned long new_addr = 0; - efi_status_t status; - unsigned long nr_pages; - efi_physical_addr_t efi_addr = preferred_addr; - - if (!image_addr || !image_size || !alloc_size) - return EFI_INVALID_PARAMETER; - if (alloc_size < image_size) - return EFI_INVALID_PARAMETER; - - cur_image_addr = *image_addr; - - /* - * The EFI firmware loader could have placed the kernel image - * anywhere in memory, but the kernel has restrictions on the - * max physical address it can run at. Some architectures - * also have a preferred address, so first try to relocate - * to the preferred address. If that fails, allocate as low - * as possible while respecting the required alignment. - */ - nr_pages = round_up(alloc_size, EFI_ALLOC_ALIGN) / EFI_PAGE_SIZE; - status = efi_bs_call(allocate_pages, EFI_ALLOCATE_ADDRESS, - EFI_LOADER_DATA, nr_pages, &efi_addr); - new_addr = efi_addr; - /* - * If preferred address allocation failed allocate as low as - * possible. - */ - if (status != EFI_SUCCESS) { - status = efi_low_alloc_above(alloc_size, alignment, &new_addr, - min_addr); - } - if (status != EFI_SUCCESS) { - efi_err("Failed to allocate usable memory for kernel.\n"); - return status; - } - - /* - * We know source/dest won't overlap since both memory ranges - * have been allocated by UEFI, so we can safely use memcpy. - */ - memcpy((void *)new_addr, (void *)cur_image_addr, image_size); - - /* Return the new address of the relocated image. */ - *image_addr = new_addr; - - return status; -} diff --git a/drivers/firmware/efi/sysfb_efi.c b/drivers/firmware/efi/sysfb_efi.c index 4c3986ddcd54..685283bb7327 100644 --- a/drivers/firmware/efi/sysfb_efi.c +++ b/drivers/firmware/efi/sysfb_efi.c @@ -311,11 +311,14 @@ static const struct dmi_system_id efifb_dmi_swap_width_height[] __initconst = { .callback = efifb_swap_width_height, }, { - /* Lenovo IdeaPad Duet 3 10IGL5 with 1200x1920 portrait screen */ + /* + * Lenovo IdeaPad Duet 3 10IGL5 and 10IGL5-LTE with + * 1200x1920 portrait screen + */ .matches = { DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), - DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, - "IdeaPad Duet 3 10IGL5"), + /* Non exact match to also match the LTE version */ + DMI_MATCH(DMI_PRODUCT_VERSION, "IdeaPad Duet 3 10IGL5"), }, .callback = efifb_swap_width_height, }, diff --git a/drivers/firmware/psci/psci.c b/drivers/firmware/psci/psci.c index 38ca190d4a22..e73bae6cb23a 100644 --- a/drivers/firmware/psci/psci.c +++ b/drivers/firmware/psci/psci.c @@ -539,12 +539,22 @@ static int psci_system_suspend(unsigned long unused) static int psci_system_suspend_enter(suspend_state_t state) { + pm_set_resume_via_firmware(); + return cpu_suspend(0, psci_system_suspend); } +static int psci_system_suspend_begin(suspend_state_t state) +{ + pm_set_suspend_via_firmware(); + + return 0; +} + static const struct platform_suspend_ops psci_suspend_ops = { .valid = suspend_valid_only_mem, .enter = psci_system_suspend_enter, + .begin = psci_system_suspend_begin, }; static void __init psci_init_system_reset2(void) diff --git a/drivers/fwctl/pds/main.c b/drivers/fwctl/pds/main.c index 08872ee8422f..68fe254dd10a 100644 --- a/drivers/fwctl/pds/main.c +++ b/drivers/fwctl/pds/main.c @@ -362,6 +362,9 @@ static void *pdsfc_fw_rpc(struct fwctl_uctx *uctx, enum fwctl_rpc_scope scope, void *out = NULL; int err; + if (in_len < sizeof(*rpc)) + return ERR_PTR(-EINVAL); + err = pdsfc_validate_rpc(pdsfc, rpc, scope); if (err) return ERR_PTR(err); diff --git a/drivers/gpio/gpio-aggregator.c b/drivers/gpio/gpio-aggregator.c index 5915209e1e21..bc6699a821ee 100644 --- a/drivers/gpio/gpio-aggregator.c +++ b/drivers/gpio/gpio-aggregator.c @@ -968,9 +968,12 @@ static int gpio_aggregator_activate(struct gpio_aggregator *aggr) } wait_for_device_probe(); - if (!device_is_bound(&pdev->dev)) { - ret = -ENXIO; - goto err_unregister_pdev; + + scoped_guard(device, &pdev->dev) { + if (!device_is_bound(&pdev->dev)) { + ret = -ENXIO; + goto err_unregister_pdev; + } } aggr->pdev = pdev; @@ -979,8 +982,8 @@ static int gpio_aggregator_activate(struct gpio_aggregator *aggr) err_unregister_pdev: platform_device_unregister(pdev); err_remove_lookup_table: - kfree(aggr->lookups->dev_id); gpiod_remove_lookup_table(aggr->lookups); + kfree(aggr->lookups->dev_id); err_remove_swnode: fwnode_remove_software_node(swnode); err_remove_lookups: @@ -991,11 +994,15 @@ static int gpio_aggregator_activate(struct gpio_aggregator *aggr) static void gpio_aggregator_deactivate(struct gpio_aggregator *aggr) { + struct fwnode_handle *swnode; + + swnode = dev_fwnode(&aggr->pdev->dev); platform_device_unregister(aggr->pdev); aggr->pdev = NULL; gpiod_remove_lookup_table(aggr->lookups); kfree(aggr->lookups->dev_id); kfree(aggr->lookups); + fwnode_remove_software_node(swnode); } static void gpio_aggregator_lockup_configfs(struct gpio_aggregator *aggr, diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 52e96cc5f67b..b9c905a0ffa9 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -1411,7 +1411,7 @@ static int pca953x_resume(struct device *dev) ret = regulator_enable(chip->regulator); if (ret) { dev_err(dev, "Failed to enable regulator: %d\n", ret); - return 0; + return ret; } } diff --git a/drivers/gpio/gpio-sim.c b/drivers/gpio/gpio-sim.c index e19701c2ed67..0da2c5a45843 100644 --- a/drivers/gpio/gpio-sim.c +++ b/drivers/gpio/gpio-sim.c @@ -901,7 +901,7 @@ static int gpio_sim_device_activate(struct gpio_sim_device *dev) struct platform_device *pdev; struct fwnode_handle *swnode; struct gpio_sim_bank *bank; - int ret; + int ret = 0; lockdep_assert_held(&dev->lock); @@ -945,9 +945,12 @@ static int gpio_sim_device_activate(struct gpio_sim_device *dev) } wait_for_device_probe(); - if (!device_is_bound(&pdev->dev)) { - ret = -ENXIO; - goto err_unregister_pdev; + + scoped_guard(device, &pdev->dev) { + if (!device_is_bound(&pdev->dev)) { + ret = -ENXIO; + goto err_unregister_pdev; + } } dev->pdev = pdev; diff --git a/drivers/gpio/gpio-virtuser.c b/drivers/gpio/gpio-virtuser.c index fe0eac920ced..128520d340d4 100644 --- a/drivers/gpio/gpio-virtuser.c +++ b/drivers/gpio/gpio-virtuser.c @@ -1477,9 +1477,12 @@ gpio_virtuser_device_activate(struct gpio_virtuser_device *dev) } wait_for_device_probe(); - if (!device_is_bound(&pdev->dev)) { - ret = -ENXIO; - goto err_unregister_pdev; + + scoped_guard(device, &pdev->dev) { + if (!device_is_bound(&pdev->dev)) { + ret = -ENXIO; + goto err_unregister_pdev; + } } dev->pdev = pdev; diff --git a/drivers/gpio/gpiolib-cdev.c b/drivers/gpio/gpiolib-cdev.c index f36b7c06996d..82f27db0b230 100644 --- a/drivers/gpio/gpiolib-cdev.c +++ b/drivers/gpio/gpiolib-cdev.c @@ -1184,6 +1184,7 @@ static int gpio_v2_line_flags_validate(u64 flags) static int gpio_v2_line_config_validate(struct gpio_v2_line_config *lc, unsigned int num_lines) { + size_t unused_attrs; unsigned int i; u64 flags; int ret; @@ -1191,9 +1192,21 @@ static int gpio_v2_line_config_validate(struct gpio_v2_line_config *lc, if (lc->num_attrs > GPIO_V2_LINE_NUM_ATTRS_MAX) return -EINVAL; + unused_attrs = GPIO_V2_LINE_NUM_ATTRS_MAX - lc->num_attrs; + if (!mem_is_zero(lc->padding, sizeof(lc->padding))) return -EINVAL; + for (i = 0; i < lc->num_attrs; i++) { + if (lc->attrs[i].attr.padding != 0) + return -EINVAL; + } + + if (unused_attrs) { + if (!mem_is_zero(&lc->attrs[lc->num_attrs], unused_attrs * sizeof(*lc->attrs))) + return -EINVAL; + } + for (i = 0; i < num_lines; i++) { flags = gpio_v2_line_config_flags(lc, i); ret = gpio_v2_line_flags_validate(flags); diff --git a/drivers/gpu/buddy.c b/drivers/gpu/buddy.c index 52686672e99f..eb1457376307 100644 --- a/drivers/gpu/buddy.c +++ b/drivers/gpu/buddy.c @@ -437,6 +437,9 @@ int gpu_buddy_init(struct gpu_buddy *mm, u64 size, u64 chunk_size) root_count++; } while (size); +#ifdef CONFIG_LOCKDEP + mm->lock_dep_map = NULL; +#endif return 0; out_free_roots: @@ -538,6 +541,7 @@ void gpu_buddy_reset_clear(struct gpu_buddy *mm, bool is_clear) unsigned int order; int i; + gpu_buddy_driver_lock_held(mm); size = mm->size; for (i = 0; i < mm->n_roots; ++i) { order = ilog2(size) - ilog2(mm->chunk_size); @@ -580,6 +584,7 @@ EXPORT_SYMBOL(gpu_buddy_reset_clear); void gpu_buddy_free_block(struct gpu_buddy *mm, struct gpu_buddy_block *block) { + gpu_buddy_driver_lock_held(mm); BUG_ON(!gpu_buddy_block_is_allocated(block)); mm->avail += gpu_buddy_block_size(mm, block); if (gpu_buddy_block_is_clear(block)) @@ -633,6 +638,7 @@ void gpu_buddy_free_list(struct gpu_buddy *mm, { bool mark_clear = flags & GPU_BUDDY_CLEARED; + gpu_buddy_driver_lock_held(mm); __gpu_buddy_free_list(mm, objects, mark_clear, !mark_clear); } EXPORT_SYMBOL(gpu_buddy_free_list); @@ -1172,6 +1178,8 @@ int gpu_buddy_block_trim(struct gpu_buddy *mm, u64 new_start; int err; + gpu_buddy_driver_lock_held(mm); + if (!list_is_singular(blocks)) return -EINVAL; @@ -1287,6 +1295,8 @@ int gpu_buddy_alloc_blocks(struct gpu_buddy *mm, unsigned long pages; int err; + gpu_buddy_driver_lock_held(mm); + if (size < mm->chunk_size) return -EINVAL; @@ -1475,6 +1485,7 @@ void gpu_buddy_print(struct gpu_buddy *mm) { int order; + gpu_buddy_driver_lock_held(mm); pr_info("chunk_size: %lluKiB, total: %lluMiB, free: %lluMiB, clear_free: %lluMiB\n", mm->chunk_size >> 10, mm->size >> 20, mm->avail >> 20, mm->clear_avail >> 20); diff --git a/drivers/gpu/drm/adp/adp_drv.c b/drivers/gpu/drm/adp/adp_drv.c index 4554cf75565e..ce9dd6222634 100644 --- a/drivers/gpu/drm/adp/adp_drv.c +++ b/drivers/gpu/drm/adp/adp_drv.c @@ -129,7 +129,7 @@ struct adp_drv_private { #define crtc_to_adp(x) container_of(x, struct adp_drv_private, crtc) static int adp_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state; struct drm_crtc_state *crtc_state; @@ -151,7 +151,7 @@ static int adp_plane_atomic_check(struct drm_plane *plane, } static void adp_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adp_drv_private *adp; struct drm_rect src_rect; @@ -193,7 +193,7 @@ static void adp_plane_atomic_update(struct drm_plane *plane, } static void adp_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adp_drv_private *adp = to_adp(plane->dev); @@ -279,7 +279,7 @@ static void adp_crtc_disable_vblank(struct drm_crtc *crtc) } static void adp_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adp_drv_private *adp = crtc_to_adp(crtc); @@ -292,7 +292,7 @@ static void adp_crtc_atomic_enable(struct drm_crtc *crtc, } static void adp_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adp_drv_private *adp = crtc_to_adp(crtc); struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -308,7 +308,7 @@ static void adp_crtc_atomic_disable(struct drm_crtc *crtc, } static void adp_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { u32 frame_num = 1; unsigned long flags; @@ -444,8 +444,6 @@ static int adp_setup_mode_config(struct adp_drv_private *adp) if (IS_ERR(adp->connector)) return PTR_ERR(adp->connector); - drm_connector_attach_encoder(adp->connector, adp->encoder); - ret = drm_vblank_init(drm, drm->mode_config.num_crtc); if (ret < 0) { drm_err(drm, "failed to initialize vblank"); diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 7fb0b93bc1ca..12e4a41bf1f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -3,7 +3,6 @@ config DRM_AMDGPU tristate "AMD GPU" depends on DRM && PCI - depends on !UML select FW_LOADER select DRM_CLIENT select DRM_CLIENT_SELECTION diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index db66c6372199..ee3574797bc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -90,7 +90,7 @@ amdgpu-y += \ nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \ sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \ nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o \ - cyan_skillfish_reg_init.o soc_v1_0.o lsdma_v7_1.o + cyan_skillfish_reg_init.o soc_v1_0.o lsdma_v7_1.o nbio_v6_3_2.o # add DF block amdgpu-y += \ @@ -234,7 +234,8 @@ amdgpu-y += \ # add VPE block amdgpu-y += \ amdgpu_vpe.o \ - vpe_v6_1.o + vpe_v6_1.o \ + vpe_v2_0.o # add UMSCH block amdgpu-y += \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 8bc591deb546..5d7bfa59424a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -267,6 +267,7 @@ extern int amdgpu_rebar; extern int amdgpu_wbrf; extern int amdgpu_user_queue; +extern int amdgpu_ptl; extern uint amdgpu_hdmi_hpd_debounce_delay_ms; @@ -464,7 +465,7 @@ int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ /** - * amdgpu_wb - This struct is used for small GPU memory allocation. + * struct amdgpu_wb - This struct is used for small GPU memory allocation. * * This struct is used to allocate a small amount of GPU memory that can be * used to shadow certain states into the memory. This is especially useful for @@ -538,44 +539,6 @@ struct amdgpu_allowed_register_entry { bool grbm_indexed; }; -/** - * enum amd_reset_method - Methods for resetting AMD GPU devices - * - * @AMD_RESET_METHOD_NONE: The device will not be reset. - * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. - * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the - * any device. - * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) - * individually. Suitable only for some discrete GPU, not - * available for all ASICs. - * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs - * are reset depends on the ASIC. Notably doesn't reset IPs - * shared with the CPU on APUs or the memory controllers (so - * VRAM is not lost). Not available on all ASICs. - * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs - * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card - * but without powering off the PCI bus. Suitable only for - * discrete GPUs. - * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset - * and does a secondary bus reset or FLR, depending on what the - * underlying hardware supports. - * - * Methods available for AMD GPU driver for resetting the device. Not all - * methods are suitable for every device. User can override the method using - * module parameter `reset_method`. - */ -enum amd_reset_method { - AMD_RESET_METHOD_NONE = -1, - AMD_RESET_METHOD_LEGACY = 0, - AMD_RESET_METHOD_MODE0, - AMD_RESET_METHOD_MODE1, - AMD_RESET_METHOD_MODE2, - AMD_RESET_METHOD_LINK, - AMD_RESET_METHOD_BACO, - AMD_RESET_METHOD_PCI, - AMD_RESET_METHOD_ON_INIT, -}; - struct amdgpu_video_codec_info { u32 codec_type; u32 max_width; @@ -1111,6 +1074,7 @@ struct amdgpu_device { long psp_timeout; uint64_t unique_id; + uint8_t unitid; uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; /* enable runtime pm on the device */ @@ -1190,7 +1154,6 @@ struct amdgpu_device { bool apu_prefer_gtt; bool userq_halt_for_enforce_isolation; - struct work_struct userq_reset_work; struct amdgpu_uid *uid_info; struct amdgpu_uma_carveout_info uma_info; @@ -1373,6 +1336,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) +#include "amdgpu_reset.h" + /* * ASICs macro. */ @@ -1462,6 +1427,8 @@ ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, const struct amdgpu_vm_pte_funcs *vm_pte_funcs); +void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, + const struct amdgpu_buffer_funcs *buffer_funcs); /* atpx handler */ #if defined(CONFIG_VGA_SWITCHEROO) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 62807b65f2af..4c732e0f776e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -228,7 +228,6 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block) u64 acp_base; u32 val = 0; u32 count = 0; - struct i2s_platform_data *i2s_pdata = NULL; struct amdgpu_device *adev = ip_block->adev; @@ -272,18 +271,18 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block) goto failure; } - i2s_pdata = kzalloc_objs(struct i2s_platform_data, 1); - if (!i2s_pdata) { + adev->acp.i2s_pdata = kzalloc_objs(struct i2s_platform_data, 1); + if (!adev->acp.i2s_pdata) { r = -ENOMEM; goto failure; } - i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | - DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; - i2s_pdata[0].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; - i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; - i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; - i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; + adev->acp.i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | + DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; + adev->acp.i2s_pdata[0].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; + adev->acp.i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; + adev->acp.i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; + adev->acp.i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; adev->acp.acp_res[0].name = "acp2x_dma"; adev->acp.acp_res[0].flags = IORESOURCE_MEM; @@ -311,7 +310,7 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block) adev->acp.acp_cell[1].id = 1; adev->acp.acp_cell[1].num_resources = 1; adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; - adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; + adev->acp.acp_cell[1].platform_data = &adev->acp.i2s_pdata[0]; adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); r = mfd_add_devices(adev->acp.parent, 0, adev->acp.acp_cell, 2, NULL, 0, NULL); if (r) @@ -336,53 +335,53 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block) goto failure; } - i2s_pdata = kzalloc_objs(struct i2s_platform_data, 3); - if (!i2s_pdata) { + adev->acp.i2s_pdata = kzalloc_objs(struct i2s_platform_data, 3); + if (!adev->acp.i2s_pdata) { r = -ENOMEM; goto failure; } switch (adev->asic_type) { case CHIP_STONEY: - i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | - DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; + adev->acp.i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | + DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; break; default: - i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; + adev->acp.i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; } - i2s_pdata[0].cap = DWC_I2S_PLAY; - i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; - i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; - i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; + adev->acp.i2s_pdata[0].cap = DWC_I2S_PLAY; + adev->acp.i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; + adev->acp.i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; + adev->acp.i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; switch (adev->asic_type) { case CHIP_STONEY: - i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | - DW_I2S_QUIRK_COMP_PARAM1 | - DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; + adev->acp.i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | + DW_I2S_QUIRK_COMP_PARAM1 | + DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; break; default: - i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | - DW_I2S_QUIRK_COMP_PARAM1; + adev->acp.i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | + DW_I2S_QUIRK_COMP_PARAM1; } - i2s_pdata[1].cap = DWC_I2S_RECORD; - i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; - i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; - i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; + adev->acp.i2s_pdata[1].cap = DWC_I2S_RECORD; + adev->acp.i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; + adev->acp.i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; + adev->acp.i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; - i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; + adev->acp.i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; switch (adev->asic_type) { case CHIP_STONEY: - i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; + adev->acp.i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; break; default: break; } - i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; - i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; - i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET; - i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET; + adev->acp.i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; + adev->acp.i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; + adev->acp.i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET; + adev->acp.i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET; adev->acp.acp_res[0].name = "acp2x_dma"; adev->acp.acp_res[0].flags = IORESOURCE_MEM; @@ -420,21 +419,21 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block) adev->acp.acp_cell[1].id = 1; adev->acp.acp_cell[1].num_resources = 1; adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; - adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; + adev->acp.acp_cell[1].platform_data = &adev->acp.i2s_pdata[0]; adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); adev->acp.acp_cell[2].name = "designware-i2s"; adev->acp.acp_cell[2].id = 2; adev->acp.acp_cell[2].num_resources = 1; adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; - adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; + adev->acp.acp_cell[2].platform_data = &adev->acp.i2s_pdata[1]; adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); adev->acp.acp_cell[3].name = "designware-i2s"; adev->acp.acp_cell[3].id = 3; adev->acp.acp_cell[3].num_resources = 1; adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3]; - adev->acp.acp_cell[3].platform_data = &i2s_pdata[2]; + adev->acp.acp_cell[3].platform_data = &adev->acp.i2s_pdata[2]; adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data); r = mfd_add_devices(adev->acp.parent, 0, adev->acp.acp_cell, ACP_DEVS, NULL, 0, NULL); @@ -491,7 +490,7 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block) return 0; failure: - kfree(i2s_pdata); + kfree(adev->acp.i2s_pdata); kfree(adev->acp.acp_res); kfree(adev->acp.acp_cell); kfree(adev->acp.acp_genpd); @@ -556,6 +555,7 @@ static int acp_hw_fini(struct amdgpu_ip_block *ip_block) acp_genpd_remove_device); mfd_remove_devices(adev->acp.parent); + kfree(adev->acp.i2s_pdata); kfree(adev->acp.acp_res); kfree(adev->acp.acp_genpd); kfree(adev->acp.acp_cell); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h index a288ce25c176..13b48c582314 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h @@ -35,6 +35,7 @@ struct amdgpu_acp { struct mfd_cell *acp_cell; struct resource *acp_res; struct acp_pm_domain *acp_genpd; + struct i2s_platform_data *i2s_pdata; }; extern const struct amdgpu_ip_block_version acp_ip_block; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index d9e283f3b57d..9783a3cefb04 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -36,6 +36,9 @@ #include "amdgpu_ras.h" #include "amdgpu_umc.h" #include "amdgpu_reset.h" +#if IS_ENABLED(CONFIG_HSA_AMD) +#include "kfd_priv.h" +#endif /* Total memory size in system memory and all GPU VRAM. Used to * estimate worst case amount of memory to reserve for page tables @@ -320,6 +323,28 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) (void)amdgpu_reset_domain_schedule(adev->reset_domain, &adev->kfd.reset_work); } +void amdgpu_amdkfd_clear_kfd_mapping(struct amdgpu_device *adev) +{ +#if IS_ENABLED(CONFIG_HSA_AMD) + struct kfd_dev *kfd = adev->kfd.dev; + unsigned int i; + + if (!kfd) + return; + + for (i = 0; i < kfd->num_nodes; i++) { + struct kfd_node *node = kfd->nodes[i]; + + kfd_dev_unmap_mapping_range(KFD_MMAP_TYPE_DOORBELL | + KFD_MMAP_GPU_ID(node->id), + kfd_doorbell_process_slice(kfd)); + kfd_dev_unmap_mapping_range(KFD_MMAP_TYPE_MMIO | + KFD_MMAP_GPU_ID(node->id), + PAGE_SIZE); + } +#endif +} + int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, u32 domain, void **mem_obj, uint64_t *gpu_addr, void **cpu_ptr, bool cp_mqd_gfx9) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index cdbab7f8cee8..5333e052d56d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -38,6 +38,8 @@ #include "amdgpu_vm.h" #include "amdgpu_xcp.h" #include "kfd_topology.h" +#include "amdgpu_ptl.h" + extern uint64_t amdgpu_amdkfd_total_mem_size; enum TLB_FLUSH_TYPE { @@ -358,6 +360,7 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, uint64_t size, u32 alloc_flag, int8_t xcp_id); void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, uint64_t size, u32 alloc_flag, int8_t xcp_id); +void amdgpu_amdkfd_clear_kfd_mapping(struct amdgpu_device *adev); u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id); @@ -434,8 +437,10 @@ int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd); void kgd2kfd_unlock_kfd(struct kfd_dev *kfd); int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id); int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd); +int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev); int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id); int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd); +int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev); bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, bool retry_fault); @@ -532,6 +537,11 @@ static inline int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) return 0; } +static inline int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev) +{ + return 0; +} + static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) { return 0; @@ -542,6 +552,11 @@ static inline int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) return 0; } +static inline int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev) +{ + return 0; +} + static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) { return false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index f35947be3763..6ed399163547 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -520,6 +520,16 @@ static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return is_active ? doorbell_off >> 2 : 0; } +static uint32_t kgd_v9_4_3_ptl_ctrl(struct amdgpu_device *adev, + uint32_t cmd, + uint32_t *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2) +{ + return amdgpu_ptl_perf_monitor_ctrl(adev, cmd, + ptl_state, fmt1, fmt2); +} + const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_4_3_set_pasid_vmid_mapping, @@ -555,5 +565,6 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell, + .ptl_ctrl = kgd_v9_4_3_ptl_ctrl }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 3698dd0330ff..acd22bff1882 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -36,6 +36,21 @@ #include "atombios_encoders.h" #include "bif/bif_4_1_d.h" +/* VBIOS-reported table size is unchecked against the image; cap iterations and + * adev->i2c_bus[] indexing to AMDGPU_MAX_I2C_BUS. + */ +static int amdgpu_atombios_gpio_i2c_num_entries(uint16_t size) +{ + u32 bytes; + + if (size < sizeof(ATOM_COMMON_TABLE_HEADER)) + return 0; + + bytes = size - sizeof(ATOM_COMMON_TABLE_HEADER); + return (int)min_t(u32, bytes / sizeof(ATOM_GPIO_I2C_ASSIGMENT), + AMDGPU_MAX_I2C_BUS); +} + static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) { struct amdgpu_i2c_bus_rec i2c; @@ -96,8 +111,7 @@ struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device * if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); - num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / - sizeof(ATOM_GPIO_I2C_ASSIGMENT); + num_indices = amdgpu_atombios_gpio_i2c_num_entries(size); gpio = &i2c_info->asGPIO_Info[0]; for (i = 0; i < num_indices; i++) { @@ -127,8 +141,7 @@ void amdgpu_atombios_i2c_init(struct amdgpu_device *adev) if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); - num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / - sizeof(ATOM_GPIO_I2C_ASSIGMENT); + num_indices = amdgpu_atombios_gpio_i2c_num_entries(size); gpio = &i2c_info->asGPIO_Info[0]; for (i = 0; i < num_indices; i++) { @@ -158,8 +171,7 @@ void amdgpu_atombios_oem_i2c_init(struct amdgpu_device *adev, u8 i2c_id) if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); - num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / - sizeof(ATOM_GPIO_I2C_ASSIGMENT); + num_indices = amdgpu_atombios_gpio_i2c_num_entries(size); gpio = &i2c_info->asGPIO_Info[0]; for (i = 0; i < num_indices; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 35d04e69aec0..aa039e148a5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -33,6 +33,7 @@ #include #include #include +#include /* * BIOS. */ @@ -467,7 +468,8 @@ static bool amdgpu_prefer_rom_resource(struct amdgpu_device *adev) { struct resource *res = &adev->pdev->resource[PCI_ROM_RESOURCE]; - return (res->flags & IORESOURCE_ROM_SHADOW); + return (res->flags & IORESOURCE_ROM_SHADOW) || + adev->pdev == vga_default_device(); } static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c index 4e6e390854e6..d5e59c24d907 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c @@ -153,7 +153,7 @@ int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev, FATAL_SEC_OFFSET(hdr->sec_cnt, idx)); amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, false, - CPER_SEV_FATAL, CRASHDUMP, FATAL_SEC_LEN, + CPER_SEV_FATAL_UNCORRECTED, CRASHDUMP, FATAL_SEC_LEN, FATAL_SEC_OFFSET(hdr->sec_cnt, idx)); section->body.reg_ctx_type = CPER_CTX_TYPE_CRASH; @@ -215,7 +215,7 @@ int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); amdgpu_cper_entry_fill_section_desc(adev, section_desc, true, false, - CPER_SEV_FATAL, RUNTIME, NONSTD_SEC_LEN, + CPER_SEV_FATAL_UNCORRECTED, RUNTIME, NONSTD_SEC_LEN, NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); section->hdr.valid_bits.err_info_cnt = 1; @@ -312,7 +312,7 @@ int amdgpu_cper_generate_ue_record(struct amdgpu_device *adev, reg_data.synd_lo = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]); reg_data.synd_hi = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]); - amdgpu_cper_entry_fill_hdr(adev, fatal, AMDGPU_CPER_TYPE_FATAL, CPER_SEV_FATAL); + amdgpu_cper_entry_fill_hdr(adev, fatal, AMDGPU_CPER_TYPE_FATAL, CPER_SEV_FATAL_UNCORRECTED); ret = amdgpu_cper_entry_fill_fatal_section(adev, fatal, 0, reg_data); if (ret) return ret; @@ -337,7 +337,7 @@ int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev) amdgpu_cper_entry_fill_hdr(adev, bp_threshold, AMDGPU_CPER_TYPE_BP_THRESHOLD, - CPER_SEV_FATAL); + CPER_SEV_FATAL_UNCORRECTED); ret = amdgpu_cper_entry_fill_bad_page_threshold_section(adev, bp_threshold, 0); if (ret) return ret; @@ -353,14 +353,14 @@ static enum cper_error_severity amdgpu_aca_err_type_to_cper_sev(struct amdgpu_de { switch (aca_err_type) { case ACA_ERROR_TYPE_UE: - return CPER_SEV_FATAL; + return CPER_SEV_FATAL_UNCORRECTED; case ACA_ERROR_TYPE_CE: return CPER_SEV_NON_FATAL_CORRECTED; case ACA_ERROR_TYPE_DEFERRED: return CPER_SEV_NON_FATAL_UNCORRECTED; default: dev_err(adev->dev, "Unknown ACA error type!\n"); - return CPER_SEV_FATAL; + return CPER_SEV_FATAL_UNCORRECTED; } } @@ -484,7 +484,7 @@ static u32 amdgpu_cper_ring_get_ent_sz(struct amdgpu_ring *ring, u64 pos) void amdgpu_cper_ring_write(struct amdgpu_ring *ring, void *src, int count) { - u64 pos, wptr_old, rptr; + u64 pos, wptr_old, rptr, next_rptr; int rec_cnt_dw = count >> 2; u32 chunk, ent_sz; u8 *s = (u8 *)src; @@ -525,9 +525,19 @@ void amdgpu_cper_ring_write(struct amdgpu_ring *ring, void *src, int count) do { ent_sz = amdgpu_cper_ring_get_ent_sz(ring, pos); + next_rptr = rptr; + if (ent_sz >= sizeof(u32)) + next_rptr = (rptr + (ent_sz >> 2)) & ring->ptr_mask; - rptr += (ent_sz >> 2); - rptr &= ring->ptr_mask; + if (next_rptr == rptr) { + /* Corrupt entry size, reset the ring to avoid an infinite loop. */ + rptr = ring->wptr; + *ring->rptr_cpu_addr = rptr; + ring->count_dw = (ring->ring_size - 4) >> 2; + goto out_unlock; + } + + rptr = next_rptr; *ring->rptr_cpu_addr = rptr; pos = rptr; @@ -536,6 +546,8 @@ void amdgpu_cper_ring_write(struct amdgpu_ring *ring, void *src, int count) if (ring->count_dw >= rec_cnt_dw) ring->count_dw -= rec_cnt_dw; + +out_unlock: mutex_unlock(&ring->adev->cper.ring_lock); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index b24d5d21be5f..32af8cce3df8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1100,7 +1100,8 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) if (p->gang_size > 1 && !adev->vm_manager.concurrent_flush) { for (i = 0; i < p->gang_size; ++i) { struct drm_sched_entity *entity = p->entities[i]; - struct drm_gpu_scheduler *sched = entity->rq->sched; + struct drm_gpu_scheduler *sched = + container_of(entity->rq, typeof(*sched), rq); struct amdgpu_ring *ring = to_amdgpu_ring(sched); if (amdgpu_vmid_uses_reserved(vm, ring->vm_hub)) @@ -1231,7 +1232,8 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) return r; } - sched = p->gang_leader->base.entity->rq->sched; + sched = container_of(p->gang_leader->base.entity->rq, typeof(*sched), + rq); while ((fence = amdgpu_sync_get_fence(&p->sync))) { struct drm_sched_fence *s_fence = to_drm_sched_fence(fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 092fd3309099..389bad724273 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2049,7 +2049,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) /* swap out the old fences */ amdgpu_ib_preempt_fences_swap(ring, fences); - amdgpu_fence_driver_force_completion(ring); + amdgpu_fence_driver_force_completion(ring, NULL); /* resubmit unfinished jobs */ amdgpu_ib_preempt_job_recovery(&ring->sched); @@ -2126,6 +2126,9 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) debugfs_create_x32("amdgpu_smu_debug", 0600, root, &adev->pm.smu_debug_mask); + debugfs_create_x64("unique_id", 0444, root, &adev->unique_id); + debugfs_create_x8("unitid", 0444, root, &adev->unitid); + ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev, &fops_ib_preempt); if (IS_ERR(ent)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 737ef1ef96a5..21a3fb574d53 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2221,7 +2221,6 @@ static int amdgpu_device_init_schedulers(struct amdgpu_device *adev) { struct drm_sched_init_args args = { .ops = &amdgpu_sched_ops, - .num_rqs = DRM_SCHED_PRIORITY_COUNT, .timeout_wq = adev->reset_domain->wq, .dev = adev->dev, }; @@ -2460,7 +2459,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) if (r) goto init_failed; - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_enable_buffer_funcs(adev); /* Don't init kfd if whole hive need to be reset during init */ if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { @@ -2839,8 +2838,12 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) * that checks whether the PSP is running. A solution for those issues * in the APU is to trigger a GPU reset, but this should be done during * the unload phase to avoid adding boot latency and screen flicker. + * GFX V11 has GC block as default off IP. Every time AMDGPU driver sends + * a request to PMFW to unload MP1, PMFW will put GC in reset and power down + * the voltage. Hence, skipping reset for APUs with GFX V11 or later. */ - if ((adev->flags & AMD_IS_APU) && !adev->gmc.is_app_apu) { + if ((adev->flags & AMD_IS_APU) && !adev->gmc.is_app_apu && + amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 0, 0)) { r = amdgpu_asic_reset(adev); if (r) dev_err(adev->dev, "asic reset on %s failed\n", __func__); @@ -3144,7 +3147,7 @@ static int amdgpu_device_ip_suspend(struct amdgpu_device *adev) amdgpu_virt_request_full_gpu(adev, false); } - amdgpu_ttm_set_buffer_funcs_status(adev, false); + amdgpu_ttm_disable_buffer_funcs(adev); r = amdgpu_device_ip_suspend_phase1(adev); if (r) @@ -3359,7 +3362,7 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev) r = amdgpu_device_ip_resume_phase2(adev); - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_enable_buffer_funcs(adev); if (r) return r; @@ -3644,6 +3647,7 @@ static int amdgpu_device_sys_interface_init(struct amdgpu_device *adev) amdgpu_reg_state_sysfs_init(adev); amdgpu_xcp_sysfs_init(adev); amdgpu_uma_sysfs_init(adev); + amdgpu_ptl_sysfs_init(adev); return r; } @@ -3660,6 +3664,7 @@ static void amdgpu_device_sys_interface_fini(struct amdgpu_device *adev) amdgpu_reg_state_sysfs_fini(adev); amdgpu_xcp_sysfs_fini(adev); amdgpu_uma_sysfs_fini(adev); + amdgpu_ptl_sysfs_fini(adev); } /** @@ -3697,7 +3702,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->num_rings = 0; RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub()); adev->mman.buffer_funcs = NULL; - adev->mman.buffer_funcs_ring = NULL; + adev->mman.num_buffer_funcs_scheds = 0; adev->vm_manager.vm_pte_funcs = NULL; adev->vm_manager.vm_pte_num_scheds = 0; adev->gmc.gmc_funcs = NULL; @@ -3728,6 +3733,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->virt.vf_errors.lock); hash_init(adev->mn_hash); mutex_init(&adev->psp.mutex); + mutex_init(&adev->psp.ptl.mutex); mutex_init(&adev->notifier_lock); mutex_init(&adev->pm.stable_pstate_ctx_lock); mutex_init(&adev->benchmark_mutex); @@ -3783,7 +3789,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, } INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); - INIT_WORK(&adev->userq_reset_work, amdgpu_userq_reset_work); amdgpu_coredump_init(adev); @@ -3854,6 +3859,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, * completed before the need for a different level is detected. */ amdgpu_set_init_level(adev, AMDGPU_INIT_LEVEL_DEFAULT); + + amdgpu_device_check_iommu_direct_map(adev); + /* early init functions */ r = amdgpu_device_ip_early_init(adev); if (r) @@ -4111,8 +4119,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (px) vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); - amdgpu_device_check_iommu_direct_map(adev); - adev->pm_nb.notifier_call = amdgpu_device_pm_notifier; r = register_pm_notifier(&adev->pm_nb); if (r) @@ -4210,7 +4216,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); - amdgpu_ttm_set_buffer_funcs_status(adev, false); + amdgpu_ttm_disable_buffer_funcs(adev); /* * device went through surprise hotplug; we need to destroy topology @@ -4477,7 +4483,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) if (r) goto unwind_userq; - amdgpu_ttm_set_buffer_funcs_status(adev, false); + amdgpu_ttm_disable_buffer_funcs(adev); amdgpu_fence_driver_hw_fini(adev); @@ -4491,7 +4497,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) return 0; unwind_evict: - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_enable_buffer_funcs(adev); amdgpu_fence_driver_hw_init(adev); unwind_userq: @@ -5086,6 +5092,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, { int i, r = 0; struct amdgpu_job *job = NULL; + struct dma_fence *fence = NULL; struct amdgpu_device *tmp_adev = reset_context->reset_req_dev; bool need_full_reset = test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); @@ -5098,6 +5105,9 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, amdgpu_fence_driver_isr_toggle(adev, true); + if (job) + fence = &job->hw_fence->base; + /* block all schedulers and reset given job's ring */ for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; @@ -5106,7 +5116,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, continue; /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ - amdgpu_fence_driver_force_completion(ring); + amdgpu_fence_driver_force_completion(ring, fence); } amdgpu_fence_driver_isr_toggle(adev, false); @@ -5225,7 +5235,7 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) if (r) goto out; - amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); + amdgpu_ttm_enable_buffer_funcs(tmp_adev); r = amdgpu_device_ip_resume_phase3(tmp_adev); if (r) @@ -5474,7 +5484,7 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) if (!amdgpu_sriov_vf(adev)) cancel_work(&adev->reset_work); #endif - cancel_work(&adev->userq_reset_work); + amdgpu_userq_mgr_cancel_reset_work(adev); if (adev->kfd.dev) cancel_work(&adev->kfd.reset_work); @@ -5832,6 +5842,12 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, /* We need to lock reset domain only once both for XGMI and single device */ amdgpu_device_recovery_get_reset_lock(adev, &device_list); + /* unmap all the mappings of doorbell and framebuffer to prevent user space from + * accessing them + */ + unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); + amdgpu_amdkfd_clear_kfd_mapping(adev); + amdgpu_device_halt_activities(adev, job, reset_context, &device_list, hive, need_emergency_restart); if (need_emergency_restart) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index fcad7daaa41b..21f6761624c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -64,6 +64,7 @@ #include "nbio_v7_2.h" #include "nbio_v7_7.h" #include "nbif_v6_3_1.h" +#include "nbio_v6_3_2.h" #include "hdp_v5_0.h" #include "hdp_v5_2.h" #include "hdp_v6_0.h" @@ -304,7 +305,7 @@ static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; adev->discovery.size = adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; - if (!adev->discovery.offset || !adev->discovery.size) + if (!adev->discovery.size) return -EINVAL; } else { goto out; @@ -2737,6 +2738,9 @@ static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(6, 1, 3): amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); break; + case IP_VERSION(2, 0, 0): + amdgpu_device_ip_block_add(adev, &vpe_v2_0_ip_block); + break; default: break; } @@ -3090,10 +3094,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): - adev->family = AMDGPU_FAMILY_GC_11_5_0; - break; case IP_VERSION(11, 5, 4): - adev->family = AMDGPU_FAMILY_GC_11_5_4; + adev->family = AMDGPU_FAMILY_GC_11_5_0; break; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): @@ -3195,6 +3197,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) adev->nbio.funcs = &nbif_v6_3_1_funcs; adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; break; + case IP_VERSION(6, 3, 2): + adev->nbio.funcs = &nbio_v6_3_2_funcs; + break; default: break; } @@ -3418,3 +3423,28 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) return 0; } +int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev, + uint16_t *major, uint16_t *minor) +{ + uint8_t *discovery_bin = adev->discovery.bin; + struct table_info *info; + union gc_info *gc_info; + u16 offset; + + if (!discovery_bin) + return -EINVAL; + if (amdgpu_discovery_get_table_info(adev, &info, GC)) + return -EINVAL; + + offset = le16_to_cpu(info->offset); + if (!offset) + return -EINVAL; + + gc_info = (union gc_info *)(discovery_bin + offset); + + if (major) + *major = le16_to_cpu(gc_info->v1.header.version_major); + if (minor) + *minor = le16_to_cpu(gc_info->v1.header.version_minor); + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index 0ff1a7923eed..e0010f6a3eda 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -48,6 +48,8 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, uint32_t *nps_type, struct amdgpu_gmc_memrange *ranges, int *range_cnt, bool refresh); +int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev, + uint16_t *major, uint16_t *minor); void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index e47921e2a9af..1781c0c3d010 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -246,6 +246,7 @@ int amdgpu_umsch_mm_fwlog; int amdgpu_rebar = -1; /* auto */ int amdgpu_user_queue = -1; uint amdgpu_hdmi_hpd_debounce_delay_ms; +int amdgpu_ptl = -1; /* auto */ DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, "DRM_UT_CORE", @@ -1112,6 +1113,18 @@ module_param_named(user_queue, amdgpu_user_queue, int, 0444); MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)"); module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644); +/** + * DOC: ptl (int) + * Enable PTL feature at boot time. Possible values: + * + * - -1 = auto (ASIC specific default) + * - 0 = disable PTL (default) + * - 1 = enable PTL + * - 2 = permanently disable PTL (cannot be re-enabled at runtime) + */ +MODULE_PARM_DESC(ptl, "Enable PTL (-1 = auto, 0 = disable (default), 1 = enable, 2 = permanently disable)"); +module_param_named(ptl, amdgpu_ptl, int, 0444); + /* These devices are not supported by amdgpu. * They are supported by the mach64, r128, radeon drivers */ @@ -2797,12 +2810,11 @@ static int amdgpu_runtime_idle_check_userq(struct device *dev) return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY; } -static int amdgpu_pmops_runtime_suspend(struct device *dev) +static int amdgpu_pmops_runtime_checks(struct device *dev) { - struct pci_dev *pdev = to_pci_dev(dev); - struct drm_device *drm_dev = pci_get_drvdata(pdev); + struct drm_device *drm_dev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(drm_dev); - int ret, i; + int ret; if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { pm_runtime_forbid(dev); @@ -2812,7 +2824,27 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev) ret = amdgpu_runtime_idle_check_display(dev); if (ret) return ret; - ret = amdgpu_runtime_idle_check_userq(dev); + + return amdgpu_runtime_idle_check_userq(dev); +} + +static int amdgpu_pmops_runtime_idle(struct device *dev) +{ + int ret; + + ret = amdgpu_pmops_runtime_checks(dev); + pm_runtime_autosuspend(dev); + return ret; +} + +static int amdgpu_pmops_runtime_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + struct amdgpu_device *adev = drm_to_adev(drm_dev); + int ret, i; + + ret = amdgpu_pmops_runtime_checks(dev); if (ret) return ret; @@ -2924,27 +2956,6 @@ static int amdgpu_pmops_runtime_resume(struct device *dev) return 0; } -static int amdgpu_pmops_runtime_idle(struct device *dev) -{ - struct drm_device *drm_dev = dev_get_drvdata(dev); - struct amdgpu_device *adev = drm_to_adev(drm_dev); - int ret; - - if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { - pm_runtime_forbid(dev); - return -EBUSY; - } - - ret = amdgpu_runtime_idle_check_display(dev); - if (ret) - goto done; - - ret = amdgpu_runtime_idle_check_userq(dev); -done: - pm_runtime_autosuspend(dev); - return ret; -} - static int amdgpu_drm_release(struct inode *inode, struct file *filp) { struct drm_file *file_priv = filp->private_data; @@ -3149,17 +3160,15 @@ static int __init amdgpu_init(void) r = amdgpu_sync_init(); if (r) - goto error_sync; - - r = amdgpu_userq_fence_slab_init(); - if (r) - goto error_fence; + return r; amdgpu_register_atpx_handler(); amdgpu_acpi_detect(); - /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ - amdgpu_amdkfd_init(); + /* Ignore KFD init failures when CONFIG_HSA_AMD is not set. */ + r = amdgpu_amdkfd_init(); + if (r && r != -ENOENT) + goto error_fini_sync; if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); @@ -3170,10 +3179,8 @@ static int __init amdgpu_init(void) /* let modprobe override vga console setting */ return pci_register_driver(&amdgpu_kms_pci_driver); -error_fence: +error_fini_sync: amdgpu_sync_fini(); - -error_sync: return r; } @@ -3184,7 +3191,6 @@ static void __exit amdgpu_exit(void) amdgpu_unregister_atpx_handler(); amdgpu_acpi_release(); amdgpu_sync_fini(); - amdgpu_userq_fence_slab_fini(); mmu_notifier_synchronize(); amdgpu_xcp_drv_release(); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 8048a4c04b47..ea69b1bac7c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -547,7 +547,7 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev) r = -ENODEV; /* no need to trigger GPU reset as we are unloading */ if (r) - amdgpu_fence_driver_force_completion(ring); + amdgpu_fence_driver_force_completion(ring, NULL); if (!drm_dev_is_unplugged(adev_to_drm(adev)) && ring->fence_drv.irq_src && @@ -662,16 +662,34 @@ void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error) * amdgpu_fence_driver_force_completion - force signal latest fence of ring * * @ring: fence of the ring to signal + * @timedout_fence: fence of the timedout job * */ -void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) +void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring, + struct dma_fence *timedout_fence) { - amdgpu_fence_driver_set_error(ring, -ECANCELED); + struct amdgpu_fence_driver *drv = &ring->fence_drv; + unsigned long flags; + + spin_lock_irqsave(&drv->lock, flags); + for (unsigned int i = 0; i <= drv->num_fences_mask; ++i) { + struct dma_fence *fence; + + fence = rcu_dereference_protected(drv->fences[i], + lockdep_is_held(&drv->lock)); + if (fence && !dma_fence_is_signaled_locked(fence)) { + if (fence == timedout_fence) + dma_fence_set_error(fence, -ETIME); + else + dma_fence_set_error(fence, -ECANCELED); + } + } + spin_unlock_irqrestore(&drv->lock, flags); + amdgpu_fence_write(ring, ring->fence_drv.sync_seq); amdgpu_fence_process(ring); } - /* * Kernel queue reset handling * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index bc772ca3dab7..b6f849d51c2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -262,12 +262,19 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) */ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) { + int r; + if (adev->gart.bo != NULL) return 0; - return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo, - NULL, (void *)&adev->gart.ptr); + r = amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo, + NULL, (void *)&adev->gart.ptr); + if (r) + return r; + + memset_io(adev->gart.ptr, adev->gart.gart_pte_flags, adev->gart.table_size); + return 0; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 5376035d32fe..27be5083f2af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -27,10 +27,12 @@ */ #include #include +#include #include #include #include #include +#include #include #include @@ -508,6 +510,9 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (offset_in_page(args->addr | args->size)) return -EINVAL; + if (!access_ok((void __user *)(uintptr_t)args->addr, args->size)) + return -EFAULT; + /* reject unknown flag values */ if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | @@ -821,7 +826,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct drm_syncobj *timeline_syncobj = NULL; struct dma_fence_chain *timeline_chain = NULL; struct drm_exec exec; - uint64_t vm_size; + uint64_t vm_size, tmp; int r = 0; /* Validate virtual address range against reserved regions. */ @@ -845,7 +850,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; vm_size -= AMDGPU_VA_RESERVED_TOP; - if (args->va_address + args->map_size > vm_size) { + if (check_add_overflow(args->va_address, args->map_size, &tmp) || tmp > vm_size) { dev_dbg(dev->dev, "va_address 0x%llx is in top reserved area 0x%llx\n", args->va_address + args->map_size, vm_size); @@ -1217,13 +1222,14 @@ int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, return ret; } -static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, - int width, - int cpp, - bool tiled) +static unsigned int amdgpu_gem_align_pitch(struct amdgpu_device *adev, + unsigned int width, + unsigned int cpp, + bool tiled) { - int aligned = width; - int pitch_mask = 0; + unsigned int aligned = width; + unsigned int pitch_mask = 0; + unsigned int pitch; switch (cpp) { case 1: @@ -1238,9 +1244,12 @@ static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, break; } - aligned += pitch_mask; + if (check_add_overflow(aligned, pitch_mask, &aligned)) + return 0; aligned &= ~pitch_mask; - return aligned * cpp; + if (check_mul_overflow(aligned, cpp, &pitch)) + return 0; + return pitch; } int amdgpu_mode_dumb_create(struct drm_file *file_priv, @@ -1267,8 +1276,12 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, args->pitch = amdgpu_gem_align_pitch(adev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); + if (!args->pitch) + return -EINVAL; args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); + if (!args->size) + return -EINVAL; domain = amdgpu_bo_get_preferred_domain(adev, amdgpu_display_supported_domains(adev, flags)); r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index b8ca876694ff..515cc4a2aeb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2686,3 +2686,54 @@ void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev) #endif } +int amdgpu_gfx_ring_preempt_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; + struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; + int i; + + if (adev->enable_mes) + return -EINVAL; + + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) + return -EINVAL; + + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } + + /* assert preemption condition */ + amdgpu_ring_set_preempt_cond_exec(ring, false); + + /* assert IB preemption, emit the trailing fence */ + kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, + ring->trail_fence_gpu_addr, + ++ring->trail_seq); + amdgpu_ring_commit(kiq_ring); + + spin_unlock_irqrestore(&kiq->ring_lock, flags); + + /* poll the trailing fence */ + for (i = 0; i < adev->usec_timeout; i++) { + if (ring->trail_seq == + le32_to_cpu(*(ring->trail_fence_cpu_addr))) + break; + udelay(1); + } + + /* deassert preemption condition */ + amdgpu_ring_set_preempt_cond_exec(ring, true); + + if (i >= adev->usec_timeout) { + DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); + return -EINVAL; + } + + return 0; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index a0cf0a3b41da..77050f9884f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -664,6 +664,8 @@ void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count); void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev); void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev); +int amdgpu_gfx_ring_preempt_ib(struct amdgpu_ring *ring); + static inline const char *amdgpu_gfx_compute_mode_desc(int mode) { switch (mode) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 285e217fba04..276f9f49d6d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -280,6 +280,15 @@ void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc mc->gart_size >> 20, mc->gart_start, mc->gart_end); } +void amdgpu_gmc_set_gart_size(struct amdgpu_device *adev, u64 default_size) +{ + if (amdgpu_gart_size == -1) + adev->gmc.gart_size = + default_size + adev->pm.smu_prv_buffer_size; + else + adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; +} + /** * amdgpu_gmc_gart_location - try to find GART location * @@ -314,7 +323,10 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, mc->gart_start = max_mc_address - mc->gart_size + 1; break; case AMDGPU_GART_PLACEMENT_LOW: - mc->gart_start = 0; + if (size_bf >= mc->gart_size) + mc->gart_start = 0; + else + mc->gart_start = ALIGN(mc->fb_end, four_gb); break; case AMDGPU_GART_PLACEMENT_BEST_FIT: default: @@ -708,12 +720,14 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t vmhub, uint32_t flush_type) { - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + struct amdgpu_ring *ring; struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; struct dma_fence *fence; struct amdgpu_job *job; int r; + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); + if (!hub->sdma_invalidation_workaround || vmid || !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready || !ring->sched.ready) { @@ -1002,6 +1016,9 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) gc_ver == IP_VERSION(9, 5, 0) || gc_ver >= IP_VERSION(10, 3, 0)); + /* For GFX12.1 B0, set xnack (retry) on as default */ + if (gc_ver == IP_VERSION(12, 1, 0) && (adev->rev_id & 0xf) == 0x1) + noretry_default = false; if (!amdgpu_sriov_xnack_support(adev)) gmc->noretry = 1; else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 6ab4c1e297fc..676e3aaa1f27 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -365,6 +365,8 @@ struct amdgpu_gmc { bool flush_tlb_needs_extra_type_0; bool flush_tlb_needs_extra_type_2; bool flush_pasid_uses_kiq; + + bool override_pte; }; #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) @@ -484,4 +486,6 @@ void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, struct amdgpu_mem_partition_info *mem_ranges); int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor); + +void amdgpu_gmc_set_gart_size(struct amdgpu_device *adev, u64 default_size); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 620fddde4c4d..a5d26b943f6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -199,11 +199,18 @@ int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr *mgr, enum drm_mm_insert_mode mode) { struct amdgpu_device *adev = container_of(mgr, typeof(*adev), mman.gtt_mgr); + u32 alignment = 0; int r; + /* Align to TLB L2 cache entry size to work around "V bit HW bug" */ + if (adev->asic_type == CHIP_TAHITI) { + alignment = 32 * 1024 / AMDGPU_GPU_PAGE_SIZE; + num_pages = ALIGN(num_pages, alignment); + } + spin_lock(&mgr->lock); r = drm_mm_insert_node_in_range(&mgr->mm, mm_node, num_pages, - 0, GART_ENTRY_WITHOUT_BO_COLOR, 0, + alignment, GART_ENTRY_WITHOUT_BO_COLOR, 0, adev->gmc.gart_size >> PAGE_SHIFT, mode); spin_unlock(&mgr->lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index f58b6be7fccc..444437c30088 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -91,6 +91,12 @@ struct amdgpu_ih_funcs { uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr, signed int offset); void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); + /* Decode IH cookie node_id into a human-readable die name string. + * Returns buf, or NULL if this IH version does not support node_id decoding. + */ + const char *(*node_id_to_die_name)(struct amdgpu_device *adev, + unsigned int node_id, + char *buf, size_t size); }; #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h index 9c56be725ff3..eb8537558f5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h @@ -39,7 +39,6 @@ struct amdgpu_imu_funcs { int (*switch_compute_partition)(struct amdgpu_device *adev, int num_xccs_per_xcp, int compute_partition_mode); - void (*init_mcm_addr_lut)(struct amdgpu_device *adev); }; struct imu_rlc_ram_golden { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 07771721af9d..9ecc6387c1eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -388,7 +388,9 @@ static struct dma_fence * amdgpu_job_prepare_job(struct drm_sched_job *sched_job, struct drm_sched_entity *s_entity) { - struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); + struct drm_gpu_scheduler *sched = + container_of(s_entity->rq, typeof(*sched), rq); + struct amdgpu_ring *ring = to_amdgpu_ring(sched); struct amdgpu_job *job = to_amdgpu_job(sched_job); struct dma_fence *fence; int r; @@ -481,25 +483,22 @@ drm_sched_entity_queue_pop(struct drm_sched_entity *entity) void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) { + struct drm_sched_rq *rq = &sched->rq; + struct drm_sched_entity *s_entity; struct drm_sched_job *s_job; - struct drm_sched_entity *s_entity = NULL; - int i; /* Signal all jobs not yet scheduled */ - for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) { - struct drm_sched_rq *rq = sched->sched_rq[i]; - spin_lock(&rq->lock); - list_for_each_entry(s_entity, &rq->entities, list) { - while ((s_job = drm_sched_entity_queue_pop(s_entity))) { - struct drm_sched_fence *s_fence = s_job->s_fence; + spin_lock(&rq->lock); + list_for_each_entry(s_entity, &rq->entities, list) { + while ((s_job = drm_sched_entity_queue_pop(s_entity))) { + struct drm_sched_fence *s_fence = s_job->s_fence; - dma_fence_signal(&s_fence->scheduled); - dma_fence_set_error(&s_fence->finished, -EHWPOISON); - dma_fence_signal(&s_fence->finished); - } + dma_fence_signal(&s_fence->scheduled); + dma_fence_set_error(&s_fence->finished, -EHWPOISON); + dma_fence_signal(&s_fence->finished); } - spin_unlock(&rq->lock); } + spin_unlock(&rq->lock); /* Signal all jobs already scheduled to HW */ list_for_each_entry(s_job, &sched->pending_list, list) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h index 56a88e14a044..e70a1117b812 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h @@ -107,7 +107,10 @@ struct amdgpu_job { static inline struct amdgpu_ring *amdgpu_job_ring(struct amdgpu_job *job) { - return to_amdgpu_ring(job->base.entity->rq->sched); + struct drm_gpu_scheduler *sched = + container_of(job->base.entity->rq, typeof(*sched), rq); + + return to_amdgpu_ring(sched); } int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 06efce38f323..71272f40feef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -873,68 +873,59 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) ? -EFAULT : 0; } case AMDGPU_INFO_READ_MMR_REG: { - int ret = 0; - unsigned int n, alloc_size; - uint32_t *regs; unsigned int se_num = (info->read_mmr_reg.instance >> AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & AMDGPU_INFO_MMR_SE_INDEX_MASK; unsigned int sh_num = (info->read_mmr_reg.instance >> AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & AMDGPU_INFO_MMR_SH_INDEX_MASK; - - if (!down_read_trylock(&adev->reset_domain->sem)) - return -ENOENT; + unsigned int alloc_size; + uint32_t *regs; + int ret; /* set full masks if the userspace set all bits * in the bitfields */ - if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) { + if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) se_num = 0xffffffff; - } else if (se_num >= AMDGPU_GFX_MAX_SE) { - ret = -EINVAL; - goto out; - } + else if (se_num >= AMDGPU_GFX_MAX_SE) + return -EINVAL; - if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) { + if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) sh_num = 0xffffffff; - } else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) { - ret = -EINVAL; - goto out; - } + else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) + return -EINVAL; - if (info->read_mmr_reg.count > 128) { - ret = -EINVAL; - goto out; - } + if (info->read_mmr_reg.count > 128) + return -EINVAL; - regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); - if (!regs) { - ret = -ENOMEM; - goto out; - } + regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), + GFP_KERNEL); + if (!regs) + return -ENOMEM; + down_read(&adev->reset_domain->sem); alloc_size = info->read_mmr_reg.count * sizeof(*regs); - amdgpu_gfx_off_ctrl(adev, false); + ret = 0; for (i = 0; i < info->read_mmr_reg.count; i++) { if (amdgpu_asic_read_register(adev, se_num, sh_num, info->read_mmr_reg.dword_offset + i, ®s[i])) { DRM_DEBUG_KMS("unallowed offset %#x\n", info->read_mmr_reg.dword_offset + i); - kfree(regs); - amdgpu_gfx_off_ctrl(adev, true); ret = -EFAULT; - goto out; + break; } } amdgpu_gfx_off_ctrl(adev, true); - n = copy_to_user(out, regs, min(size, alloc_size)); - kfree(regs); - ret = (n ? -EFAULT : 0); -out: up_read(&adev->reset_domain->sem); + + if (!ret) { + ret = copy_to_user(out, regs, min(size, alloc_size)) + ? -EFAULT : 0; + } + kfree(regs); return ret; } case AMDGPU_INFO_DEV_INFO: { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 0d4c77c1b4b5..c9467b26e42c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -103,7 +103,7 @@ static inline u32 amdgpu_mes_get_hqd_mask(u32 num_pipe, int amdgpu_mes_init(struct amdgpu_device *adev) { - int i, r, num_pipes; + int i, r, num_pipes, num_queues = 0; u32 total_vmid_mask, reserved_vmid_mask; int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; u32 gfx_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.me.num_pipe_per_me, @@ -159,7 +159,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev) adev->mes.compute_hqd_mask[i] = compute_hqd_mask; } - num_pipes = adev->sdma.num_instances; + num_pipes = adev->sdma.num_inst_per_xcc ? + adev->sdma.num_inst_per_xcc : adev->sdma.num_instances; if (num_pipes > AMDGPU_MES_MAX_SDMA_PIPES) dev_warn(adev->dev, "more SDMA pipes than supported by MES! (%d vs %d)\n", num_pipes, AMDGPU_MES_MAX_SDMA_PIPES); @@ -216,8 +217,27 @@ int amdgpu_mes_init(struct amdgpu_device *adev) if (r) goto error_doorbell; + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0)) { + /* When queue/pipe reset is done in MES instead of in the + * driver, MES passes hung queues information to the driver in + * hung_queue_hqd_info. Calculate required space to store this + * information. + */ + for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) + num_queues += hweight32(adev->mes.gfx_hqd_mask[i]); + + for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) + num_queues += hweight32(adev->mes.compute_hqd_mask[i]); + + for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) + num_queues += hweight32(adev->mes.sdma_hqd_mask[i]) * num_xcc; + + adev->mes.hung_queue_hqd_info_offset = num_queues; + adev->mes.hung_queue_db_array_size = num_queues * 2; + } + if (adev->mes.hung_queue_db_array_size) { - for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { + for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { r = amdgpu_bo_create_kernel(adev, adev->mes.hung_queue_db_array_size * sizeof(u32), PAGE_SIZE, @@ -264,10 +284,10 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) &adev->mes.event_log_cpu_addr); for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { - amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], - &adev->mes.hung_queue_db_array_gpu_addr[i], - &adev->mes.hung_queue_db_array_cpu_addr[i]); - + if (adev->mes.hung_queue_db_array_gpu_obj[i]) + amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], + &adev->mes.hung_queue_db_array_gpu_addr[i], + &adev->mes.hung_queue_db_array_cpu_addr[i]); if (adev->mes.sch_ctx_ptr[i]) amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]); if (adev->mes.query_status_fence_ptr[i]) @@ -281,7 +301,7 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) mutex_destroy(&adev->mes.mutex_hidden); } -int amdgpu_mes_suspend(struct amdgpu_device *adev) +int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id) { struct mes_suspend_gang_input input; int r; @@ -291,6 +311,10 @@ int amdgpu_mes_suspend(struct amdgpu_device *adev) memset(&input, 0x0, sizeof(struct mes_suspend_gang_input)); input.suspend_all_gangs = 1; + input.xcc_id = xcc_id; + if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) && + ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x71)) + input.suspend_all_sdma_gangs = 1; /* * Avoid taking any other locks under MES lock to avoid circular @@ -305,7 +329,7 @@ int amdgpu_mes_suspend(struct amdgpu_device *adev) return r; } -int amdgpu_mes_resume(struct amdgpu_device *adev) +int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id) { struct mes_resume_gang_input input; int r; @@ -315,6 +339,7 @@ int amdgpu_mes_resume(struct amdgpu_device *adev) memset(&input, 0x0, sizeof(struct mes_resume_gang_input)); input.resume_all_gangs = 1; + input.xcc_id = xcc_id; /* * Avoid taking any other locks under MES lock to avoid circular @@ -428,7 +453,7 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, { struct mes_detect_and_reset_queue_input input; u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr[xcc_id]; - int r, i; + int hqd_info_offset = adev->mes.hung_queue_hqd_info_offset, r, i; if (!hung_db_num || !hung_db_array) return -EINVAL; @@ -443,26 +468,34 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, adev->mes.hung_queue_db_array_size * sizeof(u32)); input.queue_type = queue_type; input.detect_only = detect_only; + input.xcc_id = xcc_id; r = adev->mes.funcs->detect_and_reset_hung_queues(&adev->mes, &input); - if (r) { - dev_err(adev->dev, "failed to detect and reset\n"); - } else { - *hung_db_num = 0; - for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) { - if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) { - hung_db_array[i] = db_array[i]; - *hung_db_num += 1; - } - } - /* - * TODO: return HQD info for MES scheduled user compute queue reset cases - * stored in hung_db_array hqd info offset to full array size - */ + if (r && detect_only) { + dev_err(adev->dev, "Failed to detect hung queues\n"); + return r; } + *hung_db_num = 0; + /* MES passes hung queues' doorbell to driver */ + for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) { + /* Finding hung queues where db_array[i] is a valid doorbell */ + if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) { + hung_db_array[i] = db_array[i]; + *hung_db_num += 1; + } + } + + if (r && !(*hung_db_num)) { + dev_err(adev->dev, "Failed to detect and reset hung queues\n"); + return r; + } + + for (i = hqd_info_offset; i < hqd_info_offset + *hung_db_num; i++) + hung_db_array[i] = db_array[i]; + return r; } @@ -758,6 +791,12 @@ bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev) amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)); } +bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev) +{ + return (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) && + (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x73); +} + /* Fix me -- node_id is used to identify the correct MES instances in the future */ static int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev, uint32_t node_id, bool enable) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index f80e3aca9c78..93990d4990f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -170,6 +170,19 @@ struct amdgpu_mes { uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; }; +struct amdgpu_mes_hung_queue_hqd_info { + union { + struct { + u32 queue_type: 3; // queue type + u32 pipe_index: 4; // pipe index + u32 queue_index: 8; // queue index + u32 reserved: 17; + }; + + u32 bit0_31; + }; +}; + struct amdgpu_mes_gang { int gang_id; int priority; @@ -285,6 +298,7 @@ struct mes_unmap_legacy_queue_input { struct mes_suspend_gang_input { uint32_t xcc_id; bool suspend_all_gangs; + bool suspend_all_sdma_gangs; uint64_t gang_context_addr; uint64_t suspend_fence_addr; uint32_t suspend_fence_value; @@ -312,8 +326,9 @@ struct mes_reset_queue_input { }; struct mes_detect_and_reset_queue_input { - uint32_t queue_type; - bool detect_only; + u32 queue_type; + bool detect_only; + u32 xcc_id; }; struct mes_inv_tlbs_pasid_input { @@ -429,8 +444,8 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); int amdgpu_mes_init(struct amdgpu_device *adev); void amdgpu_mes_fini(struct amdgpu_device *adev); -int amdgpu_mes_suspend(struct amdgpu_device *adev); -int amdgpu_mes_resume(struct amdgpu_device *adev); +int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id); +int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id); int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring, uint32_t xcc_id); @@ -534,6 +549,7 @@ static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) } bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); +bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev); int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 51ab1a332615..8069fc41cc7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -38,7 +38,6 @@ #include #include #include -#include #include "amdgpu_irq.h" #include @@ -505,9 +504,6 @@ struct amdgpu_crtc { u32 line_time; u32 lb_vblank_lead_lines; struct drm_display_mode hw_mode; - /* for virtual dce */ - struct hrtimer vblank_timer; - enum amdgpu_interrupt_state vsync_timer_enabled; int otg_inst; struct drm_pending_vblank_event *event; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c index a974265837f0..e4c8e98725f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c @@ -84,3 +84,13 @@ int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if * amdgpu_ras_block_late_fini(adev, ras_block); return r; } + + +void amdgpu_nbio_program_aspm(struct amdgpu_device *adev) +{ + if (!amdgpu_device_should_use_aspm(adev)) + return; + + if (adev->nbio.funcs->program_aspm) + adev->nbio.funcs->program_aspm(adev); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h index b528de6a01f6..a61f3a6e8ec7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h @@ -121,4 +121,6 @@ u64 amdgpu_nbio_get_pcie_replay_count(struct amdgpu_device *adev); bool amdgpu_nbio_is_replay_cnt_supported(struct amdgpu_device *adev); +void amdgpu_nbio_program_aspm(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index b6aabac39b46..f98bfba59a2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -717,13 +717,17 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bo->tbo.resource->mem_type == TTM_PL_VRAM) { struct dma_fence *fence; - r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence); + r = amdgpu_ttm_clear_buffer(amdgpu_ttm_next_clear_entity(adev), + bo, bo->tbo.base.resv, &fence, + true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (unlikely(r)) goto fail_unreserve; - dma_resv_add_fence(bo->tbo.base.resv, fence, - DMA_RESV_USAGE_KERNEL); - dma_fence_put(fence); + if (fence) { + dma_resv_add_fence(bo->tbo.base.resv, fence, + DMA_RESV_USAGE_KERNEL); + dma_fence_put(fence); + } } if (!bp->resv) amdgpu_bo_unreserve(bo); @@ -1325,9 +1329,9 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) if (r) goto out; - r = amdgpu_fill_buffer(amdgpu_ttm_next_clear_entity(adev), - abo, 0, &bo->base._resv, - &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); + r = amdgpu_ttm_clear_buffer(amdgpu_ttm_next_clear_entity(adev), + abo, &bo->base._resv, &fence, + false, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 912c9afaf9e1..4d68732d6223 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -96,7 +96,8 @@ struct amdgpu_bo_va { * if non-zero, cannot unmap from GPU because user queues may still access it */ unsigned int queue_refcount; - atomic_t userq_va_mapped; + /* Indicates if this buffer is mapped for any user queue. Once set, never reset. */ + bool userq_va_mapped; }; struct amdgpu_bo { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index f0e4d020f4c7..665a2632379d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -52,6 +52,17 @@ static int psp_load_smu_fw(struct psp_context *psp); static int psp_rap_terminate(struct psp_context *psp); static int psp_securedisplay_terminate(struct psp_context *psp); +static const char * const amdgpu_ptl_fmt_str[] = { + [AMDGPU_PTL_FMT_I8] = "I8", + [AMDGPU_PTL_FMT_F16] = "F16", + [AMDGPU_PTL_FMT_BF16] = "BF16", + [AMDGPU_PTL_FMT_F32] = "F32", + [AMDGPU_PTL_FMT_F64] = "F64", + [AMDGPU_PTL_FMT_F8] = "F8", + [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", + [AMDGPU_PTL_FMT_INVALID] = "INVALID", +}; + static int psp_ring_init(struct psp_context *psp, enum psp_ring_type ring_type) { @@ -518,7 +529,7 @@ static int psp_sw_init(struct amdgpu_ip_block *ip_block) } ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, - (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? + (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, &psp->fw_pri_bo, &psp->fw_pri_mc_addr, @@ -682,6 +693,8 @@ static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) return "SPATIAL_PARTITION"; case GFX_CMD_ID_FB_NPS_MODE: return "NPS_MODE_CHANGE"; + case GFX_CMD_ID_PERF_HW: + return "PERF MONITORING HW"; default: return "UNKNOWN CMD"; } @@ -844,7 +857,11 @@ static int psp_load_toc(struct psp_context *psp, struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); /* Copy toc to psp firmware private buffer */ - psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); + ret = psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); + if (ret) { + release_psp_cmd_buf(psp); + return ret; + } psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); @@ -1160,8 +1177,11 @@ static int psp_rl_load(struct amdgpu_device *adev) cmd = acquire_psp_cmd_buf(psp); - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); + ret = psp_copy_fw(psp, psp->rl.start_addr, psp->rl.size_bytes); + if (ret) { + release_psp_cmd_buf(psp); + return ret; + } cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); @@ -1201,6 +1221,369 @@ int psp_memory_partition(struct psp_context *psp, int mode) return ret; } +static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, + uint32_t *ptl_fmt) +{ + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) + return -EINVAL; + + switch (fmt) { + case AMDGPU_PTL_FMT_I8: + *ptl_fmt = GFX_FTYPE_I8; + break; + case AMDGPU_PTL_FMT_F16: + *ptl_fmt = GFX_FTYPE_F16; + break; + case AMDGPU_PTL_FMT_BF16: + *ptl_fmt = GFX_FTYPE_BF16; + break; + case AMDGPU_PTL_FMT_F32: + *ptl_fmt = GFX_FTYPE_F32; + break; + case AMDGPU_PTL_FMT_F64: + *ptl_fmt = GFX_FTYPE_F64; + break; + case AMDGPU_PTL_FMT_F8: + *ptl_fmt = GFX_FTYPE_F8; + break; + case AMDGPU_PTL_FMT_VECTOR: + *ptl_fmt = GFX_FTYPE_VECTOR; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, + uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) +{ + struct psp_gfx_cmd_resp *cmd; + struct amdgpu_ptl *ptl = &psp->ptl; + int ret; + + cmd = acquire_psp_cmd_buf(psp); + + cmd->cmd_id = GFX_CMD_ID_PERF_HW; + cmd->cmd.cmd_req_perf_hw.req = req_code; + cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; + cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; + cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; + + ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); + if (ret) + goto out; + + /* + * Check response status explicitly to avoid + * updating cached PTL state with invalid data. + */ + if (cmd->resp.status) { + dev_err(psp->adev->dev, + "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", + req_code, cmd->resp.status, + cmd->resp.uresp.perf_hw_info.resp); + ret = -EIO; + goto out; + } + + /* Parse response */ + switch (req_code) { + case PSP_PTL_PERF_MON_QUERY: + *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; + *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; + *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; + dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", + *ptl_state, *fmt1, *fmt2); + break; + case PSP_PTL_PERF_MON_SET: + /* Update cached state only on success */ + ptl->enabled = *ptl_state; + ptl->fmt1 = *fmt1; + ptl->fmt2 = *fmt2; + dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", + *ptl_state, *fmt1, *fmt2); + break; + } + +out: + release_psp_cmd_buf(psp); + return ret; +} + +int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, + uint32_t *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2) +{ + uint32_t ptl_fmt1, ptl_fmt2; + struct psp_context *psp; + struct amdgpu_ptl *ptl; + int ret; + + if (!adev || !ptl_state || !fmt1 || !fmt2) + return -EINVAL; + + if (amdgpu_sriov_vf(adev)) + return 0; + + psp = &adev->psp; + ptl = &psp->ptl; + + if (ptl->permanently_disabled && *ptl_state == 1) + return 0; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || + psp->sos.fw_version < 0x0036081a) + return -EOPNOTSUPP; + + /* Verify formats */ + if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || + psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) + return -EINVAL; + + /* + * Add check to skip if state and formats are identical to current ones + */ + if (req_code == PSP_PTL_PERF_MON_SET && + ptl->enabled == *ptl_state && + ptl->fmt1 == ptl_fmt1 && + ptl->fmt2 == ptl_fmt2) + return 0; + + /* If enabling PTL, check disable bitmap */ + if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { + if (!bitmap_empty(ptl->disable_bitmap, + AMDGPU_PTL_DISABLE_MAX)) { + dev_dbg(adev->dev, + "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", + test_bit(AMDGPU_PTL_DISABLE_SYSFS, + ptl->disable_bitmap), + test_bit(AMDGPU_PTL_DISABLE_PROFILER, + ptl->disable_bitmap), + atomic_read(&ptl->disable_ref)); + return 0; + } + } + + if (req_code == PSP_PTL_PERF_MON_SET) { + amdgpu_amdkfd_stop_sched_all(adev); + /* Wait for GFX engine idle before PTL state transition */ + ret = amdgpu_device_ip_wait_for_idle(adev, + AMD_IP_BLOCK_TYPE_GFX); + if (ret) { + amdgpu_amdkfd_start_sched_all(adev); + dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); + return ret; + } + ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); + amdgpu_amdkfd_start_sched_all(adev); + } else { + ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); + } + + return ret; +} + +static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) +{ + int i; + + for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { + if (!strcmp(str, amdgpu_ptl_fmt_str[i])) + return (enum amdgpu_ptl_fmt)i; + } + + return AMDGPU_PTL_FMT_INVALID; +} + +static ssize_t ptl_supported_formats_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t len = 0; + + for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { + const char *fmt = amdgpu_ptl_fmt_str[i]; + + len += sysfs_emit_at(buf, len, "%s%s", + fmt ? fmt : "UNKNOWN", + (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); + } + + return len; +} + +static ssize_t ptl_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct amdgpu_ptl *ptl = &adev->psp.ptl; + uint32_t ptl_state, fmt1, fmt2; + int ret; + bool enable; + bool bit_changed = false; + + mutex_lock(&ptl->mutex); + if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { + enable = true; + } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { + enable = false; + } else { + mutex_unlock(&ptl->mutex); + return -EINVAL; + } + + /* Block enable when permanently disabled */ + if (ptl->permanently_disabled) { + mutex_unlock(&ptl->mutex); + return -EPERM; + } + + fmt1 = ptl->fmt1; + fmt2 = ptl->fmt2; + ptl_state = enable ? 1 : 0; + + if (enable) + bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, + ptl->disable_bitmap); + + ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); + if (ret) { + dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); + if (enable && bit_changed) + set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); + mutex_unlock(&ptl->mutex); + return ret; + } + + if (!enable) + set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); + + mutex_unlock(&ptl->mutex); + + return count; +} + +static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct amdgpu_ptl *ptl = &adev->psp.ptl; + + if (ptl->permanently_disabled) + return sysfs_emit(buf, "permanently disabled\n"); + + return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); +} + +static ssize_t ptl_format_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + char fmt1_str[8], fmt2_str[8]; + enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; + struct amdgpu_ptl *ptl = &adev->psp.ptl; + uint32_t ptl_state, fmt1, fmt2; + int ret; + + /* Only allow format update when PTL is enabled */ + if (!ptl->enabled) + return -EPERM; + + mutex_lock(&ptl->mutex); + /* Parse input, expecting "FMT1,FMT2" */ + if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { + mutex_unlock(&ptl->mutex); + return -EINVAL; + } + + fmt1_enum = str_to_ptl_fmt(fmt1_str); + fmt2_enum = str_to_ptl_fmt(fmt2_str); + + if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || + fmt2_enum >= AMDGPU_PTL_FMT_INVALID || + fmt1_enum == fmt2_enum) { + mutex_unlock(&ptl->mutex); + return -EINVAL; + } + + ptl_state = ptl->enabled; + fmt1 = fmt1_enum; + fmt2 = fmt2_enum; + ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); + if (ret) { + dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); + mutex_unlock(&ptl->mutex); + return ret; + } + mutex_unlock(&ptl->mutex); + + return count; +} + +static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct psp_context *psp = &adev->psp; + + return sysfs_emit(buf, "%s,%s\n", + amdgpu_ptl_fmt_str[psp->ptl.fmt1], + amdgpu_ptl_fmt_str[psp->ptl.fmt2]); +} + +static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + + /* Only show PTL sysfs files if PTL hardware is supported */ + if (!adev->psp.ptl.hw_supported) + return 0; + + return attr->mode; +} + +int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) +{ + struct amdgpu_ptl *ptl = &adev->psp.ptl; + int ret; + + if (!ptl->hw_supported) + return 0; + + if (ptl->ptl_sysfs_created) + return 0; + + ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); + if (!ret) + ptl->ptl_sysfs_created = true; + + return ret; +} + +void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ptl *ptl = &adev->psp.ptl; + + if (!ptl->hw_supported) + return; + + if (!ptl->ptl_sysfs_created) + return; + + sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); + ptl->ptl_sysfs_created = false; +} + int psp_spatial_partition(struct psp_context *psp, int mode) { struct psp_gfx_cmd_resp *cmd; @@ -1384,8 +1767,12 @@ int psp_ta_load(struct psp_context *psp, struct ta_context *context) cmd = acquire_psp_cmd_buf(psp); - psp_copy_fw(psp, context->bin_desc.start_addr, - context->bin_desc.size_bytes); + ret = psp_copy_fw(psp, context->bin_desc.start_addr, + context->bin_desc.size_bytes); + if (ret) { + release_psp_cmd_buf(psp); + return ret; + } if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && context->mem_context.shared_bo) @@ -3527,7 +3914,12 @@ int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) const struct psp_firmware_header_v1_0 *toc_hdr; int err = 0; - err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, + if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) && + adev->rev_id == 0) + err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_toc_1.bin", chip_name); + else + err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, "amdgpu/%s_toc.bin", chip_name); if (err) goto out; @@ -4181,17 +4573,24 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, return count; } -void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) +int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) { int idx; if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) - return; + return -ENODEV; + + if (!bin_size || bin_size > PSP_1_MEG) { + dev_err(psp->adev->dev, "PSP firmware is invalid\n"); + drm_dev_exit(idx); + return -EINVAL; + } memset(psp->fw_pri_buf, 0, PSP_1_MEG); memcpy(psp->fw_pri_buf, start_addr, bin_size); drm_dev_exit(idx); + return 0; } /** @@ -4202,6 +4601,31 @@ void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size static DEVICE_ATTR(usbc_pd_fw, 0644, psp_usbc_pd_fw_sysfs_read, psp_usbc_pd_fw_sysfs_write); +/** + * DOC: PTL sysfs attributes + * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable + * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported + * formats for each GPU. + */ +static DEVICE_ATTR(ptl_enable, 0644, + ptl_enable_show, ptl_enable_store); +static DEVICE_ATTR(ptl_format, 0644, + ptl_format_show, ptl_format_store); +static DEVICE_ATTR(ptl_supported_formats, 0444, + ptl_supported_formats_show, NULL); + +static struct attribute *ptl_attrs[] = { + &dev_attr_ptl_enable.attr, + &dev_attr_ptl_format.attr, + &dev_attr_ptl_supported_formats.attr, + NULL, +}; + +const struct attribute_group amdgpu_ptl_attr_group = { + .name = "ptl", + .attrs = ptl_attrs, + .is_visible = amdgpu_ptl_is_visible, +}; int is_psp_fw_valid(struct psp_bin_desc bin) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 7e94ec11c57e..2d838b1b2b11 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -31,6 +31,8 @@ #include "ta_ras_if.h" #include "ta_rap_if.h" #include "ta_secureDisplay_if.h" +#include +#include "amdgpu_ptl.h" #define PSP_FENCE_BUFFER_SIZE 0x1000 #define PSP_CMD_BUFFER_SIZE 0x1000 @@ -358,6 +360,29 @@ struct spirom_bo { }; #endif +enum psp_ptl_cmd { + PSP_PTL_PERF_MON_QUERY = 0xA0000000, + PSP_PTL_PERF_MON_SET = 0xA0000001, +}; + +enum psp_ptl_format_type { + GFX_FTYPE_I8 = 0x00000000, + GFX_FTYPE_F16 = 0x00000001, + GFX_FTYPE_BF16 = 0x00000002, + GFX_FTYPE_F32 = 0x00000003, + GFX_FTYPE_F64 = 0x00000004, + GFX_FTYPE_F8 = 0x00000005, + GFX_FTYPE_VECTOR = 0x00000006, + GFX_FTYPE_INVALID = 0xFFFFFFFF, +}; + +struct psp_ptl_perf_req { + enum psp_ptl_cmd req; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + struct psp_context { struct amdgpu_device *adev; struct psp_ring km_ring; @@ -448,6 +473,7 @@ struct psp_context { #if defined(CONFIG_DEBUG_FS) struct spirom_bo *spirom_dump_trip; #endif + struct amdgpu_ptl ptl; }; struct amdgpu_psp_funcs { @@ -612,7 +638,7 @@ int psp_get_fw_attestation_records_addr(struct psp_context *psp, int psp_update_fw_reservation(struct psp_context *psp); int psp_load_fw_list(struct psp_context *psp, struct amdgpu_firmware_info **ucode_list, int ucode_count); -void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); +int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); int psp_spatial_partition(struct psp_context *psp, int mode); int psp_memory_partition(struct psp_context *psp, int mode); @@ -631,5 +657,4 @@ void amdgpu_psp_debugfs_init(struct amdgpu_device *adev); int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type); - #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 6c644cfe6695..3e1f8b15f75d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3093,6 +3093,25 @@ static int amdgpu_ras_mca2pa(struct amdgpu_device *adev, return -EINVAL; } +static bool __check_record_in_range(struct amdgpu_device *adev, + struct eeprom_table_record *bps, int count) +{ + int i; + + for (i = 0; i < count; i++) { + if (bps[i].retired_page >= + (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT)) { + dev_warn(adev->dev, + "Recorded address out of range: 0x%llx, 0x%llx, 0x%x, 0x%x\n", + bps[i].address, bps[i].retired_page, + bps[i].mem_channel, bps[i].mcumc_id); + return false; + } + } + + return true; +} + static int __amdgpu_ras_restore_bad_pages(struct amdgpu_device *adev, struct eeprom_table_record *bps, int count) { @@ -3100,6 +3119,9 @@ static int __amdgpu_ras_restore_bad_pages(struct amdgpu_device *adev, struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_err_handler_data *data = con->eh_data; + if (!__check_record_in_range(adev, bps, count)) + return 0; + for (j = 0; j < count; j++) { if (!data->space_left && amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { @@ -5641,6 +5663,11 @@ int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn) uint64_t start = pfn << AMDGPU_GPU_PAGE_SHIFT; int ret = 0; + if (pfn >= (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT)) { + dev_warn(adev->dev, "Ignoring out-of-range bad page 0x%llx", start); + return 0; + } + if (amdgpu_ras_check_critical_address(adev, start)) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index cdf4909592d2..c61389a07982 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1051,6 +1051,7 @@ int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, uint64_t ts, end_idx; int i, ret; u64 mca, ipid; + u32 cu, mem_channel, mcumc_id; if (!amdgpu_ras_smu_eeprom_supported(adev)) return 0; @@ -1079,9 +1080,10 @@ int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, record[i - rec_idx].err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; adev->umc.ras->mca_ipid_parse(adev, ipid, - (uint32_t *)&(record[i - rec_idx].cu), - (uint32_t *)&(record[i - rec_idx].mem_channel), - (uint32_t *)&(record[i - rec_idx].mcumc_id), NULL); + &cu, &mem_channel, &mcumc_id, NULL); + record[i - rec_idx].cu = (u8)cu; + record[i - rec_idx].mem_channel = (u8)mem_channel; + record[i - rec_idx].mcumc_id = (u8)mcumc_id; } return 0; @@ -1632,6 +1634,14 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) } control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); + if (hdr->first_rec_offset < control->ras_record_offset || + control->ras_fri >= control->ras_max_record_count) { + dev_err(adev->dev, + "RAS header invalid, ras_fri: %u, first_rec_offset:0x%x", + control->ras_fri, hdr->first_rec_offset); + return -EINVAL; + } + control->ras_num_mca_recs = 0; control->ras_num_pa_recs = 0; return 0; @@ -1950,7 +1960,7 @@ void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev) if (!control || amdgpu_bad_page_threshold == 0) return; - if (control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) { + if (control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { if (amdgpu_dpm_send_rma_reason(adev)) dev_warn(adev->dev, "Unable to send out-of-band RMA CPER"); else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 540040c76058..daefbeeee4d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -956,3 +956,21 @@ uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, } return ret; } + + +uint32_t amdgpu_read_indexed_register(struct amdgpu_device *adev, + u32 se_num, u32 sh_num, u32 reg_offset) +{ + uint32_t val; + + mutex_lock(&adev->grbm_idx_mutex); + if (se_num != 0xffffffff || sh_num != 0xffffffff) + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); + + val = RREG32(reg_offset); + + if (se_num != 0xffffffff || sh_num != 0xffffffff) + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); + mutex_unlock(&adev->grbm_idx_mutex); + return val; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index 4d88e5cd19fc..a1011af6b52b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -160,4 +160,7 @@ uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, uint32_t reg_addr, char reg_name[], uint32_t expected_value, uint32_t mask); +uint32_t amdgpu_read_indexed_register(struct amdgpu_device *adev, + u32 se_num, u32 sh_num, u32 reg_offset); + #endif /* __AMDGPU_REG_ACCESS_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index 1b982b803e6f..428c3cbc4a40 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -90,6 +90,7 @@ static int amdgpu_reset_xgmi_reset_on_init_restore_hwctxt( kgd2kfd_init_zone_device(tmp_adev); amdgpu_amdkfd_device_init(tmp_adev); amdgpu_amdkfd_drm_client_create(tmp_adev); + amdgpu_ptl_sysfs_init(tmp_adev); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 07b4d37f1db6..c9f23a8e8db8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -46,6 +46,47 @@ enum AMDGPU_RESET_SRCS { AMDGPU_RESET_SRC_USERQ, }; +/** + * enum amd_reset_method - Methods for resetting AMD GPU devices + * + * @AMD_RESET_METHOD_NONE: The device will not be reset. + * @AMD_RESET_METHOD_LEGACY: Method reserved for SI, CIK and VI ASICs. + * @AMD_RESET_METHOD_MODE0: Reset the entire ASIC. Not currently available for + * the any device. + * @AMD_RESET_METHOD_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, + * etc.) individually. Suitable only for some discrete GPU, + * not available for all ASICs. + * @AMD_RESET_METHOD_MODE2: Resets a lesser level of IPs compared to MODE1. + * Which IPs are reset depends on the ASIC. Notably doesn't + * reset IPs shared with the CPU on APUs or the memory + * controllers (so VRAM is not lost). Not available on all + * ASICs. + * @AMD_RESET_METHOD_LINK: Triggers SW-UP link reset on other GPUs + * @AMD_RESET_METHOD_BACO: BACO (Bus Alive, Chip Off) method powers off and on + * the card but without powering off the PCI bus. Suitable + * only for discrete GPUs. + * @AMD_RESET_METHOD_PCI: Does a full bus reset using core Linux subsystem + * PCI reset and does a secondary bus reset or FLR, + * depending on what the underlying hardware supports. + * @AMD_RESET_METHOD_ON_INIT: Does a device reset during the driver init + * sequence. + * + * Methods available for AMD GPU driver for resetting the device. Not all + * methods are suitable for every device. User can override the method using + * module parameter `reset_method`. + */ +enum amd_reset_method { + AMD_RESET_METHOD_NONE = -1, + AMD_RESET_METHOD_LEGACY = 0, + AMD_RESET_METHOD_MODE0, + AMD_RESET_METHOD_MODE1, + AMD_RESET_METHOD_MODE2, + AMD_RESET_METHOD_LINK, + AMD_RESET_METHOD_BACO, + AMD_RESET_METHOD_PCI, + AMD_RESET_METHOD_ON_INIT, +}; + struct amdgpu_reset_context { enum amd_reset_method method; struct amdgpu_device *reset_req_dev; @@ -56,6 +97,20 @@ struct amdgpu_reset_context { enum AMDGPU_RESET_SRCS src; }; +struct amdgpu_reset_control { + void *handle; + struct work_struct reset_work; + struct mutex reset_lock; + struct amdgpu_reset_handler *( + *reset_handlers)[AMDGPU_RESET_MAX_HANDLERS]; + atomic_t in_reset; + enum amd_reset_method active_reset; + struct amdgpu_reset_handler *(*get_reset_handler)( + struct amdgpu_reset_control *reset_ctl, + struct amdgpu_reset_context *context); + void (*async_reset)(struct work_struct *work); +}; + struct amdgpu_reset_handler { enum amd_reset_method reset_method; int (*prepare_env)(struct amdgpu_reset_control *reset_ctl, @@ -72,20 +127,6 @@ struct amdgpu_reset_handler { int (*do_reset)(struct amdgpu_device *adev); }; -struct amdgpu_reset_control { - void *handle; - struct work_struct reset_work; - struct mutex reset_lock; - struct amdgpu_reset_handler *( - *reset_handlers)[AMDGPU_RESET_MAX_HANDLERS]; - atomic_t in_reset; - enum amd_reset_method active_reset; - struct amdgpu_reset_handler *(*get_reset_handler)( - struct amdgpu_reset_control *reset_ctl, - struct amdgpu_reset_context *context); - void (*async_reset)(struct work_struct *work); -}; - enum amdgpu_reset_domain_type { SINGLE_DEVICE, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 66e8a2f7afcf..d6bee5c30073 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -552,8 +552,9 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { struct amdgpu_ring *ring = file_inode(f)->i_private; - uint32_t value, result, early[3]; + u32 value, result, early[3] = { 0 }; uint64_t p; + u32 avail_dw, start_dw, read_dw; loff_t i; int r; @@ -565,10 +566,10 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, result = 0; - if (*pos < 12) { - if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) - mutex_lock(&ring->adev->cper.ring_lock); + if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) + mutex_lock(&ring->adev->cper.ring_lock); + if (*pos < 12) { early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; early[2] = ring->wptr & ring->buf_mask; @@ -600,13 +601,24 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, *pos += 4; } } else { + early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; + early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; + p = early[0]; if (early[0] <= early[1]) - size = (early[1] - early[0]); + avail_dw = early[1] - early[0]; else - size = ring->ring_size - (early[0] - early[1]); + avail_dw = ring->buf_mask + 1 - (early[0] - early[1]); - while (size) { + start_dw = (*pos > 12) ? ((*pos - 12) >> 2) : 0; + if (start_dw >= avail_dw) + goto out; + + p = (p + start_dw) & ring->ptr_mask; + avail_dw -= start_dw; + read_dw = min_t(u32, avail_dw, size >> 2); + + while (read_dw) { if (p == early[1]) goto out; @@ -619,9 +631,10 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, buf += 4; result += 4; - size--; + read_dw--; p++; p &= ring->ptr_mask; + *pos += 4; } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 715c9e43e13a..8f28b3bd7010 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -159,7 +159,8 @@ struct amdgpu_fence { extern const struct drm_sched_backend_ops amdgpu_sched_ops; void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); -void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); +void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring, + struct dma_fence *timedout_fence); void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring, struct amdgpu_fence *guilty_fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index 321310ba2c08..fcd81242059e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -600,10 +600,10 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id, * to be submitted to the queues after the reset is complete. */ if (!ret) { - amdgpu_fence_driver_force_completion(gfx_ring); + amdgpu_fence_driver_force_completion(gfx_ring, NULL); drm_sched_wqueue_start(&gfx_ring->sched); if (adev->sdma.has_page_queue) { - amdgpu_fence_driver_force_completion(page_ring); + amdgpu_fence_driver_force_completion(page_ring, NULL); drm_sched_wqueue_start(&page_ring->sched); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c index a0b479d5fff1..f4be19223588 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c @@ -175,11 +175,14 @@ int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va, { unsigned long bit_pos; - bit_pos = find_first_zero_bit(adev->seq64.used, adev->seq64.num_sem); - if (bit_pos >= adev->seq64.num_sem) - return -ENOSPC; + for (;;) { + bit_pos = find_first_zero_bit(adev->seq64.used, adev->seq64.num_sem); + if (bit_pos >= adev->seq64.num_sem) + return -ENOSPC; - __set_bit(bit_pos, adev->seq64.used); + if (!test_and_set_bit(bit_pos, adev->seq64.used)) + break; + } *va = bit_pos * sizeof(u64) + amdgpu_seq64_get_va_base(adev); @@ -205,7 +208,7 @@ void amdgpu_seq64_free(struct amdgpu_device *adev, u64 va) bit_pos = (va - amdgpu_seq64_get_va_base(adev)) / sizeof(u64); if (bit_pos < adev->seq64.num_sem) - __clear_bit(bit_pos, adev->seq64.used); + clear_bit(bit_pos, adev->seq64.used); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index d13e64a69e25..85724ec6aaf8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -145,6 +145,7 @@ TRACE_EVENT(amdgpu_cs, struct amdgpu_ib *ib), TP_ARGS(p, job, ib), TP_STRUCT__entry( + __field(struct drm_gpu_scheduler *, sched) __field(struct amdgpu_bo_list *, bo_list) __field(u32, ring) __field(u32, dw) @@ -152,11 +153,14 @@ TRACE_EVENT(amdgpu_cs, ), TP_fast_assign( + __entry->sched = container_of(job->base.entity->rq, + typeof(*__entry->sched), + rq); __entry->bo_list = p->bo_list; - __entry->ring = to_amdgpu_ring(job->base.entity->rq->sched)->idx; + __entry->ring = to_amdgpu_ring(__entry->sched)->idx; __entry->dw = ib->length_dw; __entry->fences = amdgpu_fence_count_emitted( - to_amdgpu_ring(job->base.entity->rq->sched)); + to_amdgpu_ring(__entry->sched)); ), TP_printk("bo_list=%p, ring=%u, dw=%u, fences=%u", __entry->bo_list, __entry->ring, __entry->dw, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 0dc68fb9d88e..2740de94e93c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -75,6 +75,9 @@ static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, unsigned int type, uint64_t size_in_page) { + if (!size_in_page) + return 0; + return ttm_range_man_init(&adev->mman.bdev, type, false, size_in_page); } @@ -168,7 +171,7 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entit { struct amdgpu_ring *ring; - ring = adev->mman.buffer_funcs_ring; + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > num_dw); @@ -417,8 +420,8 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, if (old_mem->mem_type == TTM_PL_VRAM && (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { struct dma_fence *wipe_fence = NULL; - r = amdgpu_fill_buffer(entity, abo, 0, NULL, &wipe_fence, - AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); + r = amdgpu_ttm_clear_buffer(entity, abo, NULL, &wipe_fence, + false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { goto error; } else if (wipe_fence) { @@ -1560,7 +1563,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, if (!adev->mman.sdma_access_ptr) return -EACCES; - if (!drm_dev_enter(adev_to_drm(adev), &idx)) + if (!adev->mman.buffer_funcs_enabled || !drm_dev_enter(adev_to_drm(adev), &idx)) return -ENODEV; if (write) @@ -1712,10 +1715,7 @@ static void amdgpu_ttm_init_fw_resv_region(struct amdgpu_device *adev) reserve_size = max(reserve_size, (uint32_t)280 << 20); else if (!adev->bios && amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { - if (hweight32(adev->aid_mask) == 1) - reserve_size = max(reserve_size, (uint32_t)128 << 20); - else - reserve_size = max(reserve_size, (uint32_t)144 << 20); + reserve_size = max(reserve_size, (uint32_t)150 << 20); } else if (!reserve_size) reserve_size = DISCOVERY_TMR_OFFSET; @@ -2098,7 +2098,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) } /* Change the size here instead of the init above so only lpfn is affected */ - amdgpu_ttm_set_buffer_funcs_status(adev, false); + amdgpu_ttm_disable_buffer_funcs(adev); #ifdef CONFIG_64BIT #ifdef CONFIG_X86 if (adev->gmc.xgmi.connected_to_cpu) @@ -2278,115 +2278,92 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) } /** - * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions + * amdgpu_ttm_enable_buffer_funcs - enable use of buffer functions * * @adev: amdgpu_device pointer - * @enable: true when we can use buffer functions. * - * Enable/disable use of buffer functions during suspend/resume. This should + * Enable use of buffer functions during suspend/resume. This should * only be called at bootup or when userspace isn't running. */ -void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) +void amdgpu_ttm_enable_buffer_funcs(struct amdgpu_device *adev) { struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); u32 num_clear_entities, num_move_entities; - uint64_t size; int r, i, j; if (!adev->mman.initialized || amdgpu_in_reset(adev) || - adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu) + adev->mman.buffer_funcs_enabled || adev->gmc.is_app_apu) return; - if (enable) { - struct amdgpu_ring *ring; - struct drm_gpu_scheduler *sched; + if (!adev->mman.num_buffer_funcs_scheds) { + dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use"); + return; + } - if (!adev->mman.buffer_funcs_ring || !adev->mman.buffer_funcs_ring->sched.ready) { - dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use"); - return; - } + /* default_entity doesn't need multiple schedulers so pass only 1. */ + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.default_entity, + DRM_SCHED_PRIORITY_KERNEL, + adev->mman.buffer_funcs_scheds, 1, 0); + if (r < 0) { + dev_err(adev->dev, + "Failed setting up TTM entity (%d)\n", r); + return; + } + + num_clear_entities = MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOVE_FENCES); + num_move_entities = MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOVE_FENCES); + + adev->mman.clear_entities = kcalloc(num_clear_entities, + sizeof(struct amdgpu_ttm_buffer_entity), + GFP_KERNEL); + atomic_set(&adev->mman.next_clear_entity, 0); + if (!adev->mman.clear_entities) + goto error_free_default_entity; + + adev->mman.num_clear_entities = num_clear_entities; + + for (i = 0; i < num_clear_entities; i++) { + r = amdgpu_ttm_buffer_entity_init( + &adev->mman.gtt_mgr, + &adev->mman.clear_entities[i], + DRM_SCHED_PRIORITY_KERNEL, + adev->mman.buffer_funcs_scheds, + adev->mman.num_buffer_funcs_scheds, 1); - num_clear_entities = 1; - num_move_entities = 1; - ring = adev->mman.buffer_funcs_ring; - sched = &ring->sched; - r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, - &adev->mman.default_entity, - DRM_SCHED_PRIORITY_KERNEL, - &sched, 1, 0); if (r < 0) { - dev_err(adev->dev, - "Failed setting up TTM entity (%d)\n", r); - return; - } - - adev->mman.clear_entities = kcalloc(num_clear_entities, - sizeof(struct amdgpu_ttm_buffer_entity), - GFP_KERNEL); - atomic_set(&adev->mman.next_clear_entity, 0); - if (!adev->mman.clear_entities) + for (j = 0; j < i; j++) + amdgpu_ttm_buffer_entity_fini( + &adev->mman.gtt_mgr, &adev->mman.clear_entities[j]); + adev->mman.num_clear_entities = 0; + kfree(adev->mman.clear_entities); goto error_free_default_entity; - - adev->mman.num_clear_entities = num_clear_entities; - - for (i = 0; i < num_clear_entities; i++) { - r = amdgpu_ttm_buffer_entity_init( - &adev->mman.gtt_mgr, &adev->mman.clear_entities[i], - DRM_SCHED_PRIORITY_NORMAL, &sched, 1, 1); - - if (r < 0) { - for (j = 0; j < i; j++) - amdgpu_ttm_buffer_entity_fini( - &adev->mman.gtt_mgr, &adev->mman.clear_entities[j]); - kfree(adev->mman.clear_entities); - adev->mman.num_clear_entities = 0; - adev->mman.clear_entities = NULL; - goto error_free_default_entity; - } } + } - adev->mman.num_move_entities = num_move_entities; - atomic_set(&adev->mman.next_move_entity, 0); - for (i = 0; i < num_move_entities; i++) { - r = amdgpu_ttm_buffer_entity_init( - &adev->mman.gtt_mgr, - &adev->mman.move_entities[i], - DRM_SCHED_PRIORITY_NORMAL, &sched, 1, 2); + adev->mman.num_move_entities = num_move_entities; + atomic_set(&adev->mman.next_move_entity, 0); + for (i = 0; i < num_move_entities; i++) { + r = amdgpu_ttm_buffer_entity_init( + &adev->mman.gtt_mgr, + &adev->mman.move_entities[i], + DRM_SCHED_PRIORITY_KERNEL, + adev->mman.buffer_funcs_scheds, + adev->mman.num_buffer_funcs_scheds, 2); - if (r < 0) { - for (j = 0; j < i; j++) - amdgpu_ttm_buffer_entity_fini( - &adev->mman.gtt_mgr, &adev->mman.move_entities[j]); - adev->mman.num_move_entities = 0; - goto error_free_clear_entities; - } + if (r < 0) { + for (j = 0; j < i; j++) + amdgpu_ttm_buffer_entity_fini( + &adev->mman.gtt_mgr, + &adev->mman.move_entities[j]); + adev->mman.num_move_entities = 0; + goto error_free_clear_entities; } - } else { - amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, - &adev->mman.default_entity); - for (i = 0; i < adev->mman.num_clear_entities; i++) - amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, - &adev->mman.clear_entities[i]); - for (i = 0; i < adev->mman.num_move_entities; i++) - amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, - &adev->mman.move_entities[i]); - /* Drop all the old fences since re-creating the scheduler entities - * will allocate new contexts. - */ - ttm_resource_manager_cleanup(man); - kfree(adev->mman.clear_entities); - adev->mman.clear_entities = NULL; - adev->mman.num_clear_entities = 0; - adev->mman.num_move_entities = 0; } /* this just adjusts TTM size idea, which sets lpfn to the correct value */ - if (enable) - size = adev->gmc.real_vram_size; - else - size = adev->gmc.visible_vram_size; - man->size = size; - adev->mman.buffer_funcs_enabled = enable; + man->size = adev->gmc.real_vram_size; + adev->mman.buffer_funcs_enabled = true; return; @@ -2402,6 +2379,42 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) &adev->mman.default_entity); } +/** + * amdgpu_ttm_disable_buffer_funcs - disable use of buffer functions + * + * @adev: amdgpu_device pointer + */ +void amdgpu_ttm_disable_buffer_funcs(struct amdgpu_device *adev) +{ + struct ttm_resource_manager *man = + ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); + int i; + + if (!adev->mman.buffer_funcs_enabled || amdgpu_in_reset(adev)) + return; + + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.default_entity); + for (i = 0; i < adev->mman.num_move_entities; i++) + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.move_entities[i]); + for (i = 0; i < adev->mman.num_clear_entities; i++) + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.clear_entities[i]); + /* Drop all the old fences since re-creating the scheduler entities + * will allocate new contexts. + */ + ttm_resource_manager_cleanup(man); + + kfree(adev->mman.clear_entities); + adev->mman.clear_entities = NULL; + adev->mman.num_clear_entities = 0; + adev->mman.num_move_entities = 0; + + man->size = adev->gmc.visible_vram_size; + adev->mman.buffer_funcs_enabled = false; +} + static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, unsigned int num_dw, @@ -2446,7 +2459,7 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, unsigned int i; int r; - ring = adev->mman.buffer_funcs_ring; + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); if (!ring->sched.ready) { dev_err(adev->dev, @@ -2521,77 +2534,23 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, } /** - * amdgpu_ttm_clear_buffer - clear memory buffers - * @bo: amdgpu buffer object - * @resv: reservation object - * @fence: dma_fence associated with the operation + * amdgpu_ttm_clear_buffer - fill a buffer with 0 + * @entity: entity to use + * @bo: the bo to fill + * @resv: fences contained in this reservation will be used as dependencies. + * @out_fence: the fence from the last clear will be stored here. It might be + * NULL if no job was run. + * @consider_clear_status: true if region reported as cleared by amdgpu_res_cleared() + * are skipped. + * @k_job_id: trace id * - * Clear the memory buffer resource. - * - * Returns: - * 0 for success or a negative error code on failure. */ -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, +int amdgpu_ttm_clear_buffer(struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_bo *bo, struct dma_resv *resv, - struct dma_fence **fence) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - struct amdgpu_ttm_buffer_entity *entity; - struct amdgpu_res_cursor cursor; - u64 addr; - int r = 0; - - if (!adev->mman.buffer_funcs_enabled) - return -EINVAL; - - if (!fence) - return -EINVAL; - entity = &adev->mman.clear_entities[0]; - *fence = dma_fence_get_stub(); - - amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); - - mutex_lock(&entity->lock); - while (cursor.remaining) { - struct dma_fence *next = NULL; - u64 size; - - if (amdgpu_res_cleared(&cursor)) { - amdgpu_res_next(&cursor, cursor.size); - continue; - } - - /* Never clear more than 256MiB at once to avoid timeouts */ - size = min(cursor.size, 256ULL << 20); - - r = amdgpu_ttm_map_buffer(entity, &bo->tbo, bo->tbo.resource, &cursor, - 0, false, &size, &addr); - if (r) - goto err; - - r = amdgpu_ttm_fill_mem(adev, entity, 0, addr, size, resv, - &next, true, - AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); - if (r) - goto err; - - dma_fence_put(*fence); - *fence = next; - - amdgpu_res_next(&cursor, size); - } -err: - mutex_unlock(&entity->lock); - - return r; -} - -int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, - struct amdgpu_bo *bo, - uint32_t src_data, - struct dma_resv *resv, - struct dma_fence **f, - u64 k_job_id) + struct dma_fence **out_fence, + bool consider_clear_status, + u64 k_job_id) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct dma_fence *fence = NULL; @@ -2608,6 +2567,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, struct dma_fence *next; uint64_t cur_size, to; + if (consider_clear_status && amdgpu_res_cleared(&dst)) { + amdgpu_res_next(&dst, dst.size); + continue; + } + /* Never fill more than 256MiB at once to avoid timeouts */ cur_size = min(dst.size, 256ULL << 20); @@ -2617,7 +2581,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, goto error; r = amdgpu_ttm_fill_mem(adev, entity, - src_data, to, cur_size, resv, + 0, to, cur_size, resv, &next, true, k_job_id); if (r) goto error; @@ -2629,9 +2593,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, } error: mutex_unlock(&entity->lock); - if (f) - *f = dma_fence_get(fence); - dma_fence_put(fence); + *out_fence = fence; return r; } @@ -2679,6 +2641,41 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) return ttm_resource_manager_evict_all(&adev->mman.bdev, man); } +void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, + const struct amdgpu_buffer_funcs *buffer_funcs) +{ + struct drm_gpu_scheduler *sched; + struct amdgpu_vmhub *hub; + int i, n; + + adev->mman.buffer_funcs = buffer_funcs; + + for (i = 0, n = 0; i < adev->sdma.num_instances; i++) { + if (adev->sdma.has_page_queue) + sched = &adev->sdma.instance[i].page.sched; + else + sched = &adev->sdma.instance[i].ring.sched; + + if (!sched->ready) + continue; + + adev->mman.buffer_funcs_scheds[n++] = sched; + } + + if (n == 0) { + adev->mman.num_buffer_funcs_scheds = 0; + drm_warn(&adev->ddev, "No working sdma ring available\n"); + return; + } + + /* Navi1x's workaround requires us to limit to a single SDMA sched + * for ttm. + */ + hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; + adev->mman.num_buffer_funcs_scheds = hub->sdma_invalidation_workaround ? + 1 : n; +} + #if defined(CONFIG_DEBUG_FS) static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index f2f23a42b3cc..2d72fa217274 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -87,7 +87,8 @@ struct amdgpu_mman { /* buffer handling */ const struct amdgpu_buffer_funcs *buffer_funcs; - struct amdgpu_ring *buffer_funcs_ring; + struct drm_gpu_scheduler *buffer_funcs_scheds[AMDGPU_MAX_RINGS]; + u32 num_buffer_funcs_scheds; bool buffer_funcs_enabled; /* @default_entity: for workarounds, has no gart windows */ @@ -184,8 +185,8 @@ void amdgpu_ttm_unmark_vram_reserved(struct amdgpu_device *adev, int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); -void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, - bool enable); +void amdgpu_ttm_enable_buffer_funcs(struct amdgpu_device *adev); +void amdgpu_ttm_disable_buffer_funcs(struct amdgpu_device *adev); int amdgpu_copy_buffer(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, uint64_t src_offset, @@ -193,15 +194,12 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, struct dma_resv *resv, struct dma_fence **fence, bool vm_needs_flush, uint32_t copy_flags); -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, +int amdgpu_ttm_clear_buffer(struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_bo *bo, struct dma_resv *resv, - struct dma_fence **fence); -int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, - struct amdgpu_bo *bo, - uint32_t src_data, - struct dma_resv *resv, - struct dma_fence **f, - u64 k_job_id); + struct dma_fence **out_fence, + bool consider_clear_status, + u64 k_job_id); struct amdgpu_ttm_buffer_entity *amdgpu_ttm_next_clear_entity(struct amdgpu_device *adev); int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index 0238c2798de4..b8ed931f8a40 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -130,6 +130,7 @@ void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && adev->umc.ras->ras_block.hw_ops->query_ras_error_address && adev->umc.max_ras_err_cnt_per_query) { + kfree(err_data->err_addr); err_data->err_addr = kzalloc_objs(struct eeprom_table_record, adev->umc.max_ras_err_cnt_per_query); @@ -160,6 +161,7 @@ void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, if (adev->umc.ras && adev->umc.ras->ecc_info_query_ras_error_address && adev->umc.max_ras_err_cnt_per_query) { + kfree(err_data->err_addr); err_data->err_addr = kzalloc_objs(struct eeprom_table_record, adev->umc.max_ras_err_cnt_per_query); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index d5abf785ca17..b634defb0be8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -82,19 +82,11 @@ static bool amdgpu_userq_is_reset_type_supported(struct amdgpu_device *adev, return false; } -static void amdgpu_userq_gpu_reset(struct amdgpu_device *adev) -{ - if (amdgpu_device_should_recover_gpu(adev)) { - amdgpu_reset_domain_schedule(adev->reset_domain, - &adev->userq_reset_work); - /* Wait for the reset job to complete */ - flush_work(&adev->userq_reset_work); - } -} - -static int -amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) +static void amdgpu_userq_mgr_reset_work(struct work_struct *work) { + struct amdgpu_userq_mgr *uq_mgr = + container_of(work, struct amdgpu_userq_mgr, + reset_work); struct amdgpu_device *adev = uq_mgr->adev; const int queue_types[] = { AMDGPU_RING_TYPE_COMPUTE, @@ -103,15 +95,11 @@ amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) }; const int num_queue_types = ARRAY_SIZE(queue_types); bool gpu_reset = false; - int r = 0; - int i; - - /* Warning if current process mutex is not held */ - WARN_ON(!mutex_is_locked(&uq_mgr->userq_mutex)); + int i, r; if (unlikely(adev->debug_disable_gpu_ring_reset)) { dev_err(adev->dev, "userq reset disabled by debug mask\n"); - return 0; + return; } /* @@ -119,7 +107,7 @@ amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) * skip all reset detection logic */ if (!amdgpu_gpu_recovery) - return 0; + return; /* * Iterate through all queue types to detect and reset problematic queues @@ -127,9 +115,11 @@ amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) */ for (i = 0; i < num_queue_types; i++) { int ring_type = queue_types[i]; - const struct amdgpu_userq_funcs *funcs = adev->userq_funcs[ring_type]; + const struct amdgpu_userq_funcs *funcs = + adev->userq_funcs[ring_type]; - if (!amdgpu_userq_is_reset_type_supported(adev, ring_type, AMDGPU_RESET_TYPE_PER_QUEUE)) + if (!amdgpu_userq_is_reset_type_supported(adev, ring_type, + AMDGPU_RESET_TYPE_PER_QUEUE)) continue; if (atomic_read(&uq_mgr->userq_count[ring_type]) > 0 && @@ -142,46 +132,43 @@ amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) } } - if (gpu_reset) - amdgpu_userq_gpu_reset(adev); + if (gpu_reset) { + struct amdgpu_reset_context reset_context; - return r; + memset(&reset_context, 0, sizeof(reset_context)); + + reset_context.method = AMD_RESET_METHOD_NONE; + reset_context.reset_req_dev = adev; + reset_context.src = AMDGPU_RESET_SRC_USERQ; + set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); + /*set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags);*/ + + amdgpu_device_gpu_recover(adev, NULL, &reset_context); + } } static void amdgpu_userq_hang_detect_work(struct work_struct *work) { - struct amdgpu_usermode_queue *queue = container_of(work, - struct amdgpu_usermode_queue, - hang_detect_work.work); - struct dma_fence *fence; - struct amdgpu_userq_mgr *uq_mgr; + struct amdgpu_usermode_queue *queue = + container_of(work, struct amdgpu_usermode_queue, + hang_detect_work.work); - if (!queue->userq_mgr) - return; - - uq_mgr = queue->userq_mgr; - fence = READ_ONCE(queue->hang_detect_fence); - /* Fence already signaled – no action needed */ - if (!fence || dma_fence_is_signaled(fence)) - return; - - mutex_lock(&uq_mgr->userq_mutex); - amdgpu_userq_detect_and_reset_queues(uq_mgr); - mutex_unlock(&uq_mgr->userq_mutex); + /* + * Don't schedule the work here! Scheduling or queue work from one reset + * handler to another is illegal if you don't take extra precautions! + */ + amdgpu_userq_mgr_reset_work(&queue->userq_mgr->reset_work); } /* * Start hang detection for a user queue fence. A delayed work will be scheduled - * to check if the fence is still pending after the timeout period. -*/ + * to reset the queues when the fence doesn't signal in time. + */ void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue) { struct amdgpu_device *adev; unsigned long timeout_ms; - if (!queue || !queue->userq_mgr || !queue->userq_mgr->adev) - return; - adev = queue->userq_mgr->adev; /* Determine timeout based on queue type */ switch (queue->queue_type) { @@ -199,16 +186,33 @@ void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue) break; } - /* Store the fence to monitor and schedule hang detection */ - WRITE_ONCE(queue->hang_detect_fence, queue->last_fence); - schedule_delayed_work(&queue->hang_detect_work, - msecs_to_jiffies(timeout_ms)); + queue_delayed_work(adev->reset_domain->wq, &queue->hang_detect_work, + msecs_to_jiffies(timeout_ms)); } -static void amdgpu_userq_init_hang_detect_work(struct amdgpu_usermode_queue *queue) +void amdgpu_userq_process_fence_irq(struct amdgpu_device *adev, u32 doorbell) { - INIT_DELAYED_WORK(&queue->hang_detect_work, amdgpu_userq_hang_detect_work); - queue->hang_detect_fence = NULL; + struct xarray *xa = &adev->userq_doorbell_xa; + struct amdgpu_usermode_queue *queue; + unsigned long flags; + int r; + + xa_lock_irqsave(xa, flags); + queue = xa_load(xa, doorbell); + if (queue) { + r = amdgpu_userq_fence_driver_process(queue->fence_drv); + /* + * We are in interrupt context here, this *can't* wait for + * reset work to finish. + */ + if (r >= 0) + cancel_delayed_work(&queue->hang_detect_work); + + /* Restart the timer when there are still fences pending */ + if (r == 1) + amdgpu_userq_start_hang_detect_work(queue); + } + xa_unlock_irqrestore(xa, flags); } static int amdgpu_userq_buffer_va_list_add(struct amdgpu_usermode_queue *queue, @@ -223,7 +227,7 @@ static int amdgpu_userq_buffer_va_list_add(struct amdgpu_usermode_queue *queue, INIT_LIST_HEAD(&va_cursor->list); va_cursor->gpu_addr = addr; - atomic_set(&va_map->bo_va->userq_va_mapped, 1); + va_map->bo_va->userq_va_mapped = true; list_add(&va_cursor->list, &queue->userq_va_list); return 0; @@ -270,7 +274,7 @@ static bool amdgpu_userq_buffer_va_mapped(struct amdgpu_vm *vm, u64 addr) dma_resv_assert_held(vm->root.bo->tbo.base.resv); mapping = amdgpu_vm_bo_lookup_mapping(vm, addr); - if (!IS_ERR_OR_NULL(mapping) && atomic_read(&mapping->bo_va->userq_va_mapped)) + if (!IS_ERR_OR_NULL(mapping) && mapping->bo_va->userq_va_mapped) r = true; else r = false; @@ -296,16 +300,8 @@ static bool amdgpu_userq_buffer_vas_mapped(struct amdgpu_usermode_queue *queue) return false; } -static void amdgpu_userq_buffer_va_list_del(struct amdgpu_bo_va_mapping *mapping, - struct amdgpu_userq_va_cursor *va_cursor) -{ - atomic_set(&mapping->bo_va->userq_va_mapped, 0); - list_del(&va_cursor->list); - kfree(va_cursor); -} - -static int amdgpu_userq_buffer_vas_list_cleanup(struct amdgpu_device *adev, - struct amdgpu_usermode_queue *queue) +static void amdgpu_userq_buffer_vas_list_cleanup(struct amdgpu_device *adev, + struct amdgpu_usermode_queue *queue) { struct amdgpu_userq_va_cursor *va_cursor, *tmp; struct amdgpu_bo_va_mapping *mapping; @@ -315,15 +311,12 @@ static int amdgpu_userq_buffer_vas_list_cleanup(struct amdgpu_device *adev, list_for_each_entry_safe(va_cursor, tmp, &queue->userq_va_list, list) { mapping = amdgpu_vm_bo_lookup_mapping(queue->vm, va_cursor->gpu_addr); - if (!mapping) { - return -EINVAL; - } - dev_dbg(adev->dev, "delete the userq:%p va:%llx\n", - queue, va_cursor->gpu_addr); - amdgpu_userq_buffer_va_list_del(mapping, va_cursor); + if (mapping) + dev_dbg(adev->dev, "delete the userq:%p va:%llx\n", + queue, va_cursor->gpu_addr); + list_del(&va_cursor->list); + kfree(va_cursor); } - - return 0; } static int amdgpu_userq_preempt_helper(struct amdgpu_usermode_queue *queue) @@ -332,23 +325,18 @@ static int amdgpu_userq_preempt_helper(struct amdgpu_usermode_queue *queue) struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; - bool found_hung_queue = false; - int r = 0; + int r; if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { r = userq_funcs->preempt(queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; - found_hung_queue = true; + return r; } else { queue->state = AMDGPU_USERQ_STATE_PREEMPTED; } } - - if (found_hung_queue) - amdgpu_userq_detect_and_reset_queues(uq_mgr); - - return r; + return 0; } static int amdgpu_userq_restore_helper(struct amdgpu_usermode_queue *queue) @@ -377,24 +365,21 @@ static int amdgpu_userq_unmap_helper(struct amdgpu_usermode_queue *queue) struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; - bool found_hung_queue = false; - int r = 0; + int r; if ((queue->state == AMDGPU_USERQ_STATE_MAPPED) || - (queue->state == AMDGPU_USERQ_STATE_PREEMPTED)) { + (queue->state == AMDGPU_USERQ_STATE_PREEMPTED)) { + r = userq_funcs->unmap(queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; - found_hung_queue = true; + return r; } else { queue->state = AMDGPU_USERQ_STATE_UNMAPPED; } } - if (found_hung_queue) - amdgpu_userq_detect_and_reset_queues(uq_mgr); - - return r; + return 0; } static int amdgpu_userq_map_helper(struct amdgpu_usermode_queue *queue) @@ -403,19 +388,19 @@ static int amdgpu_userq_map_helper(struct amdgpu_usermode_queue *queue) struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; - int r = 0; + int r; if (queue->state == AMDGPU_USERQ_STATE_UNMAPPED) { r = userq_funcs->map(queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; - amdgpu_userq_detect_and_reset_queues(uq_mgr); + return r; } else { queue->state = AMDGPU_USERQ_STATE_MAPPED; } } - return r; + return 0; } static void amdgpu_userq_wait_for_last_fence(struct amdgpu_usermode_queue *queue) @@ -512,16 +497,20 @@ int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr, goto free_obj; } + r = amdgpu_bo_pin(userq_obj->obj, AMDGPU_GEM_DOMAIN_GTT); + if (r) + goto unresv; + r = amdgpu_ttm_alloc_gart(&(userq_obj->obj)->tbo); if (r) { drm_file_err(uq_mgr->file, "Failed to alloc GART for userqueue object (%d)", r); - goto unresv; + goto unpin_bo; } r = amdgpu_bo_kmap(userq_obj->obj, &userq_obj->cpu_ptr); if (r) { drm_file_err(uq_mgr->file, "Failed to map BO for userqueue (%d)", r); - goto unresv; + goto unpin_bo; } userq_obj->gpu_addr = amdgpu_bo_gpu_offset(userq_obj->obj); @@ -529,11 +518,13 @@ int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr, memset(userq_obj->cpu_ptr, 0, size); return 0; +unpin_bo: + amdgpu_bo_unpin(userq_obj->obj); unresv: amdgpu_bo_unreserve(userq_obj->obj); - free_obj: amdgpu_bo_unref(&userq_obj->obj); + return r; } @@ -541,6 +532,7 @@ void amdgpu_userq_destroy_object(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_userq_obj *userq_obj) { amdgpu_bo_kunmap(userq_obj->obj); + amdgpu_bo_unpin(userq_obj->obj); amdgpu_bo_unref(&userq_obj->obj); } @@ -635,20 +627,12 @@ amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_que amdgpu_bo_unreserve(vm->root.bo); mutex_lock(&uq_mgr->userq_mutex); - queue->hang_detect_fence = NULL; amdgpu_userq_wait_for_last_fence(queue); #if defined(CONFIG_DEBUG_FS) debugfs_remove_recursive(queue->debugfs_queue); #endif - amdgpu_userq_detect_and_reset_queues(uq_mgr); r = amdgpu_userq_unmap_helper(queue); - /*TODO: It requires a reset for userq hw unmap error*/ - if (r) { - drm_warn(adev_to_drm(uq_mgr->adev), "trying to destroy a HW mapping userq\n"); - queue->state = AMDGPU_USERQ_STATE_HUNG; - } - atomic_dec(&uq_mgr->userq_count[queue->queue_type]); amdgpu_userq_cleanup(queue); mutex_unlock(&uq_mgr->userq_mutex); @@ -724,14 +708,14 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) const struct amdgpu_userq_funcs *uq_funcs; struct amdgpu_usermode_queue *queue; struct amdgpu_db_info db_info; - bool skip_map_queue; - u32 qid; uint64_t index; - int r = 0; - int priority = - (args->in.flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK) >> - AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT; + int priority; + u32 qid; + int r; + priority = + (args->in.flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK) + >> AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT; r = amdgpu_userq_priority_permit(filp, priority); if (r) return r; @@ -744,40 +728,43 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) uq_funcs = adev->userq_funcs[args->in.ip_type]; if (!uq_funcs) { - drm_file_err(uq_mgr->file, "Usermode queue is not supported for this IP (%u)\n", - args->in.ip_type); r = -EINVAL; goto err_pm_runtime; } queue = kzalloc_obj(struct amdgpu_usermode_queue); if (!queue) { - drm_file_err(uq_mgr->file, "Failed to allocate memory for queue\n"); r = -ENOMEM; goto err_pm_runtime; } + kref_init(&queue->refcount); INIT_LIST_HEAD(&queue->userq_va_list); queue->doorbell_handle = args->in.doorbell_handle; queue->queue_type = args->in.ip_type; queue->vm = &fpriv->vm; queue->priority = priority; - - db_info.queue_type = queue->queue_type; - db_info.doorbell_handle = queue->doorbell_handle; - db_info.db_obj = &queue->db_obj; - db_info.doorbell_offset = args->in.doorbell_offset; - queue->userq_mgr = uq_mgr; + INIT_DELAYED_WORK(&queue->hang_detect_work, + amdgpu_userq_hang_detect_work); - /* Validate the userq virtual address.*/ - r = amdgpu_bo_reserve(fpriv->vm.root.bo, false); + mutex_init(&queue->fence_drv_lock); + xa_init_flags(&queue->fence_drv_xa, XA_FLAGS_ALLOC); + r = amdgpu_userq_fence_driver_alloc(adev, &queue->fence_drv); if (r) goto free_queue; - if (amdgpu_userq_input_va_validate(adev, queue, args->in.queue_va, args->in.queue_size) || - amdgpu_userq_input_va_validate(adev, queue, args->in.rptr_va, AMDGPU_GPU_PAGE_SIZE) || - amdgpu_userq_input_va_validate(adev, queue, args->in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) { + /* Make sure the queue can actually run with those virtual addresses. */ + r = amdgpu_bo_reserve(fpriv->vm.root.bo, false); + if (r) + goto free_fence_drv; + + if (amdgpu_userq_input_va_validate(adev, queue, args->in.queue_va, + args->in.queue_size) || + amdgpu_userq_input_va_validate(adev, queue, args->in.rptr_va, + AMDGPU_GPU_PAGE_SIZE) || + amdgpu_userq_input_va_validate(adev, queue, args->in.wptr_va, + AMDGPU_GPU_PAGE_SIZE)) { r = -EINVAL; amdgpu_bo_unreserve(fpriv->vm.root.bo); goto clean_mapping; @@ -785,6 +772,10 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) amdgpu_bo_unreserve(fpriv->vm.root.bo); /* Convert relative doorbell offset into absolute doorbell index */ + db_info.queue_type = queue->queue_type; + db_info.doorbell_handle = queue->doorbell_handle; + db_info.db_obj = &queue->db_obj; + db_info.doorbell_offset = args->in.doorbell_offset; index = amdgpu_userq_get_doorbell_index(uq_mgr, &db_info, filp); if (index == (uint64_t)-EINVAL) { drm_file_err(uq_mgr->file, "Failed to get doorbell for queue\n"); @@ -793,79 +784,64 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) } queue->doorbell_index = index; - xa_init_flags(&queue->fence_drv_xa, XA_FLAGS_ALLOC); - r = amdgpu_userq_fence_driver_alloc(adev, &queue->fence_drv); - if (r) { - drm_file_err(uq_mgr->file, "Failed to alloc fence driver\n"); - goto clean_mapping; - } - r = uq_funcs->mqd_create(queue, &args->in); if (r) { drm_file_err(uq_mgr->file, "Failed to create Queue\n"); - goto clean_fence_driver; + goto clean_mapping; } + /* Update VM owner at userq submit-time for page-fault attribution. */ + amdgpu_vm_set_task_info(&fpriv->vm); + + r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, + GFP_KERNEL)); + if (r) + goto clean_mqd; + amdgpu_userq_ensure_ev_fence(&fpriv->userq_mgr, &fpriv->evf_mgr); /* don't map the queue if scheduling is halted */ - if (adev->userq_halt_for_enforce_isolation && - ((queue->queue_type == AMDGPU_HW_IP_GFX) || - (queue->queue_type == AMDGPU_HW_IP_COMPUTE))) - skip_map_queue = true; - else - skip_map_queue = false; - if (!skip_map_queue) { + if (!adev->userq_halt_for_enforce_isolation || + ((queue->queue_type != AMDGPU_HW_IP_GFX) && + (queue->queue_type != AMDGPU_HW_IP_COMPUTE))) { r = amdgpu_userq_map_helper(queue); if (r) { drm_file_err(uq_mgr->file, "Failed to map Queue\n"); - goto clean_mqd; + mutex_unlock(&uq_mgr->userq_mutex); + goto clean_doorbell; } } - /* drop this refcount during queue destroy */ - kref_init(&queue->refcount); - - /* Wait for mode-1 reset to complete */ - down_read(&adev->reset_domain->sem); - - r = xa_alloc(&uq_mgr->userq_xa, &qid, queue, - XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), GFP_KERNEL); - if (r) { - if (!skip_map_queue) - amdgpu_userq_unmap_helper(queue); - r = -ENOMEM; - goto clean_reset_domain; - } - - r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL)); - if (r) { - xa_erase(&uq_mgr->userq_xa, qid); - if (!skip_map_queue) - amdgpu_userq_unmap_helper(queue); - goto clean_reset_domain; - } - up_read(&adev->reset_domain->sem); - - amdgpu_debugfs_userq_init(filp, queue, qid); - amdgpu_userq_init_hang_detect_work(queue); - - args->out.queue_id = qid; atomic_inc(&uq_mgr->userq_count[queue->queue_type]); mutex_unlock(&uq_mgr->userq_mutex); + + r = xa_alloc(&uq_mgr->userq_xa, &qid, queue, + XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), + GFP_KERNEL); + if (r) { + /* + * This drops the last reference which should take care of + * all cleanup. + */ + amdgpu_userq_put(queue); + return r; + } + + amdgpu_debugfs_userq_init(filp, queue, qid); + args->out.queue_id = qid; return 0; -clean_reset_domain: - up_read(&adev->reset_domain->sem); +clean_doorbell: + xa_erase_irq(&adev->userq_doorbell_xa, index); clean_mqd: - mutex_unlock(&uq_mgr->userq_mutex); uq_funcs->mqd_destroy(queue); -clean_fence_driver: - amdgpu_userq_fence_driver_free(queue); clean_mapping: amdgpu_bo_reserve(fpriv->vm.root.bo, true); amdgpu_userq_buffer_vas_list_cleanup(adev, queue); amdgpu_bo_unreserve(fpriv->vm.root.bo); + mutex_destroy(&queue->fence_drv_lock); +free_fence_drv: + amdgpu_userq_fence_driver_free(queue); free_queue: kfree(queue); err_pm_runtime: @@ -1052,12 +1028,12 @@ amdgpu_userq_bo_validate(struct amdgpu_device *adev, struct drm_exec *exec, struct amdgpu_bo *bo; int ret; - spin_lock(&vm->status_lock); - while (!list_empty(&vm->invalidated)) { - bo_va = list_first_entry(&vm->invalidated, + spin_lock(&vm->individual_lock); + while (!list_empty(&vm->always_valid.evicted)) { + bo_va = list_first_entry(&vm->always_valid.evicted, struct amdgpu_bo_va, base.vm_status); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->individual_lock); bo = bo_va->base.bo; ret = drm_exec_prepare_obj(exec, &bo->tbo.base, 2); @@ -1069,14 +1045,14 @@ amdgpu_userq_bo_validate(struct amdgpu_device *adev, struct drm_exec *exec, if (ret) return ret; - /* This moves the bo_va to the done list */ + /* This moves the bo_va to the idle list */ ret = amdgpu_vm_bo_update(adev, bo_va, false); if (ret) return ret; - spin_lock(&vm->status_lock); + spin_lock(&vm->individual_lock); } - spin_unlock(&vm->status_lock); + spin_unlock(&vm->individual_lock); return 0; } @@ -1108,7 +1084,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) if (unlikely(ret)) goto unlock_all; - ret = amdgpu_vm_lock_done_list(vm, &exec, 1); + ret = amdgpu_vm_lock_individual(vm, &exec, 1); drm_exec_retry_on_contention(&exec); if (unlikely(ret)) goto unlock_all; @@ -1151,7 +1127,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) key = 0; /* Validate User Ptr BOs */ - list_for_each_entry(bo_va, &vm->done, base.vm_status) { + list_for_each_entry(bo_va, &vm->always_valid.idle, base.vm_status) { bo = bo_va->base.bo; if (!bo) continue; @@ -1187,7 +1163,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) bo = range->bo; ret = amdgpu_ttm_tt_get_user_pages(bo, range); if (ret) - goto unlock_all; + goto free_ranges; } invalidated = true; @@ -1201,10 +1177,10 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) /* * We need to wait for all VM updates to finish before restarting the - * queues. Using the done list like that is now ok since everything is + * queues. Using the idle list like that is now ok since everything is * locked in place. */ - list_for_each_entry(bo_va, &vm->done, base.vm_status) + list_for_each_entry(bo_va, &vm->always_valid.idle, base.vm_status) dma_fence_wait(bo_va->last_pt_update, false); dma_fence_wait(vm->last_update, false); @@ -1214,6 +1190,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) unlock_all: drm_exec_fini(&exec); +free_ranges: xa_for_each(&xa, tmp_key, range) { if (!range) continue; @@ -1254,7 +1231,6 @@ amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) unsigned long queue_id; int ret = 0, r; - amdgpu_userq_detect_and_reset_queues(uq_mgr); /* Try to unmap all the queues in this process ctx */ xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { r = amdgpu_userq_preempt_helper(queue); @@ -1262,29 +1238,16 @@ amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) ret = r; } - if (ret) + if (ret) { drm_file_err(uq_mgr->file, "Couldn't unmap all the queues, eviction failed ret=%d\n", ret); + amdgpu_reset_domain_schedule(uq_mgr->adev->reset_domain, + &uq_mgr->reset_work); + flush_work(&uq_mgr->reset_work); + } return ret; } -void amdgpu_userq_reset_work(struct work_struct *work) -{ - struct amdgpu_device *adev = container_of(work, struct amdgpu_device, - userq_reset_work); - struct amdgpu_reset_context reset_context; - - memset(&reset_context, 0, sizeof(reset_context)); - - reset_context.method = AMD_RESET_METHOD_NONE; - reset_context.reset_req_dev = adev; - reset_context.src = AMDGPU_RESET_SRC_USERQ; - set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); - /*set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags);*/ - - amdgpu_device_gpu_recover(adev, NULL, &reset_context); -} - static void amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) { @@ -1318,9 +1281,24 @@ int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *f userq_mgr->file = file_priv; INIT_DELAYED_WORK(&userq_mgr->resume_work, amdgpu_userq_restore_worker); + INIT_WORK(&userq_mgr->reset_work, amdgpu_userq_mgr_reset_work); return 0; } +void amdgpu_userq_mgr_cancel_reset_work(struct amdgpu_device *adev) +{ + struct xarray *xa = &adev->userq_doorbell_xa; + struct amdgpu_usermode_queue *queue; + unsigned long flags, queue_id; + + xa_lock_irqsave(xa, flags); + xa_for_each(xa, queue_id, queue) { + cancel_delayed_work(&queue->hang_detect_work); + cancel_work(&queue->userq_mgr->reset_work); + } + xa_unlock_irqrestore(xa, flags); +} + void amdgpu_userq_mgr_cancel_resume(struct amdgpu_userq_mgr *userq_mgr) { cancel_delayed_work_sync(&userq_mgr->resume_work); @@ -1346,6 +1324,14 @@ void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr) } xa_destroy(&userq_mgr->userq_xa); + + /* + * Drain any in-flight reset_work. By this point all queues are freed + * and userq_count is 0, so if reset_work starts now it exits early. + * We still need to wait in case it was already executing gpu_recover. + */ + cancel_work_sync(&userq_mgr->reset_work); + mutex_destroy(&userq_mgr->userq_mutex); } @@ -1364,7 +1350,6 @@ int amdgpu_userq_suspend(struct amdgpu_device *adev) uqm = queue->userq_mgr; cancel_delayed_work_sync(&uqm->resume_work); guard(mutex)(&uqm->userq_mutex); - amdgpu_userq_detect_and_reset_queues(uqm); if (adev->in_s0ix) r = amdgpu_userq_preempt_helper(queue); else @@ -1423,7 +1408,6 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, if (((queue->queue_type == AMDGPU_HW_IP_GFX) || (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && (queue->xcp_id == idx)) { - amdgpu_userq_detect_and_reset_queues(uqm); r = amdgpu_userq_preempt_helper(queue); if (r) ret = r; @@ -1496,23 +1480,21 @@ void amdgpu_userq_pre_reset(struct amdgpu_device *adev) { const struct amdgpu_userq_funcs *userq_funcs; struct amdgpu_usermode_queue *queue; - struct amdgpu_userq_mgr *uqm; unsigned long queue_id; + /* TODO: We probably need a new lock for the queue state */ xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { - uqm = queue->userq_mgr; - cancel_delayed_work_sync(&uqm->resume_work); - if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { - amdgpu_userq_wait_for_last_fence(queue); - userq_funcs = adev->userq_funcs[queue->queue_type]; - userq_funcs->unmap(queue); - /* just mark all queues as hung at this point. - * if unmap succeeds, we could map again - * in amdgpu_userq_post_reset() if vram is not lost - */ - queue->state = AMDGPU_USERQ_STATE_HUNG; - amdgpu_userq_fence_driver_force_completion(queue); - } + if (queue->state != AMDGPU_USERQ_STATE_MAPPED) + continue; + + userq_funcs = adev->userq_funcs[queue->queue_type]; + userq_funcs->unmap(queue); + /* just mark all queues as hung at this point. + * if unmap succeeds, we could map again + * in amdgpu_userq_post_reset() if vram is not lost + */ + queue->state = AMDGPU_USERQ_STATE_HUNG; + amdgpu_userq_fence_driver_force_completion(queue); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 675fe6395ac8..49b33e2d6932 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -66,14 +66,31 @@ struct amdgpu_usermode_queue { struct amdgpu_userq_obj db_obj; struct amdgpu_userq_obj fw_obj; struct amdgpu_userq_obj wptr_obj; + + /** + * @fence_drv_lock: Protecting @fence_drv_xa. + */ + struct mutex fence_drv_lock; + + /** + * @fence_drv_xa: + * + * References to the external fence drivers returned by wait_ioctl. + * Dropped on the next signaled dma_fence or queue destruction. + */ struct xarray fence_drv_xa; struct amdgpu_userq_fence_driver *fence_drv; struct dma_fence *last_fence; u32 xcp_id; int priority; struct dentry *debugfs_queue; - struct delayed_work hang_detect_work; - struct dma_fence *hang_detect_fence; + + /** + * @hang_detect_work: + * + * Delayed work which runs when userq_fences time out. + */ + struct delayed_work hang_detect_work; struct kref refcount; struct list_head userq_va_list; @@ -105,6 +122,13 @@ struct amdgpu_userq_mgr { struct amdgpu_device *adev; struct delayed_work resume_work; struct drm_file *file; + + /** + * @reset_work: + * + * Reset work which is used when eviction fails. + */ + struct work_struct reset_work; atomic_t userq_count[AMDGPU_RING_TYPE_MAX]; }; @@ -123,6 +147,7 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv, struct amdgpu_device *adev); +void amdgpu_userq_mgr_cancel_reset_work(struct amdgpu_device *adev); void amdgpu_userq_mgr_cancel_resume(struct amdgpu_userq_mgr *userq_mgr); void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr); @@ -156,6 +181,7 @@ void amdgpu_userq_reset_work(struct work_struct *work); void amdgpu_userq_pre_reset(struct amdgpu_device *adev); int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost); void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue); +void amdgpu_userq_process_fence_irq(struct amdgpu_device *adev, u32 doorbell); int amdgpu_userq_input_va_validate(struct amdgpu_device *adev, struct amdgpu_usermode_queue *queue, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index da39ac862f37..a41fb72dba94 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -32,29 +32,9 @@ #include "amdgpu.h" #include "amdgpu_userq_fence.h" -static const struct dma_fence_ops amdgpu_userq_fence_ops; -static struct kmem_cache *amdgpu_userq_fence_slab; - #define AMDGPU_USERQ_MAX_HANDLES (1U << 16) -int amdgpu_userq_fence_slab_init(void) -{ - amdgpu_userq_fence_slab = kmem_cache_create("amdgpu_userq_fence", - sizeof(struct amdgpu_userq_fence), - 0, - SLAB_HWCACHE_ALIGN, - NULL); - if (!amdgpu_userq_fence_slab) - return -ENOMEM; - - return 0; -} - -void amdgpu_userq_fence_slab_fini(void) -{ - rcu_barrier(); - kmem_cache_destroy(amdgpu_userq_fence_slab); -} +static const struct dma_fence_ops amdgpu_userq_fence_ops; static inline struct amdgpu_userq_fence *to_amdgpu_userq_fence(struct dma_fence *f) { @@ -141,6 +121,7 @@ amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq) userq->last_fence = NULL; amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_xa); xa_destroy(&userq->fence_drv_xa); + mutex_destroy(&userq->fence_drv_lock); /* Drop the queue's ownership reference to fence_drv explicitly */ amdgpu_userq_fence_driver_put(userq->fence_drv); } @@ -154,7 +135,14 @@ amdgpu_userq_fence_put_fence_drv_array(struct amdgpu_userq_fence *userq_fence) userq_fence->fence_drv_array_count = 0; } -void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv) +/* + * Returns: + * -ENOENT when no fences were processes + * 1 when more fences are pending + * 0 when no fences are pending any more + */ +int +amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv) { struct amdgpu_userq_fence *userq_fence, *tmp; LIST_HEAD(to_be_signaled); @@ -162,9 +150,6 @@ void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_d unsigned long flags; u64 rptr; - if (!fence_drv) - return; - spin_lock_irqsave(&fence_drv->fence_list_lock, flags); rptr = amdgpu_userq_fence_read(fence_drv); @@ -177,6 +162,9 @@ void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_d &userq_fence->link); spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); + if (list_empty(&to_be_signaled)) + return -ENOENT; + list_for_each_entry_safe(userq_fence, tmp, &to_be_signaled, link) { fence = &userq_fence->base; list_del_init(&userq_fence->link); @@ -188,6 +176,8 @@ void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_d dma_fence_put(fence); } + /* That doesn't need to be accurate so no locking */ + return list_empty(&fence_drv->fences) ? 0 : 1; } void amdgpu_userq_fence_driver_destroy(struct kref *ref) @@ -229,80 +219,84 @@ void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv) kref_put(&fence_drv->refcount, amdgpu_userq_fence_driver_destroy); } -static int amdgpu_userq_fence_alloc(struct amdgpu_userq_fence **userq_fence) +static int amdgpu_userq_fence_alloc(struct amdgpu_usermode_queue *userq, + struct amdgpu_userq_fence **pfence) { - *userq_fence = kmem_cache_alloc(amdgpu_userq_fence_slab, GFP_ATOMIC); - return *userq_fence ? 0 : -ENOMEM; + struct amdgpu_userq_fence_driver *fence_drv = userq->fence_drv; + struct amdgpu_userq_fence *userq_fence; + void *entry; + + userq_fence = kmalloc(sizeof(*userq_fence), GFP_KERNEL); + if (!userq_fence) + return -ENOMEM; + + /* + * Get the next unused entry, since we fill from the start this can be + * used as size to allocate the array. + */ + mutex_lock(&userq->fence_drv_lock); + XA_STATE(xas, &userq->fence_drv_xa, 0); + + rcu_read_lock(); + do { + entry = xas_find_marked(&xas, ULONG_MAX, XA_FREE_MARK); + } while (xas_retry(&xas, entry)); + rcu_read_unlock(); + + userq_fence->fence_drv_array = kvmalloc_array(xas.xa_index, + sizeof(fence_drv), + GFP_KERNEL); + if (!userq_fence->fence_drv_array) { + mutex_unlock(&userq->fence_drv_lock); + kfree(userq_fence); + return -ENOMEM; + } + + userq_fence->fence_drv_array_count = xas.xa_index; + xa_extract(&userq->fence_drv_xa, (void **)userq_fence->fence_drv_array, + 0, ULONG_MAX, xas.xa_index, XA_PRESENT); + xa_destroy(&userq->fence_drv_xa); + + mutex_unlock(&userq->fence_drv_lock); + + amdgpu_userq_fence_driver_get(fence_drv); + userq_fence->fence_drv = fence_drv; + + *pfence = userq_fence; + return 0; } -static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, - struct amdgpu_userq_fence *userq_fence, - u64 seq, struct dma_fence **f) +static void amdgpu_userq_fence_init(struct amdgpu_usermode_queue *userq, + struct amdgpu_userq_fence *fence, + u64 seq) { - struct amdgpu_userq_fence_driver *fence_drv; - struct dma_fence *fence; + struct amdgpu_userq_fence_driver *fence_drv = userq->fence_drv; unsigned long flags; bool signaled = false; - fence_drv = userq->fence_drv; - if (!fence_drv) - return -EINVAL; - - spin_lock_init(&userq_fence->lock); - INIT_LIST_HEAD(&userq_fence->link); - fence = &userq_fence->base; - userq_fence->fence_drv = fence_drv; - - dma_fence_init64(fence, &amdgpu_userq_fence_ops, &userq_fence->lock, + spin_lock_init(&fence->lock); + dma_fence_init64(&fence->base, &amdgpu_userq_fence_ops, &fence->lock, fence_drv->context, seq); - amdgpu_userq_fence_driver_get(fence_drv); - dma_fence_get(fence); + /* Make sure the fence is visible to the hang detect worker */ + dma_fence_put(userq->last_fence); + userq->last_fence = dma_fence_get(&fence->base); - if (!xa_empty(&userq->fence_drv_xa)) { - struct amdgpu_userq_fence_driver *stored_fence_drv; - unsigned long index, count = 0; - int i = 0; - - xa_lock(&userq->fence_drv_xa); - xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) - count++; - - userq_fence->fence_drv_array = - kvmalloc_objs(struct amdgpu_userq_fence_driver *, count, - GFP_ATOMIC); - - if (userq_fence->fence_drv_array) { - xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) { - userq_fence->fence_drv_array[i] = stored_fence_drv; - __xa_erase(&userq->fence_drv_xa, index); - i++; - } - } - - userq_fence->fence_drv_array_count = i; - xa_unlock(&userq->fence_drv_xa); - } else { - userq_fence->fence_drv_array = NULL; - userq_fence->fence_drv_array_count = 0; - } - - /* Check if hardware has already processed the job */ + /* Check if hardware has already processed the fence */ spin_lock_irqsave(&fence_drv->fence_list_lock, flags); - if (!dma_fence_is_signaled(fence)) { - list_add_tail(&userq_fence->link, &fence_drv->fences); + if (!dma_fence_is_signaled(&fence->base)) { + dma_fence_get(&fence->base); + list_add_tail(&fence->link, &fence_drv->fences); } else { + INIT_LIST_HEAD(&fence->link); signaled = true; - dma_fence_put(fence); } spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); if (signaled) - amdgpu_userq_fence_put_fence_drv_array(userq_fence); - - *f = fence; - - return 0; + amdgpu_userq_fence_put_fence_drv_array(fence); + else + amdgpu_userq_start_hang_detect_work(userq); } static const char *amdgpu_userq_fence_get_driver_name(struct dma_fence *f) @@ -342,7 +336,7 @@ static void amdgpu_userq_fence_free(struct rcu_head *rcu) amdgpu_userq_fence_driver_put(fence_drv); kvfree(userq_fence->fence_drv_array); - kmem_cache_free(amdgpu_userq_fence_slab, userq_fence); + kfree(userq_fence); } static void amdgpu_userq_fence_release(struct dma_fence *f) @@ -376,56 +370,48 @@ static int amdgpu_userq_fence_read_wptr(struct amdgpu_device *adev, { struct amdgpu_bo_va_mapping *mapping; struct amdgpu_bo *bo; + struct drm_exec exec; u64 addr, *ptr; - int r; - - r = amdgpu_bo_reserve(queue->vm->root.bo, false); - if (r) - return r; + int ret; addr = queue->userq_prop->wptr_gpu_addr; addr &= AMDGPU_GMC_HOLE_MASK; - mapping = amdgpu_vm_bo_lookup_mapping(queue->vm, addr >> PAGE_SHIFT); - if (!mapping) { - amdgpu_bo_unreserve(queue->vm->root.bo); - DRM_ERROR("Failed to lookup amdgpu_bo_va_mapping\n"); - return -EINVAL; + drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 2); + drm_exec_until_all_locked(&exec) { + ret = amdgpu_vm_lock_pd(queue->vm, &exec, 1); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto lock_error; + + mapping = amdgpu_vm_bo_lookup_mapping(queue->vm, addr >> PAGE_SHIFT); + if (!mapping) { + ret = -EINVAL; + goto lock_error; + } + + ret = drm_exec_lock_obj(&exec, &mapping->bo_va->base.bo->tbo.base); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto lock_error; } - bo = amdgpu_bo_ref(mapping->bo_va->base.bo); - amdgpu_bo_unreserve(queue->vm->root.bo); - r = amdgpu_bo_reserve(bo, true); - if (r) { - amdgpu_bo_unref(&bo); - DRM_ERROR("Failed to reserve userqueue wptr bo"); - return r; - } - - r = amdgpu_bo_kmap(bo, (void **)&ptr); - if (r) { + bo = mapping->bo_va->base.bo; + ret = amdgpu_bo_kmap(bo, (void **)&ptr); + if (ret) { DRM_ERROR("Failed mapping the userqueue wptr bo"); - goto map_error; + goto lock_error; } *wptr = le64_to_cpu(*ptr); amdgpu_bo_kunmap(bo); - amdgpu_bo_unreserve(bo); - amdgpu_bo_unref(&bo); - + drm_exec_fini(&exec); return 0; -map_error: - amdgpu_bo_unreserve(bo); - amdgpu_bo_unref(&bo); - - return r; -} - -static void amdgpu_userq_fence_cleanup(struct dma_fence *fence) -{ - dma_fence_put(fence); +lock_error: + drm_exec_fini(&exec); + return ret; } static void @@ -471,13 +457,14 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, const unsigned int num_read_bo_handles = args->num_bo_read_handles; struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; + struct drm_gem_object **gobj_write, **gobj_read; u32 *syncobj_handles, num_syncobj_handles; - struct amdgpu_userq_fence *userq_fence; - struct amdgpu_usermode_queue *queue = NULL; - struct drm_syncobj **syncobj = NULL; - struct dma_fence *fence; + struct amdgpu_usermode_queue *queue; + struct amdgpu_userq_fence *fence; + struct drm_syncobj **syncobj; struct drm_exec exec; + void __user *ptr; int r, i, entry; u64 wptr; @@ -489,13 +476,14 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, return -EINVAL; num_syncobj_handles = args->num_syncobj_handles; - syncobj_handles = memdup_array_user(u64_to_user_ptr(args->syncobj_handles), - num_syncobj_handles, sizeof(u32)); + ptr = u64_to_user_ptr(args->syncobj_handles); + syncobj_handles = memdup_array_user(ptr, num_syncobj_handles, + sizeof(u32)); if (IS_ERR(syncobj_handles)) return PTR_ERR(syncobj_handles); - /* Array of pointers to the looked up syncobjs */ - syncobj = kmalloc_array(num_syncobj_handles, sizeof(*syncobj), GFP_KERNEL); + syncobj = kmalloc_array(num_syncobj_handles, sizeof(*syncobj), + GFP_KERNEL); if (!syncobj) { r = -ENOMEM; goto free_syncobj_handles; @@ -509,21 +497,17 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, } } - r = drm_gem_objects_lookup(filp, - u64_to_user_ptr(args->bo_read_handles), - num_read_bo_handles, - &gobj_read); + ptr = u64_to_user_ptr(args->bo_read_handles); + r = drm_gem_objects_lookup(filp, ptr, num_read_bo_handles, &gobj_read); if (r) goto free_syncobj; - r = drm_gem_objects_lookup(filp, - u64_to_user_ptr(args->bo_write_handles), - num_write_bo_handles, + ptr = u64_to_user_ptr(args->bo_write_handles); + r = drm_gem_objects_lookup(filp, ptr, num_write_bo_handles, &gobj_write); if (r) goto put_gobj_read; - /* Retrieve the user queue */ queue = amdgpu_userq_get(userq_mgr, args->queue_id); if (!queue) { r = -ENOENT; @@ -532,73 +516,61 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, r = amdgpu_userq_fence_read_wptr(adev, queue, &wptr); if (r) - goto put_gobj_write; + goto put_queue; - r = amdgpu_userq_fence_alloc(&userq_fence); + r = amdgpu_userq_fence_alloc(queue, &fence); if (r) - goto put_gobj_write; + goto put_queue; /* We are here means UQ is active, make sure the eviction fence is valid */ amdgpu_userq_ensure_ev_fence(&fpriv->userq_mgr, &fpriv->evf_mgr); - /* Create a new fence */ - r = amdgpu_userq_fence_create(queue, userq_fence, wptr, &fence); - if (r) { - mutex_unlock(&userq_mgr->userq_mutex); - kmem_cache_free(amdgpu_userq_fence_slab, userq_fence); - goto put_gobj_write; - } + /* Create the new fence */ + amdgpu_userq_fence_init(queue, fence, wptr); - dma_fence_put(queue->last_fence); - queue->last_fence = dma_fence_get(fence); - amdgpu_userq_start_hang_detect_work(queue); mutex_unlock(&userq_mgr->userq_mutex); + /* + * This needs to come after the fence is created since + * amdgpu_userq_ensure_ev_fence() can't be called while holding the resv + * locks. + */ drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, (num_read_bo_handles + num_write_bo_handles)); - /* Lock all BOs with retry handling */ drm_exec_until_all_locked(&exec) { - r = drm_exec_prepare_array(&exec, gobj_read, num_read_bo_handles, 1); + r = drm_exec_prepare_array(&exec, gobj_read, + num_read_bo_handles, 1); drm_exec_retry_on_contention(&exec); - if (r) { - amdgpu_userq_fence_cleanup(fence); + if (r) goto exec_fini; - } - r = drm_exec_prepare_array(&exec, gobj_write, num_write_bo_handles, 1); + r = drm_exec_prepare_array(&exec, gobj_write, + num_write_bo_handles, 1); drm_exec_retry_on_contention(&exec); - if (r) { - amdgpu_userq_fence_cleanup(fence); + if (r) goto exec_fini; - } } - for (i = 0; i < num_read_bo_handles; i++) { - if (!gobj_read || !gobj_read[i]->resv) - continue; - - dma_resv_add_fence(gobj_read[i]->resv, fence, + /* And publish the new fence in the BOs and syncobj */ + for (i = 0; i < num_read_bo_handles; i++) + dma_resv_add_fence(gobj_read[i]->resv, &fence->base, DMA_RESV_USAGE_READ); - } - for (i = 0; i < num_write_bo_handles; i++) { - if (!gobj_write || !gobj_write[i]->resv) - continue; - - dma_resv_add_fence(gobj_write[i]->resv, fence, + for (i = 0; i < num_write_bo_handles; i++) + dma_resv_add_fence(gobj_write[i]->resv, &fence->base, DMA_RESV_USAGE_WRITE); - } - /* Add the created fence to syncobj/BO's */ for (i = 0; i < num_syncobj_handles; i++) - drm_syncobj_replace_fence(syncobj[i], fence); - - /* drop the reference acquired in fence creation function */ - dma_fence_put(fence); + drm_syncobj_replace_fence(syncobj[i], &fence->base); exec_fini: + /* drop the reference acquired in fence creation function */ + dma_fence_put(&fence->base); + drm_exec_fini(&exec); +put_queue: + amdgpu_userq_put(queue); put_gobj_write: for (i = 0; i < num_write_bo_handles; i++) drm_gem_object_put(gobj_write[i]); @@ -609,15 +581,11 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, kvfree(gobj_read); free_syncobj: while (entry-- > 0) - if (syncobj[entry]) - drm_syncobj_put(syncobj[entry]); + drm_syncobj_put(syncobj[entry]); kfree(syncobj); free_syncobj_handles: kfree(syncobj_handles); - if (queue) - amdgpu_userq_put(queue); - return r; } @@ -892,8 +860,10 @@ amdgpu_userq_wait_return_fence_info(struct drm_file *filp, * Otherwise, we would gather those references until we don't * have any more space left and crash. */ + mutex_lock(&waitq->fence_drv_lock); r = xa_alloc(&waitq->fence_drv_xa, &index, fence_drv, xa_limit_32b, GFP_KERNEL); + mutex_unlock(&waitq->fence_drv_lock); if (r) goto put_waitq; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h index d56246ad8c26..0bd51616cef1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h @@ -58,15 +58,12 @@ struct amdgpu_userq_fence_driver { char timeline_name[TASK_COMM_LEN]; }; -int amdgpu_userq_fence_slab_init(void); -void amdgpu_userq_fence_slab_fini(void); - void amdgpu_userq_fence_driver_get(struct amdgpu_userq_fence_driver *fence_drv); void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv); int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, struct amdgpu_userq_fence_driver **fence_drv_req); void amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq); -void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv); +int amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv); void amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq); void amdgpu_userq_fence_driver_destroy(struct kref *ref); int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 9d5cca7da1d9..3a3bc0d370fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -512,7 +512,7 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev) } memset_io(ptr, 0, size); /* to restore uvd fence seq */ - amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); + amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring, NULL); } } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index debb82a2e031..616967519869 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -1486,18 +1486,27 @@ int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block, } /** - * amdgpu_vcn_reset_engine - Reset a specific VCN engine - * @adev: Pointer to the AMDGPU device - * @instance_id: VCN engine instance to reset + * amdgpu_vcn_ring_reset - Reset a VCN ring + * @ring: ring to reset + * @vmid: vmid of guilty job + * @timedout_fence: fence of timed out job * + * This helper is for VCN blocks without unified queues because + * resetting the engine resets all queues in that case. With + * unified queues we have one queue per engine. * Returns: 0 on success, or a negative error code on failure. */ -static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev, - uint32_t instance_id) +int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence) { - struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[instance_id]; + struct amdgpu_device *adev = ring->adev; + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; int r, i; + if (adev->vcn.inst[ring->me].using_unified_queue) + return -EINVAL; + mutex_lock(&vinst->engine_reset_mutex); /* Stop the scheduler's work queue for the dec and enc rings if they are running. * This ensures that no new tasks are submitted to the queues while @@ -1519,9 +1528,13 @@ static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev, if (r) goto unlock; } - amdgpu_fence_driver_force_completion(&vinst->ring_dec); + amdgpu_fence_driver_force_completion(&vinst->ring_dec, + (&vinst->ring_dec == ring) ? + &timedout_fence->base : NULL); for (i = 0; i < vinst->num_enc_rings; i++) - amdgpu_fence_driver_force_completion(&vinst->ring_enc[i]); + amdgpu_fence_driver_force_completion(&vinst->ring_enc[i], + (&vinst->ring_enc[i] == ring) ? + &timedout_fence->base : NULL); /* Restart the scheduler's work queue for the dec and enc rings * if they were stopped by this function. This allows new tasks @@ -1537,29 +1550,6 @@ static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev, return r; } -/** - * amdgpu_vcn_ring_reset - Reset a VCN ring - * @ring: ring to reset - * @vmid: vmid of guilty job - * @timedout_fence: fence of timed out job - * - * This helper is for VCN blocks without unified queues because - * resetting the engine resets all queues in that case. With - * unified queues we have one queue per engine. - * Returns: 0 on success, or a negative error code on failure. - */ -int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, - unsigned int vmid, - struct amdgpu_fence *timedout_fence) -{ - struct amdgpu_device *adev = ring->adev; - - if (adev->vcn.inst[ring->me].using_unified_queue) - return -EINVAL; - - return amdgpu_vcn_reset_engine(adev, ring->me); -} - int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, const struct amdgpu_hwip_reg_entry *reg, u32 count) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index e8d180a412d1..3fcbd722ee3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -463,6 +463,9 @@ static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) { struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; + struct amdgim_pf2vf_info_v1 *pf2vf_v1; + struct amd_sriov_msg_pf2vf_info *pf2vf; + uint32_t checksum; uint32_t checkval; @@ -479,7 +482,8 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) switch (pf2vf_info->version) { case 1: - checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; + pf2vf_v1 = (struct amdgim_pf2vf_info_v1 *)pf2vf_info; + checksum = pf2vf_v1->checksum; checkval = amd_sriov_msg_checksum( adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, adev->virt.fw_reserve.checksum_key, checksum); @@ -490,12 +494,12 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) return -EINVAL; } - adev->virt.gim_feature = - ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; + adev->virt.gim_feature = pf2vf_v1->feature_flags; break; case 2: /* TODO: missing key, need to add it later */ - checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; + pf2vf = (struct amd_sriov_msg_pf2vf_info *)pf2vf_info; + checksum = pf2vf->checksum; checkval = amd_sriov_msg_checksum( adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 0, checksum); @@ -507,11 +511,9 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) } adev->virt.vf2pf_update_interval_ms = - ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; - adev->virt.gim_feature = - ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; - adev->virt.reg_access = - ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; + pf2vf->vf2pf_update_interval_ms; + adev->virt.gim_feature = pf2vf->feature_flags.all; + adev->virt.reg_access = pf2vf->reg_access_flags.all; adev->virt.decode_max_dimension_pixels = 0; adev->virt.decode_max_frame_pixels = 0; @@ -519,26 +521,30 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) adev->virt.encode_max_frame_pixels = 0; adev->virt.is_mm_bw_enabled = false; for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { - tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; + tmp = pf2vf->mm_bw_management[i].decode_max_dimension_pixels; adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); - tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; + tmp = pf2vf->mm_bw_management[i].decode_max_frame_pixels; adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); - tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; + tmp = pf2vf->mm_bw_management[i].encode_max_dimension_pixels; adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); - tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; + tmp = pf2vf->mm_bw_management[i].encode_max_frame_pixels; adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); } if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) adev->virt.is_mm_bw_enabled = true; - adev->unique_id = - ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; - adev->virt.ras_en_caps.all = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_en_caps.all; + adev->unique_id = pf2vf->uuid; + + adev->unitid = 0; + if (amdgpu_sriov_is_unitid_support(adev)) + adev->unitid = pf2vf->unitid; + + adev->virt.ras_en_caps.all = pf2vf->ras_en_caps.all; adev->virt.ras_telemetry_en_caps.all = - ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_telemetry_en_caps.all; + pf2vf->ras_telemetry_en_caps.all; break; default: dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 9da0c6e9b869..d563deec0916 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -163,6 +163,8 @@ enum AMDGIM_FEATURE_FLAG { AMDGIM_FEATURE_RAS_CPER = (1 << 11), AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12), AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU = (1 << 13), + AMDGIM_FEATURE_PTL_SUPPORT = (1 << 14), + AMDGIM_FEATURE_UNITID_SUPPORT = (1 << 15), }; enum AMDGIM_REG_ACCESS_FLAG { @@ -441,6 +443,8 @@ static inline bool is_virtual_machine(void) ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) #define amdgpu_sriov_is_mes_info_enable(adev) \ ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE) +#define amdgpu_sriov_is_unitid_support(adev) \ + ((adev)->virt.gim_feature & AMDGIM_FEATURE_UNITID_SUPPORT) #define amdgpu_virt_xgmi_migrate_enabled(adev) \ ((adev)->virt.is_xgmi_node_migrate_enabled && (adev)->gmc.xgmi.node_segment_size != 0) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index e54295b56282..170adaf7e76a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "amdgpu.h" #ifdef CONFIG_DRM_AMDGPU_SI @@ -42,81 +43,6 @@ static const u32 amdgpu_vkms_formats[] = { DRM_FORMAT_XRGB8888, }; -static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) -{ - struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer); - struct drm_crtc *crtc = &amdgpu_crtc->base; - struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); - u64 ret_overrun; - bool ret; - - ret_overrun = hrtimer_forward_now(&amdgpu_crtc->vblank_timer, - output->period_ns); - if (ret_overrun != 1) - drm_warn(amdgpu_crtc->base.dev, - "%s: vblank timer overrun count: %llu\n", - __func__, ret_overrun); - - ret = drm_crtc_handle_vblank(crtc); - /* Don't queue timer again when vblank is disabled. */ - if (!ret) - return HRTIMER_NORESTART; - - return HRTIMER_RESTART; -} - -static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc) -{ - struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); - struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - - drm_calc_timestamping_constants(crtc, &crtc->mode); - - out->period_ns = ktime_set(0, vblank->framedur_ns); - hrtimer_start(&amdgpu_crtc->vblank_timer, out->period_ns, HRTIMER_MODE_REL); - - return 0; -} - -static void amdgpu_vkms_disable_vblank(struct drm_crtc *crtc) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - - hrtimer_try_to_cancel(&amdgpu_crtc->vblank_timer); -} - -static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, - int *max_error, - ktime_t *vblank_time, - bool in_vblank_irq) -{ - struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); - struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - - if (!READ_ONCE(vblank->enabled)) { - *vblank_time = ktime_get(); - return true; - } - - *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); - - if (WARN_ON(*vblank_time == vblank->time)) - return true; - - /* - * To prevent races we roll the hrtimer forward before we do any - * interrupt processing - this is how real hw works (the interrupt is - * only generated after all the vblank registers are updated) and what - * the vblank core expects. Therefore we need to always correct the - * timestampe by one frame. - */ - *vblank_time -= output->period_ns; - - return true; -} - static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { .set_config = drm_atomic_helper_set_config, .destroy = drm_crtc_cleanup, @@ -124,45 +50,11 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { .reset = drm_atomic_helper_crtc_reset, .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, - .enable_vblank = amdgpu_vkms_enable_vblank, - .disable_vblank = amdgpu_vkms_disable_vblank, - .get_vblank_timestamp = amdgpu_vkms_get_vblank_timestamp, + DRM_CRTC_VBLANK_TIMER_FUNCS, }; -static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - drm_crtc_vblank_on(crtc); -} - -static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - drm_crtc_vblank_off(crtc); -} - -static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) -{ - unsigned long flags; - if (crtc->state->event) { - spin_lock_irqsave(&crtc->dev->event_lock, flags); - - if (drm_crtc_vblank_get(crtc) != 0) - drm_crtc_send_vblank_event(crtc, crtc->state->event); - else - drm_crtc_arm_vblank_event(crtc, crtc->state->event); - - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - - crtc->state->event = NULL; - } -} - static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { - .atomic_flush = amdgpu_vkms_crtc_atomic_flush, - .atomic_enable = amdgpu_vkms_crtc_atomic_enable, - .atomic_disable = amdgpu_vkms_crtc_atomic_disable, + DRM_CRTC_HELPER_VBLANK_FUNCS, }; static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, @@ -187,10 +79,6 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; - amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; - - hrtimer_setup(&amdgpu_crtc->vblank_timer, &amdgpu_vkms_vblank_simulate, CLOCK_MONOTONIC, - HRTIMER_MODE_REL); return ret; } @@ -262,13 +150,13 @@ static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = { }; static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { return; } static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -538,11 +426,6 @@ static int amdgpu_vkms_sw_init(struct amdgpu_ip_block *ip_block) static int amdgpu_vkms_sw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - int i = 0; - - for (i = 0; i < adev->mode_info.num_crtc; i++) - if (adev->mode_info.crtcs[i]) - hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer); drm_kms_helper_poll_fini(adev_to_drm(adev)); drm_mode_config_cleanup(adev_to_drm(adev)); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 115a7b269af3..a99d01f9dc75 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -138,6 +138,47 @@ static void amdgpu_vm_assert_locked(struct amdgpu_vm *vm) dma_resv_assert_held(vm->root.bo->tbo.base.resv); } +/* Initialize the amdgpu_vm_bo_status object */ +static void amdgpu_vm_bo_status_init(struct amdgpu_vm_bo_status *lists) +{ + INIT_LIST_HEAD(&lists->evicted); + INIT_LIST_HEAD(&lists->moved); + INIT_LIST_HEAD(&lists->idle); +} + +/* + * Make sure we have the lock to modify the vm_bo status and return the object + * with the status lists. + */ +static struct amdgpu_vm_bo_status * +amdgpu_vm_bo_lock_lists(struct amdgpu_vm_bo_base *vm_bo) +{ + struct amdgpu_vm *vm = vm_bo->vm; + struct amdgpu_bo *bo = vm_bo->bo; + + if (amdgpu_vm_is_bo_always_valid(vm, bo)) { + /* No extra locking needed, protected by the root PD resv lock */ + amdgpu_vm_assert_locked(vm); + + if (bo->tbo.type == ttm_bo_type_kernel) + return &vm->kernel; + + return &vm->always_valid; + } + + spin_lock(&vm_bo->vm->individual_lock); + return &vm->individual; +} + +/* Eventually unlock the status list lock again */ +static void amdgpu_vm_bo_unlock_lists(struct amdgpu_vm_bo_base *vm_bo) +{ + if (amdgpu_vm_is_bo_always_valid(vm_bo->vm, vm_bo->bo)) + amdgpu_vm_assert_locked(vm_bo->vm); + else + spin_unlock(&vm_bo->vm->individual_lock); +} + /** * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid * @@ -157,37 +198,44 @@ bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo) * * @vm_bo: vm_bo which is evicted * - * State for PDs/PTs and per VM BOs which are not at the location they should - * be. + * State for vm_bo objects meaning the underlying BO was evicted and need to + * move in place again. */ static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) { - struct amdgpu_vm *vm = vm_bo->vm; - struct amdgpu_bo *bo = vm_bo->bo; + struct amdgpu_vm_bo_status *lists; + lists = amdgpu_vm_bo_lock_lists(vm_bo); vm_bo->moved = true; - amdgpu_vm_assert_locked(vm); - spin_lock(&vm_bo->vm->status_lock); - if (bo->tbo.type == ttm_bo_type_kernel) - list_move(&vm_bo->vm_status, &vm->evicted); - else - list_move_tail(&vm_bo->vm_status, &vm->evicted); - spin_unlock(&vm_bo->vm->status_lock); + list_move(&vm_bo->vm_status, &lists->evicted); + amdgpu_vm_bo_unlock_lists(vm_bo); } /** * amdgpu_vm_bo_moved - vm_bo is moved * * @vm_bo: vm_bo which is moved * - * State for per VM BOs which are moved, but that change is not yet reflected - * in the page tables. + * State for vm_bo objects meaning the underlying BO was moved but the new + * location not yet reflected in the page tables. */ static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) { - amdgpu_vm_assert_locked(vm_bo->vm); - spin_lock(&vm_bo->vm->status_lock); - list_move(&vm_bo->vm_status, &vm_bo->vm->moved); - spin_unlock(&vm_bo->vm->status_lock); + struct amdgpu_vm_bo_status *lists; + struct amdgpu_bo *bo = vm_bo->bo; + + /* + * The root PD doesn't have a parent PDE and goes directly into the + * idle state. + */ + lists = amdgpu_vm_bo_lock_lists(vm_bo); + if (bo && bo->tbo.type == ttm_bo_type_kernel && !bo->parent) { + vm_bo->moved = false; + list_move(&vm_bo->vm_status, &lists->idle); + } else { + vm_bo->moved = true; + list_move(&vm_bo->vm_status, &lists->moved); + } + amdgpu_vm_bo_unlock_lists(vm_bo); } /** @@ -195,120 +243,43 @@ static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) * * @vm_bo: vm_bo which is now idle * - * State for PDs/PTs and per VM BOs which have gone through the state machine - * and are now idle. + * State for vm_bo objects meaning we are done with the state machine and no + * further action is necessary. */ static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) { - amdgpu_vm_assert_locked(vm_bo->vm); - spin_lock(&vm_bo->vm->status_lock); - list_move(&vm_bo->vm_status, &vm_bo->vm->idle); - spin_unlock(&vm_bo->vm->status_lock); - vm_bo->moved = false; -} + struct amdgpu_vm_bo_status *lists; -/** - * amdgpu_vm_bo_invalidated - vm_bo is invalidated - * - * @vm_bo: vm_bo which is now invalidated - * - * State for normal BOs which are invalidated and that change not yet reflected - * in the PTs. - */ -static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) -{ - spin_lock(&vm_bo->vm->status_lock); - list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated); - spin_unlock(&vm_bo->vm->status_lock); -} - -/** - * amdgpu_vm_bo_evicted_user - vm_bo is evicted - * - * @vm_bo: vm_bo which is evicted - * - * State for BOs used by user mode queues which are not at the location they - * should be. - */ -static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo) -{ - vm_bo->moved = true; - spin_lock(&vm_bo->vm->status_lock); - list_move(&vm_bo->vm_status, &vm_bo->vm->evicted_user); - spin_unlock(&vm_bo->vm->status_lock); -} - -/** - * amdgpu_vm_bo_relocated - vm_bo is reloacted - * - * @vm_bo: vm_bo which is relocated - * - * State for PDs/PTs which needs to update their parent PD. - * For the root PD, just move to idle state. - */ -static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) -{ - amdgpu_vm_assert_locked(vm_bo->vm); - if (vm_bo->bo->parent) { - spin_lock(&vm_bo->vm->status_lock); - list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); - spin_unlock(&vm_bo->vm->status_lock); - } else { - amdgpu_vm_bo_idle(vm_bo); - } -} - -/** - * amdgpu_vm_bo_done - vm_bo is done - * - * @vm_bo: vm_bo which is now done - * - * State for normal BOs which are invalidated and that change has been updated - * in the PTs. - */ -static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) -{ - amdgpu_vm_assert_locked(vm_bo->vm); - spin_lock(&vm_bo->vm->status_lock); - list_move(&vm_bo->vm_status, &vm_bo->vm->done); - spin_unlock(&vm_bo->vm->status_lock); + lists = amdgpu_vm_bo_lock_lists(vm_bo); + if (!amdgpu_vm_is_bo_always_valid(vm_bo->vm, vm_bo->bo)) + vm_bo->moved = false; + list_move(&vm_bo->vm_status, &lists->idle); + amdgpu_vm_bo_unlock_lists(vm_bo); } /** * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine * @vm: the VM which state machine to reset * - * Move all vm_bo object in the VM into a state where they will be updated - * again during validation. + * Move all vm_bo object in the VM into a state where their location will be + * updated in the page tables again. */ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm) { - struct amdgpu_vm_bo_base *vm_bo, *tmp; - amdgpu_vm_assert_locked(vm); + list_splice_init(&vm->kernel.idle, &vm->kernel.moved); + list_splice_init(&vm->always_valid.idle, &vm->always_valid.moved); - spin_lock(&vm->status_lock); - list_splice_init(&vm->done, &vm->invalidated); - list_for_each_entry(vm_bo, &vm->invalidated, vm_status) - vm_bo->moved = true; - - list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) { - struct amdgpu_bo *bo = vm_bo->bo; - - vm_bo->moved = true; - if (!bo || bo->tbo.type != ttm_bo_type_kernel) - list_move(&vm_bo->vm_status, &vm_bo->vm->moved); - else if (bo->parent) - list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); - } - spin_unlock(&vm->status_lock); + spin_lock(&vm->individual_lock); + list_splice_init(&vm->individual.idle, &vm->individual.moved); + spin_unlock(&vm->individual_lock); } /** * amdgpu_vm_update_shared - helper to update shared memory stat * @base: base structure for tracking BO usage in a VM * - * Takes the vm status_lock and updates the shared memory stat. If the basic + * Takes the vm stats_lock and updates the shared memory stat. If the basic * stat changed (e.g. buffer was moved) amdgpu_vm_update_stats need to be called * as well. */ @@ -321,7 +292,7 @@ static void amdgpu_vm_update_shared(struct amdgpu_vm_bo_base *base) bool shared; dma_resv_assert_held(bo->tbo.base.resv); - spin_lock(&vm->status_lock); + spin_lock(&vm->stats_lock); shared = drm_gem_object_is_shared_for_memory_stats(&bo->tbo.base); if (base->shared != shared) { base->shared = shared; @@ -333,7 +304,7 @@ static void amdgpu_vm_update_shared(struct amdgpu_vm_bo_base *base) vm->stats[bo_memtype].drm.private += size; } } - spin_unlock(&vm->status_lock); + spin_unlock(&vm->stats_lock); } /** @@ -358,11 +329,11 @@ void amdgpu_vm_bo_update_shared(struct amdgpu_bo *bo) * be bo->tbo.resource * @sign: if we should add (+1) or subtract (-1) from the stat * - * Caller need to have the vm status_lock held. Useful for when multiple update + * Caller need to have the vm stats_lock held. Useful for when multiple update * need to happen at the same time. */ static void amdgpu_vm_update_stats_locked(struct amdgpu_vm_bo_base *base, - struct ttm_resource *res, int sign) + struct ttm_resource *res, int sign) { struct amdgpu_vm *vm = base->vm; struct amdgpu_bo *bo = base->bo; @@ -386,7 +357,8 @@ static void amdgpu_vm_update_stats_locked(struct amdgpu_vm_bo_base *base, */ if (bo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) vm->stats[res_memtype].drm.purgeable += size; - if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(res_memtype))) + if (!(bo->preferred_domains & + amdgpu_mem_type_to_domain(res_memtype))) vm->stats[bo_memtype].evicted += size; } } @@ -405,9 +377,9 @@ void amdgpu_vm_update_stats(struct amdgpu_vm_bo_base *base, { struct amdgpu_vm *vm = base->vm; - spin_lock(&vm->status_lock); + spin_lock(&vm->stats_lock); amdgpu_vm_update_stats_locked(base, res, sign); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->stats_lock); } /** @@ -428,37 +400,34 @@ void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, base->next = NULL; INIT_LIST_HEAD(&base->vm_status); + dma_resv_assert_held(vm->root.bo->tbo.base.resv); if (!bo) return; + base->next = bo->vm_bo; bo->vm_bo = base; - spin_lock(&vm->status_lock); + spin_lock(&vm->stats_lock); base->shared = drm_gem_object_is_shared_for_memory_stats(&bo->tbo.base); amdgpu_vm_update_stats_locked(base, bo->tbo.resource, +1); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->stats_lock); - if (!amdgpu_vm_is_bo_always_valid(vm, bo)) + if (!amdgpu_vm_is_bo_always_valid(vm, bo)) { + amdgpu_vm_bo_idle(base); return; - - dma_resv_assert_held(vm->root.bo->tbo.base.resv); + } ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move); - if (bo->tbo.type == ttm_bo_type_kernel && bo->parent) - amdgpu_vm_bo_relocated(base); - else - amdgpu_vm_bo_idle(base); - - if (bo->preferred_domains & - amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type)) - return; /* - * we checked all the prerequisites, but it looks like this per vm bo - * is currently evicted. add the bo to the evicted list to make sure it - * is validated on next vm use to avoid fault. - * */ - amdgpu_vm_bo_evicted(base); + * When a per VM isn't in the desired domain put it into the evicted + * state to make sure that it gets validated on the next best occasion. + */ + if (bo->preferred_domains & + amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type)) + amdgpu_vm_bo_moved(base); + else + amdgpu_vm_bo_evicted(base); } /** @@ -479,41 +448,41 @@ int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, } /** - * amdgpu_vm_lock_done_list - lock all BOs on the done list + * amdgpu_vm_lock_individual - lock all BOs on the individual idle list * @vm: vm providing the BOs * @exec: drm execution context * @num_fences: number of extra fences to reserve * - * Lock the BOs on the done list in the DRM execution context. + * Lock the BOs on the individual idle list in the DRM execution context. */ -int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec, - unsigned int num_fences) +int amdgpu_vm_lock_individual(struct amdgpu_vm *vm, struct drm_exec *exec, + unsigned int num_fences) { - struct list_head *prev = &vm->done; + struct list_head *prev = &vm->individual.idle; struct amdgpu_bo_va *bo_va; struct amdgpu_bo *bo; int ret; /* We can only trust prev->next while holding the lock */ - spin_lock(&vm->status_lock); - while (!list_is_head(prev->next, &vm->done)) { + spin_lock(&vm->individual_lock); + while (!list_is_head(prev->next, &vm->individual.idle)) { bo_va = list_entry(prev->next, typeof(*bo_va), base.vm_status); bo = bo_va->base.bo; if (bo) { amdgpu_bo_ref(bo); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->individual_lock); ret = drm_exec_prepare_obj(exec, &bo->tbo.base, 1); amdgpu_bo_unref(&bo); if (unlikely(ret)) return ret; - spin_lock(&vm->status_lock); + spin_lock(&vm->individual_lock); } prev = prev->next; } - spin_unlock(&vm->status_lock); + spin_unlock(&vm->individual_lock); return 0; } @@ -609,10 +578,10 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, void *param) { uint64_t new_vm_generation = amdgpu_vm_generation(adev, vm); - struct amdgpu_vm_bo_base *bo_base; - struct amdgpu_bo *bo; + struct amdgpu_vm_bo_base *bo_base, *tmp; int r; + dma_resv_assert_held(vm->root.bo->tbo.base.resv); if (vm->generation != new_vm_generation) { vm->generation = new_vm_generation; amdgpu_vm_bo_reset_state_machine(vm); @@ -622,50 +591,60 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, return r; } - spin_lock(&vm->status_lock); - while (!list_empty(&vm->evicted)) { - bo_base = list_first_entry(&vm->evicted, - struct amdgpu_vm_bo_base, - vm_status); - spin_unlock(&vm->status_lock); - - bo = bo_base->bo; - - r = validate(param, bo); + list_for_each_entry_safe(bo_base, tmp, &vm->kernel.evicted, vm_status) { + r = validate(param, bo_base->bo); if (r) return r; - if (bo->tbo.type != ttm_bo_type_kernel) { - amdgpu_vm_bo_moved(bo_base); - } else { - vm->update_funcs->map_table(to_amdgpu_bo_vm(bo)); - amdgpu_vm_bo_relocated(bo_base); - } - spin_lock(&vm->status_lock); + vm->update_funcs->map_table(to_amdgpu_bo_vm(bo_base->bo)); + amdgpu_vm_bo_moved(bo_base); } - while (ticket && !list_empty(&vm->evicted_user)) { - bo_base = list_first_entry(&vm->evicted_user, - struct amdgpu_vm_bo_base, - vm_status); - spin_unlock(&vm->status_lock); - - bo = bo_base->bo; - dma_resv_assert_held(bo->tbo.base.resv); - - r = validate(param, bo); - if (r) - return r; - - amdgpu_vm_bo_invalidated(bo_base); - - spin_lock(&vm->status_lock); - } - spin_unlock(&vm->status_lock); + /* + * As soon as all page tables are in place we can start updating them + * again. + */ amdgpu_vm_eviction_lock(vm); vm->evicting = false; amdgpu_vm_eviction_unlock(vm); + list_for_each_entry_safe(bo_base, tmp, &vm->always_valid.evicted, + vm_status) { + r = validate(param, bo_base->bo); + if (r) + return r; + + amdgpu_vm_bo_moved(bo_base); + } + + if (!ticket) + return 0; + + spin_lock(&vm->individual_lock); +restart: + list_for_each_entry(bo_base, &vm->individual.evicted, vm_status) { + struct amdgpu_bo *bo = bo_base->bo; + + if (dma_resv_locking_ctx(bo->tbo.base.resv) != ticket) + continue; + + spin_unlock(&vm->individual_lock); + + r = validate(param, bo); + if (r) + return r; + + amdgpu_vm_bo_moved(bo_base); + + /* It's a bit inefficient to always jump back to the start, but + * we would need to re-structure the KFD for properly fixing + * that. + */ + spin_lock(&vm->individual_lock); + goto restart; + } + spin_unlock(&vm->individual_lock); + return 0; } @@ -689,9 +668,7 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm) ret = !vm->evicting; amdgpu_vm_eviction_unlock(vm); - spin_lock(&vm->status_lock); - ret &= list_empty(&vm->evicted); - spin_unlock(&vm->status_lock); + ret &= list_empty(&vm->kernel.evicted); spin_lock(&vm->immediate.lock); ret &= !vm->immediate.stopped; @@ -985,18 +962,13 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, struct amdgpu_vm *vm, bool immediate) { struct amdgpu_vm_update_params params; - struct amdgpu_vm_bo_base *entry; + struct amdgpu_vm_bo_base *entry, *tmp; bool flush_tlb_needed = false; - LIST_HEAD(relocated); int r, idx; amdgpu_vm_assert_locked(vm); - spin_lock(&vm->status_lock); - list_splice_init(&vm->relocated, &relocated); - spin_unlock(&vm->status_lock); - - if (list_empty(&relocated)) + if (list_empty(&vm->kernel.moved)) return 0; if (!drm_dev_enter(adev_to_drm(adev), &idx)) @@ -1012,7 +984,7 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, if (r) goto error; - list_for_each_entry(entry, &relocated, vm_status) { + list_for_each_entry(entry, &vm->kernel.moved, vm_status) { /* vm_flush_needed after updating moved PDEs */ flush_tlb_needed |= entry->moved; @@ -1028,11 +1000,8 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, if (flush_tlb_needed) atomic64_inc(&vm->tlb_seq); - while (!list_empty(&relocated)) { - entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base, - vm_status); + list_for_each_entry_safe(entry, tmp, &vm->kernel.moved, vm_status) amdgpu_vm_bo_idle(entry); - } error: drm_dev_exit(idx); @@ -1163,7 +1132,7 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, params.pages_addr = pages_addr; params.unlocked = unlocked; params.needs_flush = flush_tlb; - params.allow_override = allow_override; + params.override_pte = allow_override && adev->gmc.override_pte; INIT_LIST_HEAD(¶ms.tlb_flush_waitlist); amdgpu_vm_eviction_lock(vm); @@ -1260,9 +1229,9 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, void amdgpu_vm_get_memory(struct amdgpu_vm *vm, struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]) { - spin_lock(&vm->status_lock); + spin_lock(&vm->stats_lock); memcpy(stats, vm->stats, sizeof(*stats) * __AMDGPU_PL_NUM); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->stats_lock); } /** @@ -1406,7 +1375,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, else amdgpu_vm_bo_idle(&bo_va->base); } else { - amdgpu_vm_bo_done(&bo_va->base); + amdgpu_vm_bo_idle(&bo_va->base); } list_splice_init(&bo_va->invalids, &bo_va->valids); @@ -1629,29 +1598,25 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) { - struct amdgpu_bo_va *bo_va; + struct amdgpu_bo_va *bo_va, *tmp; struct dma_resv *resv; bool clear, unlock; int r; - spin_lock(&vm->status_lock); - while (!list_empty(&vm->moved)) { - bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va, - base.vm_status); - spin_unlock(&vm->status_lock); - + list_for_each_entry_safe(bo_va, tmp, &vm->always_valid.moved, + base.vm_status) { /* Per VM BOs never need to bo cleared in the page tables */ r = amdgpu_vm_bo_update(adev, bo_va, false); if (r) return r; - spin_lock(&vm->status_lock); } - while (!list_empty(&vm->invalidated)) { - bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, - base.vm_status); + spin_lock(&vm->individual_lock); + while (!list_empty(&vm->individual.moved)) { + bo_va = list_first_entry(&vm->individual.moved, + typeof(*bo_va), base.vm_status); resv = bo_va->base.bo->tbo.base.resv; - spin_unlock(&vm->status_lock); + spin_unlock(&vm->individual_lock); /* Try to reserve the BO to avoid clearing its ptes */ if (!adev->debug_vm && dma_resv_trylock(resv)) { @@ -1681,11 +1646,11 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, drm_gem_is_imported(&bo_va->base.bo->tbo.base) && (!bo_va->base.bo->tbo.resource || bo_va->base.bo->tbo.resource->mem_type == TTM_PL_SYSTEM)) - amdgpu_vm_bo_evicted_user(&bo_va->base); + amdgpu_vm_bo_evicted(&bo_va->base); - spin_lock(&vm->status_lock); + spin_lock(&vm->individual_lock); } - spin_unlock(&vm->status_lock); + spin_unlock(&vm->individual_lock); return 0; } @@ -2002,7 +1967,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, * during user requests GEM unmap IOCTL except for forcing the unmap * from user space. */ - if (unlikely(atomic_read(&bo_va->userq_va_mapped) > 0)) + if (unlikely(bo_va->userq_va_mapped)) amdgpu_userq_gem_va_unmap_validate(adev, mapping, saddr); list_del(&mapping->list); @@ -2223,9 +2188,9 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev, } } - spin_lock(&vm->status_lock); + spin_lock(&vm->individual_lock); list_del(&bo_va->base.vm_status); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->individual_lock); list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { list_del(&mapping->list); @@ -2305,14 +2270,7 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_bo *bo, bool evicted) if (bo_base->moved) continue; - bo_base->moved = true; - - if (bo->tbo.type == ttm_bo_type_kernel) - amdgpu_vm_bo_relocated(bo_base); - else if (amdgpu_vm_is_bo_always_valid(vm, bo)) - amdgpu_vm_bo_moved(bo_base); - else - amdgpu_vm_bo_invalidated(bo_base); + amdgpu_vm_bo_moved(bo_base); } } @@ -2333,10 +2291,10 @@ void amdgpu_vm_bo_move(struct amdgpu_bo *bo, struct ttm_resource *new_mem, for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - spin_lock(&vm->status_lock); + spin_lock(&vm->stats_lock); amdgpu_vm_update_stats_locked(bo_base, bo->tbo.resource, -1); amdgpu_vm_update_stats_locked(bo_base, new_mem, +1); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->stats_lock); } amdgpu_vm_bo_invalidate(bo, evicted); @@ -2600,16 +2558,14 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, vm->va = RB_ROOT_CACHED; for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) vm->reserved_vmid[i] = NULL; - INIT_LIST_HEAD(&vm->evicted); - INIT_LIST_HEAD(&vm->evicted_user); - INIT_LIST_HEAD(&vm->relocated); - INIT_LIST_HEAD(&vm->moved); - INIT_LIST_HEAD(&vm->idle); - INIT_LIST_HEAD(&vm->invalidated); - spin_lock_init(&vm->status_lock); + + amdgpu_vm_bo_status_init(&vm->kernel); + amdgpu_vm_bo_status_init(&vm->always_valid); + spin_lock_init(&vm->individual_lock); + amdgpu_vm_bo_status_init(&vm->individual); INIT_LIST_HEAD(&vm->freed); - INIT_LIST_HEAD(&vm->done); INIT_KFIFO(vm->faults); + spin_lock_init(&vm->stats_lock); r = amdgpu_vm_init_entities(adev, vm); if (r) @@ -3023,11 +2979,22 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, is_compute_context = vm->is_compute_context; - if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid, - node_id, addr >> PAGE_SHIFT, ts, write_fault)) { + if (is_compute_context) { + /* Unreserve root since svm_range_restore_pages might try to reserve it. */ + /* TODO: rework svm_range_restore_pages so that this isn't necessary. */ amdgpu_bo_unreserve(root); + + if (!svm_range_restore_pages(adev, pasid, vmid, + node_id, addr >> PAGE_SHIFT, ts, write_fault)) { + amdgpu_bo_unref(&root); + return true; + } amdgpu_bo_unref(&root); - return true; + + /* Re-acquire the VM lock, could be that the VM was freed in between. */ + vm = amdgpu_vm_lock_by_pasid(adev, &root, pasid); + if (!vm) + return false; } addr /= AMDGPU_GPU_PAGE_SIZE; @@ -3075,6 +3042,42 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, } #if defined(CONFIG_DEBUG_FS) + +/* print the debug info for a specific set of status lists */ +static void amdgpu_debugfs_vm_bo_status_info(struct seq_file *m, + struct amdgpu_vm_bo_status *lists) +{ + struct amdgpu_vm_bo_base *base; + unsigned int id; + + id = 0; + seq_puts(m, "\tEvicted BOs:\n"); + list_for_each_entry(base, &lists->evicted, vm_status) { + if (!base->bo) + continue; + + amdgpu_bo_print_info(id++, base->bo, m); + } + + id = 0; + seq_puts(m, "\tMoved BOs:\n"); + list_for_each_entry(base, &lists->moved, vm_status) { + if (!base->bo) + continue; + + amdgpu_bo_print_info(id++, base->bo, m); + } + + id = 0; + seq_puts(m, "\tIdle BOs:\n"); + list_for_each_entry(base, &lists->moved, vm_status) { + if (!base->bo) + continue; + + amdgpu_bo_print_info(id++, base->bo, m); + } +} + /** * amdgpu_debugfs_vm_bo_info - print BO info for the VM * @@ -3085,90 +3088,18 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, */ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) { - struct amdgpu_bo_va *bo_va, *tmp; - u64 total_idle = 0; - u64 total_evicted = 0; - u64 total_relocated = 0; - u64 total_moved = 0; - u64 total_invalidated = 0; - u64 total_done = 0; - unsigned int total_idle_objs = 0; - unsigned int total_evicted_objs = 0; - unsigned int total_relocated_objs = 0; - unsigned int total_moved_objs = 0; - unsigned int total_invalidated_objs = 0; - unsigned int total_done_objs = 0; - unsigned int id = 0; - amdgpu_vm_assert_locked(vm); - spin_lock(&vm->status_lock); - seq_puts(m, "\tIdle BOs:\n"); - list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) { - if (!bo_va->base.bo) - continue; - total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m); - } - total_idle_objs = id; - id = 0; + seq_puts(m, "\tKernel PT/PDs:\n"); + amdgpu_debugfs_vm_bo_status_info(m, &vm->kernel); - seq_puts(m, "\tEvicted BOs:\n"); - list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) { - if (!bo_va->base.bo) - continue; - total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m); - } - total_evicted_objs = id; - id = 0; + seq_puts(m, "\tPer VM BOs:\n"); + amdgpu_debugfs_vm_bo_status_info(m, &vm->always_valid); - seq_puts(m, "\tRelocated BOs:\n"); - list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) { - if (!bo_va->base.bo) - continue; - total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m); - } - total_relocated_objs = id; - id = 0; - - seq_puts(m, "\tMoved BOs:\n"); - list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { - if (!bo_va->base.bo) - continue; - total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m); - } - total_moved_objs = id; - id = 0; - - seq_puts(m, "\tInvalidated BOs:\n"); - list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) { - if (!bo_va->base.bo) - continue; - total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m); - } - total_invalidated_objs = id; - id = 0; - - seq_puts(m, "\tDone BOs:\n"); - list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) { - if (!bo_va->base.bo) - continue; - total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m); - } - spin_unlock(&vm->status_lock); - total_done_objs = id; - - seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle, - total_idle_objs); - seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted, - total_evicted_objs); - seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated, - total_relocated_objs); - seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved, - total_moved_objs); - seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated, - total_invalidated_objs); - seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done, - total_done_objs); + seq_puts(m, "\tIndividual BOs:\n"); + spin_lock(&vm->individual_lock); + amdgpu_debugfs_vm_bo_status_info(m, &vm->individual); + spin_unlock(&vm->individual_lock); } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index d083d7aab75c..3695299f1a03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -205,17 +205,34 @@ struct amdgpu_vm_bo_base { /* protected by bo being reserved */ struct amdgpu_vm_bo_base *next; - /* protected by vm status_lock */ + /* protected by vm reservation and invalidated_lock */ struct list_head vm_status; /* if the bo is counted as shared in mem stats - * protected by vm status_lock */ + * protected by vm BO being reserved */ bool shared; /* protected by the BO being reserved */ bool moved; }; +/* + * The following status lists contain amdgpu_vm_bo_base objects for + * either PD/PTs, per VM BOs or BOs with individual resv object. + * + * The state transits are: evicted -> moved -> idle + */ +struct amdgpu_vm_bo_status { + /* BOs evicted which need to move into place again */ + struct list_head evicted; + + /* BOs which moved but new location hasn't been updated in the PDs/PTs */ + struct list_head moved; + + /* BOs done with the state machine and need no further action */ + struct list_head idle; +}; + /* provided by hw blocks that can write ptes, e.g., sdma */ struct amdgpu_vm_pte_funcs { /* number of dw to reserve per operation */ @@ -296,10 +313,10 @@ struct amdgpu_vm_update_params { bool needs_flush; /** - * @allow_override: true for memory that is not uncached: allows MTYPE - * to be overridden for NUMA local memory. + * @override_pte: true for memory that is not uncached and gmc override function is + * implemented to allow MTYPE to be overridden for NUMA local memory. */ - bool allow_override; + bool override_pte; /** * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush @@ -345,47 +362,29 @@ struct amdgpu_vm { bool evicting; unsigned int saved_flags; - /* Lock to protect vm_bo add/del/move on all lists of vm */ - spinlock_t status_lock; - - /* Memory statistics for this vm, protected by status_lock */ + /* Memory statistics for this vm, protected by stats_lock */ + spinlock_t stats_lock; struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]; + /* BO's belonging to PD/PT which are internal to the kernel. */ + struct amdgpu_vm_bo_status kernel; + /* - * The following lists contain amdgpu_vm_bo_base objects for either - * PDs, PTs or per VM BOs. The state transits are: - * - * evicted -> relocated (PDs, PTs) or moved (per VM BOs) -> idle + * BOs allocated by userspace where the dma_resv is shared with the + * root PD */ - - /* Per-VM and PT BOs who needs a validation */ - struct list_head evicted; - - /* PT BOs which relocated and their parent need an update */ - struct list_head relocated; - - /* per VM BOs moved, but not yet updated in the PT */ - struct list_head moved; - - /* All BOs of this VM not currently in the state machine */ - struct list_head idle; + struct amdgpu_vm_bo_status always_valid; /* * The following lists contain amdgpu_vm_bo_base objects for BOs which - * have their own dma_resv object and not depend on the root PD. Their - * state transits are: + * have their own dma_resv object and not depend on the root PD. * - * evicted_user or invalidated -> done + * Lists are protected by the individual_lock. */ + spinlock_t individual_lock; - /* BOs for user mode queues that need a validation */ - struct list_head evicted_user; - - /* regular invalidated BOs, but not yet updated in the PT */ - struct list_head invalidated; - - /* BOs which are invalidated, has been updated in the PTs */ - struct list_head done; + /* Userspace BOs with individual resv object */ + struct amdgpu_vm_bo_status individual; /* * This list contains amdgpu_bo_va_mapping objects which have been freed @@ -507,8 +506,8 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, unsigned int num_fences); -int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec, - unsigned int num_fences); +int amdgpu_vm_lock_individual(struct amdgpu_vm *vm, struct drm_exec *exec, + unsigned int num_fences); bool amdgpu_vm_ready(struct amdgpu_vm *vm); uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index f078db3fef79..b31ff6f56f0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -88,12 +88,21 @@ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p, trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate); + if (!p->pages_addr && p->override_pte) + amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, addr, &flags); + for (i = 0; i < count; i++) { + u64 oflags = flags; + value = p->pages_addr ? amdgpu_vm_map_gart(p->pages_addr, addr) : addr; + + if (p->pages_addr && p->override_pte) + amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, value, &oflags); + amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe, - i, value, flags); + i, value, oflags); addr += incr; } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index a930f1522f96..e43a60d09808 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -544,9 +544,7 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry) entry->bo->vm_bo = NULL; ttm_bo_set_bulk_move(&entry->bo->tbo, NULL); - spin_lock(&entry->vm->status_lock); list_del(&entry->vm_status); - spin_unlock(&entry->vm->status_lock); amdgpu_bo_unref(&entry->bo); } @@ -590,7 +588,6 @@ static void amdgpu_vm_pt_add_list(struct amdgpu_vm_update_params *params, struct amdgpu_vm_pt_cursor seek; struct amdgpu_vm_bo_base *entry; - spin_lock(¶ms->vm->status_lock); for_each_amdgpu_vm_pt_dfs_safe(params->adev, params->vm, cursor, seek, entry) { if (entry && entry->bo) list_move(&entry->vm_status, ¶ms->tlb_flush_waitlist); @@ -598,7 +595,6 @@ static void amdgpu_vm_pt_add_list(struct amdgpu_vm_update_params *params, /* enter start node now */ list_move(&cursor->entry->vm_status, ¶ms->tlb_flush_waitlist); - spin_unlock(¶ms->vm->status_lock); } /** @@ -710,15 +706,6 @@ static void amdgpu_vm_pte_update_flags(struct amdgpu_vm_update_params *params, if (level == AMDGPU_VM_PTB) amdgpu_vm_pte_update_noretry_flags(adev, &flags); - /* APUs mapping system memory may need different MTYPEs on different - * NUMA nodes. Only do this for contiguous ranges that can be assumed - * to be on the same NUMA node. - */ - if ((flags & AMDGPU_PTE_SYSTEM) && (adev->flags & AMD_IS_APU) && - adev->gmc.gmc_funcs->override_vm_pte_flags && - num_possible_nodes() > 1 && !params->pages_addr && params->allow_override) - amdgpu_gmc_override_vm_pte_flags(adev, params->vm, addr, &flags); - params->vm->update_funcs->update(params, pt, pe, addr, count, incr, flags); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 36805dcfa159..fd09a2b5a147 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -106,13 +106,13 @@ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p, static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, struct dma_fence **fence) { + struct drm_gpu_scheduler *sched = + container_of(p->vm->delayed.rq, typeof(*sched), rq); + struct amdgpu_ring *ring = + container_of(sched, struct amdgpu_ring, sched); struct amdgpu_ib *ib = p->job->ibs; - struct amdgpu_ring *ring; struct dma_fence *f; - ring = container_of(p->vm->delayed.rq->sched, struct amdgpu_ring, - sched); - WARN_ON(ib->length_dw == 0); amdgpu_ring_pad_ib(ring, ib); @@ -257,6 +257,9 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, } if (!p->pages_addr) { + if (p->override_pte) + amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, addr, &flags); + /* set page commands needed */ amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count, incr, flags); @@ -275,8 +278,14 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, p->num_dw_left -= nptes * 2; pte = (uint64_t *)&(p->job->ibs->ptr[p->num_dw_left]); for (i = 0; i < nptes; ++i, addr += incr) { + u64 oflags = flags; + pte[i] = amdgpu_vm_map_gart(p->pages_addr, addr); - pte[i] |= flags; + + if (p->override_pte) + amdgpu_gmc_override_vm_pte_flags(p->adev, p->vm, pte[i], &oflags); + + pte[i] |= oflags; } amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index fd881388d612..601420491477 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -29,6 +29,7 @@ #include "amdgpu_smu.h" #include "soc15_common.h" #include "vpe_v6_1.h" +#include "vpe_v2_0.h" #define AMDGPU_CSA_VPE_SIZE 64 /* VPE CSA resides in the 4th page of CSA */ @@ -310,6 +311,9 @@ static int vpe_early_init(struct amdgpu_ip_block *ip_block) vpe_v6_1_set_funcs(vpe); vpe->collaborate_mode = true; break; + case IP_VERSION(2, 0, 0): + vpe_v2_0_set_funcs(vpe); + break; default: return -EINVAL; } @@ -562,6 +566,11 @@ static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, amdgpu_ring_write(ring, 0); } + /* WA: Force sync after TRAP to avoid VPE1 fail to power off */ + if (ring->adev->vpe.collaborate_mode) { + amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COLLAB_SYNC, 0)); + amdgpu_ring_write(ring, 0xabcd); + } } static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring) @@ -968,7 +977,7 @@ static const struct amdgpu_ring_funcs vpe_ring_funcs = { .emit_frame_size = 5 + /* vpe_ring_init_cond_exec */ 6 + /* vpe_ring_emit_pipeline_sync */ - 10 + 10 + 10 + /* vpe_ring_emit_fence */ + 12 + 12 + 12 + /* vpe_ring_emit_fence */ /* vpe_ring_emit_vm_flush */ SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6, @@ -1009,6 +1018,19 @@ const struct amd_ip_funcs vpe_ip_funcs = { .set_powergating_state = vpe_set_powergating_state, }; +const struct amd_ip_funcs vpe2_ip_funcs = { + .name = "vpe_v2_0", + .early_init = vpe_early_init, + .sw_init = vpe_sw_init, + .sw_fini = vpe_sw_fini, + .hw_init = vpe_hw_init, + .hw_fini = vpe_hw_fini, + .suspend = vpe_suspend, + .resume = vpe_resume, + .set_clockgating_state = vpe_set_clockgating_state, + .set_powergating_state = vpe_set_powergating_state, +}; + const struct amdgpu_ip_block_version vpe_v6_1_ip_block = { .type = AMD_IP_BLOCK_TYPE_VPE, .major = 6, @@ -1016,3 +1038,11 @@ const struct amdgpu_ip_block_version vpe_v6_1_ip_block = { .rev = 0, .funcs = &vpe_ip_funcs, }; + +const struct amdgpu_ip_block_version vpe_v2_0_ip_block = { + .type = AMD_IP_BLOCK_TYPE_VPE, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vpe2_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h index 695da740a97e..5c9a9f59a02b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h @@ -107,5 +107,6 @@ int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev); ((vpe)->funcs->load_microcode ? (vpe)->funcs->load_microcode((vpe)) : 0) extern const struct amdgpu_ip_block_version vpe_v6_1_ip_block; +extern const struct amdgpu_ip_block_version vpe_v2_0_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 42be8ee155dd..409e103ffe8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -466,15 +466,15 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev, void amdgpu_xcp_release_sched(struct amdgpu_device *adev, struct amdgpu_ctx_entity *entity) { - struct drm_gpu_scheduler *sched; - struct amdgpu_ring *ring; + struct drm_gpu_scheduler *sched = + container_of(entity->entity.rq, typeof(*sched), rq); if (!adev->xcp_mgr) return; - sched = entity->entity.rq->sched; if (drm_sched_wqueue_ready(sched)) { - ring = to_amdgpu_ring(entity->entity.rq->sched); + struct amdgpu_ring *ring = to_amdgpu_ring(sched); + atomic_dec(&adev->xcp_mgr->xcp[ring->xcp_id].ref_cnt); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 847cfd1fd004..d80f01c0e754 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -162,7 +162,9 @@ union amd_sriov_msg_feature_flags { uint32_t ras_cper : 1; uint32_t xgmi_ta_ext_peer_link : 1; uint32_t xgmi_connected_to_cpu : 1; - uint32_t reserved : 18; + uint32_t ptl_support : 1; + uint32_t unitid_support : 1; + uint32_t reserved : 16; } flags; uint32_t all; }; @@ -256,7 +258,7 @@ struct amd_sriov_msg_pf2vf_info_header { uint32_t reserved[2]; }; -#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (55) +#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (59) struct amd_sriov_msg_pf2vf_info { /* header contains size and version */ struct amd_sriov_msg_pf2vf_info_header header; @@ -293,7 +295,7 @@ struct amd_sriov_msg_pf2vf_info { uint32_t vf2pf_update_interval_ms; /* identification in ROCm SMI */ uint64_t uuid; - uint32_t fcn_idx; + uint32_t pad; /* flags to indicate which register access method VF should use */ union amd_sriov_reg_access_flags reg_access_flags; /* MM BW management */ @@ -314,6 +316,13 @@ struct amd_sriov_msg_pf2vf_info { uint32_t more_bp; //Reserved for future use. union amd_sriov_ras_caps ras_en_caps; union amd_sriov_ras_caps ras_telemetry_en_caps; + /* PTL status response for guest */ + uint32_t ptl_enabled; // PTL enable status: 0=disabled, 1=enabled + uint32_t ptl_pref_format1; // Current preferred format 1 + uint32_t ptl_pref_format2; // Current preferred format 2 + /* unit ID assigned by host; vf_idx [0..254] maps to unitid [1..255] (0 = pf) */ + uint8_t unitid; + uint8_t padding[3]; //use the 3 bytes to align /* reserved */ uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE]; diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index 6e37961f6be5..ca5d091549e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -59,6 +59,9 @@ #define ATOM_CMD_TIMEOUT_SEC 20 +/* Limit ATOM command table recursion (calltable) to avoid kernel stack overflow. */ +#define ATOM_EXECUTE_MAX_DEPTH 32 + typedef struct { struct atom_context *ctx; uint32_t *ps, *ws; @@ -1229,6 +1232,13 @@ static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, if (!base) return -EINVAL; + if (ctx->execute_depth >= ATOM_EXECUTE_MAX_DEPTH) { + DRM_ERROR("atombios command table nesting exceeded limit (%u)\n", + ATOM_EXECUTE_MAX_DEPTH); + return -ELOOP; + } + ctx->execute_depth++; + len = CU16(base + ATOM_CT_SIZE_PTR); ws = CU8(base + ATOM_CT_WS_PTR); ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; @@ -1285,6 +1295,7 @@ static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, free: if (ws) kfree(ectx.ws); + ctx->execute_depth--; return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h index 825ff28731f5..bb3d9eb7eb6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.h +++ b/drivers/gpu/drm/amd/amdgpu/atom.h @@ -153,6 +153,9 @@ struct atom_context { uint8_t vbios_ver_str[STRLEN_NORMAL]; uint8_t date[STRLEN_NORMAL]; uint8_t build_num[STRLEN_NORMAL]; + + /* Nesting depth for ATOM_OP_CALLTABLE */ + unsigned int execute_depth; }; extern int amdgpu_atom_debug; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 22780c09177d..120da838ac28 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -939,7 +939,6 @@ static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) cik_sdma_set_ring_funcs(adev); cik_sdma_set_irq_funcs(adev); - cik_sdma_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &cik_sdma_vm_pte_funcs); return 0; @@ -1000,8 +999,15 @@ static int cik_sdma_sw_fini(struct amdgpu_ip_block *ip_block) static int cik_sdma_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; - return cik_sdma_start(adev); + r = cik_sdma_start(adev); + if (r) + return r; + + cik_sdma_set_buffer_funcs(adev); + + return 0; } static int cik_sdma_hw_fini(struct amdgpu_ip_block *ip_block) @@ -1340,8 +1346,7 @@ static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &cik_sdma_buffer_funcs); } const struct amdgpu_ip_block_version cik_sdma_ip_block = diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 8b60299b73ef..58c69dcb527f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7011,6 +7011,11 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); mqd->cp_hqd_ib_control = tmp; + tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; + /* set static priority for a compute queue/ring */ mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 8c82e90f871b..fabdbbd0abb7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4417,6 +4417,11 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; + tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; + mqd->cp_hqd_active = prop->hqd_active; /* set UQ fenceaddress */ @@ -5219,7 +5224,7 @@ static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block) /** * GFX soft reset will impact MES, need resume MES when do GFX soft reset */ - return amdgpu_mes_resume(adev); + return amdgpu_mes_resume(adev, 0); } static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) @@ -6227,56 +6232,6 @@ static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, ring->set_q_mode_offs = offs; } -static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) -{ - int i, r = 0; - struct amdgpu_device *adev = ring->adev; - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; - struct amdgpu_ring *kiq_ring = &kiq->ring; - unsigned long flags; - - if (adev->enable_mes) - return -EINVAL; - - if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) - return -EINVAL; - - spin_lock_irqsave(&kiq->ring_lock, flags); - - if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { - spin_unlock_irqrestore(&kiq->ring_lock, flags); - return -ENOMEM; - } - - /* assert preemption condition */ - amdgpu_ring_set_preempt_cond_exec(ring, false); - - /* assert IB preemption, emit the trailing fence */ - kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, - ring->trail_fence_gpu_addr, - ++ring->trail_seq); - amdgpu_ring_commit(kiq_ring); - - spin_unlock_irqrestore(&kiq->ring_lock, flags); - - /* poll the trailing fence */ - for (i = 0; i < adev->usec_timeout; i++) { - if (ring->trail_seq == - le32_to_cpu(*(ring->trail_fence_cpu_addr))) - break; - udelay(1); - } - - if (i >= adev->usec_timeout) { - r = -EINVAL; - DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); - } - - /* deassert preemption condition */ - amdgpu_ring_set_preempt_cond_exec(ring, true); - return r; -} - static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) { struct amdgpu_device *adev = ring->adev; @@ -6523,15 +6478,7 @@ static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, DRM_DEBUG("IH: CP EOP\n"); if (adev->enable_mes && doorbell_offset) { - struct amdgpu_usermode_queue *queue; - struct xarray *xa = &adev->userq_doorbell_xa; - unsigned long flags; - - xa_lock_irqsave(xa, flags); - queue = xa_load(xa, doorbell_offset); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - xa_unlock_irqrestore(xa, flags); + amdgpu_userq_process_fence_irq(adev, doorbell_offset); } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; @@ -7316,7 +7263,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, - .preempt_ib = gfx_v11_0_ring_preempt_ib, + .preempt_ib = amdgpu_gfx_ring_preempt_ib, .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, .emit_wreg = gfx_v11_0_ring_emit_wreg, .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 65c33823a688..f47928dcd848 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -602,6 +602,13 @@ static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) "amdgpu/%s_pfp.bin", ucode_prefix); if (err) goto out; + + adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( + (union amdgpu_firmware_header *) + adev->gfx.pfp_fw->data, 2, 0); + if (adev->gfx.rs64_enable) + dev_dbg(adev->dev, "CP RS64 enable\n"); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); @@ -3268,6 +3275,11 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; + tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; + mqd->cp_hqd_active = prop->hqd_active; /* set UQ fenceaddress */ @@ -4611,56 +4623,6 @@ static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, return ret; } -static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) -{ - int i, r = 0; - struct amdgpu_device *adev = ring->adev; - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; - struct amdgpu_ring *kiq_ring = &kiq->ring; - unsigned long flags; - - if (adev->enable_mes) - return -EINVAL; - - if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) - return -EINVAL; - - spin_lock_irqsave(&kiq->ring_lock, flags); - - if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { - spin_unlock_irqrestore(&kiq->ring_lock, flags); - return -ENOMEM; - } - - /* assert preemption condition */ - amdgpu_ring_set_preempt_cond_exec(ring, false); - - /* assert IB preemption, emit the trailing fence */ - kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, - ring->trail_fence_gpu_addr, - ++ring->trail_seq); - amdgpu_ring_commit(kiq_ring); - - spin_unlock_irqrestore(&kiq->ring_lock, flags); - - /* poll the trailing fence */ - for (i = 0; i < adev->usec_timeout; i++) { - if (ring->trail_seq == - le32_to_cpu(*(ring->trail_fence_cpu_addr))) - break; - udelay(1); - } - - if (i >= adev->usec_timeout) { - r = -EINVAL; - DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); - } - - /* deassert preemption condition */ - amdgpu_ring_set_preempt_cond_exec(ring, true); - return r; -} - static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) { @@ -4854,15 +4816,7 @@ static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, DRM_DEBUG("IH: CP EOP\n"); if (adev->enable_mes && doorbell_offset) { - struct xarray *xa = &adev->userq_doorbell_xa; - struct amdgpu_usermode_queue *queue; - unsigned long flags; - - xa_lock_irqsave(xa, flags); - queue = xa_load(xa, doorbell_offset); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - xa_unlock_irqrestore(xa, flags); + amdgpu_userq_process_fence_irq(adev, doorbell_offset); } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; @@ -5539,7 +5493,7 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { .pad_ib = amdgpu_ring_generic_pad_ib, .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, - .preempt_ib = gfx_v12_0_ring_preempt_ib, + .preempt_ib = amdgpu_gfx_ring_preempt_ib, .emit_wreg = gfx_v12_0_ring_emit_wreg, .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 68fd3c04134d..033f15e21ad3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -61,7 +61,7 @@ #define regCP_HQD_IB_CONTROL_DEFAULT 0x00100000 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc_1.bin"); #define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 0x00000001 #define DEFAULT_SH_MEM_CONFIG \ @@ -243,9 +243,9 @@ static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); amdgpu_ring_write(ring, /* memory (1) or register (0) */ - (WAIT_REG_MEM_MEM_SPACE(mem_space) | - WAIT_REG_MEM_OPERATION(opt) | /* wait */ - WAIT_REG_MEM_FUNCTION(3))); /* equal */ + (PACKET3_WAIT_REG_MEM__MEM_SPACE(mem_space) | + PACKET3_WAIT_REG_MEM__OPERATION(opt) | /* wait */ + PACKET3_WAIT_REG_MEM__FUNCTION(3))); /* equal */ if (mem_space) BUG_ON(addr0 & 0x3); /* Dword align */ @@ -335,7 +335,7 @@ static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) } ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); - ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; + ib.ptr[1] = PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1); ib.ptr[2] = lower_32_bits(gpu_addr); ib.ptr[3] = upper_32_bits(gpu_addr); ib.ptr[4] = 0xDEADBEEF; @@ -409,7 +409,13 @@ static int gfx_v12_1_init_microcode(struct amdgpu_device *adev) amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); if (!amdgpu_sriov_vf(adev)) { - err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) && + adev->rev_id == 0) + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, + AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_rlc_1.bin", ucode_prefix); + else + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, AMDGPU_UCODE_REQUIRED, "amdgpu/%s_rlc.bin", ucode_prefix); if (err) @@ -712,10 +718,19 @@ static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev, soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); } +#define regGFX_IMU_PARTITION_SWITCH 0x5f8c +#define regGFX_IMU_PARTITION_SWITCH_BASE_IDX 1 +#define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP__SHIFT 0x2 +#define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL + static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev) { - /* Fill this in when the interface is ready */ - return 1; + u32 reg_data; + + /* the register data is expected to be the same on all instances */ + reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), regGFX_IMU_PARTITION_SWITCH); + + return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH, TOTAL_XCCS_IN_XCP); } static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) @@ -1136,6 +1151,7 @@ static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) { + uint16_t major_ver, minor_ver; int i, j, k, r, ring_id = 0; unsigned num_compute_rings; int xcc_id, num_xcc; @@ -1146,6 +1162,15 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) adev->gfx.mec.num_mec = 1; adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; + + if (!amdgpu_discovery_get_gc_major_minor_version( + adev, &major_ver, &minor_ver)) { + if (major_ver == 1 && minor_ver == 3) { + adev->gfx.config.max_cu_per_sh /= 2; + dev_dbg(adev->dev, "Halving max_cu_per_sh for GC Discovery table v1:3 %d\n", + adev->gfx.config.max_cu_per_sh); + } + } break; default: adev->gfx.mec.num_mec = 2; @@ -1450,6 +1475,19 @@ static void gfx_v12_1_get_tcc_info(struct amdgpu_device *adev) { } +static void gfx_v12_1_xcc_xnack_set_chicken_bits(struct amdgpu_device *adev, int xcc_id) +{ + /* NOTE: COMPRESSION_ENABLE is used a chicken bit to enable/disable xcc xnack */ + mutex_lock(&adev->srbm_mutex); + if (!adev->gmc.noretry) { + WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), + TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x1); + } else + WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), + TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x0); + mutex_unlock(&adev->srbm_mutex); +} + static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, int xcc_id) { @@ -1477,6 +1515,8 @@ static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, mutex_unlock(&adev->srbm_mutex); gfx_v12_1_xcc_init_compute_vmid(adev, xcc_id); + gfx_v12_1_xcc_xnack_set_chicken_bits(adev, xcc_id); + } static void gfx_v12_1_constants_init(struct amdgpu_device *adev) @@ -2246,6 +2286,11 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m, mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size : AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size); + tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; + mqd->cp_hqd_active = prop->hqd_active; return 0; @@ -3355,7 +3400,7 @@ static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring, uint32_t flags) { unsigned vmid = AMDGPU_JOB_GET_VMID(job); - u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); + u32 control = PACKET3_INDIRECT_BUFFER__VALID(1) | ib->length_dw | (vmid << 24); /* Currently, there is a high possibility to get wave ID mismatch * between ME and GDS, leading to a hw deadlock, because ME generates @@ -3391,15 +3436,15 @@ static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, /* RELEASE_MEM - flush caches, send int */ amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); - amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ(1) | - PACKET3_RELEASE_MEM_GCR_GLV_WB | - PACKET3_RELEASE_MEM_GCR_GL2_WB | - PACKET3_RELEASE_MEM_GCR_GL2_SCOPE(2) | - PACKET3_RELEASE_MEM_TEMPORAL(3) | - PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | - PACKET3_RELEASE_MEM_EVENT_INDEX(5))); - amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | - PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); + amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__GCR_SEQ(1) | + PACKET3_RELEASE_MEM__GCR_GLV_WB | + PACKET3_RELEASE_MEM__GCR_GL2_WB | + PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(2) | + PACKET3_RELEASE_MEM__TEMPORAL(3) | + PACKET3_RELEASE_MEM__EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | + PACKET3_RELEASE_MEM__EVENT_INDEX(5))); + amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__DATA_SEL(write64bit ? 2 : 1) | + PACKET3_RELEASE_MEM__INT_SEL(int_sel ? 2 : 0))); /* * the address should be Qword aligned if 64bit write, Dword @@ -3460,7 +3505,7 @@ static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, /* write fence seq to the "addr" */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); + amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1))); amdgpu_ring_write(ring, lower_32_bits(addr)); amdgpu_ring_write(ring, upper_32_bits(addr)); amdgpu_ring_write(ring, lower_32_bits(seq)); @@ -3468,7 +3513,7 @@ static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, if (flags & AMDGPU_FENCE_FLAG_INT) { /* set register to trigger INT */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); + amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(0) | PACKET3_WRITE_DATA__WR_CONFIRM(1))); amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ @@ -3507,7 +3552,7 @@ static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, cmd = (1 << 16); /* no inc addr */ break; default: - cmd = WR_CONFIRM; + cmd = PACKET3_WRITE_DATA__WR_CONFIRM(1); break; } amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); @@ -3643,16 +3688,7 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, DRM_DEBUG("IH: CP EOP\n"); if (adev->enable_mes && doorbell_offset) { - struct xarray *xa = &adev->userq_doorbell_xa; - struct amdgpu_usermode_queue *queue; - unsigned long flags; - - xa_lock_irqsave(xa, flags); - queue = xa_load(xa, doorbell_offset); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - - xa_unlock_irqrestore(xa, flags); + amdgpu_userq_process_fence_irq(adev, doorbell_offset); } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; @@ -3819,12 +3855,12 @@ static int gfx_v12_1_rlc_poison_irq(struct amdgpu_device *adev, static void gfx_v12_1_emit_mem_sync(struct amdgpu_ring *ring) { const unsigned int gcr_cntl = - PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | - PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | - PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | - PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | - PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1) | - PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_SCOPE(2); + PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(1) | + PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(1) | + PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(1) | + PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(1) | + PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(1) | + PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(2); /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h index 21a07530c64d..77b4f6ea532f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h @@ -58,11 +58,36 @@ #define PACKET3_DISPATCH_DIRECT 0x15 #define PACKET3_DISPATCH_INDIRECT 0x16 #define PACKET3_ATOMIC_MEM 0x1E +#define PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) & 0x7F) << 0) +#define PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) & 0xF) << 8) +#define PACKET3_ATOMIC_MEM__SCOPE(x) ((((unsigned)(x)) & 0x3) << 23) +#define PACKET3_ATOMIC_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) +#define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x))) +#define PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) & 0x1FFF) << 0) +#define PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC 0 +#define PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1 +#define PACKET3_ATOMIC_MEM__COMMAND__WAIT_FOR_WRITE_CONFIRMATION 2 +#define PACKET3_ATOMIC_MEM__COMMAND__SEND_AND_CONTINUE 3 +#define PACKET3_ATOMIC_MEM__SCOPE__CU 0 +#define PACKET3_ATOMIC_MEM__SCOPE__SE 1 +#define PACKET3_ATOMIC_MEM__SCOPE__DEVICE 2 +#define PACKET3_ATOMIC_MEM__SCOPE__SYSTEM 3 +#define PACKET3_ATOMIC_MEM__TEMPORAL__RT 0 +#define PACKET3_ATOMIC_MEM__TEMPORAL__NT 1 +#define PACKET3_ATOMIC_MEM__TEMPORAL__FW 2 +#define PACKET3_ATOMIC_MEM__TEMPORAL__UC 3 #define PACKET3_OCCLUSION_QUERY 0x1F #define PACKET3_SET_PREDICATION 0x20 #define PACKET3_REG_RMW 0x21 #define PACKET3_COND_EXEC 0x22 #define PACKET3_PRED_EXEC 0x23 +#define PACKET3_PRED_EXEC__EXEC_COUNT(x) ((((unsigned)(x)) & 0x3FFF) << 0) +#define PACKET3_PRED_EXEC__VIRTUALXCCID_SELECT(x) ((((unsigned)(x)) & 0xFF) << 24) #define PACKET3_DRAW_INDIRECT 0x24 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 #define PACKET3_INDEX_BASE 0x26 @@ -74,7 +99,11 @@ #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 #define PACKET3_WRITE_DATA 0x37 -#define WRITE_DATA_DST_SEL(x) (((x) & 0xf) << 8) +#define PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8) +#define PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER 0 +#define PACKET3_WRITE_DATA__DST_SEL__TC_L2 2 +#define PACKET3_WRITE_DATA__DST_SEL__MEMORY 5 +#define PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE 6 /* 0 - register * 1 - reserved * 2 - tc_l2 @@ -83,27 +112,52 @@ * 5 - memory (same as tc_l2) * 6 - memory_mapped_adc_persistent_state */ -#define WRITE_DATA_SCOPE(x) (((x) & 0x3) << 12) -#define WRITE_DATA_MODE(x) (((x) & 0x3) << 14) +#define PACKET3_WRITE_DATA__SCOPE(x) ((((unsigned)(x)) & 0x3) << 12) +#define PACKET3_WRITE_DATA__SCOPE__CU 0 +#define PACKET3_WRITE_DATA__SCOPE__SE 1 +#define PACKET3_WRITE_DATA__SCOPE__DEVICE 2 +#define PACKET3_WRITE_DATA__SCOPE__SYSTEM 3 +#define PACKET3_WRITE_DATA__MODE(x) ((((unsigned)(x)) & 0x3) << 14) +#define PACKET3_WRITE_DATA__MODE__LOCAL_XCD 0 +#define PACKET3_WRITE_DATA__MODE__REMOTE_OR_LOCAL_AID 1 +#define PACKET3_WRITE_DATA__MODE__REMOTE_XCD 2 +#define PACKET3_WRITE_DATA__MODE__REMOTE_MID 3 /* 0 - local xcd * 1 - remote/local aid * 2 - remote xcd * 3 - remote mid */ -#define WRITE_DATA_ADDR_INCR (1 << 16) -#define WRITE_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) -#define WR_CONFIRM (1 << 20) -#define WRITE_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) -#define WRITE_DATA_TEMPORAL(x) (((x) & 0x3) << 25) - /* 0 - rt - * 1 - nt - * 2 - ht - * 3 - lu - */ -#define WRITE_DATA_COOP_DISABLE (1 << 27) +#define PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) & 0x1) << 16) +#define PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS 0 +#define PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1 +#define PACKET3_WRITE_DATA__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 18) +#define PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20) +#define PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION 0 +#define PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1 +#define PACKET3_WRITE_DATA__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xF) << 21) +#define PACKET3_WRITE_DATA__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) +#define PACKET3_WRITE_DATA__TEMPORAL__RT 0 +#define PACKET3_WRITE_DATA__TEMPORAL__NT 1 +#define PACKET3_WRITE_DATA__TEMPORAL__HT 2 +#define PACKET3_WRITE_DATA__TEMPORAL__LU 3 +#define PACKET3_WRITE_DATA__COOP_DISABLE(x) ((((unsigned)(x)) & 0x1) << 27) +#define PACKET3_WRITE_DATA__COOP_DISABLE__MASTER_AND_SLAVE_COOP 0 +#define PACKET3_WRITE_DATA__COOP_DISABLE__MASTER_ONLY 1 +#define PACKET3_WRITE_DATA__DST_MMREG_ADDR_LO(x) ((unsigned)(x)) +#define PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_WRITE_DATA__DST_MMREG_ADDR_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) +#define PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x)) +#define PACKET3_WRITE_DATA__DATA(x) ((unsigned)(x)) #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 #define PACKET3_WAIT_REG_MEM 0x3C -#define WAIT_REG_MEM_FUNCTION(x) (((x) & 0x7) << 0) +#define PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) & 0x7) << 0) +#define PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS 0 +#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1 +#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE 2 +#define PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3 +#define PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE 4 +#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE 5 +#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE 6 /* 0 - always * 1 - < * 2 - <= @@ -112,117 +166,222 @@ * 5 - >= * 6 - > */ -#define WAIT_REG_MEM_MEM_SPACE(x) (((x) & 0x3) << 4) +#define PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) & 0x3) << 4) +#define PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE 0 +#define PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1 /* 0 - reg * 1 - mem */ -#define WAIT_REG_MEM_OPERATION(x) (((x) & 0x3) << 6) +#define PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) & 0x3) << 6) +#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM 0 +#define PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1 +#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3 /* 0 - wait_reg_mem * 1 - wr_wait_wr_reg + * 2 - reserved + * 3 - wait_mem_preemptable */ -#define WAIT_REG_MEM_MODE(x) (((x) & 0x3) << 10) +#define PACKET3_WAIT_REG_MEM__MODE(x) ((((unsigned)(x)) & 0x3) << 10) +#define PACKET3_WAIT_REG_MEM__MODE__LOCAL_XCD 0 +#define PACKET3_WAIT_REG_MEM__MODE__REMOTE_OR_LOCAL_AID 1 +#define PACKET3_WAIT_REG_MEM__MODE__REMOTE_XCD 2 +#define PACKET3_WAIT_REG_MEM__MODE__REMOTE_MID 3 /* 0 - local xcd * 1 - remote/local aid * 2 - remote xcd * 3 - remote mid */ -#define WAIT_REG_MEM_MID_DIE_ID(x) (((x) & 0x3) << 12) -#define WAIT_REG_MEM_XCD_DIE_ID(x) (((x) & 0xf) << 14) -#define WAIT_REG_MEM_MES_INTR_PIPE(x) (((x) & 0x3) << 22) -#define WAIT_REG_MEM_MES_ACTION(x) (((x) & 0x1) << 24) -#define WAIT_REG_MEM_TEMPORAL(x) (((x) & 0x3) << 25) +#define PACKET3_WAIT_REG_MEM__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 12) +#define PACKET3_WAIT_REG_MEM__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xf) << 14) +#define PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 22) +#define PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) & 0x1) << 24) +#define PACKET3_WAIT_REG_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) +#define PACKET3_WAIT_REG_MEM__TEMPORAL__RT 0 +#define PACKET3_WAIT_REG_MEM__TEMPORAL__NT 1 +#define PACKET3_WAIT_REG_MEM__TEMPORAL__HT 2 +#define PACKET3_WAIT_REG_MEM__TEMPORAL__LU 3 /* 0 - rt * 1 - nt * 2 - ht * 3 - lu */ +#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((unsigned)(x)) +#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) & 0x3FFFF) << 0) +#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x)) +#define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) +#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) & 0x3FFFF) << 0) +#define PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x)) +#define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x)) +#define PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0) +#define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31) #define PACKET3_INDIRECT_BUFFER 0x3F -#define INDIRECT_BUFFER_VALID (1 << 23) -#define INDIRECT_BUFFER_TEMPORAL(x) (x) << 28) - /* 0 - rt - * 1 - nt - * 2 - ht - * 3 - lu - */ +#define PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x)) +#define PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) & 0xFFFFF) << 0) +#define PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) & 0x1) << 20) +#define PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) & 0x1) << 21) +#define PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) & 0x1) << 23) +#define PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) & 0xF) << 24) +#define PACKET3_INDIRECT_BUFFER__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 28) +#define PACKET3_INDIRECT_BUFFER__INHERIT_VMID(x) ((((unsigned)(x)) & 0x1) << 30) +#define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31) +#define PACKET3_INDIRECT_BUFFER__TEMPORAL__RT 0 +#define PACKET3_INDIRECT_BUFFER__TEMPORAL__NT 1 +#define PACKET3_INDIRECT_BUFFER__TEMPORAL__HT 2 +#define PACKET3_INDIRECT_BUFFER__TEMPORAL__LU 3 #define PACKET3_COND_INDIRECT_BUFFER 0x3F #define PACKET3_COPY_DATA 0x40 -#define COPY_DATA_SRC_SEL(x) (((x) & 0xf) << 0) -#define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8) -#define COPY_DATA_SRC_SCOPE(x) (((x) & 0x3) << 4) -#define COPY_DATA_DST_SCOPE(x) (((x) & 0x3) << 27) -#define COPY_DATA_MODE(x) (((x) & 0x3) << 6) - /* 0 - local xcd - * 1 - remote/local aid - * 2 - remote xcd - * 3 - remote mid - */ -#define COPY_DATA_SRC_TEMPORAL(x) (((x) & 0x3) << 13) -#define COPY_DATA_DST_TEMPORAL(x) (((x) & 0x3) << 25) - /* 0 - rt - * 1 - nt - * 2 - ht - * 3 - lu - */ -#define COPY_DATA_COUNT_SEL (1 << 16) -#define COPY_DATA_SRC_DST_REMOTE_MODE(x) (((x)) & 0x1 << 16) - /* 0 - src remote - * 1 - dst remote - */ -#define COPY_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) -#define COPY_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) -#define COPY_DATA_PQ_EXE_STATUS (1 << 27) +#define PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) & 0xF) << 0) +#define PACKET3_COPY_DATA__SRC_SCOPE(x) ((((unsigned)(x)) & 0x3) << 4) +#define PACKET3_COPY_DATA__MODE(x) ((((unsigned)(x)) & 0x3) << 6) +#define PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8) +#define PACKET3_COPY_DATA__SRC_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 13) +#define PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) & 0x1) << 16) +#define PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE(x) ((((unsigned)(x)) & 0x1) << 17) +#define PACKET3_COPY_DATA__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 18) +#define PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20) +#define PACKET3_COPY_DATA__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xF) << 21) +#define PACKET3_COPY_DATA__DST_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) +#define PACKET3_COPY_DATA__DST_SCOPE(x) ((((unsigned)(x)) & 0x3) << 27) +#define PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 29) +#define PACKET3_COPY_DATA__SRC_REG_OFFSET_LO(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) +#define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__SRC_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) +#define PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__DST_REG_OFFSET_LO(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) +#define PACKET3_COPY_DATA__DST_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0) +#define PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x)) +#define PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER 0 +#define PACKET3_COPY_DATA__SRC_SEL__TC_L2_OBSOLETE 1 +#define PACKET3_COPY_DATA__SRC_SEL__TC_L2 2 +#define PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS 4 +#define PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA 5 +#define PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA 6 +#define PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT 9 +#define PACKET3_COPY_DATA__SRC_SEL__SYSTEM_CLOCK_COUNT 10 +#define PACKET3_COPY_DATA__SRC_SCOPE__CU 0 +#define PACKET3_COPY_DATA__SRC_SCOPE__SE 1 +#define PACKET3_COPY_DATA__SRC_SCOPE__DEVICE 2 +#define PACKET3_COPY_DATA__SRC_SCOPE__SYSTEM 3 +#define PACKET3_COPY_DATA__MODE__LOCAL_XCD 0 +#define PACKET3_COPY_DATA__MODE__REMOTE_OR_LOCAL_AID 1 +#define PACKET3_COPY_DATA__MODE__REMOTE_XCD 2 +#define PACKET3_COPY_DATA__MODE__REMOTE_MID 3 +#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER 0 +#define PACKET3_COPY_DATA__DST_SEL__TC_L2 2 +#define PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS 4 +#define PACKET3_COPY_DATA__DST_SEL__TC_L2_OBSOLETE 5 +#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC 6 +#define PACKET3_COPY_DATA__SRC_TEMPORAL__RT 0 +#define PACKET3_COPY_DATA__SRC_TEMPORAL__NT 1 +#define PACKET3_COPY_DATA__SRC_TEMPORAL__HT 2 +#define PACKET3_COPY_DATA__SRC_TEMPORAL__LU 3 +#define PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA 0 +#define PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1 +#define PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE__SRC_IS_REMOTE 0 +#define PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE__DST_IS_REMOTE 1 +#define PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION 0 +#define PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1 +#define PACKET3_COPY_DATA__DST_TEMPORAL__RT 0 +#define PACKET3_COPY_DATA__DST_TEMPORAL__NT 1 +#define PACKET3_COPY_DATA__DST_TEMPORAL__HT 2 +#define PACKET3_COPY_DATA__DST_TEMPORAL__LU 3 +#define PACKET3_COPY_DATA__DST_SCOPE__CU 0 +#define PACKET3_COPY_DATA__DST_SCOPE__SE 1 +#define PACKET3_COPY_DATA__DST_SCOPE__DEVICE 2 +#define PACKET3_COPY_DATA__DST_SCOPE__SYSTEM 3 +#define PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT 0 +#define PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1 #define PACKET3_PFP_SYNC_ME 0x42 #define PACKET3_COND_WRITE 0x45 #define PACKET3_EVENT_WRITE 0x46 -#define EVENT_TYPE(x) ((x) << 0) -#define EVENT_INDEX(x) ((x) << 8) - /* 0 - any non-TS event - * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* - * 2 - SAMPLE_PIPELINESTAT - * 3 - SAMPLE_STREAMOUTSTAT* - * 4 - *S_PARTIAL_FLUSH - */ +#define PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0) +#define PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8) +#define PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) & 0x1) << 31) +#define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) +#define PACKET3_EVENT_WRITE__ADDRESS_HI(x) ((unsigned)(x)) +#define PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER 0 +#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTAT 2 +#define PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH 4 +#define PACKET3_EVENT_WRITE_EOP 0x47 +#define PACKET3_EVENT_WRITE_EOS 0x48 #define PACKET3_RELEASE_MEM 0x49 -#define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) -#define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) -#define PACKET3_RELEASE_MEM_GCR_GL2_SCOPE(x) ((x) << 12) -#define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14) -#define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16) -#define PACKET3_RELEASE_MEM_GCR_GL2_RANGE(x) ((x) << 17) -#define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19) -#define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20) -#define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21) -#define PACKET3_RELEASE_MEM_GCR_SEQ(x) ((x) << 22) -#define PACKET3_RELEASE_MEM_GCR_GLV_WB (1 << 24) -#define PACKET3_RELEASE_MEM_TEMPORAL(x) ((x) << 25) +#define PACKET3_RELEASE_MEM__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0) +#define PACKET3_RELEASE_MEM__WAIT_SYNC(x) ((((unsigned)(x)) & 0x1) << 7) +#define PACKET3_RELEASE_MEM__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8) +#define PACKET3_RELEASE_MEM__EVENT_INDEX__END_OF_PIPE 5 +#define PACKET3_RELEASE_MEM__EVENT_INDEX__SHADER_DONE 6 +#define PACKET3_RELEASE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x1FFF) << 12) +#define PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(x) ((x) << 12) +#define PACKET3_RELEASE_MEM__GCR_GLV_INV (1 << 14) +#define PACKET3_RELEASE_MEM__GCR_GL2_US (1 << 16) +#define PACKET3_RELEASE_MEM__GCR_GL2_RANGE(x) ((x) << 17) +#define PACKET3_RELEASE_MEM__GCR_GL2_DISCARD (1 << 19) +#define PACKET3_RELEASE_MEM__GCR_GL2_INV (1 << 20) +#define PACKET3_RELEASE_MEM__GCR_GL2_WB (1 << 21) +#define PACKET3_RELEASE_MEM__GCR_SEQ(x) ((x) << 22) +#define PACKET3_RELEASE_MEM__GCR_GLV_WB (1 << 24) +#define PACKET3_RELEASE_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) +#define PACKET3_RELEASE_MEM__TEMPORAL__RT 0 +#define PACKET3_RELEASE_MEM__TEMPORAL__NT 1 +#define PACKET3_RELEASE_MEM__TEMPORAL__HT 2 +#define PACKET3_RELEASE_MEM__TEMPORAL__LU 3 /* 0 - temporal__release_mem__rt * 1 - temporal__release_mem__nt * 2 - temporal__release_mem__ht * 3 - temporal__release_mem__lu */ -#define PACKET3_RELEASE_MEM_PQ_EXE_STATUS (1 << 28) -#define PACKET3_RELEASE_MEM_GCR_GLK_INV (1 << 30) +#define PACKET3_RELEASE_MEM__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 28) +#define PACKET3_RELEASE_MEM__PQ_EXE_STATUS__DEFAULT 0 +#define PACKET3_RELEASE_MEM__PQ_EXE_STATUS__PHASE_UPDATE 1 +#define PACKET3_RELEASE_MEM__GCR_GLK_INV (1 << 30) -#define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) - /* 0 - memory controller - * 1 - TC/L2 - * 2 - register - */ -#define PACKET3_RELEASE_MEM_MES_INTR_PIPE(x) ((x) << 20) -#define PACKET3_RELEASE_MEM_MES_ACTION_ID(x) ((x) << 22) -#define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) - /* 0 - none - * 1 - interrupt only (DATA_SEL = 0) - * 2 - interrupt when data write is confirmed - */ -#define PACKET3_RELEASE_MEM_ADD_DOOREBLL_OFFSET(x) (1 << 28) -#define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) +#define PACKET3_RELEASE_MEM__DST_SEL(x) ((((unsigned)(x)) & 0x3) << 16) +#define PACKET3_RELEASE_MEM__DST_SEL__MEMORY_CONTROLLER 0 +#define PACKET3_RELEASE_MEM__DST_SEL__TC_L2 1 +#define PACKET3_RELEASE_MEM__DST_SEL__QUQUE_WRITE_POINTER_REGISTER 2 +#define PACKET3_RELEASE_MEM__DST_SEL__QUQUE_WRITE_POINTER_POLL_MASK_BIT 3 +#define PACKET3_RELEASE_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 20) +#define PACKET3_RELEASE_MEM__MES_ACTION_ID(x) ((((unsigned)(x)) & 0x3) << 22) +#define PACKET3_RELEASE_MEM__MES_ACTION_ID__NO_MES_NOTIFICATION 0 +#define PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_AND_FENCE 1 +#define PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_NO_FENCE_THEN_ADDRESS_PAYLOAD 2 +#define PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_AND_ADDRESS_PAYLOAD 3 +#define PACKET3_RELEASE_MEM__INT_SEL(x) ((((unsigned)(x)) & 0x7) << 24) +#define PACKET3_RELEASE_MEM__INT_SEL__NONE 0 +#define PACKET3_RELEASE_MEM__INT_SEL__SEND_INTERRUPT_ONLY 1 +#define PACKET3_RELEASE_MEM__INT_SEL__SEND_INTERRUPT_AFTER_WRITE_CONFIRM 2 +#define PACKET3_RELEASE_MEM__INT_SEL__SEND_DATA_AND_WRITE_CONFIRM 3 +#define PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID 4 +#define PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID_BASED_ON_32_BIT_COMPARE 5 +#define PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID_BASED_ON_64_BIT_COMPARE 6 +#define PACKET3_RELEASE_MEM__ADD_DOOREBLL_OFFSET(x) ((((unsigned)(x)) & 0x1) << 28) +#define PACKET3_RELEASE_MEM__DATA_SEL(x) ((((unsigned)(x)) & 0x7) << 29) +#define PACKET3_RELEASE_MEM__DATA_SEL__NONE 0 +#define PACKET3_RELEASE_MEM__DATA_SEL__SEND_32_BIT_LOW 1 +#define PACKET3_RELEASE_MEM__DATA_SEL__SEND_64_BIT_DATA 2 +#define PACKET3_RELEASE_MEM__DATA_SEL__SEND_GPU_CLOCK_COUNTER 3 +#define PACKET3_RELEASE_MEM__DATA_SEL__SEND_SYSTEM_CLOCK_COUNTER 4 /* 0 - discard * 1 - send low 32bit data * 2 - send 64bit data * 3 - send 64bit GPU counter value * 4 - send 64bit sys counter value */ +#define PACKET3_RELEASE_MEM__ADDRESS_LO_32B(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) +#define PACKET3_RELEASE_MEM__ADDRESS_LO_64B(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) +#define PACKET3_RELEASE_MEM__ADDRESS_HI(x) ((unsigned)(x)) +#define PACKET3_RELEASE_MEM__DATA_LO(x) ((unsigned)(x)) +#define PACKET3_RELEASE_MEM__CMP_DATA_LO(x) ((unsigned)(x)) +#define PACKET3_RELEASE_MEM__DATA_HI(x) ((unsigned)(x)) +#define PACKET3_RELEASE_MEM__CMP_DATA_HI(x) ((unsigned)(x)) +#define PACKET3_RELEASE_MEM__INT_CTXID(x) ((unsigned)(x)) #define PACKET3_PREAMBLE_CNTL 0x4A # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) @@ -279,58 +438,78 @@ # define PACKET3_DMA_DATA_CMD_DIS_WC (1 << 30) #define PACKET3_CONTEXT_REG_RMW 0x51 #define PACKET3_ACQUIRE_MEM 0x58 -/* 1. HEADER - * 2. COHER_CNTL [30:0] - * 2.1 ENGINE_SEL [31:31] - * 2. COHER_SIZE [31:0] - * 3. COHER_SIZE_HI [7:0] - * 4. COHER_BASE_LO [31:0] - * 5. COHER_BASE_HI [23:0] - * 7. POLL_INTERVAL [15:0] - * 8. GCR_CNTL [18:0] - */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) +/* 1. HEADER */ +#define PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x)) +/* 3. COHER_SIZE [31:0] */ +#define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) & 0xFF) << 0) +/* 4. COHER_SIZE_HI [7:0] */ +#define PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x)) +/* 5. COHER_BASE_LO [31:0] */ +#define PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) & 0xFFFFFF) << 0) +/* 6. COHER_BASE_HI [23:0] */ +#define PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0) +/* 7. POLL_INTERVAL [15:0] */ +#define PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x7FFFF) << 0) +/* 8. GCR_CNTL [18:0] */ +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(x) ((x) << 0) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__NOP 0 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__ALL 1 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__RANGE 2 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__FIRST_LAST 3 /* * 0:NOP * 1:ALL * 2:RANGE * 3:FIRST_LAST */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE(x) ((x) << 2) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__ALL 0 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__RANGE 2 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__FIRST_LAST 3 /* * 0:ALL * 1:reserved * 2:RANGE * 3:FIRST_LAST */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_SCOPE(x) ((x) << 4) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(x) ((x) << 4) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__DEVICE 0 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__SYSTEM 1 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__FORCE_ALL 2 /* * 0:Device scope * 1:System scope * 2:Force INV/WB all * 3:Reserved */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_WB(x) ((x) << 6) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_WB(x) ((x) << 6) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(x) ((x) << 7) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(x) ((x) << 8) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_US(x) ((x) << 10) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE(x) ((x) << 11) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__ALL 0 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__VOL 1 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__RANGE 2 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__FIRST_LAST 3 /* * 0:ALL * 1:VOL * 2:RANGE * 3:FIRST_LAST */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_DISCARD(x) ((x) << 13) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(x) ((x) << 14) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(x) ((x) << 15) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ(x) ((x) << 16) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__PARALLET 0 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__FORWARD 1 +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__REVERSE 2 /* * 0: PARALLEL * 1: FORWARD * 2: REVERSE */ -#define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) +#define PACKET3_ACQUIRE_MEM__GCR_CNTL__GCR_RANGE_IS_PA (1 << 18) #define PACKET3_GEN_PDEPTE 0x5B #define PACKET3_PRIME_UTCL2 0x5D #define PACKET3_LOAD_UCONFIG_REG 0x5E @@ -348,11 +527,19 @@ #define PACKET3_SET_SH_REG 0x76 #define PACKET3_SET_SH_REG_START 0x00002c00 #define PACKET3_SET_SH_REG_END 0x00003000 +#define PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0) +#define PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) & 0x1F) << 23) +#define PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) & 0xF) << 28) +#define PACKET3_SET_SH_REG__REG_DATA(x) (((unsigned)(x))) +#define PACKET3_SET_SH_REG__INDEX__DEFAULT 0 +#define PACKET3_SET_SH_REG__INDEX__INSERT_VMID 1 #define PACKET3_SET_SH_REG_OFFSET 0x77 #define PACKET3_SET_QUEUE_REG 0x78 #define PACKET3_SET_UCONFIG_REG 0x79 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 +#define PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0) +#define PACKET3_SET_UCONFIG_REG__REG_DATA(x) (((unsigned)(x))) #define PACKET3_SET_UCONFIG_REG_INDEX 0x7A #define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C #define PACKET3_DISPATCH_DRAW 0x8D diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 73223d97a87f..ac90d8e9d86a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -1571,6 +1571,71 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) mutex_unlock(&adev->grbm_idx_mutex); } +/** + * gfx_v6_0_setup_tcc() - setup which TCCs are used + * + * @adev: amdgpu_device pointer + * + * Verify whether the current GPU has any TCCs disabled, + * which can happen when the GPU is harvested and some + * memory channels are disabled, reducing the memory bus width. + * For example, on the Radeon HD 7870 XT (Tahiti LE). + * + * If some TCCs are disabled, we need to make sure that + * the disabled TCCs are not used, and the remaining TCCs + * are used optimally. + * + * TCP_CHAN_STEER_LO/HI control which TCC is used by TCP channels. + * TCP_ADDR_CONFIG.NUM_TCC_BANKS controls how many channels are used. + * + * For optimal performance: + * - Rely on the CHAN_STEER from the golden registers table, + * only skip disabled TCCs but keep the mapping order. + * - Limit NUM_TCC_BANKS to number of active TCCs to avoid thrashing, + * which performs better than using the same TCC twice. + */ +static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev) +{ + u32 i, tcc, tcp_addr_config, num_active_tcc = 0; + u64 chan_steer, patched_chan_steer = 0; + const u32 num_max_tcc = adev->gfx.config.max_texture_channel_caches; + const u32 dis_tcc_mask = + amdgpu_gfx_create_bitmask(num_max_tcc) & + (REG_GET_FIELD(RREG32(mmCGTS_TCC_DISABLE), + CGTS_TCC_DISABLE, TCC_DISABLE) | + REG_GET_FIELD(RREG32(mmCGTS_USER_TCC_DISABLE), + CGTS_USER_TCC_DISABLE, TCC_DISABLE)); + + /* When no TCC is disabled, the golden registers table already has optimal TCC setup */ + if (!dis_tcc_mask) + return; + + /* Each 4-bit nibble contains the index of a TCC used by all TCPs */ + chan_steer = RREG32(mmTCP_CHAN_STEER_LO) | ((u64)RREG32(mmTCP_CHAN_STEER_HI) << 32ull); + + /* Patch the TCP to TCC mapping to skip disabled TCCs */ + for (i = 0; i < num_max_tcc; ++i) { + tcc = (chan_steer >> (u64)(4 * i)) & 0xf; + + if (!((1 << tcc) & dis_tcc_mask)) { + /* Copy enabled TCC indices to the patched register value. */ + patched_chan_steer |= (u64)tcc << (u64)(4 * num_active_tcc); + ++num_active_tcc; + } + } + + WARN_ON(num_active_tcc != num_max_tcc - hweight32(dis_tcc_mask)); + + /* Patch number of TCCs used by TCPs */ + tcp_addr_config = REG_SET_FIELD(RREG32(mmTCP_ADDR_CONFIG), + TCP_ADDR_CONFIG, NUM_TCC_BANKS, + num_active_tcc - 1); + + WREG32(mmTCP_ADDR_CONFIG, tcp_addr_config); + WREG32(mmTCP_CHAN_STEER_HI, upper_32_bits(patched_chan_steer)); + WREG32(mmTCP_CHAN_STEER_LO, lower_32_bits(patched_chan_steer)); +} + static void gfx_v6_0_config_init(struct amdgpu_device *adev) { adev->gfx.config.double_offchip_lds_buf = 0; @@ -1729,6 +1794,7 @@ static void gfx_v6_0_constants_init(struct amdgpu_device *adev) gfx_v6_0_tiling_mode_table_init(adev); gfx_v6_0_setup_rb(adev); + gfx_v6_0_setup_tcc(adev); gfx_v6_0_setup_spi(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 2b691452775b..65b8497ad5f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2819,6 +2819,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, { u64 hqd_gpu_addr; u64 wb_gpu_addr; + u32 tmp; /* init the mqd struct */ memset(mqd, 0, sizeof(struct cik_mqd)); @@ -2923,7 +2924,11 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); - mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); + tmp = RREG32(mmCP_HQD_QUANTUM); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10); + mqd->cp_hqd_quantum = tmp; mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index a6b4c8f41dc1..130196859ff3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4532,7 +4532,11 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) /* set static priority for a queue/ring */ gfx_v8_0_mqd_set_priority(ring, mqd); - mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); + tmp = RREG32(mmCP_HQD_QUANTUM); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10); + mqd->cp_hqd_quantum = tmp; /* map_queues packet doesn't need activate the queue, * so only kiq need set this field. diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 95be105671ec..bf270e605949 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3667,7 +3667,11 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) /* set static priority for a queue/ring */ gfx_v9_0_mqd_set_priority(ring, mqd); - mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); + tmp = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; /* map_queues packet doesn't need activate the queue, * so only kiq need set this field. @@ -5660,9 +5664,6 @@ static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, { struct amdgpu_device *adev = ring->adev; - /* we only allocate 32bit for each seq wb address */ - BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); - /* write fence seq to the "addr" */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index ad4d442e7345..9f76e1af8a55 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1943,7 +1943,11 @@ static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) /* set static priority for a queue/ring */ gfx_v9_4_3_mqd_set_priority(ring, mqd); - mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); + mqd->cp_hqd_quantum = tmp; /* map_queues packet doesn't need activate the queue, * so only kiq need set this field. @@ -2370,11 +2374,78 @@ static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) return r; } +static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool enable) +{ + struct amdgpu_ptl *ptl = &adev->psp.ptl; + uint32_t ptl_state = enable ? 1 : 0; + uint32_t fmt1, fmt2; + int r; + + if (!adev->psp.funcs) + return -EOPNOTSUPP; + + if (!ptl->hw_supported) { + fmt1 = GFX_FTYPE_VECTOR; + fmt2 = GFX_FTYPE_F8; + } else { + fmt1 = ptl->fmt1; + fmt2 = ptl->fmt2; + } + + /* initialize PTL with default formats: GFX_FTYPE_VECTOR & GFX_FTYPE_F8 */ + r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, + &fmt1, &fmt2); + if (r) + return r; + + ptl->hw_supported = true; + + atomic_set(&ptl->disable_ref, 0); + if (!enable && !amdgpu_in_reset(adev) && !adev->in_suspend) { + dev_dbg(adev->dev, + "PTL disabled (amdgpu.ptl=%d)\ + To enable, set amdgpu.ptl=1 via module param or kernel cmdline\n", + amdgpu_ptl); + set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); + } + + return 0; +} + +static int gfx_v9_4_3_ptl_hw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ptl *ptl = &adev->psp.ptl; + bool enable; + + switch (amdgpu_ptl) { + case 1: + enable = true; + break; + case 2: + /* Permanently disabled - cannot be re-enabled */ + enable = false; + ptl->permanently_disabled = true; + break; + case -1: + case 0: + default: + enable = false; + break; + } + + gfx_v9_4_3_perf_monitor_ptl_init(adev, enable ? 1 : 0); + + return 0; +} + static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; int i, num_xcc; + if (adev->psp.ptl.hw_supported && !amdgpu_in_reset(adev)) + gfx_v9_4_3_perf_monitor_ptl_init(adev, false); + amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); @@ -2401,12 +2472,21 @@ static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; int i, num_xcc; + u32 gc_ip_version; num_xcc = NUM_XCC(adev->gfx.xcc_mask); + gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); + for (i = 0; i < num_xcc; i++) { - if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), - GRBM_STATUS, GUI_ACTIVE)) - return false; + if (gc_ip_version == IP_VERSION(9, 4, 4)) { + if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), + GRBM_STATUS, SPI_BUSY)) + return false; + } else { + if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), + GRBM_STATUS, GUI_ACTIVE)) + return false; + } } return true; } @@ -2549,6 +2629,8 @@ static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) adev->gfx.ras->enable_watchdog_timer) adev->gfx.ras->enable_watchdog_timer(adev); + gfx_v9_4_3_ptl_hw_init(adev); + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index e1ace7d44ffd..8523833a74fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -707,20 +707,16 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.aper_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { - default: - adev->gmc.gart_size = 512ULL << 20; - break; - case IP_VERSION(10, 3, 1): /* DCE SG support */ - case IP_VERSION(10, 3, 3): /* DCE SG support */ - case IP_VERSION(10, 3, 6): /* DCE SG support */ - case IP_VERSION(10, 3, 7): /* DCE SG support */ - adev->gmc.gart_size = 1024ULL << 20; - break; - } - } else { - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(10, 3, 1): /* DCE SG support */ + case IP_VERSION(10, 3, 3): /* DCE SG support */ + case IP_VERSION(10, 3, 6): /* DCE SG support */ + case IP_VERSION(10, 3, 7): /* DCE SG support */ + amdgpu_gmc_set_gart_size(adev, SZ_1G); + break; + default: + amdgpu_gmc_set_gart_size(adev, SZ_512M); + break; } gmc_v10_0_vram_gtt_location(adev, &adev->gmc); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 94d6631ce0bc..16388e3caea3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -709,10 +709,7 @@ static int gmc_v11_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.real_vram_size; /* set the gart size */ - if (amdgpu_gart_size == -1) - adev->gmc.gart_size = 512ULL << 20; - else - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + amdgpu_gmc_set_gart_size(adev, SZ_512M); gmc_v11_0_vram_gtt_location(adev, &adev->gmc); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index e10ac9788d13..586703ec0dfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -729,8 +729,10 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev) int r; if (adev->gmc.xgmi.connected_to_cpu) - adev->gmc.mc_vram_size = - adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; + /* On A+A, manage driver allocation range to the local + * node segment and prevent allocations on remote HBM. + */ + adev->gmc.mc_vram_size = adev->gmc.xgmi.node_segment_size; else adev->gmc.mc_vram_size = adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; @@ -763,10 +765,7 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.real_vram_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - adev->gmc.gart_size = 512ULL << 20; - } else - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + amdgpu_gmc_set_gart_size(adev, SZ_512M); gmc_v12_0_vram_gtt_location(adev, &adev->gmc); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index 7ea7b9c30bca..855cd29cbffa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -112,6 +112,8 @@ static int gmc_v12_1_process_interrupt(struct amdgpu_device *adev, const char *hub_name; int ret, xcc_id = 0; uint32_t status = 0; + const char *die_name; + char die_name_buf[32]; u64 addr; node_id = entry->node_id; @@ -201,6 +203,17 @@ static int gmc_v12_1_process_interrupt(struct amdgpu_device *adev, dev_err(adev->dev, " in page starting at address 0x%016llx from IH client %d (%s)\n", addr, entry->client_id, soc_v1_0_ih_clientid_name[entry->client_id]); + if (adev->irq.ih_funcs && + adev->irq.ih_funcs->node_id_to_die_name) { + die_name = adev->irq.ih_funcs->node_id_to_die_name(adev, node_id, + die_name_buf, + sizeof(die_name_buf)); + if (die_name) + dev_err(adev->dev, + " cookie node_id %d fault from die %s\n", + node_id, die_name); + } + if (amdgpu_sriov_vf(adev)) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index cc272a96fcef..af6944d2d330 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -328,24 +328,18 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.aper_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - switch (adev->asic_type) { - case CHIP_HAINAN: /* no MM engines */ - default: - adev->gmc.gart_size = 256ULL << 20; - break; - case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ - case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ - case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ - case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ - adev->gmc.gart_size = 1024ULL << 20; - break; - } - } else { - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + switch (adev->asic_type) { + case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ + case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ + case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ + case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ + amdgpu_gmc_set_gart_size(adev, SZ_1G); + break; + case CHIP_HAINAN: /* no MM engines */ + default: + amdgpu_gmc_set_gart_size(adev, SZ_256M); + break; } - - adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; gmc_v6_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index bb16ba2ef6fd..96023b4f5f92 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -394,27 +394,21 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.aper_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - switch (adev->asic_type) { - case CHIP_TOPAZ: /* no MM engines */ - default: - adev->gmc.gart_size = 256ULL << 20; - break; + switch (adev->asic_type) { #ifdef CONFIG_DRM_AMDGPU_CIK - case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ - case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ - case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ - case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ - case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ - adev->gmc.gart_size = 1024ULL << 20; - break; + case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ + case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ + case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ + case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ + case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ + amdgpu_gmc_set_gart_size(adev, SZ_1G); + break; #endif - } - } else { - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + case CHIP_TOPAZ: /* no MM engines */ + default: + amdgpu_gmc_set_gart_size(adev, SZ_256M); + break; } - - adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; gmc_v7_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index a59174f6bcc1..b76fc4441eb7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -585,27 +585,21 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.aper_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - switch (adev->asic_type) { - case CHIP_POLARIS10: /* all engines support GPUVM */ - case CHIP_POLARIS11: /* all engines support GPUVM */ - case CHIP_POLARIS12: /* all engines support GPUVM */ - case CHIP_VEGAM: /* all engines support GPUVM */ - default: - adev->gmc.gart_size = 256ULL << 20; - break; - case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ - case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ - case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ - case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ - adev->gmc.gart_size = 1024ULL << 20; - break; - } - } else { - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + switch (adev->asic_type) { + case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ + case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ + case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ + case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ + amdgpu_gmc_set_gart_size(adev, SZ_1G); + break; + case CHIP_POLARIS10: /* all engines support GPUVM */ + case CHIP_POLARIS11: /* all engines support GPUVM */ + case CHIP_POLARIS12: /* all engines support GPUVM */ + case CHIP_VEGAM: /* all engines support GPUVM */ + default: + amdgpu_gmc_set_gart_size(adev, SZ_256M); + break; } - - adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; gmc_v8_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e7b78027002b..ced0f3941863 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1204,21 +1204,6 @@ static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, { int local_node, nid; - /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system - * memory can use more efficient MTYPEs. - */ - if (!(adev->flags & AMD_IS_APU) || - amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) - return; - - /* Only direct-mapped memory allows us to determine the NUMA node from - * the DMA address. - */ - if (!adev->ram_is_direct_mapped) { - dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); - return; - } - /* MTYPE_NC is the same default and can be overridden. * MTYPE_UC will be present if the memory is extended-coherent * and can also be overridden. @@ -1231,11 +1216,7 @@ static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, return; } - /* FIXME: Only supported on native mode for now. For carve-out, the - * NUMA affinity of the GPU/VM needs to come from the PCI info because - * memory partitions are not associated with different NUMA nodes. - */ - if (adev->gmc.is_app_apu && vm->mem_id >= 0) { + if (vm->mem_id >= 0) { local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; } else { dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); @@ -1344,6 +1325,20 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) { adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; + + /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes, local system + * memory can use more efficient MTYPEs. + * + * APUs mapping system memory may need different MTYPEs on different + * NUMA nodes. + * + * Only direct-mapped memory allows us to determine the NUMA node from + * the DMA address. + */ + adev->gmc.override_pte = adev->gmc.is_app_apu && + num_possible_nodes() > 1 && + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && + adev->ram_is_direct_mapped; } static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) @@ -1736,31 +1731,25 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) adev->gmc.visible_vram_size = adev->gmc.aper_size; /* set the gart size */ - if (amdgpu_gart_size == -1) { - switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { - case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ - case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ - case IP_VERSION(9, 4, 0): - case IP_VERSION(9, 4, 1): - case IP_VERSION(9, 4, 2): - case IP_VERSION(9, 4, 3): - case IP_VERSION(9, 4, 4): - case IP_VERSION(9, 5, 0): - default: - adev->gmc.gart_size = 512ULL << 20; - break; - case IP_VERSION(9, 1, 0): /* DCE SG support */ - case IP_VERSION(9, 2, 2): /* DCE SG support */ - case IP_VERSION(9, 3, 0): - adev->gmc.gart_size = 1024ULL << 20; - break; - } - } else { - adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(9, 1, 0): /* DCE SG support */ + case IP_VERSION(9, 2, 2): /* DCE SG support */ + case IP_VERSION(9, 3, 0): + amdgpu_gmc_set_gart_size(adev, SZ_1G); + break; + case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ + case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ + case IP_VERSION(9, 4, 0): + case IP_VERSION(9, 4, 1): + case IP_VERSION(9, 4, 2): + case IP_VERSION(9, 4, 3): + case IP_VERSION(9, 4, 4): + case IP_VERSION(9, 5, 0): + default: + amdgpu_gmc_set_gart_size(adev, SZ_512M); + break; } - adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; - gmc_v9_0_vram_gtt_location(adev, &adev->gmc); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 1fbe904f4223..6de9e87e04e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -798,6 +798,43 @@ static void ih_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 return; } +/* + * ih_v7_0_node_id_to_die_name - Decode IH cookie node_id to a die name string + * + * Currently, only applies to IH v7_1. For other IH versions returns NULL. + * + * IH v7_1 node_id encoding: + * node_id[N:3] = MID index + * node_id[2:0] = sub-slot: 0=MID, 1=AID, 2-5=AID.XCD, 6-7=RSV + */ +static const char *ih_v7_0_node_id_to_die_name(struct amdgpu_device *adev, + unsigned int node_id, + char *buf, size_t size) +{ + int mid_id, sub_slot; + + /* Node ID to die name decoding is only defined for IH v7_1 currenlty. */ + if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(7, 1, 0)) + return NULL; + + mid_id = node_id >> 3; + sub_slot = node_id & 0x7; + + if (mid_id > 1) + return "UNKNOWN"; + + if (sub_slot == 0) + snprintf(buf, size, "MID%d", mid_id); + else if (sub_slot == 1) + snprintf(buf, size, "AID%d", mid_id); + else if (sub_slot <= 5) + snprintf(buf, size, "AID%d.XCD%d", mid_id, sub_slot - 2); + else + snprintf(buf, size, "RSV"); + + return buf; +} + static const struct amd_ip_funcs ih_v7_0_ip_funcs = { .name = "ih_v7_0", .early_init = ih_v7_0_early_init, @@ -819,7 +856,8 @@ static const struct amdgpu_ih_funcs ih_v7_0_funcs = { .get_wptr = ih_v7_0_get_wptr, .decode_iv = amdgpu_ih_decode_iv_helper, .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, - .set_rptr = ih_v7_0_set_rptr + .set_rptr = ih_v7_0_set_rptr, + .node_id_to_die_name = ih_v7_0_node_id_to_die_name, }; static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c b/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c index 539785a51f69..fe20cf2b9454 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c @@ -140,27 +140,17 @@ static int imu_v12_1_switch_compute_partition(struct amdgpu_device *adev, int ret; if (adev->psp.funcs) { - /*TODO: revisit asp interface once it's avaialble */ - ret = psp_spatial_partition(&adev->psp, - NUM_XCC(adev->gfx.xcc_mask) / - num_xccs_per_xcp); + ret = psp_spatial_partition(&adev->psp, compute_partition_mode); if (ret) return ret; } adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; - return 0; } -static void imu_v12_1_init_mcm_addr_lut(struct amdgpu_device *adev) -{ - /* todo: fill in when interface is ready */ -} - const struct amdgpu_imu_funcs gfx_v12_1_imu_funcs = { .init_microcode = imu_v12_1_init_microcode, .load_microcode = imu_v12_1_load_microcode, .switch_compute_partition = imu_v12_1_switch_compute_partition, - .init_mcm_addr_lut = imu_v12_1_init_mcm_addr_lut, }; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 9fe8d10ab270..cffb1e6bab35 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -802,6 +802,7 @@ static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v2_0_dec_ring_get_rptr, .get_wptr = jpeg_v2_0_dec_ring_get_wptr, .set_wptr = jpeg_v2_0_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index 20983f126b49..5208312e7017 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -149,7 +149,7 @@ static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block) else ring->vm_hub = AMDGPU_MMHUB0(0); ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i; - sprintf(ring->name, "jpeg_dec_%d", i); + snprintf(ring->name, sizeof(ring->name), "jpeg_dec_%d", i); r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 0, AMDGPU_RING_PRIO_DEFAULT, NULL); if (r) @@ -693,6 +693,7 @@ static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v2_5_dec_ring_get_rptr, .get_wptr = jpeg_v2_5_dec_ring_get_wptr, .set_wptr = jpeg_v2_5_dec_ring_set_wptr, @@ -724,6 +725,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v2_5_dec_ring_get_rptr, .get_wptr = jpeg_v2_5_dec_ring_get_wptr, .set_wptr = jpeg_v2_5_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index 98f5e0622bc5..d0445df39d2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -594,6 +594,7 @@ static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v3_0_dec_ring_get_rptr, .get_wptr = jpeg_v3_0_dec_ring_get_wptr, .set_wptr = jpeg_v3_0_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index 0bd83820dd20..6fd4238a8471 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -759,6 +759,7 @@ static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v4_0_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 82abe181c730..0c746580de11 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -1219,6 +1219,7 @@ static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index 54fd9c800c40..a43582b9c876 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -804,6 +804,7 @@ static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v4_0_5_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_5_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_5_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index 46bf15dce2bd..72a4b2d0676f 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -680,6 +680,7 @@ static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v5_0_0_dec_ring_get_rptr, .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr, .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index edecbfe66c79..250316704dfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -884,6 +884,7 @@ static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v5_0_1_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v5_0_1_dec_ring_get_rptr, .get_wptr = jpeg_v5_0_1_dec_ring_get_wptr, .set_wptr = jpeg_v5_0_1_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c index 285c459379c4..7a4ecea6b39a 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c @@ -703,6 +703,7 @@ static const struct amd_ip_funcs jpeg_v5_0_2_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v5_0_2_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v5_0_2_dec_ring_get_rptr, .get_wptr = jpeg_v5_0_2_dec_ring_get_wptr, .set_wptr = jpeg_v5_0_2_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c index 1821dced936f..e7546816baba 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c @@ -661,6 +661,7 @@ static const struct amd_ip_funcs jpeg_v5_3_0_ip_funcs = { static const struct amdgpu_ring_funcs jpeg_v5_3_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_JPEG, .align_mask = 0xf, + .no_user_fence = true, .get_rptr = jpeg_v5_3_0_dec_ring_get_rptr, .get_wptr = jpeg_v5_3_0_dec_ring_get_wptr, .set_wptr = jpeg_v5_3_0_dec_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 2fc39a6938f6..9bb8f7330537 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -30,34 +30,6 @@ #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE -static int -mes_userq_map_gtt_bo_to_gart(struct amdgpu_bo *bo) -{ - int ret; - - ret = amdgpu_bo_reserve(bo, true); - if (ret) { - DRM_ERROR("Failed to reserve bo. ret %d\n", ret); - goto err_reserve_bo_failed; - } - - ret = amdgpu_ttm_alloc_gart(&bo->tbo); - if (ret) { - DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); - goto err_map_bo_gart_failed; - } - - amdgpu_bo_unreserve(bo); - bo = amdgpu_bo_ref(bo); - - return 0; - -err_map_bo_gart_failed: - amdgpu_bo_unreserve(bo); -err_reserve_bo_failed: - return ret; -} - static int mes_userq_create_wptr_mapping(struct amdgpu_device *adev, struct amdgpu_userq_mgr *uq_mgr, @@ -65,55 +37,62 @@ mes_userq_create_wptr_mapping(struct amdgpu_device *adev, uint64_t wptr) { struct amdgpu_bo_va_mapping *wptr_mapping; - struct amdgpu_vm *wptr_vm; struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj; + struct amdgpu_bo *obj; + struct amdgpu_vm *vm = queue->vm; + struct drm_exec exec; int ret; - wptr_vm = queue->vm; - ret = amdgpu_bo_reserve(wptr_vm->root.bo, false); - if (ret) - return ret; - wptr &= AMDGPU_GMC_HOLE_MASK; - wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT); - amdgpu_bo_unreserve(wptr_vm->root.bo); - if (!wptr_mapping) { - DRM_ERROR("Failed to lookup wptr bo\n"); - return -EINVAL; + + drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 2); + drm_exec_until_all_locked(&exec) { + ret = amdgpu_vm_lock_pd(vm, &exec, 1); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto fail_lock; + + wptr_mapping = amdgpu_vm_bo_lookup_mapping(vm, wptr >> PAGE_SHIFT); + if (!wptr_mapping) { + ret = -EINVAL; + goto fail_lock; + } + + obj = wptr_mapping->bo_va->base.bo; + ret = drm_exec_lock_obj(&exec, &obj->tbo.base); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto fail_lock; } - wptr_obj->obj = wptr_mapping->bo_va->base.bo; + wptr_obj->obj = amdgpu_bo_ref(wptr_mapping->bo_va->base.bo); if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) { - DRM_ERROR("Requested GART mapping for wptr bo larger than one page\n"); - return -EINVAL; - } - - ret = mes_userq_map_gtt_bo_to_gart(wptr_obj->obj); - if (ret) { - DRM_ERROR("Failed to map wptr bo to GART\n"); - return ret; - } - - ret = amdgpu_bo_reserve(wptr_obj->obj, true); - if (ret) { - DRM_ERROR("Failed to reserve wptr bo\n"); - return ret; + ret = -EINVAL; + goto fail_map; } /* TODO use eviction fence instead of pinning. */ ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT); if (ret) { - drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n"); - goto unresv_bo; + DRM_ERROR("Failed to pin wptr bo. ret %d\n", ret); + goto fail_map; + } + + ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo); + if (ret) { + DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); + goto fail_map; } queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); - amdgpu_bo_unreserve(wptr_obj->obj); + drm_exec_fini(&exec); return 0; -unresv_bo: - amdgpu_bo_unreserve(wptr_obj->obj); +fail_map: + amdgpu_bo_unref(&wptr_obj->obj); +fail_lock: + drm_exec_fini(&exec); return ret; } @@ -266,7 +245,7 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, if (found_hung_queue) { /* Resume scheduling after hang recovery */ - r = amdgpu_mes_resume(adev); + r = amdgpu_mes_resume(adev, input.xcc_id); } return r; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index cec801278126..b169e577e583 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -44,8 +44,11 @@ static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block); static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id); +static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id); #define MES_EOP_SIZE 2048 +#define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ +#define MES12_HUNG_HQD_INFO_OFFSET 4 #define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000 #define XCC_MID_MASK 0x41000000 @@ -229,7 +232,7 @@ static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, xcc_id, pipe, x_pkt->header.opcode); r = amdgpu_fence_wait_polling(ring, seq, timeout); - if (r < 1 || !*status_ptr) { + if (r < 1 || !lower_32_bits(*status_ptr)) { if (misc_op_str) dev_err(adev->dev, "MES(%d, %d) failed to respond to msg=%s (%s)\n", @@ -468,13 +471,44 @@ static int mes_v12_1_unmap_legacy_queue(struct amdgpu_mes *mes, static int mes_v12_1_suspend_gang(struct amdgpu_mes *mes, struct mes_suspend_gang_input *input) { - return 0; + union MESAPI__SUSPEND mes_suspend_gang_pkt; + + memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); + + mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; + mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; + mes_suspend_gang_pkt.suspend_all_sdma_gangs = input->suspend_all_sdma_gangs; + mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; + mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; + mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; + + /* Suspend gang is handled by master MES */ + return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE, + &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), + offsetof(union MESAPI__SUSPEND, api_status)); } static int mes_v12_1_resume_gang(struct amdgpu_mes *mes, struct mes_resume_gang_input *input) { - return 0; + union MESAPI__RESUME mes_resume_gang_pkt; + + memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); + + mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; + mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; + mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; + + /* Resume gang is handled by master MES */ + return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE, + &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), + offsetof(union MESAPI__RESUME, api_status)); } static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes, @@ -621,11 +655,15 @@ static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; - if (mes->enable_coop_mode && pipe == AMDGPU_MES_SCHED_PIPE) { + /* From version 0x74 above, pipe1 support use shared command buffer + to distribute some tasks on individual XCCs*/ + if (mes->enable_coop_mode && + ((pipe == AMDGPU_MES_SCHED_PIPE) || + ((mes->kiq_version & AMDGPU_MES_VERSION_MASK) >= 0x74))) { master_xcc_id = mes->master_xcc_ids[inst]; mes_set_hw_res_1_pkt.mes_coop_mode = 1; mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr = - mes->shared_cmd_buf_gpu_addr[master_xcc_id]; + mes->shared_cmd_buf_gpu_addr[master_xcc_id + pipe]; } return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, @@ -633,21 +671,10 @@ static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); } -static void mes_v12_1_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt) -{ - /* - * GFX V12 has only one GFX pipe, but 8 queues in it. - * GFX pipe 0 queue 0 is being used by Kernel queue. - * Set GFX pipe 0 queue 1-7 for MES scheduling - * mask = 1111 1110b - */ - pkt->gfx_hqd_mask[0] = 0xFE; -} - static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, int pipe, int xcc_id) { - int i; + int i, status; struct amdgpu_device *adev = mes->adev; union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; @@ -667,7 +694,9 @@ static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, mes_set_hw_res_pkt.compute_hqd_mask[i] = mes->compute_hqd_mask[i]; - mes_v12_1_set_gfx_hqd_mask(&mes_set_hw_res_pkt); + for (i = 0; i < MAX_GFX_PIPES; i++) + mes_set_hw_res_pkt.gfx_hqd_mask[i] = + mes->gfx_hqd_mask[i]; for (i = 0; i < MAX_SDMA_PIPES; i++) mes_set_hw_res_pkt.sdma_hqd_mask[i] = @@ -715,9 +744,23 @@ static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) mes_set_hw_res_pkt.limit_single_process = 1; - return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, + status = mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); + + /* get MES scheduler versions */ + mutex_lock(&adev->srbm_mutex); + soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); + + if (pipe == AMDGPU_MES_SCHED_PIPE) + adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); + else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) + adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); + + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); + + return status; } static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes, @@ -837,6 +880,33 @@ static int mes_v12_1_reset_legacy_queue(struct amdgpu_mes *mes, } #endif +static int mes_v12_1_detect_and_reset_hung_queues(struct amdgpu_mes *mes, + struct mes_detect_and_reset_queue_input *input) +{ + union MESAPI__RESET mes_reset_queue_pkt; + + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); + + mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; + mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_reset_queue_pkt.queue_type = + convert_to_mes_queue_type(input->queue_type); + mes_reset_queue_pkt.doorbell_offset_addr = + mes->hung_queue_db_array_gpu_addr[0]; + + if (input->detect_only) + mes_reset_queue_pkt.hang_detect_only = 1; + else + mes_reset_queue_pkt.hang_detect_then_reset = 1; + + return mes_v12_1_submit_pkt_and_poll_completion(mes, + input->xcc_id, AMDGPU_MES_SCHED_PIPE, + &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), + offsetof(union MESAPI__RESET, api_status)); +} + static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) { /* @@ -894,6 +964,7 @@ static const struct amdgpu_mes_funcs mes_v12_1_funcs = { .resume_gang = mes_v12_1_resume_gang, .misc_op = mes_v12_1_misc_op, .reset_hw_queue = mes_v12_1_reset_hw_queue, + .detect_and_reset_hung_queues = mes_v12_1_detect_and_reset_hung_queues, .invalidate_tlbs_pasid = mes_v12_1_inv_tlbs_pasid, }; @@ -1157,9 +1228,6 @@ static int mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device *adev, { int r, inst = MES_PIPE_INST(xcc_id, pipe); - if (pipe == AMDGPU_MES_KIQ_PIPE) - return 0; - r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, &adev->mes.shared_cmd_buf_obj[inst], @@ -1405,18 +1473,6 @@ static int mes_v12_1_queue_init(struct amdgpu_device *adev, mes_v12_1_queue_init_register(ring, xcc_id); } - /* get MES scheduler/KIQ versions */ - mutex_lock(&adev->srbm_mutex); - soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); - - if (pipe == AMDGPU_MES_SCHED_PIPE) - adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); - else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) - adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); - - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); - mutex_unlock(&adev->srbm_mutex); - return 0; } @@ -1723,6 +1779,10 @@ static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) goto failure; if (adev->enable_uni_mes) { + r = mes_v12_1_setup_coop_mode(adev, xcc_id); + if (r) + goto failure; + r = mes_v12_1_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE, xcc_id); if (r) @@ -1845,9 +1905,6 @@ static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id) goto failure; if (adev->enable_uni_mes) { - r = mes_v12_1_setup_coop_mode(adev, xcc_id); - if (r) - goto failure; mes_v12_1_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE, xcc_id); } @@ -1897,24 +1954,12 @@ static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) static int mes_v12_1_suspend(struct amdgpu_ip_block *ip_block) { - int r; - - r = amdgpu_mes_suspend(ip_block->adev); - if (r) - return r; - return mes_v12_1_hw_fini(ip_block); } static int mes_v12_1_resume(struct amdgpu_ip_block *ip_block) { - int r; - - r = mes_v12_1_hw_init(ip_block); - if (r) - return r; - - return amdgpu_mes_resume(ip_block->adev); + return mes_v12_1_hw_init(ip_block); } static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) @@ -1922,6 +1967,9 @@ static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int pipe, r; + adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; + adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { r = amdgpu_mes_init_microcode(adev, pipe); if (r) @@ -2016,7 +2064,7 @@ static int mes_v12_1_map_test_bo(struct amdgpu_device *adev, error: amdgpu_sync_free(&sync); - return 0; + return r; } static int mes_v12_1_test_ring(struct amdgpu_device *adev, int xcc_id, diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c index b6f832c53860..28a99b52f59f 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c @@ -144,10 +144,13 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, { u32 doorbell_range; - if (instance) + if (instance) { + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) + return; doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); - else + } else { doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL); + } if (use_doorbell) { doorbell_range = REG_SET_FIELD(doorbell_range, @@ -177,10 +180,7 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, 0); if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { - if (instance) - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range); - else - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, doorbell_range); } else { if (instance) WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); @@ -189,6 +189,51 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, } } +static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev, + int instance, bool use_doorbell, + int doorbell_index, + int doorbell_size) +{ + if (instance) + return; + + u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); + + if (use_doorbell) { + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_ENABLE, + 0x1); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_AWID, + 0xf); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_RANGE_OFFSET, + doorbell_index); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_RANGE_SIZE, + doorbell_size); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE, + 0xf); + } else { + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_RANGE_SIZE, + 0); + } + + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range); + else + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); + +} + static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) { if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { @@ -517,6 +562,7 @@ const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = { .get_memsize = nbif_v6_3_1_get_memsize, .sdma_doorbell_range = nbif_v6_3_1_sdma_doorbell_range, .vcn_doorbell_range = nbif_v6_3_1_vcn_doorbell_range, + .vpe_doorbell_range = nbif_v6_3_1_vpe_doorbell_range, .gc_doorbell_init = nbif_v6_3_1_gc_doorbell_init, .enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture, .enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture, diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c new file mode 100644 index 000000000000..5e8f466f23ad --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c @@ -0,0 +1,369 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "nbio/nbio_6_3_2_offset.h" +#include "nbio/nbio_6_3_2_sh_mask.h" + +#include "amdgpu.h" +#include "nbio_v6_3_2.h" + +static u32 nbio_v6_3_2_get_pcie_index_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); +} + +static u32 nbio_v6_3_2_get_pcie_data_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); +} + +static u32 nbio_v6_3_2_get_pcie_index_hi_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI); +} + +static u32 nbio_v6_3_2_get_rev_id(struct amdgpu_device *adev) +{ + u32 tmp; + + /* TODO: RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 is not accessible from + * guest side. It requires bootloader to update specific fields + * in ip discovery table to identify soc revision id. + * Return 0 when the function is called from guest side until + * bootloader change is available. + */ + if (amdgpu_sriov_vf(adev)) + return 0; + + tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); + tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, + STRAP_ATI_REV_ID_DEV0_F0); + + return tmp; +} + +static void nbio_v6_3_2_mc_access_enable(struct amdgpu_device *adev, + bool enable) +{ + if (enable) + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, + BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); + else + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); +} + +static void nbio_v6_3_2_init_registers(struct amdgpu_device *adev) +{ + WREG32_SOC15(NBIO, 0, regXCD_DOORBELL_FENCE_1, + (0xff & ~(adev->gfx.xcc_mask)) << + XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE__SHIFT); +} + +static u32 nbio_v6_3_2_get_memsize(struct amdgpu_device *adev) +{ + return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); +} + +static void nbio_v6_3_2_enable_doorbell_aperture(struct amdgpu_device *adev, + bool enable) +{ + /* Enable to allow doorbell pass thru on pre-silicon bare-metal */ + WREG32_SOC15(NBIO, 0, regGDC0_DOORBELL_ACCESS_EN_PF, 0xfffff); + WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, + BIF_DOORBELL_APER_EN, enable ? 1 : 0); +} + +static void nbio_v6_3_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, + bool enable) +{ + u32 tmp = 0; + + if (enable) { + tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, + DOORBELL_SELFRING_GPA_APER_EN, 1) | + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, + DOORBELL_SELFRING_GPA_APER_MODE, 1) | + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, + DOORBELL_SELFRING_GPA_APER_SIZE, 0); + + WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, + lower_32_bits(adev->doorbell.base)); + WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, + upper_32_bits(adev->doorbell.base)); + } + + WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); +} + +static void nbio_v6_3_2_enable_doorbell_interrupt(struct amdgpu_device *adev, + bool enable) +{ + WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL, + DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); +} + +static void nbio_v6_3_2_ih_control(struct amdgpu_device *adev) +{ + u32 interrupt_cntl; + + /* setup interrupt control */ + WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); + + interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); + /* + * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi + * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN + */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, + IH_DUMMY_RD_OVERRIDE, 0); + + /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, + IH_REQ_NONSNOOP_EN, 0); + + WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); +} + +static void nbio_v6_3_2_ih_doorbell_range(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index) +{ + u32 ih_doorbell_range = 0; + u32 ih_doorbell_range1 = 0; + + if (use_doorbell) { + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, + S2A_DOORBELL_PORT1_ENABLE, + 0x1); + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, + S2A_DOORBELL_PORT1_AWID, + 0x0); + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, + S2A_DOORBELL_PORT1_RANGE_OFFSET, + doorbell_index); + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, + S2A_DOORBELL_PORT1_RANGE_SIZE, + 8); + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, + S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, + 0x0); + ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1, + S2A_DOORBELL_PORT1_TARGET_PORT_TYPE, + 0x3); + ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1, + S2A_DOORBELL_PORT1_TARGET_DIEID, + 0x0); + ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1, + S2A_DOORBELL_PORT1_TARGET_PORT_ID, + 0x0); + } + + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1, ih_doorbell_range1); +} + +static void nbio_v6_3_2_gc_doorbell_init(struct amdgpu_device *adev) +{ + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1, 0x3); +} + +static void nbio_v6_3_2_sdma_doorbell_range(struct amdgpu_device *adev, + int instance, bool use_doorbell, + int doorbell_index, + int doorbell_size) +{ + if (instance == 0) { + u32 doorbell_range = 0; + u32 doorbell_range1 = 0; + + if (use_doorbell) { + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, + S2A_DOORBELL_PORT6_ENABLE, + 0x1); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, + S2A_DOORBELL_PORT6_AWID, + 0xe); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, + S2A_DOORBELL_PORT6_RANGE_OFFSET, + doorbell_index); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, + S2A_DOORBELL_PORT6_RANGE_SIZE, + doorbell_size); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, + S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE, + 0xe); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, + S2A_DOORBELL_PORT6_TARGET_PORT_TYPE, + 0x3); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, + S2A_DOORBELL_PORT6_TARGET_DIEID, + 0x0); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, + S2A_DOORBELL_PORT6_TARGET_PORT_ID, + 0x0); + } + + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, doorbell_range1); + } +} + +static void nbio_v6_3_2_vcn_doorbell_range(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index, + int instance) +{ + u32 doorbell_range = 0; + u32 doorbell_range1 = 0; + + if (use_doorbell) { + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, + S2A_DOORBELL_PORT2_ENABLE, + 0x1); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, + S2A_DOORBELL_PORT2_AWID, + (instance % adev->vcn.num_inst_per_aid) ? 0x7 : 0x4); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, + S2A_DOORBELL_PORT2_RANGE_OFFSET, + doorbell_index); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, + S2A_DOORBELL_PORT2_RANGE_SIZE, + 8); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, + S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, + (instance % adev->vcn.num_inst_per_aid) ? 0x7 : 0x4); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, + S2A_DOORBELL_PORT2_TARGET_PORT_TYPE, + 0x3); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, + S2A_DOORBELL_PORT2_TARGET_DIEID, + (instance / adev->vcn.num_inst_per_aid) ? 0x3 : 0x0); + doorbell_range1 = REG_SET_FIELD(doorbell_range1, + GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, + S2A_DOORBELL_PORT2_TARGET_PORT_ID, + 0x0); + } + + switch (instance) { + case 0: + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, doorbell_range1); + break; + case 1: + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1, doorbell_range1); + break; + case 2: + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1, doorbell_range1); + break; + case 3: + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1, doorbell_range1); + break; + default: + dev_err(adev->dev, + "amdgpu: invalid vcn instance set when program doorbell range\n"); + break; + } +} + +static int nbio_v6_3_2_get_compute_partition_mode(struct amdgpu_device *adev) +{ + u32 tmp, px; + + tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS); + px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS, + PARTITION_MODE); + + return px; +} + +static bool nbio_v6_3_2_is_nps_switch_requested(struct amdgpu_device *adev) +{ + u32 tmp; + + tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); + tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, + CHANGE_STATUS); + + /* 0x8 - NPS switch requested */ + return (tmp == 0x8); +} +static u32 nbio_v6_3_2_get_memory_partition_mode(struct amdgpu_device *adev, + u32 *supp_modes) +{ + u32 tmp; + + tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); + tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE); + + if (supp_modes) { + *supp_modes = + RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP); + } + + return ffs(tmp); +} + +const struct amdgpu_nbio_funcs nbio_v6_3_2_funcs = { + .get_pcie_index_offset = nbio_v6_3_2_get_pcie_index_offset, + .get_pcie_data_offset = nbio_v6_3_2_get_pcie_data_offset, + .get_pcie_index_hi_offset = nbio_v6_3_2_get_pcie_index_hi_offset, + .get_rev_id = nbio_v6_3_2_get_rev_id, + .mc_access_enable = nbio_v6_3_2_mc_access_enable, + .get_memsize = nbio_v6_3_2_get_memsize, + .enable_doorbell_aperture = nbio_v6_3_2_enable_doorbell_aperture, + .enable_doorbell_selfring_aperture = nbio_v6_3_2_enable_doorbell_selfring_aperture, + .enable_doorbell_interrupt = nbio_v6_3_2_enable_doorbell_interrupt, + .get_compute_partition_mode = nbio_v6_3_2_get_compute_partition_mode, + .get_memory_partition_mode = nbio_v6_3_2_get_memory_partition_mode, + .is_nps_switch_requested = nbio_v6_3_2_is_nps_switch_requested, + .ih_control = nbio_v6_3_2_ih_control, + .ih_doorbell_range = nbio_v6_3_2_ih_doorbell_range, + .gc_doorbell_init = nbio_v6_3_2_gc_doorbell_init, + .sdma_doorbell_range = nbio_v6_3_2_sdma_doorbell_range, + .vcn_doorbell_range = nbio_v6_3_2_vcn_doorbell_range, + .init_registers = nbio_v6_3_2_init_registers, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h new file mode 100644 index 000000000000..bc7f747c88f4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h @@ -0,0 +1,31 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __NBIO_V6_3_2_H__ +#define __NBIO_V6_3_2_H__ + +#include "soc15_common.h" + +extern const struct amdgpu_nbio_funcs nbio_v6_3_2_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 7ce1a1b95606..72edf5326b05 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -354,29 +354,12 @@ static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, }; -static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, - u32 sh_num, u32 reg_offset) -{ - uint32_t val; - - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); - - val = RREG32(reg_offset); - - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); - mutex_unlock(&adev->grbm_idx_mutex); - return val; -} - static uint32_t nv_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { if (indexed) { - return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); + return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) return adev->gfx.config.gb_addr_config; @@ -511,16 +494,6 @@ static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) return 0; } -static void nv_program_aspm(struct amdgpu_device *adev) -{ - if (!amdgpu_device_should_use_aspm(adev)) - return; - - if (adev->nbio.funcs->program_aspm) - adev->nbio.funcs->program_aspm(adev); - -} - const struct amdgpu_ip_block_version nv_common_ip_block = { .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 1, @@ -984,7 +957,7 @@ static int nv_common_hw_init(struct amdgpu_ip_block *ip_block) adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); /* enable aspm */ - nv_program_aspm(adev); + amdgpu_nbio_program_aspm(adev); /* setup nbio registers */ adev->nbio.funcs->init_registers(adev); /* remap HDP registers to a hole in mmio space, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index e8f768638fd5..ac34bac3c839 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -107,6 +107,7 @@ enum psp_gfx_cmd_id GFX_CMD_ID_CONFIG_SQ_PERFMON = 0x00000046, /* Config CGTT_SQ_CLK_CTRL */ /* Dynamic memory partitioninig (NPS mode change)*/ GFX_CMD_ID_FB_NPS_MODE = 0x00000048, /* Configure memory partitioning mode */ + GFX_CMD_ID_PERF_HW = 0x0000004C, /* performance monitor */ GFX_CMD_ID_FB_FW_RESERV_ADDR = 0x00000050, /* Query FW reservation addr */ GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR = 0x00000051, /* Query FW reservation extended addr */ }; @@ -373,6 +374,13 @@ struct psp_gfx_cmd_fb_memory_part { uint32_t resvd; }; +struct psp_gfx_cmd_req_perf_hw { + uint32_t req; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + /* All GFX ring buffer commands. */ union psp_gfx_commands { @@ -389,6 +397,7 @@ union psp_gfx_commands struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part; struct psp_gfx_cmd_config_sq_perfmon config_sq_perfmon; struct psp_gfx_cmd_fb_memory_part cmd_memory_part; + struct psp_gfx_cmd_req_perf_hw cmd_req_perf_hw; }; struct psp_gfx_uresp_reserved @@ -415,12 +424,20 @@ struct psp_gfx_uresp_fw_reserve_info { uint32_t reserve_size; }; +struct psp_gfx_uresp_perf_hw { + uint32_t resp; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + /* Union of command-specific responses for GPCOM ring. */ union psp_gfx_uresp { struct psp_gfx_uresp_reserved reserved; struct psp_gfx_uresp_bootcfg boot_cfg; struct psp_gfx_uresp_fwar_db_info fwar_db_info; struct psp_gfx_uresp_fw_reserve_info fw_reserve_info; + struct psp_gfx_uresp_perf_hw perf_hw_info; }; /* Structure of GFX Response buffer. diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index fb7aaf5ae05c..479690c44f0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -217,7 +217,9 @@ static int psp_v11_0_bootloader_load_component(struct psp_context *psp, return ret; /* Copy PSP System Driver binary to memory */ - psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); + ret = psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); + if (ret) + return ret; /* Provide the sys driver to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, @@ -263,7 +265,9 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) return ret; /* Copy Secure OS binary to PSP memory */ - psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); + ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); + if (ret) + return ret; /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c index c3cae29eeca1..f823f042788d 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c @@ -87,7 +87,9 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) return ret; /* Copy PSP System Driver binary to memory */ - psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes); + ret = psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes); + if (ret) + return ret; /* Provide the sys driver to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, @@ -123,7 +125,9 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) return ret; /* Copy Secure OS binary to PSP memory */ - psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); + ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); + if (ret) + return ret; /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index a0c84f81c0c9..00b4a34e6601 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -271,10 +271,9 @@ static int psp_v13_0_bootloader_load_component(struct psp_context *psp, if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - - /* Copy PSP KDB binary to memory */ - memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); + ret = psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); + if (ret) + return ret; /* Provide the PSP KDB to bootloader */ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, @@ -353,10 +352,9 @@ static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - - /* Copy Secure OS binary to PSP memory */ - memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); + ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); + if (ret) + return ret; /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c index 5f39a2edcc95..3d5e26b3fa00 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c @@ -105,10 +105,9 @@ static int psp_v13_0_4_bootloader_load_component(struct psp_context *psp, if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - - /* Copy PSP KDB binary to memory */ - memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); + ret = psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); + if (ret) + return ret; /* Provide the PSP KDB to bootloader */ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, @@ -168,10 +167,9 @@ static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - - /* Copy Secure OS binary to PSP memory */ - memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); + ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); + if (ret) + return ret; /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c index 38dfc5c19f2a..040a61aefa86 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c @@ -140,10 +140,9 @@ static int psp_v14_0_bootloader_load_component(struct psp_context *psp, if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - - /* Copy PSP KDB binary to memory */ - memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); + ret = psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); + if (ret) + return ret; /* Provide the PSP KDB to bootloader */ WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, @@ -214,10 +213,9 @@ static int psp_v14_0_bootloader_load_sos(struct psp_context *psp) if (ret) return ret; - memset(psp->fw_pri_buf, 0, PSP_1_MEG); - - /* Copy Secure OS binary to PSP memory */ - memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); + ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); + if (ret) + return ret; /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c index b2d7cbd894c0..ec20cd5eb755 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c @@ -32,6 +32,7 @@ #include "mp/mp_15_0_8_sh_mask.h" MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc.bin"); +MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc_1.bin"); static int psp_v15_0_8_init_microcode(struct psp_context *psp) { diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index f5030efc6c80..24856c91c135 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -96,7 +96,9 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) return ret; /* Copy PSP System Driver binary to memory */ - psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes); + ret = psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes); + if (ret) + return ret; /* Provide the sys driver to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, @@ -135,7 +137,9 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) return ret; /* Copy Secure OS binary to PSP memory */ - psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); + ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); + if (ret) + return ret; /* Provide the PSP secure OS to bootloader */ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 0090ace49024..93ec52c1f367 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -828,7 +828,6 @@ static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block) return r; sdma_v2_4_set_ring_funcs(adev); - sdma_v2_4_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v2_4_vm_pte_funcs); sdma_v2_4_set_irq_funcs(adev); @@ -898,7 +897,9 @@ static int sdma_v2_4_hw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - return r; + sdma_v2_4_set_buffer_funcs(adev); + + return 0; } static int sdma_v2_4_hw_fini(struct amdgpu_ip_block *ip_block) @@ -1235,8 +1236,7 @@ static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v2_4_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v2_4_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 2526d393162a..3fde9be74690 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1108,7 +1108,6 @@ static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) return r; sdma_v3_0_set_ring_funcs(adev); - sdma_v3_0_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs); sdma_v3_0_set_irq_funcs(adev); @@ -1184,7 +1183,9 @@ static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - return r; + sdma_v3_0_set_buffer_funcs(adev); + + return 0; } static int sdma_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) @@ -1677,8 +1678,7 @@ static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v3_0_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v3_0_ip_block = diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 44f0f23e1148..cb64d17000df 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -889,7 +889,7 @@ static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se /* write the fence */ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); /* zero in first two bits */ - BUG_ON(addr & 0x3); + WARN_ON(addr & 0x3); amdgpu_ring_write(ring, lower_32_bits(addr)); amdgpu_ring_write(ring, upper_32_bits(addr)); amdgpu_ring_write(ring, lower_32_bits(seq)); @@ -899,7 +899,7 @@ static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se addr += 4; amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); /* zero in first two bits */ - BUG_ON(addr & 0x3); + WARN_ON(addr & 0x3); amdgpu_ring_write(ring, lower_32_bits(addr)); amdgpu_ring_write(ring, upper_32_bits(addr)); amdgpu_ring_write(ring, upper_32_bits(seq)); @@ -1775,7 +1775,6 @@ static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block) adev->sdma.has_page_queue = true; sdma_v4_0_set_ring_funcs(adev); - sdma_v4_0_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_0_vm_pte_funcs); sdma_v4_0_set_irq_funcs(adev); sdma_v4_0_set_ras_funcs(adev); @@ -1961,6 +1960,7 @@ static int sdma_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; if (adev->flags & AMD_IS_APU) amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0); @@ -1968,7 +1968,12 @@ static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block) if (!amdgpu_sriov_vf(adev)) sdma_v4_0_init_golden_registers(adev); - return sdma_v4_0_start(adev); + r = sdma_v4_0_start(adev); + if (r) + return r; + sdma_v4_0_set_buffer_funcs(adev); + + return 0; } static int sdma_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) @@ -2626,13 +2631,9 @@ static const struct amdgpu_buffer_funcs sdma_v4_4_buffer_funcs = { static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) { if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= IP_VERSION(4, 4, 0)) - adev->mman.buffer_funcs = &sdma_v4_4_buffer_funcs; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_buffer_funcs); else - adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; - if (adev->sdma.has_page_queue) - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; - else - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_0_buffer_funcs); } static void sdma_v4_0_get_ras_error_count(uint32_t value, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 78bdfed0a7fd..88428b88e00f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1368,7 +1368,6 @@ static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) adev->sdma.has_page_queue = true; sdma_v4_4_2_set_ring_funcs(adev); - sdma_v4_4_2_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs); sdma_v4_4_2_set_irq_funcs(adev); sdma_v4_4_2_set_ras_funcs(adev); @@ -1568,8 +1567,11 @@ static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); r = sdma_v4_4_2_inst_start(adev, inst_mask, false); + if (r) + return r; + sdma_v4_4_2_set_buffer_funcs(adev); - return r; + return 0; } static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) @@ -2316,11 +2318,7 @@ static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; - if (adev->sdma.has_page_queue) - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; - else - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_2_buffer_funcs); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 52f4e9e099cb..fa02907217e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1373,7 +1373,6 @@ static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) return r; sdma_v5_0_set_ring_funcs(adev); - sdma_v5_0_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_0_vm_pte_funcs); sdma_v5_0_set_irq_funcs(adev); sdma_v5_0_set_mqd_funcs(adev); @@ -1472,8 +1471,11 @@ static int sdma_v5_0_hw_init(struct amdgpu_ip_block *ip_block) sdma_v5_0_init_golden_registers(adev); r = sdma_v5_0_start(adev); + if (r) + return r; + sdma_v5_0_set_buffer_funcs(adev); - return r; + return 0; } static int sdma_v5_0_hw_fini(struct amdgpu_ip_block *ip_block) @@ -2052,10 +2054,7 @@ static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) { - if (adev->mman.buffer_funcs == NULL) { - adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; - } + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v5_0_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index b4fb90cc8f7d..f6ecbc524c9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1264,7 +1264,6 @@ static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block) return r; sdma_v5_2_set_ring_funcs(adev); - sdma_v5_2_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_2_vm_pte_funcs); sdma_v5_2_set_irq_funcs(adev); sdma_v5_2_set_mqd_funcs(adev); @@ -1385,8 +1384,14 @@ static int sdma_v5_2_sw_fini(struct amdgpu_ip_block *ip_block) static int sdma_v5_2_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; - return sdma_v5_2_start(adev); + r = sdma_v5_2_start(adev); + if (r) + return r; + sdma_v5_2_set_buffer_funcs(adev); + + return 0; } static int sdma_v5_2_hw_fini(struct amdgpu_ip_block *ip_block) @@ -2056,10 +2061,7 @@ static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) { - if (adev->mman.buffer_funcs == NULL) { - adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; - } + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v5_2_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 0f530bb8a9a3..bf09ac841a68 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1313,7 +1313,6 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) return r; sdma_v6_0_set_ring_funcs(adev); - sdma_v6_0_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v6_0_vm_pte_funcs); sdma_v6_0_set_irq_funcs(adev); sdma_v6_0_set_mqd_funcs(adev); @@ -1477,6 +1476,7 @@ static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block) r = sdma_v6_0_start(adev); if (r) return r; + sdma_v6_0_set_buffer_funcs(adev); return sdma_v6_0_set_userq_trap_interrupts(adev, true); } @@ -1662,17 +1662,8 @@ static int sdma_v6_0_process_fence_irq(struct amdgpu_device *adev, u32 doorbell_offset = entry->src_data[0]; if (adev->enable_mes && doorbell_offset) { - struct amdgpu_usermode_queue *queue; - struct xarray *xa = &adev->userq_doorbell_xa; - unsigned long flags; - doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; - - xa_lock_irqsave(xa, flags); - queue = xa_load(xa, doorbell_offset); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - xa_unlock_irqrestore(xa, flags); + amdgpu_userq_process_fence_irq(adev, doorbell_offset); } return 0; @@ -1895,8 +1886,7 @@ static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v6_0_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 9ed817b69a3b..f154b68dda70 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1299,7 +1299,6 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) } sdma_v7_0_set_ring_funcs(adev); - sdma_v7_0_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_0_vm_pte_funcs); sdma_v7_0_set_irq_funcs(adev); sdma_v7_0_set_mqd_funcs(adev); @@ -1432,6 +1431,7 @@ static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block) r = sdma_v7_0_start(adev); if (r) return r; + sdma_v7_0_set_buffer_funcs(adev); return sdma_v7_0_set_userq_trap_interrupts(adev, true); } @@ -1594,17 +1594,8 @@ static int sdma_v7_0_process_fence_irq(struct amdgpu_device *adev, u32 doorbell_offset = entry->src_data[0]; if (adev->enable_mes && doorbell_offset) { - struct xarray *xa = &adev->userq_doorbell_xa; - struct amdgpu_usermode_queue *queue; - unsigned long flags; - doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; - - xa_lock_irqsave(xa, flags); - queue = xa_load(xa, doorbell_offset); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - xa_unlock_irqrestore(xa, flags); + amdgpu_userq_process_fence_irq(adev, doorbell_offset); } return 0; @@ -1845,8 +1836,7 @@ static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = { static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v7_0_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v7_0_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index 061934a2e93a..e1c0a4ff0e7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -1287,7 +1287,6 @@ static int sdma_v7_1_early_init(struct amdgpu_ip_block *ip_block) } sdma_v7_1_set_ring_funcs(adev); - sdma_v7_1_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_1_vm_pte_funcs); sdma_v7_1_set_irq_funcs(adev); sdma_v7_1_set_mqd_funcs(adev); @@ -1386,10 +1385,16 @@ static int sdma_v7_1_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; uint32_t inst_mask; + int r; inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); - return sdma_v7_1_inst_start(adev, inst_mask); + r = sdma_v7_1_inst_start(adev, inst_mask); + if (r) + return r; + sdma_v7_1_set_buffer_funcs(adev); + + return 0; } static int sdma_v7_1_hw_fini(struct amdgpu_ip_block *ip_block) @@ -1776,8 +1781,7 @@ static const struct amdgpu_buffer_funcs sdma_v7_1_buffer_funcs = { static void sdma_v7_1_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v7_1_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v7_1_buffer_funcs); } const struct amdgpu_ip_block_version sdma_v7_1_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 3e58feb2d5e4..549708075eb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -487,7 +487,6 @@ static int si_dma_early_init(struct amdgpu_ip_block *ip_block) adev->sdma.num_instances = SDMA_MAX_INSTANCE; si_dma_set_ring_funcs(adev); - si_dma_set_buffer_funcs(adev); amdgpu_sdma_set_vm_pte_scheds(adev, &si_dma_vm_pte_funcs); si_dma_set_irq_funcs(adev); @@ -543,8 +542,14 @@ static int si_dma_sw_fini(struct amdgpu_ip_block *ip_block) static int si_dma_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; - return si_dma_start(adev); + r = si_dma_start(adev); + if (r) + return r; + si_dma_set_buffer_funcs(adev); + + return 0; } static int si_dma_hw_fini(struct amdgpu_ip_block *ip_block) @@ -833,8 +838,7 @@ static const struct amdgpu_buffer_funcs si_dma_buffer_funcs = { static void si_dma_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &si_dma_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + amdgpu_sdma_set_buffer_funcs_scheds(adev, &si_dma_buffer_funcs); } const struct amdgpu_ip_block_version si_dma_ip_block = diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index b456e4541d9a..87b398dd0769 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -401,29 +401,12 @@ static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, }; -static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, - u32 sh_num, u32 reg_offset) -{ - uint32_t val; - - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); - - val = RREG32(reg_offset); - - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); - mutex_unlock(&adev->grbm_idx_mutex); - return val; -} - static uint32_t soc15_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { if (indexed) { - return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); + return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) return adev->gfx.config.gb_addr_config; @@ -695,15 +678,6 @@ static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk return 0; } -static void soc15_program_aspm(struct amdgpu_device *adev) -{ - if (!amdgpu_device_should_use_aspm(adev)) - return; - - if (adev->nbio.funcs->program_aspm) - adev->nbio.funcs->program_aspm(adev); -} - const struct amdgpu_ip_block_version vega10_common_ip_block = { .type = AMD_IP_BLOCK_TYPE_COMMON, @@ -1284,7 +1258,7 @@ static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; /* enable aspm */ - soc15_program_aspm(adev); + amdgpu_nbio_program_aspm(adev); /* setup nbio registers */ adev->nbio.funcs->init_registers(adev); /* remap HDP registers to a hole in mmio space, diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index fbd1d97f33ad..93c002e511c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -306,29 +306,12 @@ static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, }; -static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, - u32 sh_num, u32 reg_offset) -{ - uint32_t val; - - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); - - val = RREG32(reg_offset); - - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); - mutex_unlock(&adev->grbm_idx_mutex); - return val; -} - static uint32_t soc21_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { if (indexed) { - return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); + return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) return adev->gfx.config.gb_addr_config; @@ -470,15 +453,6 @@ static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk return 0; } -static void soc21_program_aspm(struct amdgpu_device *adev) -{ - if (!amdgpu_device_should_use_aspm(adev)) - return; - - if (adev->nbio.funcs->program_aspm) - adev->nbio.funcs->program_aspm(adev); -} - const struct amdgpu_ip_block_version soc21_common_ip_block = { .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 1, @@ -925,7 +899,7 @@ static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; /* enable aspm */ - soc21_program_aspm(adev); + amdgpu_nbio_program_aspm(adev); /* setup nbio registers */ adev->nbio.funcs->init_registers(adev); /* remap HDP registers to a hole in mmio space, diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index d1adf19a51c4..265db9331d0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -132,31 +132,12 @@ static struct soc15_allowed_register_entry soc24_allowed_read_registers[] = { { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, }; -static uint32_t soc24_read_indexed_register(struct amdgpu_device *adev, - u32 se_num, - u32 sh_num, - u32 reg_offset) -{ - uint32_t val; - - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); - - val = RREG32(reg_offset); - - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); - mutex_unlock(&adev->grbm_idx_mutex); - return val; -} - static uint32_t soc24_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { if (indexed) { - return soc24_read_indexed_register(adev, se_num, sh_num, reg_offset); + return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 709b1669b07b..5f05c8e68297 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -184,31 +184,13 @@ static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = { { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) }, }; -static uint32_t soc_v1_0_read_indexed_register(struct amdgpu_device *adev, - u32 se_num, - u32 sh_num, - u32 reg_offset) -{ - uint32_t val; - - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); - - val = RREG32(reg_offset); - - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); - mutex_unlock(&adev->grbm_idx_mutex); - return val; -} static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { if (indexed) { - return soc_v1_0_read_indexed_register(adev, se_num, sh_num, reg_offset); + return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); } else { if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) && adev->gfx.config.gb_addr_config) @@ -330,6 +312,8 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) return -EINVAL; } + adev->nbio.funcs->init_registers(adev); + return 0; } @@ -737,15 +721,8 @@ static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode); if (adev->gfx.imu.funcs && - adev->gfx.imu.funcs->switch_compute_partition) { - ret = adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); - if (ret) - goto out; - } - if (adev->gfx.imu.funcs && - adev->gfx.imu.funcs->init_mcm_addr_lut && - amdgpu_emu_mode) - adev->gfx.imu.funcs->init_mcm_addr_lut(adev); + adev->gfx.imu.funcs->switch_compute_partition) + adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); /* Init info about new xcps */ *num_xcps = num_xcc / num_xcc_per_xcp; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index fea576a7f397..efb3fde919ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -242,6 +242,10 @@ static void uvd_v3_1_mc_resume(struct amdgpu_device *adev) uint64_t addr; uint32_t size; + /* When the keyselect is already set, don't perturb it. */ + if (RREG32(mmUVD_FW_START)) + return; + /* program the VCPU memory controller bits 0-27 */ addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; @@ -284,6 +288,12 @@ static int uvd_v3_1_fw_validate(struct amdgpu_device *adev) int i; uint32_t keysel = adev->uvd.keyselect; + if (RREG32(mmUVD_FW_START) & UVD_FW_STATUS__PASS_MASK) { + dev_dbg(adev->dev, "UVD keyselect already set: 0x%x (on CPU: 0x%x)\n", + RREG32(mmUVD_FW_START), adev->uvd.keyselect); + return 0; + } + WREG32(mmUVD_FW_START, keysel); for (i = 0; i < 10; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c index 5b7b46d242c6..93253db5e2de 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c @@ -42,9 +42,10 @@ #include "oss/oss_1_0_d.h" #include "oss/oss_1_0_sh_mask.h" +#define VCE_V1_0_ALIGNMENT (32 * 1024) #define VCE_V1_0_FW_SIZE (256 * 1024) #define VCE_V1_0_STACK_SIZE (64 * 1024) -#define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1)) +#define VCE_V1_0_DATA_SIZE (ALIGN(7808 * (AMDGPU_MAX_VCE_HANDLES + 1), VCE_V1_0_ALIGNMENT)) #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev); @@ -177,7 +178,7 @@ static void vce_v1_0_init_cg(struct amdgpu_device *adev) } /** - * vce_v1_0_load_fw_signature - load firmware signature into VCPU BO + * vce_v1_0_load_fw() - load firmware signature into VCPU BO * * @adev: amdgpu_device pointer * @@ -185,21 +186,26 @@ static void vce_v1_0_init_cg(struct amdgpu_device *adev) * This function finds the signature appropriate for the current * ASIC and writes that into the VCPU BO. */ -static int vce_v1_0_load_fw_signature(struct amdgpu_device *adev) +static int vce_v1_0_load_fw(struct amdgpu_device *adev) { const struct common_firmware_header *hdr; struct vce_v1_0_fw_signature *sign; - unsigned int ucode_offset; + u32 ucode_offset; + u32 ucode_size; uint32_t chip_id; u32 *cpu_addr; int i; hdr = (const struct common_firmware_header *)adev->vce.fw->data; ucode_offset = le32_to_cpu(hdr->ucode_array_offset_bytes); + ucode_size = hdr->ucode_size_bytes - sizeof(struct vce_v1_0_fw_signature *); cpu_addr = adev->vce.cpu_addr; sign = (void *)adev->vce.fw->data + ucode_offset; + if (ucode_size > VCE_V1_0_FW_SIZE - AMDGPU_VCE_FIRMWARE_OFFSET) + return -EINVAL; + switch (adev->asic_type) { case CHIP_TAHITI: chip_id = 0x01000014; @@ -226,12 +232,14 @@ static int vce_v1_0_load_fw_signature(struct amdgpu_device *adev) return -EINVAL; } + memset_io(&cpu_addr[0], 0, amdgpu_bo_size(adev->vce.vcpu_bo)); + cpu_addr += (256 - 64) / 4; memcpy_toio(&cpu_addr[0], &sign->val[i].nonce[0], 16); cpu_addr[4] = cpu_to_le32(le32_to_cpu(sign->length) + 64); memset_io(&cpu_addr[5], 0, 44); - memcpy_toio(&cpu_addr[16], &sign[1], hdr->ucode_size_bytes - sizeof(*sign)); + memcpy_toio(&cpu_addr[16], &sign[1], ucode_size); cpu_addr += (le32_to_cpu(sign->length) + 64) / 4; memcpy_toio(&cpu_addr[0], &sign->val[i].sigval[0], 16); @@ -312,18 +320,23 @@ static int vce_v1_0_mc_resume(struct amdgpu_device *adev) WREG32(mmVCE_VCPU_SCRATCH7, AMDGPU_MAX_VCE_HANDLES); offset = adev->vce.gpu_addr + AMDGPU_VCE_FIRMWARE_OFFSET; - size = VCE_V1_0_FW_SIZE; - WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); + size = VCE_V1_0_FW_SIZE - AMDGPU_VCE_FIRMWARE_OFFSET; + WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset); WREG32(mmVCE_VCPU_CACHE_SIZE0, size); offset += size; size = VCE_V1_0_STACK_SIZE; - WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); + WARN_ON(!IS_ALIGNED(offset, VCE_V1_0_ALIGNMENT)); + WARN_ON(!IS_ALIGNED(size, VCE_V1_0_ALIGNMENT)); + WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset); WREG32(mmVCE_VCPU_CACHE_SIZE1, size); offset += size; size = VCE_V1_0_DATA_SIZE; - WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); + WARN_ON(!IS_ALIGNED(offset, VCE_V1_0_ALIGNMENT)); + WARN_ON(!IS_ALIGNED(size, VCE_V1_0_ALIGNMENT)); + WARN_ON((offset + size - adev->vce.gpu_addr) > amdgpu_bo_size(adev->vce.vcpu_bo)); + WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset); WREG32(mmVCE_VCPU_CACHE_SIZE2, size); WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); @@ -527,22 +540,31 @@ static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block) * To accomodate that, we put GART to the LOW address range * and reserve some GART pages where we map the VCPU BO, * so that it gets a 32-bit address. + * + * The BAR address is zero and we can't change it + * due to the firmware validation mechanism. + * It seems that it fails to initialize if the address is >= 128 MiB. */ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev) { u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo); - u64 max_vcpu_bo_addr = 0xffffffff - bo_size; + u64 max_vcpu_bo_addr = 0x07ffffff - bo_size; u64 num_pages = ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_SIZE; u64 pa = amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo); u64 flags = AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID; u64 vce_gart_start_offs; int r; - r = amdgpu_gtt_mgr_alloc_entries(&adev->mman.gtt_mgr, - &adev->vce.gart_node, num_pages, - DRM_MM_INSERT_LOW); - if (r) - return r; + if (adev->gmc.vram_start < adev->gmc.gart_start) + return amdgpu_bo_gpu_offset(adev->vce.vcpu_bo) <= max_vcpu_bo_addr ? 0 : -EINVAL; + + if (!drm_mm_node_allocated(&adev->vce.gart_node)) { + r = amdgpu_gtt_mgr_alloc_entries(&adev->mman.gtt_mgr, + &adev->vce.gart_node, num_pages, + DRM_MM_INSERT_LOW); + if (r) + return r; + } vce_gart_start_offs = amdgpu_gtt_node_to_byte_offset(&adev->vce.gart_node); @@ -553,8 +575,6 @@ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev) amdgpu_gart_map_vram_range(adev, pa, adev->vce.gart_node.start, num_pages, flags, adev->gart.ptr); adev->vce.gpu_addr = adev->gmc.gart_start + vce_gart_start_offs; - if (adev->vce.gpu_addr > max_vcpu_bo_addr) - return -EINVAL; return 0; } @@ -574,10 +594,7 @@ static int vce_v1_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - r = amdgpu_vce_resume(adev); - if (r) - return r; - r = vce_v1_0_load_fw_signature(adev); + r = vce_v1_0_load_fw(adev); if (r) return r; r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev); @@ -696,10 +713,7 @@ static int vce_v1_0_resume(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int r; - r = amdgpu_vce_resume(adev); - if (r) - return r; - r = vce_v1_0_load_fw_signature(adev); + r = vce_v1_0_load_fw(adev); if (r) return r; r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index db149eda6204..3a6fc8604108 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -37,9 +37,14 @@ #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" + +/* Use 24K to be safe. The FW supposedly only requires 23744 bytes. */ +#define VCE_V2_0_DATA_ENTRY_SIZE (24 * 1024) + #define VCE_V2_0_FW_SIZE (256 * 1024) #define VCE_V2_0_STACK_SIZE (64 * 1024) -#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES) +#define VCE_V2_0_DATA_SIZE (VCE_V2_0_DATA_ENTRY_SIZE * (AMDGPU_MAX_VCE_HANDLES + 1)) + #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev); @@ -183,7 +188,7 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev) WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); offset = AMDGPU_VCE_FIRMWARE_OFFSET; - size = VCE_V2_0_FW_SIZE; + size = VCE_V2_0_FW_SIZE - AMDGPU_VCE_FIRMWARE_OFFSET; WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE0, size); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 03d79e464f04..c69f7d82060f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -574,7 +574,7 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) } else WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); offset = AMDGPU_VCE_FIRMWARE_OFFSET; - size = VCE_V3_0_FW_SIZE; + size = VCE_V3_0_FW_SIZE - AMDGPU_VCE_FIRMWARE_OFFSET; WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE0, size); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index e35fae9cdaf6..0442bfcfd384 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -2113,6 +2113,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0xf, + .no_user_fence = true, .secure_submission_supported = true, .get_rptr = vcn_v2_0_dec_ring_get_rptr, .get_wptr = vcn_v2_0_dec_ring_get_wptr, @@ -2145,6 +2146,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v2_0_enc_ring_get_rptr, .get_wptr = vcn_v2_0_enc_ring_get_wptr, .set_wptr = vcn_v2_0_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 006a15451197..8b8184fe6764 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1778,6 +1778,7 @@ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0xf, + .no_user_fence = true, .secure_submission_supported = true, .get_rptr = vcn_v2_5_dec_ring_get_rptr, .get_wptr = vcn_v2_5_dec_ring_get_wptr, @@ -1879,6 +1880,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v2_5_enc_ring_get_rptr, .get_wptr = vcn_v2_5_enc_ring_get_wptr, .set_wptr = vcn_v2_5_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 6fb4fcdbba4f..81bba3ec2a93 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -1856,6 +1856,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0x3f, .nop = VCN_DEC_SW_CMD_NO_OP, + .no_user_fence = true, .secure_submission_supported = true, .get_rptr = vcn_v3_0_dec_ring_get_rptr, .get_wptr = vcn_v3_0_dec_ring_get_wptr, @@ -1972,6 +1973,7 @@ static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { uint32_t offset, size, *create; + uint64_t buf_end; if (msg[0] != RDECODE_MESSAGE_CREATE) continue; @@ -1979,7 +1981,8 @@ static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, offset = msg[1]; size = msg[2]; - if (size < 4 || offset + size > end - addr) { + if (size < 4 || check_add_overflow(offset, size, &buf_end) || + buf_end > end - addr) { DRM_ERROR("VCN message buffer exceeds BO bounds!\n"); r = -EINVAL; goto out; @@ -2036,6 +2039,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0xf, + .no_user_fence = true, .secure_submission_supported = true, .get_rptr = vcn_v3_0_dec_ring_get_rptr, .get_wptr = vcn_v3_0_dec_ring_get_wptr, @@ -2138,6 +2142,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v3_0_enc_ring_get_rptr, .get_wptr = vcn_v3_0_enc_ring_get_wptr, .set_wptr = vcn_v3_0_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 5dec92691f73..ff7269bafae8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1889,6 +1889,7 @@ static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { uint32_t offset, size, *create; + uint64_t buf_end; if (msg[0] != RDECODE_MESSAGE_CREATE) continue; @@ -1896,7 +1897,8 @@ static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, offset = msg[1]; size = msg[2]; - if (size < 4 || offset + size > end - addr) { + if (size < 4 || check_add_overflow(offset, size, &buf_end) || + buf_end > end - addr) { DRM_ERROR("VCN message buffer exceeds BO bounds!\n"); r = -EINVAL; goto out; @@ -1994,6 +1996,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .extra_bytes = sizeof(struct amdgpu_vcn_rb_metadata), .get_rptr = vcn_v4_0_unified_ring_get_rptr, .get_wptr = vcn_v4_0_unified_ring_get_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index ff3013b97abd..7f001c32e911 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1686,7 +1686,7 @@ static int vcn_v4_0_3_reset_jpeg_post_helper(struct amdgpu_device *adev, int ins for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { ring = &adev->jpeg.inst[inst].ring_dec[i]; /* Force completion of any remaining jobs */ - amdgpu_fence_driver_force_completion(ring); + amdgpu_fence_driver_force_completion(ring, NULL); if (ring->use_doorbell) WREG32_SOC15_OFFSET( @@ -1775,6 +1775,7 @@ static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 1f6a22983c0d..1571cc5a148c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -1483,6 +1483,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 6109124f852e..d5f49fa33bee 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -1207,6 +1207,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index c28c6aff17aa..d3db0494341e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -1332,7 +1332,7 @@ static int vcn_v5_0_1_reset_jpeg_post_helper(struct amdgpu_device *adev, int ins for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { ring = &adev->jpeg.inst[inst].ring_dec[i]; /* Force completion of any remaining jobs */ - amdgpu_fence_driver_force_completion(ring); + amdgpu_fence_driver_force_completion(ring, NULL); if (ring->use_doorbell) WREG32_SOC15_OFFSET( @@ -1419,6 +1419,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v5_0_1_unified_ring_get_rptr, .get_wptr = vcn_v5_0_1_unified_ring_get_wptr, .set_wptr = vcn_v5_0_1_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c index c3d3cc023058..bbc172db91a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c @@ -994,6 +994,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_2_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .no_user_fence = true, .get_rptr = vcn_v5_0_2_unified_ring_get_rptr, .get_wptr = vcn_v5_0_2_unified_ring_get_wptr, .set_wptr = vcn_v5_0_2_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c new file mode 100644 index 000000000000..0d91e01fbf3a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c @@ -0,0 +1,350 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "amdgpu.h" +#include "amdgpu_ucode.h" +#include "amdgpu_vpe.h" +#include "vpe_v2_0.h" +#include "soc15_common.h" +#include "ivsrcid/vpe/irqsrcs_vpe_6_1.h" +#include "vpe/vpe_2_0_0_offset.h" +#include "vpe/vpe_2_0_0_sh_mask.h" + +MODULE_FIRMWARE("amdgpu/vpe_2_0_0.bin"); + +#define VPE_THREAD1_UCODE_OFFSET 0x8000 + +static uint32_t vpe_v2_0_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset) +{ + uint32_t base; + + base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0]; + + return base + offset; +} + +static int vpe_v2_0_irq_init(struct amdgpu_vpe *vpe) +{ + struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); + int ret; + + ret = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VPE, + VPE_6_1_SRCID__VPE_TRAP, + &adev->vpe.trap_irq); + if (ret) + return ret; + + return 0; +} + +static int vpe_v2_0_load_microcode(struct amdgpu_vpe *vpe) +{ + struct amdgpu_device *adev = vpe->ring.adev; + const struct vpe_firmware_header_v1_0 *vpe_hdr; + const __le32 *data; + uint32_t ucode_offset[2], ucode_size[2], size_dw, ret; + uint32_t f32_offset, f32_cntl, reg_data; + + ret = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL)); + ret = REG_SET_FIELD(ret, VPEC_CNTL, UMSCH_INT_ENABLE, 0); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), ret); + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2)); + reg_data = REG_SET_FIELD(reg_data, VPEC_CNTL2, IB_FIFO_WATERMARK, 1); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2), reg_data); + + if (amdgpu_vpe_configure_dpm(vpe)) + dev_warn(adev->dev, "VPE DPM not enabled.\n"); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + + f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL); + f32_cntl = RREG32(f32_offset); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0); + + adev->vpe.cmdbuf_cpu_addr[0] = f32_offset; + adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl; + + return amdgpu_vpe_psp_update_sram(adev); + } + + /* Halt and Check F32 cleaness */ + f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL); + f32_cntl = RREG32(f32_offset); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 1); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 1); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_CHECKSUM_CLR, 1); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH0_CHECKSUM_CLR, 1); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl); + + f32_cntl = RREG32(f32_offset); + if (!REG_GET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT)) { + dev_err(adev->dev, "VPEC is not halted"); + return -EBUSY; + } + + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_CHECKSUM_CLR, 0); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH0_CHECKSUM_CLR, 0); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl); + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE_CHECKSUM)); + if (reg_data) { + dev_err(adev->dev, "VPE FW checksum 0 not clean"); + return -EBUSY; + } + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE1_CHECKSUM)); + if (reg_data) { + dev_err(adev->dev, "VPE FW checksum 1 not clean"); + return -EBUSY; + } + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS2)); + if (REG_GET_FIELD(reg_data, VPEC_STATUS2, TH0F32_INSTR_PTR)) { + dev_err(adev->dev, "VPE FW initial status not clean"); + return -EBUSY; + } + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS6)); + if (REG_GET_FIELD(reg_data, VPEC_STATUS6, TH1F32_INSTR_PTR)) { + dev_err(adev->dev, "VPE FW initial status not clean"); + return -EBUSY; + } + /* end of F32 cleaness check */ + + vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data; + + /* Thread 0(command thread) ucode offset/size */ + ucode_offset[0] = le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes); + ucode_size[0] = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes); + /* Thread 1(control thread) ucode offset/size */ + ucode_offset[1] = le32_to_cpu(vpe_hdr->ctl_ucode_offset); + ucode_size[1] = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes); + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL)); + reg_data = REG_SET_FIELD(reg_data, VPEC_PG_CNTL, PG_EN, 0); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data); + + for (int j = 0; j < vpe->num_instances; j++) { + for (int i = 0; i < 2; i++) { + if (i > 0) + WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET); + else + WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0); + + data = (const __le32 *)(adev->vpe.fw->data + ucode_offset[i]); + size_dw = ucode_size[i] / sizeof(__le32); + + while (size_dw--) { + if (amdgpu_emu_mode && size_dw % 500 == 0) + msleep(1); + WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++)); + } + } + } + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL)); + reg_data = REG_SET_FIELD(reg_data, VPEC_PG_CNTL, PG_EN, 1); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data); + + /* Unhalt F32 */ + f32_cntl = RREG32(f32_offset); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl); + + return 0; +} + +static int vpe_v2_0_ring_start(struct amdgpu_vpe *vpe) +{ + struct amdgpu_ring *ring = &vpe->ring; + struct amdgpu_device *adev = ring->adev; + uint32_t doorbell, doorbell_offset; + uint32_t rb_bufsz, rb_cntl; + uint32_t ib_cntl, i; + int ret; + + for (i = 0; i < vpe->num_instances; i++) { + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_PRIV, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_VMID, 0); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR), 0); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_HI), 0); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), 0); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), 0); + + /* set the wb address whether it's enabled or not */ + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_LO), + lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_HI), + upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); + + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); + + ring->wptr = 0; + + /* before programing wptr to a less value, need set minor_ptr_update first */ + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 1); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); + /* set minor_ptr_update to 0 after wptr programed */ + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 0); + + doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET)); + doorbell_offset = REG_SET_FIELD(doorbell_offset, VPEC_QUEUE0_DOORBELL_OFFSET, OFFSET, ring->doorbell_index + i*4); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET), doorbell_offset); + + doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL)); + doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL), doorbell); + + adev->nbio.funcs->vpe_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index + i*4, 4); + + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_ENABLE, 1); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); + + ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, VPEC_QUEUE0_IB_CNTL, IB_ENABLE, 1); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL), ib_cntl); + } + + ret = amdgpu_ring_test_helper(ring); + if (ret) + return ret; + + return 0; +} + +static int vpe_v2_0_ring_stop(struct amdgpu_vpe *vpe) +{ + struct amdgpu_device *adev = vpe->ring.adev; + uint32_t queue_reset, i; + int ret; + + for (i = 0; i < vpe->num_instances; i++) { + queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ)); + + queue_reset = REG_SET_FIELD(queue_reset, VPEC_QUEUE_RESET_REQ, QUEUE0_RESET, 1); + + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ), queue_reset); + /* timeout length is adev->timeout_usec */ + ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ, 0, + VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK); + + if (ret) + dev_err(adev->dev, "VPE queue reset failed\n"); + } + + vpe->ring.sched.ready = false; + + return ret; +} + +static int vpe_v2_0_set_trap_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + struct amdgpu_vpe *vpe = &adev->vpe; + uint32_t vpe_cntl; + + vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL)); + vpe_cntl = REG_SET_FIELD(vpe_cntl, VPEC_CNTL, TRAP_ENABLE, + state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); + + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), vpe_cntl); + + return 0; +} + +static int vpe_v2_0_process_trap_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + + DRM_DEBUG("IH: VPE trap\n"); + + switch (entry->client_id) { + case SOC21_IH_CLIENTID_VPE: + amdgpu_fence_process(&adev->vpe.ring); + break; + default: + break; + } + + return 0; +} + +static int vpe_v2_0_set_regs(struct amdgpu_vpe *vpe) +{ + vpe->regs.queue0_rb_rptr_lo = regVPEC_QUEUE0_RB_RPTR; + vpe->regs.queue0_rb_rptr_hi = regVPEC_QUEUE0_RB_RPTR_HI; + vpe->regs.queue0_rb_wptr_lo = regVPEC_QUEUE0_RB_WPTR; + vpe->regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI; + vpe->regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT; + vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2; + + vpe->regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4; + vpe->regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3; + vpe->regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4; + vpe->regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2; + vpe->regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3; + vpe->regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1; + vpe->regs.context_indicator = regVPEC_QUEUE6_DUMMY3; + + return 0; +} + +static struct vpe_funcs vpe_v2_0_funcs = { + .get_reg_offset = vpe_v2_0_get_reg_offset, + .set_regs = vpe_v2_0_set_regs, + .irq_init = vpe_v2_0_irq_init, + .init_microcode = amdgpu_vpe_init_microcode, + .load_microcode = vpe_v2_0_load_microcode, + .ring_init = amdgpu_vpe_ring_init, + .ring_start = vpe_v2_0_ring_start, + .ring_stop = vpe_v2_0_ring_stop, + .ring_fini = amdgpu_vpe_ring_fini, +}; + +static const struct amdgpu_irq_src_funcs vpe_v2_0_trap_irq_funcs = { + .set = vpe_v2_0_set_trap_irq_state, + .process = vpe_v2_0_process_trap_irq, +}; + +void vpe_v2_0_set_funcs(struct amdgpu_vpe *vpe) +{ + vpe->funcs = &vpe_v2_0_funcs; + vpe->trap_irq.funcs = &vpe_v2_0_trap_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.h new file mode 100644 index 000000000000..e9f2077bfdc2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __VPE_V2_0_H__ +#define __VPE_V2_0_H__ + +#include "amdgpu_vpe.h" + +void vpe_v2_0_set_funcs(struct amdgpu_vpe *vpe); + +#endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 55ea5145a28a..81bcb16eb6dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -21,10 +21,12 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include #include #include +#include #include #include #include @@ -43,6 +45,7 @@ #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" #include "kfd_debug.h" +#include "amdgpu_ptl.h" static long kfd_ioctl(struct file *, unsigned int, unsigned long); static int kfd_open(struct inode *, struct file *); @@ -66,6 +69,21 @@ static const struct class kfd_class = { .name = kfd_dev_name, }; +/* + * Cache the address space of the chardev on first open so that the reset + * path can drop all userspace mappings of doorbell and MMIO ranges via + * unmap_mapping_range(). + */ +static struct address_space *kfd_dev_mapping; + +void kfd_dev_unmap_mapping_range(loff_t const holebegin, loff_t const holelen) +{ + struct address_space *mapping = READ_ONCE(kfd_dev_mapping); + + if (mapping) + unmap_mapping_range(mapping, holebegin, holelen, 1); +} + static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id) { struct kfd_process_device *pdd; @@ -132,6 +150,13 @@ static int kfd_open(struct inode *inode, struct file *filep) if (iminor(inode) != 0) return -ENODEV; + /* + * /dev/kfd is a single chardev so all opens share one inode. Cache + * its address_space on the first open for use by the reset path. + */ + if (!READ_ONCE(kfd_dev_mapping)) + cmpxchg(&kfd_dev_mapping, NULL, inode->i_mapping); + is_32bit_user_mode = in_compat_syscall(); if (is_32bit_user_mode) { @@ -146,11 +171,6 @@ static int kfd_open(struct inode *inode, struct file *filep) if (IS_ERR(process)) return PTR_ERR(process); - if (kfd_process_init_cwsr_apu(process, filep)) { - kfd_unref_process(process); - return -EFAULT; - } - /* filep now owns the reference returned by kfd_create_process */ filep->private_data = process; @@ -1359,7 +1379,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); if (WARN_ON_ONCE(!peer_pdd)) continue; - kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); + kfd_flush_tlb(peer_pdd); } kfree(devices_arr); @@ -1454,7 +1474,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, if (WARN_ON_ONCE(!peer_pdd)) continue; if (flush_tlb) - kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); + kfd_flush_tlb(peer_pdd); /* Remove dma mapping after tlb flush to avoid IO_PAGE_FAULT */ err = amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv); @@ -1695,6 +1715,16 @@ static int kfd_ioctl_smi_events(struct file *filep, return kfd_smi_event_open(pdd->dev, &args->anon_fd); } +static int kfd_ioctl_svm_validate(void *kdata, unsigned int usize) +{ + struct kfd_ioctl_svm_args *args = kdata; + size_t expected = struct_size(args, attrs, args->nattr); + + if (expected == SIZE_MAX || usize < expected) + return -EINVAL; + return 0; +} + #if IS_ENABLED(CONFIG_HSA_AMD_SVM) static int kfd_ioctl_set_xnack_mode(struct file *filep, @@ -1766,6 +1796,108 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) } #endif +static int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) +{ + struct amdgpu_device *adev = pdd->dev->adev; + struct amdgpu_ptl *ptl = &adev->psp.ptl; + enum amdgpu_ptl_fmt pref_format1 = ptl->fmt1; + enum amdgpu_ptl_fmt pref_format2 = ptl->fmt2; + uint32_t ptl_state = enable ? 1 : 0; + int ret; + + if (!ptl->hw_supported) + return -EOPNOTSUPP; + + if (!pdd->dev->kfd2kgd || !pdd->dev->kfd2kgd->ptl_ctrl) + return -EOPNOTSUPP; + + ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, + &ptl_state, + &pref_format1, + &pref_format2); + + return ret; +} + +int kfd_ptl_disable_request(struct kfd_process_device *pdd, + struct kfd_process *p) +{ + struct amdgpu_device *adev = pdd->dev->adev; + struct amdgpu_ptl *ptl = &adev->psp.ptl; + int ret = 0; + + mutex_lock(&ptl->mutex); + + if (pdd->ptl_disable_req) + goto out; + + if (atomic_inc_return(&ptl->disable_ref) == 1) { + ret = kfd_ptl_control(pdd, false); + if (ret) { + atomic_dec(&ptl->disable_ref); + dev_warn(pdd->dev->adev->dev, + "failed to disable PTL\n"); + goto out; + } + } + set_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap); + pdd->ptl_disable_req = true; + +out: + mutex_unlock(&ptl->mutex); + return ret; +} + +int kfd_ptl_disable_release(struct kfd_process_device *pdd, + struct kfd_process *p) +{ + struct amdgpu_device *adev = pdd->dev->adev; + struct amdgpu_ptl *ptl = &adev->psp.ptl; + int ret = 0; + + mutex_lock(&ptl->mutex); + + if (!pdd->ptl_disable_req) + goto out; + + if (atomic_dec_return(&ptl->disable_ref) == 0) { + clear_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap); + ret = kfd_ptl_control(pdd, true); + if (ret) { + atomic_inc(&ptl->disable_ref); + set_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap); + dev_warn(adev->dev, "Failed to enable PTL on release: %d\n", ret); + goto out; + } + } + pdd->ptl_disable_req = false; + +out: + mutex_unlock(&ptl->mutex); + return ret; +} + +static int kfd_profiler_ptl_control(struct kfd_process *p, + struct kfd_ioctl_ptl_control *args) +{ + struct kfd_process_device *pdd; + int ret; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + + if (!pdd || !pdd->dev || !pdd->dev->kfd) + return -EINVAL; + + if (args->enable == 0) + ret = kfd_ptl_disable_request(pdd, p); + else + ret = kfd_ptl_disable_release(pdd, p); + + return ret; +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -2329,6 +2461,9 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, const bool criu_resume = true; u64 offset; + if (bo_priv->idr_handle > INT_MAX) + return -EINVAL; + if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { if (bo_bucket->size != kfd_doorbell_process_slice(pdd->dev->kfd)) @@ -3207,9 +3342,114 @@ static int kfd_ioctl_create_process(struct file *filep, struct kfd_process *p, v return 0; } +static inline uint32_t profile_lock_device(struct kfd_process *p, + uint32_t gpu_id, uint32_t op) +{ + struct kfd_process_device *pdd; + struct kfd_dev *kfd; + int status = -EINVAL; + struct amdgpu_ptl *ptl; + + if (!p) + return -EINVAL; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, gpu_id); + mutex_unlock(&p->mutex); + + if (!pdd || !pdd->dev || !pdd->dev->kfd) + return -EINVAL; + + kfd = pdd->dev->kfd; + ptl = &pdd->dev->adev->psp.ptl; + + mutex_lock(&kfd->profiler_lock); + if (op == 1) { + if (!kfd->profiler_process) { + kfd->profiler_process = p; + status = 0; + mutex_unlock(&kfd->profiler_lock); + if (ptl->hw_supported) { + status = kfd_ptl_disable_request(pdd, p); + if (status != 0) + dev_err(kfd_device, + "Failed to lock device %d for profiling, error %d\n", + gpu_id, status); + } + return status; + } else if (kfd->profiler_process == p) { + status = -EALREADY; + } else { + status = -EBUSY; + } + } else if (op == 0 && kfd->profiler_process == p) { + kfd->profiler_process = NULL; + status = 0; + mutex_unlock(&kfd->profiler_lock); + + if (ptl->hw_supported) { + status = kfd_ptl_disable_release(pdd, p); + if (status) + dev_err(kfd_device, + "Failed to unlock device %d for profiling, error %d\n", + gpu_id, status); + } + return status; + } + mutex_unlock(&kfd->profiler_lock); + + return status; +} + +static inline int kfd_profiler_pmc(struct kfd_process *p, + struct kfd_ioctl_pmc_settings *args) +{ + struct kfd_process_device *pdd; + struct device_queue_manager *dqm; + int status; + + /* Check if we have the correct permissions. */ + if (!perfmon_capable()) + return -EPERM; + + /* Lock/Unlock the device based on the parameter given in OP */ + status = profile_lock_device(p, args->gpu_id, args->lock); + if (status != 0) + return status; + + /* Enable/disable perfcount if requested */ + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + dqm = pdd->dev->dqm; + mutex_unlock(&p->mutex); + + dqm->ops.set_perfcount(dqm, args->perfcount_enable); + return status; +} + +static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_ioctl_profiler_args *args = data; + + switch (args->op) { + case KFD_IOC_PROFILER_VERSION: + args->version = KFD_IOC_PROFILER_VERSION_NUM; + return 0; + case KFD_IOC_PROFILER_PMC: + return kfd_profiler_pmc(p, &args->pmc); + case KFD_IOC_PROFILER_PTL_CONTROL: + return kfd_profiler_ptl_control(p, &args->ptl); + } + return -EINVAL; +} + #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ - .cmd_drv = 0, .name = #ioctl} + .validate = NULL, .cmd_drv = 0, .name = #ioctl} + +#define AMDKFD_IOCTL_DEF_V(ioctl, _func, _validate, _flags) \ + [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ + .validate = _validate, .cmd_drv = 0, .name = #ioctl} /** Ioctl table */ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { @@ -3306,7 +3546,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS, kfd_ioctl_smi_events, 0), - AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0), + AMDKFD_IOCTL_DEF_V(AMDKFD_IOC_SVM, kfd_ioctl_svm, + kfd_ioctl_svm_validate, 0), AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE, kfd_ioctl_set_xnack_mode, 0), @@ -3328,6 +3569,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_PROCESS, kfd_ioctl_create_process, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_PROFILER, + kfd_ioctl_profiler, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) @@ -3431,6 +3675,12 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) memset(kdata, 0, usize); } + if (ioctl->validate) { + retcode = ioctl->validate(kdata, usize); + if (retcode) + goto err_i1; + } + retcode = func(filep, process, kdata); if (cmd & IOC_OUT) @@ -3515,9 +3765,8 @@ static int kfd_mmap(struct file *filep, struct vm_area_struct *vma) return kfd_event_mmap(process, vma); case KFD_MMAP_TYPE_RESERVED_MEM: - if (!dev) - return -ENODEV; - return kfd_reserved_mem_mmap(dev, process, vma); + pr_warn("KFD_MMAP_TYPE_RESERVED_MEM is no longer supported\n"); + return -EINVAL; case KFD_MMAP_TYPE_MMIO: if (!dev) return -ENODEV; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 8ff97bf7d95a..c2c59781feee 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -936,6 +936,9 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); + kfd->profiler_process = NULL; + mutex_init(&kfd->profiler_lock); + kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -971,6 +974,7 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) ida_destroy(&kfd->doorbell_ida); kfd_gtt_sa_fini(kfd); amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); + mutex_destroy(&kfd->profiler_lock); } kfree(kfd); @@ -1647,6 +1651,22 @@ int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) return 0; } +int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev) +{ + if (!adev->kfd.init_complete) + return 0; + + return kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); +} + +int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev) +{ + if (!adev->kfd.init_complete) + return 0; + + return kgd2kfd_start_sched_all_nodes(adev->kfd.dev); +} + bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) { struct kfd_node *node; @@ -1737,37 +1757,6 @@ bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entr return false; } -/* check if there is kfd process still uses adev */ -static bool kgd2kfd_check_device_idle(struct amdgpu_device *adev) -{ - struct kfd_process *p; - struct hlist_node *p_temp; - unsigned int temp; - struct kfd_node *dev; - - mutex_lock(&kfd_processes_mutex); - - if (hash_empty(kfd_processes_table)) { - mutex_unlock(&kfd_processes_mutex); - return true; - } - - /* check if there is device still use adev */ - hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { - for (int i = 0; i < p->n_pdds; i++) { - dev = p->pdds[i]->dev; - if (dev->adev == adev) { - mutex_unlock(&kfd_processes_mutex); - return false; - } - } - } - - mutex_unlock(&kfd_processes_mutex); - - return true; -} - /** kgd2kfd_teardown_processes - gracefully tear down existing * kfd processes that use adev * @@ -1800,7 +1789,7 @@ void kgd2kfd_teardown_processes(struct amdgpu_device *adev) mutex_unlock(&kfd_processes_mutex); /* wait all kfd processes use adev terminate */ - while (!kgd2kfd_check_device_idle(adev)) + while (!!atomic_read(&adev->kfd.dev->kfd_processes_count)) cond_resched(); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index ab3b2e7be9bd..5cba592ba941 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -71,6 +71,12 @@ static int allocate_sdma_queue(struct device_queue_manager *dqm, struct queue *q, const uint32_t *restore_sdma_id); static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma); +static int resume_all_queues_mes(struct device_queue_manager *dqm); +static int suspend_all_queues_mes(struct device_queue_manager *dqm); +static struct queue *find_queue_by_doorbell_offset(struct device_queue_manager *dqm, + u32 doorbell_offset); +static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd); static inline enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) @@ -273,13 +279,19 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, return r; } -static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, - struct qcm_process_device *qpd) +static int remove_queue_mes_on_reset_option(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd, + bool is_for_reset, + bool flush_mes_queue) { struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; int r; struct mes_remove_queue_input queue_input; + /* queue was already removed during reset */ + if (q->properties.is_reset) + return 0; + if (!dqm->sched_running || dqm->sched_halt) return 0; if (!down_read_trylock(&adev->reset_domain->sem)) @@ -288,6 +300,7 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); queue_input.doorbell_offset = q->properties.doorbell_off; queue_input.gang_context_addr = q->gang_ctx_gpu_addr; + queue_input.remove_queue_after_reset = flush_mes_queue; queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; amdgpu_mes_lock(&adev->mes); @@ -295,7 +308,13 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, amdgpu_mes_unlock(&adev->mes); up_read(&adev->reset_domain->sem); + if (is_for_reset) + return r; + if (r) { + if (!suspend_all_queues_mes(dqm)) + return resume_all_queues_mes(dqm); + dev_err(adev->dev, "failed to remove hardware queue from MES, doorbell=0x%x\n", q->properties.doorbell_off); dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); @@ -305,6 +324,35 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, return r; } +static void set_perfcount(struct device_queue_manager *dqm, int enable) +{ + struct device_process_node *cur; + struct qcm_process_device *qpd; + struct queue *q; + struct mqd_update_info minfo = { 0 }; + + if (!dqm) + return; + + minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : + UPDATE_FLAG_PERFCOUNT_DISABLE); + dqm_lock(dqm); + list_for_each_entry(cur, &dqm->queues, list) { + qpd = cur->qpd; + list_for_each_entry(q, &qpd->queues_list, list) { + pqm_update_mqd(qpd->pqm, q->properties.queue_id, + &minfo); + } + } + dqm_unlock(dqm); +} + +static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd) +{ + return remove_queue_mes_on_reset_option(dqm, q, qpd, false, false); +} + static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) { struct device_process_node *cur; @@ -359,6 +407,92 @@ static int add_all_kfd_queues_mes(struct device_queue_manager *dqm) return retval; } +static int reset_queues_mes(struct device_queue_manager *dqm) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; + int hqd_info_size = adev->mes.hung_queue_hqd_info_offset; + int num_hung = 0, r = 0, i, pipe, queue, queue_type; + u32 *hung_array = dqm->hung_db_array; + struct amdgpu_mes_hung_queue_hqd_info *hqd_info = dqm->hqd_info; + struct kfd_process_device *pdd; + struct queue *q; + + if (!amdgpu_mes_queue_reset_by_mes_supported(adev)) { + r = -ENOTRECOVERABLE; + goto fail; + } + + /* reset should be used only in dqm locked queue reset */ + if (WARN_ON(dqm->detect_hang_count > 0)) + return 0; + + if (!amdgpu_gpu_recovery) { + r = -ENOTRECOVERABLE; + goto fail; + } + + if (!hung_array || !hqd_info) { + r = -ENOMEM; + goto fail; + } + + memset(hqd_info, 0, hqd_info_size * sizeof(struct amdgpu_mes_hung_queue_hqd_info)); + + /* + * AMDGPU_RING_TYPE_COMPUTE parameter does not matter if called + * post suspend_all as reset & detect will return all hung queue types. + * + * Passed parameter is for targeting queues not scheduled by MES add_queue. + */ + r = amdgpu_mes_detect_and_reset_hung_queues(adev, AMDGPU_RING_TYPE_COMPUTE, + false, &num_hung, hung_array, ffs(dqm->dev->xcc_mask) - 1); + + if (!num_hung || r) { + r = -ENOTRECOVERABLE; + goto fail; + } + + /* MES resets queue/pipe and cleans up internally */ + for (i = 0; i < num_hung; i++) { + hqd_info[i].bit0_31 = hung_array[i + hqd_info_size]; + pipe = hqd_info[i].pipe_index; + queue = hqd_info[i].queue_index; + queue_type = hqd_info[i].queue_type; + + if (queue_type != MES_QUEUE_TYPE_COMPUTE && + queue_type != MES_QUEUE_TYPE_SDMA) { + pr_warn("Unsupported hung queue reset type: %d\n", queue_type); + hung_array[i] = AMDGPU_MES_INVALID_DB_OFFSET; + continue; + } + + q = find_queue_by_doorbell_offset(dqm, hung_array[i]); + if (!q) { + r = -ENOTRECOVERABLE; + goto fail; + } + + pdd = kfd_get_process_device_data(q->device, q->process); + if (!pdd) { + r = -ENODEV; + goto fail; + } + + pr_warn("Hang detected doorbell %x pipe %d queue %d type %d\n", + hung_array[i], pipe, queue, queue_type); + /* Proceed remove_queue with reset=true */ + remove_queue_mes_on_reset_option(dqm, q, &pdd->qpd, true, false); + set_queue_as_reset(dqm, q, &pdd->qpd); + } + + dqm->detect_hang_count = num_hung; + kfd_signal_reset_event(dqm->dev); + +fail: + dqm->detect_hang_count = 0; + return r; +} + static int suspend_all_queues_mes(struct device_queue_manager *dqm) { struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; @@ -367,10 +501,13 @@ static int suspend_all_queues_mes(struct device_queue_manager *dqm) if (!down_read_trylock(&adev->reset_domain->sem)) return -EIO; - r = amdgpu_mes_suspend(adev); + r = amdgpu_mes_suspend(adev, ffs(dqm->dev->xcc_mask) - 1); up_read(&adev->reset_domain->sem); if (r) { + if (!reset_queues_mes(dqm)) + return 0; + dev_err(adev->dev, "failed to suspend gangs from MES\n"); dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); kfd_hws_hang(dqm); @@ -387,7 +524,7 @@ static int resume_all_queues_mes(struct device_queue_manager *dqm) if (!down_read_trylock(&adev->reset_domain->sem)) return -EIO; - r = amdgpu_mes_resume(adev); + r = amdgpu_mes_resume(adev, ffs(dqm->dev->xcc_mask) - 1); up_read(&adev->reset_domain->sem); if (r) { @@ -475,6 +612,9 @@ static int allocate_doorbell(struct qcm_process_device *qpd, } else { /* For CP queues on SOC15 */ if (restore_id) { + if (*restore_id >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) + return -EINVAL; + /* make sure that ID is free */ if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap)) return -EINVAL; @@ -572,7 +712,7 @@ static int allocate_vmid(struct device_queue_manager *dqm, qpd->vmid, qpd->page_table_base); /* invalidate the VM context after pasid and vmid mapping is set up */ - kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); + kfd_flush_tlb(qpd_to_pdd(qpd)); if (dqm->dev->kfd2kgd->set_scratch_backing_va) dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev, @@ -610,7 +750,7 @@ static void deallocate_vmid(struct device_queue_manager *dqm, if (flush_texture_cache_nocpsch(q->device, qpd)) dev_err(dev, "Failed to flush TC\n"); - kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); + kfd_flush_tlb(qpd_to_pdd(qpd)); /* Release the vmid mapping */ set_pasid_vmid_mapping(dqm, 0, qpd->vmid); @@ -1284,7 +1424,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, dqm->dev->adev, qpd->vmid, qpd->page_table_base); - kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); + kfd_flush_tlb(pdd); } /* Take a safe reference to the mm_struct, which may otherwise @@ -1587,6 +1727,9 @@ static int allocate_sdma_queue(struct device_queue_manager *dqm, } if (restore_sdma_id) { + if (*restore_sdma_id >= get_num_sdma_queues(dqm)) + return -EINVAL; + /* Re-use existing sdma_id */ if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) { dev_err(dev, "SDMA queue already in use\n"); @@ -1613,6 +1756,9 @@ static int allocate_sdma_queue(struct device_queue_manager *dqm, return -ENOMEM; } if (restore_sdma_id) { + if (*restore_sdma_id >= get_num_xgmi_sdma_queues(dqm)) + return -EINVAL; + /* Re-use existing sdma_id */ if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) { dev_err(dev, "SDMA queue already in use\n"); @@ -1797,10 +1943,11 @@ static int halt_cpsch(struct device_queue_manager *dqm) static int unhalt_cpsch(struct device_queue_manager *dqm) { int ret = 0; + struct amdgpu_device *adev = dqm->dev->adev; dqm_lock(dqm); if (!dqm->sched_running || !dqm->sched_halt) { - WARN_ONCE(!dqm->sched_halt, "Scheduling is not on halt.\n"); + dev_dbg(adev->dev, "Scheduling is not on halt.\n"); dqm_unlock(dqm); return 0; } @@ -1821,6 +1968,9 @@ static int start_cpsch(struct device_queue_manager *dqm) { struct device *dev = dqm->dev->adev->dev; int retval, num_hw_queue_slots; + struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; + int hung_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev); + int hqd_info_size = adev->mes.hung_queue_hqd_info_offset; dqm_lock(dqm); @@ -1870,6 +2020,11 @@ static int start_cpsch(struct device_queue_manager *dqm) goto fail_detect_hang_buffer; } + dqm->hung_db_array = kzalloc(hung_array_size * sizeof(u32), GFP_KERNEL); + dqm->hqd_info = kzalloc( + hqd_info_size * sizeof(struct amdgpu_mes_hung_queue_hqd_info), + GFP_KERNEL); + dqm_unlock(dqm); return 0; @@ -1910,6 +2065,9 @@ static int stop_cpsch(struct device_queue_manager *dqm) pm_uninit(&dqm->packet_mgr); kfree(dqm->detect_hang_info); dqm->detect_hang_info = NULL; + kfree(dqm->hung_db_array); + kfree(dqm->hqd_info); + dqm_unlock(dqm); return ret; @@ -2137,6 +2295,7 @@ static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q q->properties.queue_id, pdd->process->lead_thread->pid); pdd->has_reset_queue = true; + q->properties.is_reset = true; if (q->properties.is_active) { q->properties.is_active = false; decrement_queue_count(dqm, qpd, q); @@ -2203,6 +2362,23 @@ static struct queue *find_queue_by_address(struct device_queue_manager *dqm, uin return NULL; } +static struct queue *find_queue_by_doorbell_offset(struct device_queue_manager *dqm, u32 doorbell_offset) +{ + struct device_process_node *cur; + struct qcm_process_device *qpd; + struct queue *q; + + list_for_each_entry(cur, &dqm->queues, list) { + qpd = cur->qpd; + list_for_each_entry(q, &qpd->queues_list, list) { + if (doorbell_offset == q->properties.doorbell_off) + return q; + } + } + + return NULL; +} + static int reset_hung_queues(struct device_queue_manager *dqm) { int r = 0, reset_count = 0, i; @@ -2970,6 +3146,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.reset_queues = reset_queues_cpsch; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; case KFD_SCHED_POLICY_NO_HWS: /* initialize dqm for no cp scheduling */ @@ -2990,6 +3167,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.get_wave_state = get_wave_state; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; default: dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 3272328da11f..e0b6a47e7722 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -32,7 +32,6 @@ #include "kfd_priv.h" #include "kfd_mqd_manager.h" - #define VMID_NUM 16 #define KFD_MES_PROCESS_QUANTUM 100000 @@ -200,6 +199,8 @@ struct device_queue_manager_ops { const struct queue *q, void *mqd, void *ctl_stack); + void (*set_perfcount)(struct device_queue_manager *dqm, + int enable); }; struct device_queue_manager_asic_ops { @@ -285,6 +286,9 @@ struct device_queue_manager { struct dqm_detect_hang_info *detect_hang_info; size_t detect_hang_info_size; int detect_hang_count; + /* for per-queue reset with mes */ + u32 *hung_db_array; + struct amdgpu_mes_hung_queue_hqd_info *hqd_info; }; void device_queue_manager_init_cik( diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c index 9e70a5f8a50b..525989371378 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c @@ -54,6 +54,7 @@ static int update_qpd_v12_1(struct device_queue_manager *dqm, struct kfd_process_device *pdd; struct amdgpu_device *adev = dqm->dev->adev; struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; + bool xnack_enabled; pdd = qpd_to_pdd(qpd); qpd->vm_cntx_cntl = hub->vm_cntx_cntl; @@ -71,16 +72,18 @@ static int update_qpd_v12_1(struct device_queue_manager *dqm, qpd->sh_mem_ape1_base = 0; } - if (KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev)) { - if (!pdd->process->xnack_enabled) { - qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; - qpd->vm_cntx_cntl &= + xnack_enabled = KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev) ? + pdd->process->xnack_enabled : + !pdd->dev->kfd->noretry; + + if (!xnack_enabled) { + qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; + qpd->vm_cntx_cntl &= ~(1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT); - } else { - qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT); - qpd->vm_cntx_cntl |= + } else { + qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT); + qpd->vm_cntx_cntl |= (1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT); - } } qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 44150a71ffd5..a11c4ab3aafd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -483,6 +483,11 @@ int kfd_criu_restore_event(struct file *devkfd, } *priv_data_offset += sizeof(*ev_priv); + if (ev_priv->event_id > INT_MAX) { + ret = -EINVAL; + goto exit; + } + if (ev_priv->user_handle) { ret = kfd_kmap_event_page(p, ev_priv->user_handle); if (ret) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 964efa325908..28dc6886c1ff 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -129,13 +129,14 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, struct dma_fence **mfence) { const u64 GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE; - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + struct amdgpu_ring *ring; struct amdgpu_ttm_buffer_entity *entity; u64 gart_s, gart_d; struct dma_fence *next; u64 size; int r; + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); entity = &adev->mman.move_entities[0]; mutex_lock(&entity->lock); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 77fb41e2486a..8e8ec266ca46 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -123,10 +123,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, */ m->cp_hqd_hq_scheduler0 = 1 << 14; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -141,6 +140,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -220,6 +225,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index a1e3cf2384dd..7568e7ed5244 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -163,10 +163,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -181,6 +180,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -258,6 +262,12 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, } if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index b3e122d7876e..8c815f129614 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -138,10 +138,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -156,6 +155,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c index c90c0d99b1e3..475589b924e9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c @@ -32,6 +32,10 @@ #include "amdgpu_amdkfd.h" #include "kfd_device_queue_manager.h" +static void update_mqd(struct mqd_manager *mm, void *mqd, + struct queue_properties *q, + struct mqd_update_info *minfo); + static inline struct v12_1_compute_mqd *get_mqd(void *mqd) { return (struct v12_1_compute_mqd *)mqd; @@ -215,7 +219,7 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, *mqd = m; if (gart_addr) *gart_addr = addr; - mm->update_mqd(mm, m, q, NULL); + update_mqd(mm, m, q, NULL); } static int load_mqd(struct mqd_manager *mm, void *mqd, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index e8f97de9d6e4..17bfb419b202 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -227,10 +227,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - if (q->tba_addr) { + if (q->tba_addr) m->compute_pgm_rsrc2 |= (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); - } if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { m->cp_hqd_persistent_state |= @@ -245,6 +244,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -327,6 +331,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) @@ -364,11 +375,15 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, { struct v9_mqd *m; struct kfd_context_save_area_header header; + u32 cntl_stack_size; + u32 cntl_stack_offset; /* Control stack is located one page after MQD. */ void *mqd_ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE); m = get_mqd(mqd); + cntl_stack_size = min_t(u32, m->cp_hqd_cntl_stack_size, q->ctl_stack_size); + cntl_stack_offset = min_t(u32, m->cp_hqd_cntl_stack_offset, cntl_stack_size); *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - m->cp_hqd_cntl_stack_offset; @@ -384,9 +399,10 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) return -EFAULT; - if (copy_to_user(ctl_stack + m->cp_hqd_cntl_stack_offset, - mqd_ctl_stack + m->cp_hqd_cntl_stack_offset, - *ctl_stack_used_size)) + *ctl_stack_used_size = cntl_stack_size - cntl_stack_offset; + + if (copy_to_user(ctl_stack + cntl_stack_offset, mqd_ctl_stack + cntl_stack_offset, + *ctl_stack_used_size)) return -EFAULT; return 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 431a20323146..c86779af323b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -148,6 +148,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -230,6 +235,12 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_ctx_save_control = atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 6e333bfa17d6..acd0e41e744c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -215,8 +215,7 @@ enum cache_policy { ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \ (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \ (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \ - (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) || \ - (KFD_GC_VERSION(dev) == IP_VERSION(12, 1, 0))) + (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))) struct kfd_node; @@ -384,6 +383,11 @@ struct kfd_dev { int kfd_dev_lock; atomic_t kfd_processes_count; + + /* Lock for profiler process */ + struct mutex profiler_lock; + /* Process currently holding the lock */ + struct kfd_process *profiler_process; }; enum kfd_mempool { @@ -395,6 +399,7 @@ enum kfd_mempool { /* Character device interface */ int kfd_chardev_init(void); void kfd_chardev_exit(void); +void kfd_dev_unmap_mapping_range(loff_t const holebegin, loff_t const holelen); /** * enum kfd_unmap_queues_filter - Enum for queue filters. @@ -523,6 +528,7 @@ struct queue_properties { uint32_t pm4_target_xcc; bool is_dbg_wa; bool is_user_cu_masked; + bool is_reset; /* Not relevant for user mode queues in cp scheduling */ unsigned int vmid; /* Relevant only for sdma queues*/ @@ -556,6 +562,8 @@ enum mqd_update_flag { UPDATE_FLAG_DBG_WA_ENABLE = 1, UPDATE_FLAG_DBG_WA_DISABLE = 2, UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ + UPDATE_FLAG_PERFCOUNT_ENABLE = 5, + UPDATE_FLAG_PERFCOUNT_DISABLE = 6, }; struct mqd_update_info { @@ -865,6 +873,8 @@ struct kfd_process_device { bool has_reset_queue; u32 pasid; + /* Indicates this process has requested PTL stay disabled */ + bool ptl_disable_req; }; #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) @@ -986,9 +996,6 @@ struct kfd_process { struct kobject *kobj_queues; struct attribute attr_pasid; - /* Keep track cwsr init */ - bool has_cwsr; - /* Exception code enable mask and status */ uint64_t exception_enable_mask; uint64_t exception_status; @@ -1047,10 +1054,13 @@ extern struct srcu_struct kfd_processes_srcu; typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, void *data); +typedef int amdkfd_ioctl_validate_t(void *kdata, unsigned int usize); + struct amdkfd_ioctl_desc { unsigned int cmd; int flags; amdkfd_ioctl_t *func; + amdkfd_ioctl_validate_t *validate; unsigned int cmd_drv; const char *name; }; @@ -1101,8 +1111,6 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); -int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, - struct vm_area_struct *vma); void kfd_process_notifier_release_internal(struct kfd_process *p); /* KFD process API for creating and translating handles */ @@ -1219,9 +1227,6 @@ void kfd_process_set_trap_handler(struct qcm_process_device *qpd, void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, bool enabled); -/* CWSR initialization */ -int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep); - /* CRIU */ /* * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private @@ -1551,13 +1556,13 @@ void kfd_signal_reset_event(struct kfd_node *dev); void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); void kfd_signal_process_terminate_event(struct kfd_process *p); -static inline void kfd_flush_tlb(struct kfd_process_device *pdd, - enum TLB_FLUSH_TYPE type) +static inline void kfd_flush_tlb(struct kfd_process_device *pdd) { struct amdgpu_device *adev = pdd->dev->adev; struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv); - amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd->dev->xcc_mask); + amdgpu_vm_flush_compute_tlb(adev, vm, TLB_FLUSH_HEAVYWEIGHT, + pdd->dev->xcc_mask); } static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) @@ -1601,6 +1606,12 @@ static inline bool kfd_is_first_node(struct kfd_node *node) return (node == node->kfd->nodes[0]); } +/* PTL support */ +int kfd_ptl_disable_request(struct kfd_process_device *pdd, + struct kfd_process *p); +int kfd_ptl_disable_release(struct kfd_process_device *pdd, + struct kfd_process *p); + /* Debugfs */ #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index d28ca581cad0..368283d53077 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1106,6 +1106,16 @@ static void kfd_process_free_outstanding_kfd_bos(struct kfd_process *p) kfd_process_device_free_bos(p->pdds[i]); } +static void kfd_process_profiler_release(struct kfd_process *p, struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->dev->kfd->profiler_lock); + if (pdd->dev->kfd->profiler_process == p) { + pdd->qpd.dqm->ops.set_perfcount(pdd->qpd.dqm, 0); + pdd->dev->kfd->profiler_process = NULL; + } + mutex_unlock(&pdd->dev->kfd->profiler_lock); +} + static void kfd_process_destroy_pdds(struct kfd_process *p) { int i; @@ -1117,6 +1127,11 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d, for pid %d)\n", pdd->dev->id, p->lead_thread->pid); + kfd_process_profiler_release(p, pdd); + + if (pdd->ptl_disable_req) + kfd_ptl_disable_release(pdd, p); + kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); @@ -1409,50 +1424,6 @@ void kfd_cleanup_processes(void) mmu_notifier_synchronize(); } -int kfd_process_init_cwsr_apu(struct kfd_process *p, struct file *filep) -{ - unsigned long offset; - int i; - - if (p->has_cwsr) - return 0; - - for (i = 0; i < p->n_pdds; i++) { - struct kfd_node *dev = p->pdds[i]->dev; - struct qcm_process_device *qpd = &p->pdds[i]->qpd; - - if (!dev->kfd->cwsr_enabled || qpd->cwsr_kaddr || qpd->cwsr_base) - continue; - - offset = KFD_MMAP_TYPE_RESERVED_MEM | KFD_MMAP_GPU_ID(dev->id); - qpd->tba_addr = (int64_t)vm_mmap(filep, 0, - KFD_CWSR_TBA_TMA_SIZE, PROT_READ | PROT_EXEC, - MAP_SHARED, offset); - - if (IS_ERR_VALUE(qpd->tba_addr)) { - int err = qpd->tba_addr; - - dev_err(dev->adev->dev, - "Failure to set tba address. error %d.\n", err); - qpd->tba_addr = 0; - qpd->cwsr_kaddr = NULL; - return err; - } - - memcpy(qpd->cwsr_kaddr, dev->kfd->cwsr_isa, dev->kfd->cwsr_isa_size); - - kfd_process_set_trap_debug_flag(qpd, p->debug_trap_enabled); - - qpd->tma_addr = qpd->tba_addr + KFD_CWSR_TMA_OFFSET; - pr_debug("set tba :0x%llx, tma:0x%llx, cwsr_kaddr:%p for pqm.\n", - qpd->tba_addr, qpd->tma_addr, qpd->cwsr_kaddr); - } - - p->has_cwsr = true; - - return 0; -} - static int kfd_process_device_init_cwsr_dgpu(struct kfd_process_device *pdd) { struct kfd_node *dev = pdd->dev; @@ -2228,38 +2199,6 @@ int kfd_resume_all_processes(void) return ret; } -int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, - struct vm_area_struct *vma) -{ - struct kfd_process_device *pdd; - struct qcm_process_device *qpd; - - if ((vma->vm_end - vma->vm_start) != KFD_CWSR_TBA_TMA_SIZE) { - dev_err(dev->adev->dev, "Incorrect CWSR mapping size.\n"); - return -EINVAL; - } - - pdd = kfd_get_process_device_data(dev, process); - if (!pdd) - return -EINVAL; - qpd = &pdd->qpd; - - qpd->cwsr_kaddr = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, - get_order(KFD_CWSR_TBA_TMA_SIZE)); - if (!qpd->cwsr_kaddr) { - dev_err(dev->adev->dev, - "Error allocating per process CWSR buffer.\n"); - return -ENOMEM; - } - - vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND - | VM_NORESERVE | VM_DONTDUMP | VM_PFNMAP); - /* Mapping pages to user process */ - return remap_pfn_range(vma, vma->vm_start, - PFN_DOWN(__pa(qpd->cwsr_kaddr)), - KFD_CWSR_TBA_TMA_SIZE, vma->vm_page_prot); -} - /* assumes caller holds process lock. */ int kfd_process_drain_interrupts(struct kfd_process_device *pdd) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index b120fdb0ef77..35ec67d9739b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1366,6 +1366,12 @@ svm_range_unmap_from_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm, pr_debug("CPU[0x%llx 0x%llx] -> GPU[0x%llx 0x%llx]\n", start, last, gpu_start, gpu_end); + + if (!amdgpu_vm_ready(vm)) { + pr_debug("VM not ready, canceling unmap\n"); + return -EINVAL; + } + return amdgpu_vm_update_range(adev, vm, false, true, true, false, NULL, gpu_start, gpu_end, init_pte_value, 0, 0, NULL, NULL, fence); @@ -1418,7 +1424,7 @@ svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start, if (r) break; } - kfd_flush_tlb(pdd, TLB_FLUSH_HEAVYWEIGHT); + kfd_flush_tlb(pdd); } return r; @@ -1443,6 +1449,11 @@ svm_range_map_to_gpu(struct kfd_process_device *pdd, struct svm_range *prange, pr_debug("svms 0x%p [0x%lx 0x%lx] readonly %d\n", prange->svms, last_start, last_start + npages - 1, readonly); + if (!amdgpu_vm_ready(vm)) { + pr_debug("VM not ready, canceling map\n"); + return -EINVAL; + } + for (i = offset; i < offset + npages; i++) { uint64_t gpu_start; uint64_t gpu_end; @@ -1560,7 +1571,7 @@ svm_range_map_to_gpus(struct svm_range *prange, unsigned long offset, } } - kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); + kfd_flush_tlb(pdd); } return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 29dee26261ab..630f46091dc7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -514,7 +514,8 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, dev->node_props.capability |= HSA_CAP_AQL_QUEUE_DOUBLE_MAP; - if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0) && + if ((KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0) || + KFD_GC_VERSION(dev->gpu) == IP_VERSION(12, 1, 0)) && (dev->gpu->adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) dev->node_props.capability2 |= HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED; @@ -2027,6 +2028,7 @@ static void kfd_topology_set_capabilities(struct kfd_topology_device *dev) if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(12, 1, 0)) { dev->node_props.capability |= HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED; + dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED; dev->node_props.capability2 |= HSA_CAP2_TRAP_DEBUG_LDS_OUT_OF_ADDR_RANGE_SUPPORTED; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e96a12ff2d31..ba7f98a87808 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -104,6 +104,7 @@ #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" #include "modules/inc/mod_freesync.h" +#include "modules/inc/mod_power.h" #include "modules/power/power_helpers.h" static_assert(AMDGPU_DMUB_NOTIFICATION_MAX == DMUB_NOTIFICATION_MAX, "AMDGPU_DMUB_NOTIFICATION_MAX mismatch"); @@ -232,11 +233,11 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); -static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state); -static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); +static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state); +static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); static void handle_hpd_rx_irq(void *param); @@ -1869,7 +1870,7 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode( ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; break; case IP_VERSION(4, 2, 0): - ret = DMUB_IPS_DISABLE_ALL; + ret = DMUB_IPS_ENABLE; break; default: /* ASICs older than DCN35 do not have IPSs */ @@ -1881,6 +1882,70 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode( return ret; } +static int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm) +{ + struct mod_power_init_params init_data[MAX_NUM_EDP]; + + if (dm->num_of_edps == 0) { + drm_dbg_driver( + dm->ddev, + "amdgpu: No eDP detected, skip initializing power module\n"); + return 0; + } + + /* Initialize all the power module parameters */ + for (int i = 0; i < dm->num_of_edps; i++) { + init_data[i].allow_psr_smu_optimizations = + !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT); + init_data[i].allow_psr_multi_disp_optimizations = + !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); + /* See dm_late_init */ + init_data[i].backlight_ramping_override = false; + init_data[i].backlight_ramping_start = 0xCCCC; + init_data[i].backlight_ramping_reduction = 0xCCCCCCCC; + init_data[i].def_varibright_level = 0; + init_data[i].abm_config_setting = 0; + init_data[i].num_backlight_levels = 101; + init_data[i].use_nits_based_brightness = false; + init_data[i].panel_max_millinits = 0; + init_data[i].panel_min_millinits = 0; + init_data[i].disable_fractional_pwm = + !(amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK); + init_data[i].use_custom_backlight_caps = false; + init_data[i].custom_backlight_caps_config_no = 0; + init_data[i].use_linear_backlight_curve = false; + init_data[i].def_varibright_enable = 0; + init_data[i].varibright_level = 0; + /* + * Power module uses 16-bit backlight levels (0xFFFF max) rather + * than 8-bit(0XFF max) + */ + init_data[i].min_backlight_pwm = + dm->backlight_caps[i].min_input_signal * 0x101; + init_data[i].max_backlight_pwm = + dm->backlight_caps[i].max_input_signal * 0x101; + init_data[i].min_abm_backlight = + dm->backlight_caps[i].min_input_signal * 0x101; + + /* Min backlight level after ABM reduction, Don't allow below 1% + * 0xFFFF x 0.01 = 0x28F + */ + init_data[i].min_abm_backlight = (init_data[i].min_abm_backlight < 0x28F) ? + 0x28F : init_data[i].min_abm_backlight; + } + + dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps); + if (!dm->power_module) { + drm_err(dm->ddev, "amdgpu: Error allocating memory for power module\n"); + return -ENOMEM; + } + + mod_power_hw_init(dm->power_module); + drm_dbg_driver(dm->ddev, "amdgpu: Power module init done\n"); + + return 0; +} + static int amdgpu_dm_init(struct amdgpu_device *adev) { struct dc_init_data init_data; @@ -1898,12 +1963,18 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) mutex_init(&adev->dm.dc_lock); mutex_init(&adev->dm.audio_lock); + spin_lock_init(&adev->dm.dmub_lock); + if (amdgpu_dm_irq_init(adev)) { drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); goto error; } - init_data.asic_id.chip_family = adev->family; + /* special handling for early revisions of GC 11.5.4 */ + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) + init_data.asic_id.chip_family = AMDGPU_FAMILY_GC_11_5_4; + else + init_data.asic_id.chip_family = adev->family; init_data.asic_id.pci_revision_id = adev->pdev->revision; init_data.asic_id.hw_internal_rev = adev->external_rev_id; @@ -2194,6 +2265,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) goto error; } + if (amdgpu_dm_init_power_module(&adev->dm)) + goto error; + /* create fake encoders for MST */ dm_dp_create_fake_mst_encoders(adev); @@ -2256,9 +2330,16 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.idle_workqueue = NULL; } - /* Disable ISM before dc_destroy() invalidates dm->dc */ + /* + * Disable ISM before dc_destroy() invalidates dm->dc. + * + * Quiesce workers first without dc_lock (they take dc_lock + * themselves, so syncing under it would deadlock), then drive the + * FSM back to FULL_POWER_RUNNING under dc_lock. + */ + amdgpu_dm_ism_disable(&adev->dm); scoped_guard(mutex, &adev->dm.dc_lock) - amdgpu_dm_ism_disable(&adev->dm); + amdgpu_dm_ism_force_full_power(&adev->dm); amdgpu_dm_destroy_drm_device(&adev->dm); @@ -2330,6 +2411,10 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } + if (adev->dm.power_module) { + mod_power_destroy(adev->dm.power_module); + adev->dm.power_module = NULL; + } mutex_destroy(&adev->dm.audio_lock); mutex_destroy(&adev->dm.dc_lock); mutex_destroy(&adev->dm.dpia_aux_lock); @@ -3286,9 +3371,14 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block) if (amdgpu_in_reset(adev)) { enum dc_status res; + /* Quiesce ISM workers before taking dc_lock (workers take + * dc_lock themselves; syncing under it would deadlock). + */ + amdgpu_dm_ism_disable(dm); + mutex_lock(&dm->dc_lock); - amdgpu_dm_ism_disable(dm); + amdgpu_dm_ism_force_full_power(dm); dc_allow_idle_optimizations(adev->dm.dc, false); dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); @@ -3322,8 +3412,13 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block) amdgpu_dm_irq_suspend(adev); + /* + * Quiesce ISM workers before taking dc_lock (workers take dc_lock + * themselves; syncing under it would deadlock). + */ + amdgpu_dm_ism_disable(dm); scoped_guard(mutex, &dm->dc_lock) - amdgpu_dm_ism_disable(dm); + amdgpu_dm_ism_force_full_power(dm); hpd_rx_irq_work_suspend(dm); @@ -3338,7 +3433,7 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block) } struct drm_connector * -amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, +amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_commit *state, struct drm_crtc *crtc) { u32 i; @@ -4902,7 +4997,7 @@ static int register_outbox_irq_handlers(struct amdgpu_device *adev) * * This should only be called during atomic check. */ -int dm_atomic_get_state(struct drm_atomic_state *state, +int dm_atomic_get_state(struct drm_atomic_commit *state, struct dm_atomic_state **dm_state) { struct drm_device *dev = state->dev; @@ -4923,7 +5018,7 @@ int dm_atomic_get_state(struct drm_atomic_state *state, } static struct dm_atomic_state * -dm_atomic_get_new_state(struct drm_atomic_state *state) +dm_atomic_get_new_state(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -5050,8 +5145,8 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) #define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2) #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 -static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, - int bl_idx) +void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, + int bl_idx) { struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[bl_idx]; @@ -5213,15 +5308,34 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap max - min); } +static struct dc_stream_state *dm_find_stream_with_link( + struct amdgpu_display_manager *dm, + struct dc_link *link) +{ + struct dc_state *cur_dc_state = dm->dc->current_state; + struct dc_stream_state *stream = NULL; + int i; + + for (i = 0; i < cur_dc_state->stream_count; i++) { + stream = cur_dc_state->streams[i]; + if (stream->link == link) + return stream; + } + + return NULL; +} + static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, int bl_idx, u32 user_brightness) { struct amdgpu_dm_backlight_caps *caps; struct dc_link *link; - u32 brightness; - bool rc, reallow_idle = false; + u32 brightness = 0; + bool rc = false, reallow_idle = false; struct drm_connector *connector; + struct dc_stream_state *stream; + unsigned int min, max; list_for_each_entry(connector, &dm->ddev->mode_config.connector_list, head) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -5251,13 +5365,6 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, if (caps->brightness_mask) brightness |= caps->brightness_mask; - /* Change brightness based on AUX property */ - mutex_lock(&dm->dc_lock); - if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) { - dc_allow_idle_optimizations(dm->dc, false); - reallow_idle = true; - } - if (trace_amdgpu_dm_brightness_enabled()) { trace_amdgpu_dm_brightness(__builtin_return_address(0), user_brightness, @@ -5266,22 +5373,45 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, power_supply_is_system_supplied() > 0); } - if (caps->aux_support) { - rc = dc_link_set_backlight_level_nits(link, true, brightness, - AUX_BL_DEFAULT_TRANSITION_TIME_MS); - if (!rc) - DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); - } else { - struct set_backlight_level_params backlight_level_params = { 0 }; + stream = dm_find_stream_with_link(dm, link); + if (!stream) + return; - backlight_level_params.backlight_pwm_u16_16 = brightness; - backlight_level_params.transition_time_in_ms = 0; - - rc = dc_link_set_backlight_level(link, &backlight_level_params); - if (!rc) - DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); + mutex_lock(&dm->dc_lock); + if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) { + dc_allow_idle_optimizations(dm->dc, false); + reallow_idle = true; } + if (caps->aux_support) { + rc = mod_power_set_backlight_nits(dm->power_module, stream, brightness, + AUX_BL_DEFAULT_TRANSITION_TIME_MS, false, true); + } else { + /* power module uses millipercent */ + get_brightness_range(caps, &min, &max); + brightness = DIV_ROUND_CLOSEST(brightness * 100, (max - min)) * 1000; + rc = mod_power_set_backlight_percent(dm->power_module, stream, + brightness, 0, false); + } + + /* + * Some kms clients create a ramped backlight transition effect + * by rapidly changing the backlight. Yet we must wait on dmcub + * fw to exit psr/replay before programming backlight. To + * prevent lag, keep disable psr/replay and let the next atomic + * flip clear the event. + * + * ToDo: use ISM to handle rapidly backlight change + * + * Rapidly backlight change is similar to rapidly cursor events, + * which is now handled by ISM. ISM can delay the event until system + * is really idle, so we may use ISM to handle backlight change as well. + */ + amdgpu_dm_psr_set_event(dm, stream, true, + psr_event_hw_programming, true); + amdgpu_dm_replay_set_event(dm, stream, true, + replay_event_hw_programming, true); + if (dm->dc->caps.ips_support && reallow_idle) dc_allow_idle_optimizations(dm->dc, true); @@ -5499,6 +5629,8 @@ static void setup_backlight_device(struct amdgpu_display_manager *dm, static void amdgpu_set_panel_orientation(struct drm_connector *connector); + + /* * In this architecture, the association * connector -> encoder -> crtc @@ -5740,7 +5872,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) psr_feature_enabled = false; if (psr_feature_enabled) { - amdgpu_dm_set_psr_caps(link); + amdgpu_dm_set_psr_caps(link, aconnector); drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", aconnector->base.name, link->psr_settings.psr_feature_enabled, @@ -8366,7 +8498,7 @@ static int fill_hdr_info_packet(const struct drm_connector_state *state, static int amdgpu_dm_connector_atomic_check(struct drm_connector *conn, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *new_con_state = drm_atomic_get_new_connector_state(state, conn); @@ -8488,7 +8620,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_atomic_state *state = crtc_state->state; + struct drm_atomic_commit *state = crtc_state->state; struct drm_connector *connector = conn_state->connector; struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); @@ -8560,7 +8692,7 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check }; -static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_commit *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) { @@ -9404,9 +9536,21 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, if (acrtc_state) { timing = &acrtc_state->stream->timing; - if (amdgpu_ip_version(adev, DCE_HWIP, 0) < - IP_VERSION(3, 5, 0) || - !(adev->flags & AMD_IS_APU)) { + if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= + IP_VERSION(3, 2, 0) && + !(adev->flags & AMD_IS_APU)) { + /* + * DGPUs NV3x and newer that support idle optimizations + * experience intermittent flip-done timeouts on cursor + * updates. Restore 5s offdelay behavior for now. + * + * Discussion on the issue: + * https://lore.kernel.org/amd-gfx/20260217191632.1243826-1-sysdadmin@m1k.cloud/ + */ + config.offdelay_ms = 5000; + config.disable_immediate = false; + } else if (amdgpu_ip_version(adev, DCE_HWIP, 0) < + IP_VERSION(3, 5, 0)) { /* * Older HW and DGPU have issues with instant off; * use a 2 frame offdelay. @@ -9792,7 +9936,8 @@ static void update_stream_irq_parameters( spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); } -static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, +static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm, + struct dm_crtc_state *old_state, struct dm_crtc_state *new_state) { bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); @@ -9811,6 +9956,14 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR off->on: Get vblank ref\n", __func__, new_state->base.crtc->base.id); + + scoped_guard(mutex, &dm->dc_lock) { + dc_exit_ips_for_hw_access(dm->dc); + amdgpu_dm_psr_set_event(dm, new_state->stream, true, + psr_event_vrr_transition, true); + amdgpu_dm_replay_set_event(dm, new_state->stream, true, + replay_event_vrr, true); + } } else if (old_vrr_active && !new_vrr_active) { /* Transition VRR active -> inactive: * Allow vblank irq disable again for fixed refresh rate. @@ -9819,10 +9972,18 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, drm_crtc_vblank_put(new_state->base.crtc); drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR on->off: Drop vblank ref\n", __func__, new_state->base.crtc->base.id); + + scoped_guard(mutex, &dm->dc_lock) { + dc_exit_ips_for_hw_access(dm->dc); + amdgpu_dm_psr_set_event(dm, new_state->stream, false, + psr_event_vrr_transition, false); + amdgpu_dm_replay_set_event(dm, new_state->stream, false, + replay_event_vrr, false); + } } } -static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) +static void amdgpu_dm_commit_cursors(struct drm_atomic_commit *state) { struct drm_plane *plane; struct drm_plane_state *old_plane_state; @@ -9916,7 +10077,8 @@ static void amdgpu_dm_update_cursor(struct drm_plane *plane, } } -static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, +static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, + struct amdgpu_crtc *acrtc_attach, const struct dm_crtc_state *acrtc_state, const u64 current_ts) { @@ -9924,20 +10086,10 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; - bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); - - if (acrtc_state->update_type > UPDATE_TYPE_FAST) { - if (pr->config.replay_supported && !pr->replay_feature_enabled) - amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn); - else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED && - !psr->psr_feature_enabled) - if (!aconn->disallow_edp_enter_psr) - amdgpu_dm_link_setup_psr(acrtc_state->stream); - } /* Decrement skip count when SR is enabled and we're doing fast updates. */ if (acrtc_state->update_type == UPDATE_TYPE_FAST && - (psr->psr_feature_enabled || pr->config.replay_supported)) { + (psr->psr_feature_enabled || pr->replay_feature_enabled)) { if (aconn->sr_skip_count > 0) aconn->sr_skip_count--; @@ -9952,24 +10104,20 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, * of update events. * See `amdgpu_dm_crtc_vblank_control_worker()`. */ - if (!vrr_active && - acrtc_attach->dm_irq_params.allow_sr_entry && -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY - !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && -#endif - (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { - if (pr->replay_feature_enabled && !pr->replay_allow_active) - amdgpu_dm_replay_enable(acrtc_state->stream, true); - if (psr->psr_version == DC_PSR_VERSION_SU_1 && - !psr->psr_allow_active && !aconn->disallow_edp_enter_psr) - amdgpu_dm_psr_enable(acrtc_state->stream); + if (acrtc_attach->dm_irq_params.allow_sr_entry && + (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { + amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, + psr_event_hw_programming, false); + + amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, + replay_event_hw_programming, false); } } else { acrtc_attach->dm_irq_params.allow_sr_entry = false; } } -static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, +static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state, struct drm_device *dev, struct amdgpu_display_manager *dm, struct drm_crtc *pcrtc, @@ -10124,15 +10272,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, */ if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && acrtc_attach->dm_irq_params.allow_sr_entry && -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY - !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && -#endif dirty_rects_changed) { mutex_lock(&dm->dc_lock); acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = timestamp_ns; - if (acrtc_state->stream->link->psr_settings.psr_allow_active) - amdgpu_dm_psr_disable(acrtc_state->stream, true); + dc_exit_ips_for_hw_access(dm->dc); + amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, + psr_event_hw_programming, true); mutex_unlock(&dm->dc_lock); } } @@ -10297,15 +10443,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) bundle->stream_update.abm_level = &acrtc_state->abm_level; - mutex_lock(&dm->dc_lock); - if ((acrtc_state->update_type > UPDATE_TYPE_FAST) || vrr_active) { - if (acrtc_state->stream->link->replay_settings.replay_allow_active) - amdgpu_dm_replay_disable(acrtc_state->stream); - if (acrtc_state->stream->link->psr_settings.psr_allow_active) - amdgpu_dm_psr_disable(acrtc_state->stream, true); - } - mutex_unlock(&dm->dc_lock); - /* * If FreeSync state on the stream has changed then we need to * re-adjust the min/max bounds now that DC doesn't handle this @@ -10343,8 +10480,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) dm_update_pflip_irq_state(drm_to_adev(dev), acrtc_attach); - - amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns); + amdgpu_dm_enable_self_refresh(dm, acrtc_attach, acrtc_state, + timestamp_ns); mutex_unlock(&dm->dc_lock); } @@ -10363,7 +10500,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, } static void amdgpu_dm_commit_audio(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_dm_connector *aconnector; @@ -10463,7 +10600,118 @@ static void dm_clear_writeback(struct amdgpu_display_manager *dm, dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); } -static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, +/** + * amdgpu_dm_mod_power_update_streams - update mod_power stream state on modeset + * @state: the drm atomic state + * @dm: the display manager to update mod_power on + * + * Notify mod_power of stream changes on modeset events, and disable PSR/Replay + * in preparation for hardware programming. See also + * amdgpu_dm_mod_power_setup_streams() for post-modeset mod_power setup. + */ +static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, + struct amdgpu_display_manager *dm) +{ + struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + struct amdgpu_dm_connector *aconnector; + struct drm_crtc *crtc; + int i = 0; + + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + continue; + + /* + * Update mod_power on modeset event in preparation for hw + * programming. Always use the old stream, since it would have + * been previously added to mod_power. If old stream is null (on + * crtc enable, for example), mod_power will no-op, which is the + * desried behavior. + */ + if (old_crtc_state->active) { + scoped_guard(mutex, &dm->dc_lock) { + dc_exit_ips_for_hw_access(dm->dc); + amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true, + psr_event_hw_programming, true); + amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, + replay_event_hw_programming, true); + amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, false, + replay_event_general_ui, false); + } + } + + if (new_crtc_state->active) { + aconnector = (struct amdgpu_dm_connector *) + dm_new_crtc_state->stream->dm_stream_context; + if (old_crtc_state->active) { + mod_power_replace_stream(dm->power_module, + dm_old_crtc_state->stream, + dm_new_crtc_state->stream, + &aconnector->psr_caps); + } else { + mod_power_add_stream(dm->power_module, + dm_new_crtc_state->stream, + &aconnector->psr_caps); + } + } else if (old_crtc_state->active) { + mod_power_remove_stream(dm->power_module, + dm_old_crtc_state->stream); + } + } +} + +/** + * amdgpu_dm_mod_power_setup_streams - setup mod_power stream state post modeset + * @state: the drm atomic state + * @dm: the display manager to update mod_power on + * + * Notify mod_power of mode_change. This needs to be done after dc_stream + * updates have been committed, and VRR parameters have been updated. + */ +static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, + struct amdgpu_display_manager *dm) +{ + struct dm_crtc_state *dm_new_crtc_state; + struct drm_crtc_state *new_crtc_state; + struct amdgpu_crtc *acrtc; + struct drm_crtc *crtc; + int i = 0; + + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + acrtc = to_amdgpu_crtc(crtc); + + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + continue; + + if (new_crtc_state->active) { + amdgpu_dm_link_setup_replay(dm_new_crtc_state->stream, + &acrtc->dm_irq_params.vrr_params); + mod_power_notify_mode_change(dm->power_module, + dm_new_crtc_state->stream, + false); + + /* + * Block PSR / Replay on the new stream until display settles post-modeset. + * These events will be cleared by amdgpu_dm_enable_self_refresh() once + * allow_sr_entry becomes true. + */ + amdgpu_dm_psr_set_event(dm, dm_new_crtc_state->stream, true, + psr_event_hw_programming, true); + + amdgpu_dm_replay_set_event(dm, dm_new_crtc_state->stream, true, + replay_event_hw_programming | replay_event_general_ui, + true); + } + } + +} + +static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state, struct dc_state *dc_state) { struct drm_device *dev = state->dev; @@ -10506,6 +10754,8 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, acrtc->wb_enabled = false; } + amdgpu_dm_mod_power_update_streams(state, dm); + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); @@ -10610,13 +10860,10 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, } } /* for_each_crtc_in_state() */ - /* if there mode set or reset, disable eDP PSR, Replay */ + /* if there mode set or reset, flush vblank work queue */ if (mode_set_reset_required) { if (dm->vblank_control_workqueue) flush_workqueue(dm->vblank_control_workqueue); - - amdgpu_dm_replay_disable_all(dm); - amdgpu_dm_psr_disable_all(dm); } dm_enable_per_frame_crtc_master_sync(dc_state); @@ -10763,7 +11010,7 @@ static void dm_set_writeback(struct amdgpu_display_manager *dm, drm_writeback_queue_job(wb_conn, new_con_state); } -static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) +static void amdgpu_dm_update_hdcp(struct drm_atomic_commit *state) { struct drm_connector_state *old_con_state, *new_con_state; struct drm_device *dev = state->dev; @@ -10878,7 +11125,7 @@ static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) } } -static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) +static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -10919,7 +11166,7 @@ static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) * programming the hardware. Any failures here implies a hardware failure, since * atomic check should have filtered anything non-kosher. */ -static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) +static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -11089,7 +11336,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); } /* Handle vrr on->off / off->on transitions */ - amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); + amdgpu_dm_handle_vrr_transition(dm, dm_old_crtc_state, dm_new_crtc_state); #ifdef CONFIG_DEBUG_FS if (new_crtc_state->active && @@ -11127,6 +11374,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) #endif } + amdgpu_dm_mod_power_setup_streams(state, dm); + for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) if (new_crtc_state->async_flip) wait_for_vblank = false; @@ -11224,7 +11473,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector) { int ret = 0; struct drm_device *ddev = connector->dev; - struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); + struct drm_atomic_commit *state = drm_atomic_commit_alloc(ddev); struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); struct drm_plane *plane = disconnected_acrtc->base.primary; struct drm_connector_state *conn_state; @@ -11239,7 +11488,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector) /* Construct an atomic state to restore previous display setting */ /* - * Attach connectors to drm_atomic_state + * Attach connectors to drm_atomic_commit */ conn_state = drm_atomic_get_connector_state(state, connector); @@ -11249,7 +11498,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector) goto out; } - /* Attach crtc to drm_atomic_state*/ + /* Attach crtc to drm_atomic_commit*/ crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); /* Check for error in getting crtc state */ @@ -11261,7 +11510,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector) /* force a restore */ crtc_state->mode_changed = true; - /* Attach plane to drm_atomic_state */ + /* Attach plane to drm_atomic_commit */ plane_state = drm_atomic_get_plane_state(state, plane); /* Check for error in getting plane state */ @@ -11274,7 +11523,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector) ret = drm_atomic_commit(state); out: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); if (ret) drm_err(ddev, "Restoring old state failed with %i\n", ret); @@ -11323,7 +11572,7 @@ void dm_restore_drm_connector_state(struct drm_device *dev, * Waits for completion of all non blocking commits. */ static int do_aquire_global_lock(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_commit *commit; @@ -11468,7 +11717,7 @@ static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) } static int dm_update_crtc_state(struct amdgpu_display_manager *dm, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state, struct drm_crtc_state *new_crtc_state, @@ -11742,7 +11991,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, return ret; } -static bool should_reset_plane(struct drm_atomic_state *state, +static bool should_reset_plane(struct drm_atomic_commit *state, struct drm_plane *plane, struct drm_plane_state *old_plane_state, struct drm_plane_state *new_plane_state) @@ -12000,7 +12249,7 @@ static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, return 0; } -static bool dm_should_update_native_cursor(struct drm_atomic_state *state, +static bool dm_should_update_native_cursor(struct drm_atomic_commit *state, struct drm_crtc *old_plane_crtc, struct drm_crtc *new_plane_crtc, bool enable) @@ -12030,7 +12279,7 @@ static bool dm_should_update_native_cursor(struct drm_atomic_state *state, } static int dm_update_plane_state(struct dc *dc, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_plane *plane, struct drm_plane_state *old_plane_state, struct drm_plane_state *new_plane_state, @@ -12238,7 +12487,7 @@ dm_get_plane_scale(struct drm_plane_state *plane_state, * indefinitely. */ static inline struct __drm_planes_state *__get_next_zpos( - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct __drm_planes_state *prev) { unsigned int highest_zpos = 0, prev_zpos = 256; @@ -12288,7 +12537,7 @@ static inline struct __drm_planes_state *__get_next_zpos( (old_plane_state) = __i->old_state, \ (new_plane_state) = __i->new_state, 1)) -static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) +static int add_affected_mst_dsc_crtcs(struct drm_atomic_commit *state, struct drm_crtc *crtc) { struct drm_connector *connector; struct drm_connector_state *conn_state, *old_conn_state; @@ -12347,7 +12596,7 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm * * Return: true if the pipeline modifies pixels, false otherwise. */ -static bool dm_plane_color_pipeline_active(struct drm_atomic_state *state, +static bool dm_plane_color_pipeline_active(struct drm_atomic_commit *state, struct drm_plane *plane, bool use_old) { @@ -12387,7 +12636,7 @@ static bool dm_plane_color_pipeline_active(struct drm_atomic_state *state, * failed. */ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct dm_crtc_state *dm_crtc_state, enum amdgpu_dm_cursor_mode *cursor_mode) { @@ -12526,7 +12775,7 @@ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, } static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_crtc_state *crtc_state) { struct drm_plane *plane; @@ -12575,7 +12824,7 @@ static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, * Return: -Error code if validation failed. */ static int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct amdgpu_device *adev = drm_to_adev(dev); struct dm_atomic_state *dm_state = NULL; @@ -13685,11 +13934,17 @@ int amdgpu_dm_process_dmub_set_config_sync( bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) { + struct amdgpu_device *adev = ctx->driver_context; + + guard(spinlock_irqsave)(&adev->dm.dmub_lock); return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); } bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) { + struct amdgpu_device *adev = ctx->driver_context; + + guard(spinlock_irqsave)(&adev->dm.dmub_lock); return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 74a8fe1a1999..74f700fbeb6f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -463,6 +463,13 @@ struct amdgpu_display_manager { */ struct mutex dc_lock; + /** + * @dmub_lock: + * + * Guards access to DMUB command submission. + */ + spinlock_t dmub_lock; + /** * @audio_lock: * @@ -568,6 +575,7 @@ struct amdgpu_display_manager { struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; + struct mod_power *power_module; struct hdcp_workqueue *hdcp_workqueue; /** @@ -584,7 +592,7 @@ struct amdgpu_display_manager { */ struct idle_workqueue *idle_workqueue; - struct drm_atomic_state *cached_state; + struct drm_atomic_commit *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; @@ -835,6 +843,7 @@ struct amdgpu_dm_connector { bool force_yuv420_output; bool force_yuv422_output; struct dsc_preferred_settings dsc_settings; + struct psr_caps psr_caps; union dp_downstream_port_present mst_downstream_port_present; /* Cached display modes */ struct drm_display_mode freesync_vid_base; @@ -1123,11 +1132,11 @@ struct dc_stream_state * const struct dm_connector_state *dm_state, const struct dc_stream_state *old_stream); -int dm_atomic_get_state(struct drm_atomic_state *state, +int dm_atomic_get_state(struct drm_atomic_commit *state, struct dm_atomic_state **dm_state); struct drm_connector * -amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, +amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_commit *state, struct drm_crtc *crtc); int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); @@ -1149,4 +1158,5 @@ int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); void retrieve_dmi_info(struct amdgpu_display_manager *dm); +void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int bl_idx); #endif /* __AMDGPU_DM_H__ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index cd1e58b8defc..fa6883ae4dfb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -1499,7 +1499,7 @@ __set_dm_plane_colorop_degamma(struct drm_plane_state *plane_state, { struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; int i = 0; old_colorop = colorop; @@ -1526,7 +1526,7 @@ __set_dm_plane_colorop_3x4_matrix(struct drm_plane_state *plane_state, { struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; const struct drm_device *dev = colorop->dev; const struct drm_property_blob *blob; struct drm_color_ctm_3x4 *ctm = NULL; @@ -1567,7 +1567,7 @@ __set_dm_plane_colorop_multiplier(struct drm_plane_state *plane_state, { struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; const struct drm_device *dev = colorop->dev; int i = 0; @@ -1596,7 +1596,7 @@ __set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state, { struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; enum dc_transfer_func_predefined default_tf = TRANSFER_FUNCTION_LINEAR; struct dc_transfer_func *tf = &dc_plane_state->in_shaper_func; const struct drm_color_lut32 *shaper_lut; @@ -1704,7 +1704,7 @@ __set_dm_plane_colorop_3dlut(struct drm_plane_state *plane_state, struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; struct dc_transfer_func *tf = &dc_plane_state->in_shaper_func; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; const struct amdgpu_device *adev = drm_to_adev(colorop->dev); bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend; const struct drm_device *dev = colorop->dev; @@ -1759,7 +1759,7 @@ __set_dm_plane_colorop_blend(struct drm_plane_state *plane_state, { struct drm_colorop *old_colorop; struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; - struct drm_atomic_state *state = plane_state->state; + struct drm_atomic_commit *state = plane_state->state; enum dc_transfer_func_predefined default_tf = TRANSFER_FUNCTION_LINEAR; struct dc_transfer_func *tf = &dc_plane_state->blend_tf; const struct drm_color_lut32 *blend_lut = NULL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 62573173e2ac..5adbb0f6a0c8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -503,7 +503,6 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, { struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dc_stream_state *stream_state = dm_crtc_state->stream; - struct amdgpu_dm_connector *aconnector = NULL; bool enable = amdgpu_dm_is_valid_crc_source(source); int ret = 0; enum crc_poly_mode crc_poly_mode = CRC_POLY_MODE_16; @@ -512,21 +511,17 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, if (!stream_state) return -EINVAL; - /* Get connector from stream */ - aconnector = (struct amdgpu_dm_connector *)stream_state->dm_stream_context; - mutex_lock(&adev->dm.dc_lock); - + /* Notify power module about CRC window active to disable PSR/Replay + * Power module will check caps internally and skip if not supported + */ if (enable) { - /* For PSR1, check that the panel has exited PSR */ - if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) - amdgpu_dm_psr_wait_disable(stream_state); + amdgpu_dm_psr_set_event(&adev->dm, stream_state, true, + psr_event_crc_window_active, true); - /* Set flag to disallow enter replay when CRC source is enabled */ - if (aconnector) - aconnector->disallow_edp_enter_replay = true; - amdgpu_dm_replay_disable(stream_state); + amdgpu_dm_replay_set_event(&adev->dm, stream_state, true, + replay_event_crc_window_active, true); } /* CRC polynomial selection only support for DCN3.6+ except DCN4.0.1 */ @@ -559,11 +554,15 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, } if (!enable) { - /* Clear flag to allow enter replay when CRC source is disabled */ - if (aconnector) - aconnector->disallow_edp_enter_replay = false; - } + /* Notify power module about CRC window inactive to re-enable PSR/Replay + * Power module will check caps internally and skip if not supported + */ + amdgpu_dm_psr_set_event(&adev->dm, stream_state, false, + psr_event_crc_window_active, false); + amdgpu_dm_replay_set_event(&adev->dm, stream_state, false, + replay_event_crc_window_active, false); + } unlock: mutex_unlock(&adev->dm.dc_lock); @@ -614,8 +613,13 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) */ ret = wait_for_completion_interruptible_timeout( &commit->hw_done, 10 * HZ); - if (ret) + if (ret < 0) goto cleanup; + + if (ret == 0) { + ret = -ETIMEDOUT; + goto cleanup; + } } enable = amdgpu_dm_is_valid_crc_source(source); @@ -760,10 +764,13 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) uint32_t crcs[3]; unsigned long flags; - if (crtc == NULL) + if (!crtc || !crtc->state || !crtc->dev) return; crtc_state = to_dm_crtc_state(crtc->state); + if (!crtc_state->stream) + return; + stream_state = crtc_state->stream; acrtc = to_amdgpu_crtc(crtc); drm_dev = crtc->dev; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index d69f5a75b685..3dcedaa67ed8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -34,6 +34,7 @@ #include "amdgpu_dm_plane.h" #include "amdgpu_dm_trace.h" #include "amdgpu_dm_debugfs.h" +#include "modules/inc/mod_power.h" #define HPD_DETECTION_PERIOD_uS 2000000 #define HPD_DETECTION_TIME_uS 100000 @@ -100,68 +101,33 @@ bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state) } /** - * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features. - * @dm: amdgpu display manager instance. - * @acrtc: CRTC whose panel self-refresh state is being updated. - * @stream: DC stream associated with @acrtc. - * @vblank_enabled: Whether the DRM vblank counter is currently enabled. - * @allow_sr_entry: Whether entry into self-refresh mode is allowed. + * amdgpu_dm_crtc_set_static_screen_optimze() - Toggle static screen optimizations. * - * The DRM vblank counter enable/disable action is used as the trigger to enable - * or disable various panel self-refresh features: + * @dm: display manager + * @stream: DC stream state + * @sso_enable: desired static screen optimization state + * @allow_sr_entry: whether entry into self-refresh mode is allowed * - * Panel Replay and PSR SU - * - Enable when: - * - VRR is disabled - * - vblank counter is disabled - * - entry is allowed: usermode demonstrates an adequate number of fast - * commits - * - CRC capture window isn't active - * - Keep enabled even when vblank counter gets enabled - * - * PSR1 - * - Enable condition same as above - * - Disable when vblank counter is enabled + * This function uses the static-screen optimization state as the trigger to + * set/clear the Replay and PSR vsync-related events. */ -void amdgpu_dm_crtc_set_panel_sr_feature( +void amdgpu_dm_crtc_set_static_screen_optimze( struct amdgpu_display_manager *dm, - struct amdgpu_crtc *acrtc, struct dc_stream_state *stream, - bool vblank_enabled, bool allow_sr_entry) + bool sso_enable, bool allow_sr_entry) { struct dc_link *link = stream->link; - bool is_sr_active = (link->replay_settings.replay_allow_active || - link->psr_settings.psr_allow_active); - bool is_crc_window_active = false; - bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); + bool set_vsync_event = !sso_enable; -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY - is_crc_window_active = - amdgpu_dm_crc_window_is_activated(&acrtc->base); -#endif + if (!allow_sr_entry) + return; - if (link->replay_settings.replay_feature_enabled && !vrr_active && - allow_sr_entry && !is_sr_active && !is_crc_window_active) { - amdgpu_dm_replay_enable(stream, true); - } else if (vblank_enabled) { - if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active) - amdgpu_dm_psr_disable(stream, false); - } else if (link->psr_settings.psr_feature_enabled && !vrr_active && - allow_sr_entry && !is_sr_active && !is_crc_window_active) { + amdgpu_dm_replay_set_event(dm, stream, + set_vsync_event, replay_event_vsync, set_vsync_event); - struct amdgpu_dm_connector *aconn = - (struct amdgpu_dm_connector *) stream->dm_stream_context; - - if (!aconn->disallow_edp_enter_psr) { - amdgpu_dm_psr_enable(stream); - if (dm->idle_workqueue && - (dm->dc->config.disable_ips == DMUB_IPS_ENABLE) && - dm->dc->idle_optimizations_allowed && - dm->idle_workqueue->enable && - !dm->idle_workqueue->running) - schedule_work(&dm->idle_workqueue->work); - } - } + if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) + amdgpu_dm_psr_set_event(dm, stream, + set_vsync_event, psr_event_vsync, set_vsync_event); } bool amdgpu_dm_is_headless(struct amdgpu_device *adev) @@ -584,7 +550,7 @@ static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc) static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) { - struct drm_atomic_state *state = new_crtc_state->state; + struct drm_atomic_commit *state = new_crtc_state->state; struct drm_plane *plane; int num_active = 0; @@ -637,7 +603,7 @@ static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, } static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h index 3a8094013a5d..e9fb52f0e66d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h @@ -27,11 +27,10 @@ #ifndef __AMDGPU_DM_CRTC_H__ #define __AMDGPU_DM_CRTC_H__ -void amdgpu_dm_crtc_set_panel_sr_feature( +void amdgpu_dm_crtc_set_static_screen_optimze( struct amdgpu_display_manager *dm, - struct amdgpu_crtc *acrtc, struct dc_stream_state *stream, - bool vblank_enabled, bool allow_sr_entry); + bool sso_enable, bool allow_sr_entry); void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 2409ac72b166..4b09a740f205 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -33,6 +33,7 @@ #include "amdgpu_dm.h" #include "amdgpu_dm_debugfs.h" #include "amdgpu_dm_replay.h" +#include "amdgpu_dm_psr.h" #include "dm_helpers.h" #include "dmub/dmub_srv.h" #include "resource.h" @@ -3162,10 +3163,25 @@ static int replay_get_state(void *data, u64 *val) { struct amdgpu_dm_connector *connector = data; struct dc_link *link = connector->dc_link; + struct amdgpu_device *adev = drm_to_adev(connector->base.dev); + struct dc *dc = adev->dm.dc; uint64_t state = REPLAY_STATE_INVALID; + bool reallow_idle = false; + + mutex_lock(&adev->dm.dc_lock); + + if (dc->idle_optimizations_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } dc_link_get_replay_state(link, &state); + if (reallow_idle) + dc_allow_idle_optimizations(dc, true); + + mutex_unlock(&adev->dm.dc_lock); + *val = state; return 0; @@ -3178,10 +3194,26 @@ static int replay_set_residency(void *data, u64 val) { struct amdgpu_dm_connector *connector = data; struct dc_link *link = connector->dc_link; + struct amdgpu_device *adev = drm_to_adev(connector->base.dev); + struct dc *dc = adev->dm.dc; bool is_start = (val != 0); u32 residency = 0; + bool reallow_idle = false; + + mutex_lock(&adev->dm.dc_lock); + + if (dc->idle_optimizations_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY); + + if (reallow_idle) + dc_allow_idle_optimizations(dc, true); + + mutex_unlock(&adev->dm.dc_lock); + return 0; } @@ -3192,9 +3224,25 @@ static int replay_get_residency(void *data, u64 *val) { struct amdgpu_dm_connector *connector = data; struct dc_link *link = connector->dc_link; + struct amdgpu_device *adev = drm_to_adev(connector->base.dev); + struct dc *dc = adev->dm.dc; u32 residency = 0; + bool reallow_idle = false; + + mutex_lock(&adev->dm.dc_lock); + + if (dc->idle_optimizations_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY); + + if (reallow_idle) + dc_allow_idle_optimizations(dc, true); + + mutex_unlock(&adev->dm.dc_lock); + *val = (u64)residency; return 0; @@ -3207,10 +3255,25 @@ static int psr_get(void *data, u64 *val) { struct amdgpu_dm_connector *connector = data; struct dc_link *link = connector->dc_link; + struct amdgpu_device *adev = drm_to_adev(connector->base.dev); + struct dc *dc = adev->dm.dc; enum dc_psr_state state = PSR_STATE0; + bool reallow_idle = false; + + mutex_lock(&adev->dm.dc_lock); + + if (dc->idle_optimizations_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } dc_link_get_psr_state(link, &state); + if (reallow_idle) + dc_allow_idle_optimizations(dc, true); + + mutex_unlock(&adev->dm.dc_lock); + *val = state; return 0; @@ -3223,10 +3286,25 @@ static int psr_read_residency(void *data, u64 *val) { struct amdgpu_dm_connector *connector = data; struct dc_link *link = connector->dc_link; + struct amdgpu_device *adev = drm_to_adev(connector->base.dev); + struct dc *dc = adev->dm.dc; u32 residency = 0; + bool reallow_idle = false; + + mutex_lock(&adev->dm.dc_lock); + + if (dc->idle_optimizations_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY); + if (reallow_idle) + dc_allow_idle_optimizations(dc, true); + + mutex_unlock(&adev->dm.dc_lock); + *val = (u64)residency; return 0; @@ -3300,11 +3378,26 @@ static int disallow_edp_enter_psr_get(void *data, u64 *val) static int disallow_edp_enter_psr_set(void *data, u64 val) { struct amdgpu_dm_connector *aconnector = data; + struct dc_link *link = aconnector->dc_link; - aconnector->disallow_edp_enter_psr = val ? true : false; + aconnector->disallow_edp_enter_psr = (val != 0); + + /* eDP PSR enable / disable is happened during mode change in power module. + * Only psr_settings.psr_version is used to decide whether PSR is enabled or not. + * So here we only update psr_version based on debugfs setting. + * If disallow_edp_enter_psr is true, set psr_version to unsupported; + * if disallow_edp_enter_psr is false, set psr_version based on sink capability. + */ + if (aconnector->disallow_edp_enter_psr) + link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; + else if (aconnector->psr_caps.psr_version == 1) + link->psr_settings.psr_version = DC_PSR_VERSION_1; + else if (aconnector->psr_caps.psr_version == 2) + link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; return 0; } + /* check if kernel disallow eDP enter replay state * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay * 0: allow edp enter replay; 1: disallow @@ -3346,11 +3439,27 @@ static int disallow_edp_enter_replay_get(void *data, u64 *val) static int disallow_edp_enter_replay_set(void *data, u64 val) { struct amdgpu_dm_connector *aconnector = data; + struct dc_link *link = aconnector->dc_link; - aconnector->disallow_edp_enter_replay = val ? true : false; + aconnector->disallow_edp_enter_replay = (val != 0); + + /* eDP replay enable / disable is happened during mode change in power module. + * Only replay_settings.config.replay_supported is used to decide whether + * replay is enabled or not. So here we only update replay_supported based on + * debugfs setting. + * If disallow_edp_enter_replay is true, set replay_supported to false. + * if disallow_edp_enter_replay is false, set replay_supported back based on + * sink replay capability. + */ + if (aconnector->disallow_edp_enter_replay) + link->replay_settings.config.replay_supported = false; + else + link->replay_settings.config.replay_supported = + link->replay_settings.config.replay_cap_support; return 0; } + static int dmub_trace_mask_set(void *data, u64 val) { struct amdgpu_device *adev = data; @@ -3485,6 +3594,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_replay_fops, DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get, ips_residency_cntl_set, "%llu\n"); + DEFINE_SHOW_ATTRIBUTE(current_backlight); DEFINE_SHOW_ATTRIBUTE(target_backlight); DEFINE_SHOW_ATTRIBUTE(ips_status); @@ -3855,28 +3965,35 @@ DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, static int crc_win_update_set(void *data, u64 val) { struct drm_crtc *crtc = data; - struct amdgpu_crtc *acrtc; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = drm_to_adev(crtc->dev); if (val) { - acrtc = to_amdgpu_crtc(crtc); mutex_lock(&adev->dm.dc_lock); - /* PSR may write to OTG CRC window control register, - * so close it before starting secure_display. + /* PSR Replay may write to OTG CRC window control register, + * so inactive it before starting secure_display by sending disable event. */ - amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream, true); + amdgpu_dm_psr_set_event(&adev->dm, acrtc->dm_irq_params.stream, true, + psr_event_crc_window_active, true); + amdgpu_dm_replay_set_event(&adev->dm, acrtc->dm_irq_params.stream, true, + replay_event_crc_window_active, true); spin_lock_irq(&adev_to_drm(adev)->event_lock); - acrtc->dm_irq_params.window_param[0].enable = true; acrtc->dm_irq_params.window_param[0].update_win = true; acrtc->dm_irq_params.window_param[0].skip_frame_cnt = 0; acrtc->dm_irq_params.crc_window_activated = true; - spin_unlock_irq(&adev_to_drm(adev)->event_lock); mutex_unlock(&adev->dm.dc_lock); + } else { + /* Clear disable events to allow PSR/Replay to active */ + mutex_lock(&adev->dm.dc_lock); + amdgpu_dm_psr_set_event(&adev->dm, acrtc->dm_irq_params.stream, false, + psr_event_crc_window_active, false); + amdgpu_dm_replay_set_event(&adev->dm, acrtc->dm_irq_params.stream, false, + replay_event_crc_window_active, false); + mutex_unlock(&adev->dm.dc_lock); } - return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 3b8ae7798a93..a3cb05490dc9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1032,6 +1032,45 @@ dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector) return drm_edid_read_custom(connector, dm_helpers_probe_acpi_edid, connector); } +static const struct drm_edid * +dm_helpers_read_vbios_hardcoded_edid(struct dc_link *link, struct amdgpu_dm_connector *aconnector) +{ + struct dc_bios *bios = link->ctx->dc_bios; + struct embedded_panel_info info; + const struct drm_edid *edid; + enum bp_result r; + + if (!dc_is_embedded_signal(link->connector_signal) || + !bios->funcs->get_embedded_panel_info) + return NULL; + + memset(&info, 0, sizeof(info)); + r = bios->funcs->get_embedded_panel_info(bios, &info); + + if (r != BP_RESULT_OK) { + dm_error("Error when reading embedded panel info: %u\n", r); + return NULL; + } + + if (!info.fake_edid || !info.fake_edid_size) { + dm_error("Embedded panel info doesn't contain an EDID\n"); + return NULL; + } + + edid = drm_edid_alloc(info.fake_edid, info.fake_edid_size); + + if (!drm_edid_valid(edid)) { + dm_error("EDID from embedded panel info is invalid\n"); + drm_edid_free(edid); + return NULL; + } + + aconnector->base.display_info.width_mm = info.panel_width_mm; + aconnector->base.display_info.height_mm = info.panel_height_mm; + + return edid; +} + void populate_hdmi_info_from_connector(struct drm_hdmi_info *hdmi, struct dc_edid_caps *edid_caps) { edid_caps->scdc_present = hdmi->scdc.supported; @@ -1052,6 +1091,9 @@ enum dc_edid_status dm_helpers_read_local_edid( if (link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; + else if (link->ddc_hw_inst == GPIO_DDC_LINE_UNKNOWN && + dc_is_embedded_signal(link->connector_signal)) + ddc = NULL; else ddc = &aconnector->i2c->base; @@ -1065,6 +1107,8 @@ enum dc_edid_status dm_helpers_read_local_edid( drm_edid = dm_helpers_read_acpi_edid(aconnector); if (drm_edid) drm_info(connector->dev, "Using ACPI provided EDID for %s\n", connector->name); + else if (!ddc) + drm_edid = dm_helpers_read_vbios_hardcoded_edid(link, aconnector); else drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c index a64e95860e99..7dcc587c45e9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c @@ -291,24 +291,16 @@ static void dm_ism_commit_idle_optimization_state(struct amdgpu_dm_ism *ism, */ if (stream && stream->link) { /* - * If allow_panel_sso is true when disabling vblank, allow - * deeper panel sleep states such as PSR1 and Replay static - * screen optimization. - */ - if (!vblank_enabled && allow_panel_sso) { - amdgpu_dm_crtc_set_panel_sr_feature( - dm, acrtc, stream, false, - acrtc->dm_irq_params.allow_sr_entry); - } else if (vblank_enabled) { - /* Make sure to exit SSO on vblank enable */ - amdgpu_dm_crtc_set_panel_sr_feature( - dm, acrtc, stream, true, - acrtc->dm_irq_params.allow_sr_entry); - } - /* - * Else, vblank_enabled == false and allow_panel_sso == false; - * do nothing here. + * If the OS requires vblank events (or vblank is otherwise enabled), + * do not allow static screen optimizations. + * + * Keep ism->allow_static_screen_optimizations unchanged so the + * hysteresis-based decision can be reused once vblank is disabled. */ + allow_panel_sso = allow_panel_sso && !vblank_enabled; + amdgpu_dm_crtc_set_static_screen_optimze( + dm, stream, allow_panel_sso, + acrtc->dm_irq_params.allow_sr_entry); } /* @@ -459,8 +451,8 @@ void amdgpu_dm_ism_commit_event(struct amdgpu_dm_ism *ism, struct amdgpu_display_manager *dm = &adev->dm; struct dm_crtc_state *acrtc_state = to_dm_crtc_state(acrtc->base.state); - /* ISM transitions must be called with mutex acquired */ - ASSERT(mutex_is_locked(&dm->dc_lock)); + /* ISM transitions must be called with dc_lock held */ + lockdep_assert_held(&dm->dc_lock); /* ISM should not run after dc is destroyed */ ASSERT(dm->dc); @@ -524,13 +516,20 @@ static void dm_ism_sso_delayed_work_func(struct work_struct *work) } /** - * amdgpu_dm_ism_disable - Disable the ISM + * amdgpu_dm_ism_disable - Quiesce ISM workers * * @dm: The amdgpu display manager * - * Disable the idle state manager by disabling any ISM work, canceling pending - * work, and waiting for in-progress work to finish. After disabling, the system - * is left in DM_ISM_STATE_FULL_POWER_RUNNING state. + * Cancels and disables any pending or in-flight ISM delayed work and waits + * for in-progress work to finish. After this returns, no ISM worker can run + * and subsequent mod_delayed_work() calls become no-ops via + * clear_pending_if_disabled(). + * + * Must NOT be called with dc_lock held: the workers themselves take dc_lock, + * so a synchronous wait under dc_lock would deadlock. + * + * The caller is responsible for driving the FSM back to FULL_POWER_RUNNING + * (under dc_lock) by calling amdgpu_dm_ism_force_full_power(). */ void amdgpu_dm_ism_disable(struct amdgpu_display_manager *dm) { @@ -538,21 +537,54 @@ void amdgpu_dm_ism_disable(struct amdgpu_display_manager *dm) struct amdgpu_crtc *acrtc; struct amdgpu_dm_ism *ism; - ASSERT(mutex_is_locked(&dm->dc_lock)); + /* + * Caller must NOT hold dc_lock: the ISM delayed work handlers + * acquire dc_lock themselves, so waiting for them via + * disable_delayed_work_sync() while holding dc_lock would + * self-deadlock against an in-flight worker. + */ + lockdep_assert_not_held(&dm->dc_lock); drm_for_each_crtc(crtc, dm->ddev) { acrtc = to_amdgpu_crtc(crtc); ism = &acrtc->ism; - /* Cancel and disable any pending work */ disable_delayed_work_sync(&ism->delayed_work); disable_delayed_work_sync(&ism->sso_delayed_work); + } +} + +/** + * amdgpu_dm_ism_force_full_power - Force every CRTC's ISM FSM to FULL_POWER + * + * @dm: The amdgpu display manager + * + * Sends DM_ISM_EVENT_EXIT_IDLE_REQUESTED to every CRTC's ISM, leaving each + * FSM in FULL_POWER_RUNNING. Intended to be paired with + * amdgpu_dm_ism_disable(): callers should first quiesce workers (without + * dc_lock), then take dc_lock and call this helper. + * + * Must be called with dc_lock held. + */ +void amdgpu_dm_ism_force_full_power(struct amdgpu_display_manager *dm) +{ + struct drm_crtc *crtc; + struct amdgpu_crtc *acrtc; + + /* + * Caller must hold dc_lock: commit_event() drives the FSM and + * may touch dc state via dc_allow_idle_optimizations() etc. + */ + lockdep_assert_held(&dm->dc_lock); + + drm_for_each_crtc(crtc, dm->ddev) { + acrtc = to_amdgpu_crtc(crtc); /* * When disabled, leave in FULL_POWER_RUNNING state. - * EXIT_IDLE will not queue any work + * EXIT_IDLE will not queue any work. */ - amdgpu_dm_ism_commit_event(ism, + amdgpu_dm_ism_commit_event(&acrtc->ism, DM_ISM_EVENT_EXIT_IDLE_REQUESTED); } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.h index fde0ddc8d4e4..964408cd9a83 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.h @@ -146,6 +146,7 @@ void amdgpu_dm_ism_fini(struct amdgpu_dm_ism *ism); void amdgpu_dm_ism_commit_event(struct amdgpu_dm_ism *ism, enum amdgpu_dm_ism_event event); void amdgpu_dm_ism_disable(struct amdgpu_display_manager *dm); +void amdgpu_dm_ism_force_full_power(struct amdgpu_display_manager *dm); void amdgpu_dm_ism_enable(struct amdgpu_display_manager *dm); #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index be038d9014bb..51924ae87705 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -497,7 +497,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) static struct drm_encoder * dm_mst_atomic_best_encoder(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, connector); @@ -579,7 +579,7 @@ dm_dp_mst_detect(struct drm_connector *connector, } static int dm_dp_mst_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; @@ -986,7 +986,7 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) return dsc_config.bits_per_pixel; } -static int increase_dsc_bpp(struct drm_atomic_state *state, +static int increase_dsc_bpp(struct drm_atomic_commit *state, struct drm_dp_mst_topology_state *mst_state, struct dc_link *dc_link, struct dsc_mst_fairness_params *params, @@ -1090,7 +1090,7 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, return 0; } -static int try_disable_dsc(struct drm_atomic_state *state, +static int try_disable_dsc(struct drm_atomic_commit *state, struct dc_link *dc_link, struct dsc_mst_fairness_params *params, struct dsc_mst_fairness_vars *vars, @@ -1183,7 +1183,7 @@ static void log_dsc_params(int count, struct dsc_mst_fairness_vars *vars, int k) i, vars[i + k].dsc_enabled, vars[i + k].bpp_x16, vars[i + k].pbn); } -static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, +static int compute_mst_dsc_configs_for_link(struct drm_atomic_commit *state, struct dc_state *dc_state, struct dc_link *dc_link, struct dsc_mst_fairness_vars *vars, @@ -1348,7 +1348,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, } static bool is_dsc_need_re_compute( - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct dc_state *dc_state, struct dc_link *dc_link) { @@ -1479,7 +1479,7 @@ static bool is_dsc_need_re_compute( return is_dsc_need_re_compute; } -int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, +int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) { @@ -1549,7 +1549,7 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, return ret; } -static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, +static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) { @@ -1602,7 +1602,7 @@ static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, return ret; } -static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state, +static int find_crtc_index_in_state_by_stream(struct drm_atomic_commit *state, struct dc_stream_state *stream) { int i; @@ -1633,7 +1633,7 @@ static bool is_link_to_dschub(struct dc_link *dc_link) return true; } -static bool is_dsc_precompute_needed(struct drm_atomic_state *state) +static bool is_dsc_precompute_needed(struct drm_atomic_commit *state) { int i; struct drm_crtc *crtc; @@ -1654,7 +1654,7 @@ static bool is_dsc_precompute_needed(struct drm_atomic_state *state) return ret; } -int pre_validate_dsc(struct drm_atomic_state *state, +int pre_validate_dsc(struct drm_atomic_commit *state, struct dm_atomic_state **dm_state_ptr, struct dsc_mst_fairness_vars *vars) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 6f7ea684b555..0e8eef5bdb74 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -80,13 +80,13 @@ struct dsc_mst_fairness_vars { struct amdgpu_dm_connector *aconnector; }; -int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, +int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars); bool needs_dsc_aux_workaround(struct dc_link *link); -int pre_validate_dsc(struct drm_atomic_state *state, +int pre_validate_dsc(struct drm_atomic_commit *state, struct dm_atomic_state **dm_state_ptr, struct dsc_mst_fairness_vars *vars); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 81e43534ec59..e957657b06c7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1227,7 +1227,7 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, } static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -1274,7 +1274,7 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, } static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, - struct drm_atomic_state *state, bool flip) + struct drm_atomic_commit *state, bool flip) { struct drm_crtc_state *new_crtc_state; struct drm_plane_state *new_plane_state; @@ -1431,7 +1431,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, } static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index 99d6d6c93561..dc5913a6456e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -58,171 +58,76 @@ static bool link_supports_psrsu(struct dc_link *link) return false; } +static void amdgpu_dm_psr_fill_caps(struct dc_link *link, struct psr_caps *caps) +{ + struct dpcd_caps *dpcd_caps = &link->dpcd_caps; + unsigned int power_opts = 0; + + if (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) + power_opts |= psr_power_opt_smu_opt_static_screen; + power_opts |= psr_power_opt_z10_static_screen; + + if (link->psr_settings.psr_version == DC_PSR_VERSION_1) + caps->psr_version = 1; + else if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) + caps->psr_version = 2; + + caps->psr_rfb_setup_time = (6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * 55; + caps->psr_exit_link_training_required = + !dpcd_caps->psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED; + caps->edp_revision = dpcd_caps->edp_rev; + caps->support_ver = dpcd_caps->psr_info.psr_version; + caps->su_granularity_required = + dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED; + caps->y_coordinate_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED; + caps->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap; + caps->alpm_cap = dpcd_caps->alpm_caps.bits.AUX_WAKE_ALPM_CAP; + caps->standby_support = dpcd_caps->alpm_caps.bits.PM_STATE_2A_SUPPORT; + caps->rate_control_caps = 0; /* TODO: read in rc caps from aux */ + caps->psr_power_opt_flag = power_opts; +} + /* * amdgpu_dm_set_psr_caps() - set link psr capabilities * @link: link - * + * @aconnector: amdgpu_dm_connector */ -void amdgpu_dm_set_psr_caps(struct dc_link *link) +bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector) { - if (!(link->connector_signal & SIGNAL_TYPE_EDP)) { - link->psr_settings.psr_feature_enabled = false; - return; - } + struct dc *dc; + unsigned int panel_inst = 0; - if (link->type == dc_connection_none) { - link->psr_settings.psr_feature_enabled = false; - return; - } - - if (link->dpcd_caps.psr_info.psr_version == 0) { - link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; - link->psr_settings.psr_feature_enabled = false; - - } else { - unsigned int panel_inst = 0; - - if (link_supports_psrsu(link)) - link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; - else - link->psr_settings.psr_version = DC_PSR_VERSION_1; - - link->psr_settings.psr_feature_enabled = true; - - /*disable allow psr/psrsu/replay on eDP1*/ - if (dc_get_edp_link_panel_inst(link->ctx->dc, link, &panel_inst) && panel_inst == 1) { - link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; - link->psr_settings.psr_feature_enabled = false; - } - } -} - -/* - * amdgpu_dm_link_setup_psr() - configure psr link - * @stream: stream state - * - * Return: true if success - */ -bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) -{ - struct dc_link *link = NULL; - struct psr_config psr_config = {0}; - struct psr_context psr_context = {0}; - struct dc *dc = NULL; - bool ret = false; - - if (stream == NULL) + if (!link || !aconnector) return false; - link = stream->link; dc = link->ctx->dc; - if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) { - mod_power_calc_psr_configs(&psr_config, link, stream); + /* Reset psr version first */ + link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; - /* linux DM specific updating for psr config fields */ - psr_config.allow_smu_optimizations = - (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) && - mod_power_only_edp(dc->current_state, stream); - psr_config.allow_multi_disp_optimizations = - (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); + if (!dc->caps.dmub_caps.psr) + return false; - if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) { - if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config)) - return false; - } + if (!(link->connector_signal & SIGNAL_TYPE_EDP)) + return false; - ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); + if (link->type == dc_connection_none) + return false; - } - DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled); + if (link->dpcd_caps.psr_info.psr_version == 0) + return false; - return ret; -} + /*disable allow psr/psrsu/replay on eDP1*/ + if (dc_get_edp_link_panel_inst(link->ctx->dc, link, &panel_inst) && panel_inst == 1) + return false; -/* - * amdgpu_dm_psr_enable() - enable psr f/w - * @stream: stream state - * - */ -void amdgpu_dm_psr_enable(struct dc_stream_state *stream) -{ - struct dc_link *link = stream->link; - unsigned int vsync_rate_hz = 0; - struct dc_static_screen_params params = {0}; - /* Calculate number of static frames before generating interrupt to - * enter PSR. - */ - // Init fail safe of 2 frames static - unsigned int num_frames_static = 2; - unsigned int power_opt = 0; - bool psr_enable = true; + if (link_supports_psrsu(link)) + link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; + else + link->psr_settings.psr_version = DC_PSR_VERSION_1; - DRM_DEBUG_DRIVER("Enabling psr...\n"); - - vsync_rate_hz = div64_u64(div64_u64(( - stream->timing.pix_clk_100hz * (uint64_t)100), - stream->timing.v_total), - stream->timing.h_total); - - /* Round up - * Calculate number of frames such that at least 30 ms of time has - * passed. - */ - if (vsync_rate_hz != 0) { - unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; - - num_frames_static = (30000 / frame_time_microsec) + 1; - } - - params.triggers.cursor_update = true; - params.triggers.overlay_update = true; - params.triggers.surface_update = true; - params.num_frames = num_frames_static; - - dc_stream_set_static_screen_params(link->ctx->dc, - &stream, 1, - ¶ms); - - /* - * Only enable static-screen optimizations for PSR1. For PSR SU, this - * causes vstartup interrupt issues, used by amdgpu_dm to send vblank - * events. - */ - if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) - power_opt |= psr_power_opt_z10_static_screen; - - dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt); - - if (link->ctx->dc->caps.ips_support) - dc_allow_idle_optimizations(link->ctx->dc, true); -} - -/* - * amdgpu_dm_psr_disable() - disable psr f/w - * @stream: stream state - * - * Return: true if success - */ -bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait) -{ - bool psr_enable = false; - - DRM_DEBUG_DRIVER("Disabling psr...\n"); - - return dc_link_set_psr_allow_active(stream->link, &psr_enable, wait, false, NULL); -} - -/* - * amdgpu_dm_psr_disable_all() - disable psr f/w for all streams - * if psr is enabled on any stream - * - * Return: true if success - */ -bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) -{ - DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n"); - return dc_set_psr_allow_active(dm->dc, false); + amdgpu_dm_psr_fill_caps(link, &aconnector->psr_caps); + return true; } /* @@ -250,36 +155,37 @@ bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm) break; } } - return allow_active; } -/** - * amdgpu_dm_psr_wait_disable() - Wait for eDP panel to exit PSR - * @stream: stream state attached to the eDP link +/* + * amdgpu_dm_psr_set_event() - set or clear PSR event for stream + * @dm: pointer to amdgpu_display_manager + * @stream: pointer to dc_stream_state + * @set_event: true to set event, false to clear event + * @event: PSR event type + * @wait_for_disable: whether to wait for PSR to be disabled * - * Waits for a max of 500ms for the eDP panel to exit PSR. - * - * Return: true if panel exited PSR, false otherwise. + * Return: true if successful, false otherwise */ -bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream) +bool amdgpu_dm_psr_set_event(struct amdgpu_display_manager *dm, struct dc_stream_state *stream, + bool set_event, enum psr_event event, bool wait_for_disable) { - enum dc_psr_state psr_state = PSR_STATE0; - struct dc_link *link = stream->link; - int retry_count; + unsigned int psr_events; - if (link == NULL) + /* Validate all required parameters */ + if (!stream || !stream->link || + !stream->link->psr_settings.psr_feature_enabled) return false; - for (retry_count = 0; retry_count <= 1000; retry_count++) { - dc_link_get_psr_state(link, &psr_state); - if (psr_state == PSR_STATE0) - break; - udelay(500); - } - - if (retry_count == 1000) + /* Get current psr events */ + if (!mod_power_get_psr_event(dm->power_module, stream, &psr_events)) return false; - return true; + /* If all events already in desired state, return true. */ + if ((psr_events & event) == (set_event ? event : 0)) + return true; + + return mod_power_set_psr_event(dm->power_module, stream, + set_event, event, wait_for_disable); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h index 4fb8626913cf..16d535806ad6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h @@ -28,16 +28,15 @@ #define AMDGPU_DM_AMDGPU_DM_PSR_H_ #include "amdgpu.h" +#include "dc.h" +#include "modules/inc/mod_power.h" /* the number of pageflips before enabling psr */ #define AMDGPU_DM_PSR_ENTRY_DELAY 5 -void amdgpu_dm_set_psr_caps(struct dc_link *link); -void amdgpu_dm_psr_enable(struct dc_stream_state *stream); -bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream); -bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait); -bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm); +bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector); bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm); -bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream); - +bool amdgpu_dm_psr_set_event(struct amdgpu_display_manager *dm, + struct dc_stream_state *stream, bool set_event, enum psr_event event, + bool wait_for_disable); #endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c index 8c150b001105..297125d1db70 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c @@ -27,7 +27,6 @@ #include "amdgpu_dm_replay.h" #include "dc_dmub_srv.h" #include "dc.h" -#include "dm_helpers.h" #include "amdgpu_dm.h" #include "modules/power/power_helpers.h" #include "dmub/inc/dmub_cmd.h" @@ -99,13 +98,29 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector !dc->ctx->dmub_srv->dmub->feature_caps.replay_supported) return false; + /* Mark Replay is supported in link and update related attributes + * This flag presents DPCD caps & amd_vsdb caps satisfy replay requirement. + */ + pr_config.replay_cap_support = true; + // Mark Replay is supported in pr_config pr_config.replay_supported = true; + pr_config.replay_enable_option = pr_enable_option_general_ui | + pr_enable_option_static_screen | + pr_enable_option_static_screen_coasting; + pr_config.replay_power_opt_supported = replay_power_opt_smu_opt_static_screen | + replay_power_opt_z10_static_screen; + pr_config.replay_smu_opt_supported = false; + pr_config.replay_support_fast_resync_in_ultra_sleep_mode = + aconnector->max_vfreq >= 2 * aconnector->min_vfreq; + pr_config.force_disable_desync_error_check = false; + debug_flags = (union replay_debug_flags *)&pr_config.debug_flags; debug_flags->u32All = 0; debug_flags->bitfields.visual_confirm = link->ctx->dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY; + debug_flags->bitfields.skip_crtc_disabled = dc->debug.replay_skip_crtc_disabled; init_replay_config(link, &pr_config); @@ -113,104 +128,80 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector } /* - * amdgpu_dm_link_setup_replay() - configure replay link - * @link: link - * @aconnector: aconnector + * amdgpu_dm_link_setup_replay() - config replay settings + * @stream: pointer to dc_stream_state structure + * @vrr_params: pointer to mod_vrr_params structure containing VRR parameters * + * config replay link settings including coasting vtotal calculations. + * + * Return: true if successful, false if any parameter is invalid or replay not supported */ -bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector) +bool amdgpu_dm_link_setup_replay(struct dc_stream_state *stream, + struct mod_vrr_params *vrr_params) { - struct replay_config *pr_config; + struct dc_link *link; + unsigned int static_coasting_vtotal; + unsigned int nom_coasting_vtotal; - if (link == NULL || aconnector == NULL) + if (!stream || !stream->link || !vrr_params) return false; - pr_config = &link->replay_settings.config; - - if (!pr_config->replay_supported) + link = stream->link; + if (!link->replay_settings.config.replay_supported) return false; - pr_config->replay_power_opt_supported = 0x11; - pr_config->replay_smu_opt_supported = false; - pr_config->replay_enable_option |= pr_enable_option_static_screen; - pr_config->replay_support_fast_resync_in_ultra_sleep_mode = aconnector->max_vfreq >= 2 * aconnector->min_vfreq; - pr_config->replay_timing_sync_supported = false; + if (link->replay_settings.replay_feature_enabled) + return true; - if (!pr_config->replay_timing_sync_supported) - pr_config->replay_enable_option &= ~pr_enable_option_general_ui; + calculate_replay_link_off_frame_count(link, stream->timing.v_total, + stream->timing.h_total); - link->replay_settings.replay_feature_enabled = true; + nom_coasting_vtotal = stream->timing.v_total; + static_coasting_vtotal = mod_freesync_calc_v_total_from_refresh(stream, + vrr_params->min_refresh_in_uhz); + set_replay_coasting_vtotal(link, PR_COASTING_TYPE_NOM, + nom_coasting_vtotal); + set_replay_coasting_vtotal(link, PR_COASTING_TYPE_STATIC, + static_coasting_vtotal); return true; } /* - * amdgpu_dm_replay_enable() - enable replay f/w - * @stream: stream state + * amdgpu_dm_replay_set_event() - set or clear replay event for a stream + * @dm: pointer to amdgpu_display_manager + * @stream: pointer to dc_stream_state + * @set_event: true to set event, false to clear event + * @event: replay event type to set or clear + * @wait_for_disable: whether to wait for replay to be disabled before returning * - * Return: true if success + * This function sets or clears a specific replay event for the given stream. + * It temporarily disables idle optimizations during the operation to ensure + * hardware access is available. + * + * Return: true if successful, false if any parameter is invalid or operation fails */ -bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait) +bool amdgpu_dm_replay_set_event(struct amdgpu_display_manager *dm, + struct dc_stream_state *stream, + bool set_event, + enum replay_event event, + bool wait_for_disable) { - bool replay_active = true; - struct dc_link *link = NULL; - struct amdgpu_dm_connector *aconnector = NULL; + unsigned int replay_events; - if (stream == NULL) + /* Validate all required parameters */ + if (!stream || !stream->link || + !stream->link->replay_settings.replay_feature_enabled) return false; - /* Check if replay is disabled by connector flag */ - aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; - if (!aconnector || aconnector->disallow_edp_enter_replay) { + /* Get current replay events */ + if (!mod_power_get_replay_event(dm->power_module, stream, &replay_events)) return false; - } - link = stream->link; - - if (link) { - link->dc->link_srv->dp_setup_replay(link, stream); - link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total, 0); - DRM_DEBUG_DRIVER("Enabling replay...\n"); - link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL); + /* If all events already in desired state, return true. */ + if ((replay_events & event) == (set_event ? event : 0)) return true; - } - return false; -} - -/* - * amdgpu_dm_replay_disable() - disable replay f/w - * @stream: stream state - * - * Return: true if success - */ -bool amdgpu_dm_replay_disable(struct dc_stream_state *stream) -{ - bool replay_active = false; - struct dc_link *link = NULL; - - if (stream == NULL) - return false; - - link = stream->link; - - if (link) { - DRM_DEBUG_DRIVER("Disabling replay...\n"); - link->dc->link_srv->edp_set_replay_allow_active(stream->link, &replay_active, true, false, NULL); - return true; - } - - return false; -} - -/* - * amdgpu_dm_replay_disable_all() - disable replay f/w - * if replay is enabled on any stream - * - * Return: true if success - */ -bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm) -{ - DRM_DEBUG_DRIVER("Disabling replay if replay is enabled on any stream\n"); - return dc_set_replay_allow_active(dm->dc, false); + return mod_power_set_replay_event(dm->power_module, stream, + set_event, event, wait_for_disable); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h index 73b6c67ae5e7..021bf0255516 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h @@ -28,22 +28,16 @@ #define AMDGPU_DM_AMDGPU_DM_REPLAY_H_ #include "amdgpu.h" +#include "dc.h" +#include "modules/inc/mod_power.h" -enum replay_enable_option { - pr_enable_option_static_screen = 0x1, - pr_enable_option_mpo_video = 0x2, - pr_enable_option_full_screen_video = 0x4, - pr_enable_option_general_ui = 0x8, - pr_enable_option_static_screen_coasting = 0x10000, - pr_enable_option_mpo_video_coasting = 0x20000, - pr_enable_option_full_screen_video_coasting = 0x40000, -}; - -bool amdgpu_dm_link_supports_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector); -bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool enable); -bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector); -bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector); -bool amdgpu_dm_replay_disable(struct dc_stream_state *stream); -bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm); - +bool amdgpu_dm_link_supports_replay(struct dc_link *link, + struct amdgpu_dm_connector *aconnector); +bool amdgpu_dm_set_replay_caps(struct dc_link *link, + struct amdgpu_dm_connector *aconnector); +bool amdgpu_dm_link_setup_replay(struct dc_stream_state *stream, + struct mod_vrr_params *vrr_params); +bool amdgpu_dm_replay_set_event(struct amdgpu_display_manager *dm, + struct dc_stream_state *stream, bool set_event, + enum replay_event event, bool wait_for_disable); #endif /* AMDGPU_DM_AMDGPU_DM_REPLAY_H_ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 8550d5e8b753..84dcb573d98f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -62,3 +62,30 @@ void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx) } /**** power component interfaces ****/ + +bool dm_query_extended_brightness_caps(struct dc_context *ctx, + enum dm_acpi_display_type display, struct dm_acpi_atif_backlight_caps *pCaps) +{ + struct amdgpu_device *adev; + struct amdgpu_display_manager *dm; + int bl_index = (display == AcpiDisplayType_LCD1) ? 0 : 1; + + if (!ctx || !pCaps || !ctx->driver_context) + return false; + + adev = (struct amdgpu_device *)ctx->driver_context; + dm = &adev->dm; + + amdgpu_dm_update_backlight_caps(dm, bl_index); + + pCaps->num_data_points = dm->backlight_caps[bl_index].data_points; + pCaps->max_input_signal = dm->backlight_caps[bl_index].max_input_signal; + pCaps->min_input_signal = dm->backlight_caps[bl_index].min_input_signal; + pCaps->ac_level_percentage = dm->backlight_caps[bl_index].ac_level; + pCaps->dc_level_percentage = dm->backlight_caps[bl_index].dc_level; + + if (pCaps->num_data_points > 0) + memcpy(pCaps->data_points, dm->backlight_caps[bl_index].luminance_data, + sizeof(struct dm_bl_data_point) * pCaps->num_data_points); + return true; +} diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index e0fab8878d19..f33a2c1e0da5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -108,7 +108,7 @@ TRACE_EVENT(amdgpu_dm_connector_atomic_check, TP_STRUCT__entry( __field(uint32_t, conn_id) __field(const struct drm_connector_state *, conn_state) - __field(const struct drm_atomic_state *, state) + __field(const struct drm_atomic_commit *, state) __field(const struct drm_crtc_commit *, commit) __field(uint32_t, crtc_id) __field(uint32_t, best_encoder_id) @@ -163,7 +163,7 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, TP_ARGS(state), TP_STRUCT__entry( - __field(const struct drm_atomic_state *, state) + __field(const struct drm_atomic_commit *, state) __field(const struct drm_crtc_state *, crtc_state) __field(const struct drm_crtc_commit *, commit) __field(uint32_t, crtc_id) @@ -229,7 +229,7 @@ DECLARE_EVENT_CLASS(amdgpu_dm_plane_state_template, __field(uint32_t, plane_id) __field(enum drm_plane_type, plane_type) __field(const struct drm_plane_state *, plane_state) - __field(const struct drm_atomic_state *, state) + __field(const struct drm_atomic_commit *, state) __field(uint32_t, crtc_id) __field(uint32_t, fb_id) __field(uint32_t, fb_format) @@ -315,11 +315,11 @@ DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_atomic_update_cursor, TP_ARGS(state)); TRACE_EVENT(amdgpu_dm_atomic_state_template, - TP_PROTO(const struct drm_atomic_state *state), + TP_PROTO(const struct drm_atomic_commit *state), TP_ARGS(state), TP_STRUCT__entry( - __field(const struct drm_atomic_state *, state) + __field(const struct drm_atomic_commit *, state) __field(bool, allow_modeset) __field(bool, legacy_cursor_update) __field(bool, async_update) @@ -347,23 +347,23 @@ TRACE_EVENT(amdgpu_dm_atomic_state_template, ); DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_begin, - TP_PROTO(const struct drm_atomic_state *state), + TP_PROTO(const struct drm_atomic_commit *state), TP_ARGS(state)); DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_finish, - TP_PROTO(const struct drm_atomic_state *state), + TP_PROTO(const struct drm_atomic_commit *state), TP_ARGS(state)); DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_check_begin, - TP_PROTO(const struct drm_atomic_state *state), + TP_PROTO(const struct drm_atomic_commit *state), TP_ARGS(state)); TRACE_EVENT(amdgpu_dm_atomic_check_finish, - TP_PROTO(const struct drm_atomic_state *state, int res), + TP_PROTO(const struct drm_atomic_commit *state, int res), TP_ARGS(state, res), TP_STRUCT__entry( - __field(const struct drm_atomic_state *, state) + __field(const struct drm_atomic_commit *, state) __field(int, res) __field(bool, async_update) __field(bool, allow_modeset) diff --git a/drivers/gpu/drm/amd/display/dc/basics/conversion.c b/drivers/gpu/drm/amd/display/dc/basics/conversion.c index bd1f60ecaba4..a1f2350388e2 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/conversion.c +++ b/drivers/gpu/drm/amd/display/dc/basics/conversion.c @@ -131,7 +131,7 @@ void convert_hw_matrix(struct fixed31_32 *matrix, uint16_t *reg, uint32_t buffer_size) { - for (int i = 0; i < buffer_size; ++i) + for (uint32_t i = 0; i < buffer_size; ++i) matrix[i] = int_frac_to_fixed_point(reg[i], 2, 13); } diff --git a/drivers/gpu/drm/amd/display/dc/basics/custom_float.c b/drivers/gpu/drm/amd/display/dc/basics/custom_float.c index ae05ded9a7f3..d313584335d3 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/custom_float.c +++ b/drivers/gpu/drm/amd/display/dc/basics/custom_float.c @@ -90,7 +90,7 @@ static bool build_custom_float(struct fixed31_32 value, dc_fixpt_lt(dc_fixpt_one, mantiss)) mantiss = dc_fixpt_zero; else - mantiss = dc_fixpt_shl(mantiss, format->mantissa_bits); + mantiss = dc_fixpt_shl(mantiss, (unsigned char)format->mantissa_bits); *mantissa = dc_fixpt_floor(mantiss); diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c index f37a43f4172e..1b8e843020d6 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c @@ -302,7 +302,7 @@ static void calculate_bandwidth( fbc_enabled = false; lpt_enabled = false; for (i = 4; i <= maximum_number_of_surfaces - 3; i++) { - if (i < data->number_of_displays + 4) { + if (i < (int32_t)(data->number_of_displays + 4)) { if (i == 4 && data->d0_underlay_mode == bw_def_underlay_only) { data->enable[i] = 0; data->use_alpha[i] = 0; @@ -2767,7 +2767,7 @@ static bool is_display_configuration_supported( const struct bw_calcs_vbios *vbios, const struct dce_bw_output *calcs_output) { - uint32_t int_max_clk; + int32_t int_max_clk; int_max_clk = bw_fixed_to_int(vbios->high_voltage_max_dispclk); int_max_clk *= 1000; /* MHz to kHz */ @@ -3077,7 +3077,7 @@ bool bw_calcs(struct dc_context *ctx, } calculate_bandwidth(dceip, vbios, data); - yclk_lvl = data->y_clk_level; + yclk_lvl = (uint8_t)data->y_clk_level; calcs_output->nbp_state_change_enable = data->nbp_state_change_enable; diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index dd362071a6c9..30567ef74e5c 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -794,17 +794,19 @@ static enum bp_result bios_parser_external_encoder_control( static enum bp_result bios_parser_dac_load_detection( struct dc_bios *dcb, - enum engine_id engine_id) + enum engine_id engine_id, + struct graphics_object_id ext_enc_id) { struct bios_parser *bp = BP_FROM_DCB(dcb); struct dc_context *ctx = dcb->ctx; struct bp_load_detection_parameters bp_params = {0}; + struct bp_external_encoder_control ext_cntl = {0}; enum bp_result bp_result = BP_RESULT_UNSUPPORTED; uint32_t bios_0_scratch; uint32_t device_id_mask = 0; - bp_params.device_id = get_support_mask_for_device_id( - DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1); + bp_params.device_id = (uint16_t)get_support_mask_for_device_id( + DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1); if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT) device_id_mask = ATOM_S0_CRT1_MASK; @@ -824,6 +826,13 @@ static enum bp_result bios_parser_dac_load_detection( bp_params.engine_id = engine_id; bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); + } else if (ext_enc_id.id) { + if (!bp->cmd_tbl.external_encoder_control) + return BP_RESULT_UNSUPPORTED; + + ext_cntl.action = EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT; + ext_cntl.encoder_id = ext_enc_id; + bp_result = bp->cmd_tbl.external_encoder_control(bp, &ext_cntl); } if (bp_result != BP_RESULT_OK) @@ -1304,6 +1313,60 @@ static enum bp_result bios_parser_get_embedded_panel_info( return BP_RESULT_FAILURE; } +static enum bp_result get_embedded_panel_extra_info( + struct bios_parser *bp, + struct embedded_panel_info *info, + const uint32_t table_offset) +{ + uint8_t *record = bios_get_image(&bp->base, table_offset, 1); + ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; + ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; + + while (*record != ATOM_RECORD_END_TYPE) { + switch (*record) { + case LCD_MODE_PATCH_RECORD_MODE_TYPE: + record += sizeof(ATOM_PATCH_RECORD_MODE); + break; + case LCD_RTS_RECORD_TYPE: + record += sizeof(ATOM_LCD_RTS_RECORD); + break; + case LCD_CAP_RECORD_TYPE: + record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); + break; + case LCD_FAKE_EDID_PATCH_RECORD_TYPE: + fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; + if (fake_edid_record->ucFakeEDIDLength) { + if (fake_edid_record->ucFakeEDIDLength == 128) + info->fake_edid_size = + fake_edid_record->ucFakeEDIDLength; + else + info->fake_edid_size = + fake_edid_record->ucFakeEDIDLength * 128; + + info->fake_edid = fake_edid_record->ucFakeEDIDString; + + record += struct_size(fake_edid_record, + ucFakeEDIDString, + info->fake_edid_size); + } else { + /* empty fake edid record must be 3 bytes long */ + record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1; + } + break; + case LCD_PANEL_RESOLUTION_RECORD_TYPE: + panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; + info->panel_width_mm = panel_res_record->usHSize; + info->panel_height_mm = panel_res_record->usVSize; + record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); + break; + default: + return BP_RESULT_BADBIOSTABLE; + } + } + + return BP_RESULT_OK; +} + static enum bp_result get_embedded_panel_info_v1_2( struct bios_parser *bp, struct embedded_panel_info *info) @@ -1382,7 +1445,7 @@ static enum bp_result get_embedded_panel_info_v1_2( info->ss_id = lvds->ucSS_Id; { - uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate); + uint16_t rr = le16_to_cpu(lvds->usSupportedRefreshRate); /* Get minimum supported refresh rate*/ if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr) info->supported_rr.REFRESH_RATE_30HZ = 1; @@ -1420,6 +1483,10 @@ static enum bp_result get_embedded_panel_info_v1_2( if (ATOM_PANEL_MISC_API_ENABLED & lvds->ucLVDS_Misc) info->lcd_timing.misc_info.API_ENABLED = true; + if (lvds->usExtInfoTableOffset) + return get_embedded_panel_extra_info(bp, info, + le16_to_cpu(lvds->usExtInfoTableOffset) + DATA_TABLES(LCD_Info)); + return BP_RESULT_OK; } @@ -1545,6 +1612,10 @@ static enum bp_result get_embedded_panel_info_v1_3( (uint32_t) (ATOM_PANEL_MISC_V13_GREY_LEVEL & lvds->ucLCD_Misc) >> ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT; + if (lvds->usExtInfoTableOffset) + return get_embedded_panel_extra_info(bp, info, + le16_to_cpu(lvds->usExtInfoTableOffset) + DATA_TABLES(LCD_Info)); + return BP_RESULT_OK; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index a1c08e1cc411..ee6d52b87b02 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -157,7 +157,7 @@ static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) break; } - return count; + return (uint8_t)count; } static struct graphics_object_id bios_parser_get_connector_id( @@ -401,7 +401,7 @@ static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, return BP_RESULT_BADINPUT; if (id.type == OBJECT_TYPE_GENERIC) { - dummy_record.i2c_id = id.id; + dummy_record.i2c_id = (uint8_t)id.id; if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) return BP_RESULT_OK; @@ -493,6 +493,10 @@ static enum bp_result get_gpio_i2c_info( - sizeof(struct atom_common_table_header)) / sizeof(struct atom_gpio_pin_assignment); + if (!bios_get_image(&bp->base, DATA_TABLES(gpio_pin_lut), + le16_to_cpu(header->table_header.structuresize))) + return BP_RESULT_BADBIOSTABLE; + pin = (struct atom_gpio_pin_assignment *) header->gpio_pin; for (table_index = 0; table_index < count; table_index++) { @@ -681,6 +685,11 @@ static enum bp_result bios_parser_get_gpio_pin_info( count = (le16_to_cpu(header->table_header.structuresize) - sizeof(struct atom_common_table_header)) / sizeof(struct atom_gpio_pin_assignment); + + if (!bios_get_image(&bp->base, DATA_TABLES(gpio_pin_lut), + le16_to_cpu(header->table_header.structuresize))) + return BP_RESULT_BADBIOSTABLE; + for (i = 0; i < count; ++i) { if (header->gpio_pin[i].gpio_id != gpio_id) continue; @@ -1228,7 +1237,7 @@ static enum bp_result get_disp_caps_v4_1( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = disp_cntl_tbl->display_caps; + *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; return result; } @@ -1252,7 +1261,7 @@ static enum bp_result get_disp_caps_v4_2( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = disp_cntl_tbl->display_caps; + *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; return result; } @@ -1276,7 +1285,7 @@ static enum bp_result get_disp_caps_v4_3( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = disp_cntl_tbl->display_caps; + *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; return result; } @@ -1300,7 +1309,7 @@ static enum bp_result get_disp_caps_v4_4( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = disp_cntl_tbl->display_caps; + *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; return result; } @@ -1324,7 +1333,7 @@ static enum bp_result get_disp_caps_v4_5( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = disp_cntl_tbl->display_caps; + *dce_caps = (uint8_t)disp_cntl_tbl->display_caps; return result; } @@ -2585,7 +2594,7 @@ static enum bp_result get_integrated_info_v11( info->ext_disp_conn_info.path[i].channel_mapping.raw = info_v11->extdispconninfo.path[i].channelmapping; info->ext_disp_conn_info.path[i].caps = - le16_to_cpu(info_v11->extdispconninfo.path[i].caps); + (unsigned short)le16_to_cpu(info_v11->extdispconninfo.path[i].caps); } info->ext_disp_conn_info.checksum = info_v11->extdispconninfo.checksum; @@ -2790,7 +2799,7 @@ static enum bp_result get_integrated_info_v2_1( info->ext_disp_conn_info.path[i].channel_mapping.raw = info_v2_1->extdispconninfo.path[i].channelmapping; info->ext_disp_conn_info.path[i].caps = - le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); + (unsigned short)le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); } info->ext_disp_conn_info.checksum = @@ -2954,7 +2963,7 @@ static enum bp_result get_integrated_info_v2_2( info->ext_disp_conn_info.path[i].channel_mapping.raw = info_v2_2->extdispconninfo.path[i].channelmapping; info->ext_disp_conn_info.path[i].caps = - le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); + (unsigned short)le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); } info->ext_disp_conn_info.checksum = @@ -2977,6 +2986,7 @@ static enum bp_result get_integrated_info_v2_2( info->edp1_info.edp_panel_bpc = info_v2_2->edp1_info.edp_panel_bpc; info->edp1_info.edp_bootup_bl_level = + info_v2_2->edp1_info.edp_bootup_bl_level; info->edp2_info.edp_backlight_pwm_hz = le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c index 8d2cf95ae739..e00dc05c2d9d 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c @@ -37,10 +37,13 @@ uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset, uint32_t size) { - if (bp->bios && offset + size < bp->bios_size) - return bp->bios + offset; - else + if (!bp->bios) return NULL; + + if (offset > bp->bios_size || size > bp->bios_size - offset) + return NULL; + + return bp->bios + offset; } #include "reg_helper.h" diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index f6e22dcecf29..0df84394a325 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -1521,8 +1521,8 @@ static enum bp_result adjust_display_pll_v2( if (pixel_clock_10KHz_in != 0) { bp_params->adjusted_pixel_clock = - div_u64(pixel_clk * pixel_clk_10_khz_out, - pixel_clock_10KHz_in); + (uint32_t)div_u64(pixel_clk * pixel_clk_10_khz_out, + pixel_clock_10KHz_in); } else { bp_params->adjusted_pixel_clock = 0; BREAK_TO_DEBUGGER(); @@ -1571,8 +1571,8 @@ static enum bp_result adjust_display_pll_v3( if (pixel_clk_10_kHz_in != 0) { bp_params->adjusted_pixel_clock = - div_u64(pixel_clk * pixel_clk_10_khz_out, - pixel_clk_10_kHz_in); + (uint32_t)div_u64(pixel_clk * pixel_clk_10_khz_out, + pixel_clk_10_kHz_in); } else { bp_params->adjusted_pixel_clock = 0; BREAK_TO_DEBUGGER(); @@ -2662,8 +2662,8 @@ static enum bp_result set_dce_clock_v2_1( !cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type)) return BP_RESULT_BADINPUT; - params.asParam.ucDCEClkSrc = atom_pll_id; - params.asParam.ucDCEClkType = atom_clock_type; + params.asParam.ucDCEClkSrc = (uint8_t)atom_pll_id; + params.asParam.ucDCEClkType = (uint8_t)atom_clock_type; if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) { if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK) diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c index 17ef515c6c69..88625daf5378 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c @@ -929,8 +929,8 @@ static enum bp_result set_dce_clock_v2_1( &atom_clock_type)) return BP_RESULT_BADINPUT; - params.param.dceclksrc = atom_pll_id; - params.param.dceclktype = atom_clock_type; + params.param.dceclksrc = (uint8_t)atom_pll_id; + params.param.dceclktype = (uint8_t)atom_clock_type; if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) { if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 6d41df52d7c9..808e24f0e88f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -88,7 +88,7 @@ static const struct state_dependent_clocks dce80_max_clks_by_state[] = { /* ClocksStatePerformance */ { .display_clk_khz = 625000, .pixel_clk_khz = 400000 } }; -int dentist_get_divider_from_did(int did) +unsigned int dentist_get_divider_from_did(unsigned int did) { if (did < DENTIST_BASE_DID_1) did = DENTIST_BASE_DID_1; @@ -155,8 +155,8 @@ static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - int dprefclk_wdivider; - int dprefclk_src_sel; + uint32_t dprefclk_wdivider; + uint32_t dprefclk_src_sel; int dp_ref_clk_khz; int target_div; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h index f6622f58f62e..9ea1b0a9923d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h @@ -54,6 +54,6 @@ int dce_set_clock( void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr); -int dentist_get_divider_from_did(int did); +unsigned int dentist_get_divider_from_did(unsigned int did); #endif /* _DCE_CLK_MGR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c index cd4c45516616..b35a44976477 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c @@ -63,11 +63,11 @@ static const struct state_dependent_clocks dce110_max_clks_by_state[] = { /*ClocksStatePerformance*/ { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } }; -static int determine_sclk_from_bounding_box( +static uint32_t determine_sclk_from_bounding_box( const struct dc *dc, - int required_sclk) + uint32_t required_sclk) { - int i; + uint32_t i; /* * Some asics do not give us sclk levels, so we just report the actual @@ -127,7 +127,7 @@ void dce110_fill_display_configs( pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; - pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator; + pp_display_cfg->crtc_index = (uint8_t)dc->res_pool->res_cap->num_timing_generator; for (j = 0; j < context->stream_count; j++) { int k; @@ -151,7 +151,7 @@ void dce110_fill_display_configs( num_cfgs++; cfg->signal = pipe_ctx->stream->signal; - cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; + cfg->pipe_idx = (uint8_t)pipe_ctx->stream_res.tg->inst; cfg->src_height = stream->src.height; cfg->src_width = stream->src.width; cfg->ddi_channel_mapping = @@ -189,7 +189,7 @@ void dce110_fill_display_configs( pp_display_cfg->line_time_in_us = 0; } - pp_display_cfg->display_count = num_cfgs; + pp_display_cfg->display_count = (uint8_t)num_cfgs; } void dce11_pplib_apply_display_requirements( diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c index 369421e46c52..06a51f47aed7 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c @@ -88,7 +88,7 @@ static void ramp_up_dispclk_with_dpp( struct dc_clocks *new_clocks, bool safe_to_lower) { - int i; + uint32_t i; int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks); bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index bb4f3bd7532e..cbd989b6a3df 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -104,7 +104,7 @@ uint32_t dentist_get_did_from_divider(int divider) void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower) { - int i; + uint32_t i; clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { @@ -255,9 +255,12 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, pp_smu->set_display_count(&pp_smu->pp_smu, display_count); } - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; @@ -427,8 +430,8 @@ void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base) struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); uint32_t dispclk_wdivider; uint32_t dppclk_wdivider; - int disp_divider; - int dpp_divider; + unsigned int disp_divider; + unsigned int dpp_divider; REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider); @@ -531,8 +534,8 @@ void dcn20_clk_mgr_construct( struct pp_smu_funcs *pp_smu, struct dccg *dccg) { - int dprefclk_did; - int target_div; + unsigned int dprefclk_did; + unsigned int target_div; uint32_t pll_req_reg; struct fixed31_32 pll_req; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index 09e83097a623..b5378344d2bc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -106,7 +106,7 @@ static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dpp_clk, bool safe_to_lower) { - int i; + uint32_t i; clk_mgr->dccg->ref_dppclk = ref_dpp_clk; @@ -462,8 +462,10 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm if (!bw_params->wm_table.entries[i].valid) continue; - ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; - ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; + ranges->reader_wm_sets[num_valid_sets].wm_inst = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + ranges->reader_wm_sets[num_valid_sets].wm_type = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; @@ -474,9 +476,11 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0; else { /* add 1 to make it non-overlapping with next lvl */ - ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } - ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; + ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -640,6 +644,8 @@ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsi static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info) { int i, j = 0; + unsigned int entry_idx; + unsigned int wm_idx; j = -1; @@ -663,28 +669,28 @@ static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params bw_params->clk_table.num_entries = j + 1; - for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { - bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; - bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; - bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; - bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol); - bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table, - bw_params->clk_table.entries[i].voltage); + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++, j--) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = clock_table->FClocks[j].Freq; + bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->MemClocks[j].Freq; + bw_params->clk_table.entries[entry_idx].voltage = clock_table->FClocks[j].Vol; + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol); + bw_params->clk_table.entries[entry_idx].socclk_mhz = find_socclk_for_voltage(clock_table, + bw_params->clk_table.entries[entry_idx].voltage); } bw_params->vram_type = bios_info->memory_type; bw_params->num_channels = bios_info->ma_channel_number; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (wm_idx = 0; wm_idx < (unsigned int)WM_SET_COUNT; wm_idx++) { + bw_params->wm_table.entries[wm_idx].wm_inst = wm_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (wm_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[wm_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[wm_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[wm_idx].valid = true; } if (bw_params->vram_type == LpDdr4MemType) { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c index dcec9d0f8c34..5641f9089b0b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c @@ -78,9 +78,9 @@ static const struct clk_mgr_mask clk_mgr_mask = { /* Query SMU for all clock states for a particular clock */ -static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels) +static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, uint8_t *num_levels) { - unsigned int i; + uint8_t i; char *entry_i = (char *)entry_0; uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); @@ -109,7 +109,7 @@ static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - unsigned int num_levels; + uint8_t num_levels; memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); clk_mgr_base->clks.p_state_change_support = true; @@ -228,13 +228,16 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, if (enter_display_off == safe_to_lower) dcn30_smu_set_num_of_displays(clk_mgr, display_count); - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { @@ -251,8 +254,10 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, // invalidate the current P-State forced min in certain dc_mode_softmax situations if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) { - if ((new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) != - (clk_mgr_base->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)) + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if ((new_clocks->dramclk_khz <= softmax_memclk_khz) != + (clk_mgr_base->clks.dramclk_khz <= softmax_memclk_khz)) update_pstate_unsupported_clk = true; } @@ -263,12 +268,13 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, /* to disable P-State switching, set UCLK min = max */ if (!clk_mgr_base->clks.p_state_change_support) { if (dc->clk_mgr->dc_mode_softmax_enabled && - new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + new_clocks->dramclk_khz <= (int)(dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)) dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - dc->clk_mgr->bw_params->dc_mode_softmax_memclk); + (uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk); else dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[ + clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } } @@ -281,20 +287,20 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ if (clk_mgr_base->clks.p_state_change_support && (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) dpp_clock_lowered = true; clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); update_dppclk = true; } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); update_dispclk = true; } @@ -323,7 +329,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { - unsigned int i; + uint8_t i; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table; @@ -363,13 +369,14 @@ static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_ if (current_mode) { if (clk_mgr_base->clks.p_state_change_support) dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); else dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[ + clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } else { dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); } } @@ -382,7 +389,8 @@ static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) return; dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[ + clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); } static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) @@ -392,7 +400,7 @@ static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memcl if (!clk_mgr->smu_present) return; - dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz); } static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) { @@ -400,14 +408,14 @@ static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memcl if (!clk_mgr->smu_present) return; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz); } /* Get current memclk states, update bounding box */ static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - unsigned int num_levels; + uint8_t num_levels; if (!clk_mgr->smu_present) return; @@ -480,7 +488,7 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { clk_mgr_base->clks.phyclk_khz = max_phyclk_req; - dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz)); + dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz)); } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c index 827bc2431d5d..e36233127b15 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c @@ -123,12 +123,12 @@ bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input) return false; } -bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) +bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version) { smu_print("SMU Get SMU version\n"); if (dcn30_smu_send_msg_with_param(clk_mgr, - DALSMC_MSG_GetSmuVersion, 0, version)) { + DALSMC_MSG_GetSmuVersion, 0, (uint32_t *)version)) { smu_print("SMU version: %d\n", *version); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h index ca9f5296be94..67e93f9cac71 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h @@ -31,7 +31,7 @@ struct clk_mgr_internal; bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input); -bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version); +bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version); bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr); bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr); void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c index 57ba7bc4d16e..e40bbc495fc4 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c @@ -385,7 +385,7 @@ static void vg_init_clocks(struct clk_mgr *clk_mgr) static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -394,8 +394,11 @@ static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct wa if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -406,10 +409,10 @@ static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct wa else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -530,7 +533,7 @@ static struct clk_bw_params vg_bw_params = { static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { uint32_t max = 0; - int i; + uint32_t i; for (i = 0; i < num_clocks; ++i) { if (clocks[i] > max) @@ -562,6 +565,7 @@ static void vg_clk_mgr_helper_populate_bw_params( const struct vg_dpm_clocks *clock_table) { int i, j; + unsigned int entry_idx; struct clk_bw_params *bw_params = clk_mgr->base.bw_params; uint32_t max_dispclk = 0, max_dppclk = 0; @@ -596,16 +600,17 @@ static void vg_clk_mgr_helper_populate_bw_params( bw_params->clk_table.num_entries = j + 1; - for (i = 0; i < bw_params->clk_table.num_entries - 1; i++, j--) { - bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; - bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; - bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; - bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage); + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries - 1; entry_idx++, j--) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = clock_table->DfPstateTable[j].fclk; + bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->DfPstateTable[j].memclk; + bw_params->clk_table.entries[entry_idx].voltage = clock_table->DfPstateTable[j].voltage; + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage); /* Now update clocks we do read */ - bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; - bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; + bw_params->clk_table.entries[entry_idx].dispclk_mhz = max_dispclk; + bw_params->clk_table.entries[entry_idx].dppclk_mhz = max_dppclk; } + i = (int)entry_idx; bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; @@ -616,16 +621,16 @@ static void vg_clk_mgr_helper_populate_bw_params( bw_params->vram_type = bios_info->memory_type; bw_params->num_channels = bios_info->ma_channel_number; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } if (bw_params->vram_type == LpDdr4MemType) { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c index 89fc482947ef..dc7f50095a13 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c @@ -114,7 +114,7 @@ static int dcn31_get_active_display_cnt_wa( static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; - int i; + uint8_t i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -424,7 +424,7 @@ static struct dcn31_watermarks dummy_wms = { 0 }; static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -433,8 +433,10 @@ static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -445,10 +447,10 @@ static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -523,7 +525,7 @@ static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { uint32_t max = 0; - int i; + uint32_t i; for (i = 0; i < num_clocks; ++i) { if (clocks[i] > max) @@ -539,8 +541,8 @@ static unsigned int find_clk_for_voltage( unsigned int voltage) { int i; - int max_voltage = 0; - int clock = 0; + unsigned int max_voltage = 0; + unsigned int clock = 0; for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) { if (clock_table->SocVoltage[i] == voltage) { @@ -561,6 +563,7 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk const DpmClocks_t *clock_table) { int i, j; + unsigned int entry_idx; struct clk_bw_params *bw_params = clk_mgr->base.bw_params; uint32_t max_dispclk = 0, max_dppclk = 0; @@ -595,24 +598,24 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk ASSERT(0); } - for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { - bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; - bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; - bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++, j--) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = clock_table->DfPstateTable[j].FClk; + bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->DfPstateTable[j].MemClk; + bw_params->clk_table.entries[entry_idx].voltage = clock_table->DfPstateTable[j].Voltage; switch (clock_table->DfPstateTable[j].WckRatio) { case WCK_RATIO_1_2: - bw_params->clk_table.entries[i].wck_ratio = 2; + bw_params->clk_table.entries[entry_idx].wck_ratio = 2; break; case WCK_RATIO_1_4: - bw_params->clk_table.entries[i].wck_ratio = 4; + bw_params->clk_table.entries[entry_idx].wck_ratio = 4; break; default: - bw_params->clk_table.entries[i].wck_ratio = 1; + bw_params->clk_table.entries[entry_idx].wck_ratio = 1; } - bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage); - bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage); - bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; - bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage); + bw_params->clk_table.entries[entry_idx].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage); + bw_params->clk_table.entries[entry_idx].dispclk_mhz = max_dispclk; + bw_params->clk_table.entries[entry_idx].dppclk_mhz = max_dppclk; } bw_params->vram_type = bios_info->memory_type; @@ -620,16 +623,16 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; //bw_params->dram_channel_width_bytes = dc->ctx->asic_id.vram_width; bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index b08a70a2f571..5fe59adc862f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -149,7 +149,7 @@ static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state bool safe_to_lower, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; - int i; + uint8_t i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *pipe = safe_to_lower @@ -295,7 +295,7 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { - int requested_dispclk_khz = new_clocks->dispclk_khz; + uint32_t requested_dispclk_khz = new_clocks->dispclk_khz; dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); @@ -495,7 +495,7 @@ static struct dcn314_ss_info_table ss_info_table = { static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -504,8 +504,10 @@ static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struc if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -516,10 +518,10 @@ static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struc else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -614,7 +616,7 @@ static unsigned int convert_wck_ratio(uint8_t wck_ratio) static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { uint32_t max = 0; - int i; + uint32_t i; for (i = 0; i < num_clocks; ++i) { if (clocks[i] > max) @@ -632,6 +634,7 @@ static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *cl struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1]; uint32_t max_pstate = 0, max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0; int i; + unsigned int entry_idx; /* Find highest valid fclk pstate */ for (i = 0; i < clock_table->NumDfPstatesEnabled; i++) { @@ -721,26 +724,26 @@ static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *cl * Set any 0 clocks to max default setting. Not an issue for * power since we aren't doing switching in such case anyway */ - for (i = 0; i < bw_params->clk_table.num_entries; i++) { - if (!bw_params->clk_table.entries[i].fclk_mhz) { - bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; - bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; - bw_params->clk_table.entries[i].voltage = def_max.voltage; + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++) { + if (!bw_params->clk_table.entries[entry_idx].fclk_mhz) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz; + bw_params->clk_table.entries[entry_idx].memclk_mhz = def_max.memclk_mhz; + bw_params->clk_table.entries[entry_idx].voltage = def_max.voltage; } - if (!bw_params->clk_table.entries[i].dcfclk_mhz) - bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; - if (!bw_params->clk_table.entries[i].socclk_mhz) - bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz; - if (!bw_params->clk_table.entries[i].dispclk_mhz) - bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; - if (!bw_params->clk_table.entries[i].dppclk_mhz) - bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_mhz) - bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_d18_mhz) - bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz; - if (!bw_params->clk_table.entries[i].dtbclk_mhz) - bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dcfclk_mhz) + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = def_max.dcfclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].socclk_mhz) + bw_params->clk_table.entries[entry_idx].socclk_mhz = def_max.socclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dispclk_mhz) + bw_params->clk_table.entries[entry_idx].dispclk_mhz = def_max.dispclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dppclk_mhz) + bw_params->clk_table.entries[entry_idx].dppclk_mhz = def_max.dppclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_mhz = def_max.phyclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = def_max.phyclk_d18_mhz; + if (!bw_params->clk_table.entries[entry_idx].dtbclk_mhz) + bw_params->clk_table.entries[entry_idx].dtbclk_mhz = def_max.dtbclk_mhz; } ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); bw_params->vram_type = bios_info->memory_type; @@ -748,16 +751,16 @@ static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *cl bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index 3a651c1a866d..b6f26475ac16 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -100,7 +100,7 @@ static bool should_disable_otg(struct pipe_ctx *pipe) static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; - int i; + uint8_t i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -203,7 +203,7 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { - int requested_dispclk_khz = new_clocks->dispclk_khz; + uint32_t requested_dispclk_khz = new_clocks->dispclk_khz; dcn315_disable_otg_wa(clk_mgr_base, context, true); @@ -384,7 +384,7 @@ static struct dcn315_watermarks dummy_wms = { 0 }; static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -393,8 +393,11 @@ static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struc if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -405,10 +408,10 @@ static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struc else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -486,6 +489,7 @@ static void dcn315_clk_mgr_helper_populate_bw_params( const DpmClocks_315_t *clock_table) { int i; + unsigned int entry_idx; struct clk_bw_params *bw_params = clk_mgr->base.bw_params; uint32_t max_pstate = clock_table->NumDfPstatesEnabled - 1; struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1]; @@ -541,26 +545,26 @@ static void dcn315_clk_mgr_helper_populate_bw_params( /* Set any 0 clocks to max default setting. Not an issue for * power since we aren't doing switching in such case anyway */ - for (i = 0; i < bw_params->clk_table.num_entries; i++) { - if (!bw_params->clk_table.entries[i].fclk_mhz) { - bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; - bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; - bw_params->clk_table.entries[i].voltage = def_max.voltage; + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++) { + if (!bw_params->clk_table.entries[entry_idx].fclk_mhz) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz; + bw_params->clk_table.entries[entry_idx].memclk_mhz = def_max.memclk_mhz; + bw_params->clk_table.entries[entry_idx].voltage = def_max.voltage; } - if (!bw_params->clk_table.entries[i].dcfclk_mhz) - bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; - if (!bw_params->clk_table.entries[i].socclk_mhz) - bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz; - if (!bw_params->clk_table.entries[i].dispclk_mhz) - bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; - if (!bw_params->clk_table.entries[i].dppclk_mhz) - bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_mhz) - bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_d18_mhz) - bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz; - if (!bw_params->clk_table.entries[i].dtbclk_mhz) - bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dcfclk_mhz) + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = def_max.dcfclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].socclk_mhz) + bw_params->clk_table.entries[entry_idx].socclk_mhz = def_max.socclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dispclk_mhz) + bw_params->clk_table.entries[entry_idx].dispclk_mhz = def_max.dispclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dppclk_mhz) + bw_params->clk_table.entries[entry_idx].dppclk_mhz = def_max.dppclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_mhz = def_max.phyclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = def_max.phyclk_d18_mhz; + if (!bw_params->clk_table.entries[entry_idx].dtbclk_mhz) + bw_params->clk_table.entries[entry_idx].dtbclk_mhz = def_max.dtbclk_mhz; } /* Make sure all highest default clocks are included*/ @@ -572,16 +576,16 @@ static void dcn315_clk_mgr_helper_populate_bw_params( bw_params->num_channels = bios_info->ma_channel_number; bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c index e9d492d8c8d4..72a38f7a761c 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c @@ -103,7 +103,7 @@ static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state bool safe_to_lower, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; - int i; + uint8_t i; for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *pipe = safe_to_lower @@ -211,7 +211,7 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { - int requested_dispclk_khz = new_clocks->dispclk_khz; + uint32_t requested_dispclk_khz = new_clocks->dispclk_khz; dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); @@ -350,7 +350,7 @@ static struct dcn316_watermarks dummy_wms = { 0 }; static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -359,8 +359,11 @@ static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struc if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -371,10 +374,10 @@ static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struc else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -449,7 +452,7 @@ static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { uint32_t max = 0; - int i; + uint32_t i; for (i = 0; i < num_clocks; ++i) { if (clocks[i] > max) @@ -465,8 +468,8 @@ static unsigned int find_clk_for_voltage( unsigned int voltage) { int i; - int max_voltage = 0; - int clock = 0; + unsigned int max_voltage = 0; + unsigned int clock = 0; for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) { if (clock_table->SocVoltage[i] == voltage) { @@ -488,6 +491,7 @@ static void dcn316_clk_mgr_helper_populate_bw_params( const DpmClocks_316_t *clock_table) { int i, j; + unsigned int entry_idx; struct clk_bw_params *bw_params = clk_mgr->base.bw_params; uint32_t max_dispclk = 0, max_dppclk = 0; @@ -522,46 +526,46 @@ static void dcn316_clk_mgr_helper_populate_bw_params( ASSERT(0); } - for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++, j--) { int temp; - bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; - bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; - bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; + bw_params->clk_table.entries[entry_idx].fclk_mhz = clock_table->DfPstateTable[j].FClk; + bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->DfPstateTable[j].MemClk; + bw_params->clk_table.entries[entry_idx].voltage = clock_table->DfPstateTable[j].Voltage; switch (clock_table->DfPstateTable[j].WckRatio) { case WCK_RATIO_1_2: - bw_params->clk_table.entries[i].wck_ratio = 2; + bw_params->clk_table.entries[entry_idx].wck_ratio = 2; break; case WCK_RATIO_1_4: - bw_params->clk_table.entries[i].wck_ratio = 4; + bw_params->clk_table.entries[entry_idx].wck_ratio = 4; break; default: - bw_params->clk_table.entries[i].wck_ratio = 1; + bw_params->clk_table.entries[entry_idx].wck_ratio = 1; } temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage); if (temp) - bw_params->clk_table.entries[i].dcfclk_mhz = temp; + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = temp; temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage); if (temp) - bw_params->clk_table.entries[i].socclk_mhz = temp; - bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; - bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; + bw_params->clk_table.entries[entry_idx].socclk_mhz = temp; + bw_params->clk_table.entries[entry_idx].dispclk_mhz = max_dispclk; + bw_params->clk_table.entries[entry_idx].dppclk_mhz = max_dppclk; } bw_params->vram_type = bios_info->memory_type; bw_params->num_channels = bios_info->ma_channel_number; bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index fda6cade30a8..90fdbf279868 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -132,7 +132,7 @@ static const struct clk_mgr_mask clk_mgr_mask_dcn321 = { static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels) { - unsigned int i; + uint8_t i; char *entry_i = (char *)entry_0; uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); @@ -236,9 +236,9 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) { for (i = 0; i < num_levels; i++) if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz - < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) + < (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz - = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); + = (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); } for (i = 0; i < num_levels; i++) if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950) @@ -247,9 +247,9 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) { for (i = 0; i < num_levels; i++) if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz - < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) + < (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz - = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); + = (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); } for (i = 0; i < num_levels; i++) @@ -269,7 +269,7 @@ static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, { struct dccg *dccg = clk_mgr->dccg; uint32_t tg_mask = 0; - int i; + uint32_t i; for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -314,7 +314,7 @@ static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, s void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower) { - int i; + uint32_t i; clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { @@ -409,7 +409,7 @@ static void dcn32_update_clocks_update_dentist( * floored in Mhz to describe the intended clock. */ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, - khz_to_mhz_floor(temp_dispclk_khz)); + (uint16_t)khz_to_mhz_floor(temp_dispclk_khz)); if (dc->debug.override_dispclk_programming) { REG_GET(DENTIST_DISPCLK_CNTL, @@ -456,7 +456,7 @@ static void dcn32_update_clocks_update_dentist( * floored in Mhz to describe the intended clock. */ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, - khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz)); + (uint16_t)khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz)); if (dc->debug.override_dispclk_programming) { REG_GET(DENTIST_DISPCLK_CNTL, @@ -475,7 +475,7 @@ static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); uint32_t dispclk_wdivider; - int disp_divider; + unsigned int disp_divider; REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); disp_divider = dentist_get_divider_from_did(dispclk_wdivider); @@ -673,14 +673,17 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, } } - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->work_arounds.clock_update_disable_mask.dcfclk) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && @@ -715,13 +718,13 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, * frequency. */ if (dc->debug.disable_dc_mode_overwrite) { - dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz); } else dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - dc->clk_mgr->bw_params->dc_mode_softmax_memclk); + (uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk); } else { - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz); } } } @@ -755,9 +758,10 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, !dc->work_arounds.clock_update_disable_mask.uclk) { if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite) dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, - max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz))); + (uint16_t)max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, + khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz))); - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); } if (clk_mgr_base->clks.num_ways != new_clocks->num_ways && @@ -783,7 +787,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, * floored in Mhz to describe the intended clock. */ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, - khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz)); + (uint16_t)khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz)); update_dppclk = true; } @@ -803,7 +807,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) { /* DCCG requires KHz precision for DTBCLK */ clk_mgr_base->clks.ref_dtbclk_khz = - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz); } @@ -822,7 +826,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, * floored in Mhz to describe the intended clock. */ dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, - khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz)); + (uint16_t)khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz)); } else { /* if clock is being raised, increase refclk before lowering DTO */ if (update_dppclk || update_dispclk) @@ -968,7 +972,7 @@ static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr) } static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { - unsigned int i; + uint8_t i; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table; @@ -1002,13 +1006,13 @@ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current if (current_mode) { if (clk_mgr_base->clks.p_state_change_support) dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); + (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); else dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->max_memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->max_memclk_mhz); } else { dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); } } @@ -1020,7 +1024,7 @@ static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) if (!clk_mgr->smu_present) return; - dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz); + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)clk_mgr_base->bw_params->max_memclk_mhz); } /* Get current memclk states, update bounding box */ @@ -1052,7 +1056,7 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) clk_mgr_base->bw_params->max_memclk_mhz = clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz; - clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; + clk_mgr_base->bw_params->clk_table.num_entries = (uint8_t)(num_levels ? num_levels : 1); if (clk_mgr->dpm_present && !num_levels) clk_mgr->dpm_present = false; @@ -1109,7 +1113,7 @@ static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memc if (!clk_mgr->smu_present) return; - dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); + dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz); } static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) @@ -1119,7 +1123,7 @@ static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memc if (!clk_mgr->smu_present) return; - dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); + dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz); } static struct clk_mgr_funcs dcn32_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 2798088842f4..6c6848e375e1 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -190,7 +190,7 @@ void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context bool safe_to_lower, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; - int i; + uint8_t i; if (dc->ctx->dce_environment == DCE_ENV_DIAG) return; @@ -257,7 +257,7 @@ static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, { struct dccg *dccg = clk_mgr->dccg; uint32_t tg_mask = 0; - int i; + uint32_t i; for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -280,7 +280,7 @@ static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower) { - int i; + uint32_t i; bool dppclk_active[MAX_PIPES] = {0}; @@ -332,7 +332,7 @@ static uint8_t get_lowest_dpia_index(const struct dc_link *link) continue; if (idx > dc_struct->links[i]->link_index) - idx = dc_struct->links[i]->link_index; + idx = (uint8_t)dc_struct->links[i]->link_index; } return idx; @@ -450,9 +450,12 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; } } - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; @@ -478,7 +481,7 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { - int requested_dispclk_khz = new_clocks->dispclk_khz; + uint32_t requested_dispclk_khz = new_clocks->dispclk_khz; dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); @@ -863,7 +866,7 @@ static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr) static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -872,8 +875,10 @@ static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -884,10 +889,10 @@ static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -978,7 +983,7 @@ static void dcn351_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { uint32_t max = 0; - int i; + uint32_t i; for (i = 0; i < num_clocks; ++i) { if (clocks[i] > max) @@ -1025,28 +1030,29 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0; uint32_t num_memps, num_fclk, num_dcfclk; int i; + unsigned int entry_idx; /* Determine min/max p-state values. */ num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS : clock_table->NumMemPstatesEnabled; - for (i = 0; i < num_memps; i++) { - uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]); + for (entry_idx = 0; entry_idx < num_memps; entry_idx++) { + uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[entry_idx]); if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) { max_dram_speed_mts = dram_speed_mts; - max_pstate = i; + max_pstate = entry_idx; } } min_dram_speed_mts = max_dram_speed_mts; min_pstate = max_pstate; - for (i = 0; i < num_memps; i++) { - uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]); + for (entry_idx = 0; entry_idx < num_memps; entry_idx++) { + uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[entry_idx]); if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) { min_dram_speed_mts = dram_speed_mts; - min_pstate = i; + min_pstate = entry_idx; } } @@ -1076,31 +1082,32 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk num_dcfclk = (clock_table->NumDcfClkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS : clock_table->NumDcfClkLevelsEnabled; - for (i = 0; i < num_dcfclk; i++) { + for (entry_idx = 0; entry_idx < num_dcfclk; entry_idx++) { int j; /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */ for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) - if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) + if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[entry_idx]) break; - bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; - bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; - bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; + bw_params->clk_table.entries[entry_idx].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; + bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; + bw_params->clk_table.entries[entry_idx].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; /* Now update clocks we do read */ - bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk; - bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage; - bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; - bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i]; - bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; - bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; - bw_params->clk_table.entries[i].wck_ratio = + bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk; + bw_params->clk_table.entries[entry_idx].voltage = clock_table->MemPstateTable[min_pstate].Voltage; + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = clock_table->DcfClocks[entry_idx]; + bw_params->clk_table.entries[entry_idx].socclk_mhz = clock_table->SocClocks[entry_idx]; + bw_params->clk_table.entries[entry_idx].dispclk_mhz = max_dispclk; + bw_params->clk_table.entries[entry_idx].dppclk_mhz = max_dppclk; + bw_params->clk_table.entries[entry_idx].wck_ratio = convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio); /* Dcfclk and Fclk are tied, but at a different ratio */ - bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]); + bw_params->clk_table.entries[entry_idx].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[entry_idx]); } + i = (int)entry_idx; /* Make sure to include at least one entry at highest pstate */ if (max_pstate != min_pstate || i == 0) { @@ -1146,44 +1153,44 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk * Set any 0 clocks to max default setting. Not an issue for * power since we aren't doing switching in such case anyway */ - for (i = 0; i < bw_params->clk_table.num_entries; i++) { - if (!bw_params->clk_table.entries[i].fclk_mhz) { - bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; - bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; - bw_params->clk_table.entries[i].voltage = def_max.voltage; + for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++) { + if (!bw_params->clk_table.entries[entry_idx].fclk_mhz) { + bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz; + bw_params->clk_table.entries[entry_idx].memclk_mhz = def_max.memclk_mhz; + bw_params->clk_table.entries[entry_idx].voltage = def_max.voltage; } - if (!bw_params->clk_table.entries[i].dcfclk_mhz) - bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; - if (!bw_params->clk_table.entries[i].socclk_mhz) - bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz; - if (!bw_params->clk_table.entries[i].dispclk_mhz) - bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; - if (!bw_params->clk_table.entries[i].dppclk_mhz) - bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; - if (!bw_params->clk_table.entries[i].fclk_mhz) - bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_mhz) - bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; - if (!bw_params->clk_table.entries[i].phyclk_d18_mhz) - bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz; - if (!bw_params->clk_table.entries[i].dtbclk_mhz) - bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dcfclk_mhz) + bw_params->clk_table.entries[entry_idx].dcfclk_mhz = def_max.dcfclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].socclk_mhz) + bw_params->clk_table.entries[entry_idx].socclk_mhz = def_max.socclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dispclk_mhz) + bw_params->clk_table.entries[entry_idx].dispclk_mhz = def_max.dispclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].dppclk_mhz) + bw_params->clk_table.entries[entry_idx].dppclk_mhz = def_max.dppclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].fclk_mhz) + bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_mhz = def_max.phyclk_mhz; + if (!bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz) + bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = def_max.phyclk_d18_mhz; + if (!bw_params->clk_table.entries[entry_idx].dtbclk_mhz) + bw_params->clk_table.entries[entry_idx].dtbclk_mhz = def_max.dtbclk_mhz; } ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); bw_params->vram_type = bios_info->memory_type; bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4; - for (i = 0; i < WM_SET_COUNT; i++) { - bw_params->wm_table.entries[i].wm_inst = i; + for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) { + bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx; - if (i >= bw_params->clk_table.num_entries) { - bw_params->wm_table.entries[i].valid = false; + if (entry_idx >= bw_params->clk_table.num_entries) { + bw_params->wm_table.entries[entry_idx].valid = false; continue; } - bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; - bw_params->wm_table.entries[i].valid = true; + bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG; + bw_params->wm_table.entries[entry_idx].valid = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 82c1a55a2271..5bf6f2d50705 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -174,7 +174,7 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c /* if the initial message failed, num_levels will be 0 */ for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { - *((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); + *((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, (uint8_t)i) & 0xFFFF); entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); } } @@ -182,15 +182,15 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr) { /* For min clocks use as reported by PM FW and report those as min */ - uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; - uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; + unsigned int min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; + unsigned int min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; /* Set A - Normal - default values */ clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true; clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; - clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; + clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz; clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; - clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; + clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz; clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; /* Set B - Unused on dcn4 */ @@ -201,9 +201,9 @@ static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr) if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true; clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; - clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; + clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz; clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF; - clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz; + clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz; clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF; } else { clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false; @@ -291,17 +291,17 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base) if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) { for (i = 0; i < num_entries_per_clk->num_dispclk_levels; i++) if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz - < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) + < (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz - = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); + = (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); } if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) { for (i = 0; i < num_entries_per_clk->num_dppclk_levels; i++) if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz - < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) + < (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz - = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); + = (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); } /* Get UCLK, update bounding box */ @@ -558,7 +558,7 @@ static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz) { - int i; + uint32_t i; clk_mgr->dccg->ref_dppclk = ref_dppclk_khz; for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { @@ -604,10 +604,10 @@ static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mg * clock returned is less than requested, then we will ceil the * requested value to mhz and call it again. */ - int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz)); + int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_floor(requested_clk_khz)); if (actual_clk_khz < requested_clk_khz) - actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz)); + actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_ceil(requested_clk_khz)); return actual_clk_khz; } @@ -841,15 +841,18 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( } /* UPDATE DCFCLK */ - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) { block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK; - block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz); + block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz); block_sequence[num_steps].params.update_hardmin_params.response = NULL; block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK; num_steps++; @@ -860,7 +863,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) { - block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz); + block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz); block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK; num_steps++; } @@ -984,24 +987,24 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( /* When idle DPM is enabled, need to send active and idle hardmins separately */ /* CLK_MGR401_UPDATE_ACTIVE_HARDMINS */ if ((update_active_uclk || update_active_fclk) && is_idle_dpm_enabled) { - block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz; - block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)active_uclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)active_fclk_mhz; block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS; num_steps++; } /* CLK_MGR401_UPDATE_IDLE_HARDMINS */ if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) { - block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz; - block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)idle_uclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)idle_fclk_mhz; block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS; num_steps++; } /* CLK_MGR401_UPDATE_SUBVP_HARDMINS */ if ((update_subvp_prefetch_dramclk || update_subvp_prefetch_fclk) && is_df_throttle_opt_enabled) { - block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = subvp_prefetch_dramclk_mhz; - block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = subvp_prefetch_fclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)subvp_prefetch_dramclk_mhz; + block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)subvp_prefetch_fclk_mhz; block_sequence[num_steps].func = CLK_MGR401_UPDATE_SUBVP_HARDMINS; num_steps++; } @@ -1010,7 +1013,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence( if (update_active_uclk || update_idle_uclk) { if (!is_idle_dpm_enabled) { block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK; - block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz; + block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)active_uclk_mhz; block_sequence[num_steps].params.update_hardmin_params.response = NULL; block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK; num_steps++; @@ -1123,7 +1126,7 @@ static unsigned int dcn401_build_update_display_clocks_sequence( dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) { /* DCCG requires KHz precision for DTBCLK */ block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK; - block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz); + block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz); block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz; block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK; num_steps++; @@ -1318,7 +1321,7 @@ static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base) /* collect valid ranges, place in pmfw table */ for (i = 0; i < WM_SET_COUNT; i++) if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { - table->Watermarks.WatermarkRow[i].WmSetting = i; + table->Watermarks.WatermarkRow[i].WmSetting = (uint8_t)i; table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type; } dcn401_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); @@ -1487,7 +1490,7 @@ static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); uint32_t dispclk_wdivider; - int disp_divider; + unsigned int disp_divider; REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); disp_divider = dentist_get_divider_from_did(dispclk_wdivider); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h index 97a1ce1e8a9e..370d2ddd6064 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h @@ -17,14 +17,14 @@ union dcn401_clk_mgr_block_sequence_params { uint32_t ppclk; uint16_t freq_mhz; /* outputs */ - uint32_t *response; + int *response; } update_hardmin_params; struct { /* inputs */ uint32_t ppclk; int freq_khz; /* outputs */ - uint32_t *response; + int *response; } update_hardmin_optimized_params; struct { /* inputs */ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c index 3a263840893e..82ccd9b407f4 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c @@ -143,12 +143,12 @@ static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mg return false; } -bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) +bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version) { smu_print("SMU Get SMU version\n"); if (dcn401_smu_send_msg_with_param(clk_mgr, - DALSMC_MSG_GetSmuVersion, 0, version)) { + DALSMC_MSG_GetSmuVersion, 0, (uint32_t *)version)) { smu_print("SMU version: %d\n", *version); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h index 4f5ac603e822..1addbed1cb99 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h @@ -10,7 +10,7 @@ struct clk_mgr_internal; -bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version); +bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version); bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr); bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr); void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 6a97ce69a562..d01e5969a670 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -167,7 +167,7 @@ void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower) { - int i; + uint32_t i; bool dppclk_active[MAX_PIPES] = {0}; @@ -282,9 +282,12 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; } } - if (dc->debug.force_min_dcfclk_mhz > 0) - new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? - new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + if (dc->debug.force_min_dcfclk_mhz > 0) { + int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000; + + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ? + new_clocks->dcfclk_khz : force_min_dcfclk_khz; + } if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; @@ -298,13 +301,16 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; /* Clamp the requested clock to PMFW based on DCN limit. */ - if (dc->debug.min_deep_sleep_dcfclk_khz > 0 && clk_mgr_base->clks.dcfclk_deep_sleep_khz < dc->debug.min_deep_sleep_dcfclk_khz) - clk_mgr_base->clks.dcfclk_deep_sleep_khz = dc->debug.min_deep_sleep_dcfclk_khz; + if (dc->debug.min_deep_sleep_dcfclk_khz > 0 && + clk_mgr_base->clks.dcfclk_deep_sleep_khz < (int)dc->debug.min_deep_sleep_dcfclk_khz) + clk_mgr_base->clks.dcfclk_deep_sleep_khz = (int)dc->debug.min_deep_sleep_dcfclk_khz; dcn42_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); } // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. + if (new_clocks->dppclk_khz < 100000) + new_clocks->dppclk_khz = 100000; if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) @@ -315,13 +321,13 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && has_active_display == false))) { - int requested_dispclk_khz = new_clocks->dispclk_khz; + uint32_t requested_dispclk_khz = new_clocks->dispclk_khz; dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); /* Clamp the requested clock to PMFW based on their limit. */ - if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz) - requested_dispclk_khz = dc->debug.min_disp_clk_khz; + if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < (uint32_t)dc->debug.min_disp_clk_khz) + requested_dispclk_khz = (uint32_t)dc->debug.min_disp_clk_khz; dcn42_smu_set_dispclk(clk_mgr, requested_dispclk_khz); clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; @@ -634,7 +640,7 @@ static void dcn42_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr) void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table) { - int i, num_valid_sets; + uint8_t i, num_valid_sets; num_valid_sets = 0; @@ -643,8 +649,10 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_ if (!bw_params->wm_table.entries[i].valid) continue; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; - table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = + (uint8_t)bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = + (uint8_t)bw_params->wm_table.entries[i].wm_type; /* We will not select WM based on fclk, so leave it as unconstrained */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; @@ -655,10 +663,10 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_ else { /* add 1 to make it non-overlapping with next lvl */ table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = - bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1); } table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = - bw_params->clk_table.entries[i].dcfclk_mhz; + (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ @@ -690,7 +698,7 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_ void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { - int i = 0; + unsigned int i = 0; struct dcn42_watermarks *table = NULL; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct clk_mgr_dcn42 *clk_mgr_dcn42 = TO_CLK_MGR_DCN42(clk_mgr); @@ -734,9 +742,12 @@ void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base) clk_mgr_dcn42->smu_wm_set.mc_address.low_part); dcn42_smu_transfer_wm_table_dram_2_smu(clk_mgr); - if (clk_mgr_dcn42->smu_wm_set.wm_set && clk_mgr_dcn42->smu_wm_set.mc_address.quad_part != 0) + if (clk_mgr_dcn42->smu_wm_set.wm_set && clk_mgr_dcn42->smu_wm_set.mc_address.quad_part != 0) { dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART, clk_mgr_dcn42->smu_wm_set.wm_set); + clk_mgr_dcn42->smu_wm_set.wm_set = NULL; + clk_mgr_dcn42->smu_wm_set.mc_address.quad_part = 0; + } } @@ -870,7 +881,7 @@ int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) (void)clk_mgr_base; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); uint32_t dispclk_wdivider; - int disp_divider; + unsigned int disp_divider; REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); disp_divider = dentist_get_divider_from_did(dispclk_wdivider); @@ -1015,7 +1026,7 @@ static struct clk_mgr_funcs dcn42_funcs = { .init_clocks = dcn42_init_clocks, .enable_pme_wa = dcn42_enable_pme_wa, .are_clock_states_equal = dcn42_are_clock_states_equal, - .notify_wm_ranges = dcn42_notify_wm_ranges, + .notify_wm_ranges = NULL, .set_low_power_state = dcn42_set_low_power_state, .exit_low_power_state = dcn42_exit_low_power_state, .get_max_clock_khz = dcn42_get_max_clock_khz, @@ -1069,10 +1080,11 @@ void dcn42_clk_mgr_construct( dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type; dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4; - dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1; - clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); - clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); - + dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 2; + if (clk_mgr->base.smu_present) { + clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); + clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); + } clk_mgr->base.base.bw_params = &dcn42_bw_params; if (clk_mgr->base.smu_present) @@ -1099,7 +1111,10 @@ void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) { struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int); - if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) + if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) { dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_GART, clk_mgr->smu_wm_set.wm_set); + clk_mgr->smu_wm_set.wm_set = NULL; + clk_mgr->smu_wm_set.mc_address.quad_part = 0; + } } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c index c791bb1edb47..6d0012b7d6dc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c @@ -428,4 +428,3 @@ void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) enable); smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0); } - diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 419f894c87b0..6d520d5b02e9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -32,6 +32,7 @@ #include "core_types.h" #include "hw_sequencer.h" #include "dce/dce_hwseq.h" +#include "hw/dccg.h" #include "resource.h" #include "dc_state.h" @@ -61,6 +62,7 @@ #include "link_enc_cfg.h" #include "link_service.h" +#include "link/protocols/link_dp_capability.h" #include "dm_helpers.h" #include "mem_input.h" @@ -172,7 +174,7 @@ static void destroy_links(struct dc *dc) static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links) { - int i; + uint32_t i; uint32_t count = 0; for (i = 0; i < num_links; i++) { @@ -200,7 +202,7 @@ static bool create_links( struct dc *dc, uint32_t num_virtual_links) { - int i; + uint32_t i; int connectors_num; struct dc_bios *bios = dc->ctx->dc_bios; @@ -235,7 +237,7 @@ static bool create_links( * variants of the same card. */ for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) { - struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i); + struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, (uint8_t)i); struct link_init_data link_init_params = {0}; struct dc_link *link; @@ -246,7 +248,7 @@ static bool create_links( link_init_params.ctx = dc->ctx; /* next BIOS object table connector */ - link_init_params.connector_index = i; + link_init_params.connector_index = (uint8_t)i; link_init_params.link_index = dc->link_count; link_init_params.dc = dc; link = dc->link_srv->create_link(&link_init_params); @@ -267,7 +269,7 @@ static bool create_links( struct dc_link *link; link_init_params.ctx = dc->ctx; - link_init_params.connector_index = i; + link_init_params.connector_index = (uint8_t)i; link_init_params.link_index = dc->link_count; link_init_params.dc = dc; link_init_params.is_dpia_link = true; @@ -341,7 +343,7 @@ static bool create_link_encoders(struct dc *dc) bool res = true; unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; - int i; + unsigned int i; /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG * link encoders and physical display endpoints and does not require @@ -381,7 +383,7 @@ static void destroy_link_encoders(struct dc *dc) { unsigned int num_usb4_dpia; unsigned int num_dig_link_enc; - int i; + unsigned int i; if (!dc->res_pool) return; @@ -659,12 +661,12 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, /* By default, capture the full frame */ param.windowa_x_start = 0; param.windowa_y_start = 0; - param.windowa_x_end = pipe->stream->timing.h_addressable; - param.windowa_y_end = pipe->stream->timing.v_addressable; + param.windowa_x_end = (uint16_t)pipe->stream->timing.h_addressable; + param.windowa_y_end = (uint16_t)pipe->stream->timing.v_addressable; param.windowb_x_start = 0; param.windowb_y_start = 0; - param.windowb_x_end = pipe->stream->timing.h_addressable; - param.windowb_y_end = pipe->stream->timing.v_addressable; + param.windowb_x_end = (uint16_t)pipe->stream->timing.h_addressable; + param.windowb_y_end = (uint16_t)pipe->stream->timing.v_addressable; param.crc_poly_mode = crc_poly_mode; if (crc_window) { @@ -1136,7 +1138,7 @@ static void disable_all_writeback_pipes_for_stream( { (void)dc; (void)context; - int i; + unsigned int i; for (i = 0; i < stream->num_wb_info; i++) stream->writeback_info[i].wb_enabled = false; @@ -1149,7 +1151,7 @@ static void apply_ctx_interdependent_lock(struct dc *dc, { (void)dc; (void)context; - int i; + unsigned int i; /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */ if (dc->hwss.interdependent_update_lock) @@ -1336,7 +1338,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, static void disable_dangling_plane(struct dc *dc, struct dc_state *context) { - int i, j; + unsigned int i, j; struct dc_state *dangling_context = dc_state_create_current_copy(dc); struct dc_state *current_ctx; struct pipe_ctx *pipe; @@ -1799,7 +1801,8 @@ bool dc_validate_boot_timing(const struct dc *dc, struct dc_crtc_timing hw_crtc_timing = {0}; struct dc_link *link = sink->link; - unsigned int i, enc_inst, tg_inst = 0; + unsigned int i, enc_inst; + unsigned int tg_inst = 0; /* Support seamless boot on EDP displays only */ if (sink->sink_signal != SIGNAL_TYPE_EDP) { @@ -1928,7 +1931,7 @@ bool dc_validate_boot_timing(const struct dc *dc, struct dcn_dsc_state dsc_state = {0}; /* Find DSC associated with this timing generator */ - if (tg_inst < dc->res_pool->res_cap->num_dsc) { + if (tg_inst < (unsigned int)dc->res_pool->res_cap->num_dsc) { dsc = dc->res_pool->dscs[tg_inst]; } @@ -2129,7 +2132,7 @@ void dc_trigger_sync(struct dc *dc, struct dc_state *context) static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; unsigned int stream_mask = 0; for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -2137,7 +2140,7 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context) stream_mask |= 1 << i; } - return stream_mask; + return (uint8_t)stream_mask; } void dc_z10_restore(const struct dc *dc) @@ -2203,7 +2206,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; - int i, k, l; + unsigned int i, k, l; struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; struct dc_state *old_state; bool subvp_prev_use = false; @@ -2443,7 +2446,7 @@ static bool commit_minimal_transition_state(struct dc *dc, */ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params) { - int i, j; + unsigned int i, j; struct dc_state *context; enum dc_status res = DC_OK; struct dc_validation_set set[MAX_STREAMS] = {0}; @@ -2482,8 +2485,8 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params set[i].stream = stream; if (status) { - set[i].plane_count = status->plane_count; - for (j = 0; j < status->plane_count; j++) + set[i].plane_count = (uint8_t)status->plane_count; + for (j = 0; j < (unsigned int)status->plane_count; j++) set[i].plane_states[j] = status->plane_states[j]; } } @@ -2541,7 +2544,7 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params for (i = 0; i < params->stream_count; i++) { for (j = 0; j < context->stream_count; j++) { if (params->streams[i]->stream_id == context->streams[j]->stream_id) - params->streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst; + params->streams[i]->out.otg_offset = (uint8_t)context->stream_status[j].primary_otg_inst; if (dc_is_embedded_signal(params->streams[i]->signal)) { struct dc_stream_status *status = dc_state_get_stream_status(context, params->streams[i]); @@ -2573,7 +2576,7 @@ bool dc_acquire_release_mpc_3dlut( struct dc_3dlut **lut, struct dc_transfer_func **shaper) { - int pipe_idx; + unsigned int pipe_idx; bool ret = false; bool found_pipe_idx = false; const struct resource_pool *pool = dc->res_pool; @@ -2645,7 +2648,7 @@ static void process_deferred_updates(struct dc *dc) void dc_post_update_surfaces_to_stream(struct dc *dc) { - int i; + unsigned int i; struct dc_state *context = dc->current_state; if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0) @@ -2669,7 +2672,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) for (i = 0; i < dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == NULL || context->res_ctx.pipe_ctx[i].plane_state == NULL) { - context->res_ctx.pipe_ctx[i].pipe_idx = i; + context->res_ctx.pipe_ctx[i].pipe_idx = (uint8_t)i; dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]); } @@ -2885,7 +2888,7 @@ static struct surface_update_descriptor get_scaling_info_update_type( /* Making dst rect smaller requires a bandwidth change */ update_flags->bits.bandwidth_change = 1; - if (u->scaling_info->src_rect.width > check_config->max_optimizable_video_width && + if (u->scaling_info->src_rect.width > (int)check_config->max_optimizable_video_width && (u->scaling_info->clip_rect.width > u->surface->clip_rect.width || u->scaling_info->clip_rect.height > u->surface->clip_rect.height)) /* Changing clip size of a large surface may result in MPC slice count change */ @@ -2946,6 +2949,11 @@ static struct surface_update_descriptor det_surface_update( elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } + if (u->cursor_csc_color_matrix) { + update_flags->bits.cursor_csc_color_matrix_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + if (u->coeff_reduction_factor) { update_flags->bits.coeff_reduction_change = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); @@ -2956,27 +2964,16 @@ static struct surface_update_descriptor det_surface_update( elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (u->cm || (u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) { + if (u->blend_tf || (u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) { update_flags->bits.gamma_change = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (u->cm && (u->cm->flags.bits.lut3d_enable || u->surface->cm.flags.bits.lut3d_enable)) { + if (u->lut3d_func || u->func_shaper) { update_flags->bits.lut_3d = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (u->cm && u->cm->flags.bits.lut3d_dma_enable != u->surface->cm.flags.bits.lut3d_dma_enable && - u->cm->flags.bits.lut3d_enable && u->surface->cm.flags.bits.lut3d_enable) { - /* Toggling 3DLUT loading between DMA and Host is illegal */ - BREAK_TO_DEBUGGER(); - } - - if (u->cm && u->cm->flags.bits.lut3d_enable && !u->cm->flags.bits.lut3d_dma_enable) { - /* Host loading 3DLUT requires full update but only stream lock */ - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM); - } - if (u->hdr_mult.value) if (u->hdr_mult.value != u->surface->hdr_mult.value) { // TODO: Should be fast? @@ -2995,6 +2992,20 @@ static struct surface_update_descriptor det_surface_update( update_flags->bits.cm_hist_change = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } + if (u->cm2_params) { + if (u->cm2_params->component_settings.shaper_3dlut_setting != u->surface->mcm_shaper_3dlut_setting + || u->cm2_params->component_settings.lut1d_enable != u->surface->mcm_lut1d_enable + || u->cm2_params->cm2_luts.lut3d_data.lut3d_src != u->surface->mcm_luts.lut3d_data.lut3d_src) { + update_flags->bits.mcm_transfer_function_enable_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + } + } + + if (update_flags->bits.lut_3d && + u->surface->mcm_luts.lut3d_data.lut3d_src != DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + } + if (check_config->enable_legacy_fast_update && (update_flags->bits.gamma_change || update_flags->bits.gamut_remap_change || @@ -3073,7 +3084,7 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL | LOCK_DESCRIPTOR_LINK); } - if (stream_update->gamut_remap) + if (check_config->enable_legacy_fast_update && stream_update->gamut_remap) su_flags->bits.gamut_remap = 1; if (stream_update->wb_update) @@ -3104,6 +3115,29 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); // Non-global cases + + if (stream_update->gamut_remap) { + su_flags->bits.gamut_remap = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if ((stream_update->hdr_static_metadata && !stream_update->stream->use_dynamic_meta) || + stream_update->vrr_infopacket || + stream_update->vsc_infopacket || + stream_update->vsp_infopacket || + stream_update->hfvsif_infopacket || + stream_update->adaptive_sync_infopacket || + stream_update->vtem_infopacket || + stream_update->avi_infopacket) { + su_flags->bits.info_frame = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->hdr_static_metadata && stream_update->stream->use_dynamic_meta) { + su_flags->bits.dmdata = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + if (stream_update->output_csc_transform) { su_flags->bits.out_csc = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); @@ -3113,6 +3147,26 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( su_flags->bits.out_tf = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } + + if (stream_update->periodic_interrupt) { + su_flags->bits.periodic_interrupt = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->dither_option) { + su_flags->bits.dither = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->cursor_attributes) { + su_flags->bits.cursor_attr = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->cursor_position) { + su_flags->bits.cursor_pos = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } } for (int i = 0 ; i < surface_count; i++) { @@ -3170,10 +3224,10 @@ static void copy_surface_update_to_plane( surface->flip_immediate = srf_update->flip_addr->flip_immediate; surface->time.time_elapsed_in_us[surface->time.index] = - srf_update->flip_addr->flip_timestamp_in_us - - surface->time.prev_update_time_in_us; + (unsigned int)(srf_update->flip_addr->flip_timestamp_in_us - + surface->time.prev_update_time_in_us); surface->time.prev_update_time_in_us = - srf_update->flip_addr->flip_timestamp_in_us; + (unsigned int)srf_update->flip_addr->flip_timestamp_in_us; surface->time.index++; if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX) surface->time.index = 0; @@ -3250,12 +3304,24 @@ static void copy_surface_update_to_plane( sizeof(struct dc_transfer_func_distributed_points)); } - /* Shaper, 3DLUT, 1DLUT */ - if (srf_update->cm) { - memcpy(&surface->cm, srf_update->cm, - sizeof(surface->cm)); + if (srf_update->cm2_params) { + surface->mcm_shaper_3dlut_setting = srf_update->cm2_params->component_settings.shaper_3dlut_setting; + surface->mcm_lut1d_enable = srf_update->cm2_params->component_settings.lut1d_enable; + surface->mcm_luts = srf_update->cm2_params->cm2_luts; } + if (srf_update->func_shaper) { + memcpy(&surface->in_shaper_func, srf_update->func_shaper, + sizeof(surface->in_shaper_func)); + + if (surface->mcm_shaper_3dlut_setting >= DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER) + surface->mcm_luts.shaper = &surface->in_shaper_func; + } + + if (srf_update->lut3d_func) + memcpy(&surface->lut3d_func, srf_update->lut3d_func, + sizeof(surface->lut3d_func)); + if (srf_update->hdr_mult.value) surface->hdr_mult = srf_update->hdr_mult; @@ -3264,6 +3330,17 @@ static void copy_surface_update_to_plane( surface->sdr_white_level_nits = srf_update->sdr_white_level_nits; + if (srf_update->blend_tf) { + memcpy(&surface->blend_tf, srf_update->blend_tf, + sizeof(surface->blend_tf)); + + if (surface->mcm_lut1d_enable) + surface->mcm_luts.lut1d_func = &surface->blend_tf; + } + + if (srf_update->cm2_params || srf_update->blend_tf) + surface->lut_bank_a = !surface->lut_bank_a; + if (srf_update->input_csc_color_matrix) surface->input_csc_color_matrix = *srf_update->input_csc_color_matrix; @@ -3387,7 +3464,7 @@ static void copy_stream_update_to_stream(struct dc *dc, stream->test_pattern = *update->pending_test_pattern; /* update current stream with writeback info */ if (update->wb_update) { - int i; + unsigned int i; stream->num_wb_info = update->wb_update->num_wb_info; ASSERT(stream->num_wb_info <= MAX_DWB_PIPES); @@ -3582,7 +3659,8 @@ static bool update_planes_and_stream_state(struct dc *dc, struct dc_state **new_context) { struct dc_state *context; - int i, j; + int i; + unsigned int j; enum surface_update_type update_type; const struct dc_stream_status *stream_status; struct dc_context *dc_ctx = dc->ctx; @@ -3743,14 +3821,433 @@ static bool update_planes_and_stream_state(struct dc *dc, } +static void program_cursor_attributes_sequence( + struct dc *dc, + struct dc_stream_state *stream, + struct dc_state *context, + struct block_sequence_state *seq_state) +{ + int k; + struct pipe_ctx *pipe_to_program = NULL; + bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); + + for (k = 0; k < (int)dc->res_pool->pipe_count; k++) { + struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k]; + + if (tmp_pipe->stream != stream) + continue; + + if (!pipe_to_program) { + pipe_to_program = tmp_pipe; + + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { + hwss_add_begin_cursor_offload_update(seq_state, dc, tmp_pipe); + } else { + hwss_add_cursor_lock(seq_state, dc, pipe_to_program, true); + if (pipe_to_program->next_odm_pipe) + hwss_add_cursor_lock(seq_state, dc, pipe_to_program->next_odm_pipe, true); + } + } + + hwss_add_set_cursor_attribute(seq_state, dc, tmp_pipe); + if (dc->ctx->dmub_srv) + hwss_add_send_update_cursor_info_to_dmu(seq_state, tmp_pipe, k); + if (dc->hwss.set_cursor_sdr_white_level) + hwss_add_set_cursor_sdr_white_level(seq_state, dc, tmp_pipe); + if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) + hwss_add_update_cursor_offload_pipe(seq_state, dc, tmp_pipe); + } + + if (pipe_to_program) { + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { + hwss_add_commit_cursor_offload_update(seq_state, dc, pipe_to_program); + } else { + hwss_add_cursor_lock(seq_state, dc, pipe_to_program, false); + if (pipe_to_program->next_odm_pipe) + hwss_add_cursor_lock(seq_state, dc, pipe_to_program->next_odm_pipe, false); + } + } +} + +static void program_cursor_position_sequence( + struct dc *dc, + struct dc_stream_state *stream, + struct dc_state *context, + struct block_sequence_state *seq_state) +{ + int k; + struct pipe_ctx *pipe_to_program = NULL; + bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); + + for (k = 0; k < (int)dc->res_pool->pipe_count; k++) { + struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k]; + + if (tmp_pipe->stream != stream || + (!tmp_pipe->plane_res.mi && !tmp_pipe->plane_res.hubp) || + !tmp_pipe->plane_state || + (!tmp_pipe->plane_res.xfm && !tmp_pipe->plane_res.dpp) || + (!tmp_pipe->plane_res.ipp && !tmp_pipe->plane_res.dpp)) + continue; + + if (!pipe_to_program) { + pipe_to_program = tmp_pipe; + + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) + hwss_add_begin_cursor_offload_update(seq_state, dc, tmp_pipe); + else + hwss_add_cursor_lock(seq_state, dc, pipe_to_program, true); + } + + hwss_add_set_cursor_position(seq_state, dc, tmp_pipe); + if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) + hwss_add_update_cursor_offload_pipe(seq_state, dc, tmp_pipe); + + if (dc->ctx->dmub_srv) + hwss_add_send_update_cursor_info_to_dmu(seq_state, tmp_pipe, k); + } + + if (pipe_to_program) { + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) + hwss_add_commit_cursor_offload_update(seq_state, dc, pipe_to_program); + else + hwss_add_cursor_lock(seq_state, dc, pipe_to_program, false); + } +} + +static void add_update_info_frame_sequence( + struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + bool is_hdmi_tmds; + bool is_dp; + + if (!pipe_ctx || !pipe_ctx->stream) + return; + + if (pipe_ctx->stream_res.stream_enc == NULL) + return; + + is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); + is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); + + if (!is_hdmi_tmds && !is_dp) + return; + + if (is_hdmi_tmds) { + hwss_add_stream_enc_update_hdmi_info_packets(seq_state, pipe_ctx); + return; + } + + if (is_dp) { + if (dp_is_128b_132b_signal(pipe_ctx)) { + hwss_add_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(seq_state, pipe_ctx); + hwss_add_hpo_dp_stream_enc_update_dp_info_packets(seq_state, pipe_ctx); + } else { + hwss_add_stream_enc_update_dp_info_packets_sdp_line_num(seq_state, pipe_ctx); + hwss_add_stream_enc_update_dp_info_packets(seq_state, pipe_ctx); + } + } +} + +static void add_link_update_dsc_config_sequence( + struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + struct dsc_config *dsc_cfg, + struct dsc_optc_config *dsc_optc_cfg) +{ + struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc *dc = stream->ctx->dc; + struct dccg *dccg = dc->res_pool->dccg; + struct pipe_ctx *top_pipe = pipe_ctx; + struct pipe_ctx *odm_pipe = NULL; + int opp_cnt = 1; + bool should_use_dto_dscclk = false; + struct dsc_config dsc_pps_cfg; + uint8_t *dsc_packed_pps = stream->dsc_packed_pps; + int last_dsc_set_config_step = 0; + + if (!stream->timing.flags.DSC || !dsc) + return; + + while (top_pipe->prev_odm_pipe) + top_pipe = top_pipe->prev_odm_pipe; + + for (odm_pipe = top_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) + opp_cnt++; + + memset(dsc_cfg, 0, sizeof(*dsc_cfg)); + memset(dsc_optc_cfg, 0, sizeof(*dsc_optc_cfg)); + + dsc_cfg->pic_width = (stream->timing.h_addressable + + top_pipe->dsc_padding_params.dsc_hactive_padding + + stream->timing.h_border_left + + stream->timing.h_border_right) / opp_cnt; + dsc_cfg->pic_height = stream->timing.v_addressable + + stream->timing.v_border_top + + stream->timing.v_border_bottom; + dsc_cfg->pixel_encoding = stream->timing.pixel_encoding; + dsc_cfg->color_depth = stream->timing.display_color_depth; + dsc_cfg->is_odm = top_pipe->next_odm_pipe ? true : false; + dsc_cfg->dc_dsc_cfg = stream->timing.dsc_cfg; + ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h % opp_cnt == 0); + dsc_cfg->dc_dsc_cfg.num_slices_h /= opp_cnt; + dsc_cfg->dsc_padding = 0; + + if (dccg && dccg->funcs->set_dto_dscclk && + stream->timing.pix_clk_100hz > 480000) + should_use_dto_dscclk = true; + + if (should_use_dto_dscclk) + hwss_add_dccg_set_dto_dscclk(seq_state, dccg, dsc->inst, + dsc_cfg->dc_dsc_cfg.num_slices_h); + + last_dsc_set_config_step = *seq_state->num_steps; + hwss_add_dsc_set_config(seq_state, dsc, dsc_cfg, dsc_optc_cfg); + hwss_add_dsc_enable_with_opp(seq_state, top_pipe); + + for (odm_pipe = top_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { + struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; + + if (should_use_dto_dscclk) + hwss_add_dccg_set_dto_dscclk(seq_state, dccg, odm_dsc->inst, + dsc_cfg->dc_dsc_cfg.num_slices_h); + + last_dsc_set_config_step = *seq_state->num_steps; + hwss_add_dsc_set_config(seq_state, odm_dsc, dsc_cfg, dsc_optc_cfg); + hwss_add_dsc_enable_with_opp(seq_state, odm_pipe); + } + + if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) + hwss_add_stream_enc_dp_set_dsc_config(seq_state, + pipe_ctx->stream_res.stream_enc, + &seq_state->steps[last_dsc_set_config_step].params.dsc_set_config_simple_params.dsc_optc_cfg); + + hwss_add_tg_set_dsc_config(seq_state, top_pipe->stream_res.tg, + &seq_state->steps[last_dsc_set_config_step].params.dsc_set_config_simple_params.dsc_optc_cfg, true); + + memset(&dsc_pps_cfg, 0, sizeof(dsc_pps_cfg)); + dsc_pps_cfg.pic_width = stream->timing.h_addressable + + stream->timing.h_border_left + stream->timing.h_border_right; + dsc_pps_cfg.pic_height = stream->timing.v_addressable + + stream->timing.v_border_top + stream->timing.v_border_bottom; + dsc_pps_cfg.pixel_encoding = stream->timing.pixel_encoding; + dsc_pps_cfg.color_depth = stream->timing.display_color_depth; + dsc_pps_cfg.is_odm = top_pipe->next_odm_pipe ? true : false; + dsc_pps_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; + dsc_pps_cfg.dsc_padding = top_pipe->dsc_padding_params.dsc_hactive_padding; + + if (dsc->funcs->dsc_get_packed_pps) { + dsc->funcs->dsc_get_packed_pps(dsc, &dsc_pps_cfg, dsc_packed_pps); + + if (dc_is_dp_signal(stream->signal)) { + if (dp_is_128b_132b_signal(pipe_ctx)) + hwss_add_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(seq_state, + pipe_ctx->stream_res.hpo_dp_stream_enc, + true, dsc_packed_pps, false); + else + hwss_add_stream_enc_dp_set_dsc_pps_info_packet(seq_state, + pipe_ctx->stream_res.stream_enc, + true, dsc_packed_pps, false); + } + } +} + +static void commit_planes_do_stream_update_sequence(struct dc *dc, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + enum surface_update_type update_type, + struct dc_state *context, + struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], + unsigned int *num_steps) +{ + int j; + struct block_sequence_state seq_state = { .steps = block_sequence, .num_steps = num_steps }; + struct dsc_config dsc_cfgs[MAX_PIPES]; + struct dsc_optc_config dsc_optc_cfgs[MAX_PIPES]; + unsigned int dsc_cfg_index = 0; + *num_steps = 0; // Initialize to 0 + + // Stream updates + for (j = 0; j < (int)dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; + + if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) { + + if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt) + hwss_add_setup_periodic_interrupt(&seq_state, dc, pipe_ctx); + + if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) || + stream_update->vrr_infopacket || + stream_update->vsc_infopacket || + stream_update->vsp_infopacket || + stream_update->hfvsif_infopacket || + stream_update->adaptive_sync_infopacket || + stream_update->vtem_infopacket || + stream_update->avi_infopacket) { + resource_build_info_frame(pipe_ctx); + add_update_info_frame_sequence(&seq_state, pipe_ctx); + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) + hwss_add_dp_trace_source_sequence(&seq_state, + pipe_ctx->stream->link, + DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); + } + + if (stream_update->hdr_static_metadata && + stream->use_dynamic_meta && + dc->hwss.set_dmdata_attributes && + pipe_ctx->stream->dmdata_address.quad_part != 0) + hwss_add_set_dmdata_attributes(&seq_state, pipe_ctx); + + if (stream_update->gamut_remap) + hwss_add_dpp_program_gamut_remap(&seq_state, pipe_ctx); + + if (stream_update->output_csc_transform) + hwss_add_program_output_csc(&seq_state, dc, pipe_ctx, + stream->output_color_space, + stream->csc_color_matrix.matrix, + pipe_ctx->stream_res.opp->inst); + + if (stream_update->dither_option) { + struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; + resource_build_bit_depth_reduction_params(pipe_ctx->stream, + &pipe_ctx->stream->bit_depth_params); + hwss_add_opp_program_fmt(&seq_state, pipe_ctx->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); + while (odm_pipe) { + hwss_add_opp_program_fmt(&seq_state, odm_pipe->stream_res.opp, + &stream->bit_depth_params, + &stream->clamping); + odm_pipe = odm_pipe->next_odm_pipe; + } + } + + if (stream_update->cursor_attributes) + program_cursor_attributes_sequence(dc, stream, context, &seq_state); + + if (stream_update->cursor_position) + program_cursor_position_sequence(dc, stream, context, &seq_state); + + /* Full fe update*/ + if (update_type == UPDATE_TYPE_FAST) + continue; + + if (stream_update->dsc_config) + if (dsc_cfg_index < MAX_PIPES) { + add_link_update_dsc_config_sequence(&seq_state, + pipe_ctx, + &dsc_cfgs[dsc_cfg_index], + &dsc_optc_cfgs[dsc_cfg_index]); + dsc_cfg_index++; + } + + if (stream_update->mst_bw_update) { + if (stream_update->mst_bw_update->is_increase) + hwss_add_link_increase_mst_payload(&seq_state, + pipe_ctx, + stream_update->mst_bw_update->mst_stream_bw); + else + hwss_add_link_reduce_mst_payload(&seq_state, + pipe_ctx, + stream_update->mst_bw_update->mst_stream_bw); + } + + if (stream_update->pending_test_pattern) { + /* + * test pattern params depends on ODM topology + * changes that we could be applying to front + * end. Since at the current stage front end + * changes are not yet applied. We can only + * apply test pattern in hw based on current + * state and populate the final test pattern + * params in new state. If current and new test + * pattern params are different as result of + * different ODM topology being used, it will be + * detected and handle during front end + * programming update. + */ + hwss_add_dp_set_test_pattern(&seq_state, + stream->link, + stream->test_pattern.type, + stream->test_pattern.color_space, + stream->test_pattern.p_link_settings, + stream->test_pattern.p_custom_pattern, + stream->test_pattern.cust_pattern_size); + resource_build_test_pattern_params(&context->res_ctx, pipe_ctx); + } + + if (stream_update->dpms_off) { + // DPMS should not use partially updated pipe context + struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j]; + + if (*stream_update->dpms_off) { + hwss_add_link_set_dpms_off(&seq_state, dpms_pipe_ctx); + /* for dpms, keep acquired resources*/ + if (dpms_pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) + hwss_add_disable_audio_stream(&seq_state, dpms_pipe_ctx); + + hwss_add_dc_set_optimized_required(&seq_state, dc, true); + + } else { + if (get_seamless_boot_stream_count(context) == 0) + hwss_add_prepare_bandwidth(&seq_state, dc, dc->current_state); + hwss_add_link_set_dpms_on(&seq_state, dc->current_state, dpms_pipe_ctx); + } + } else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space + && !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) { + /* + * Workaround for firmware issue in some receivers where they don't pick up + * correct output color space unless DP link is disabled/re-enabled + */ + hwss_add_link_set_dpms_on(&seq_state, dc->current_state, pipe_ctx); + } + + if (stream_update->abm_level && pipe_ctx->stream_res.abm) { + bool should_program_abm = true; + + // if otg funcs defined check if blanked before programming + if (pipe_ctx->stream_res.tg->funcs->is_blanked) + if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) + should_program_abm = false; + + if (should_program_abm) { + if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) { + hwss_add_abm_set_immediate_disable(&seq_state, dc, pipe_ctx); + } else { + hwss_add_abm_set_level(&seq_state, pipe_ctx->stream_res.abm, stream->abm_level); + } + } + } + } + } +} + static void commit_planes_do_stream_update(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update, enum surface_update_type update_type, struct dc_state *context) { - int j; + unsigned int j; + // Check if block sequence programming is enabled + if (dc->debug.enable_block_sequence_programming) { + unsigned int num_steps = 0; + + // Build the block sequence using context's pre-allocated array + commit_planes_do_stream_update_sequence(dc, stream, stream_update, + update_type, context, context->block_sequence, &num_steps); + + // Execute the block sequence + if (num_steps > 0) + hwss_execute_sequence(dc, context->block_sequence, num_steps); + + return; + } + + // Legacy path (existing implementation) // Stream updates for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -3849,27 +4346,34 @@ static void commit_planes_do_stream_update(struct dc *dc, resource_build_test_pattern_params(&context->res_ctx, pipe_ctx); } + // DPMS should not use partially updated pipe context + struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j]; + if (stream_update->dpms_off) { if (*stream_update->dpms_off) { - dc->link_srv->set_dpms_off(pipe_ctx); + dc->link_srv->set_dpms_off(dpms_pipe_ctx); /* for dpms, keep acquired resources*/ - if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) - pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); + if (dpms_pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) { + struct audio *audio = dpms_pipe_ctx->stream_res.audio; + + audio->funcs->az_disable(audio); + } dc->optimized_required = true; } else { if (get_seamless_boot_stream_count(context) == 0) dc->hwss.prepare_bandwidth(dc, dc->current_state); - dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx); + dc->link_srv->set_dpms_on(dc->current_state, dpms_pipe_ctx); } - } else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space - && !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) { + } else if (dpms_pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && + stream_update->output_color_space && + !stream->dpms_off && dc_is_dp_signal(dpms_pipe_ctx->stream->signal)) { /* * Workaround for firmware issue in some receivers where they don't pick up * correct output color space unless DP link is disabled/re-enabled */ - dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx); + dc->link_srv->set_dpms_on(dc->current_state, dpms_pipe_ctx); } if (stream_update->abm_level && pipe_ctx->stream_res.abm) { @@ -3918,7 +4422,8 @@ void dc_dmub_update_dirty_rect(struct dc *dc, { union dmub_rb_cmd cmd; struct dmub_cmd_update_dirty_rect_data *update_dirty_rect; - unsigned int i, j; + int i; + unsigned int j; unsigned int panel_inst = 0; if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) @@ -3949,7 +4454,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, else update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; - update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; + update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); for (j = 0; j < dc->res_pool->pipe_count; j++) { @@ -3960,9 +4465,9 @@ void dc_dmub_update_dirty_rect(struct dc *dc, if (pipe_ctx->plane_state != plane_state) continue; - update_dirty_rect->panel_inst = panel_inst; - update_dirty_rect->pipe_idx = j; - update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; + update_dirty_rect->panel_inst = (uint8_t)panel_inst; + update_dirty_rect->pipe_idx = (uint8_t)j; + update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); } } @@ -3979,7 +4484,8 @@ static void build_dmub_update_dirty_rect( { union dmub_rb_cmd cmd; struct dmub_cmd_update_dirty_rect_data *update_dirty_rect; - unsigned int i, j; + int i; + unsigned int j; unsigned int panel_inst = 0; if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) @@ -4010,7 +4516,7 @@ static void build_dmub_update_dirty_rect( else update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; - update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; + update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); for (j = 0; j < dc->res_pool->pipe_count; j++) { @@ -4020,9 +4526,9 @@ static void build_dmub_update_dirty_rect( continue; if (pipe_ctx->plane_state != plane_state) continue; - update_dirty_rect->panel_inst = panel_inst; - update_dirty_rect->pipe_idx = j; - update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; + update_dirty_rect->panel_inst = (uint8_t)panel_inst; + update_dirty_rect->pipe_idx = (uint8_t)j; + update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd; dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; (*dmub_cmd_count)++; @@ -4076,7 +4582,8 @@ static void commit_plane_for_stream_offload_fams2_flip(struct dc *dc, struct dc_stream_state *stream, struct dc_state *context) { - int i, j; + int i; + unsigned int j; /* update dirty rect for PSR */ dc_dmub_update_dirty_rect(dc, surface_count, stream, @@ -4117,7 +4624,8 @@ static void commit_planes_for_stream_fast(struct dc *dc, enum surface_update_type update_type, struct dc_state *context) { - int i, j; + int i; + unsigned int j; struct pipe_ctx *top_pipe_to_program = NULL; struct dc_stream_status *stream_status = NULL; bool should_offload_fams2_flip = false; @@ -4157,7 +4665,7 @@ static void commit_planes_for_stream_fast(struct dc *dc, if (!top_pipe_to_program) return; - for (i = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < (int)dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; if (pipe->stream && pipe->plane_state) { @@ -4236,7 +4744,8 @@ static void commit_planes_for_stream(struct dc *dc, enum surface_update_type update_type, struct dc_state *context) { - int i, j; + int i; + unsigned int j, pipe_idx; struct pipe_ctx *top_pipe_to_program = NULL; bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST); bool subvp_prev_use = false; @@ -4258,8 +4767,8 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming) dc->res_pool->funcs->prepare_mcache_programming(dc, context); - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[pipe_idx]; if (pipe->stream && pipe->plane_state) { if (!dc->debug.using_dml2) @@ -4290,8 +4799,8 @@ static void commit_planes_for_stream(struct dc *dc, stream); ASSERT(top_pipe_to_program != NULL); - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_idx]; // Check old context for SubVP subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) == SUBVP_PHANTOM); @@ -4299,8 +4808,8 @@ static void commit_planes_for_stream(struct dc *dc, break; } - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[pipe_idx]; if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { subvp_curr_use = true; @@ -4325,7 +4834,7 @@ static void commit_planes_for_stream(struct dc *dc, struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_dig = 1; - inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; + inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst; dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, true, @@ -4453,7 +4962,7 @@ static void commit_planes_for_stream(struct dc *dc, if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && should_update_pipe_for_stream(context, pipe_ctx, stream)) { - struct dc_stream_status *stream_status = NULL; + struct dc_stream_status *pipe_stream_status = NULL; if (!pipe_ctx->plane_state) continue; @@ -4462,12 +4971,12 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type == UPDATE_TYPE_FAST) continue; - stream_status = + pipe_stream_status = stream_get_status(context, pipe_ctx->stream); - if (dc->hwss.apply_ctx_for_surface && stream_status) + if (dc->hwss.apply_ctx_for_surface && pipe_stream_status) dc->hwss.apply_ctx_for_surface( - dc, pipe_ctx->stream, stream_status->plane_count, context); + dc, pipe_ctx->stream, pipe_stream_status->plane_count, context); } } @@ -4502,16 +5011,16 @@ static void commit_planes_for_stream(struct dc *dc, } if (dc->debug.validate_dml_output) { - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; if (cur_pipe->stream == NULL) continue; cur_pipe->plane_res.hubp->funcs->validate_dml_output( cur_pipe->plane_res.hubp, dc->ctx, - &context->res_ctx.pipe_ctx[i].rq_regs, - &context->res_ctx.pipe_ctx[i].dlg_regs, - &context->res_ctx.pipe_ctx[i].ttu_regs); + &context->res_ctx.pipe_ctx[pipe_idx].rq_regs, + &context->res_ctx.pipe_ctx[pipe_idx].dlg_regs, + &context->res_ctx.pipe_ctx[pipe_idx].ttu_regs); } } } @@ -4550,9 +5059,11 @@ static void commit_planes_for_stream(struct dc *dc, if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) continue; - if (srf_updates[i].cm && - srf_updates[i].cm->flags.bits.lut3d_enable && - srf_updates[i].cm->flags.bits.lut3d_dma_enable && + if (srf_updates[i].cm2_params && + srf_updates[i].cm2_params->cm2_luts.lut3d_data.lut3d_src == + DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM && + srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting == + DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT && dc->hwss.trigger_3dlut_dma_load) dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx); @@ -4592,7 +5103,7 @@ static void commit_planes_for_stream(struct dc *dc, struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_dig = 1; - inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; + inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst; dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, false, @@ -4831,7 +5342,7 @@ static void swap_and_release_current_context(struct dc *dc, struct dc_state *new_context, struct dc_stream_state *stream) { - int i; + unsigned int i; struct dc_state *old = dc->current_state; struct pipe_ctx *pipe_ctx; @@ -5091,7 +5602,7 @@ static bool commit_minimal_transition_state(struct dc *dc, /* force full surface update */ for (i = 0; i < dc->current_state->stream_count; i++) { - for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { + for (j = 0; j < (unsigned int)dc->current_state->stream_status[i].plane_count; j++) { dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF; } } @@ -5109,9 +5620,35 @@ void populate_fast_updates(struct dc_fast_update *fast_update, if (stream_update) { fast_update[0].out_transfer_func = stream_update->out_transfer_func; fast_update[0].output_csc_transform = stream_update->output_csc_transform; + fast_update[0].cursor_attributes = stream_update->cursor_attributes; + fast_update[0].cursor_position = stream_update->cursor_position; + fast_update[0].periodic_interrupt = stream_update->periodic_interrupt; + fast_update[0].dither_option = stream_update->dither_option; + fast_update[0].gamut_remap = stream_update->gamut_remap; + fast_update[0].vrr_infopacket = stream_update->vrr_infopacket; + fast_update[0].vsc_infopacket = stream_update->vsc_infopacket; + fast_update[0].vsp_infopacket = stream_update->vsp_infopacket; + fast_update[0].hfvsif_infopacket = stream_update->hfvsif_infopacket; + fast_update[0].vtem_infopacket = stream_update->vtem_infopacket; + fast_update[0].adaptive_sync_infopacket = stream_update->adaptive_sync_infopacket; + fast_update[0].avi_infopacket = stream_update->avi_infopacket; + fast_update[0].hdr_static_metadata = stream_update->hdr_static_metadata; } else { fast_update[0].out_transfer_func = NULL; fast_update[0].output_csc_transform = NULL; + fast_update[0].cursor_attributes = NULL; + fast_update[0].cursor_position = NULL; + fast_update[0].periodic_interrupt = NULL; + fast_update[0].dither_option = NULL; + fast_update[0].gamut_remap = NULL; + fast_update[0].vrr_infopacket = NULL; + fast_update[0].vsc_infopacket = NULL; + fast_update[0].vsp_infopacket = NULL; + fast_update[0].hfvsif_infopacket = NULL; + fast_update[0].vtem_infopacket = NULL; + fast_update[0].adaptive_sync_infopacket = NULL; + fast_update[0].avi_infopacket = NULL; + fast_update[0].hdr_static_metadata = NULL; } for (i = 0; i < surface_count; i++) { @@ -5121,9 +5658,7 @@ void populate_fast_updates(struct dc_fast_update *fast_update, fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix; fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor; fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix; -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) fast_update[i].cm_hist_control = srf_updates[i].cm_hist_control; -#endif } } @@ -5132,7 +5667,20 @@ static bool fast_updates_exist(const struct dc_fast_update *fast_update, int sur int i; if (fast_update[0].out_transfer_func || - fast_update[0].output_csc_transform) + fast_update[0].output_csc_transform || + fast_update[0].cursor_attributes || + fast_update[0].cursor_position || + fast_update[0].periodic_interrupt || + fast_update[0].dither_option || + fast_update[0].gamut_remap || + fast_update[0].vrr_infopacket || + fast_update[0].vsc_infopacket || + fast_update[0].vsp_infopacket || + fast_update[0].hfvsif_infopacket || + fast_update[0].vtem_infopacket || + fast_update[0].adaptive_sync_infopacket || + fast_update[0].avi_infopacket || + fast_update[0].hdr_static_metadata) return true; for (i = 0; i < surface_count; i++) { @@ -5141,9 +5689,7 @@ static bool fast_updates_exist(const struct dc_fast_update *fast_update, int sur fast_update[i].gamut_remap_matrix || fast_update[i].input_csc_color_matrix || fast_update[i].cursor_csc_color_matrix || -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) fast_update[i].cm_hist_control || -#endif fast_update[i].coeff_reduction_factor) return true; } @@ -5156,7 +5702,20 @@ bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_ int i; if (fast_update[0].out_transfer_func || - fast_update[0].output_csc_transform) + fast_update[0].output_csc_transform || + fast_update[0].gamut_remap || + fast_update[0].cursor_attributes || + fast_update[0].cursor_position || + fast_update[0].periodic_interrupt || + fast_update[0].dither_option || + fast_update[0].vrr_infopacket || + fast_update[0].vsc_infopacket || + fast_update[0].vsp_infopacket || + fast_update[0].hfvsif_infopacket || + fast_update[0].vtem_infopacket || + fast_update[0].adaptive_sync_infopacket || + fast_update[0].avi_infopacket || + fast_update[0].hdr_static_metadata) return true; for (i = 0; i < surface_count; i++) { @@ -5164,9 +5723,7 @@ bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_ fast_update[i].gamma || fast_update[i].gamut_remap_matrix || fast_update[i].coeff_reduction_factor || -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) fast_update[i].cm_hist_control || -#endif fast_update[i].cursor_csc_color_matrix) return true; } @@ -5209,12 +5766,6 @@ static bool full_update_required( const struct dc_stream_update *stream_update, const struct dc_stream_state *stream) { - const union dc_plane_cm_flags blend_only_flags = { - .bits = { - .blend_enable = 1, - } - }; - if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) return true; @@ -5227,12 +5778,14 @@ static bool full_update_required( (srf_updates[i].sdr_white_level_nits && srf_updates[i].sdr_white_level_nits != srf_updates->surface->sdr_white_level_nits) || srf_updates[i].in_transfer_func || + srf_updates[i].func_shaper || + srf_updates[i].lut3d_func || srf_updates[i].surface->force_full_update || (srf_updates[i].flip_addr && srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) || - (srf_updates[i].cm && - ((srf_updates[i].cm->flags.all != blend_only_flags.all && srf_updates[i].cm->flags.all != 0) || - (srf_updates[i].surface->cm.flags.all != blend_only_flags.all && srf_updates[i].surface->cm.flags.all != 0))))) + (srf_updates[i].cm2_params && + (srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting != srf_updates[i].surface->mcm_shaper_3dlut_setting || + srf_updates[i].cm2_params->component_settings.lut1d_enable != srf_updates[i].surface->mcm_lut1d_enable)))) return true; } @@ -5240,23 +5793,12 @@ static bool full_update_required( (((stream_update->src.height != 0 && stream_update->src.width != 0) || (stream_update->dst.height != 0 && stream_update->dst.width != 0) || stream_update->integer_scaling_update) || - stream_update->hdr_static_metadata || stream_update->abm_level || - stream_update->periodic_interrupt || - stream_update->vrr_infopacket || - stream_update->vsc_infopacket || - stream_update->vsp_infopacket || - stream_update->hfvsif_infopacket || - stream_update->vtem_infopacket || - stream_update->adaptive_sync_infopacket || - stream_update->avi_infopacket || stream_update->dpms_off || stream_update->allow_freesync || stream_update->vrr_active_variable || stream_update->vrr_active_fixed || - stream_update->gamut_remap || stream_update->output_color_space || - stream_update->dither_option || stream_update->wb_update || stream_update->dsc_config || stream_update->mst_bw_update || @@ -5766,7 +6308,8 @@ bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips) void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char const *caller_name) { - int idle_fclk_khz = 0, idle_dramclk_khz = 0, i = 0; + int idle_fclk_khz = 0, idle_dramclk_khz = 0; + unsigned int i = 0; enum mall_stream_type subvp_pipe_type[MAX_PIPES] = {0}; struct pipe_ctx *pipe = NULL; struct dc_state *context = dc->current_state; @@ -5865,7 +6408,7 @@ static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memcl struct dc_state *context = dc->current_state; struct hubp *hubp; struct pipe_ctx *pipe; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { pipe = &context->res_ctx.pipe_ctx[i]; @@ -6071,7 +6614,11 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc, uint8_t action; union dmub_rb_cmd cmd = {0}; - ASSERT(payload->length <= 16); + if (link_index >= dc->link_count || !dc->links[link_index]) + return false; + + if (payload->length > sizeof(cmd.dp_aux_access.aux_control.dpaux.data)) + return false; cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS; cmd.dp_aux_access.header.payload_bytes = 0; @@ -6081,12 +6628,12 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc, else cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC; - cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst; + cmd.dp_aux_access.aux_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst; cmd.dp_aux_access.aux_control.sw_crc_enabled = 0; cmd.dp_aux_access.aux_control.timeout = 0; cmd.dp_aux_access.aux_control.dpaux.address = payload->address; cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux; - cmd.dp_aux_access.aux_control.dpaux.length = payload->length; + cmd.dp_aux_access.aux_control.dpaux.length = (uint8_t)payload->length; /* set aux action */ if (payload->i2c_over_aux) { @@ -6152,7 +6699,7 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_ } if (pipe_ctx) - otg_inst = pipe_ctx->stream_res.tg->inst; + otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; // before enable smart power OLED, we need to call set pipe for DMUB to set ABM config if (enable) { @@ -6169,11 +6716,11 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_ sizeof(struct dmub_rb_cmd_smart_power_oled_enable_data) - sizeof(struct dmub_cmd_header); cmd.smart_power_oled_enable.header.ret_status = 1; cmd.smart_power_oled_enable.data.enable = enable; - cmd.smart_power_oled_enable.data.panel_inst = panel_inst; + cmd.smart_power_oled_enable.data.panel_inst = (uint8_t)panel_inst; cmd.smart_power_oled_enable.data.peak_nits = peak_nits; cmd.smart_power_oled_enable.data.otg_inst = otg_inst; - cmd.smart_power_oled_enable.data.digfe_inst = link->link_enc->preferred_engine; - cmd.smart_power_oled_enable.data.digbe_inst = link->link_enc->transmitter; + cmd.smart_power_oled_enable.data.digfe_inst = (uint8_t)link->link_enc->preferred_engine; + cmd.smart_power_oled_enable.data.digbe_inst = (uint8_t)link->link_enc->transmitter; cmd.smart_power_oled_enable.data.debugcontrol = debug_control; cmd.smart_power_oled_enable.data.triggerline = triggerline; @@ -6182,6 +6729,10 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_ // send cmd status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); + // Update firmware_controlled_hdr_info_packet state on successful command execution + if (status && pipe_ctx) + pipe_ctx->stream->firmware_controlled_hdr_info_packet = enable; + return status; } @@ -6204,7 +6755,7 @@ bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *p cmd.smart_power_oled_getmaxcll.header.payload_bytes = sizeof(cmd.smart_power_oled_getmaxcll.data); cmd.smart_power_oled_getmaxcll.header.ret_status = 1; - cmd.smart_power_oled_getmaxcll.data.input.panel_inst = panel_inst; + cmd.smart_power_oled_getmaxcll.data.input.panel_inst = (uint8_t)panel_inst; // send cmd and wait for reply status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); @@ -6262,7 +6813,7 @@ bool dc_process_dmub_set_config_async(struct dc *dc, cmd.set_config_access.header.type = DMUB_CMD__DPIA; cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS; - cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst; + cmd.set_config_access.set_config_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst; cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type; cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data; @@ -6306,7 +6857,7 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA; cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS; - cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst; + cmd.set_mst_alloc_slots.mst_slots_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst; cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots; if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) @@ -6346,7 +6897,7 @@ void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t lin cmd.set_tps_notification.header.type = DMUB_CMD__DPIA; cmd.set_tps_notification.header.sub_type = DMUB_CMD__DPIA_SET_TPS_NOTIFICATION; - cmd.set_tps_notification.tps_notification.instance = dc->links[link_index]->ddc_hw_inst; + cmd.set_tps_notification.tps_notification.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst; cmd.set_tps_notification.tps_notification.tps = tps; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); @@ -6642,7 +7193,7 @@ bool dc_can_clear_cursor_limit(const struct dc *dc) return false; } -void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, +void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data) { struct timing_generator *tg = NULL; @@ -6660,7 +7211,7 @@ void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, dc->hwss.get_underflow_debug_data(dc, tg, out_data); } -void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, +void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data) { (void)primary_otg_inst; @@ -6672,7 +7223,8 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa { struct dc_state *context; struct resource_context *res_ctx; - int i; + unsigned int i; + const unsigned int max_pipes = MAX_PIPES; if (!dc || !dc->current_state || !state) { if (state) @@ -6696,7 +7248,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture HUBP programming state for each pipe */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; state->hubp[i].valid_stream = false; @@ -6818,7 +7370,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa /* Capture HUBBUB programming state */ if (dc->res_pool->hubbub) { /* Individual DET buffer sizes - software state variables that program DET registers */ - for (i = 0; i < 4 && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < 4u && i < dc->res_pool->pipe_count; i++) { uint32_t det_size = res_ctx->pipe_ctx[i].det_buffer_size_kb; switch (i) { case 0: @@ -6842,7 +7394,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture DPP programming state for each pipe */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (!pipe_ctx->stream) @@ -6883,7 +7435,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa state->dccg.dispclk_khz = dc->clk_mgr->clks.dispclk_khz; /* Per-pipe clock configuration - only capture what's essential */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (pipe_ctx->stream) { /* Essential clocks that directly affect underflow risk */ @@ -6910,7 +7462,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* DSC clock state - only when actually using DSC */ - for (i = 0; i < MAX_PIPES; i++) { + for (i = 0; i < max_pipes; i++) { struct pipe_ctx *pipe_ctx = (i < dc->res_pool->pipe_count) ? &res_ctx->pipe_ctx[i] : NULL; if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) { state->dccg.dscclk_khz[i] = 400000; /* Typical DSC clock frequency */ @@ -6927,7 +7479,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture essential DSC configuration for underflow analysis */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) { @@ -6955,14 +7507,14 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture MPC programming state - comprehensive register field coverage */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (pipe_ctx->plane_state && pipe_ctx->stream) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; /* MPCC blending tree and mode control - capture actual blend configuration */ - state->mpc.mpcc_mode[i] = (plane_state->cm.blend_func.type != TF_TYPE_BYPASS) ? 1 : 0; + state->mpc.mpcc_mode[i] = (plane_state->blend_tf.type != TF_TYPE_BYPASS) ? 1 : 0; state->mpc.mpcc_alpha_blend_mode[i] = plane_state->per_pixel_alpha ? 1 : 0; state->mpc.mpcc_alpha_multiplied_mode[i] = plane_state->pre_multiplied_alpha ? 1 : 0; state->mpc.mpcc_blnd_active_overlap_only[i] = 0; /* Default - no overlap restriction */ @@ -7023,7 +7575,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture OPP programming state for each pipe - comprehensive register field coverage */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (!pipe_ctx->stream) @@ -7141,7 +7693,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa } /* Capture OPTC programming state for each pipe - comprehensive register field coverage */ - for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (!pipe_ctx->stream) @@ -7237,7 +7789,8 @@ void dc_log_preos_dmcub_info(const struct dc *dc) bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info) { const struct dc_clocks *clk = &dc->current_state->bw_ctx.bw.dcn.clk; - struct memory_qos qos; + struct dc_measured_memory_qos measured = {}; + struct dc_requested_memory_qos requested = {}; memset(info, 0, sizeof(*info)); @@ -7246,20 +7799,38 @@ bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info) return false; } - // Call unified measurement function - dc->hwss.measure_memory_qos(dc, &qos); + dc->hwss.measure_memory_qos(dc, &measured); - // Populate info from measured qos - info->actual_peak_bw_in_mbps = qos.peak_bw_mbps; - info->actual_avg_bw_in_mbps = qos.avg_bw_mbps; - info->actual_min_latency_in_ns = qos.min_latency_ns; - info->actual_max_latency_in_ns = qos.max_latency_ns; - info->actual_avg_latency_in_ns = qos.avg_latency_ns; - info->dcn_bandwidth_ub_in_mbps = (uint32_t)(clk->fclk_khz / 1000 * 64); + info->actual_peak_bw_in_mbps = measured.peak_bw_mbps; + info->actual_avg_bw_in_mbps = measured.avg_bw_mbps; + info->actual_min_latency_in_ns = measured.min_latency_ns; + info->actual_max_latency_in_ns = measured.max_latency_ns; + info->actual_avg_latency_in_ns = measured.avg_latency_ns; + info->dcn_bandwidth_ub_in_mbps = (uint32_t)(clk->fclk_khz / 1000 * 64); + + if (dc->clk_mgr && dc->clk_mgr->funcs->get_requested_memory_qos) { + dc->clk_mgr->funcs->get_requested_memory_qos(dc->clk_mgr, &requested); + info->qos_bandwidth_lb_in_mbps = requested.bandwidth_lb_in_mbps; + info->calculated_avg_bw_in_mbps = requested.calculated_avg_bw_in_mbps; + info->qos_max_latency_ub_in_ns = requested.max_latency_ub_in_ns; + info->qos_avg_latency_ub_in_ns = requested.avg_latency_ub_in_ns; + info->qos_max_bw_budget_in_mbps = requested.max_bw_budget_in_mbps; + } return true; } +unsigned int dc_override_memory_bandwidth_request( + struct dc *dc, + unsigned int bw_mbps) +{ + if (!dc->clk_mgr || !dc->clk_mgr->funcs) + return 0; + + return dc->clk_mgr->funcs->override_memory_bandwidth_request( + dc->clk_mgr, bw_mbps * 1000) / 1000; +} + enum update_v3_flow { UPDATE_V3_FLOW_INVALID, UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 7333f5905330..1916aa3ebaea 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -39,6 +39,7 @@ #include "abm.h" #include "dcn10/dcn10_hubbub.h" #include "dce/dmub_hw_lock_mgr.h" +#include "link_service.h" #define MAX_NUM_MCACHE 8 @@ -345,39 +346,39 @@ void get_surface_visual_confirm_color( switch (pipe_ctx->plane_res.scl_data.format) { case PIXEL_FORMAT_ARGB8888: /* set border color to red */ - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; if (pipe_ctx->plane_state->layer_index > 0) { /* set border color to pink */ - color->color_b_cb = color_value; - color->color_g_y = color_value * 0.5; + color->color_b_cb = (uint16_t)color_value; + color->color_g_y = (uint16_t)(color_value / 2); } break; case PIXEL_FORMAT_ARGB2101010: /* set border color to blue */ - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; if (pipe_ctx->plane_state->layer_index > 0) { /* set border color to cyan */ - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; } break; case PIXEL_FORMAT_420BPP8: /* set border color to green */ - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; break; case PIXEL_FORMAT_420BPP10: /* set border color to yellow */ - color->color_g_y = color_value; - color->color_r_cr = color_value; + color->color_g_y = (uint16_t)color_value; + color->color_r_cr = (uint16_t)color_value; break; case PIXEL_FORMAT_FP16: /* set border color to white */ - color->color_r_cr = color_value; - color->color_b_cb = color_value; - color->color_g_y = color_value; + color->color_r_cr = (uint16_t)color_value; + color->color_b_cb = (uint16_t)color_value; + color->color_g_y = (uint16_t)color_value; if (pipe_ctx->plane_state->layer_index > 0) { /* set border color to orange */ - color->color_g_y = 0.22 * color_value; + color->color_g_y = (uint16_t)((color_value * 22) / 100); color->color_b_cb = 0; } break; @@ -403,21 +404,21 @@ void get_hdr_visual_confirm_color( case PIXEL_FORMAT_ARGB2101010: if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) { /* HDR10, ARGB2101010 - set border color to red */ - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) { /* FreeSync 2 ARGB2101010 - set border color to pink */ - color->color_r_cr = color_value; - color->color_b_cb = color_value; + color->color_r_cr = (uint16_t)color_value; + color->color_b_cb = (uint16_t)color_value; } else is_sdr = true; break; case PIXEL_FORMAT_FP16: if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) { /* HDR10, FP16 - set border color to blue */ - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) { /* FreeSync 2 HDR - set border color to green */ - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; } else is_sdr = true; break; @@ -428,9 +429,9 @@ void get_hdr_visual_confirm_color( if (is_sdr) { /* SDR - set border color to Gray */ - color->color_r_cr = color_value/2; - color->color_b_cb = color_value/2; - color->color_g_y = color_value/2; + color->color_r_cr = (uint16_t)(color_value / 2); + color->color_b_cb = (uint16_t)(color_value / 2); + color->color_g_y = (uint16_t)(color_value / 2); } } @@ -454,7 +455,7 @@ void get_smartmux_visual_confirm_color( *color = sm_ver_colors[dc->config.smart_mux_version]; } else { /* dGPU driving the eDP - red */ - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; color->color_b_cb = 0; } @@ -476,19 +477,19 @@ void get_vabc_visual_confirm_color( if (edp_link) { switch (edp_link->backlight_control_type) { case BACKLIGHT_CONTROL_PWM: - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; color->color_b_cb = 0; break; case BACKLIGHT_CONTROL_AMD_AUX: color->color_r_cr = 0; - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; color->color_b_cb = 0; break; case BACKLIGHT_CONTROL_VESA_AUX: color->color_r_cr = 0; color->color_g_y = 0; - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; break; } } else { @@ -506,19 +507,19 @@ void get_subvp_visual_confirm_color( if (pipe_ctx) { switch (pipe_ctx->p_state_type) { case P_STATE_SUB_VP: - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; color->color_b_cb = 0; break; case P_STATE_DRR_SUB_VP: color->color_r_cr = 0; - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; color->color_b_cb = 0; break; case P_STATE_V_BLANK_SUB_VP: color->color_r_cr = 0; color->color_g_y = 0; - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; break; default: break; @@ -535,34 +536,34 @@ void get_mclk_switch_visual_confirm_color( if (pipe_ctx) { switch (pipe_ctx->p_state_type) { case P_STATE_V_BLANK: - color->color_r_cr = color_value; - color->color_g_y = color_value; + color->color_r_cr = (uint16_t)color_value; + color->color_g_y = (uint16_t)color_value; color->color_b_cb = 0; break; case P_STATE_FPO: color->color_r_cr = 0; - color->color_g_y = color_value; - color->color_b_cb = color_value; + color->color_g_y = (uint16_t)color_value; + color->color_b_cb = (uint16_t)color_value; break; case P_STATE_V_ACTIVE: - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; break; case P_STATE_SUB_VP: - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; color->color_b_cb = 0; break; case P_STATE_DRR_SUB_VP: color->color_r_cr = 0; - color->color_g_y = color_value; + color->color_g_y = (uint16_t)color_value; color->color_b_cb = 0; break; case P_STATE_V_BLANK_SUB_VP: color->color_r_cr = 0; color->color_g_y = 0; - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; break; default: break; @@ -577,13 +578,13 @@ void get_cursor_visual_confirm_color( uint32_t color_value = MAX_TG_COLOR_VALUE; if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) { - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; color->color_g_y = 0; color->color_b_cb = 0; } else { color->color_r_cr = 0; color->color_g_y = 0; - color->color_b_cb = color_value; + color->color_b_cb = (uint16_t)color_value; } } @@ -665,7 +666,7 @@ void set_p_state_switch_method( /* SubVP */ enable_subvp = false; - for (int i = 0; i < dc->res_pool->pipe_count; i++) { + for (unsigned int i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) && @@ -721,9 +722,9 @@ void get_fams2_visual_confirm_color( /* driver only handles visual confirm when FAMS2 is disabled */ if (!dc_state_is_fams2_in_use(dc, context)) { /* when FAMS2 is disabled, all pipes are grey */ - color->color_g_y = color_value / 2; - color->color_b_cb = color_value / 2; - color->color_r_cr = color_value / 2; + color->color_g_y = (uint16_t)(color_value / 2); + color->color_b_cb = (uint16_t)(color_value / 2); + color->color_r_cr = (uint16_t)(color_value / 2); } } @@ -789,8 +790,241 @@ void hwss_build_fast_sequence(struct dc *dc, (*num_steps)++; } + if (dc->hwss.setup_periodic_interrupt && stream->update_flags.bits.periodic_interrupt) { + block_sequence[*num_steps].params.setup_periodic_interrupt_params.dc = dc; + block_sequence[*num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx; + block_sequence[*num_steps].func = HWSS_SETUP_PERIODIC_INTERRUPT; + (*num_steps)++; + } + + if (stream->update_flags.bits.info_frame) { + resource_build_info_frame(pipe_ctx); + block_sequence[*num_steps].params.update_info_frame_params.dc = dc; + block_sequence[*num_steps].params.update_info_frame_params.pipe_ctx = pipe_ctx; + block_sequence[*num_steps].func = HWSS_UPDATE_INFO_FRAME; + (*num_steps)++; + + if (dc_is_dp_signal(pipe_ctx->stream->signal)) { + block_sequence[*num_steps].params.dp_trace_source_sequence_params.link = pipe_ctx->stream->link; + block_sequence[*num_steps].params.dp_trace_source_sequence_params.source = DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME; + block_sequence[*num_steps].func = DP_TRACE_SOURCE_SEQUENCE; + (*num_steps)++; + } + } + + if (dc->hwss.set_dmdata_attributes && stream->update_flags.bits.dmdata && + stream->use_dynamic_meta && pipe_ctx->stream->dmdata_address.quad_part != 0) { + struct dc_dmdata_attributes attr = { 0 }; + + attr.dmdata_mode = DMDATA_HW_MODE; + attr.dmdata_size = dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; + attr.address.quad_part = pipe_ctx->stream->dmdata_address.quad_part; + attr.dmdata_dl_delta = 0; + attr.dmdata_qos_mode = 0; + attr.dmdata_qos_level = 0; + attr.dmdata_repeat = 1; /* always repeat */ + attr.dmdata_updated = 1; + attr.dmdata_sw_data = NULL; + + block_sequence[*num_steps].params.set_dmdata_attributes_params.hubp = pipe_ctx->plane_res.hubp; + block_sequence[*num_steps].params.set_dmdata_attributes_params.attr = attr; + block_sequence[*num_steps].func = HUBP_SET_DMDATA_ATTRIBUTES; + (*num_steps)++; + } + + /* Track cursor lock state - separate locks for attribute and position updates */ + bool enable_cursor_offload = false; + + if ((dc->hwss.set_cursor_attribute && stream->update_flags.bits.cursor_attr) || + (dc->hwss.set_cursor_position && stream->update_flags.bits.cursor_pos)) + enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); + + /* Cursor attribute updates - separate lock/iterate/unlock */ + if (dc->hwss.set_cursor_attribute && stream->update_flags.bits.cursor_attr) { + struct pipe_ctx *cursor_pipe_to_program = NULL; + + for (i = 0; i < MAX_PIPES; i++) { + current_pipe = &context->res_ctx.pipe_ctx[i]; + + if (current_pipe->stream != stream) + continue; + + if (!cursor_pipe_to_program) { + cursor_pipe_to_program = current_pipe; + + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { + block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc; + block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE; + (*num_steps)++; + } else { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe; + block_sequence[*num_steps].params.cursor_lock_params.lock = true; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + + if (current_pipe->next_odm_pipe) { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = + current_pipe->next_odm_pipe; + block_sequence[*num_steps].params.cursor_lock_params.lock = true; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + } + } + } + + block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.hubp = + current_pipe->plane_res.hubp; + block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.attributes = + ¤t_pipe->stream->cursor_attributes; + block_sequence[*num_steps].func = HUBP_SET_CURSOR_ATTRIBUTES; + (*num_steps)++; + + block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.dpp = + current_pipe->plane_res.dpp; + block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.attributes = + ¤t_pipe->stream->cursor_attributes; + block_sequence[*num_steps].func = DPP_SET_CURSOR_ATTRIBUTES; + (*num_steps)++; + + if (dc->ctx->dmub_srv) { + block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_idx = + current_pipe->pipe_idx; + block_sequence[*num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU; + (*num_steps)++; + } + + block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.dc = dc; + block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL; + (*num_steps)++; + + if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) { + block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc; + block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE; + (*num_steps)++; + } + } + + /* Unlock cursor attributes after all pipes have been programmed */ + if (cursor_pipe_to_program) { + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { + block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc; + block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx = + cursor_pipe_to_program; + block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE; + (*num_steps)++; + } else { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program; + block_sequence[*num_steps].params.cursor_lock_params.lock = false; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + + if (cursor_pipe_to_program->next_odm_pipe) { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = + cursor_pipe_to_program->next_odm_pipe; + block_sequence[*num_steps].params.cursor_lock_params.lock = false; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + } + } + } + } + + /* Cursor position updates */ + if (dc->hwss.set_cursor_position && stream->update_flags.bits.cursor_pos) { + struct pipe_ctx *cursor_pipe_to_program = NULL; + + for (i = 0; i < MAX_PIPES; i++) { + current_pipe = &context->res_ctx.pipe_ctx[i]; + + if (current_pipe->stream != stream || + (!current_pipe->plane_res.mi && !current_pipe->plane_res.hubp) || + !current_pipe->plane_state || + (!current_pipe->plane_res.xfm && !current_pipe->plane_res.dpp) || + (!current_pipe->plane_res.ipp && !current_pipe->plane_res.dpp)) + continue; + + if (!cursor_pipe_to_program) { + cursor_pipe_to_program = current_pipe; + + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { + block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc; + block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE; + (*num_steps)++; + } else { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe; + block_sequence[*num_steps].params.cursor_lock_params.lock = true; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + } + } + + block_sequence[*num_steps].params.set_cursor_position_params.dc = dc; + block_sequence[*num_steps].params.set_cursor_position_params.pipe_ctx = current_pipe; + block_sequence[*num_steps].func = SET_CURSOR_POSITION; + (*num_steps)++; + + if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) { + block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc; + block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE; + (*num_steps)++; + } + + if (dc->ctx->dmub_srv) { + block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = + current_pipe; + block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_idx = + current_pipe->pipe_idx; + block_sequence[*num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU; + (*num_steps)++; + } + } + + /* Unlock cursor position after all pipes have been programmed */ + if (cursor_pipe_to_program) { + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { + block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc; + block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx = + cursor_pipe_to_program; + block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE; + (*num_steps)++; + } else { + block_sequence[*num_steps].params.cursor_lock_params.dc = dc; + block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program; + block_sequence[*num_steps].params.cursor_lock_params.lock = false; + block_sequence[*num_steps].func = HWSS_CURSOR_LOCK; + (*num_steps)++; + } + } + } + current_pipe = pipe_ctx; while (current_pipe) { + if (current_pipe->stream->update_flags.bits.dither) { + resource_build_bit_depth_reduction_params(current_pipe->stream, ¤t_pipe->stream->bit_depth_params); + block_sequence[*num_steps].params.opp_program_fmt_params.opp = current_pipe->stream_res.opp; + block_sequence[*num_steps].params.opp_program_fmt_params.fmt_bit_depth = ¤t_pipe->stream->bit_depth_params; + block_sequence[*num_steps].params.opp_program_fmt_params.clamping = ¤t_pipe->stream->clamping; + block_sequence[*num_steps].func = OPP_PROGRAM_FMT; + (*num_steps)++; + } + current_mpc_pipe = current_pipe; while (current_mpc_pipe) { if (current_mpc_pipe->plane_state) { @@ -831,7 +1065,9 @@ void hwss_build_fast_sequence(struct dc *dc, (*num_steps)++; } - if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) { + if (dc->hwss.program_gamut_remap && + (current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change || + current_mpc_pipe->stream->update_flags.bits.gamut_remap)) { block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe; block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP; (*num_steps)++; @@ -856,6 +1092,16 @@ void hwss_build_fast_sequence(struct dc *dc, block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST; (*num_steps)++; } + + if (current_mpc_pipe->plane_res.dpp && + current_mpc_pipe->plane_res.dpp->funcs->set_cursor_matrix && + current_mpc_pipe->plane_state->update_flags.bits.cursor_csc_color_matrix_change) { + block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.dpp = current_mpc_pipe->plane_res.dpp; + block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.color_space = current_mpc_pipe->plane_state->color_space; + block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = ¤t_mpc_pipe->plane_state->cursor_csc_color_matrix; + block_sequence[*num_steps].func = DPP_SET_CURSOR_MATRIX; + (*num_steps)++; + } } if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) { block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc; @@ -953,7 +1199,7 @@ void hwss_execute_sequence(struct dc *dc, struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], int num_steps) { - unsigned int i; + int i; union block_sequence_params *params; struct dce_hwseq *hws = dc->hwseq; @@ -989,7 +1235,22 @@ void hwss_execute_sequence(struct dc *dc, params->set_input_transfer_func_params.plane_state); break; case DPP_PROGRAM_GAMUT_REMAP: - dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx); + hwss_program_gamut_remap(params); + break; + case HUBP_ENABLE_3DLUT_FL: + hwss_hubp_enable_3dlut_fl(params); + break; + case OTG_SETUP_VERTICAL_INTERRUPT: + hwss_tg_setup_vertical_interrupt0(params); + break; + case HWSS_SETUP_PERIODIC_INTERRUPT: + hwss_setup_periodic_interrupt(dc, params); + break; + case HWSS_UPDATE_INFO_FRAME: + hwss_update_info_frame(dc, params); + break; + case HUBP_SET_DMDATA_ATTRIBUTES: + hwss_set_dmdata_attributes(params); break; case DPP_SETUP_DPP: hwss_setup_dpp(params); @@ -1311,9 +1572,30 @@ void hwss_execute_sequence(struct dc *dc, case ABORT_CURSOR_OFFLOAD_UPDATE: hwss_abort_cursor_offload_update(params); break; + case HWSS_CURSOR_LOCK: + hwss_cursor_lock(params); + break; + case HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE: + hwss_begin_cursor_offload_update(params); + break; + case HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE: + hwss_commit_cursor_offload_update(params); + break; + case HWSS_UPDATE_CURSOR_OFFLOAD_PIPE: + hwss_update_cursor_offload_pipe(params); + break; + case DC_SEND_CURSOR_INFO_TO_DMU: + hwss_send_cursor_info_to_dmu(params); + break; case SET_CURSOR_ATTRIBUTE: hwss_set_cursor_attribute(params); break; + case HUBP_SET_CURSOR_ATTRIBUTES: + hwss_hubp_set_cursor_attributes(params); + break; + case DPP_SET_CURSOR_ATTRIBUTES: + hwss_dpp_set_cursor_attributes(params); + break; case SET_CURSOR_POSITION: hwss_set_cursor_position(params); break; @@ -1329,6 +1611,57 @@ void hwss_execute_sequence(struct dc *dc, case PHANTOM_HUBP_POST_ENABLE: hwss_phantom_hubp_post_enable(params); break; + case STREAM_ENC_UPDATE_HDMI_INFO_PACKETS: + hwss_stream_enc_update_hdmi_info_packets(params); + break; + case HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM: + hwss_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(params); + break; + case HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS: + hwss_hpo_dp_stream_enc_update_dp_info_packets(params); + break; + case STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM: + hwss_stream_enc_update_dp_info_packets_sdp_line_num(params); + break; + case STREAM_ENC_UPDATE_DP_INFO_PACKETS: + hwss_stream_enc_update_dp_info_packets(params); + break; + case DSC_SET_CONFIG_SIMPLE: + hwss_dsc_set_config_simple(params); + break; + case STREAM_ENC_DP_SET_DSC_CONFIG: + hwss_stream_enc_dp_set_dsc_config(params); + break; + case HPO_DP_STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET: + hwss_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(params); + break; + case STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET: + hwss_stream_enc_dp_set_dsc_pps_info_packet(params); + break; + case DP_TRACE_SOURCE_SEQUENCE: + hwss_dp_trace_source_sequence(params); + break; + case LINK_INCREASE_MST_PAYLOAD: + hwss_link_increase_mst_payload(params); + break; + case LINK_REDUCE_MST_PAYLOAD: + hwss_link_reduce_mst_payload(params); + break; + case DP_SET_TEST_PATTERN: + hwss_dp_set_test_pattern(params); + break; + case LINK_SET_DPMS_OFF: + hwss_link_set_dpms_off(params); + break; + case DISABLE_AUDIO_STREAM: + hwss_disable_audio_stream(dc, params); + break; + case PREPARE_BANDWIDTH: + hwss_prepare_bandwidth(dc, params); + break; + case LINK_SET_DPMS_ON: + hwss_link_set_dpms_on(params); + break; default: ASSERT(false); break; @@ -1732,6 +2065,21 @@ void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, } } +/* + * Helper function to add OTG setup vertical interrupt0 to block sequence + */ +void hwss_add_vertical_interrupt_setup(struct block_sequence_state *seq_state, + struct timing_generator *tg, uint32_t start_line, uint32_t end_line) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.start_line = start_line; + seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.end_line = end_line; + seq_state->steps[*seq_state->num_steps].func = OTG_SETUP_VERTICAL_INTERRUPT; + (*seq_state->num_steps)++; + } +} + /* * Helper function to add TG setup vertical interrupt2 to block sequence */ @@ -1947,6 +2295,16 @@ void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_sta } } +void hwss_add_hubp_enable_3dlut_fl(struct block_sequence_state *seq_state, + struct hubp *hubp) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.hubp_enable_3dlut_fl_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].func = HUBP_ENABLE_3DLUT_FL; + (*seq_state->num_steps)++; + } +} + void hwss_program_manual_trigger(union block_sequence_params *params) { struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx; @@ -2091,7 +2449,7 @@ void get_surface_tile_visual_confirm_color( switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { case DC_SW_LINEAR: /* LINEAR Surface - set border color to red */ - color->color_r_cr = color_value; + color->color_r_cr = (uint16_t)color_value; break; default: break; @@ -2180,7 +2538,7 @@ void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_con * operations to complete. It should be invoked as a pre-amble prior * to full update programming before asserting any HW locks. */ - int pipe_idx; + unsigned int pipe_idx; int opp_inst; int opp_count = dc->res_pool->res_cap->num_opp; struct hubp *hubp; @@ -2416,6 +2774,40 @@ void hwss_tg_set_vtg_params(union block_sequence_params *params) tg->funcs->set_vtg_params(tg, timing, program_fp2); } +void hwss_hubp_enable_3dlut_fl(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_enable_3dlut_fl_params.hubp; + + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); +} + +void hwss_update_info_frame(struct dc *dc, union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->update_info_frame_params.pipe_ctx; + + if (dc->hwss.update_info_frame) + dc->hwss.update_info_frame(pipe_ctx); +} + +void hwss_setup_periodic_interrupt(struct dc *dc, union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->setup_periodic_interrupt_params.pipe_ctx; + + if (dc->hwss.setup_periodic_interrupt) + dc->hwss.setup_periodic_interrupt(dc, pipe_ctx); +} + +void hwss_tg_setup_vertical_interrupt0(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_setup_vertical_interrupt0_params.tg; + uint32_t start_line = params->tg_setup_vertical_interrupt0_params.start_line; + uint32_t end_line = params->tg_setup_vertical_interrupt0_params.end_line; + + if (tg->funcs->setup_vertical_interrupt0) + tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line); +} + void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params) { struct timing_generator *tg = params->tg_setup_vertical_interrupt2_params.tg; @@ -2615,7 +3007,7 @@ void hwss_hubp_wait_flip_pending(union block_sequence_params *params) struct hubp *hubp = params->hubp_wait_flip_pending_params.hubp; unsigned int timeout_us = params->hubp_wait_flip_pending_params.timeout_us; unsigned int polling_interval_us = params->hubp_wait_flip_pending_params.polling_interval_us; - int j = 0; + unsigned int j = 0; for (j = 0; j < timeout_us / polling_interval_us && hubp->funcs->hubp_is_flip_pending(hubp); j++) @@ -2627,7 +3019,7 @@ void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params) struct timing_generator *tg = params->tg_wait_double_buffer_pending_params.tg; unsigned int timeout_us = params->tg_wait_double_buffer_pending_params.timeout_us; unsigned int polling_interval_us = params->tg_wait_double_buffer_pending_params.polling_interval_us; - int j = 0; + unsigned int j = 0; if (tg->funcs->get_optc_double_buffer_pending) { for (j = 0; j < timeout_us / polling_interval_us @@ -3113,6 +3505,51 @@ void hwss_abort_cursor_offload_update(union block_sequence_params *params) dc->hwss.abort_cursor_offload_update(dc, pipe_ctx); } +void hwss_cursor_lock(union block_sequence_params *params) +{ + struct dc *dc = params->cursor_lock_params.dc; + struct pipe_ctx *pipe_ctx = params->cursor_lock_params.pipe_ctx; + bool lock = params->cursor_lock_params.lock; + + if (dc && dc->hwss.cursor_lock) + dc->hwss.cursor_lock(dc, pipe_ctx, lock); +} + +void hwss_begin_cursor_offload_update(union block_sequence_params *params) +{ + struct dc *dc = params->begin_cursor_offload_update_params.dc; + struct pipe_ctx *pipe_ctx = params->begin_cursor_offload_update_params.pipe_ctx; + + if (dc && dc->hwss.begin_cursor_offload_update) + dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); +} + +void hwss_commit_cursor_offload_update(union block_sequence_params *params) +{ + struct dc *dc = params->commit_cursor_offload_update_params.dc; + struct pipe_ctx *pipe_ctx = params->commit_cursor_offload_update_params.pipe_ctx; + + if (dc && dc->hwss.commit_cursor_offload_update) + dc->hwss.commit_cursor_offload_update(dc, pipe_ctx); +} + +void hwss_update_cursor_offload_pipe(union block_sequence_params *params) +{ + struct dc *dc = params->update_cursor_offload_pipe_params.dc; + struct pipe_ctx *pipe_ctx = params->update_cursor_offload_pipe_params.pipe_ctx; + + if (dc && dc->hwss.update_cursor_offload_pipe) + dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx); +} + +void hwss_send_cursor_info_to_dmu(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->send_cursor_info_to_dmu_params.pipe_ctx; + int pipe_idx = params->send_cursor_info_to_dmu_params.pipe_idx; + + dc_send_update_cursor_info_to_dmu(pipe_ctx, (uint8_t)pipe_idx); +} + void hwss_set_cursor_attribute(union block_sequence_params *params) { struct dc *dc = params->set_cursor_attribute_params.dc; @@ -3122,6 +3559,24 @@ void hwss_set_cursor_attribute(union block_sequence_params *params) dc->hwss.set_cursor_attribute(pipe_ctx); } +void hwss_hubp_set_cursor_attributes(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_set_cursor_attributes_params.hubp; + const struct dc_cursor_attributes *attributes = params->hubp_set_cursor_attributes_params.attributes; + + if (hubp && hubp->funcs->set_cursor_attributes) + hubp->funcs->set_cursor_attributes(hubp, attributes); +} + +void hwss_dpp_set_cursor_attributes(union block_sequence_params *params) +{ + struct dpp *dpp = params->dpp_set_cursor_attributes_params.dpp; + struct dc_cursor_attributes *attributes = params->dpp_set_cursor_attributes_params.attributes; + + if (dpp && dpp->funcs->set_cursor_attributes) + dpp->funcs->set_cursor_attributes(dpp, attributes); +} + void hwss_set_cursor_position(union block_sequence_params *params) { struct dc *dc = params->set_cursor_position_params.dc; @@ -3140,6 +3595,14 @@ void hwss_set_cursor_sdr_white_level(union block_sequence_params *params) dc->hwss.set_cursor_sdr_white_level(pipe_ctx); } +void hwss_program_gamut_remap(union block_sequence_params *params) +{ + struct dc *dc = params->program_gamut_remap_params.pipe_ctx->stream->ctx->dc; + + if (dc && dc->hwss.program_gamut_remap) + dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx); +} + void hwss_program_output_csc(union block_sequence_params *params) { struct dc *dc = params->program_output_csc_params.dc; @@ -3169,6 +3632,198 @@ void hwss_phantom_hubp_post_enable(union block_sequence_params *params) hubp->funcs->phantom_hubp_post_enable(hubp); } +void hwss_stream_enc_update_hdmi_info_packets(union block_sequence_params *params) +{ + if (params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc && + params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets) + params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( + params->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.stream_enc, + ¶ms->stream_enc_update_hdmi_info_packets_params.pipe_ctx->stream_res.encoder_info_frame); +} + +void hwss_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params) +{ + if (params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc && + params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num) + params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num( + params->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.hpo_dp_stream_enc, + ¶ms->hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.encoder_info_frame); +} + +void hwss_hpo_dp_stream_enc_update_dp_info_packets(union block_sequence_params *params) +{ + if (params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc && + params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets) + params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( + params->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.hpo_dp_stream_enc, + ¶ms->hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.encoder_info_frame); +} + +void hwss_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params) +{ + if (params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc && + params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) + params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( + params->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.stream_enc, + ¶ms->stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx->stream_res.encoder_info_frame); +} + +void hwss_stream_enc_update_dp_info_packets(union block_sequence_params *params) +{ + if (params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc && + params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets) + params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( + params->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.stream_enc, + ¶ms->stream_enc_update_dp_info_packets_params.pipe_ctx->stream_res.encoder_info_frame); +} + +void hwss_stream_enc_dp_set_dsc_config(union block_sequence_params *params) +{ + if (params->stream_enc_dp_set_dsc_config_params.stream_enc && + params->stream_enc_dp_set_dsc_config_params.stream_enc->funcs->dp_set_dsc_config) { + enum optc_dsc_mode dsc_mode = OPTC_DSC_DISABLED; + uint32_t dsc_bytes_per_pixel = 0; + uint32_t dsc_slice_width = 0; + const struct dsc_optc_config *dsc_optc_cfg = params->stream_enc_dp_set_dsc_config_params.dsc_optc_cfg; + + if (dsc_optc_cfg) { + dsc_mode = dsc_optc_cfg->is_pixel_format_444 ? + OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; + dsc_bytes_per_pixel = dsc_optc_cfg->bytes_per_pixel; + dsc_slice_width = dsc_optc_cfg->slice_width; + } + + params->stream_enc_dp_set_dsc_config_params.stream_enc->funcs->dp_set_dsc_config( + params->stream_enc_dp_set_dsc_config_params.stream_enc, + dsc_mode, dsc_bytes_per_pixel, dsc_slice_width); + } +} + +void hwss_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params) +{ + if (params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc && + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet) + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc, + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update, + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps, + params->hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream); +} + +void hwss_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params) +{ + if (params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc && + params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc->funcs->dp_set_dsc_pps_info_packet) + params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc->funcs->dp_set_dsc_pps_info_packet( + params->stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc, + params->stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update, + params->stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps, + params->stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream); +} + +void hwss_set_dmdata_attributes(union block_sequence_params *params) +{ + struct hubp *hubp = params->set_dmdata_attributes_params.hubp; + + if (!hubp || !hubp->funcs->dmdata_set_attributes) + return; + + hubp->funcs->dmdata_set_attributes(hubp, + ¶ms->set_dmdata_attributes_params.attr); +} + +void hwss_dp_trace_source_sequence(union block_sequence_params *params) +{ + struct dc_link *link = params->dp_trace_source_sequence_params.link; + enum dpcd_source_sequence source = params->dp_trace_source_sequence_params.source; + + if (link && link->dc && link->dc->link_srv && link->dc->link_srv->dp_trace_source_sequence) + link->dc->link_srv->dp_trace_source_sequence(link, source); +} + +void hwss_link_increase_mst_payload(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->link_increase_mst_payload_params.pipe_ctx; + uint32_t mst_stream_bw = params->link_increase_mst_payload_params.mst_stream_bw; + + if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && + pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && + pipe_ctx->stream->link->dc->link_srv->increase_mst_payload) + pipe_ctx->stream->link->dc->link_srv->increase_mst_payload(pipe_ctx, mst_stream_bw); +} + +void hwss_link_reduce_mst_payload(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->link_reduce_mst_payload_params.pipe_ctx; + uint32_t mst_stream_bw = params->link_reduce_mst_payload_params.mst_stream_bw; + + if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && + pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && + pipe_ctx->stream->link->dc->link_srv->reduce_mst_payload) + pipe_ctx->stream->link->dc->link_srv->reduce_mst_payload(pipe_ctx, mst_stream_bw); +} + +void hwss_dp_set_test_pattern(union block_sequence_params *params) +{ + struct dc_link *link = params->dp_set_test_pattern_params.link; + enum dp_test_pattern test_pattern = params->dp_set_test_pattern_params.test_pattern; + enum dp_test_pattern_color_space test_pattern_color_space = + params->dp_set_test_pattern_params.test_pattern_color_space; + const struct link_training_settings *p_link_settings = + params->dp_set_test_pattern_params.p_link_settings; + const unsigned char *p_custom_pattern = params->dp_set_test_pattern_params.p_custom_pattern; + unsigned int cust_pattern_size = params->dp_set_test_pattern_params.cust_pattern_size; + + if (link && link->dc && link->dc->link_srv && link->dc->link_srv->dp_set_test_pattern) + link->dc->link_srv->dp_set_test_pattern(link, test_pattern, test_pattern_color_space, + p_link_settings, p_custom_pattern, cust_pattern_size); +} + +void hwss_link_set_dpms_off(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->link_set_dpms_off_params.pipe_ctx; + + if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && + pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && + pipe_ctx->stream->link->dc->link_srv->set_dpms_off) + pipe_ctx->stream->link->dc->link_srv->set_dpms_off(pipe_ctx); +} + +void hwss_disable_audio_stream(struct dc *dc, union block_sequence_params *params) +{ + if (dc->hwss.disable_audio_stream) + dc->hwss.disable_audio_stream( + params->disable_audio_stream_params.pipe_ctx); +} + +void hwss_prepare_bandwidth(struct dc *dc, union block_sequence_params *params) +{ + if (dc && dc->hwss.prepare_bandwidth) + dc->hwss.prepare_bandwidth(dc, + params->prepare_bandwidth_params.context); +} + +void hwss_link_set_dpms_on(union block_sequence_params *params) +{ + struct dc_state *state = params->link_set_dpms_on_params.state; + struct pipe_ctx *pipe_ctx = params->link_set_dpms_on_params.pipe_ctx; + + if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link && + pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv && + pipe_ctx->stream->link->dc->link_srv->set_dpms_on) + pipe_ctx->stream->link->dc->link_srv->set_dpms_on(state, pipe_ctx); +} + +void hwss_dsc_set_config_simple(union block_sequence_params *params) +{ + struct display_stream_compressor *dsc = params->dsc_set_config_simple_params.dsc; + struct dsc_config *dsc_cfg = ¶ms->dsc_set_config_simple_params.dsc_cfg; + struct dsc_optc_config *dsc_optc_cfg = ¶ms->dsc_set_config_simple_params.dsc_optc_cfg; + + if (dsc && dsc->funcs && dsc->funcs->dsc_set_config) + dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); +} + void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state, struct dccg *dccg, int inst, int num_slices_h) { @@ -4009,6 +4664,30 @@ void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, } } +void hwss_add_hubp_set_cursor_attributes(struct block_sequence_state *seq_state, + struct hubp *hubp, + const struct dc_cursor_attributes *attributes) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_CURSOR_ATTRIBUTES; + seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.attributes = attributes; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dpp_set_cursor_attributes(struct block_sequence_state *seq_state, + struct dpp *dpp, + struct dc_cursor_attributes *attributes) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_ATTRIBUTES; + seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.dpp = dpp; + seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.attributes = attributes; + (*seq_state->num_steps)++; + } +} + void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, struct dc *dc, struct pipe_ctx *pipe_ctx) @@ -4109,6 +4788,313 @@ void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, } } +void hwss_add_begin_cursor_offload_update(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE; + seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_cursor_lock(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool lock) +{ + /* cursor lock is per MPCC tree, so only need to lock one pipe per stream */ + if (!pipe_ctx || pipe_ctx->top_pipe) + return; + + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HWSS_CURSOR_LOCK; + seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.lock = lock; + (*seq_state->num_steps)++; + } +} + +void hwss_add_send_update_cursor_info_to_dmu(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + int index) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU; + seq_state->steps[*seq_state->num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.send_cursor_info_to_dmu_params.pipe_idx = index; + (*seq_state->num_steps)++; + } +} + +void hwss_add_update_cursor_offload_pipe(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE; + seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_commit_cursor_offload_update(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE; + seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_stream_enc_update_hdmi_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_HDMI_INFO_PACKETS; + seq_state->steps[*seq_state->num_steps].params.stream_enc_update_hdmi_info_packets_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hpo_dp_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_update_dp_info_packets_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM; + seq_state->steps[*seq_state->num_steps].params.stream_enc_update_dp_info_packets_sdp_line_num_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_UPDATE_DP_INFO_PACKETS; + seq_state->steps[*seq_state->num_steps].params.stream_enc_update_dp_info_packets_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dsc_set_config(struct block_sequence_state *seq_state, + struct display_stream_compressor *dsc, + const struct dsc_config *dsc_cfg, + const struct dsc_optc_config *dsc_optc_cfg) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DSC_SET_CONFIG_SIMPLE; + seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc = dsc; + seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc_cfg = *dsc_cfg; + seq_state->steps[*seq_state->num_steps].params.dsc_set_config_simple_params.dsc_optc_cfg = *dsc_optc_cfg; + (*seq_state->num_steps)++; + } +} + +void hwss_add_stream_enc_dp_set_dsc_config(struct block_sequence_state *seq_state, + struct stream_encoder *stream_enc, + const struct dsc_optc_config *dsc_optc_cfg) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_DP_SET_DSC_CONFIG; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_config_params.stream_enc = stream_enc; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, + struct hpo_dp_stream_encoder *hpo_dp_stream_enc, + bool immediate_update, + uint8_t *dsc_packed_pps, + bool pps_sdp_stream) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HPO_DP_STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.hpo_dp_stream_enc = hpo_dp_stream_enc; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update = immediate_update; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps = dsc_packed_pps; + seq_state->steps[*seq_state->num_steps].params.hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream = pps_sdp_stream; + (*seq_state->num_steps)++; + } +} + +void hwss_add_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, + struct stream_encoder *stream_enc, + bool immediate_update, + uint8_t *dsc_packed_pps, + bool pps_sdp_stream) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.stream_enc = stream_enc; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.immediate_update = immediate_update; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.dsc_packed_pps = dsc_packed_pps; + seq_state->steps[*seq_state->num_steps].params.stream_enc_dp_set_dsc_pps_info_packet_params.pps_sdp_stream = pps_sdp_stream; + (*seq_state->num_steps)++; + } +} + +void hwss_add_setup_periodic_interrupt(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HWSS_SETUP_PERIODIC_INTERRUPT; + seq_state->steps[*seq_state->num_steps].params.setup_periodic_interrupt_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dp_trace_source_sequence(struct block_sequence_state *seq_state, + struct dc_link *link, + enum dpcd_source_sequence source) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DP_TRACE_SOURCE_SEQUENCE; + seq_state->steps[*seq_state->num_steps].params.dp_trace_source_sequence_params.link = link; + seq_state->steps[*seq_state->num_steps].params.dp_trace_source_sequence_params.source = source; + (*seq_state->num_steps)++; + } +} + +void hwss_add_set_dmdata_attributes(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + struct dc_dmdata_attributes *attr = + &seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.attr; + + memset(attr, 0, sizeof(*attr)); + attr->dmdata_mode = DMDATA_HW_MODE; + attr->dmdata_size = dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; + attr->address.quad_part = pipe_ctx->stream->dmdata_address.quad_part; + attr->dmdata_repeat = 1; /* always repeat */ + attr->dmdata_updated = 1; + + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_DMDATA_ATTRIBUTES; + seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.hubp = + pipe_ctx->plane_res.hubp; + (*seq_state->num_steps)++; + } +} + +void hwss_add_link_increase_mst_payload(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + uint32_t mst_stream_bw) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = LINK_INCREASE_MST_PAYLOAD; + seq_state->steps[*seq_state->num_steps].params.link_increase_mst_payload_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.link_increase_mst_payload_params.mst_stream_bw = mst_stream_bw; + (*seq_state->num_steps)++; + } +} + +void hwss_add_link_reduce_mst_payload(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + uint32_t mst_stream_bw) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = LINK_REDUCE_MST_PAYLOAD; + seq_state->steps[*seq_state->num_steps].params.link_reduce_mst_payload_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.link_reduce_mst_payload_params.mst_stream_bw = mst_stream_bw; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dp_set_test_pattern(struct block_sequence_state *seq_state, + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DP_SET_TEST_PATTERN; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.link = link; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.test_pattern = test_pattern; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.test_pattern_color_space = test_pattern_color_space; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.p_link_settings = p_link_settings; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.p_custom_pattern = p_custom_pattern; + seq_state->steps[*seq_state->num_steps].params.dp_set_test_pattern_params.cust_pattern_size = cust_pattern_size; + (*seq_state->num_steps)++; + } +} + +void hwss_add_link_set_dpms_off(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = LINK_SET_DPMS_OFF; + seq_state->steps[*seq_state->num_steps].params.link_set_dpms_off_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_disable_audio_stream(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DISABLE_AUDIO_STREAM; + seq_state->steps[*seq_state->num_steps].params.disable_audio_stream_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_prepare_bandwidth(struct block_sequence_state *seq_state, + struct dc *dc, + struct dc_state *context) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = PREPARE_BANDWIDTH; + seq_state->steps[*seq_state->num_steps].params.prepare_bandwidth_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.prepare_bandwidth_params.context = context; + (*seq_state->num_steps)++; + } +} + +void hwss_add_link_set_dpms_on(struct block_sequence_state *seq_state, + struct dc_state *state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = LINK_SET_DPMS_ON; + seq_state->steps[*seq_state->num_steps].params.link_set_dpms_on_params.state = state; + seq_state->steps[*seq_state->num_steps].params.link_set_dpms_on_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color *color) { @@ -4124,8 +5110,8 @@ void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color * if (max_refresh_rate - min_refresh_rate) scaling_factor = MAX_TG_COLOR_VALUE * (refresh_rate - min_refresh_rate) / (max_refresh_rate - min_refresh_rate); - pipe_ctx->visual_confirm_color.color_r_cr = color_value; - pipe_ctx->visual_confirm_color.color_g_y = scaling_factor; - pipe_ctx->visual_confirm_color.color_b_cb = color_value; + pipe_ctx->visual_confirm_color.color_r_cr = (uint16_t)color_value; + pipe_ctx->visual_confirm_color.color_g_y = (uint16_t)scaling_factor; + pipe_ctx->visual_confirm_color.color_b_cb = (uint16_t)color_value; } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c index deb23d20bca6..afdf9f8b16d7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c @@ -33,7 +33,7 @@ static bool is_dig_link_enc_stream(struct dc_stream_state *stream) { bool is_dig_stream = false; struct link_encoder *link_enc = NULL; - int i; + unsigned int i; /* Loop over created link encoder objects. */ if (stream) { @@ -161,7 +161,7 @@ static enum engine_id find_first_avail_link_enc( enum engine_id eng_id_requested) { enum engine_id eng_id = ENGINE_ID_UNKNOWN; - int i; + unsigned int i; if (eng_id_requested != ENGINE_ID_UNKNOWN) { @@ -248,7 +248,7 @@ static struct link_encoder *get_link_enc_used_by_link( /* Clear all link encoder assignments. */ static void clear_enc_assignments(const struct dc *dc, struct dc_state *state) { - int i; + unsigned int i; for (i = 0; i < MAX_PIPES; i++) { state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid = false; @@ -523,7 +523,7 @@ struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc) { struct link_encoder *link_enc = NULL; enum engine_id encs_assigned[MAX_LINK_ENCODERS]; - int i; + unsigned int i; for (i = 0; i < MAX_LINK_ENCODERS; i++) encs_assigned[i] = ENGINE_ID_UNKNOWN; @@ -624,7 +624,8 @@ bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state) bool valid_uniqueness = true; bool valid_avail = true; bool valid_streams = true; - int i, j; + int i; + unsigned int j; uint8_t valid_count = 0; uint8_t dig_stream_count = 0; int eng_ids_per_ep_id[MAX_PIPES] = {0}; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index f4e99ca7918f..5ac5ad86bd01 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@ -282,7 +282,7 @@ unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link) struct dc_sink *dc_link_add_remote_sink( struct dc_link *link, const uint8_t *edid, - int len, + unsigned int len, struct dc_sink_init_data *init_data) { return link->dc->link_srv->add_remote_sink(link, edid, len, init_data); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 05991a10f8bf..f57e9d85563e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -286,34 +286,34 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, #endif case DCE_VERSION_8_0: res_pool = dce80_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; case DCE_VERSION_8_1: res_pool = dce81_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; case DCE_VERSION_8_3: res_pool = dce83_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; case DCE_VERSION_10_0: res_pool = dce100_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; case DCE_VERSION_11_0: res_pool = dce110_create_resource_pool( - init_data->num_virtual_links, dc, + (uint8_t)init_data->num_virtual_links, dc, init_data->asic_id); break; case DCE_VERSION_11_2: case DCE_VERSION_11_22: res_pool = dce112_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; case DCE_VERSION_12_0: case DCE_VERSION_12_1: res_pool = dce120_create_resource_pool( - init_data->num_virtual_links, dc); + (uint8_t)init_data->num_virtual_links, dc); break; #if defined(CONFIG_DRM_AMD_DC_FP) @@ -446,7 +446,7 @@ bool resource_construct( { struct dc_context *ctx = dc->ctx; const struct resource_caps *caps = pool->res_cap; - int i; + unsigned int i; unsigned int num_audio = caps->num_audio; struct resource_straps straps = {0}; @@ -463,7 +463,7 @@ bool resource_construct( * PORT_CONNECTIVITY == 1 (as instructed by HW team). */ update_num_audio(&straps, &num_audio, &pool->audio_support); - for (i = 0; i < caps->num_audio; i++) { + for (i = 0; i < (unsigned int)caps->num_audio; i++) { struct audio *aud = create_funcs->create_audio(ctx, i); if (aud == NULL) { @@ -481,14 +481,14 @@ bool resource_construct( pool->stream_enc_count = 0; if (create_funcs->create_stream_encoder) { - for (i = 0; i < caps->num_stream_encoder; i++) { + for (i = 0; i < (unsigned int)caps->num_stream_encoder; i++) { pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); if (pool->stream_enc[i] == NULL) DC_ERR("DC: failed to create stream_encoder!\n"); pool->stream_enc_count++; } - for (i = 0; i < caps->num_analog_stream_encoder; i++) { + for (i = 0; i < (unsigned int)caps->num_analog_stream_encoder; i++) { pool->stream_enc[caps->num_stream_encoder + i] = create_funcs->create_stream_encoder(ENGINE_ID_DACA + i, ctx); if (pool->stream_enc[caps->num_stream_encoder + i] == NULL) @@ -499,7 +499,7 @@ bool resource_construct( pool->hpo_dp_stream_enc_count = 0; if (create_funcs->create_hpo_dp_stream_encoder) { - for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) { + for (i = 0; i < (unsigned int)caps->num_hpo_dp_stream_encoder; i++) { pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx); if (pool->hpo_dp_stream_enc[i] == NULL) DC_ERR("DC: failed to create HPO DP stream encoder!\n"); @@ -510,15 +510,15 @@ bool resource_construct( pool->hpo_dp_link_enc_count = 0; if (create_funcs->create_hpo_dp_link_encoder) { - for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) { - pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx); + for (i = 0; i < (unsigned int)caps->num_hpo_dp_link_encoder; i++) { + pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder((uint8_t)i, ctx); if (pool->hpo_dp_link_enc[i] == NULL) DC_ERR("DC: failed to create HPO DP link encoder!\n"); pool->hpo_dp_link_enc_count++; } } - for (i = 0; i < caps->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)caps->num_mpc_3dlut; i++) { pool->mpc_lut[i] = dc_create_3dlut_func(); if (pool->mpc_lut[i] == NULL) DC_ERR("DC: failed to create MPC 3dlut!\n"); @@ -551,11 +551,11 @@ static int find_matching_clock_source( struct clock_source *clock_source) { - int i; + unsigned int i; for (i = 0; i < pool->clk_src_count; i++) { if (pool->clock_sources[i] == clock_source) - return i; + return (int)i; } return -1; } @@ -610,7 +610,7 @@ bool resource_are_vblanks_synchronizable( { uint32_t base60_refresh_rates[] = {10, 20, 5}; uint8_t i; - uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates); + uint8_t rr_count = (uint8_t)ARRAY_SIZE(base60_refresh_rates); uint64_t frame_time_diff; if (stream1->ctx->dc->config.vblank_alignment_dto_params && @@ -982,7 +982,7 @@ static struct rect calculate_mpc_slice_in_timing_active( } static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx, - int *base_offset, int *dpp_offset) + unsigned int *base_offset, unsigned int *dpp_offset) { struct dc *dc = pipe_ctx->stream->ctx->dc; *base_offset = 0; @@ -1004,7 +1004,7 @@ static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx static void reverse_adjust_recout_for_visual_confirm(struct rect *recout, struct pipe_ctx *pipe_ctx) { - int dpp_offset, base_offset; + unsigned int dpp_offset, base_offset; calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset, &dpp_offset); @@ -1015,7 +1015,7 @@ static void reverse_adjust_recout_for_visual_confirm(struct rect *recout, static void adjust_recout_for_visual_confirm(struct rect *recout, struct pipe_ctx *pipe_ctx) { - int dpp_offset, base_offset; + unsigned int dpp_offset, base_offset; calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset, &dpp_offset); @@ -1692,7 +1692,7 @@ bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) struct pipe_ctx *test_pipe, *split_pipe; struct rect r1 = pipe_ctx->plane_res.scl_data.recout; int r1_right, r1_bottom; - int cur_layer = pipe_ctx->plane_state->layer_index; + unsigned int cur_layer = pipe_ctx->plane_state->layer_index; reverse_adjust_recout_for_visual_confirm(&r1, pipe_ctx); r1_right = r1.x + r1.width; @@ -1801,7 +1801,7 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy( int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; } } @@ -1813,7 +1813,7 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy( for (i = pool->pipe_count - 1; i >= 0; i--) { if (res_ctx->pipe_ctx[i].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[i]; - secondary_pipe->pipe_idx = i; + secondary_pipe->pipe_idx = (uint8_t)i; break; } } @@ -1876,7 +1876,7 @@ int recource_find_free_pipe_not_used_in_cur_res_ctx( { int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; const struct pipe_ctx *new_pipe, *cur_pipe; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { cur_pipe = &cur_res_ctx->pipe_ctx[i]; @@ -1899,7 +1899,7 @@ int recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx( { int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; const struct pipe_ctx *new_pipe, *cur_pipe; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { cur_pipe = &cur_res_ctx->pipe_ctx[i]; @@ -1922,7 +1922,7 @@ int resource_find_free_pipe_used_as_cur_sec_dpp( { int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; const struct pipe_ctx *new_pipe, *cur_pipe; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { cur_pipe = &cur_res_ctx->pipe_ctx[i]; @@ -1946,7 +1946,7 @@ int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine( { int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; const struct pipe_ctx *new_pipe, *cur_pipe; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { cur_pipe = &cur_res_ctx->pipe_ctx[i]; @@ -1969,7 +1969,7 @@ int resource_find_any_free_pipe(struct resource_context *new_res_ctx, { int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; const struct pipe_ctx *new_pipe; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { new_pipe = &new_res_ctx->pipe_ctx[i]; @@ -2564,7 +2564,7 @@ static bool update_pipe_params_after_odm_slice_count_change( struct dc_state *context, const struct resource_pool *pool) { - int i; + unsigned int i; struct pipe_ctx *pipe; bool result = true; @@ -2587,7 +2587,7 @@ static bool update_pipe_params_after_mpc_slice_count_change( struct dc_state *context, const struct resource_pool *pool) { - int i; + unsigned int i; struct pipe_ctx *pipe; bool result = true; @@ -2604,7 +2604,7 @@ static int acquire_first_split_pipe( const struct resource_pool *pool, struct dc_stream_state *stream) { - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; @@ -2624,11 +2624,11 @@ static int acquire_first_split_pipe( split_pipe->plane_res.ipp = pool->ipps[i]; split_pipe->plane_res.dpp = pool->dpps[i]; split_pipe->stream_res.opp = pool->opps[i]; - split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; - split_pipe->pipe_idx = i; + split_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[i]->inst; + split_pipe->pipe_idx = (uint8_t)i; split_pipe->stream = stream; - return i; + return (int)i; } } return FREE_PIPE_INDEX_NOT_FOUND; @@ -2640,7 +2640,7 @@ static void update_stream_engine_usage( struct stream_encoder *stream_enc, bool acquired) { - int i; + unsigned int i; for (i = 0; i < pool->stream_enc_count; i++) { if (pool->stream_enc[i] == stream_enc) @@ -2654,7 +2654,7 @@ static void update_hpo_dp_stream_engine_usage( struct hpo_dp_stream_encoder *hpo_dp_stream_enc, bool acquired) { - int i; + unsigned int i; for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc) @@ -2679,14 +2679,14 @@ static inline int find_acquired_hpo_dp_link_enc_for_link( static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx, const struct resource_pool *pool) { - int i; + unsigned int i; for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++) if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0) break; return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) && - i < pool->hpo_dp_link_enc_count) ? i : -1; + i < pool->hpo_dp_link_enc_count) ? (int)i : -1; } static inline void acquire_hpo_dp_link_enc( @@ -2773,9 +2773,10 @@ static inline int find_fixed_dio_link_enc(const struct dc_link *link) static inline int find_free_dio_link_enc(const struct resource_context *res_ctx, const struct dc_link *link, const struct resource_pool *pool, struct dc_stream_state *stream) { - int i, j = -1; + unsigned int i; + int j = -1; int stream_enc_inst = -1; - int enc_count = pool->dig_link_enc_count; + unsigned int enc_count = pool->dig_link_enc_count; /* Find stream encoder instance for the stream */ if (stream) { @@ -2931,7 +2932,7 @@ static void remove_dio_link_enc_from_ctx(struct resource_context *res_ctx, static int get_num_of_free_pipes(const struct resource_pool *pool, const struct dc_state *context) { - int i; + unsigned int i; int count = 0; for (i = 0; i < pool->pipe_count; i++) @@ -3608,7 +3609,7 @@ void update_audio_usage( struct audio *audio, bool acquired) { - int i; + unsigned int i; for (i = 0; i < pool->audio_count; i++) { if (pool->audios[i] == audio) res_ctx->is_audio_acquired[i] = acquired; @@ -3621,7 +3622,7 @@ static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for struct dc_stream_state *stream) { (void)stream; - int i; + unsigned int i; for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] && @@ -3804,7 +3805,7 @@ static int acquire_resource_from_hw_enabled_state( pipe_ctx->stream_res.opp = pool->opps[id_src[i]]; if (pool->dpps[id_src[i]]) { - pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst; + pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[id_src[i]]->inst; if (pool->mpc->funcs->read_mpcc_state) { struct mpcc_state s = {0}; @@ -3823,7 +3824,7 @@ static int acquire_resource_from_hw_enabled_state( pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; } } - pipe_ctx->pipe_idx = id_src[i]; + pipe_ctx->pipe_idx = (uint8_t)id_src[i]; if (id_src[i] >= pool->timing_generator_count) { id_src[i] = pool->timing_generator_count - 1; @@ -3939,7 +3940,7 @@ static bool acquire_otg_master_pipe_for_stream( if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) { pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx]; memset(pipe_ctx, 0, sizeof(*pipe_ctx)); - pipe_ctx->pipe_idx = pipe_idx; + pipe_ctx->pipe_idx = (uint8_t)pipe_idx; pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx]; pipe_ctx->plane_res.mi = pool->mis[pipe_idx]; pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx]; @@ -3948,9 +3949,9 @@ static bool acquire_otg_master_pipe_for_stream( pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx]; pipe_ctx->stream_res.opp = pool->opps[pipe_idx]; if (pool->dpps[pipe_idx]) - pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; + pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; - if (pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) { + if ((unsigned int)pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) { int tg_inst = pool->timing_generator_count - 1; pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; @@ -4102,9 +4103,9 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) static bool planes_changed_for_existing_stream(struct dc_state *context, struct dc_stream_state *stream, const struct dc_validation_set set[], - int set_count) + unsigned int set_count) { - int i, j; + unsigned int i, j; struct dc_stream_status *stream_status = NULL; for (i = 0; i < context->stream_count; i++) { @@ -4140,10 +4141,10 @@ static bool add_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, const struct dc_validation_set set[], - int set_count, + unsigned int set_count, struct dc_state *state) { - int i, j; + unsigned int i, j; for (i = 0; i < set_count; i++) if (set[i].stream == stream) @@ -4181,7 +4182,7 @@ static bool add_all_planes_for_stream( */ enum dc_status dc_validate_with_context(struct dc *dc, const struct dc_validation_set set[], - int set_count, + unsigned int set_count, struct dc_state *context, enum dc_validate_mode validate_mode) { @@ -4194,7 +4195,8 @@ enum dc_status dc_validate_with_context(struct dc *dc, int del_streams_count = 0; int add_streams_count = 0; bool found = false; - int i, j, k; + int i, j; + unsigned int k; DC_LOGGER_INIT(dc->ctx->logger); @@ -4421,7 +4423,8 @@ enum dc_status dc_validate_global_state( enum dc_validate_mode validate_mode) { enum dc_status result = DC_ERROR_UNEXPECTED; - int i, j; + int i; + unsigned int j; if (!new_ctx) return DC_ERROR_UNEXPECTED; @@ -4497,7 +4500,7 @@ static void patch_gamut_packet_checksum( for (i = 0; i <= gamut_packet->sb[1]; i++) chk_sum += ptr[i]; - gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); + gamut_packet->sb[2] = (uint8_t)(0x100 - chk_sum); } } @@ -4562,7 +4565,7 @@ static void set_avi_info_frame( /* Y0_Y1_Y2 : The pixel encoding */ /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ - hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding; + hdmi_info.bits.Y0_Y1_Y2 = (uint8_t)pixel_encoding; /* A0 = 1 Active Format Information valid */ hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID; @@ -4692,7 +4695,7 @@ static void set_avi_info_frame( } } /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/ - hdmi_info.bits.VIC0_VIC7 = vic; + hdmi_info.bits.VIC0_VIC7 = (uint8_t)vic; if (vic >= 128) hdmi_info.bits.header.version = 3; /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1), @@ -4710,7 +4713,7 @@ static void set_avi_info_frame( hdmi_info.bits.FR0_FR3 = fr_ind & 0xF; hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1; - hdmi_info.bits.RID0_RID5 = rid; + hdmi_info.bits.RID0_RID5 = (uint8_t)rid; } /* pixel repetition @@ -4723,11 +4726,11 @@ static void set_avi_info_frame( * barBottom: Line Number of Start of Bottom Bar. * barLeft: Pixel Number of End of Left Bar. * barRight: Pixel Number of Start of Right Bar. */ - hdmi_info.bits.bar_top = stream->timing.v_border_top; - hdmi_info.bits.bar_bottom = (stream->timing.v_total + hdmi_info.bits.bar_top = (uint16_t)stream->timing.v_border_top; + hdmi_info.bits.bar_bottom = (uint16_t)(stream->timing.v_total - stream->timing.v_border_bottom + 1); - hdmi_info.bits.bar_left = stream->timing.h_border_left; - hdmi_info.bits.bar_right = (stream->timing.h_total + hdmi_info.bits.bar_left = (uint16_t)stream->timing.h_border_left; + hdmi_info.bits.bar_right = (uint16_t)(stream->timing.h_total - stream->timing.h_border_right + 1); /* Additional Colorimetry Extension @@ -4746,7 +4749,7 @@ static void set_avi_info_frame( *check_sum += hdmi_info.packet_raw_data.sb[byte_index]; /* one byte complement */ - *check_sum = (uint8_t) (0x100 - *check_sum); + *check_sum = (uint8_t)(0x100 - *check_sum); /* Store in hw_path_mode */ info_packet->hb0 = hdmi_info.packet_raw_data.hb0; @@ -4880,7 +4883,7 @@ struct clock_source *dc_resource_find_first_free_pll( struct resource_context *res_ctx, const struct resource_pool *pool) { - int i; + unsigned int i; for (i = 0; i < pool->clk_src_count; ++i) { if (res_ctx->clock_source_ref_count[i] == 0) @@ -5369,7 +5372,7 @@ bool get_temp_dp_link_res(struct dc_link *link, void reset_syncd_pipes_from_disabled_pipes(struct dc *dc, struct dc_state *context) { - int i, j; + uint8_t i, j; struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd; /* If pipe backend is reset, need to reset pipe syncd status */ @@ -5398,7 +5401,7 @@ void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc, struct dc_state *context, uint8_t disabled_master_pipe_idx) { - int i; + unsigned int i; struct pipe_ctx *pipe_ctx, *pipe_ctx_check; pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx]; @@ -5432,7 +5435,7 @@ void reset_sync_context_for_pipe(const struct dc *dc, struct dc_state *context, uint8_t pipe_idx) { - int i; + uint8_t i; struct pipe_ctx *pipe_ctx_reset; /* reset the otg sync context for the pipe and its slave pipes if any */ @@ -5448,7 +5451,7 @@ void reset_sync_context_for_pipe(const struct dc *dc, uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter) { /* TODO - get transmitter to phy idx mapping from DMUB */ - uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A; + uint8_t phy_idx = (uint8_t)(transmitter - TRANSMITTER_UNIPHY_A); if (dc->ctx->dce_version == DCN_VERSION_3_1 && dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { @@ -5515,8 +5518,8 @@ const struct link_hwss *get_link_hwss(const struct dc_link *link, bool is_h_timing_divisible_by_2(struct dc_stream_state *stream) { bool divisible = false; - uint16_t h_blank_start = 0; - uint16_t h_blank_end = 0; + uint32_t h_blank_start = 0; + uint32_t h_blank_end = 0; if (stream) { h_blank_start = stream->timing.h_total - stream->timing.h_front_porch; @@ -5570,13 +5573,13 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy( sec_pipe->next_odm_pipe = sec_next; sec_pipe->prev_odm_pipe = sec_prev; - sec_pipe->pipe_idx = pipe_idx; + sec_pipe->pipe_idx = (uint8_t)pipe_idx; sec_pipe->plane_res.mi = pool->mis[pipe_idx]; sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; - sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; + sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; sec_pipe->stream_res.dsc = NULL; if (odm) { if (!sec_pipe->top_pipe) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c index 40f7aa732258..7edeed52cc32 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c @@ -218,13 +218,13 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p } if (dc->caps.dcmode_power_limits_present) { - bool status; + bool dc_power_status; DC_FP_START(); - status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source); + dc_power_status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source); DC_FP_END(); - if (!status) { + if (!dc_power_status) { dc_state_release(state); return NULL; } @@ -953,7 +953,7 @@ bool dc_state_remove_phantom_streams_and_planes( const struct dc *dc, struct dc_state *state) { - int i; + unsigned int i; bool removed_phantom = false; struct dc_stream_state *phantom_stream = NULL; @@ -978,7 +978,7 @@ void dc_state_release_phantom_streams_and_planes( unsigned int phantom_count; struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES]; struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES]; - int i; + unsigned int i; phantom_count = state->phantom_stream_count; memcpy(phantom_streams, state->phantom_streams, sizeof(struct dc_stream_state *) * MAX_PHANTOM_PIPES); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index e16de323f39c..434654e903b1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -259,11 +259,17 @@ const struct dc_stream_status *dc_stream_get_status_const( return dc_state_get_stream_status(dc->current_state, stream); } +struct dc_link *dc_stream_get_link( + const struct dc_stream_state *stream) +{ + return stream->link; +} + void program_cursor_attributes( struct dc *dc, struct dc_stream_state *stream) { - int i; + uint8_t i; struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); @@ -410,7 +416,7 @@ void program_cursor_position( struct dc *dc, struct dc_stream_state *stream) { - int i; + uint8_t i; struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); @@ -508,7 +514,7 @@ bool dc_stream_program_cursor_position( /* apply/update visual confirm */ if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR) { /* update software state */ - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -527,7 +533,7 @@ bool dc_stream_program_cursor_position( if (stream->drr_trigger_mode == DRR_TRIGGER_ON_FLIP_AND_CURSOR) { /* apply manual trigger */ - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -553,7 +559,7 @@ bool dc_stream_add_writeback(struct dc *dc, struct dc_writeback_info *wb_info) { bool isDrc = false; - int i = 0; + unsigned int i = 0; struct dwbc *dwb; if (stream == NULL) { @@ -596,7 +602,7 @@ bool dc_stream_add_writeback(struct dc *dc, if (dc->hwss.enable_writeback) { struct dc_stream_status *stream_status = dc_stream_get_status(stream); - struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; if (stream_status) dwb->otg_inst = stream_status->primary_otg_inst; } @@ -608,7 +614,7 @@ bool dc_stream_add_writeback(struct dc *dc, /* enable writeback */ if (dc->hwss.enable_writeback) { - struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; if (dwb->funcs->is_enabled(dwb)) { /* writeback pipe already enabled, only need to update */ @@ -962,7 +968,7 @@ struct dc_rmcm_3dlut *dc_stream_get_3dlut_for_stream( unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts; // see if one is allocated for this stream - for (int i = 0; i < num_rmcm; i++) { + for (unsigned int i = 0; i < num_rmcm; i++) { if (dc->res_pool->rmcm_3dlut[i].isInUse && dc->res_pool->rmcm_3dlut[i].stream == stream) return &dc->res_pool->rmcm_3dlut[i]; @@ -973,7 +979,7 @@ struct dc_rmcm_3dlut *dc_stream_get_3dlut_for_stream( return NULL; //see if there is an unused 3dlut, allocate - for (int i = 0; i < num_rmcm; i++) { + for (unsigned int i = 0; i < num_rmcm; i++) { if (!dc->res_pool->rmcm_3dlut[i].isInUse) { dc->res_pool->rmcm_3dlut[i].isInUse = true; dc->res_pool->rmcm_3dlut[i].stream = stream; @@ -996,6 +1002,7 @@ void dc_stream_release_3dlut_for_stream( if (rmcm_3dlut) { rmcm_3dlut->isInUse = false; rmcm_3dlut->stream = NULL; + rmcm_3dlut->protection_bits = 0; } } @@ -1004,9 +1011,10 @@ void dc_stream_init_rmcm_3dlut(struct dc *dc) { unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts; - for (int i = 0; i < num_rmcm; i++) { + for (unsigned int i = 0; i < num_rmcm; i++) { dc->res_pool->rmcm_3dlut[i].isInUse = false; dc->res_pool->rmcm_3dlut[i].stream = NULL; + dc->res_pool->rmcm_3dlut[i].protection_bits = 0; } } @@ -1032,14 +1040,18 @@ static int dc_stream_get_brightness_millinits_linear_interpolation (struct dc_st int refresh_hz) { long long slope = 0; + long long y_intercept = 0; + long long brightness_millinits = 0; + if (stream->lumin_data.refresh_rate_hz[index2] != stream->lumin_data.refresh_rate_hz[index1]) { slope = (stream->lumin_data.luminance_millinits[index2] - stream->lumin_data.luminance_millinits[index1]) / (stream->lumin_data.refresh_rate_hz[index2] - stream->lumin_data.refresh_rate_hz[index1]); } - int y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2]; + y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2]; + brightness_millinits = y_intercept + (long long)refresh_hz * slope; - return (y_intercept + refresh_hz * slope); + return (int)brightness_millinits; } /* @@ -1051,14 +1063,18 @@ static int dc_stream_get_refresh_hz_linear_interpolation (struct dc_stream_state int brightness_millinits) { long long slope = 1; + long long y_intercept = 0; + long long refresh_hz = 0; + if (stream->lumin_data.refresh_rate_hz[index2] != stream->lumin_data.refresh_rate_hz[index1]) { slope = (stream->lumin_data.luminance_millinits[index2] - stream->lumin_data.luminance_millinits[index1]) / (stream->lumin_data.refresh_rate_hz[index2] - stream->lumin_data.refresh_rate_hz[index1]); } - int y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2]; + y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2]; + refresh_hz = div64_s64((brightness_millinits - y_intercept), slope); - return ((int)div64_s64((brightness_millinits - y_intercept), slope)); + return (int)refresh_hz; } /* diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index a59b176d8e55..72845fc788f3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -69,13 +69,13 @@ void dc_plane_destruct(struct dc_plane_state *plane_state) uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state) { uint8_t pipe_mask = 0; - int i; + unsigned int i; for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) - pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst; + pipe_mask |= (uint8_t)(1 << pipe_ctx->plane_res.hubp->inst); } return pipe_mask; @@ -115,7 +115,7 @@ const struct dc_plane_status *dc_plane_get_status( { const struct dc_plane_status *plane_status; struct dc *dc; - int i; + unsigned int i; if (!plane_state || !plane_state->ctx || @@ -286,7 +286,7 @@ void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state, bool clear_tiling) { struct dc *dc; - int i; + unsigned int i; if (!plane_state) return; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c index d1e68dc57a2a..3743555133f6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c @@ -34,9 +34,9 @@ void vm_helper_mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos, uin vmids.vmid_usage[1] = 1 << pos; } -int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) +unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) { - int num_vmids = 0; + unsigned int num_vmids = 0; /* Call HWSS to setup HUBBUB for address config */ if (dc->hwss.init_sys_ctx) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7f55ba09b191..75f59ca927ff 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.378" +#define DC_VER "3.2.383" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC @@ -540,7 +540,7 @@ struct dc_config { bool use_default_clock_table; bool force_bios_enable_lttpr; uint8_t force_bios_fixed_vs; - int sdpif_request_limit_words_per_umc; + unsigned int sdpif_request_limit_words_per_umc; bool dc_mode_clk_limit_support; bool EnableMinDispClkODM; bool enable_auto_dpm_test_logs; @@ -944,20 +944,20 @@ struct dc_virtual_addr_space_config { }; struct dc_bounding_box_overrides { - int sr_exit_time_ns; - int sr_enter_plus_exit_time_ns; - int sr_exit_z8_time_ns; - int sr_enter_plus_exit_z8_time_ns; - int urgent_latency_ns; - int percent_of_ideal_drambw; - int dram_clock_change_latency_ns; - int dummy_clock_change_latency_ns; - int fclk_clock_change_latency_ns; + unsigned int sr_exit_time_ns; + unsigned int sr_enter_plus_exit_time_ns; + unsigned int sr_exit_z8_time_ns; + unsigned int sr_enter_plus_exit_z8_time_ns; + unsigned int urgent_latency_ns; + unsigned int percent_of_ideal_drambw; + unsigned int dram_clock_change_latency_ns; + unsigned int dummy_clock_change_latency_ns; + unsigned int fclk_clock_change_latency_ns; /* This forces a hard min on the DCFCLK we use * for DML. Unlike the debug option for forcing * DCFCLK, this override affects watermark calculations */ - int min_dcfclk_mhz; + unsigned int min_dcfclk_mhz; }; struct dc_qos_info { @@ -971,6 +971,7 @@ struct dc_qos_info { uint32_t actual_avg_latency_in_ns; uint32_t qos_avg_latency_ub_in_ns; uint32_t dcn_bandwidth_ub_in_mbps; + uint32_t qos_max_bw_budget_in_mbps; }; struct dc_state; @@ -989,7 +990,7 @@ struct link_service; struct dc_debug_options { bool disable_dsc; enum visual_confirm visual_confirm; - int visual_confirm_rect_height; + unsigned int visual_confirm_rect_height; bool sanity_checks; bool max_disp_clk; @@ -1025,23 +1026,23 @@ struct dc_debug_options { bool disable_io_clk_power_gate; bool disable_mem_power_gate; bool disable_dio_power_gate; - int dsc_min_slice_height_override; - int dsc_bpp_increment_div; + unsigned int dsc_min_slice_height_override; + unsigned int dsc_bpp_increment_div; bool disable_pplib_wm_range; enum wm_report_mode pplib_wm_report_mode; unsigned int min_disp_clk_khz; unsigned int min_dpp_clk_khz; unsigned int min_dram_clk_khz; - int sr_exit_time_dpm0_ns; - int sr_enter_plus_exit_time_dpm0_ns; - int sr_exit_time_ns; - int sr_enter_plus_exit_time_ns; - int sr_exit_z8_time_ns; - int sr_enter_plus_exit_z8_time_ns; - int urgent_latency_ns; + unsigned int sr_exit_time_dpm0_ns; + unsigned int sr_enter_plus_exit_time_dpm0_ns; + unsigned int sr_exit_time_ns; + unsigned int sr_enter_plus_exit_time_ns; + unsigned int sr_exit_z8_time_ns; + unsigned int sr_enter_plus_exit_z8_time_ns; + unsigned int urgent_latency_ns; uint32_t underflow_assert_delay_us; - int percent_of_ideal_drambw; - int dram_clock_change_latency_ns; + unsigned int percent_of_ideal_drambw; + unsigned int dram_clock_change_latency_ns; bool optimized_watermark; int always_scale; bool disable_pplib_clock_request; @@ -1066,8 +1067,8 @@ struct dc_debug_options { uint8_t seamless_boot_odm_combine; uint8_t force_odm_combine_4to1; //bit vector based on otg inst - int minimum_z8_residency_time; - int minimum_z10_residency_time; + unsigned int minimum_z8_residency_time; + unsigned int minimum_z10_residency_time; bool disable_z9_mpc; unsigned int force_fclk_khz; bool enable_tri_buf; @@ -1116,7 +1117,7 @@ struct dc_debug_options { uint8_t fec_enable_delay_in100us; bool enable_driver_sequence_debug; enum det_size crb_alloc_policy; - int crb_alloc_policy_min_disp_count; + unsigned int crb_alloc_policy_min_disp_count; bool disable_z10; bool enable_z9_disable_interface; bool psr_skip_crtc_disable; @@ -1218,6 +1219,8 @@ struct dc_debug_options { unsigned int force_vmin_threshold; bool enable_otg_frame_sync_pwa; unsigned int min_deep_sleep_dcfclk_khz; + unsigned int force_odm2to1_for_edp_pixclk_mhz; + bool enable_replay_esd_recovery; }; @@ -1290,7 +1293,7 @@ void dc_hardware_init(struct dc *dc); int dc_get_vmid_use_vector(struct dc *dc); void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); /* Returns the number of vmids supported */ -int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); +unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); void dc_init_callbacks(struct dc *dc, const struct dc_callback_init *init_params); void dc_deinit_callbacks(struct dc *dc); @@ -1407,50 +1410,15 @@ struct lut_mem_mapping { struct dc_rmcm_3dlut { bool isInUse; const struct dc_stream_state *stream; + uint8_t protection_bits; }; struct dc_3dlut { struct kref refcount; struct tetrahedral_params lut_3d; + struct fixed31_32 hdr_multiplier; union dc_3dlut_state state; }; - -/* 3DLUT DMA (Fast Load) params */ -struct dc_3dlut_dma { - struct dc_plane_address addr; - enum dc_cm_lut_swizzle swizzle; - enum dc_cm_lut_pixel_format format; - uint16_t bias; /* FP1.5.10 */ - uint16_t scale; /* FP1.5.10 */ - enum dc_cm_lut_size size; -}; - -/* color manager */ -union dc_plane_cm_flags { - unsigned int all; - struct { - unsigned int shaper_enable : 1; - unsigned int lut3d_enable : 1; - unsigned int blend_enable : 1; - /* whether legacy (lut3d_func) or DMA is valid */ - unsigned int lut3d_dma_enable : 1; - /* RMCM lut to be used instead of MCM */ - unsigned int rmcm_enable : 1; - unsigned int reserved: 27; - } bits; -}; - -struct dc_plane_cm { - struct kref refcount; - struct dc_transfer_func shaper_func; - union { - struct dc_3dlut lut3d_func; - struct dc_3dlut_dma lut3d_dma; - }; - struct dc_transfer_func blend_func; - union dc_plane_cm_flags flags; -}; - /* * This structure is filled in by dc_surface_get_status and contains * the last requested address and the currently active address so the called @@ -1485,6 +1453,7 @@ union surface_update_flags { uint32_t pixel_format_change:1; uint32_t plane_size_change:1; uint32_t gamut_remap_change:1; + uint32_t cursor_csc_color_matrix_change:1; /* Full updates */ uint32_t new_plane:1; @@ -1528,18 +1497,14 @@ struct dc_plane_state { struct fixed31_32 hdr_mult; struct colorspace_transform gamut_remap_matrix; + // TODO: No longer used, remove + struct dc_hdr_static_metadata hdr_static_ctx; + enum dc_color_space color_space; - bool lut_bank_a; - struct dc_hdr_static_metadata hdr_static_ctx; struct dc_3dlut lut3d_func; struct dc_transfer_func in_shaper_func; struct dc_transfer_func blend_tf; - enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; - bool mcm_lut1d_enable; - struct dc_cm2_func_luts mcm_luts; - enum mpcc_movable_cm_location mcm_location; - struct dc_plane_cm cm; struct dc_transfer_func *gamcor_tf; enum surface_pixel_format format; @@ -1554,7 +1519,7 @@ struct dc_plane_state { bool visible; bool flip_immediate; bool horizontal_mirror; - int layer_index; + unsigned int layer_index; union surface_update_flags update_flags; bool flip_int_enabled; @@ -1576,10 +1541,15 @@ struct dc_plane_state { bool is_statically_allocated; enum chroma_cositing cositing; + enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; + bool mcm_lut1d_enable; + struct dc_cm2_func_luts mcm_luts; + bool lut_bank_a; + enum mpcc_movable_cm_location mcm_location; struct dc_csc_transform cursor_csc_color_matrix; bool adaptive_sharpness_en; int adaptive_sharpness_policy; - int sharpness_level; + unsigned int sharpness_level; enum linear_light_scaling linear_light_scaling; unsigned int sdr_white_level_nits; struct cm_hist_control cm_hist_control; @@ -1602,7 +1572,7 @@ struct dc_plane_info { bool global_alpha; int global_alpha_value; bool input_csc_enabled; - int layer_index; + unsigned int layer_index; enum chroma_cositing cositing; }; @@ -1682,7 +1652,7 @@ struct dc_scratch_space { struct dc_link_training_overrides preferred_training_settings; struct dp_audio_test_data audio_test_data; - uint8_t ddc_hw_inst; + enum gpio_ddc_line ddc_hw_inst; uint8_t hpd_src; @@ -1891,9 +1861,21 @@ struct dc_fast_update { struct dc_transfer_func *out_transfer_func; struct dc_csc_transform *output_csc_transform; const struct dc_csc_transform *cursor_csc_color_matrix; -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) struct cm_hist_control *cm_hist_control; -#endif + /* stream-level fast updates */ + const struct colorspace_transform *gamut_remap; + const struct dc_cursor_attributes *cursor_attributes; + const struct dc_cursor_position *cursor_position; + const struct periodic_interrupt_config *periodic_interrupt; + const enum dc_dither_option *dither_option; + struct dc_info_packet *vrr_infopacket; + struct dc_info_packet *vsc_infopacket; + struct dc_info_packet *vsp_infopacket; + struct dc_info_packet *hfvsif_infopacket; + struct dc_info_packet *vtem_infopacket; + struct dc_info_packet *adaptive_sync_infopacket; + struct dc_info_packet *avi_infopacket; + struct dc_info_packet *hdr_static_metadata; }; struct dc_surface_update { @@ -1968,10 +1950,6 @@ struct dc_3dlut *dc_create_3dlut_func(void); void dc_3dlut_func_release(struct dc_3dlut *lut); void dc_3dlut_func_retain(struct dc_3dlut *lut); -struct dc_plane_cm *dc_plane_cm_create(void); -void dc_plane_cm_release(struct dc_plane_cm *cm); -void dc_plane_cm_retain(struct dc_plane_cm *cm); - void dc_post_update_surfaces_to_stream( struct dc *dc); @@ -2012,7 +1990,7 @@ enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *pla enum dc_status dc_validate_with_context(struct dc *dc, const struct dc_validation_set set[], - int set_count, + unsigned int set_count, struct dc_state *context, enum dc_validate_mode validate_mode); @@ -2124,7 +2102,7 @@ struct dc_sink_init_data; struct dc_sink *dc_link_add_remote_sink( struct dc_link *dc_link, const uint8_t *edid, - int len, + unsigned int len, struct dc_sink_init_data *init_data); /* Remove remote sink from a link with dc_connection_mst_branch connection type. @@ -2921,9 +2899,9 @@ bool dc_can_clear_cursor_limit(const struct dc *dc); * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. * The results are stored in the provided out_data structure for further analysis or logging. */ -void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data); +void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data); -void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, struct power_features *out_data); +void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data); /* * Software state variables used to program register fields across the display pipeline @@ -3436,4 +3414,17 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa */ bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info); +/** + * dc_override_memory_bandwidth_request - Override the DCN nominal memory + * bandwidth request sent to PMFW, independent of the current display mode. + * For debug use only. + * @dc: DC instance + * @bw_mbps: requested bandwidth in MB/s; 0 clears the override + * + * Return: capped bandwidth value actually applied (MB/s) + */ +unsigned int dc_override_memory_bandwidth_request( + struct dc *dc, + unsigned int bw_mbps); + #endif /* DC_INTERFACE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 6f96c5cf39fe..526f71616f94 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -102,7 +102,8 @@ struct dc_vbios_funcs { struct bp_external_encoder_control *cntl); enum bp_result (*dac_load_detection)( struct dc_bios *bios, - enum engine_id engine_id); + enum engine_id engine_id, + struct graphics_object_id ext_enc_id); enum bp_result (*transmitter_control)( struct dc_bios *bios, struct bp_transmitter_control *cntl); diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 79c8b4cab053..0ee5c0c5545c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -151,7 +151,7 @@ static bool dc_dmub_srv_reg_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_s struct dc_context *dc_ctx; struct dmub_srv *dmub; enum dmub_status status = DMUB_STATUS_OK; - int i; + unsigned int i; if (!dc_dmub_srv || !dc_dmub_srv->dmub) return false; @@ -193,7 +193,7 @@ static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_sr struct dc_context *dc_ctx; struct dmub_srv *dmub; enum dmub_status status; - int i; + unsigned int i; if (!dc_dmub_srv || !dc_dmub_srv->dmub) return false; @@ -336,7 +336,7 @@ bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv) return false; } - return boot_status.bits.optimized_init_done; + return (bool)boot_status.bits.optimized_init_done; } bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, @@ -346,7 +346,7 @@ bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, return false; return dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, - stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT); + (uint16_t)stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT); } bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) @@ -368,7 +368,7 @@ bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) return false; } - return boot_status.bits.restore_required; + return (bool)boot_status.bits.restore_required; } bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) @@ -415,7 +415,7 @@ void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) { uint8_t pipes = 0; - int i = 0; + uint8_t i = 0; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -430,25 +430,26 @@ static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state * struct pipe_ctx *head_pipe, struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data) { - int j; + unsigned int j; int pipe_idx = 0; - fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; + fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)head_pipe->plane_res.hubp->inst; for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j]; if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) { - fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; + fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)split_pipe->plane_res.hubp->inst; } } - fams_pipe_data->pipe_count = pipe_idx; + fams_pipe_data->pipe_count = (uint8_t)pipe_idx; } bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context) { union dmub_rb_cmd cmd = { 0 }; struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; - int i = 0, k = 0; + unsigned int i = 0; + int k = 0; int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. uint8_t visual_confirm_enabled; struct dc_stream_status *stream_status = NULL; @@ -456,7 +457,7 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru if (dc == NULL) return false; - visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; + visual_confirm_enabled = (uint8_t)(dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS); // Format command. cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; @@ -477,7 +478,8 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru */ stream_status = dc_state_get_stream_status(context, pipe->stream); if (stream_status && !stream_status->fpo_in_use) { - cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us; + cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = + (uint16_t)dc->debug.fpo_vactive_margin_us; break; } } @@ -486,17 +488,18 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - if (!resource_is_pipe_type(pipe, OTG_MASTER)) + if (!resource_is_pipe_type(pipe, OTG_MASTER) || !pipe->stream) continue; stream_status = dc_state_get_stream_status(context, pipe->stream); if (stream_status && stream_status->fpo_in_use) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000; + uint8_t min_refresh_in_hz; + + min_refresh_in_hz = (uint8_t)((pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000); config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz; config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz; - config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps; + config_data->pipe_data[k].max_ramp_step = (uint8_t)ramp_up_num_steps; config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream); dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]); k++; @@ -551,7 +554,7 @@ void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pi cmd.visual_confirm_color.header.sub_type = 0; cmd.visual_confirm_color.header.ret_status = 1; cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); - cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; + cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = (uint16_t)panel_inst; // If command was processed, copy feature caps to dmub srv if (dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && @@ -589,17 +592,17 @@ static void populate_subvp_cmd_drr_info(struct dc *dc, struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; struct dc_crtc_timing *phantom_timing; struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; - uint16_t drr_frame_us = 0; - uint16_t min_drr_supported_us = 0; - uint16_t max_drr_supported_us = 0; - uint16_t max_drr_vblank_us = 0; - uint16_t max_drr_mallregion_us = 0; - uint16_t mall_region_us = 0; - uint16_t prefetch_us = 0; - uint16_t subvp_active_us = 0; - uint16_t drr_active_us = 0; - uint16_t min_vtotal_supported = 0; - uint16_t max_vtotal_supported = 0; + uint64_t drr_frame_us = 0; + uint64_t min_drr_supported_us = 0; + uint64_t max_drr_supported_us = 0; + uint64_t max_drr_vblank_us = 0; + uint64_t max_drr_mallregion_us = 0; + uint64_t mall_region_us = 0; + uint64_t prefetch_us = 0; + uint64_t subvp_active_us = 0; + uint64_t drr_active_us = 0; + uint64_t min_vtotal_supported = 0; + uint64_t max_vtotal_supported = 0; if (!phantom_stream) return; @@ -639,9 +642,10 @@ static void populate_subvp_cmd_drr_info(struct dc *dc, */ max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us; - pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; - pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; - pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us; + pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = (uint16_t)min_vtotal_supported; + pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = (uint16_t)max_vtotal_supported; + pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = + (uint16_t)dc->caps.subvp_drr_vblank_start_margin_us; } /** @@ -686,14 +690,15 @@ static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, pipe_data->mode = VBLANK; pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; - pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - - vblank_pipe->stream->timing.v_front_porch; - pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; - pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; + pipe_data->pipe_config.vblank_data.vblank_start = (uint16_t)(vblank_pipe->stream->timing.v_total - + vblank_pipe->stream->timing.v_front_porch); + pipe_data->pipe_config.vblank_data.vtotal = (uint16_t)vblank_pipe->stream->timing.v_total; + pipe_data->pipe_config.vblank_data.htotal = (uint16_t)vblank_pipe->stream->timing.h_total; pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; - pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; + pipe_data->pipe_config.vblank_data.vstartup_start = (uint16_t)vblank_pipe->pipe_dlg_param.vstartup_start; pipe_data->pipe_config.vblank_data.vblank_end = - vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; + (uint16_t)(vblank_pipe->stream->timing.v_total - + vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable); if (vblank_pipe->stream->ignore_msa_timing_param && (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed)) @@ -739,10 +744,10 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, phantom_timing0 = &phantom_stream0->timing; phantom_timing1 = &phantom_stream1->timing; - subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * + subvp0_prefetch_us = (uint32_t)div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * (uint64_t)phantom_timing0->h_total * 1000000), (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); - subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * + subvp1_prefetch_us = (uint32_t)div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * (uint64_t)phantom_timing1->h_total * 1000000), (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); @@ -751,8 +756,8 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, if (subvp0_prefetch_us > subvp1_prefetch_us) { pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; - pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = - div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * +pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = + (uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), ((uint64_t)phantom_timing1->h_total * 1000000)); @@ -760,7 +765,7 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = - div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * + (uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), ((uint64_t)phantom_timing0->h_total * 1000000)); } @@ -800,14 +805,14 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, pipe_data->mode = SUBVP; pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; - pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; - pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; + pipe_data->pipe_config.subvp_data.htotal = (uint16_t)subvp_pipe->stream->timing.h_total; + pipe_data->pipe_config.subvp_data.vtotal = (uint16_t)subvp_pipe->stream->timing.v_total; pipe_data->pipe_config.subvp_data.main_vblank_start = - main_timing->v_total - main_timing->v_front_porch; + (uint16_t)(main_timing->v_total - main_timing->v_front_porch); pipe_data->pipe_config.subvp_data.main_vblank_end = - main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; - pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; - pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst; + (uint16_t)(main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable); + pipe_data->pipe_config.subvp_data.mall_region_lines = (uint16_t)phantom_timing->v_addressable; + pipe_data->pipe_config.subvp_data.main_pipe_index = (uint8_t)subvp_pipe->stream_res.tg->inst; pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param && (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed); @@ -822,25 +827,25 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, &out_num_plane, &out_den_plane); reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); - pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; - pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; + pipe_data->pipe_config.subvp_data.scale_factor_numerator = (uint8_t)out_num; + pipe_data->pipe_config.subvp_data.scale_factor_denominator = (uint8_t)out_den; // Prefetch lines is equal to VACTIVE + BP + VSYNC pipe_data->pipe_config.subvp_data.prefetch_lines = - phantom_timing->v_total - phantom_timing->v_front_porch; + (uint16_t)(phantom_timing->v_total - phantom_timing->v_front_porch); // Round up pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = - div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + + (uint16_t)div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); pipe_data->pipe_config.subvp_data.processing_delay_lines = - div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + + (uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); if (subvp_pipe->bottom_pipe) { - pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; + pipe_data->pipe_config.subvp_data.main_split_pipe_index = (uint8_t)subvp_pipe->bottom_pipe->pipe_idx; } else if (subvp_pipe->next_odm_pipe) { - pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; + pipe_data->pipe_config.subvp_data.main_split_pipe_index = (uint8_t)subvp_pipe->next_odm_pipe->pipe_idx; } else { pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0xF; } @@ -851,11 +856,11 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, if (resource_is_pipe_type(phantom_pipe, OTG_MASTER) && phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) { - pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst; + pipe_data->pipe_config.subvp_data.phantom_pipe_index = (uint8_t)phantom_pipe->stream_res.tg->inst; if (phantom_pipe->bottom_pipe) { - pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; + pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->bottom_pipe->plane_res.hubp->inst; } else if (phantom_pipe->next_odm_pipe) { - pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; + pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->next_odm_pipe->plane_res.hubp->inst; } else { pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0xF; } @@ -933,15 +938,15 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc, if (subvp_count == 2) { update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); } - cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; - cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; + cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = (uint8_t)dc->caps.subvp_pstate_allow_width_us; + cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = (uint8_t)dc->caps.subvp_vertical_int_margin_us; // Store the original watermark value for this SubVP config so we can lower it when the // MCLK switch starts wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; - cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; + cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = (uint16_t)(wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF); } dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); @@ -1060,10 +1065,10 @@ static void dc_build_cursor_update_payload0( payload->cursor_rect.width = hubp->cur_rect.w; payload->cursor_rect.height = hubp->cur_rect.h; - payload->enable = hubp->pos.cur_ctl.bits.cur_enable; + payload->enable = (uint8_t)hubp->pos.cur_ctl.bits.cur_enable; payload->pipe_idx = p_idx; - payload->panel_inst = panel_inst; - payload->otg_inst = pipe_ctx->stream_res.tg->inst; + payload->panel_inst = (uint8_t)panel_inst; + payload->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; } static void dc_build_cursor_position_update_payload0( @@ -1645,7 +1650,7 @@ bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv) if (dc_dmub_srv->dmub->shared_state && dc_dmub_srv->dmub->meta_info.feature_bits.bits.shared_state_link_detection) { ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; - return ips_fw->signals.bits.detection_required; + return (bool)ips_fw->signals.bits.detection_required; } /* Detection may require reading scratch 0 - exit out of idle prior to the read. */ @@ -1807,7 +1812,7 @@ static void dc_dmub_srv_rb_based_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable) { - uint8_t num_cmds = 1; + uint32_t num_cmds = 1; uint32_t i; union dmub_rb_cmd cmd[2 * MAX_STREAMS + 1]; struct dmub_rb_cmd_fams2 *global_cmd = &cmd[0].fams2_config; @@ -1940,7 +1945,7 @@ void dc_dmub_srv_fams2_drr_update(struct dc *dc, cmd.fams2_drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; cmd.fams2_drr_update.header.sub_type = DMUB_CMD__FAMS2_DRR_UPDATE; - cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = tg_inst; + cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = (uint8_t)tg_inst; cmd.fams2_drr_update.dmub_optc_state_req.v_total_max = vtotal_max; cmd.fams2_drr_update.dmub_optc_state_req.v_total_min = vtotal_min; cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid = vtotal_mid; @@ -1991,10 +1996,10 @@ void dc_dmub_srv_fams2_passthrough_flip( cmds[num_cmds].fams2_flip.header.multi_cmd_pending = 1; /* set topology info */ - cmds[num_cmds].fams2_flip.flip_info.pipe_mask = dc_plane_get_pipe_mask(state, plane_state); - if (stream_status) - cmds[num_cmds].fams2_flip.flip_info.otg_inst = stream_status->primary_otg_inst; - + cmds[num_cmds].fams2_flip.flip_info.pipe_mask = (uint8_t)dc_plane_get_pipe_mask(state, plane_state); + if (stream_status) { + cmds[num_cmds].fams2_flip.flip_info.otg_inst = (uint8_t)stream_status->primary_otg_inst; + } cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state->flip_immediate; /* build address info for command */ @@ -2249,6 +2254,8 @@ bool dmub_lsdma_send_tiled_to_tiled_copy_command( lsdma_data->u.tiled_copy_data.data_format = params.data_format; lsdma_data->u.tiled_copy_data.max_com = params.max_com; lsdma_data->u.tiled_copy_data.max_uncom = params.max_uncom; + lsdma_data->u.tiled_copy_data.cache_policy_src = params.src_cache_policy; + lsdma_data->u.tiled_copy_data.cache_policy_dst = params.dst_cache_policy; result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type); diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 6579cf9cce3c..ebcaf49e5961 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -240,11 +240,11 @@ struct lsdma_linear_sub_window_copy_params { uint32_t src_slice_pitch; uint32_t dst_slice_pitch; - uint32_t tmz : 1; + uint32_t tmz : 4; uint32_t element_size : 3; uint32_t src_cache_policy : 3; uint32_t dst_cache_policy : 3; - uint32_t padding : 22; + uint32_t padding : 19; }; bool dmub_lsdma_send_linear_sub_window_copy_command( @@ -286,12 +286,13 @@ struct lsdma_send_tiled_to_tiled_copy_command_params { uint32_t swizzle_mode : 5; uint32_t element_size : 3; uint32_t dcc : 1; - uint32_t tmz : 1; + uint32_t tmz : 4; uint32_t read_compress : 2; uint32_t write_compress : 2; uint32_t max_com : 2; uint32_t max_uncom : 1; - uint32_t padding : 9; + uint32_t src_cache_policy : 3; + uint32_t dst_cache_policy : 3; }; bool dmub_lsdma_send_tiled_to_tiled_copy_command( diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index 101bce6b8de6..7cb34e2b44a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -92,7 +92,7 @@ uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing, uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps( const struct dc_crtc_timing *timing, - const int num_slices_h, + const uint32_t num_slices_h, const bool is_dp); void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc, diff --git a/drivers/gpu/drm/amd/display/dc/dc_fused_io.c b/drivers/gpu/drm/amd/display/dc/dc_fused_io.c index fee69642fb93..664cb4abf623 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_fused_io.c +++ b/drivers/gpu/drm/amd/display/dc/dc_fused_io.c @@ -23,11 +23,11 @@ static bool op_i2c_convert( req->type = type; loc->is_aux = false; - loc->ddc_line = ddc_line; + loc->ddc_line = (uint8_t)ddc_line; loc->over_aux = over_aux; loc->address = op->address; loc->offset = op->offset; - loc->length = op->size; + loc->length = (uint8_t)op->size; memcpy(req->buffer, op->data, op->size); return true; @@ -84,7 +84,7 @@ static bool atomic_write_poll_read( timeout_us += timeout_per_aux_transaction_us * (io->request.u.aux.length / 16); } - if (!dm_helpers_execute_fused_io(link->ctx, link, commands, count, timeout_us)) + if (!dm_helpers_execute_fused_io(link->ctx, link, commands, count, (uint32_t)timeout_us)) return false; return commands[0].fused_io.request.status == FUSED_REQUEST_STATUS_SUCCESS; diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 77299767096f..9650cccf1b8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -122,7 +122,7 @@ static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask, field_value = va_arg(ap, uint32_t); set_reg_field_value_masks(field_value_mask, - field_value, mask, shift); + field_value, mask, (uint8_t)shift); i++; } } @@ -432,7 +432,7 @@ void generic_reg_wait(const struct dc_context *ctx, { uint32_t field_value; uint32_t reg_val; - int i; + unsigned int i; if (ctx->dmub_srv && ctx->dmub_srv->reg_helper_offload.gather_in_progress) { @@ -447,7 +447,7 @@ void generic_reg_wait(const struct dc_context *ctx, * This value comes from experiments. * */ - ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000); + ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000u); for (i = 0; i <= time_out_num_tries; i++) { if (i) { @@ -459,7 +459,7 @@ void generic_reg_wait(const struct dc_context *ctx, reg_val = dm_read_reg(ctx, addr); - field_value = get_reg_field_value_ex(reg_val, mask, shift); + field_value = get_reg_field_value_ex(reg_val, mask, (uint8_t)shift); if (field_value == condition_value) { if (i * delay_between_poll_us > 1000) @@ -525,7 +525,7 @@ uint32_t generic_indirect_reg_get(const struct dc_context *ctx, mask = va_arg(ap, uint32_t); field_value = va_arg(ap, uint32_t *); - *field_value = get_reg_field_value_ex(value, mask, shift); + *field_value = get_reg_field_value_ex(value, mask, (uint8_t)shift); i++; } @@ -554,7 +554,7 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, mask = va_arg(ap, uint32_t); field_value = va_arg(ap, uint32_t); - reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); + reg_val = set_reg_field_value_ex(reg_val, field_value, mask, (uint8_t)shift); i++; } @@ -584,7 +584,7 @@ uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx, mask = va_arg(ap, uint32_t); field_value = va_arg(ap, uint32_t); - reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); + reg_val = set_reg_field_value_ex(reg_val, field_value, mask, (uint8_t)shift); i++; } @@ -615,7 +615,7 @@ uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx, mask = va_arg(ap, uint32_t); field_value = va_arg(ap, uint32_t *); - *field_value = get_reg_field_value_ex(value, mask, shift); + *field_value = get_reg_field_value_ex(value, mask, (uint8_t)shift); i++; } diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index c2ca08d26e37..fa64bf6e711c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -346,7 +346,9 @@ enum swizzle_mode_addr3_values { DC_ADDR3_SW_4KB_3D = 5, DC_ADDR3_SW_64KB_3D = 6, DC_ADDR3_SW_256KB_3D = 7, - DC_ADDR3_SW_MAX = 8, + DC_ADDR3_SW_64KB_2D_Z = 8, + DC_ADDR3_SW_256KB_2D_Z = 9, + DC_ADDR3_SW_MAX = 10, DC_ADDR3_SW_UNKNOWN = DC_ADDR3_SW_MAX }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 7c38fa6f8cb1..4154cd059562 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -64,35 +64,6 @@ struct dc_stream_status { bool fpo_in_use; }; -enum hubp_dmdata_mode { - DMDATA_SW_MODE, - DMDATA_HW_MODE -}; - -struct dc_dmdata_attributes { - /* Specifies whether dynamic meta data will be updated by software - * or has to be fetched by hardware (DMA mode) - */ - enum hubp_dmdata_mode dmdata_mode; - /* Specifies if current dynamic meta data is to be used only for the current frame */ - bool dmdata_repeat; - /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ - uint32_t dmdata_size; - /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ - bool dmdata_updated; - /* If hardware mode is used, the base address where DMDATA surface is located */ - PHYSICAL_ADDRESS_LOC address; - /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ - bool dmdata_qos_mode; - /* If qos_mode = 1, this is the QOS value to be used: */ - uint32_t dmdata_qos_level; - /* Specifies the value in unit of REFCLK cycles to be added to the - * current time to produce the Amortized deadline for Dynamic Metadata chunk request - */ - uint32_t dmdata_dl_delta; - /* An unbounded array of uint32s, represents software dmdata to be loaded */ - uint32_t *dmdata_sw_data; -}; struct dc_writeback_info { bool wb_enabled; @@ -146,6 +117,12 @@ union stream_update_flags { uint32_t fams_changed : 1; uint32_t scaler_sharpener : 1; uint32_t sharpening_required : 1; + uint32_t cursor_attr : 1; + uint32_t cursor_pos : 1; + uint32_t periodic_interrupt : 1; + uint32_t info_frame : 1; + uint32_t dmdata : 1; + uint32_t dither : 1; } bits; uint32_t raw; @@ -179,8 +156,8 @@ struct luminance_data { int luminance_millinits[LUMINANCE_DATA_TABLE_SIZE]; int flicker_criteria_milli_nits_GAMING; int flicker_criteria_milli_nits_STATIC; - int nominal_refresh_rate; - int dm_max_decrease_from_nominal; + unsigned int nominal_refresh_rate; + unsigned int dm_max_decrease_from_nominal; }; enum dc_drr_trigger_mode { @@ -324,6 +301,7 @@ struct dc_stream_state { enum dc_drr_trigger_mode drr_trigger_mode; struct dc_update_scratch_space *update_scratch; + bool firmware_controlled_hdr_info_packet; }; #define ABM_LEVEL_IMMEDIATE_DISABLE 255 @@ -517,6 +495,9 @@ struct surface_update_descriptor dc_check_update_surfaces_for_stream( int surface_count, struct dc_stream_update *stream_update); +struct dc_link *dc_stream_get_link( + const struct dc_stream_state *dc_stream); + /** * Create a new default stream for the requested sink */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index c08d5c005df6..3ec49f4e277f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -790,6 +790,36 @@ struct dc_clock_config { uint32_t current_clock_khz;/*current clock in use*/ }; +enum hubp_dmdata_mode { + DMDATA_SW_MODE, + DMDATA_HW_MODE +}; + +struct dc_dmdata_attributes { + /* Specifies whether dynamic meta data will be updated by software + * or has to be fetched by hardware (DMA mode) + */ + enum hubp_dmdata_mode dmdata_mode; + /* Specifies if current dynamic meta data is to be used only for the current frame */ + bool dmdata_repeat; + /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ + uint32_t dmdata_size; + /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ + bool dmdata_updated; + /* If hardware mode is used, the base address where DMDATA surface is located */ + PHYSICAL_ADDRESS_LOC address; + /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ + bool dmdata_qos_mode; + /* If qos_mode = 1, this is the QOS value to be used: */ + uint32_t dmdata_qos_level; + /* Specifies the value in unit of REFCLK cycles to be added to the + * current time to produce the Amortized deadline for Dynamic Metadata chunk request + */ + uint32_t dmdata_dl_delta; + /* An unbounded array of uint32s, represents software dmdata to be loaded */ + uint32_t *dmdata_sw_data; +}; + struct hw_asic_id { uint32_t chip_id; uint32_t chip_family; @@ -887,7 +917,7 @@ struct dsc_dec_dpcd_caps { union dsc_slice_caps2 slice_caps2; int32_t lb_bit_depth; bool is_block_pred_supported; - int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ + uint32_t edp_max_bits_per_pixel; /* Valid only in eDP */ union dsc_color_formats color_formats; union dsc_color_depth color_depth; int32_t throughput_mode_0_mps; /* In MPs */ @@ -1493,28 +1523,4 @@ struct dc_validation_dpia_set { uint32_t required_bw; }; -enum dc_cm_lut_swizzle { - CM_LUT_3D_SWIZZLE_LINEAR_RGB, - CM_LUT_3D_SWIZZLE_LINEAR_BGR, - CM_LUT_1D_PACKED_LINEAR -}; - -enum dc_cm_lut_pixel_format { - CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB, - CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB, - CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB, - CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB, - CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10, - CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10 -}; - -enum dc_cm_lut_size { - CM_LUT_SIZE_NONE, - CM_LUT_SIZE_999, - CM_LUT_SIZE_171717, - CM_LUT_SIZE_333333, - CM_LUT_SIZE_454545, - CM_LUT_SIZE_656565, -}; - #endif /* DC_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c index a72bf413fad6..21dcb812fbf7 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c @@ -576,7 +576,7 @@ void dccg31_set_dtbclk_dto( // phase / modulo = dtbclk / dtbclk ref modulo = params->ref_dtbclk_khz * 1000; - phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1), + phase = (uint32_t)div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1), params->ref_dtbclk_khz); REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], @@ -620,7 +620,7 @@ void dccg31_set_audio_dtbclk_dto( // phase / modulo = dtbclk / dtbclk ref modulo = params->ref_dtbclk_khz * 1000; - phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), + phase = (uint32_t)div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), params->ref_dtbclk_khz); diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 97605a416031..417ed9d0e6bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -610,11 +610,13 @@ void dccg401_set_dp_dto( * int = target_pix_rate / reference_clock * phase = target_pix_rate - int * reference_clock, * modulo = reference_clock */ - dto_integer = div_u64(params->pixclk_hz, dto_modulo_hz); + + /* dto_modulo_hz = refclk (~100 MHz), well within uint32_t range */ + dto_integer = div_u64(params->pixclk_hz, (uint32_t)dto_modulo_hz); dto_phase_hz = params->pixclk_hz - dto_integer * dto_modulo_hz; - if (dto_phase_hz <= 0 && dto_integer <= 0) { - /* negative pixel rate should never happen */ + if (dto_phase_hz == 0 && dto_integer == 0) { + /* zero pixel rate should never happen */ BREAK_TO_DEBUGGER(); return; } @@ -656,25 +658,25 @@ void dccg401_set_dp_dto( dccg401_set_dtbclk_p_src(dccg, params->clk_src, params->otg_inst); - REG_WRITE(DP_DTO_PHASE[params->otg_inst], dto_phase_hz); - REG_WRITE(DP_DTO_MODULO[params->otg_inst], dto_modulo_hz); + REG_WRITE(DP_DTO_PHASE[params->otg_inst], (uint32_t)dto_phase_hz); + REG_WRITE(DP_DTO_MODULO[params->otg_inst], (uint32_t)dto_modulo_hz); switch (params->otg_inst) { case 0: REG_UPDATE(OTG_PIXEL_RATE_DIV, - DPDTO0_INT, dto_integer); + DPDTO0_INT, (uint32_t)dto_integer); break; case 1: REG_UPDATE(OTG_PIXEL_RATE_DIV, - DPDTO1_INT, dto_integer); + DPDTO1_INT, (uint32_t)dto_integer); break; case 2: REG_UPDATE(OTG_PIXEL_RATE_DIV, - DPDTO2_INT, dto_integer); + DPDTO2_INT, (uint32_t)dto_integer); break; case 3: REG_UPDATE(OTG_PIXEL_RATE_DIV, - DPDTO3_INT, dto_integer); + DPDTO3_INT, (uint32_t)dto_integer); break; default: BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c index b813310763e5..9612f4498ef6 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c @@ -6,6 +6,7 @@ #include "core_types.h" #include "dcn35/dcn35_dccg.h" #include "dcn42_dccg.h" +#include "dcn20/dcn20_dccg.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) @@ -306,6 +307,7 @@ static const struct dccg_funcs dccg42_funcs = { .dccg_root_gate_disable_control = dccg35_root_gate_disable_control, .dccg_read_reg_state = dccg31_read_reg_state, .dccg_enable_global_fgcg = dccg42_enable_global_fgcg, + .allow_clock_gating = dccg2_allow_clock_gating }; struct dccg *dccg42_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c index 673bb87d2c17..181944ce77ab 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c @@ -321,7 +321,7 @@ static int read_channel_reply(struct dce_aux *engine, uint32_t size, uint32_t aux_sw_data_val; REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); - buffer[i] = aux_sw_data_val; + buffer[i] = (uint8_t)aux_sw_data_val; ++i; } @@ -375,7 +375,7 @@ static enum aux_return_code_type get_channel_status( (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK)) return AUX_RET_ERROR_INVALID_REPLY; - *returned_bytes = get_reg_field_value(value, + *returned_bytes = (uint8_t)get_reg_field_value(value, AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT); @@ -559,6 +559,18 @@ static enum i2caux_transaction_action i2caux_action_from_payload(struct aux_payl int dce_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *payload, enum aux_return_code_type *operation_result) +{ + if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc || + !ddc->ddc_pin) { + return dce_aux_transfer_dmub_raw(ddc, payload, operation_result); + } else { + return dce_aux_transfer_raw_with_ddc_pin(ddc, payload, operation_result); + } +} + +int dce_aux_transfer_raw_with_ddc_pin(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) { struct ddc *ddc_pin = ddc->ddc_pin; struct dce_aux *aux_engine; @@ -740,13 +752,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, if (payload->write) dce_aux_log_payload(" write", payload->data, payload->length, 16); - /* Check whether aux to be processed via dmub or dcn directly */ - if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc - || ddc->ddc_pin == NULL) { - ret = dce_aux_transfer_dmub_raw(ddc, payload, &operation_result); - } else { - ret = dce_aux_transfer_raw(ddc, payload, &operation_result); - } + ret = dce_aux_transfer_raw(ddc, payload, &operation_result); DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, LOG_FLAG_I2cAux_DceAux, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h index c850ed49281f..8f4745694016 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h @@ -304,6 +304,10 @@ int dce_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *cmd, enum aux_return_code_type *operation_result); +int dce_aux_transfer_raw_with_ddc_pin(struct ddc_service *ddc, + struct aux_payload *cmd, + enum aux_return_code_type *operation_result); + int dce_aux_transfer_dmub_raw(struct ddc_service *ddc, struct aux_payload *payload, enum aux_return_code_type *operation_result); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 25c13822fede..ac9eed58c415 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -162,11 +162,9 @@ static bool calculate_fb_and_fractional_fb_divider( feedback_divider *= (uint64_t) (calc_pll_cs->fract_fb_divider_precision_factor); - *feedback_divider_param = - div_u64_rem( - feedback_divider, - calc_pll_cs->fract_fb_divider_factor, - fract_feedback_divider_param); + *feedback_divider_param = (uint32_t)div_u64_rem( + feedback_divider, calc_pll_cs->fract_fb_divider_factor, + fract_feedback_divider_param); if (*feedback_divider_param != 0) return true; @@ -240,7 +238,7 @@ static bool calc_fb_divider_checking_tolerance( pll_settings->calculated_pix_clk_100hz = actual_calculated_clock_100hz; pll_settings->vco_freq = - div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); + (uint32_t)div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); return true; } return false; @@ -440,8 +438,7 @@ static bool pll_adjust_pix_clk( bp_adjust_pixel_clock_params. encoder_object_id = pix_clk_params->encoder_object_id; bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type; - bp_adjust_pixel_clock_params. - ss_enable = pix_clk_params->flags.ENABLE_SS; + bp_adjust_pixel_clock_params.ss_enable = pix_clk_params->flags.ENABLE_SS != 0; bp_result = clk_src->bios->funcs->adjust_pixel_clock( clk_src->bios, &bp_adjust_pixel_clock_params); if (bp_result == BP_RESULT_OK) { @@ -958,7 +955,7 @@ static bool dce112_program_pix_clk( dce112_program_pixel_clk_resync(clk_src, pix_clk_params->signal_type, pix_clk_params->color_depth, - pix_clk_params->flags.SUPPORT_YCBCR420); + pix_clk_params->flags.SUPPORT_YCBCR420 != 0); return true; } @@ -1059,7 +1056,7 @@ static bool dcn31_program_pix_clk( dce112_program_pixel_clk_resync(clk_src, pix_clk_params->signal_type, pix_clk_params->color_depth, - pix_clk_params->flags.SUPPORT_YCBCR420); + pix_clk_params->flags.SUPPORT_YCBCR420 != 0); } return true; @@ -1162,7 +1159,7 @@ static bool dcn401_program_pix_clk( dce112_program_pixel_clk_resync(clk_src, pix_clk_params->signal_type, pix_clk_params->color_depth, - pix_clk_params->flags.SUPPORT_YCBCR420); + pix_clk_params->flags.SUPPORT_YCBCR420 != 0); } return true; @@ -1211,9 +1208,8 @@ static bool get_pixel_clk_frequency_100hz( */ modulo_hz = REG_READ(MODULO[inst]); if (modulo_hz) - *pixel_clk_khz = div_u64((uint64_t)clock_hz* - dp_dto_ref_khz*10, - modulo_hz); + *pixel_clk_khz = (unsigned int)div_u64((uint64_t)clock_hz * + dp_dto_ref_khz * 10, modulo_hz); else *pixel_clk_khz = 0; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c index fe239a96121e..05892ab4529f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c @@ -120,7 +120,7 @@ static void process_channel_reply( uint32_t i2c_data; REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); - *buffer++ = i2c_data; + *buffer++ = (uint8_t)i2c_data; --length; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c index 52e05b9185f1..e64b3b6bff5c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c @@ -75,7 +75,7 @@ static void release_engine_dce_sw( static bool wait_for_scl_high_sw( struct dc_context *ctx, struct ddc *ddc, - uint16_t clock_delay_div_4) + uint32_t clock_delay_div_4) { (void)ctx; uint32_t scl_retry = 0; @@ -97,7 +97,7 @@ static bool wait_for_scl_high_sw( static bool write_byte_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4, + uint32_t clock_delay_div_4, uint8_t byte) { int32_t shift = 7; @@ -154,7 +154,7 @@ static bool write_byte_sw( static bool read_byte_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4, + uint32_t clock_delay_div_4, uint8_t *byte, bool more) { @@ -214,7 +214,7 @@ static bool read_byte_sw( static bool stop_sync_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4) + uint32_t clock_delay_div_4) { uint32_t retry = 0; @@ -251,7 +251,7 @@ static bool stop_sync_sw( static bool i2c_write_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4, + uint32_t clock_delay_div_4, uint8_t address, uint32_t length, const uint8_t *data) @@ -273,7 +273,7 @@ static bool i2c_write_sw( static bool i2c_read_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4, + uint32_t clock_delay_div_4, uint8_t address, uint32_t length, uint8_t *data) @@ -298,7 +298,7 @@ static bool i2c_read_sw( static bool start_sync_sw( struct dc_context *ctx, struct ddc *ddc_handle, - uint16_t clock_delay_div_4) + uint32_t clock_delay_div_4) { uint32_t retry = 0; @@ -399,7 +399,7 @@ static void dce_i2c_sw_engine_submit_channel_request(struct dce_i2c_sw *engine, struct i2c_request_transaction_data *req) { struct ddc *ddc = engine->ddc; - uint16_t clock_delay_div_4 = engine->clock_delay >> 2; + uint32_t clock_delay_div_4 = engine->clock_delay >> 2; /* send sync (start / repeated start) */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c index ee55ec21d270..72c0950808ec 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -171,7 +171,7 @@ static void dce_ipp_program_input_lut( struct input_pixel_processor *ipp, const struct dc_gamma *gamma) { - int i; + unsigned int i; struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); /* power on LUT memory */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 5f40ae9e3120..c6a20378121b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -815,6 +815,7 @@ static bool dce110_link_encoder_validate_hdmi_output( { enum dc_color_depth max_deep_color = enc110->base.features.max_hdmi_deep_color; + int max_hdmi_pixel_clock_khz = (int)enc110->base.features.max_hdmi_pixel_clock; if (max_deep_color < crtc_timing->display_color_depth) return false; @@ -825,7 +826,7 @@ static bool dce110_link_encoder_validate_hdmi_output( return false; if ((adjusted_pix_clk_khz == 0) || - (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock)) + (adjusted_pix_clk_khz > max_hdmi_pixel_clock_khz)) return false; /* DCE11 HW does not support 420 */ @@ -1102,7 +1103,9 @@ void dce110_link_encoder_hw_init( ASSERT(result == BP_RESULT_OK); } - aux_initialize(enc110); + + if (enc110->aux_regs) + aux_initialize(enc110); /* reinitialize HPD. * hpd_initialize() will pass DIG_FE id to HW context. diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c index de31fb1b6819..31a9181c6a2b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c @@ -209,7 +209,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl, if (pwm_period_bitcnt == 0) bit_count = 16; else - bit_count = pwm_period_bitcnt; + bit_count = (uint8_t)pwm_period_bitcnt; /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */ masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1); @@ -224,7 +224,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl, * components shift by bitCount then mask 16 bits and add rounding bit * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0 */ - backlight_16bit = active_duty_cycle >> bit_count; + backlight_16bit = (uint32_t)(active_duty_cycle >> bit_count); backlight_16bit &= 0xFFFF; backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index c1448ae47366..b3640682fa60 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -802,7 +802,7 @@ static void program_bit_depth_reduction( ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */ - spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED; + spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED != 0; /* Default to 12 bit truncation without rounding */ trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT; trunc_mode = DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE; @@ -835,9 +835,9 @@ static void program_bit_depth_reduction( spatial_dither_enable, DCP_SPATIAL_DITHER_MODE_A_AA_A, DCP_SPATIAL_DITHER_DEPTH_30BPP, - bit_depth_params->flags.FRAME_RANDOM, - bit_depth_params->flags.RGB_RANDOM, - bit_depth_params->flags.HIGHPASS_RANDOM); + bit_depth_params->flags.FRAME_RANDOM != 0, + bit_depth_params->flags.RGB_RANDOM != 0, + bit_depth_params->flags.HIGHPASS_RANDOM != 0); } #if defined(CONFIG_DRM_AMD_DC_SI) @@ -1173,13 +1173,13 @@ bool dce_transform_get_optimal_number_of_taps( { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); int pixel_width = scl_data->viewport.width; - int max_num_of_lines; + uint32_t max_num_of_lines; if (xfm_dce->prescaler_on && (scl_data->viewport.width > scl_data->recout.width)) pixel_width = scl_data->recout.width; - max_num_of_lines = dce_transform_get_max_num_of_supported_lines( + max_num_of_lines = (uint32_t)dce_transform_get_max_num_of_supported_lines( xfm_dce, scl_data->lb_params.depth, pixel_width); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c index 806b5709c9e7..2f4d368bd3fd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c @@ -58,7 +58,7 @@ static void dmub_abm_enable_fractional_pwm(struct dc_context *dc) union dmub_rb_cmd cmd; uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0; uint32_t edp_id_count = dc->dc_edp_id_count; - int i; + unsigned int i; uint8_t panel_mask = 0; for (i = 0; i < edp_id_count; i++) @@ -176,7 +176,7 @@ void dmub_abm_init_config(struct abm *abm, cmd.abm_init_config.header.type = DMUB_CMD__ABM; cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG; cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr; - cmd.abm_init_config.abm_init_config_data.bytes = bytes; + cmd.abm_init_config.abm_init_config_data.bytes = (uint16_t)bytes; cmd.abm_init_config.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; cmd.abm_init_config.abm_init_config_data.panel_mask = panel_mask; @@ -237,7 +237,7 @@ bool dmub_abm_save_restore( cmd.abm_save_restore.header.sub_type = DMUB_CMD__ABM_SAVE_RESTORE; cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr; - cmd.abm_save_restore.abm_init_config_data.bytes = bytes; + cmd.abm_save_restore.abm_init_config_data.bytes = (uint16_t)bytes; cmd.abm_save_restore.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; cmd.abm_save_restore.abm_init_config_data.panel_mask = panel_mask; @@ -265,10 +265,10 @@ bool dmub_abm_set_pipe(struct abm *abm, memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_pipe.header.type = DMUB_CMD__ABM; cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE; - cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; - cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst; - cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option; - cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst; + cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = (uint8_t)otg_inst; + cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = (uint8_t)pwrseq_inst; + cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = (uint8_t)option; + cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = (uint8_t)panel_inst; cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary; cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data); @@ -308,7 +308,7 @@ bool dmub_abm_set_event(struct abm *abm, unsigned int scaling_enable, unsigned i memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_event.header.type = DMUB_CMD__ABM; cmd.abm_set_event.header.sub_type = DMUB_CMD__ABM_SET_EVENT; - cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = scaling_enable; + cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = (uint8_t)scaling_enable; cmd.abm_set_event.abm_set_event_data.vb_scaling_strength_mapping = scaling_strength_map; cmd.abm_set_event.abm_set_event_data.panel_mask = (1<mpcc_inst = pipe_ctx->plane_res.mpcc_inst; if (pipe_ctx->plane_res.dpp) - copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; + copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst; else copy_settings_data->dpp_inst = 0; if (pipe_ctx->stream_res.opp) - copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; + copy_settings_data->opp_inst = (uint8_t)pipe_ctx->stream_res.opp->inst; else copy_settings_data->opp_inst = 0; if (pipe_ctx->stream_res.tg) - copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; + copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; else copy_settings_data->otg_inst = 0; // Misc copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm; - copy_settings_data->psr_level = psr_context->psr_level.u32all; + copy_settings_data->psr_level = (uint16_t)psr_context->psr_level.u32all; copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations; - copy_settings_data->frame_delay = psr_context->frame_delay; + copy_settings_data->frame_delay = (uint8_t)psr_context->frame_delay; copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; - copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline; + copy_settings_data->init_sdp_deadline = (uint16_t)psr_context->sdpTransmitLineNumDeadline; copy_settings_data->debug.u32All = 0; copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR; copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index 0af1b8e0a49e..9b50bf1d80fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -151,22 +151,23 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub, copy_settings_data->digfe_inst = replay_context->digfe_inst; if (pipe_ctx->plane_res.dpp) - copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; + copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst; else copy_settings_data->dpp_inst = 0; + if (pipe_ctx->stream_res.tg) - copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; + copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; else copy_settings_data->otg_inst = 0; copy_settings_data->dpphy_inst = link->link_enc->transmitter; // Misc - copy_settings_data->line_time_in_ns = replay_context->line_time_in_ns; - copy_settings_data->panel_inst = panel_inst; - copy_settings_data->debug.u32All = link->replay_settings.config.debug_flags; + copy_settings_data->line_time_in_ns = (uint16_t)replay_context->line_time_in_ns; + copy_settings_data->panel_inst = (uint16_t)panel_inst; + copy_settings_data->debug.u32All = (uint16_t)link->replay_settings.config.debug_flags; copy_settings_data->pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line; - copy_settings_data->max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line; + copy_settings_data->max_deviation_line = (uint16_t)link->dpcd_caps.pr_info.max_deviation_line; copy_settings_data->smu_optimizations_en = link->replay_settings.replay_smu_opt_enable; copy_settings_data->replay_timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported; copy_settings_data->replay_support_fast_resync_in_ultra_sleep_mode = link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode; @@ -193,13 +194,13 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub, copy_settings_data->flags.bitfields.alpm_mode = (enum dmub_alpm_mode)link->replay_settings.config.alpm_mode; if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { - copy_settings_data->auxless_alpm_data.lfps_setup_ns = dc->dc->debug.auxless_alpm_lfps_setup_ns; - copy_settings_data->auxless_alpm_data.lfps_period_ns = dc->dc->debug.auxless_alpm_lfps_period_ns; - copy_settings_data->auxless_alpm_data.lfps_silence_ns = dc->dc->debug.auxless_alpm_lfps_silence_ns; + copy_settings_data->auxless_alpm_data.lfps_setup_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_setup_ns; + copy_settings_data->auxless_alpm_data.lfps_period_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_period_ns; + copy_settings_data->auxless_alpm_data.lfps_silence_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_silence_ns; copy_settings_data->auxless_alpm_data.lfps_t1_t2_override_us = - dc->dc->debug.auxless_alpm_lfps_t1t2_us; + (uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_us; copy_settings_data->auxless_alpm_data.lfps_t1_t2_offset_us = - dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us; + (uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us; copy_settings_data->auxless_alpm_data.lttpr_count = link->dc->link_srv->dp_get_lttpr_count(link); } diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c index 53c03364f5d4..20c18ac87998 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c @@ -98,7 +98,7 @@ static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) set_reg_field_value( value, - pix_dur, + (uint32_t)pix_dur, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c index c702a30563f9..502a2d9b155f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -75,8 +75,8 @@ void cm_helper_read_color_matrices(struct dc_context *ctx, csc_c11, ®val0, csc_c12, ®val1); - regval[2 * i] = regval0; - regval[(2 * i) + 1] = regval1; + regval[2 * i] = (uint16_t)regval0; + regval[(2 * i) + 1] = (uint16_t)regval1; i++; } @@ -342,8 +342,8 @@ bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx, struct pwl_result_data *rgb_minus_1; int32_t region_start, region_end; - int32_t i; - uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; + int32_t k; + uint32_t i, j, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; @@ -398,8 +398,8 @@ bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx, if (j == hw_points - 1) break; if (i >= TRANSFER_FUNC_POINTS) { - DC_LOG_ERROR("Index out of bounds: i=%d, TRANSFER_FUNC_POINTS=%d\n", - i, TRANSFER_FUNC_POINTS); + DC_LOG_ERROR("Index out of bounds: i=%u, TRANSFER_FUNC_POINTS=%u\n", + i, (uint32_t)TRANSFER_FUNC_POINTS); return false; } rgb_resulted[j].red = output_tf->tf_pts.red[i]; @@ -547,8 +547,8 @@ bool cm_helper_translate_curve_to_degamma_hw_format( struct pwl_result_data *rgb_plus_1; int32_t region_start, region_end; - int32_t i; - uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; + int32_t k; + uint32_t i, j, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c index baf663b661c8..feb6ca92802c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c @@ -59,7 +59,7 @@ unsigned int snprintf_count(char *pbuf, unsigned int bufsize, const char *fmt, . va_end(args); if (ret_vsnprintf > 0) { - if (ret_vsnprintf < bufsize) + if ((unsigned int)ret_vsnprintf < bufsize) chars_printed = ret_vsnprintf; else chars_printed = bufsize - 1; @@ -73,7 +73,7 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned i { struct dc_context *dc_ctx = dc->ctx; struct dcn_hubbub_wm wm; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -111,7 +111,7 @@ static unsigned int dcn10_get_hubp_states(struct dc *dc, char *pBuf, unsigned in { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -189,7 +189,7 @@ static unsigned int dcn10_get_hubp_states(struct dc *dc, char *pBuf, unsigned in static unsigned int dcn10_get_rq_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -231,7 +231,7 @@ static unsigned int dcn10_get_rq_states(struct dc *dc, char *pBuf, unsigned int static unsigned int dcn10_get_dlg_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -288,7 +288,7 @@ static unsigned int dcn10_get_dlg_states(struct dc *dc, char *pBuf, unsigned int static unsigned int dcn10_get_ttu_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -328,7 +328,7 @@ static unsigned int dcn10_get_ttu_states(struct dc *dc, char *pBuf, unsigned int static unsigned int dcn10_get_cm_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -383,7 +383,7 @@ static unsigned int dcn10_get_cm_states(struct dc *dc, char *pBuf, unsigned int static unsigned int dcn10_get_mpcc_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -414,7 +414,7 @@ static unsigned int dcn10_get_mpcc_states(struct dc *dc, char *pBuf, unsigned in static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int bufSize) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; unsigned int chars_printed = 0; unsigned int remaining_buffer = bufSize; @@ -491,7 +491,7 @@ static unsigned int dcn10_get_clock_states(struct dc *dc, char *pBuf, unsigned i static void dcn10_clear_otpc_underflow(struct dc *dc) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; for (i = 0; i < pool->timing_generator_count; i++) { struct timing_generator *tg = pool->timing_generators[i]; @@ -508,7 +508,7 @@ static void dcn10_clear_otpc_underflow(struct dc *dc) static void dcn10_clear_hubp_underflow(struct dc *dc) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { struct hubp *hubp = pool->hubps[i]; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c index f73c5f42ea68..7163426a0920 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c @@ -696,7 +696,7 @@ static void wbscl_set_scaler_filter( for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { for (pair = 0; pair < tap_pairs; pair++) { even_coef = filter[phase * taps + 2 * pair]; - if ((pair * 2 + 1) < taps) + if ((uint32_t)(pair * 2 + 1) < taps) odd_coef = filter[phase * taps + 2 * pair + 1]; else odd_coef = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c index 36456c9971c8..fcaa3884d705 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c @@ -205,7 +205,7 @@ static bool update_cfg_data( static bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc) { struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - int value; + uint32_t value; if (enc->features.flags.bits.DP_IS_USB_C) { REG_GET(RDPCSTX_PHY_CNTL6, diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c index 9dbccf58dde5..bfd5515c2f4f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c @@ -172,11 +172,13 @@ bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx, hw_points = fixpoint ? (hw_points - 1) : hw_points; j = 0; - for (k = 0; k < (region_end - region_start); k++) { + uint32_t region_span = (uint32_t)(region_end - region_start); + for (k = 0; k < region_span; k++) { increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); start_index = (region_start + k + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; - for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; + int32_t index_end = (int32_t)(start_index + NUMBER_SW_SEGMENTS); + for (i = start_index; i < index_end; i += increment) { if (j == hw_points) break; @@ -258,7 +260,7 @@ bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx, uint32_t green_clamp; uint32_t blue_clamp; - if (i >= hw_points) { + if ((uint32_t)i >= hw_points) { if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) rgb_plus_1->red = dc_fixpt_add(rgb->red, rgb_minus_1->delta_red); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c index 6f2a0d5d963b..62fe5c3b18dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c @@ -40,8 +40,8 @@ #define FN(reg_name, field_name) \ mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name -#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8 -#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40 +#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8)) +#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40)) /* wbif programming guide: * 1. set up wbif parameter: diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c index 13e14aad3daa..59b68422334d 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c @@ -450,7 +450,7 @@ static uint8_t get_frontend_source( unsigned int dcn10_get_dig_frontend(struct link_encoder *enc) { struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - int32_t value; + uint32_t value; enum engine_id result; REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); @@ -622,10 +622,11 @@ static bool dcn10_link_encoder_validate_hdmi_output( { enum dc_color_depth max_deep_color = enc10->base.features.max_hdmi_deep_color; + uint32_t pix_clk_100hz = (uint32_t)adjusted_pix_clk_100hz; // check pixel clock against edid specified max TMDS clk if (edid_caps->max_tmds_clk_mhz != 0 && - adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000) + pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000) return false; if (max_deep_color < crtc_timing->display_color_depth) @@ -633,11 +634,11 @@ static bool dcn10_link_encoder_validate_hdmi_output( if (crtc_timing->display_color_depth < COLOR_DEPTH_888) return false; - if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) + if (pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) return false; - if ((adjusted_pix_clk_100hz == 0) || - (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10))) + if ((pix_clk_100hz == 0) || + (pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10))) return false; /* DCE11 HW does not support 420 */ @@ -647,7 +648,7 @@ static bool dcn10_link_encoder_validate_hdmi_output( if ((!enc10->base.features.flags.bits.HDMI_6GB_EN || enc10->base.ctx->dc->debug.hdmi20_disable) && - adjusted_pix_clk_100hz >= 3000000) + pix_clk_100hz >= 3000000) return false; if (enc10->base.ctx->dc->debug.hdmi20_disable && crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c index e93be7b6d9b0..c14fb51c2611 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c @@ -470,7 +470,11 @@ void enc3_stream_encoder_update_dp_info_packets( &info_frame->spd, true); } - if (info_frame->hdrsmd.valid) { + /* While smart power oled is enabled DMUB is scanning the contents of each frame + * and updating the HDR infopacket contents. Therefore we transition the infopacket + * programming control to DMUB while Smart Power OLED is enabled. + */ + if (info_frame->hdrsmd.valid && !info_frame->firmware_controlled_hdr_info_packet) { enc->vpg->funcs->update_generic_info_packet( enc->vpg, 3, /* packetIndex */ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c index 2d33ed0c062d..79d0c2896d29 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c @@ -43,7 +43,7 @@ #undef FN #define FN(reg_name, field_name) \ - enc1->se_shift->field_name, enc1->se_mask->field_name + (uint8_t)enc1->se_shift->field_name, enc1->se_mask->field_name #define VBI_LINE_0 0 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h index 4b5a9594f279..9c607b24ec1c 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h @@ -121,8 +121,6 @@ LE_SF(DIO_CLK_CNTL, SYMCLKC_G_HDCP_GATE_DIS, mask_sh),\ LE_SF(DIO_CLK_CNTL, SYMCLKD_G_HDCP_GATE_DIS, mask_sh),\ LE_SF(DIO_CLK_CNTL, SYMCLKE_G_HDCP_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, SYMCLKF_G_HDCP_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, SYMCLKG_G_HDCP_GATE_DIS, mask_sh) void dcn42_link_encoder_construct( struct dcn20_link_encoder *enc20, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c index 65afbfcaa96b..55ddb9cf8a52 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c @@ -23,7 +23,7 @@ #undef FN #define FN(reg_name, field_name) \ - enc1->se_shift->field_name, enc1->se_mask->field_name + (uint8_t)enc1->se_shift->field_name, enc1->se_mask->field_name #define VBI_LINE_0 0 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 @@ -401,7 +401,7 @@ void enc42_se_enable_audio_clock( { struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, !!enable); + REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, enable); } diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index 107aec6a1265..63704d21a0b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -30,6 +30,7 @@ #ifndef __DM_HELPERS__ #define __DM_HELPERS__ +#include "modules/inc/mod_info_packet_types.h" #include "dc_types.h" #include "dc.h" diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c index 288d22a16cf2..5c00ef423968 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c @@ -45,25 +45,22 @@ void scaler_settings_calculation(struct dcn_bw_internal_vars *v) if (v->source_scan[k] == dcn_bw_hor) { v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k]; v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k]; - } - else { + } else { v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k]; v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k]; } - } - else { + } else { if (v->source_scan[k] == dcn_bw_hor) { - v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k] / v->scaler_recout_height[k]); - } - else { - v->h_ratio[k] =dcn_bw_max2(v->viewport_height[k] / v->scaler_rec_out_width[k], v->viewport_width[k] / v->scaler_recout_height[k]); + v->h_ratio[k] = dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k] / v->scaler_recout_height[k]); + } else { + v->h_ratio[k] = dcn_bw_max2(v->viewport_height[k] / v->scaler_rec_out_width[k], v->viewport_width[k] / v->scaler_recout_height[k]); } v->v_ratio[k] = v->h_ratio[k]; } - if (v->interlace_output[k] == 1.0) { - v->v_ratio[k] = 2.0 * v->v_ratio[k]; + if (v->interlace_output[k] == 1.0f) { + v->v_ratio[k] = 2.0f * v->v_ratio[k]; } - if (v->underscan_output[k] == 1.0) { + if (v->underscan_output[k] == 1.0f) { v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor; v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor; } @@ -71,46 +68,38 @@ void scaler_settings_calculation(struct dcn_bw_internal_vars *v) /*scaler taps calculation*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->h_ratio[k] > 1.0) { - v->acceptable_quality_hta_ps =dcn_bw_min2(v->max_hscl_taps, 2.0 *dcn_bw_ceil2(v->h_ratio[k], 1.0)); - } - else if (v->h_ratio[k] < 1.0) { - v->acceptable_quality_hta_ps = 4.0; - } - else { - v->acceptable_quality_hta_ps = 1.0; + if (v->h_ratio[k] > 1.0f) { + v->acceptable_quality_hta_ps = dcn_bw_min2(v->max_hscl_taps, 2.0f * dcn_bw_ceil2(v->h_ratio[k], 1.0f)); + } else if (v->h_ratio[k] < 1.0f) { + v->acceptable_quality_hta_ps = 4.0f; + } else { + v->acceptable_quality_hta_ps = 1.0f; } if (v->ta_pscalculation == dcn_bw_override) { v->htaps[k] = v->override_hta_ps[k]; - } - else { + } else { v->htaps[k] = v->acceptable_quality_hta_ps; } - if (v->v_ratio[k] > 1.0) { - v->acceptable_quality_vta_ps =dcn_bw_min2(v->max_vscl_taps, 2.0 *dcn_bw_ceil2(v->v_ratio[k], 1.0)); - } - else if (v->v_ratio[k] < 1.0) { - v->acceptable_quality_vta_ps = 4.0; - } - else { - v->acceptable_quality_vta_ps = 1.0; + if (v->v_ratio[k] > 1.0f) { + v->acceptable_quality_vta_ps = dcn_bw_min2(v->max_vscl_taps, 2.0f * dcn_bw_ceil2(v->v_ratio[k], 1.0f)); + } else if (v->v_ratio[k] < 1.0f) { + v->acceptable_quality_vta_ps = 4.0f; + } else { + v->acceptable_quality_vta_ps = 1.0f; } if (v->ta_pscalculation == dcn_bw_override) { v->vtaps[k] = v->override_vta_ps[k]; - } - else { + } else { v->vtaps[k] = v->acceptable_quality_vta_ps; } if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { - v->vta_pschroma[k] = 0.0; - v->hta_pschroma[k] = 0.0; - } - else { + v->vta_pschroma[k] = 0.0f; + v->hta_pschroma[k] = 0.0f; + } else { if (v->ta_pscalculation == dcn_bw_override) { v->vta_pschroma[k] = v->override_vta_pschroma[k]; v->hta_pschroma[k] = v->override_hta_pschroma[k]; - } - else { + } else { v->vta_pschroma[k] = v->acceptable_quality_vta_ps; v->hta_pschroma[k] = v->acceptable_quality_hta_ps; } @@ -129,7 +118,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->scale_ratio_support = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0 > v->hta_pschroma[k] || v->v_ratio[k] / 2.0 > v->vta_pschroma[k]))) { + if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0f > v->hta_pschroma[k] || v->v_ratio[k] / 2.0f > v->vta_pschroma[k]))) { v->scale_ratio_support = dcn_bw_no; } } @@ -146,60 +135,51 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->source_scan[k] == dcn_bw_hor) { v->swath_width_ysingle_dpp[k] = v->viewport_width[k]; - } - else { + } else { v->swath_width_ysingle_dpp[k] = v->viewport_height[k]; } if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->byte_per_pixel_in_dety[k] = 8.0; - v->byte_per_pixel_in_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { - v->byte_per_pixel_in_dety[k] = 4.0; - v->byte_per_pixel_in_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { - v->byte_per_pixel_in_dety[k] = 2.0; - v->byte_per_pixel_in_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->byte_per_pixel_in_dety[k] = 1.0; - v->byte_per_pixel_in_detc[k] = 2.0; - } - else { + v->byte_per_pixel_in_dety[k] = 8.0f; + v->byte_per_pixel_in_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { + v->byte_per_pixel_in_dety[k] = 4.0f; + v->byte_per_pixel_in_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { + v->byte_per_pixel_in_dety[k] = 2.0f; + v->byte_per_pixel_in_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->byte_per_pixel_in_dety[k] = 1.0f; + v->byte_per_pixel_in_detc[k] = 2.0f; + } else { v->byte_per_pixel_in_dety[k] = 4.0f / 3.0f; v->byte_per_pixel_in_detc[k] = 8.0f / 3.0f; } } - v->total_read_bandwidth_consumed_gbyte_per_second = 0.0; + v->total_read_bandwidth_consumed_gbyte_per_second = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k] * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) * v->v_ratio[k] +dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0 * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]); + v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k] * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) * v->v_ratio[k] + dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 2.0f * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]); if (v->dcc_enable[k] == dcn_bw_yes) { v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256); } if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) { v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 64); - } - else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) { + } else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) { v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256); - } - else if (v->pte_enable == dcn_bw_yes) { + } else if (v->pte_enable == dcn_bw_yes) { v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 512); } - v->total_read_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->read_bandwidth[k] / 1000.0; + v->total_read_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->read_bandwidth[k] / 1000.0f; } - v->total_write_bandwidth_consumed_gbyte_per_second = 0.0; + v->total_write_bandwidth_consumed_gbyte_per_second = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) { - v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0; + v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0f; + } else if (v->output[k] == dcn_bw_writeback) { + v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5f; + } else { + v->write_bandwidth[k] = 0.0f; } - else if (v->output[k] == dcn_bw_writeback) { - v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5; - } - else { - v->write_bandwidth[k] = 0.0; - } - v->total_write_bandwidth_consumed_gbyte_per_second = v->total_write_bandwidth_consumed_gbyte_per_second + v->write_bandwidth[k] / 1000.0; + v->total_write_bandwidth_consumed_gbyte_per_second = v->total_write_bandwidth_consumed_gbyte_per_second + v->write_bandwidth[k] / 1000.0f; } v->total_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->total_write_bandwidth_consumed_gbyte_per_second; v->dcc_enabled_in_any_plane = dcn_bw_no; @@ -209,29 +189,28 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) } } for (i = 0; i <= number_of_states_plus_one; i++) { - v->return_bw_todcn_per_state =dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0); + v->return_bw_todcn_per_state = dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0f * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0f); v->return_bw_per_state[i] = v->return_bw_todcn_per_state; - if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) { - v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0) + v->urgent_latency))); + if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0f) { + v->return_bw_per_state[i] = dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0f * (1.0f - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0f) + v->urgent_latency))); } - v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); - if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0 && v->critical_point < 4.0) { - v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0 * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); + v->critical_point = 2.0f * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f); + if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0f && v->critical_point < 4.0f) { + v->return_bw_per_state[i] = dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0f * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f), 2)); } - v->return_bw_todcn_per_state =dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0); - if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) { - v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0) + v->urgent_latency))); + v->return_bw_todcn_per_state = dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0f); + if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0f) { + v->return_bw_per_state[i] = dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0f * (1.0f - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0f) + v->urgent_latency))); } - v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); - if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0 && v->critical_point < 4.0) { - v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0 * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); + v->critical_point = 2.0f * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f); + if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0f && v->critical_point < 4.0f) { + v->return_bw_per_state[i] = dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0f * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f), 2)); } } for (i = 0; i <= number_of_states_plus_one; i++) { - if ((v->total_read_bandwidth_consumed_gbyte_per_second * 1000.0 <= v->return_bw_per_state[i]) && (v->total_bandwidth_consumed_gbyte_per_second * 1000.0 <= v->fabric_and_dram_bandwidth_per_state[i] * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0)) { + if ((v->total_read_bandwidth_consumed_gbyte_per_second * 1000.0f <= v->return_bw_per_state[i]) && (v->total_bandwidth_consumed_gbyte_per_second * 1000.0f <= v->fabric_and_dram_bandwidth_per_state[i] * 1000.0f * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0f)) { v->bandwidth_support[i] = dcn_bw_yes; - } - else { + } else { v->bandwidth_support[i] = dcn_bw_no; } } @@ -239,21 +218,19 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->writeback_latency_support = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0 > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) { + if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0f > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0f / v->write_back_latency) { v->writeback_latency_support = dcn_bw_no; - } - else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) >dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) { + } else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) > dcn_bw_min2(v->writeback_luma_buffer_size, 2.0f * v->writeback_chroma_buffer_size) * 1024.0f / v->write_back_latency) { v->writeback_latency_support = dcn_bw_no; } } /*re-ordering buffer support check*/ for (i = 0; i <= number_of_states_plus_one; i++) { - v->urgent_round_trip_and_out_of_order_latency_per_state[i] = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk_per_state[i] + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw_per_state[i]; - if ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / v->return_bw_per_state[i] > v->urgent_round_trip_and_out_of_order_latency_per_state[i]) { + v->urgent_round_trip_and_out_of_order_latency_per_state[i] = (v->round_trip_ping_latency_cycles + 32.0f) / v->dcfclk_per_state[i] + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw_per_state[i]; + if ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f / v->return_bw_per_state[i] > v->urgent_round_trip_and_out_of_order_latency_per_state[i]) { v->rob_support[i] = dcn_bw_yes; - } - else { + } else { v->rob_support[i] = dcn_bw_no; } } @@ -262,229 +239,201 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) { if (v->output_format[k] == dcn_bw_420) { - v->required_output_bw = v->pixel_clock[k] / 2.0; - } - else { + v->required_output_bw = v->pixel_clock[k] / 2.0f; + } else { v->required_output_bw = v->pixel_clock[k]; } - } - else if (v->output_format[k] == dcn_bw_420) { - v->required_output_bw = v->pixel_clock[k] * 3.0 / 2.0; - } - else { - v->required_output_bw = v->pixel_clock[k] * 3.0; + } else if (v->output_format[k] == dcn_bw_420) { + v->required_output_bw = v->pixel_clock[k] * 3.0f / 2.0f; + } else { + v->required_output_bw = v->pixel_clock[k] * 3.0f; } if (v->output[k] == dcn_bw_hdmi) { v->required_phyclk[k] = v->required_output_bw; switch (v->output_deep_color[k]) { case dcn_bw_encoder_10bpc: - v->required_phyclk[k] = v->required_phyclk[k] * 5.0 / 4; + v->required_phyclk[k] = v->required_phyclk[k] * 5.0f / 4; break; case dcn_bw_encoder_12bpc: - v->required_phyclk[k] = v->required_phyclk[k] * 3.0 / 2; + v->required_phyclk[k] = v->required_phyclk[k] * 3.0f / 2; break; default: break; } - v->required_phyclk[k] = v->required_phyclk[k] / 3.0; - } - else if (v->output[k] == dcn_bw_dp) { - v->required_phyclk[k] = v->required_output_bw / 4.0; - } - else { - v->required_phyclk[k] = 0.0; + v->required_phyclk[k] = v->required_phyclk[k] / 3.0f; + } else if (v->output[k] == dcn_bw_dp) { + v->required_phyclk[k] = v->required_output_bw / 4.0f; + } else { + v->required_phyclk[k] = 0.0f; } } for (i = 0; i <= number_of_states_plus_one; i++) { v->dio_support[i] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->required_phyclk[k] > v->phyclk_per_state[i] || (v->output[k] == dcn_bw_hdmi && v->required_phyclk[k] > 600.0)) { + if (v->required_phyclk[k] > v->phyclk_per_state[i] || (v->output[k] == dcn_bw_hdmi && v->required_phyclk[k] > 600.0f)) { v->dio_support[i] = dcn_bw_no; } } } /*total available writeback support check*/ - v->total_number_of_active_writeback = 0.0; + v->total_number_of_active_writeback = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->output[k] == dcn_bw_writeback) { - v->total_number_of_active_writeback = v->total_number_of_active_writeback + 1.0; + v->total_number_of_active_writeback = v->total_number_of_active_writeback + 1.0f; } } if (v->total_number_of_active_writeback <= v->max_num_writeback) { v->total_available_writeback_support = dcn_bw_yes; - } - else { + } else { v->total_available_writeback_support = dcn_bw_no; } /*maximum dispclk/dppclk support check*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->h_ratio[k] > 1.0) { - v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0)); + if (v->h_ratio[k] > 1.0f) { + v->pscl_factor[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / dcn_bw_ceil2(v->htaps[k] / 6.0f, 1.0f)); + } else { + v->pscl_factor[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); } - else { - v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); - } - if (v->byte_per_pixel_in_detc[k] == 0.0) { - v->pscl_factor_chroma[k] = 0.0; - v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0); - } - else { - if (v->h_ratio[k] / 2.0 > 1.0) { - v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0)); + if (v->byte_per_pixel_in_detc[k] == 0.0f) { + v->pscl_factor_chroma[k] = 0.0f; + v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] * dcn_bw_max3(v->vtaps[k] / 6.0f * dcn_bw_min2(1.0f, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0f); + } else { + if (v->h_ratio[k] / 2.0f > 1.0f) { + v->pscl_factor_chroma[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0f / dcn_bw_ceil2(v->hta_pschroma[k] / 6.0f, 1.0f)); + } else { + v->pscl_factor_chroma[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); } - else { - v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); - } - v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_factor_chroma[k], 1.0); + v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] * dcn_bw_max5(v->vtaps[k] / 6.0f * dcn_bw_min2(1.0f, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0f * dcn_bw_min2(1.0f, v->h_ratio[k] / 2.0f), v->h_ratio[k] * v->v_ratio[k] / 4.0f / v->pscl_factor_chroma[k], 1.0f); } } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->read256_block_height_y[k] = 1.0; + v->read256_block_height_y[k] = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { + v->read256_block_height_y[k] = 4.0f; + } else { + v->read256_block_height_y[k] = 8.0f; } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->read256_block_height_y[k] = 4.0; - } - else { - v->read256_block_height_y[k] = 8.0; - } - v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k]; - v->read256_block_height_c[k] = 0.0; - v->read256_block_width_c[k] = 0.0; - } - else { + v->read256_block_width_y[k] = 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / v->read256_block_height_y[k]; + v->read256_block_height_c[k] = 0.0f; + v->read256_block_width_c[k] = 0.0f; + } else { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->read256_block_height_y[k] = 1.0; - v->read256_block_height_c[k] = 1.0; + v->read256_block_height_y[k] = 1.0f; + v->read256_block_height_c[k] = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->read256_block_height_y[k] = 16.0f; + v->read256_block_height_c[k] = 8.0f; + } else { + v->read256_block_height_y[k] = 8.0f; + v->read256_block_height_c[k] = 8.0f; } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->read256_block_height_y[k] = 16.0; - v->read256_block_height_c[k] = 8.0; - } - else { - v->read256_block_height_y[k] = 8.0; - v->read256_block_height_c[k] = 8.0; - } - v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k]; - v->read256_block_width_c[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->read256_block_height_c[k]; + v->read256_block_width_y[k] = 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / v->read256_block_height_y[k]; + v->read256_block_width_c[k] = 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / v->read256_block_height_c[k]; } if (v->source_scan[k] == dcn_bw_hor) { v->max_swath_height_y[k] = v->read256_block_height_y[k]; v->max_swath_height_c[k] = v->read256_block_height_c[k]; - } - else { + } else { v->max_swath_height_y[k] = v->read256_block_width_y[k]; v->max_swath_height_c[k] = v->read256_block_width_c[k]; } if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) { v->min_swath_height_y[k] = v->max_swath_height_y[k]; - } - else { - v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0; + } else { + v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0f; } v->min_swath_height_c[k] = v->max_swath_height_c[k]; - } - else { + } else { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { v->min_swath_height_y[k] = v->max_swath_height_y[k]; v->min_swath_height_c[k] = v->max_swath_height_c[k]; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) { - v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) { + v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0f; if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) { v->min_swath_height_c[k] = v->max_swath_height_c[k]; + } else { + v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0f; } - else { - v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0; - } - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) { - v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) { + v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0f; if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) { v->min_swath_height_y[k] = v->max_swath_height_y[k]; + } else { + v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0f; } - else { - v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0; - } - } - else { + } else { v->min_swath_height_y[k] = v->max_swath_height_y[k]; v->min_swath_height_c[k] = v->max_swath_height_c[k]; } } if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->maximum_swath_width = 8192.0; + v->maximum_swath_width = 8192.0f; + } else { + v->maximum_swath_width = 5120.0f; } - else { - v->maximum_swath_width = 5120.0; + v->number_of_dpp_required_for_det_size = dcn_bw_ceil2(v->swath_width_ysingle_dpp[k] / dcn_bw_min2(v->maximum_swath_width, v->det_buffer_size_in_kbyte * 1024.0f / 2.0f / (v->byte_per_pixel_in_dety[k] * v->min_swath_height_y[k] + v->byte_per_pixel_in_detc[k] / 2.0f * v->min_swath_height_c[k])), 1.0f); + if (v->byte_per_pixel_in_detc[k] == 0.0f) { + v->number_of_dpp_required_for_lb_size = dcn_bw_ceil2((v->vtaps[k] + dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0f) - 2, 0.0f)) * v->swath_width_ysingle_dpp[k] / dcn_bw_max2(v->h_ratio[k], 1.0f) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0f); + } else { + v->number_of_dpp_required_for_lb_size = dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] + dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0f) - 2, 0.0f)) * v->swath_width_ysingle_dpp[k] / dcn_bw_max2(v->h_ratio[k], 1.0f) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0f), dcn_bw_ceil2((v->vta_pschroma[k] + dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0f, 1.0f) - 2, 0.0f)) * v->swath_width_ysingle_dpp[k] / 2.0f / dcn_bw_max2(v->h_ratio[k] / 2.0f, 1.0f) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0f)); } - v->number_of_dpp_required_for_det_size =dcn_bw_ceil2(v->swath_width_ysingle_dpp[k] /dcn_bw_min2(v->maximum_swath_width, v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / (v->byte_per_pixel_in_dety[k] * v->min_swath_height_y[k] + v->byte_per_pixel_in_detc[k] / 2.0 * v->min_swath_height_c[k])), 1.0); - if (v->byte_per_pixel_in_detc[k] == 0.0) { - v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0); - } - else { - v->number_of_dpp_required_for_lb_size =dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0),dcn_bw_ceil2((v->vta_pschroma[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0, 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0)); - } - v->number_of_dpp_required_for_det_and_lb_size[k] =dcn_bw_max2(v->number_of_dpp_required_for_det_size, v->number_of_dpp_required_for_lb_size); + v->number_of_dpp_required_for_det_and_lb_size[k] = dcn_bw_max2(v->number_of_dpp_required_for_det_size, v->number_of_dpp_required_for_lb_size); } for (i = 0; i <= number_of_states_plus_one; i++) { for (j = 0; j <= 1; j++) { - v->total_number_of_active_dpp[i][j] = 0.0; - v->required_dispclk[i][j] = 0.0; + v->total_number_of_active_dpp[i][j] = 0.0f; + v->required_dispclk[i][j] = 0.0f; v->dispclk_dppclk_support[i][j] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0); + v->min_dispclk_using_single_dpp = dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0f + v->downspreading / 100.0f); if (v->odm_capability == dcn_bw_yes) { - v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k] / 2.0, v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0); - } - else { - v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0); + v->min_dispclk_using_dual_dpp = dcn_bw_max2(v->pixel_clock[k] / 2.0f, v->min_dppclk_using_single_dpp[k] / 2.0f * (j + 1)) * (1.0f + v->downspreading / 100.0f); + } else { + v->min_dispclk_using_dual_dpp = dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0f * (j + 1)) * (1.0f + v->downspreading / 100.0f); } if (i < number_of_states) { - v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0 + v->dispclk_ramping_margin / 100.0); - v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0 + v->dispclk_ramping_margin / 100.0); + v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0f + v->dispclk_ramping_margin / 100.0f); + v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0f + v->dispclk_ramping_margin / 100.0f); } - if (v->min_dispclk_using_single_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i]) && v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) { - v->no_of_dpp[i][j][k] = 1.0; - v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp); - } - else if (v->min_dispclk_using_dual_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { - v->no_of_dpp[i][j][k] = 2.0; - v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); - } - else { - v->no_of_dpp[i][j][k] = 2.0; - v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); + if (v->min_dispclk_using_single_dpp <= dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i]) && v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0f) { + v->no_of_dpp[i][j][k] = 1.0f; + v->required_dispclk[i][j] = dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp); + } else if (v->min_dispclk_using_dual_dpp <= dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { + v->no_of_dpp[i][j][k] = 2.0f; + v->required_dispclk[i][j] = dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); + } else { + v->no_of_dpp[i][j][k] = 2.0f; + v->required_dispclk[i][j] = dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); v->dispclk_dppclk_support[i][j] = dcn_bw_no; } v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k]; } if (v->total_number_of_active_dpp[i][j] > v->max_num_dpp) { - v->total_number_of_active_dpp[i][j] = 0.0; - v->required_dispclk[i][j] = 0.0; + v->total_number_of_active_dpp[i][j] = 0.0f; + v->required_dispclk[i][j] = 0.0f; v->dispclk_dppclk_support[i][j] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0); - v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0); + v->min_dispclk_using_single_dpp = dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0f + v->downspreading / 100.0f); + v->min_dispclk_using_dual_dpp = dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0f * (j + 1)) * (1.0f + v->downspreading / 100.0f); if (i < number_of_states) { - v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0 + v->dispclk_ramping_margin / 100.0); - v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0 + v->dispclk_ramping_margin / 100.0); + v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0f + v->dispclk_ramping_margin / 100.0f); + v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0f + v->dispclk_ramping_margin / 100.0f); } - if (v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) { - v->no_of_dpp[i][j][k] = 1.0; - v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp); - if (v->min_dispclk_using_single_dpp >dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { + if (v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0f) { + v->no_of_dpp[i][j][k] = 1.0f; + v->required_dispclk[i][j] = dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp); + if (v->min_dispclk_using_single_dpp > dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { v->dispclk_dppclk_support[i][j] = dcn_bw_no; } - } - else { - v->no_of_dpp[i][j][k] = 2.0; - v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); - if (v->min_dispclk_using_dual_dpp >dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { + } else { + v->no_of_dpp[i][j][k] = 2.0f; + v->required_dispclk[i][j] = dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp); + if (v->min_dispclk_using_dual_dpp > dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { v->dispclk_dppclk_support[i][j] = dcn_bw_no; } } @@ -497,7 +446,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->viewport_size_support = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0) { + if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0f) { v->viewport_size_support = dcn_bw_no; } } @@ -507,8 +456,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (j = 0; j <= 1; j++) { if (v->total_number_of_active_dpp[i][j] <= v->max_num_dpp) { v->total_available_pipes_support[i][j] = dcn_bw_yes; - } - else { + } else { v->total_available_pipes_support[i][j] = dcn_bw_no; } } @@ -519,47 +467,43 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (i = 0; i <= number_of_states_plus_one; i++) { for (j = 0; j <= 1; j++) { v->swath_width_yper_state[i][j][k] = v->swath_width_ysingle_dpp[k] / v->no_of_dpp[i][j][k]; - v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->max_swath_height_y[k]; - v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pixel_in_dety[k] * v->max_swath_height_y[k]; + v->swath_width_granularity_y = 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / v->max_swath_height_y[k]; + v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] - 1.0f, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pixel_in_dety[k] * v->max_swath_height_y[k]; if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { - v->rounded_up_max_swath_size_bytes_y =dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0) + 256; + v->rounded_up_max_swath_size_bytes_y = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0f) + 256; } - if (v->max_swath_height_c[k] > 0.0) { - v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->max_swath_height_c[k]; - v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pixel_in_detc[k] * v->max_swath_height_c[k]; + if (v->max_swath_height_c[k] > 0.0f) { + v->swath_width_granularity_c = 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / v->max_swath_height_c[k]; + v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] / 2.0f - 1.0f, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pixel_in_detc[k] * v->max_swath_height_c[k]; if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { - v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0) + 256; + v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0f) + 256; } } - if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) { + if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0f / 2.0f) { v->swath_height_yper_state[i][j][k] = v->max_swath_height_y[k]; v->swath_height_cper_state[i][j][k] = v->max_swath_height_c[k]; - } - else { + } else { v->swath_height_yper_state[i][j][k] = v->min_swath_height_y[k]; v->swath_height_cper_state[i][j][k] = v->min_swath_height_c[k]; } - if (v->byte_per_pixel_in_detc[k] == 0.0) { - v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; - v->lines_in_det_chroma = 0.0; + if (v->byte_per_pixel_in_detc[k] == 0.0f) { + v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0f / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; + v->lines_in_det_chroma = 0.0f; + } else if (v->swath_height_yper_state[i][j][k] <= v->swath_height_cper_state[i][j][k]) { + v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0f / 2.0f / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; + v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0f / 2.0f / v->byte_per_pixel_in_detc[k] / (v->swath_width_yper_state[i][j][k] / 2.0f); + } else { + v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0f * 2.0f / 3.0f / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; + v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0f / 3.0f / v->byte_per_pixel_in_dety[k] / (v->swath_width_yper_state[i][j][k] / 2.0f); } - else if (v->swath_height_yper_state[i][j][k] <= v->swath_height_cper_state[i][j][k]) { - v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; - v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_detc[k] / (v->swath_width_yper_state[i][j][k] / 2.0); - } - else { - v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; - v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 3.0 / v->byte_per_pixel_in_dety[k] / (v->swath_width_yper_state[i][j][k] / 2.0); - } - v->effective_lb_latency_hiding_source_lines_luma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0); - v->effective_detlb_lines_luma =dcn_bw_floor2(v->lines_in_det_luma +dcn_bw_min2(v->lines_in_det_luma * v->required_dispclk[i][j] * v->byte_per_pixel_in_dety[k] * v->pscl_factor[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_yper_state[i][j][k]); - if (v->byte_per_pixel_in_detc[k] == 0.0) { - v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]); - } - else { - v->effective_lb_latency_hiding_source_lines_chroma = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / 2.0 / dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0); + v->effective_lb_latency_hiding_source_lines_luma = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / dcn_bw_max2(v->h_ratio[k], 1.0f)), 1.0f)) - (v->vtaps[k] - 1.0f); + v->effective_detlb_lines_luma = dcn_bw_floor2(v->lines_in_det_luma + dcn_bw_min2(v->lines_in_det_luma * v->required_dispclk[i][j] * v->byte_per_pixel_in_dety[k] * v->pscl_factor[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_yper_state[i][j][k]); + if (v->byte_per_pixel_in_detc[k] == 0.0f) { + v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]); + } else { + v->effective_lb_latency_hiding_source_lines_chroma = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / 2.0f / dcn_bw_max2(v->h_ratio[k] / 2.0f, 1.0f)), 1.0f)) - (v->vta_pschroma[k] - 1.0f); v->effective_detlb_lines_chroma = dcn_bw_floor2(v->lines_in_det_chroma + dcn_bw_min2(v->lines_in_det_chroma * v->required_dispclk[i][j] * v->byte_per_pixel_in_detc[k] * v->pscl_factor_chroma[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_cper_state[i][j][k]); - v->urgent_latency_support_us_per_state[i][j][k] = dcn_bw_min2(v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]), v->effective_detlb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_detlb_lines_chroma * v->swath_width_yper_state[i][j][k] / 2.0 * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k])); + v->urgent_latency_support_us_per_state[i][j][k] = dcn_bw_min2(v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]), v->effective_detlb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0f) - v->effective_detlb_lines_chroma * v->swath_width_yper_state[i][j][k] / 2.0f * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k])); } } } @@ -568,7 +512,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (j = 0; j <= 1; j++) { v->urgent_latency_support[i][j] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->urgent_latency_support_us_per_state[i][j][k] < v->urgent_latency / 1.0) { + if (v->urgent_latency_support_us_per_state[i][j][k] < v->urgent_latency / 1.0f) { v->urgent_latency_support[i][j] = dcn_bw_no; } } @@ -578,7 +522,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (i = 0; i <= number_of_states_plus_one; i++) { for (j = 0; j <= 1; j++) { - v->total_number_of_dcc_active_dpp[i][j] = 0.0; + v->total_number_of_dcc_active_dpp[i][j] = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->dcc_enable[k] == dcn_bw_yes) { v->total_number_of_dcc_active_dpp[i][j] = v->total_number_of_dcc_active_dpp[i][j] + v->no_of_dpp[i][j][k]; @@ -588,228 +532,198 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) } for (i = 0; i <= number_of_states_plus_one; i++) { for (j = 0; j <= 1; j++) { - v->projected_dcfclk_deep_sleep = 8.0; + v->projected_dcfclk_deep_sleep = 8.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, v->pixel_clock[k] / 16.0); - if (v->byte_per_pixel_in_detc[k] == 0.0) { - if (v->v_ratio[k] <= 1.0) { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, v->pixel_clock[k] / 16.0f); + if (v->byte_per_pixel_in_detc[k] == 0.0f) { + if (v->v_ratio[k] <= 1.0f) { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 64.0f * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); + } else { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 64.0f * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j)); } - else { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j)); + } else { + if (v->v_ratio[k] <= 1.0f) { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 32.0f * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); + } else { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 32.0f * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j)); } - } - else { - if (v->v_ratio[k] <= 1.0) { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); - } - else { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j)); - } - if (v->v_ratio[k] / 2.0 <= 1.0) { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->h_ratio[k] / 2.0 * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); - } - else { - v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->pscl_factor_chroma[k] * v->required_dispclk[i][j] / (1 + j)); + if (v->v_ratio[k] / 2.0f <= 1.0f) { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 32.0f * v->h_ratio[k] / 2.0f * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); + } else { + v->projected_dcfclk_deep_sleep = dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1f * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 32.0f * v->pscl_factor_chroma[k] * v->required_dispclk[i][j] / (1 + j)); } } } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->dcc_enable[k] == dcn_bw_yes) { - v->meta_req_height_y = 8.0 * v->read256_block_height_y[k]; - v->meta_req_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->meta_req_height_y; - v->meta_surface_width_y =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0, v->meta_req_width_y) + v->meta_req_width_y; - v->meta_surface_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, v->meta_req_height_y) + v->meta_req_height_y; + v->meta_req_height_y = 8.0f * v->read256_block_height_y[k]; + v->meta_req_width_y = 64.0f * 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / v->meta_req_height_y; + v->meta_surface_width_y = dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0f, v->meta_req_width_y) + v->meta_req_width_y; + v->meta_surface_height_y = dcn_bw_ceil2(v->viewport_height[k] - 1.0f, v->meta_req_height_y) + v->meta_req_height_y; if (v->pte_enable == dcn_bw_yes) { - v->meta_pte_bytes_per_frame_y = (dcn_bw_ceil2((v->meta_surface_width_y * v->meta_surface_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; - } - else { - v->meta_pte_bytes_per_frame_y = 0.0; + v->meta_pte_bytes_per_frame_y = (dcn_bw_ceil2((v->meta_surface_width_y * v->meta_surface_height_y * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 256.0f - 4096.0f) / 8.0f / 4096.0f, 1.0f) + 1) * 64.0f; + } else { + v->meta_pte_bytes_per_frame_y = 0.0f; } if (v->source_scan[k] == dcn_bw_hor) { - v->meta_row_bytes_y = v->meta_surface_width_y * v->meta_req_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0; + v->meta_row_bytes_y = v->meta_surface_width_y * v->meta_req_height_y * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 256.0f; + } else { + v->meta_row_bytes_y = v->meta_surface_height_y * v->meta_req_width_y * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / 256.0f; } - else { - v->meta_row_bytes_y = v->meta_surface_height_y * v->meta_req_width_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0; - } - } - else { - v->meta_pte_bytes_per_frame_y = 0.0; - v->meta_row_bytes_y = 0.0; + } else { + v->meta_pte_bytes_per_frame_y = 0.0f; + v->meta_row_bytes_y = 0.0f; } if (v->pte_enable == dcn_bw_yes) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->macro_tile_block_size_bytes_y = 256.0; - v->macro_tile_block_height_y = 1.0; + v->macro_tile_block_size_bytes_y = 256.0f; + v->macro_tile_block_height_y = 1.0f; + } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { + v->macro_tile_block_size_bytes_y = 4096.0f; + v->macro_tile_block_height_y = 4.0f * v->read256_block_height_y[k]; + } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { + v->macro_tile_block_size_bytes_y = 64.0f * 1024; + v->macro_tile_block_height_y = 16.0f * v->read256_block_height_y[k]; + } else { + v->macro_tile_block_size_bytes_y = 256.0f * 1024; + v->macro_tile_block_height_y = 32.0f * v->read256_block_height_y[k]; } - else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { - v->macro_tile_block_size_bytes_y = 4096.0; - v->macro_tile_block_height_y = 4.0 * v->read256_block_height_y[k]; - } - else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { - v->macro_tile_block_size_bytes_y = 64.0 * 1024; - v->macro_tile_block_height_y = 16.0 * v->read256_block_height_y[k]; - } - else { - v->macro_tile_block_size_bytes_y = 256.0 * 1024; - v->macro_tile_block_height_y = 32.0 * v->read256_block_height_y[k]; - } - if (v->macro_tile_block_size_bytes_y <= 65536.0) { + if (v->macro_tile_block_size_bytes_y <= 65536.0f) { v->data_pte_req_height_y = v->macro_tile_block_height_y; + } else { + v->data_pte_req_height_y = 16.0f * v->read256_block_height_y[k]; } - else { - v->data_pte_req_height_y = 16.0 * v->read256_block_height_y[k]; - } - v->data_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->data_pte_req_height_y * 8; + v->data_pte_req_width_y = 4096.0f / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) / v->data_pte_req_height_y * 8; if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_y / (v->viewport_width[k] / v->no_of_dpp[i][j][k]), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_y, 1.0) + 1); + v->dpte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] * dcn_bw_min2(128.0f, dcn_bw_pow(2.0f, dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_y / (v->viewport_width[k] / v->no_of_dpp[i][j][k]), 2.0f), 1.0f))) - 1.0f) / v->data_pte_req_width_y, 1.0f) + 1); + } else if (v->source_scan[k] == dcn_bw_hor) { + v->dpte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0f) / v->data_pte_req_width_y, 1.0f) + 1); + } else { + v->dpte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->viewport_height[k] - 1.0f) / v->data_pte_req_height_y, 1.0f) + 1); } - else if (v->source_scan[k] == dcn_bw_hor) { - v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0) / v->data_pte_req_width_y, 1.0) + 1); - } - else { - v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->data_pte_req_height_y, 1.0) + 1); - } - } - else { - v->dpte_bytes_per_row_y = 0.0; + } else { + v->dpte_bytes_per_row_y = 0.0f; } if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { if (v->dcc_enable[k] == dcn_bw_yes) { - v->meta_req_height_c = 8.0 * v->read256_block_height_c[k]; - v->meta_req_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->meta_req_height_c; - v->meta_surface_width_c =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0, v->meta_req_width_c) + v->meta_req_width_c; - v->meta_surface_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, v->meta_req_height_c) + v->meta_req_height_c; + v->meta_req_height_c = 8.0f * v->read256_block_height_c[k]; + v->meta_req_width_c = 64.0f * 256.0f / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / v->meta_req_height_c; + v->meta_surface_width_c = dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0f - 1.0f, v->meta_req_width_c) + v->meta_req_width_c; + v->meta_surface_height_c = dcn_bw_ceil2(v->viewport_height[k] / 2.0f - 1.0f, v->meta_req_height_c) + v->meta_req_height_c; if (v->pte_enable == dcn_bw_yes) { - v->meta_pte_bytes_per_frame_c = (dcn_bw_ceil2((v->meta_surface_width_c * v->meta_surface_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; - } - else { - v->meta_pte_bytes_per_frame_c = 0.0; + v->meta_pte_bytes_per_frame_c = (dcn_bw_ceil2((v->meta_surface_width_c * v->meta_surface_height_c * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 256.0f - 4096.0f) / 8.0f / 4096.0f, 1.0f) + 1) * 64.0f; + } else { + v->meta_pte_bytes_per_frame_c = 0.0f; } if (v->source_scan[k] == dcn_bw_hor) { - v->meta_row_bytes_c = v->meta_surface_width_c * v->meta_req_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0; + v->meta_row_bytes_c = v->meta_surface_width_c * v->meta_req_height_c * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 256.0f; + } else { + v->meta_row_bytes_c = v->meta_surface_height_c * v->meta_req_width_c * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 256.0f; } - else { - v->meta_row_bytes_c = v->meta_surface_height_c * v->meta_req_width_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0; - } - } - else { - v->meta_pte_bytes_per_frame_c = 0.0; - v->meta_row_bytes_c = 0.0; + } else { + v->meta_pte_bytes_per_frame_c = 0.0f; + v->meta_row_bytes_c = 0.0f; } if (v->pte_enable == dcn_bw_yes) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->macro_tile_block_size_bytes_c = 256.0; - v->macro_tile_block_height_c = 1.0; + v->macro_tile_block_size_bytes_c = 256.0f; + v->macro_tile_block_height_c = 1.0f; + } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { + v->macro_tile_block_size_bytes_c = 4096.0f; + v->macro_tile_block_height_c = 4.0f * v->read256_block_height_c[k]; + } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { + v->macro_tile_block_size_bytes_c = 64.0f * 1024; + v->macro_tile_block_height_c = 16.0f * v->read256_block_height_c[k]; + } else { + v->macro_tile_block_size_bytes_c = 256.0f * 1024; + v->macro_tile_block_height_c = 32.0f * v->read256_block_height_c[k]; } - else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { - v->macro_tile_block_size_bytes_c = 4096.0; - v->macro_tile_block_height_c = 4.0 * v->read256_block_height_c[k]; - } - else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { - v->macro_tile_block_size_bytes_c = 64.0 * 1024; - v->macro_tile_block_height_c = 16.0 * v->read256_block_height_c[k]; - } - else { - v->macro_tile_block_size_bytes_c = 256.0 * 1024; - v->macro_tile_block_height_c = 32.0 * v->read256_block_height_c[k]; - } - v->macro_tile_block_width_c = v->macro_tile_block_size_bytes_c /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->macro_tile_block_height_c; - if (v->macro_tile_block_size_bytes_c <= 65536.0) { + v->macro_tile_block_width_c = v->macro_tile_block_size_bytes_c / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / v->macro_tile_block_height_c; + if (v->macro_tile_block_size_bytes_c <= 65536.0f) { v->data_pte_req_height_c = v->macro_tile_block_height_c; + } else { + v->data_pte_req_height_c = 16.0f * v->read256_block_height_c[k]; } - else { - v->data_pte_req_height_c = 16.0 * v->read256_block_height_c[k]; - } - v->data_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->data_pte_req_height_c * 8; + v->data_pte_req_width_c = 4096.0f / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / v->data_pte_req_height_c * 8; if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_c / (v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_c, 1.0) + 1); - } - else if (v->source_scan[k] == dcn_bw_hor) { - v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0) / v->data_pte_req_width_c, 1.0) + 1); - } - else { - v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->data_pte_req_height_c, 1.0) + 1); + v->dpte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0f * dcn_bw_min2(128.0f, dcn_bw_pow(2.0f, dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_c / (v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0f), 2.0f), 1.0f))) - 1.0f) / v->data_pte_req_width_c, 1.0f) + 1); + } else if (v->source_scan[k] == dcn_bw_hor) { + v->dpte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0f - 1.0f) / v->data_pte_req_width_c, 1.0f) + 1); + } else { + v->dpte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->viewport_height[k] / 2.0f - 1.0f) / v->data_pte_req_height_c, 1.0f) + 1); } + } else { + v->dpte_bytes_per_row_c = 0.0f; } - else { - v->dpte_bytes_per_row_c = 0.0; - } - } - else { - v->dpte_bytes_per_row_c = 0.0; - v->meta_pte_bytes_per_frame_c = 0.0; - v->meta_row_bytes_c = 0.0; + } else { + v->dpte_bytes_per_row_c = 0.0f; + v->meta_pte_bytes_per_frame_c = 0.0f; + v->meta_row_bytes_c = 0.0f; } v->dpte_bytes_per_row[k] = v->dpte_bytes_per_row_y + v->dpte_bytes_per_row_c; v->meta_pte_bytes_per_frame[k] = v->meta_pte_bytes_per_frame_y + v->meta_pte_bytes_per_frame_c; v->meta_row_bytes[k] = v->meta_row_bytes_y + v->meta_row_bytes_c; - v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0; - v->prefill_y[k] =dcn_bw_floor2(v->v_init_y, 1.0); - v->max_num_sw_y[k] =dcn_bw_ceil2((v->prefill_y[k] - 1.0) / v->swath_height_yper_state[i][j][k], 1.0) + 1; - if (v->prefill_y[k] > 1.0) { - v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] - 2.0), v->swath_height_yper_state[i][j][k]); + v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0f + v->interlace_output[k] * 0.5f * v->v_ratio[k]) / 2.0f; + v->prefill_y[k] = dcn_bw_floor2(v->v_init_y, 1.0f); + v->max_num_sw_y[k] = dcn_bw_ceil2((v->prefill_y[k] - 1.0f) / v->swath_height_yper_state[i][j][k], 1.0f) + 1; + if (v->prefill_y[k] > 1.0f) { + v->max_partial_sw_y = dcn_bw_mod((v->prefill_y[k] - 2.0f), v->swath_height_yper_state[i][j][k]); + } else { + v->max_partial_sw_y = dcn_bw_mod((v->prefill_y[k] + v->swath_height_yper_state[i][j][k] - 2.0f), v->swath_height_yper_state[i][j][k]); } - else { - v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] + v->swath_height_yper_state[i][j][k] - 2.0), v->swath_height_yper_state[i][j][k]); - } - v->max_partial_sw_y =dcn_bw_max2(1.0, v->max_partial_sw_y); + v->max_partial_sw_y = dcn_bw_max2(1.0f, v->max_partial_sw_y); v->prefetch_lines_y[k] = v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k] + v->max_partial_sw_y; if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { - v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0; - v->prefill_c[k] =dcn_bw_floor2(v->v_init_c, 1.0); - v->max_num_sw_c[k] =dcn_bw_ceil2((v->prefill_c[k] - 1.0) / v->swath_height_cper_state[i][j][k], 1.0) + 1; - if (v->prefill_c[k] > 1.0) { - v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] - 2.0), v->swath_height_cper_state[i][j][k]); + v->v_init_c = (v->v_ratio[k] / 2.0f + v->vtaps[k] + 1.0f + v->interlace_output[k] * 0.5f * v->v_ratio[k] / 2.0f) / 2.0f; + v->prefill_c[k] = dcn_bw_floor2(v->v_init_c, 1.0f); + v->max_num_sw_c[k] = dcn_bw_ceil2((v->prefill_c[k] - 1.0f) / v->swath_height_cper_state[i][j][k], 1.0f) + 1; + if (v->prefill_c[k] > 1.0f) { + v->max_partial_sw_c = dcn_bw_mod((v->prefill_c[k] - 2.0f), v->swath_height_cper_state[i][j][k]); + } else { + v->max_partial_sw_c = dcn_bw_mod((v->prefill_c[k] + v->swath_height_cper_state[i][j][k] - 2.0f), v->swath_height_cper_state[i][j][k]); } - else { - v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] + v->swath_height_cper_state[i][j][k] - 2.0), v->swath_height_cper_state[i][j][k]); - } - v->max_partial_sw_c =dcn_bw_max2(1.0, v->max_partial_sw_c); + v->max_partial_sw_c = dcn_bw_max2(1.0f, v->max_partial_sw_c); v->prefetch_lines_c[k] = v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k] + v->max_partial_sw_c; + } else { + v->prefetch_lines_c[k] = 0.0f; } - else { - v->prefetch_lines_c[k] = 0.0; - } - v->dst_x_after_scaler = 90.0 * v->pixel_clock[k] / (v->required_dispclk[i][j] / (j + 1)) + 42.0 * v->pixel_clock[k] / v->required_dispclk[i][j]; - if (v->no_of_dpp[i][j][k] > 1.0) { - v->dst_x_after_scaler = v->dst_x_after_scaler + v->scaler_rec_out_width[k] / 2.0; + v->dst_x_after_scaler = 90.0f * v->pixel_clock[k] / (v->required_dispclk[i][j] / (j + 1)) + 42.0f * v->pixel_clock[k] / v->required_dispclk[i][j]; + if (v->no_of_dpp[i][j][k] > 1.0f) { + v->dst_x_after_scaler = v->dst_x_after_scaler + v->scaler_rec_out_width[k] / 2.0f; } if (v->output_format[k] == dcn_bw_420) { - v->dst_y_after_scaler = 1.0; + v->dst_y_after_scaler = 1.0f; + } else { + v->dst_y_after_scaler = 0.0f; } - else { - v->dst_y_after_scaler = 0.0; - } - v->time_calc = 24.0 / v->projected_dcfclk_deep_sleep; - v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); - v->total_repeater_delay = v->max_inter_dcn_tile_repeaters * (2.0 / (v->required_dispclk[i][j] / (j + 1)) + 3.0 / v->required_dispclk[i][j]); - v->v_update_width[k][j] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k]; - v->v_ready_offset[k][j] = dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k]; + v->time_calc = 24.0f / v->projected_dcfclk_deep_sleep; + v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0f, 1.0f); + v->total_repeater_delay = v->max_inter_dcn_tile_repeaters * (2.0f / (v->required_dispclk[i][j] / (j + 1)) + 3.0f / v->required_dispclk[i][j]); + v->v_update_width[k][j] = (14.0f / v->projected_dcfclk_deep_sleep + 12.0f / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k]; + v->v_ready_offset[k][j] = dcn_bw_max2(150.0f / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0f / v->projected_dcfclk_deep_sleep + 10.0f / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k]; v->time_setup = (v->v_update_offset[k][j] + v->v_update_width[k][j] + v->v_ready_offset[k][j]) / v->pixel_clock[k]; - v->extra_latency = v->urgent_round_trip_and_out_of_order_latency_per_state[i] + (v->total_number_of_active_dpp[i][j] * v->pixel_chunk_size_in_kbyte + v->total_number_of_dcc_active_dpp[i][j] * v->meta_chunk_size) * 1024.0 / v->return_bw_per_state[i]; + v->extra_latency = v->urgent_round_trip_and_out_of_order_latency_per_state[i] + (v->total_number_of_active_dpp[i][j] * v->pixel_chunk_size_in_kbyte + v->total_number_of_dcc_active_dpp[i][j] * v->meta_chunk_size) * 1024.0f / v->return_bw_per_state[i]; if (v->pte_enable == dcn_bw_yes) { - v->extra_latency = v->extra_latency + v->total_number_of_active_dpp[i][j] * v->pte_chunk_size * 1024.0 / v->return_bw_per_state[i]; + v->extra_latency = v->extra_latency + v->total_number_of_active_dpp[i][j] * v->pte_chunk_size * 1024.0f / v->return_bw_per_state[i]; } if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes) { - v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0; - } - else { - v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0; + v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0f; + } else { + v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0f; } do { v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dst_y_after_scaler + v->dst_x_after_scaler / v->htotal[k]); - v->line_times_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->line_times_for_prefetch[k] + 0.125), 1.0) / 4; - v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0 * v->meta_row_bytes[k] + 2.0 * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]); + v->line_times_for_prefetch[k] = dcn_bw_floor2(4.0f * (v->line_times_for_prefetch[k] + 0.125f), 1.0f) / 4; + v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0f * v->meta_row_bytes[k] + 2.0f * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0f * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]); if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) { v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3( v->meta_pte_bytes_frame[k] / v->prefetch_bw[k], v->extra_latency, - v->htotal[k] / v->pixel_clock[k] / 4.0); + v->htotal[k] / v->pixel_clock[k] / 4.0f); } else { - v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0; + v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0f; } if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) { @@ -823,11 +737,11 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->extra_latency - v->time_for_meta_pte_with_immediate_flip); } - v->lines_for_meta_pte_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; - v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; + v->lines_for_meta_pte_without_immediate_flip[k] = dcn_bw_floor2(4.0f * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; + v->lines_for_meta_and_dpte_row_without_immediate_flip[k] = dcn_bw_floor2(4.0f * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; v->maximum_vstartup = v->maximum_vstartup - 1; - if (v->lines_for_meta_pte_without_immediate_flip[k] < 32.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0) + if (v->lines_for_meta_pte_without_immediate_flip[k] < 32.0f && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0f) break; } while(1); @@ -837,100 +751,91 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->bw_available_for_immediate_flip = v->bw_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth[k], v->prefetch_bw[k]); } for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->total_immediate_flip_bytes[k] = 0.0; + v->total_immediate_flip_bytes[k] = 0.0f; if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { v->total_immediate_flip_bytes[k] = v->total_immediate_flip_bytes[k] + v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]; } } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) { - v->time_for_meta_pte_with_immediate_flip =dcn_bw_max5(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->meta_pte_bytes_per_frame[k] * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0); - } - else { - v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0; + v->time_for_meta_pte_with_immediate_flip = dcn_bw_max5(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->meta_pte_bytes_per_frame[k] * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0f); + } else { + v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0f; } if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) { - v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max5((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency, 2.0 * v->urgent_latency); + v->time_for_meta_and_dpte_row_with_immediate_flip = dcn_bw_max5((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency, 2.0f * v->urgent_latency); + } else { + v->time_for_meta_and_dpte_row_with_immediate_flip = dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency - v->time_for_meta_pte_with_immediate_flip); } - else { - v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency - v->time_for_meta_pte_with_immediate_flip); - } - v->lines_for_meta_pte_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; - v->lines_for_meta_and_dpte_row_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; + v->lines_for_meta_pte_with_immediate_flip[k] = dcn_bw_floor2(4.0f * (v->time_for_meta_pte_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; + v->lines_for_meta_and_dpte_row_with_immediate_flip[k] = dcn_bw_floor2(4.0f * (v->time_for_meta_and_dpte_row_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; v->line_times_to_request_prefetch_pixel_data_with_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_with_immediate_flip[k] - v->lines_for_meta_and_dpte_row_with_immediate_flip[k]; v->line_times_to_request_prefetch_pixel_data_without_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_without_immediate_flip[k] - v->lines_for_meta_and_dpte_row_without_immediate_flip[k]; - if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip > 0.0) { + if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip > 0.0f) { v->v_ratio_pre_ywith_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip; - if ((v->swath_height_yper_state[i][j][k] > 4.0)) { - if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) { - v->v_ratio_pre_ywith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywith_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0; + if ((v->swath_height_yper_state[i][j][k] > 4.0f)) { + if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0f) / 2.0f > 0.0f) { + v->v_ratio_pre_ywith_immediate_flip[i][j][k] = dcn_bw_max2(v->v_ratio_pre_ywith_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0f; } } v->v_ratio_pre_cwith_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip; - if ((v->swath_height_cper_state[i][j][k] > 4.0)) { - if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) { - v->v_ratio_pre_cwith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwith_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0; + if ((v->swath_height_cper_state[i][j][k] > 4.0f)) { + if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0f) / 2.0f > 0.0f) { + v->v_ratio_pre_cwith_immediate_flip[i][j][k] = dcn_bw_max2(v->v_ratio_pre_cwith_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0f; } } - v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]); + v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 2.0f) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]); + } else { + v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0f; + v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0f; + v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = 999999.0f; } - else { - v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0; - v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0; - v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = 999999.0; - } - if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip > 0.0) { + if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip > 0.0f) { v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip; - if ((v->swath_height_yper_state[i][j][k] > 4.0)) { - if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) { - v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywithout_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0; + if ((v->swath_height_yper_state[i][j][k] > 4.0f)) { + if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0f) / 2.0f > 0.0f) { + v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = dcn_bw_max2(v->v_ratio_pre_ywithout_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0f; } } v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip; - if ((v->swath_height_cper_state[i][j][k] > 4.0)) { - if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) { - v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwithout_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0; + if ((v->swath_height_cper_state[i][j][k] > 4.0f)) { + if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0f) / 2.0f > 0.0f) { + v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = dcn_bw_max2(v->v_ratio_pre_cwithout_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0f; } } - v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]); - } - else { - v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0; - v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0; - v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = 999999.0; + v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0f) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0f) / 2.0f) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]); + } else { + v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0f; + v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0f; + v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = 999999.0f; } } - v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = 0.0; + v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { - v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k]) +dcn_bw_max2(v->meta_pte_bytes_per_frame[k] / (v->lines_for_meta_pte_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / (v->lines_for_meta_and_dpte_row_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k])); - } - else { - v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]); + v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip + dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k]) + dcn_bw_max2(v->meta_pte_bytes_per_frame[k] / (v->lines_for_meta_pte_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / (v->lines_for_meta_and_dpte_row_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k])); + } else { + v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip + dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]); } } - v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = 0.0; + v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = v->maximum_read_bandwidth_with_prefetch_without_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]); + v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = v->maximum_read_bandwidth_with_prefetch_without_immediate_flip + dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]); } v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes; if (v->maximum_read_bandwidth_with_prefetch_with_immediate_flip > v->return_bw_per_state[i]) { v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no; } for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_with_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_with_immediate_flip[k] >= 16.0) { + if (v->line_times_for_prefetch[k] < 2.0f || v->lines_for_meta_pte_with_immediate_flip[k] >= 8.0f || v->lines_for_meta_and_dpte_row_with_immediate_flip[k] >= 16.0f) { v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no; } } @@ -939,7 +844,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no; } for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_without_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_without_immediate_flip[k] >= 16.0) { + if (v->line_times_for_prefetch[k] < 2.0f || v->lines_for_meta_pte_without_immediate_flip[k] >= 8.0f || v->lines_for_meta_and_dpte_row_without_immediate_flip[k] >= 16.0f) { v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no; } } @@ -949,13 +854,13 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) for (j = 0; j <= 1; j++) { v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywith_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwith_immediate_flip[i][j][k] > 4.0)) || ((v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 || v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)))) { + if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywith_immediate_flip[i][j][k] > 4.0f || v->v_ratio_pre_cwith_immediate_flip[i][j][k] > 4.0f)) || ((v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 || v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0f || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0f)))) { v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no; } } v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)) { + if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0f || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0f)) { v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no; } } @@ -968,18 +873,15 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) if (v->scale_ratio_support == dcn_bw_yes && v->source_format_pixel_and_scan_support == dcn_bw_yes && v->viewport_size_support == dcn_bw_yes && v->bandwidth_support[i] == dcn_bw_yes && v->dio_support[i] == dcn_bw_yes && v->urgent_latency_support[i][j] == dcn_bw_yes && v->rob_support[i] == dcn_bw_yes && v->dispclk_dppclk_support[i][j] == dcn_bw_yes && v->total_available_pipes_support[i][j] == dcn_bw_yes && v->total_available_writeback_support == dcn_bw_yes && v->writeback_latency_support == dcn_bw_yes) { if (v->prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes && v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes) { v->mode_support_with_immediate_flip[i][j] = dcn_bw_yes; - } - else { + } else { v->mode_support_with_immediate_flip[i][j] = dcn_bw_no; } if (v->prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes && v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes) { v->mode_support_without_immediate_flip[i][j] = dcn_bw_yes; - } - else { + } else { v->mode_support_without_immediate_flip[i][j] = dcn_bw_no; } - } - else { + } else { v->mode_support_with_immediate_flip[i][j] = dcn_bw_no; v->mode_support_without_immediate_flip[i][j] = dcn_bw_no; } @@ -987,21 +889,20 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) } for (i = number_of_states_plus_one; i >= 0; i--) { if ((i == number_of_states_plus_one || v->mode_support_with_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_with_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) { - v->voltage_level_with_immediate_flip = i; + v->voltage_level_with_immediate_flip = (float)i; } } for (i = number_of_states_plus_one; i >= 0; i--) { if ((i == number_of_states_plus_one || v->mode_support_without_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_without_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) { - v->voltage_level_without_immediate_flip = i; + v->voltage_level_without_immediate_flip = (float)i; } } if (v->voltage_level_with_immediate_flip == number_of_states_plus_one) { v->immediate_flip_supported = dcn_bw_no; - v->voltage_level = v->voltage_level_without_immediate_flip; - } - else { + v->voltage_level = (int)v->voltage_level_without_immediate_flip; + } else { v->immediate_flip_supported = dcn_bw_yes; - v->voltage_level = v->voltage_level_with_immediate_flip; + v->voltage_level = (int)v->voltage_level_with_immediate_flip; } v->dcfclk = v->dcfclk_per_state[v->voltage_level]; v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level]; @@ -1021,16 +922,15 @@ void display_pipe_configuration(struct dcn_bw_internal_vars *v) /*display pipe configuration*/ for (j = 0; j <= 1; j++) { - v->total_number_of_active_dpp_per_ratio[j] = 0.0; + v->total_number_of_active_dpp_per_ratio[j] = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->total_number_of_active_dpp_per_ratio[j] = v->total_number_of_active_dpp_per_ratio[j] + v->dpp_per_plane_per_ratio[j][k]; } } - if ((v->dispclk_dppclk_support_per_ratio[0] == dcn_bw_yes && v->dispclk_dppclk_support_per_ratio[1] == dcn_bw_no) || (v->dispclk_dppclk_support_per_ratio[0] == v->dispclk_dppclk_support_per_ratio[1] && (v->total_number_of_active_dpp_per_ratio[0] < v->total_number_of_active_dpp_per_ratio[1] || (((v->total_number_of_active_dpp_per_ratio[0] == v->total_number_of_active_dpp_per_ratio[1]) && v->required_dispclk_per_ratio[0] <= 0.5 * v->required_dispclk_per_ratio[1]))))) { + if ((v->dispclk_dppclk_support_per_ratio[0] == dcn_bw_yes && v->dispclk_dppclk_support_per_ratio[1] == dcn_bw_no) || (v->dispclk_dppclk_support_per_ratio[0] == v->dispclk_dppclk_support_per_ratio[1] && (v->total_number_of_active_dpp_per_ratio[0] < v->total_number_of_active_dpp_per_ratio[1] || (((v->total_number_of_active_dpp_per_ratio[0] == v->total_number_of_active_dpp_per_ratio[1]) && v->required_dispclk_per_ratio[0] <= 0.5f * v->required_dispclk_per_ratio[1]))))) { v->dispclk_dppclk_ratio = 1; v->final_error_message = v->error_message[0]; - } - else { + } else { v->dispclk_dppclk_ratio = 2; v->final_error_message = v->error_message[1]; } @@ -1039,137 +939,116 @@ void display_pipe_configuration(struct dcn_bw_internal_vars *v) } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->byte_per_pix_dety = 8.0; - v->byte_per_pix_detc = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { - v->byte_per_pix_dety = 4.0; - v->byte_per_pix_detc = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { - v->byte_per_pix_dety = 2.0; - v->byte_per_pix_detc = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->byte_per_pix_dety = 1.0; - v->byte_per_pix_detc = 2.0; - } - else { + v->byte_per_pix_dety = 8.0f; + v->byte_per_pix_detc = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { + v->byte_per_pix_dety = 4.0f; + v->byte_per_pix_detc = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { + v->byte_per_pix_dety = 2.0f; + v->byte_per_pix_detc = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->byte_per_pix_dety = 1.0f; + v->byte_per_pix_detc = 2.0f; + } else { v->byte_per_pix_dety = 4.0f / 3.0f; v->byte_per_pix_detc = 8.0f / 3.0f; } if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->read256_bytes_block_height_y = 1.0; + v->read256_bytes_block_height_y = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { + v->read256_bytes_block_height_y = 4.0f; + } else { + v->read256_bytes_block_height_y = 8.0f; } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->read256_bytes_block_height_y = 4.0; - } - else { - v->read256_bytes_block_height_y = 8.0; - } - v->read256_bytes_block_width_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->read256_bytes_block_height_y; - v->read256_bytes_block_height_c = 0.0; - v->read256_bytes_block_width_c = 0.0; - } - else { + v->read256_bytes_block_width_y = 256.0f / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0f) / v->read256_bytes_block_height_y; + v->read256_bytes_block_height_c = 0.0f; + v->read256_bytes_block_width_c = 0.0f; + } else { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->read256_bytes_block_height_y = 1.0; - v->read256_bytes_block_height_c = 1.0; + v->read256_bytes_block_height_y = 1.0f; + v->read256_bytes_block_height_c = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->read256_bytes_block_height_y = 16.0f; + v->read256_bytes_block_height_c = 8.0f; + } else { + v->read256_bytes_block_height_y = 8.0f; + v->read256_bytes_block_height_c = 8.0f; } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->read256_bytes_block_height_y = 16.0; - v->read256_bytes_block_height_c = 8.0; - } - else { - v->read256_bytes_block_height_y = 8.0; - v->read256_bytes_block_height_c = 8.0; - } - v->read256_bytes_block_width_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->read256_bytes_block_height_y; - v->read256_bytes_block_width_c = 256.0 /dcn_bw_ceil2(v->byte_per_pix_detc, 2.0) / v->read256_bytes_block_height_c; + v->read256_bytes_block_width_y = 256.0f / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0f) / v->read256_bytes_block_height_y; + v->read256_bytes_block_width_c = 256.0f / dcn_bw_ceil2(v->byte_per_pix_detc, 2.0f) / v->read256_bytes_block_height_c; } if (v->source_scan[k] == dcn_bw_hor) { v->maximum_swath_height_y = v->read256_bytes_block_height_y; v->maximum_swath_height_c = v->read256_bytes_block_height_c; - } - else { + } else { v->maximum_swath_height_y = v->read256_bytes_block_width_y; v->maximum_swath_height_c = v->read256_bytes_block_width_c; } if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) { v->minimum_swath_height_y = v->maximum_swath_height_y; - } - else { - v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0; + } else { + v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0f; } v->minimum_swath_height_c = v->maximum_swath_height_c; - } - else { + } else { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { v->minimum_swath_height_y = v->maximum_swath_height_y; v->minimum_swath_height_c = v->maximum_swath_height_c; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) { - v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) { + v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0f; if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) { v->minimum_swath_height_c = v->maximum_swath_height_c; + } else { + v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0f; } - else { - v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0; - } - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) { - v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) { + v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0f; if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) { v->minimum_swath_height_y = v->maximum_swath_height_y; + } else { + v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0f; } - else { - v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0; - } - } - else { + } else { v->minimum_swath_height_y = v->maximum_swath_height_y; v->minimum_swath_height_c = v->maximum_swath_height_c; } } if (v->source_scan[k] == dcn_bw_hor) { v->swath_width = v->viewport_width[k] / v->dpp_per_plane[k]; - } - else { + } else { v->swath_width = v->viewport_height[k] / v->dpp_per_plane[k]; } - v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->maximum_swath_height_y; - v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pix_dety * v->maximum_swath_height_y; + v->swath_width_granularity_y = 256.0f / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0f) / v->maximum_swath_height_y; + v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width - 1.0f, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pix_dety * v->maximum_swath_height_y; if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { - v->rounded_up_max_swath_size_bytes_y =dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0) + 256; + v->rounded_up_max_swath_size_bytes_y = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0f) + 256; } - if (v->maximum_swath_height_c > 0.0) { - v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pix_detc, 2.0) / v->maximum_swath_height_c; - v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pix_detc * v->maximum_swath_height_c; + if (v->maximum_swath_height_c > 0.0f) { + v->swath_width_granularity_c = 256.0f / dcn_bw_ceil2(v->byte_per_pix_detc, 2.0f) / v->maximum_swath_height_c; + v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width / 2.0f - 1.0f, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pix_detc * v->maximum_swath_height_c; if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { - v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0) + 256; + v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0f) + 256; } } - if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) { + if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0f / 2.0f) { v->swath_height_y[k] = v->maximum_swath_height_y; v->swath_height_c[k] = v->maximum_swath_height_c; - } - else { + } else { v->swath_height_y[k] = v->minimum_swath_height_y; v->swath_height_c[k] = v->minimum_swath_height_c; } - if (v->swath_height_c[k] == 0.0) { - v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0; - v->det_buffer_size_c[k] = 0.0; - } - else if (v->swath_height_y[k] <= v->swath_height_c[k]) { - v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0; - v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0; - } - else { - v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0; - v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 3.0; + if (v->swath_height_c[k] == 0.0f) { + v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0f; + v->det_buffer_size_c[k] = 0.0f; + } else if (v->swath_height_y[k] <= v->swath_height_c[k]) { + v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0f / 2.0f; + v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0f / 2.0f; + } else { + v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0f * 2.0f / 3.0f; + v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0f / 3.0f; } } } @@ -1178,52 +1057,46 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan int k; /*dispclk and dppclk calculation*/ - v->dispclk_with_ramping = 0.0; - v->dispclk_without_ramping = 0.0; + v->dispclk_with_ramping = 0.0f; + v->dispclk_without_ramping = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->h_ratio[k] > 1.0) { - v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0)); + if (v->h_ratio[k] > 1.0f) { + v->pscl_throughput[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / dcn_bw_ceil2(v->htaps[k] / 6.0f, 1.0f)); + } else { + v->pscl_throughput[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); } - else { - v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); - } - v->dppclk_using_single_dpp_luma = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_throughput[k], 1.0); + v->dppclk_using_single_dpp_luma = v->pixel_clock[k] * dcn_bw_max3(v->vtaps[k] / 6.0f * dcn_bw_min2(1.0f, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_throughput[k], 1.0f); if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { - v->pscl_throughput_chroma[k] = 0.0; + v->pscl_throughput_chroma[k] = 0.0f; v->dppclk_using_single_dpp = v->dppclk_using_single_dpp_luma; - } - else { - if (v->h_ratio[k] > 1.0) { - v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0)); + } else { + if (v->h_ratio[k] > 1.0f) { + v->pscl_throughput_chroma[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0f / dcn_bw_ceil2(v->hta_pschroma[k] / 6.0f, 1.0f)); + } else { + v->pscl_throughput_chroma[k] = dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); } - else { - v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); - } - v->dppclk_using_single_dpp_chroma = v->pixel_clock[k] *dcn_bw_max3(v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_throughput_chroma[k], 1.0); - v->dppclk_using_single_dpp =dcn_bw_max2(v->dppclk_using_single_dpp_luma, v->dppclk_using_single_dpp_chroma); + v->dppclk_using_single_dpp_chroma = v->pixel_clock[k] * dcn_bw_max3(v->vta_pschroma[k] / 6.0f * dcn_bw_min2(1.0f, v->h_ratio[k] / 2.0f), v->h_ratio[k] * v->v_ratio[k] / 4.0f / v->pscl_throughput_chroma[k], 1.0f); + v->dppclk_using_single_dpp = dcn_bw_max2(v->dppclk_using_single_dpp_luma, v->dppclk_using_single_dpp_chroma); } if (v->odm_capable == dcn_bw_yes) { - v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0)); - v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0)); - } - else { - v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0)); - v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0)); + v->dispclk_with_ramping = dcn_bw_max2(v->dispclk_with_ramping, dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0f + v->downspreading / 100.0f) * (1.0f + v->dispclk_ramping_margin / 100.0f)); + v->dispclk_without_ramping = dcn_bw_max2(v->dispclk_without_ramping, dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0f + v->downspreading / 100.0f)); + } else { + v->dispclk_with_ramping = dcn_bw_max2(v->dispclk_with_ramping, dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0f + v->downspreading / 100.0f) * (1.0f + v->dispclk_ramping_margin / 100.0f)); + v->dispclk_without_ramping = dcn_bw_max2(v->dispclk_without_ramping, dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0f + v->downspreading / 100.0f)); } } if (v->dispclk_without_ramping > v->max_dispclk[number_of_states]) { v->dispclk = v->dispclk_without_ramping; - } - else if (v->dispclk_with_ramping > v->max_dispclk[number_of_states]) { + } else if (v->dispclk_with_ramping > v->max_dispclk[number_of_states]) { v->dispclk = v->max_dispclk[number_of_states]; - } - else { + } else { v->dispclk = v->dispclk_with_ramping; } v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; /*urgent watermark*/ - v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0); + v->return_bandwidth_to_dcn = dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0f * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0f); v->dcc_enabled_any_plane = dcn_bw_no; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->dcc_enable[k] == dcn_bw_yes) { @@ -1231,129 +1104,119 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan } } v->return_bw = v->return_bandwidth_to_dcn; - if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) { - v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency))); + if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0f) { + v->return_bw = dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0f * (1.0f - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0f) + v->urgent_latency))); } - v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); - if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0 && v->critical_compression < 4.0) { - v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); + v->critical_compression = 2.0f * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f); + if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0f && v->critical_compression < 4.0f) { + v->return_bw = dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0f * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f), 2)); } - v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0); - if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) { - v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency))); + v->return_bandwidth_to_dcn = dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0f); + if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0f) { + v->return_bw = dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0f * (1.0f - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0f) + v->urgent_latency))); } - v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); - if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0 && v->critical_compression < 4.0) { - v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); + v->critical_compression = 2.0f * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f); + if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0f && v->critical_compression < 4.0f) { + v->return_bw = dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0f * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0f), 2)); } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->source_scan[k] == dcn_bw_hor) { v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k]; - } - else { + } else { v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k]; } } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->byte_per_pixel_dety[k] = 8.0; - v->byte_per_pixel_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { - v->byte_per_pixel_dety[k] = 4.0; - v->byte_per_pixel_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { - v->byte_per_pixel_dety[k] = 2.0; - v->byte_per_pixel_detc[k] = 0.0; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->byte_per_pixel_dety[k] = 1.0; - v->byte_per_pixel_detc[k] = 2.0; - } - else { + v->byte_per_pixel_dety[k] = 8.0f; + v->byte_per_pixel_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { + v->byte_per_pixel_dety[k] = 4.0f; + v->byte_per_pixel_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { + v->byte_per_pixel_dety[k] = 2.0f; + v->byte_per_pixel_detc[k] = 0.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->byte_per_pixel_dety[k] = 1.0f; + v->byte_per_pixel_detc[k] = 2.0f; + } else { v->byte_per_pixel_dety[k] = 4.0f / 3.0f; v->byte_per_pixel_detc[k] = 8.0f / 3.0f; } } - v->total_data_read_bandwidth = 0.0; + v->total_data_read_bandwidth = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; - v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0; + v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; + v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0f * v->dpp_per_plane[k] * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0f; v->total_data_read_bandwidth = v->total_data_read_bandwidth + v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k]; } - v->total_active_dpp = 0.0; - v->total_dcc_active_dpp = 0.0; + v->total_active_dpp = 0.0f; + v->total_dcc_active_dpp = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->total_active_dpp = v->total_active_dpp + v->dpp_per_plane[k]; if (v->dcc_enable[k] == dcn_bw_yes) { v->total_dcc_active_dpp = v->total_dcc_active_dpp + v->dpp_per_plane[k]; } } - v->urgent_round_trip_and_out_of_order_latency = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw; - v->last_pixel_of_line_extra_watermark = 0.0; + v->urgent_round_trip_and_out_of_order_latency = (v->round_trip_ping_latency_cycles + 32.0f) / v->dcfclk + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw; + v->last_pixel_of_line_extra_watermark = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->v_ratio[k] <= 1.0) { + if (v->v_ratio[k] <= 1.0f) { v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k]; - } - else { + } else { v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; } - v->data_fabric_line_delivery_time_luma = v->swath_width_y[k] * v->swath_height_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->return_bw * v->read_bandwidth_plane_luma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth); - v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_luma - v->display_pipe_line_delivery_time_luma[k]); - if (v->byte_per_pixel_detc[k] == 0.0) { - v->display_pipe_line_delivery_time_chroma[k] = 0.0; - } - else { - if (v->v_ratio[k] / 2.0 <= 1.0) { - v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0) / v->pixel_clock[k]; + v->data_fabric_line_delivery_time_luma = v->swath_width_y[k] * v->swath_height_y[k] * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / (v->return_bw * v->read_bandwidth_plane_luma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth); + v->last_pixel_of_line_extra_watermark = dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_luma - v->display_pipe_line_delivery_time_luma[k]); + if (v->byte_per_pixel_detc[k] == 0.0f) { + v->display_pipe_line_delivery_time_chroma[k] = 0.0f; + } else { + if (v->v_ratio[k] / 2.0f <= 1.0f) { + v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0f * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0f) / v->pixel_clock[k]; + } else { + v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0f / v->pscl_throughput_chroma[k] / v->dppclk; } - else { - v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk; - } - v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0 * v->swath_height_c[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->return_bw * v->read_bandwidth_plane_chroma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth); - v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_chroma - v->display_pipe_line_delivery_time_chroma[k]); + v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0f * v->swath_height_c[k] * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / (v->return_bw * v->read_bandwidth_plane_chroma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth); + v->last_pixel_of_line_extra_watermark = dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_chroma - v->display_pipe_line_delivery_time_chroma[k]); } } - v->urgent_extra_latency = v->urgent_round_trip_and_out_of_order_latency + (v->total_active_dpp * v->pixel_chunk_size_in_kbyte + v->total_dcc_active_dpp * v->meta_chunk_size) * 1024.0 / v->return_bw; + v->urgent_extra_latency = v->urgent_round_trip_and_out_of_order_latency + (v->total_active_dpp * v->pixel_chunk_size_in_kbyte + v->total_dcc_active_dpp * v->meta_chunk_size) * 1024.0f / v->return_bw; if (v->pte_enable == dcn_bw_yes) { - v->urgent_extra_latency = v->urgent_extra_latency + v->total_active_dpp * v->pte_chunk_size * 1024.0 / v->return_bw; + v->urgent_extra_latency = v->urgent_extra_latency + v->total_active_dpp * v->pte_chunk_size * 1024.0f / v->return_bw; } v->urgent_watermark = v->urgent_latency + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency; - v->ptemeta_urgent_watermark = v->urgent_watermark + 2.0 * v->urgent_latency; + v->ptemeta_urgent_watermark = v->urgent_watermark + 2.0f * v->urgent_latency; /*nb p-state/dram clock change watermark*/ v->dram_clock_change_watermark = v->dram_clock_change_latency + v->urgent_watermark; - v->total_active_writeback = 0.0; + v->total_active_writeback = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->output[k] == dcn_bw_writeback) { - v->total_active_writeback = v->total_active_writeback + 1.0; + v->total_active_writeback = v->total_active_writeback + 1.0f; } } - if (v->total_active_writeback <= 1.0) { + if (v->total_active_writeback <= 1.0f) { v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency; - } - else { - v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency + v->writeback_chunk_size * 1024.0 / 32.0 / v->socclk; + } else { + v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency + v->writeback_chunk_size * 1024.0f / 32.0f / v->socclk; } /*stutter efficiency*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->lines_in_dety[k] = v->det_buffer_size_y[k] / v->byte_per_pixel_dety[k] / v->swath_width_y[k]; - v->lines_in_dety_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_dety[k], v->swath_height_y[k]); + v->lines_in_dety_rounded_down_to_swath[k] = dcn_bw_floor2(v->lines_in_dety[k], v->swath_height_y[k]); v->full_det_buffering_time_y[k] = v->lines_in_dety_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k]; - if (v->byte_per_pixel_detc[k] > 0.0) { - v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k] / (v->swath_width_y[k] / 2.0); - v->lines_in_detc_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_detc[k], v->swath_height_c[k]); - v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0); - } - else { - v->lines_in_detc[k] = 0.0; - v->lines_in_detc_rounded_down_to_swath[k] = 0.0; - v->full_det_buffering_time_c[k] = 999999.0; + if (v->byte_per_pixel_detc[k] > 0.0f) { + v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k] / (v->swath_width_y[k] / 2.0f); + v->lines_in_detc_rounded_down_to_swath[k] = dcn_bw_floor2(v->lines_in_detc[k], v->swath_height_c[k]); + v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0f); + } else { + v->lines_in_detc[k] = 0.0f; + v->lines_in_detc_rounded_down_to_swath[k] = 0.0f; + v->full_det_buffering_time_c[k] = 999999.0f; } } - v->min_full_det_buffering_time = 999999.0; + v->min_full_det_buffering_time = 999999.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->full_det_buffering_time_y[k] < v->min_full_det_buffering_time) { v->min_full_det_buffering_time = v->full_det_buffering_time_y[k]; @@ -1364,76 +1227,71 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k]; } } - v->average_read_bandwidth_gbyte_per_second = 0.0; + v->average_read_bandwidth_gbyte_per_second = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->dcc_enable[k] == dcn_bw_yes) { - v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / v->dcc_rate[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / v->dcc_rate[k] / 1000.0; - } - else { - v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / 1000.0; + v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / v->dcc_rate[k] / 1000.0f + v->read_bandwidth_plane_chroma[k] / v->dcc_rate[k] / 1000.0f; + } else { + v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0f + v->read_bandwidth_plane_chroma[k] / 1000.0f; } if (v->dcc_enable[k] == dcn_bw_yes) { - v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 256.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 256.0; + v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0f / 256.0f + v->read_bandwidth_plane_chroma[k] / 1000.0f / 256.0f; } if (v->pte_enable == dcn_bw_yes) { - v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 512.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 512.0; + v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0f / 512.0f + v->read_bandwidth_plane_chroma[k] / 1000.0f / 512.0f; } } - v->part_of_burst_that_fits_in_rob =dcn_bw_min2(v->min_full_det_buffering_time * v->total_data_read_bandwidth, v->rob_buffer_size_in_kbyte * 1024.0 * v->total_data_read_bandwidth / (v->average_read_bandwidth_gbyte_per_second * 1000.0)); - v->stutter_burst_time = v->part_of_burst_that_fits_in_rob * (v->average_read_bandwidth_gbyte_per_second * 1000.0) / v->total_data_read_bandwidth / v->return_bw + (v->min_full_det_buffering_time * v->total_data_read_bandwidth - v->part_of_burst_that_fits_in_rob) / (v->dcfclk * 64.0); - if (v->total_active_writeback == 0.0) { - v->stutter_efficiency_not_including_vblank = (1.0 - (v->sr_exit_time + v->stutter_burst_time) / v->min_full_det_buffering_time) * 100.0; + v->part_of_burst_that_fits_in_rob = dcn_bw_min2(v->min_full_det_buffering_time * v->total_data_read_bandwidth, v->rob_buffer_size_in_kbyte * 1024.0f * v->total_data_read_bandwidth / (v->average_read_bandwidth_gbyte_per_second * 1000.0f)); + v->stutter_burst_time = v->part_of_burst_that_fits_in_rob * (v->average_read_bandwidth_gbyte_per_second * 1000.0f) / v->total_data_read_bandwidth / v->return_bw + (v->min_full_det_buffering_time * v->total_data_read_bandwidth - v->part_of_burst_that_fits_in_rob) / (v->dcfclk * 64.0f); + if (v->total_active_writeback == 0.0f) { + v->stutter_efficiency_not_including_vblank = (1.0f - (v->sr_exit_time + v->stutter_burst_time) / v->min_full_det_buffering_time) * 100.0f; + } else { + v->stutter_efficiency_not_including_vblank = 0.0f; } - else { - v->stutter_efficiency_not_including_vblank = 0.0; - } - v->smallest_vblank = 999999.0; + v->smallest_vblank = 999999.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) { v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k] / v->pixel_clock[k]; + } else { + v->v_blank_time = 0.0f; } - else { - v->v_blank_time = 0.0; - } - v->smallest_vblank =dcn_bw_min2(v->smallest_vblank, v->v_blank_time); + v->smallest_vblank = dcn_bw_min2(v->smallest_vblank, v->v_blank_time); } - v->stutter_efficiency = (v->stutter_efficiency_not_including_vblank / 100.0 * (v->frame_time_for_min_full_det_buffering_time - v->smallest_vblank) + v->smallest_vblank) / v->frame_time_for_min_full_det_buffering_time * 100.0; + v->stutter_efficiency = (v->stutter_efficiency_not_including_vblank / 100.0f * (v->frame_time_for_min_full_det_buffering_time - v->smallest_vblank) + v->smallest_vblank) / v->frame_time_for_min_full_det_buffering_time * 100.0f; /*dcfclk deep sleep*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->byte_per_pixel_detc[k] > 0.0) { - v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 32.0 / v->display_pipe_line_delivery_time_luma[k], 1.1 * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 32.0 / v->display_pipe_line_delivery_time_chroma[k]); + if (v->byte_per_pixel_detc[k] > 0.0f) { + v->dcfclk_deep_sleep_per_plane[k] = dcn_bw_max2(1.1f * v->swath_width_y[k] * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / 32.0f / v->display_pipe_line_delivery_time_luma[k], 1.1f * v->swath_width_y[k] / 2.0f * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / 32.0f / v->display_pipe_line_delivery_time_chroma[k]); + } else { + v->dcfclk_deep_sleep_per_plane[k] = 1.1f * v->swath_width_y[k] * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / 64.0f / v->display_pipe_line_delivery_time_luma[k]; } - else { - v->dcfclk_deep_sleep_per_plane[k] = 1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 64.0 / v->display_pipe_line_delivery_time_luma[k]; - } - v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(v->dcfclk_deep_sleep_per_plane[k], v->pixel_clock[k] / 16.0); + v->dcfclk_deep_sleep_per_plane[k] = dcn_bw_max2(v->dcfclk_deep_sleep_per_plane[k], v->pixel_clock[k] / 16.0f); } - v->dcf_clk_deep_sleep = 8.0; + v->dcf_clk_deep_sleep = 8.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->dcf_clk_deep_sleep =dcn_bw_max2(v->dcf_clk_deep_sleep, v->dcfclk_deep_sleep_per_plane[k]); + v->dcf_clk_deep_sleep = dcn_bw_max2(v->dcf_clk_deep_sleep, v->dcfclk_deep_sleep_per_plane[k]); } /*stutter watermark*/ - v->stutter_exit_watermark = v->sr_exit_time + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency + 10.0 / v->dcf_clk_deep_sleep; + v->stutter_exit_watermark = v->sr_exit_time + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency + 10.0f / v->dcf_clk_deep_sleep; v->stutter_enter_plus_exit_watermark = v->sr_enter_plus_exit_time + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency; /*urgent latency supported*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]); + v->effective_det_plus_lb_lines_luma = dcn_bw_floor2(v->lines_in_dety[k] + dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]); v->urgent_latency_support_us_luma = v->effective_det_plus_lb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_det_plus_lb_lines_luma * v->swath_width_y[k] * v->byte_per_pixel_dety[k] / (v->return_bw / v->dpp_per_plane[k]); - if (v->byte_per_pixel_detc[k] > 0.0) { - v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]); - v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_det_plus_lb_lines_chroma * (v->swath_width_y[k] / 2.0) * v->byte_per_pixel_detc[k] / (v->return_bw / v->dpp_per_plane[k]); - v->urgent_latency_support_us[k] =dcn_bw_min2(v->urgent_latency_support_us_luma, v->urgent_latency_support_us_chroma); - } - else { + if (v->byte_per_pixel_detc[k] > 0.0f) { + v->effective_det_plus_lb_lines_chroma = dcn_bw_floor2(v->lines_in_detc[k] + dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]); + v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0f) - v->effective_det_plus_lb_lines_chroma * (v->swath_width_y[k] / 2.0f) * v->byte_per_pixel_detc[k] / (v->return_bw / v->dpp_per_plane[k]); + v->urgent_latency_support_us[k] = dcn_bw_min2(v->urgent_latency_support_us_luma, v->urgent_latency_support_us_chroma); + } else { v->urgent_latency_support_us[k] = v->urgent_latency_support_us_luma; } } - v->min_urgent_latency_support_us = 999999.0; + v->min_urgent_latency_support_us = 999999.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->min_urgent_latency_support_us =dcn_bw_min2(v->min_urgent_latency_support_us, v->urgent_latency_support_us[k]); + v->min_urgent_latency_support_us = dcn_bw_min2(v->min_urgent_latency_support_us, v->urgent_latency_support_us[k]); } /*non-urgent latency tolerance*/ @@ -1443,195 +1301,165 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan for (k = 0; k <= v->number_of_active_planes - 1; k++) { if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->block_height256_bytes_y = 1.0; + v->block_height256_bytes_y = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { + v->block_height256_bytes_y = 4.0f; + } else { + v->block_height256_bytes_y = 8.0f; } - else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->block_height256_bytes_y = 4.0; - } - else { - v->block_height256_bytes_y = 8.0; - } - v->block_height256_bytes_c = 0.0; - } - else { + v->block_height256_bytes_c = 0.0f; + } else { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->block_height256_bytes_y = 1.0; - v->block_height256_bytes_c = 1.0; - } - else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->block_height256_bytes_y = 16.0; - v->block_height256_bytes_c = 8.0; - } - else { - v->block_height256_bytes_y = 8.0; - v->block_height256_bytes_c = 8.0; + v->block_height256_bytes_y = 1.0f; + v->block_height256_bytes_c = 1.0f; + } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { + v->block_height256_bytes_y = 16.0f; + v->block_height256_bytes_c = 8.0f; + } else { + v->block_height256_bytes_y = 8.0f; + v->block_height256_bytes_c = 8.0f; } } if (v->dcc_enable[k] == dcn_bw_yes) { - v->meta_request_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (8.0 * v->block_height256_bytes_y); - v->meta_surf_width_y =dcn_bw_ceil2(v->swath_width_y[k] - 1.0, v->meta_request_width_y) + v->meta_request_width_y; - v->meta_surf_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, 8.0 * v->block_height256_bytes_y) + 8.0 * v->block_height256_bytes_y; + v->meta_request_width_y = 64.0f * 256.0f / dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / (8.0f * v->block_height256_bytes_y); + v->meta_surf_width_y = dcn_bw_ceil2(v->swath_width_y[k] - 1.0f, v->meta_request_width_y) + v->meta_request_width_y; + v->meta_surf_height_y = dcn_bw_ceil2(v->viewport_height[k] - 1.0f, 8.0f * v->block_height256_bytes_y) + 8.0f * v->block_height256_bytes_y; if (v->pte_enable == dcn_bw_yes) { - v->meta_pte_bytes_frame_y = (dcn_bw_ceil2((v->meta_surf_width_y * v->meta_surf_height_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; - } - else { - v->meta_pte_bytes_frame_y = 0.0; + v->meta_pte_bytes_frame_y = (dcn_bw_ceil2((v->meta_surf_width_y * v->meta_surf_height_y * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / 256.0f - 4096.0f) / 8.0f / 4096.0f, 1.0f) + 1) * 64.0f; + } else { + v->meta_pte_bytes_frame_y = 0.0f; } if (v->source_scan[k] == dcn_bw_hor) { - v->meta_row_byte_y = v->meta_surf_width_y * 8.0 * v->block_height256_bytes_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0; + v->meta_row_byte_y = v->meta_surf_width_y * 8.0f * v->block_height256_bytes_y * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / 256.0f; + } else { + v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / 256.0f; } - else { - v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0; - } - } - else { - v->meta_pte_bytes_frame_y = 0.0; - v->meta_row_byte_y = 0.0; + } else { + v->meta_pte_bytes_frame_y = 0.0f; + v->meta_row_byte_y = 0.0f; } if (v->pte_enable == dcn_bw_yes) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->macro_tile_size_byte_y = 256.0; - v->macro_tile_height_y = 1.0; + v->macro_tile_size_byte_y = 256.0f; + v->macro_tile_height_y = 1.0f; + } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { + v->macro_tile_size_byte_y = 4096.0f; + v->macro_tile_height_y = 4.0f * v->block_height256_bytes_y; + } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { + v->macro_tile_size_byte_y = 64.0f * 1024; + v->macro_tile_height_y = 16.0f * v->block_height256_bytes_y; + } else { + v->macro_tile_size_byte_y = 256.0f * 1024; + v->macro_tile_height_y = 32.0f * v->block_height256_bytes_y; } - else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { - v->macro_tile_size_byte_y = 4096.0; - v->macro_tile_height_y = 4.0 * v->block_height256_bytes_y; - } - else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { - v->macro_tile_size_byte_y = 64.0 * 1024; - v->macro_tile_height_y = 16.0 * v->block_height256_bytes_y; - } - else { - v->macro_tile_size_byte_y = 256.0 * 1024; - v->macro_tile_height_y = 32.0 * v->block_height256_bytes_y; - } - if (v->macro_tile_size_byte_y <= 65536.0) { + if (v->macro_tile_size_byte_y <= 65536.0f) { v->pixel_pte_req_height_y = v->macro_tile_height_y; + } else { + v->pixel_pte_req_height_y = 16.0f * v->block_height256_bytes_y; } - else { - v->pixel_pte_req_height_y = 16.0 * v->block_height256_bytes_y; - } - v->pixel_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / v->pixel_pte_req_height_y * 8; + v->pixel_pte_req_width_y = 4096.0f / dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / v->pixel_pte_req_height_y * 8; if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_y / v->swath_width_y[k], 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1); + v->pixel_pte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->swath_width_y[k] * dcn_bw_min2(128.0f, dcn_bw_pow(2.0f, dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_y / v->swath_width_y[k], 2.0f), 1.0f))) - 1.0f) / v->pixel_pte_req_width_y, 1.0f) + 1); + } else if (v->source_scan[k] == dcn_bw_hor) { + v->pixel_pte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->swath_width_y[k] - 1.0f) / v->pixel_pte_req_width_y, 1.0f) + 1); + } else { + v->pixel_pte_bytes_per_row_y = 64.0f * (dcn_bw_ceil2((v->viewport_height[k] - 1.0f) / v->pixel_pte_req_height_y, 1.0f) + 1); } - else if (v->source_scan[k] == dcn_bw_hor) { - v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1); - } - else { - v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->pixel_pte_req_height_y, 1.0) + 1); - } - } - else { - v->pixel_pte_bytes_per_row_y = 0.0; + } else { + v->pixel_pte_bytes_per_row_y = 0.0f; } if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { if (v->dcc_enable[k] == dcn_bw_yes) { - v->meta_request_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (8.0 * v->block_height256_bytes_c); - v->meta_surf_width_c =dcn_bw_ceil2(v->swath_width_y[k] / 2.0 - 1.0, v->meta_request_width_c) + v->meta_request_width_c; - v->meta_surf_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, 8.0 * v->block_height256_bytes_c) + 8.0 * v->block_height256_bytes_c; + v->meta_request_width_c = 64.0f * 256.0f / dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / (8.0f * v->block_height256_bytes_c); + v->meta_surf_width_c = dcn_bw_ceil2(v->swath_width_y[k] / 2.0f - 1.0f, v->meta_request_width_c) + v->meta_request_width_c; + v->meta_surf_height_c = dcn_bw_ceil2(v->viewport_height[k] / 2.0f - 1.0f, 8.0f * v->block_height256_bytes_c) + 8.0f * v->block_height256_bytes_c; if (v->pte_enable == dcn_bw_yes) { - v->meta_pte_bytes_frame_c = (dcn_bw_ceil2((v->meta_surf_width_c * v->meta_surf_height_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; - } - else { - v->meta_pte_bytes_frame_c = 0.0; + v->meta_pte_bytes_frame_c = (dcn_bw_ceil2((v->meta_surf_width_c * v->meta_surf_height_c * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / 256.0f - 4096.0f) / 8.0f / 4096.0f, 1.0f) + 1) * 64.0f; + } else { + v->meta_pte_bytes_frame_c = 0.0f; } if (v->source_scan[k] == dcn_bw_hor) { - v->meta_row_byte_c = v->meta_surf_width_c * 8.0 * v->block_height256_bytes_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0; + v->meta_row_byte_c = v->meta_surf_width_c * 8.0f * v->block_height256_bytes_c * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / 256.0f; + } else { + v->meta_row_byte_c = v->meta_surf_height_c * v->meta_request_width_c * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / 256.0f; } - else { - v->meta_row_byte_c = v->meta_surf_height_c * v->meta_request_width_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0; - } - } - else { - v->meta_pte_bytes_frame_c = 0.0; - v->meta_row_byte_c = 0.0; + } else { + v->meta_pte_bytes_frame_c = 0.0f; + v->meta_row_byte_c = 0.0f; } if (v->pte_enable == dcn_bw_yes) { if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->macro_tile_size_bytes_c = 256.0; - v->macro_tile_height_c = 1.0; + v->macro_tile_size_bytes_c = 256.0f; + v->macro_tile_height_c = 1.0f; + } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { + v->macro_tile_size_bytes_c = 4096.0f; + v->macro_tile_height_c = 4.0f * v->block_height256_bytes_c; + } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { + v->macro_tile_size_bytes_c = 64.0f * 1024; + v->macro_tile_height_c = 16.0f * v->block_height256_bytes_c; + } else { + v->macro_tile_size_bytes_c = 256.0f * 1024; + v->macro_tile_height_c = 32.0f * v->block_height256_bytes_c; } - else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { - v->macro_tile_size_bytes_c = 4096.0; - v->macro_tile_height_c = 4.0 * v->block_height256_bytes_c; - } - else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { - v->macro_tile_size_bytes_c = 64.0 * 1024; - v->macro_tile_height_c = 16.0 * v->block_height256_bytes_c; - } - else { - v->macro_tile_size_bytes_c = 256.0 * 1024; - v->macro_tile_height_c = 32.0 * v->block_height256_bytes_c; - } - if (v->macro_tile_size_bytes_c <= 65536.0) { + if (v->macro_tile_size_bytes_c <= 65536.0f) { v->pixel_pte_req_height_c = v->macro_tile_height_c; + } else { + v->pixel_pte_req_height_c = 16.0f * v->block_height256_bytes_c; } - else { - v->pixel_pte_req_height_c = 16.0 * v->block_height256_bytes_c; - } - v->pixel_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / v->pixel_pte_req_height_c * 8; + v->pixel_pte_req_width_c = 4096.0f / dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / v->pixel_pte_req_height_c * 8; if (v->source_surface_mode[k] == dcn_bw_sw_linear) { - v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_c / (v->swath_width_y[k] / 2.0), 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1); - } - else if (v->source_scan[k] == dcn_bw_hor) { - v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1); - } - else { - v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->pixel_pte_req_height_c, 1.0) + 1); + v->pixel_pte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0f * dcn_bw_min2(128.0f, dcn_bw_pow(2.0f, dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_c / (v->swath_width_y[k] / 2.0f), 2.0f), 1.0f))) - 1.0f) / v->pixel_pte_req_width_c, 1.0f) + 1); + } else if (v->source_scan[k] == dcn_bw_hor) { + v->pixel_pte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0f - 1.0f) / v->pixel_pte_req_width_c, 1.0f) + 1); + } else { + v->pixel_pte_bytes_per_row_c = 64.0f * (dcn_bw_ceil2((v->viewport_height[k] / 2.0f - 1.0f) / v->pixel_pte_req_height_c, 1.0f) + 1); } + } else { + v->pixel_pte_bytes_per_row_c = 0.0f; } - else { - v->pixel_pte_bytes_per_row_c = 0.0; - } - } - else { - v->pixel_pte_bytes_per_row_c = 0.0; - v->meta_pte_bytes_frame_c = 0.0; - v->meta_row_byte_c = 0.0; + } else { + v->pixel_pte_bytes_per_row_c = 0.0f; + v->meta_pte_bytes_frame_c = 0.0f; + v->meta_row_byte_c = 0.0f; } v->pixel_pte_bytes_per_row[k] = v->pixel_pte_bytes_per_row_y + v->pixel_pte_bytes_per_row_c; v->meta_pte_bytes_frame[k] = v->meta_pte_bytes_frame_y + v->meta_pte_bytes_frame_c; v->meta_row_byte[k] = v->meta_row_byte_y + v->meta_row_byte_c; - v->v_init_pre_fill_y[k] =dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0, 1.0); - v->max_num_swath_y[k] =dcn_bw_ceil2((v->v_init_pre_fill_y[k] - 1.0) / v->swath_height_y[k], 1.0) + 1; - if (v->v_init_pre_fill_y[k] > 1.0) { - v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] - 2.0), v->swath_height_y[k]); + v->v_init_pre_fill_y[k] = dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0f + v->interlace_output[k] * 0.5f * v->v_ratio[k]) / 2.0f, 1.0f); + v->max_num_swath_y[k] = dcn_bw_ceil2((v->v_init_pre_fill_y[k] - 1.0f) / v->swath_height_y[k], 1.0f) + 1; + if (v->v_init_pre_fill_y[k] > 1.0f) { + v->max_partial_swath_y = dcn_bw_mod((v->v_init_pre_fill_y[k] - 2.0f), v->swath_height_y[k]); + } else { + v->max_partial_swath_y = dcn_bw_mod((v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0f), v->swath_height_y[k]); } - else { - v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0), v->swath_height_y[k]); - } - v->max_partial_swath_y =dcn_bw_max2(1.0, v->max_partial_swath_y); + v->max_partial_swath_y = dcn_bw_max2(1.0f, v->max_partial_swath_y); v->prefetch_source_lines_y[k] = v->max_num_swath_y[k] * v->swath_height_y[k] + v->max_partial_swath_y; if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { - v->v_init_pre_fill_c[k] =dcn_bw_floor2((v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0, 1.0); - v->max_num_swath_c[k] =dcn_bw_ceil2((v->v_init_pre_fill_c[k] - 1.0) / v->swath_height_c[k], 1.0) + 1; - if (v->v_init_pre_fill_c[k] > 1.0) { - v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] - 2.0), v->swath_height_c[k]); + v->v_init_pre_fill_c[k] = dcn_bw_floor2((v->v_ratio[k] / 2.0f + v->vtaps[k] + 1.0f + v->interlace_output[k] * 0.5f * v->v_ratio[k] / 2.0f) / 2.0f, 1.0f); + v->max_num_swath_c[k] = dcn_bw_ceil2((v->v_init_pre_fill_c[k] - 1.0f) / v->swath_height_c[k], 1.0f) + 1; + if (v->v_init_pre_fill_c[k] > 1.0f) { + v->max_partial_swath_c = dcn_bw_mod((v->v_init_pre_fill_c[k] - 2.0f), v->swath_height_c[k]); + } else { + v->max_partial_swath_c = dcn_bw_mod((v->v_init_pre_fill_c[k] + v->swath_height_c[k] - 2.0f), v->swath_height_c[k]); } - else { - v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] + v->swath_height_c[k] - 2.0), v->swath_height_c[k]); - } - v->max_partial_swath_c =dcn_bw_max2(1.0, v->max_partial_swath_c); - } - else { - v->max_num_swath_c[k] = 0.0; - v->max_partial_swath_c = 0.0; + v->max_partial_swath_c = dcn_bw_max2(1.0f, v->max_partial_swath_c); + } else { + v->max_num_swath_c[k] = 0.0f; + v->max_partial_swath_c = 0.0f; } v->prefetch_source_lines_c[k] = v->max_num_swath_c[k] * v->swath_height_c[k] + v->max_partial_swath_c; } - v->t_calc = 24.0 / v->dcf_clk_deep_sleep; + v->t_calc = 24.0f / v->dcf_clk_deep_sleep; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes) { - v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0; - } - else { - v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0; + v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0f; + } else { + v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0f; } } - v->next_prefetch_mode = 0.0; + v->next_prefetch_mode = 0.0f; do { - v->v_startup_lines = 13.0; + v->v_startup_lines = 13.0f; do { v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw = dcn_bw_yes; v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 = dcn_bw_no; @@ -1640,159 +1468,142 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan v->destination_line_times_for_prefetch_less_than2 = dcn_bw_no; v->prefetch_mode = v->next_prefetch_mode; for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk; - if (v->dpp_per_plane[k] > 1.0) { - v->dstx_after_scaler = v->dstx_after_scaler + v->scaler_rec_out_width[k] / 2.0; + v->dstx_after_scaler = 90.0f * v->pixel_clock[k] / v->dppclk + 42.0f * v->pixel_clock[k] / v->dispclk; + if (v->dpp_per_plane[k] > 1.0f) { + v->dstx_after_scaler = v->dstx_after_scaler + v->scaler_rec_out_width[k] / 2.0f; } if (v->output_format[k] == dcn_bw_420) { - v->dsty_after_scaler = 1.0; + v->dsty_after_scaler = 1.0f; + } else { + v->dsty_after_scaler = 0.0f; } - else { - v->dsty_after_scaler = 0.0; - } - v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); - v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk); - v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k]; - v->v_ready_offset_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k]; + v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0f, 1.0f); + v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0f / v->dppclk + 3.0f / v->dispclk); + v->v_update_width_pix[k] = (14.0f / v->dcf_clk_deep_sleep + 12.0f / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k]; + v->v_ready_offset_pix[k] = dcn_bw_max2(150.0f / v->dppclk, v->total_repeater_delay_time + 20.0f / v->dcf_clk_deep_sleep + 10.0f / v->dppclk) * v->pixel_clock[k]; v->t_setup = (v->v_update_offset_pix[k] + v->v_update_width_pix[k] + v->v_ready_offset_pix[k]) / v->pixel_clock[k]; - v->v_startup[k] =dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]); - if (v->prefetch_mode == 0.0) { - v->t_wait =dcn_bw_max3(v->dram_clock_change_latency + v->urgent_latency, v->sr_enter_plus_exit_time, v->urgent_latency); - } - else if (v->prefetch_mode == 1.0) { - v->t_wait =dcn_bw_max2(v->sr_enter_plus_exit_time, v->urgent_latency); - } - else { + v->v_startup[k] = dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]); + if (v->prefetch_mode == 0.0f) { + v->t_wait = dcn_bw_max3(v->dram_clock_change_latency + v->urgent_latency, v->sr_enter_plus_exit_time, v->urgent_latency); + } else if (v->prefetch_mode == 1.0f) { + v->t_wait = dcn_bw_max2(v->sr_enter_plus_exit_time, v->urgent_latency); + } else { v->t_wait = v->urgent_latency; } - v->destination_lines_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->v_startup[k] - v->t_wait / (v->htotal[k] / v->pixel_clock[k]) - (v->t_calc + v->t_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dsty_after_scaler + v->dstx_after_scaler / v->htotal[k]) + 0.125), 1.0) / 4; - if (v->destination_lines_for_prefetch[k] > 0.0) { - v->prefetch_bandwidth[k] = (v->meta_pte_bytes_frame[k] + 2.0 * v->meta_row_byte[k] + 2.0 * v->pixel_pte_bytes_per_row[k] + v->prefetch_source_lines_y[k] * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)) / (v->destination_lines_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]); - } - else { - v->prefetch_bandwidth[k] = 999999.0; + v->destination_lines_for_prefetch[k] = dcn_bw_floor2(4.0f * (v->v_startup[k] - v->t_wait / (v->htotal[k] / v->pixel_clock[k]) - (v->t_calc + v->t_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dsty_after_scaler + v->dstx_after_scaler / v->htotal[k]) + 0.125f), 1.0f) / 4; + if (v->destination_lines_for_prefetch[k] > 0.0f) { + v->prefetch_bandwidth[k] = (v->meta_pte_bytes_frame[k] + 2.0f * v->meta_row_byte[k] + 2.0f * v->pixel_pte_bytes_per_row[k] + v->prefetch_source_lines_y[k] * v->swath_width_y[k] * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) + v->prefetch_source_lines_c[k] * v->swath_width_y[k] / 2.0f * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f)) / (v->destination_lines_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]); + } else { + v->prefetch_bandwidth[k] = 999999.0f; } } v->bandwidth_available_for_immediate_flip = v->return_bw; for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->bandwidth_available_for_immediate_flip = v->bandwidth_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->prefetch_bandwidth[k]); } - v->tot_immediate_flip_bytes = 0.0; + v->tot_immediate_flip_bytes = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { v->tot_immediate_flip_bytes = v->tot_immediate_flip_bytes + v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]; } } - v->max_rd_bandwidth = 0.0; + v->max_rd_bandwidth = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) { if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { - v->time_for_fetching_meta_pte =dcn_bw_max5(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->meta_pte_bytes_frame[k] * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0); - } - else { - v->time_for_fetching_meta_pte =dcn_bw_max3(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0); + v->time_for_fetching_meta_pte = dcn_bw_max5(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->meta_pte_bytes_frame[k] * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0f); + } else { + v->time_for_fetching_meta_pte = dcn_bw_max3(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0f); } + } else { + v->time_for_fetching_meta_pte = v->htotal[k] / v->pixel_clock[k] / 4.0f; } - else { - v->time_for_fetching_meta_pte = v->htotal[k] / v->pixel_clock[k] / 4.0; - } - v->destination_lines_to_request_vm_inv_blank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_meta_pte / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; + v->destination_lines_to_request_vm_inv_blank[k] = dcn_bw_floor2(4.0f * (v->time_for_fetching_meta_pte / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; if ((v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes)) { if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { - v->time_for_fetching_row_in_vblank =dcn_bw_max5((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, 2.0 * v->urgent_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); - } - else { - v->time_for_fetching_row_in_vblank =dcn_bw_max3((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); + v->time_for_fetching_row_in_vblank = dcn_bw_max5((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, 2.0f * v->urgent_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); + } else { + v->time_for_fetching_row_in_vblank = dcn_bw_max3((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); } + } else { + v->time_for_fetching_row_in_vblank = dcn_bw_max2(v->urgent_extra_latency - v->time_for_fetching_meta_pte, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); } - else { - v->time_for_fetching_row_in_vblank =dcn_bw_max2(v->urgent_extra_latency - v->time_for_fetching_meta_pte, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); - } - v->destination_lines_to_request_row_in_vblank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_row_in_vblank / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; + v->destination_lines_to_request_row_in_vblank[k] = dcn_bw_floor2(4.0f * (v->time_for_fetching_row_in_vblank / (v->htotal[k] / v->pixel_clock[k]) + 0.125f), 1.0f) / 4; v->lines_to_request_prefetch_pixel_data = v->destination_lines_for_prefetch[k] - v->destination_lines_to_request_vm_inv_blank[k] - v->destination_lines_to_request_row_in_vblank[k]; - if (v->lines_to_request_prefetch_pixel_data > 0.0) { + if (v->lines_to_request_prefetch_pixel_data > 0.0f) { v->v_ratio_prefetch_y[k] = v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data; - if ((v->swath_height_y[k] > 4.0)) { - if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_y[k] - 3.0) / 2.0) { - v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], v->max_num_swath_y[k] * v->swath_height_y[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_y[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_prefetch_y[k] = 999999.0; + if ((v->swath_height_y[k] > 4.0f)) { + if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_y[k] - 3.0f) / 2.0f) { + v->v_ratio_prefetch_y[k] = dcn_bw_max2(v->v_ratio_prefetch_y[k], v->max_num_swath_y[k] * v->swath_height_y[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_y[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_prefetch_y[k] = 999999.0f; } } + } else { + v->v_ratio_prefetch_y[k] = 999999.0f; } - else { - v->v_ratio_prefetch_y[k] = 999999.0; - } - v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0); - if (v->lines_to_request_prefetch_pixel_data > 0.0) { + v->v_ratio_prefetch_y[k] = dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0f); + if (v->lines_to_request_prefetch_pixel_data > 0.0f) { v->v_ratio_prefetch_c[k] = v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data; - if ((v->swath_height_c[k] > 4.0)) { - if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_c[k] - 3.0) / 2.0) { - v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], v->max_num_swath_c[k] * v->swath_height_c[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_c[k] - 3.0) / 2.0)); - } - else { - v->v_ratio_prefetch_c[k] = 999999.0; + if ((v->swath_height_c[k] > 4.0f)) { + if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_c[k] - 3.0f) / 2.0f) { + v->v_ratio_prefetch_c[k] = dcn_bw_max2(v->v_ratio_prefetch_c[k], v->max_num_swath_c[k] * v->swath_height_c[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_c[k] - 3.0f) / 2.0f)); + } else { + v->v_ratio_prefetch_c[k] = 999999.0f; } } + } else { + v->v_ratio_prefetch_c[k] = 999999.0f; } - else { - v->v_ratio_prefetch_c[k] = 999999.0; + v->v_ratio_prefetch_c[k] = dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0f); + if (v->lines_to_request_prefetch_pixel_data > 0.0f) { + v->required_prefetch_pix_data_bw = v->dpp_per_plane[k] * (v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) + v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / 2.0f) * v->swath_width_y[k] / (v->htotal[k] / v->pixel_clock[k]); + } else { + v->required_prefetch_pix_data_bw = 999999.0f; } - v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0); - if (v->lines_to_request_prefetch_pixel_data > 0.0) { - v->required_prefetch_pix_data_bw = v->dpp_per_plane[k] * (v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 2.0) * v->swath_width_y[k] / (v->htotal[k] / v->pixel_clock[k]); - } - else { - v->required_prefetch_pix_data_bw = 999999.0; - } - v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->required_prefetch_pix_data_bw); + v->max_rd_bandwidth = v->max_rd_bandwidth + dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->required_prefetch_pix_data_bw); if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { - v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->meta_pte_bytes_frame[k] / (v->destination_lines_to_request_vm_inv_blank[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / (v->destination_lines_to_request_row_in_vblank[k] * v->htotal[k] / v->pixel_clock[k])); + v->max_rd_bandwidth = v->max_rd_bandwidth + dcn_bw_max2(v->meta_pte_bytes_frame[k] / (v->destination_lines_to_request_vm_inv_blank[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / (v->destination_lines_to_request_row_in_vblank[k] * v->htotal[k] / v->pixel_clock[k])); } - if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) { + if (v->v_ratio_prefetch_y[k] > 4.0f || v->v_ratio_prefetch_c[k] > 4.0f) { v->v_ratio_prefetch_more_than4 = dcn_bw_yes; } - if (v->destination_lines_for_prefetch[k] < 2.0) { + if (v->destination_lines_for_prefetch[k] < 2.0f) { v->destination_line_times_for_prefetch_less_than2 = dcn_bw_yes; } if (v->max_vstartup_lines[k] > v->v_startup_lines) { if (v->required_prefetch_pix_data_bw > (v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k])) { v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw = dcn_bw_no; } - if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) { + if (v->v_ratio_prefetch_y[k] > 4.0f || v->v_ratio_prefetch_c[k] > 4.0f) { v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 = dcn_bw_yes; } - if (v->destination_lines_for_prefetch[k] < 2.0) { + if (v->destination_lines_for_prefetch[k] < 2.0f) { v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 = dcn_bw_yes; } } } if (v->max_rd_bandwidth <= v->return_bw && v->v_ratio_prefetch_more_than4 == dcn_bw_no && v->destination_line_times_for_prefetch_less_than2 == dcn_bw_no) { v->prefetch_mode_supported = dcn_bw_yes; - } - else { + } else { v->prefetch_mode_supported = dcn_bw_no; } - v->v_startup_lines = v->v_startup_lines + 1.0; + v->v_startup_lines = v->v_startup_lines + 1.0f; } while (!(v->prefetch_mode_supported == dcn_bw_yes || (v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw == dcn_bw_yes && v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 == dcn_bw_no && v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 == dcn_bw_no))); - v->next_prefetch_mode = v->next_prefetch_mode + 1.0; - } while (!(v->prefetch_mode_supported == dcn_bw_yes || v->prefetch_mode == 2.0)); + v->next_prefetch_mode = v->next_prefetch_mode + 1.0f; + } while (!(v->prefetch_mode_supported == dcn_bw_yes || v->prefetch_mode == 2.0f)); for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->v_ratio_prefetch_y[k] <= 1.0) { + if (v->v_ratio_prefetch_y[k] <= 1.0f) { v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k]; - } - else { + } else { v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; } - if (v->byte_per_pixel_detc[k] == 0.0) { - v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0; - } - else { - if (v->v_ratio_prefetch_c[k] <= 1.0) { + if (v->byte_per_pixel_detc[k] == 0.0f) { + v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0f; + } else { + if (v->v_ratio_prefetch_c[k] <= 1.0f) { v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k]; - } - else { + } else { v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; } } @@ -1800,17 +1611,15 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan /*min ttuv_blank*/ for (k = 0; k <= v->number_of_active_planes - 1; k++) { - if (v->prefetch_mode == 0.0) { + if (v->prefetch_mode == 0.0f) { v->allow_dram_clock_change_during_vblank[k] = dcn_bw_yes; v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes; - v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max3(v->dram_clock_change_watermark, v->stutter_enter_plus_exit_watermark, v->urgent_watermark); - } - else if (v->prefetch_mode == 1.0) { + v->min_ttuv_blank[k] = v->t_calc + dcn_bw_max3(v->dram_clock_change_watermark, v->stutter_enter_plus_exit_watermark, v->urgent_watermark); + } else if (v->prefetch_mode == 1.0f) { v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no; v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes; - v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max2(v->stutter_enter_plus_exit_watermark, v->urgent_watermark); - } - else { + v->min_ttuv_blank[k] = v->t_calc + dcn_bw_max2(v->stutter_enter_plus_exit_watermark, v->urgent_watermark); + } else { v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no; v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_no; v->min_ttuv_blank[k] = v->t_calc + v->urgent_watermark; @@ -1818,115 +1627,102 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan } /*nb p-state/dram clock change support*/ - v->active_dp_ps = 0.0; + v->active_dp_ps = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->active_dp_ps = v->active_dp_ps + v->dpp_per_plane[k]; } for (k = 0; k <= v->number_of_active_planes - 1; k++) { - v->lb_latency_hiding_source_lines_y =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0); - v->lb_latency_hiding_source_lines_c =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0); + v->lb_latency_hiding_source_lines_y = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / dcn_bw_max2(v->h_ratio[k], 1.0f)), 1.0f)) - (v->vtaps[k] - 1.0f); + v->lb_latency_hiding_source_lines_c = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / 2.0f / dcn_bw_max2(v->h_ratio[k] / 2.0f, 1.0f)), 1.0f)) - (v->vta_pschroma[k] - 1.0f); v->effective_lb_latency_hiding_y = v->lb_latency_hiding_source_lines_y / v->v_ratio[k] * (v->htotal[k] / v->pixel_clock[k]); - v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c / (v->v_ratio[k] / 2.0) * (v->htotal[k] / v->pixel_clock[k]); - if (v->swath_width_y[k] > 2.0 * v->dpp_output_buffer_pixels) { + v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c / (v->v_ratio[k] / 2.0f) * (v->htotal[k] / v->pixel_clock[k]); + if (v->swath_width_y[k] > 2.0f * v->dpp_output_buffer_pixels) { v->dpp_output_buffer_lines_y = v->dpp_output_buffer_pixels / v->swath_width_y[k]; + } else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) { + v->dpp_output_buffer_lines_y = 0.5f; + } else { + v->dpp_output_buffer_lines_y = 1.0f; } - else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) { - v->dpp_output_buffer_lines_y = 0.5; - } - else { - v->dpp_output_buffer_lines_y = 1.0; - } - if (v->swath_width_y[k] / 2.0 > 2.0 * v->dpp_output_buffer_pixels) { - v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels / (v->swath_width_y[k] / 2.0); - } - else if (v->swath_width_y[k] / 2.0 > v->dpp_output_buffer_pixels) { - v->dpp_output_buffer_lines_c = 0.5; - } - else { - v->dpp_output_buffer_lines_c = 1.0; + if (v->swath_width_y[k] / 2.0f > 2.0f * v->dpp_output_buffer_pixels) { + v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels / (v->swath_width_y[k] / 2.0f); + } else if (v->swath_width_y[k] / 2.0f > v->dpp_output_buffer_pixels) { + v->dpp_output_buffer_lines_c = 0.5f; + } else { + v->dpp_output_buffer_lines_c = 1.0f; } v->dppopp_buffering_y = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_y + v->opp_output_buffer_lines); v->max_det_buffering_time_y = v->full_det_buffering_time_y[k] + (v->lines_in_dety[k] - v->lines_in_dety_rounded_down_to_swath[k]) / v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]); v->active_dram_clock_change_latency_margin_y = v->dppopp_buffering_y + v->effective_lb_latency_hiding_y + v->max_det_buffering_time_y - v->dram_clock_change_watermark; - if (v->active_dp_ps > 1.0) { - v->active_dram_clock_change_latency_margin_y = v->active_dram_clock_change_latency_margin_y - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]); + if (v->active_dp_ps > 1.0f) { + v->active_dram_clock_change_latency_margin_y = v->active_dram_clock_change_latency_margin_y - (1.0f - 1.0f / (v->active_dp_ps - 1.0f)) * v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]); } - if (v->byte_per_pixel_detc[k] > 0.0) { + if (v->byte_per_pixel_detc[k] > 0.0f) { v->dppopp_buffering_c = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_c + v->opp_output_buffer_lines); v->max_det_buffering_time_c = v->full_det_buffering_time_c[k] + (v->lines_in_detc[k] - v->lines_in_detc_rounded_down_to_swath[k]) / v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]); v->active_dram_clock_change_latency_margin_c = v->dppopp_buffering_c + v->effective_lb_latency_hiding_c + v->max_det_buffering_time_c - v->dram_clock_change_watermark; - if (v->active_dp_ps > 1.0) { - v->active_dram_clock_change_latency_margin_c = v->active_dram_clock_change_latency_margin_c - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]); + if (v->active_dp_ps > 1.0f) { + v->active_dram_clock_change_latency_margin_c = v->active_dram_clock_change_latency_margin_c - (1.0f - 1.0f / (v->active_dp_ps - 1.0f)) * v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]); } - v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin_y, v->active_dram_clock_change_latency_margin_c); - } - else { + v->active_dram_clock_change_latency_margin[k] = dcn_bw_min2(v->active_dram_clock_change_latency_margin_y, v->active_dram_clock_change_latency_margin_c); + } else { v->active_dram_clock_change_latency_margin[k] = v->active_dram_clock_change_latency_margin_y; } if (v->output_format[k] == dcn_bw_444) { - v->writeback_dram_clock_change_latency_margin = (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0) - v->writeback_dram_clock_change_watermark; - } - else { - v->writeback_dram_clock_change_latency_margin =dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])) - v->writeback_dram_clock_change_watermark; + v->writeback_dram_clock_change_latency_margin = (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0f / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0f) - v->writeback_dram_clock_change_watermark; + } else { + v->writeback_dram_clock_change_latency_margin = dcn_bw_min2(v->writeback_luma_buffer_size, 2.0f * v->writeback_chroma_buffer_size) * 1024.0f / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])) - v->writeback_dram_clock_change_watermark; } if (v->output[k] == dcn_bw_writeback) { - v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin[k], v->writeback_dram_clock_change_latency_margin); + v->active_dram_clock_change_latency_margin[k] = dcn_bw_min2(v->active_dram_clock_change_latency_margin[k], v->writeback_dram_clock_change_latency_margin); } } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->allow_dram_clock_change_during_vblank[k] == dcn_bw_yes) { v->v_blank_dram_clock_change_latency_margin[k] = (v->vtotal[k] - v->scaler_recout_height[k]) * (v->htotal[k] / v->pixel_clock[k]) -dcn_bw_max2(v->dram_clock_change_watermark, v->writeback_dram_clock_change_watermark); - } - else { - v->v_blank_dram_clock_change_latency_margin[k] = 0.0; + } else { + v->v_blank_dram_clock_change_latency_margin[k] = 0.0f; } } - v->min_active_dram_clock_change_margin = 999999.0; - v->v_blank_of_min_active_dram_clock_change_margin = 999999.0; - v->second_min_active_dram_clock_change_margin = 999999.0; + v->min_active_dram_clock_change_margin = 999999.0f; + v->v_blank_of_min_active_dram_clock_change_margin = 999999.0f; + v->second_min_active_dram_clock_change_margin = 999999.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->active_dram_clock_change_latency_margin[k] < v->min_active_dram_clock_change_margin) { v->second_min_active_dram_clock_change_margin = v->min_active_dram_clock_change_margin; v->min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k]; v->v_blank_of_min_active_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k]; - } - else if (v->active_dram_clock_change_latency_margin[k] < v->second_min_active_dram_clock_change_margin) { + } else if (v->active_dram_clock_change_latency_margin[k] < v->second_min_active_dram_clock_change_margin) { v->second_min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k]; } } - v->min_vblank_dram_clock_change_margin = 999999.0; + v->min_vblank_dram_clock_change_margin = 999999.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->min_vblank_dram_clock_change_margin > v->v_blank_dram_clock_change_latency_margin[k]) { v->min_vblank_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k]; } } if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) { - v->dram_clock_change_margin =dcn_bw_max2(v->min_active_dram_clock_change_margin, v->min_vblank_dram_clock_change_margin); - } - else if (v->v_blank_of_min_active_dram_clock_change_margin > v->min_active_dram_clock_change_margin) { - v->dram_clock_change_margin =dcn_bw_min2(v->second_min_active_dram_clock_change_margin, v->v_blank_of_min_active_dram_clock_change_margin); - } - else { + v->dram_clock_change_margin = dcn_bw_max2(v->min_active_dram_clock_change_margin, v->min_vblank_dram_clock_change_margin); + } else if (v->v_blank_of_min_active_dram_clock_change_margin > v->min_active_dram_clock_change_margin) { + v->dram_clock_change_margin = dcn_bw_min2(v->second_min_active_dram_clock_change_margin, v->v_blank_of_min_active_dram_clock_change_margin); + } else { v->dram_clock_change_margin = v->min_active_dram_clock_change_margin; } - if (v->min_active_dram_clock_change_margin > 0.0) { + if (v->min_active_dram_clock_change_margin > 0.0f) { v->dram_clock_change_support = dcn_bw_supported_in_v_active; - } - else if (v->dram_clock_change_margin > 0.0) { + } else if (v->dram_clock_change_margin > 0.0f) { v->dram_clock_change_support = dcn_bw_supported_in_v_blank; - } - else { + } else { v->dram_clock_change_support = dcn_bw_not_supported; } /*maximum bandwidth used*/ - v->wr_bandwidth = 0.0; + v->wr_bandwidth = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) { - v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0; - } - else if (v->output[k] == dcn_bw_writeback) { - v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5; + v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0f; + } else if (v->output[k] == dcn_bw_writeback) { + v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5f; } } v->max_used_bw = v->max_rd_bandwidth + v->wr_bandwidth; diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_math.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_math.c index cac72413a097..16b990147d1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_math.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_math.c @@ -76,12 +76,12 @@ float dcn_bw_floor2(const float arg, const float significance) } float dcn_bw_floor(const float arg) { - return ((int) (arg)); + return (float)((int)(arg)); } float dcn_bw_ceil(const float arg) { - return (int) (arg + 0.99999); + return (float)((int)(arg + 0.99999f)); } float dcn_bw_ceil2(const float arg, const float significance) @@ -107,7 +107,7 @@ float dcn_bw_pow(float a, float exp) /*ASSERT(exp == (int)exp);*/ if ((int)exp == 0) return 1; - temp = dcn_bw_pow(a, (int)(exp / 2)); + temp = dcn_bw_pow(a, (float)((int)(exp / 2))); if (((int)exp % 2) == 0) { return temp * temp; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c index 61553e24d53e..dcca23d53261 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c @@ -72,21 +72,21 @@ const struct dcn_soc_bounding_box dcn10_soc_defaults = { * Use these value if fused value doesn't make sense as earlier * part don't have correct value fused */ /* default DCF CLK DPM on RV*/ - .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5 */ - .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75 */ + .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5f */ + .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75f */ .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */ .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */ /* default DISP CLK voltage state on RV */ - .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25 */ - .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5 */ - .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75 */ - .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75 */ + .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25f */ + .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5f */ + .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75f */ + .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75f */ /* default DPP CLK voltage state on RV */ .max_dppclk_vmax0p9 = 720, /* MHz, = 3600/5 */ - .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25 */ - .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */ + .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25f */ + .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75f */ .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */ /* default PHY CLK voltage state on RV */ @@ -326,7 +326,7 @@ static void pipe_ctx_to_e2e_pipe_params ( * allow us to disable dcc on the fly without re-calculating WM * * extra overhead for DCC is quite small. for 1080p WM without - * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us) + * DCC is only 0.417fus lower (urgent goes from 6.979fus to 6.562fus) */ unsigned int bpe; @@ -396,18 +396,18 @@ static void pipe_ctx_to_e2e_pipe_params ( } input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; - input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; - input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; - input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; - if (input->scale_ratio_depth.vinit < 1.0) + input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0f; + input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0f; + input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0f; + if (input->scale_ratio_depth.vinit < 1.0f) input->scale_ratio_depth.vinit = 1; input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c; - input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0; - input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0; - input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0; - if (input->scale_ratio_depth.vinit_c < 1.0) + input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0f; + input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0f; + input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0f; + if (input->scale_ratio_depth.vinit_c < 1.0f) input->scale_ratio_depth.vinit_c = 1; switch (pipe->plane_res.scl_data.lb_params.depth) { case LB_PIXEL_DEPTH_30BPP: @@ -441,7 +441,7 @@ static void pipe_ctx_to_e2e_pipe_params ( - pipe->stream->timing.v_addressable - pipe->stream->timing.v_border_bottom - pipe->stream->timing.v_border_top; - input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0; + input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0f; input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; @@ -477,10 +477,10 @@ static void dcn_bw_calc_rq_dlg_ttu( for (i = 0; i < number_of_planes; i++) { total_active_bw += v->read_bandwidth[i]; total_prefetch_bw += v->prefetch_bandwidth[i]; - total_flip_bytes += v->total_immediate_flip_bytes[i]; + total_flip_bytes += (int)v->total_immediate_flip_bytes[i]; } dlg_sys_param->total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw); - if (dlg_sys_param->total_flip_bw < 0.0) + if (dlg_sys_param->total_flip_bw < 0.0f) dlg_sys_param->total_flip_bw = 0; dlg_sys_param->t_mclk_wm_us = v->dram_clock_change_watermark; @@ -494,7 +494,7 @@ static void dcn_bw_calc_rq_dlg_ttu( input->clks_cfg.dcfclk_mhz = v->dcfclk; input->clks_cfg.dispclk_mhz = v->dispclk; input->clks_cfg.dppclk_mhz = v->dppclk; - input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; + input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0f; input->clks_cfg.socclk_mhz = v->socclk; input->clks_cfg.voltage = v->voltage_level; // dc->dml.logger = pool->base.logger; @@ -533,13 +533,14 @@ static void split_stream_across_pipes( *secondary_pipe = *primary_pipe; - secondary_pipe->pipe_idx = pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)pipe_idx; secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; - secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; + secondary_pipe->plane_res.mpcc_inst = + (uint8_t)pool->dpps[secondary_pipe->pipe_idx]->inst; if (primary_pipe->bottom_pipe) { ASSERT(primary_pipe->bottom_pipe != secondary_pipe); secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; @@ -643,7 +644,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns && dc->debug.sr_exit_time_ns) { updated = true; - dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0; + dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0f; } if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000) @@ -651,13 +652,13 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) && dc->debug.sr_enter_plus_exit_time_ns) { updated = true; dc->dcn_soc->sr_enter_plus_exit_time = - dc->debug.sr_enter_plus_exit_time_ns / 1000.0; + dc->debug.sr_enter_plus_exit_time_ns / 1000.0f; } if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns && dc->debug.urgent_latency_ns) { updated = true; - dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0; + dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0f; } if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000) @@ -665,7 +666,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) && dc->debug.percent_of_ideal_drambw) { updated = true; dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency = - dc->debug.percent_of_ideal_drambw; + (float)dc->debug.percent_of_ideal_drambw; } if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000) @@ -673,7 +674,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) && dc->debug.dram_clock_change_latency_ns) { updated = true; dc->dcn_soc->dram_clock_change_latency = - dc->debug.dram_clock_change_latency_ns / 1000.0; + dc->debug.dram_clock_change_latency_ns / 1000.0f; } return updated; @@ -691,7 +692,7 @@ static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v) static void hack_force_pipe_split(struct dcn_bw_internal_vars *v, unsigned int pixel_rate_100hz) { - float pixel_rate_mhz = pixel_rate_100hz / 10000.0; + float pixel_rate_mhz = pixel_rate_100hz / 10000.0f; /* * force enabling pipe split by lower dpp clock for DPM0 to just @@ -759,7 +760,8 @@ bool dcn_validate_bandwidth( const struct resource_pool *pool = dc->res_pool; struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; - int i, input_idx, k; + unsigned int i; + int input_idx, k; int vesa_sync_start, asic_blank_end, asic_blank_start; bool bw_limit_pass; float bw_limit; @@ -808,12 +810,12 @@ bool dcn_validate_bandwidth( v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9; v->downspreading = dc->dcn_soc->downspreading; - v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles; - v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel; - v->number_of_channels = dc->dcn_soc->number_of_channels; - v->vmm_page_size = dc->dcn_soc->vmm_page_size; + v->round_trip_ping_latency_cycles = (float)dc->dcn_soc->round_trip_ping_latency_cycles; + v->urgent_out_of_order_return_per_channel = (float)dc->dcn_soc->urgent_out_of_order_return_per_channel; + v->number_of_channels = (float)dc->dcn_soc->number_of_channels; + v->vmm_page_size = (float)dc->dcn_soc->vmm_page_size; v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency; - v->return_bus_width = dc->dcn_soc->return_bus_width; + v->return_bus_width = (float)dc->dcn_soc->return_bus_width; v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte; v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte; @@ -821,31 +823,31 @@ bool dcn_validate_bandwidth( v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines; v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte; v->pte_enable = dc->dcn_ip->pte_enable; - v->pte_chunk_size = dc->dcn_ip->pte_chunk_size; - v->meta_chunk_size = dc->dcn_ip->meta_chunk_size; - v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size; + v->pte_chunk_size = (float)dc->dcn_ip->pte_chunk_size; + v->meta_chunk_size = (float)dc->dcn_ip->meta_chunk_size; + v->writeback_chunk_size = (float)dc->dcn_ip->writeback_chunk_size; v->odm_capability = dc->dcn_ip->odm_capability; v->dsc_capability = dc->dcn_ip->dsc_capability; - v->line_buffer_size = dc->dcn_ip->line_buffer_size; + v->line_buffer_size = (float)dc->dcn_ip->line_buffer_size; v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed; - v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp; - v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines; - v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size; - v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size; - v->max_num_dpp = dc->dcn_ip->max_num_dpp; - v->max_num_writeback = dc->dcn_ip->max_num_writeback; - v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput; - v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput; - v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput; - v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput; + v->line_buffer_fixed_bpp = (float)dc->dcn_ip->line_buffer_fixed_bpp; + v->max_line_buffer_lines = (float)dc->dcn_ip->max_line_buffer_lines; + v->writeback_luma_buffer_size = (float)dc->dcn_ip->writeback_luma_buffer_size; + v->writeback_chroma_buffer_size = (float)dc->dcn_ip->writeback_chroma_buffer_size; + v->max_num_dpp = (float)dc->dcn_ip->max_num_dpp; + v->max_num_writeback = (float)dc->dcn_ip->max_num_writeback; + v->max_dchub_topscl_throughput = (float)dc->dcn_ip->max_dchub_topscl_throughput; + v->max_pscl_tolb_throughput = (float)dc->dcn_ip->max_pscl_tolb_throughput; + v->max_lb_tovscl_throughput = (float)dc->dcn_ip->max_lb_tovscl_throughput; + v->max_vscl_tohscl_throughput = (float)dc->dcn_ip->max_vscl_tohscl_throughput; v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio; v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio; - v->max_hscl_taps = dc->dcn_ip->max_hscl_taps; - v->max_vscl_taps = dc->dcn_ip->max_vscl_taps; + v->max_hscl_taps = (float)dc->dcn_ip->max_hscl_taps; + v->max_vscl_taps = (float)dc->dcn_ip->max_vscl_taps; v->under_scan_factor = dc->dcn_ip->under_scan_factor; - v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests; - v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin; - v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters; + v->pte_buffer_size_in_requests = (float)dc->dcn_ip->pte_buffer_size_in_requests; + v->dispclk_ramping_margin = (float)dc->dcn_ip->dispclk_ramping_margin; + v->max_inter_dcn_tile_repeaters = (float)dc->dcn_ip->max_inter_dcn_tile_repeaters; v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; v->bug_forcing_luma_and_chroma_request_to_same_size_fixed = @@ -903,14 +905,14 @@ bool dcn_validate_bandwidth( v->underscan_output[input_idx] = false; /* taken care of in recout already*/ v->interlace_output[input_idx] = false; - v->htotal[input_idx] = pipe->stream->timing.h_total; - v->vtotal[input_idx] = pipe->stream->timing.v_total; - v->vactive[input_idx] = pipe->stream->timing.v_addressable + - pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom; - v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total + v->htotal[input_idx] = (float)pipe->stream->timing.h_total; + v->vtotal[input_idx] = (float)pipe->stream->timing.v_total; + v->vactive[input_idx] = (float)(pipe->stream->timing.v_addressable + + pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom); + v->v_sync_plus_back_porch[input_idx] = (float)(pipe->stream->timing.v_total - v->vactive[input_idx] - - pipe->stream->timing.v_front_porch; - v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0; + - pipe->stream->timing.v_front_porch); + v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0f; if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) v->pixel_clock[input_idx] *= 2; if (!pipe->plane_state) { @@ -918,8 +920,8 @@ bool dcn_validate_bandwidth( v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; v->lb_bit_per_pixel[input_idx] = 30; - v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; - v->viewport_height[input_idx] = pipe->stream->timing.v_addressable; + v->viewport_width[input_idx] = (float)pipe->stream->timing.h_addressable; + v->viewport_height[input_idx] = (float)pipe->stream->timing.v_addressable; /* * for cases where we have no plane, we want to validate up to 1080p * source size because here we are only interested in if the output @@ -933,17 +935,17 @@ bool dcn_validate_bandwidth( v->viewport_height[input_idx] = 1080; v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx]; v->scaler_recout_height[input_idx] = v->viewport_height[input_idx]; - v->override_hta_ps[input_idx] = 1; - v->override_vta_ps[input_idx] = 1; - v->override_hta_pschroma[input_idx] = 1; - v->override_vta_pschroma[input_idx] = 1; + v->override_hta_ps[input_idx] = 1.0f; + v->override_vta_ps[input_idx] = 1.0f; + v->override_hta_pschroma[input_idx] = 1.0f; + v->override_vta_pschroma[input_idx] = 1.0f; v->source_scan[input_idx] = dcn_bw_hor; } else { - v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height; - v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width; - v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width; - v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height; + v->viewport_height[input_idx] = (float)pipe->plane_res.scl_data.viewport.height; + v->viewport_width[input_idx] = (float)pipe->plane_res.scl_data.viewport.width; + v->scaler_rec_out_width[input_idx] = (float)pipe->plane_res.scl_data.recout.width; + v->scaler_recout_height[input_idx] = (float)pipe->plane_res.scl_data.recout.height; if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) { if (pipe->plane_state->rotation % 2 == 0) { int viewport_end = pipe->plane_res.scl_data.viewport.width @@ -952,11 +954,11 @@ bool dcn_validate_bandwidth( + pipe->bottom_pipe->plane_res.scl_data.viewport.x; if (viewport_end > viewport_b_end) - v->viewport_width[input_idx] = viewport_end - - pipe->bottom_pipe->plane_res.scl_data.viewport.x; + v->viewport_width[input_idx] = (float)(viewport_end + - pipe->bottom_pipe->plane_res.scl_data.viewport.x); else - v->viewport_width[input_idx] = viewport_b_end - - pipe->plane_res.scl_data.viewport.x; + v->viewport_width[input_idx] = (float)(viewport_b_end + - pipe->plane_res.scl_data.viewport.x); } else { int viewport_end = pipe->plane_res.scl_data.viewport.height + pipe->plane_res.scl_data.viewport.y; @@ -964,14 +966,14 @@ bool dcn_validate_bandwidth( + pipe->bottom_pipe->plane_res.scl_data.viewport.y; if (viewport_end > viewport_b_end) - v->viewport_height[input_idx] = viewport_end - - pipe->bottom_pipe->plane_res.scl_data.viewport.y; + v->viewport_height[input_idx] = (float)(viewport_end + - pipe->bottom_pipe->plane_res.scl_data.viewport.y); else - v->viewport_height[input_idx] = viewport_b_end - - pipe->plane_res.scl_data.viewport.y; + v->viewport_height[input_idx] = (float)(viewport_b_end + - pipe->plane_res.scl_data.viewport.y); } - v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width - + pipe->bottom_pipe->plane_res.scl_data.recout.width; + v->scaler_rec_out_width[input_idx] = (float)(pipe->plane_res.scl_data.recout.width + + pipe->bottom_pipe->plane_res.scl_data.recout.width); } if (pipe->plane_state->rotation % 2 == 0) { @@ -997,7 +999,7 @@ bool dcn_validate_bandwidth( * allow us to disable dcc on the fly without re-calculating WM * * extra overhead for DCC is quite small. for 1080p WM without - * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us) + * DCC is only 0.417fus lower (urgent goes from 6.979fus to 6.562fus) */ unsigned int bpe; @@ -1009,11 +1011,11 @@ bool dcn_validate_bandwidth( pipe->plane_state->format); v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( pipe->plane_state->tiling_info.gfx9.swizzle); - v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); - v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; - v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; - v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; - v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; + v->lb_bit_per_pixel[input_idx] = (float)tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); + v->override_hta_ps[input_idx] = (float)pipe->plane_res.scl_data.taps.h_taps; + v->override_vta_ps[input_idx] = (float)pipe->plane_res.scl_data.taps.v_taps; + v->override_hta_pschroma[input_idx] = (float)pipe->plane_res.scl_data.taps.h_taps_c; + v->override_vta_pschroma[input_idx] = (float)pipe->plane_res.scl_data.taps.v_taps_c; /* * Spreadsheet doesn't handle taps_c is one properly, * need to force Chroma to always be scaled to pass @@ -1091,29 +1093,29 @@ bool dcn_validate_bandwidth( } for (k = 0; k <= v->number_of_active_planes - 1; k++) { if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { - v->byte_per_pixel_dety[k] = 8.0; - v->byte_per_pixel_detc[k] = 0.0; + v->byte_per_pixel_dety[k] = 8.0f; + v->byte_per_pixel_detc[k] = 0.0f; } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { - v->byte_per_pixel_dety[k] = 4.0; - v->byte_per_pixel_detc[k] = 0.0; + v->byte_per_pixel_dety[k] = 4.0f; + v->byte_per_pixel_detc[k] = 0.0f; } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { - v->byte_per_pixel_dety[k] = 2.0; - v->byte_per_pixel_detc[k] = 0.0; + v->byte_per_pixel_dety[k] = 2.0f; + v->byte_per_pixel_detc[k] = 0.0f; } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { - v->byte_per_pixel_dety[k] = 1.0; - v->byte_per_pixel_detc[k] = 2.0; + v->byte_per_pixel_dety[k] = 1.0f; + v->byte_per_pixel_detc[k] = 2.0f; } else { v->byte_per_pixel_dety[k] = 4.0f / 3.0f; v->byte_per_pixel_detc[k] = 8.0f / 3.0f; } } - v->total_data_read_bandwidth = 0.0; + v->total_data_read_bandwidth = 0.0f; for (k = 0; k <= v->number_of_active_planes - 1; k++) { v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] * - dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; - v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] * - dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0; + dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0f) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; + v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0f * v->dpp_per_plane[k] * + dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0f) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0f; v->total_data_read_bandwidth = v->total_data_read_bandwidth + v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k]; } @@ -1144,13 +1146,13 @@ bool dcn_validate_bandwidth( dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = - v->stutter_exit_watermark * 1000; + (uint32_t)(v->stutter_exit_watermark * 1000.0f); context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = - v->stutter_enter_plus_exit_watermark * 1000; + (uint32_t)(v->stutter_enter_plus_exit_watermark * 1000.0f); context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = - v->dram_clock_change_watermark * 1000; - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000; + (uint32_t)(v->dram_clock_change_watermark * 1000.0f); + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(v->ptemeta_urgent_watermark * 1000.0f); + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(v->urgent_watermark * 1000.0f); context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; @@ -1168,14 +1170,14 @@ bool dcn_validate_bandwidth( context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); if (context->bw_ctx.bw.dcn.clk.dispclk_khz < - dc->debug.min_disp_clk_khz) { + (int)dc->debug.min_disp_clk_khz) { context->bw_ctx.bw.dcn.clk.dispclk_khz = - dc->debug.min_disp_clk_khz; + (int)dc->debug.min_disp_clk_khz; } context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio; - context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level]; + context->bw_ctx.bw.dcn.clk.phyclk_khz = (int)v->phyclk_per_state[v->voltage_level]; switch (v->voltage_level) { case 0: context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = @@ -1207,10 +1209,10 @@ bool dcn_validate_bandwidth( if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) continue; - pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; - pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; - pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; - pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; + pipe->pipe_dlg_param.vupdate_width = (unsigned int)v->v_update_width_pix[input_idx]; + pipe->pipe_dlg_param.vupdate_offset = (unsigned int)v->v_update_offset_pix[input_idx]; + pipe->pipe_dlg_param.vready_offset = (unsigned int)v->v_ready_offset_pix[input_idx]; + pipe->pipe_dlg_param.vstartup_start = (unsigned int)v->v_startup[input_idx]; pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; @@ -1248,10 +1250,10 @@ bool dcn_validate_bandwidth( TIMING_3D_FORMAT_SIDE_BY_SIDE))) { if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { /* update previously split pipe */ - hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; - hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; - hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; - hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; + hsplit_pipe->pipe_dlg_param.vupdate_width = (unsigned int)v->v_update_width_pix[input_idx]; + hsplit_pipe->pipe_dlg_param.vupdate_offset = (unsigned int)v->v_update_offset_pix[input_idx]; + hsplit_pipe->pipe_dlg_param.vready_offset = (unsigned int)v->v_ready_offset_pix[input_idx]; + hsplit_pipe->pipe_dlg_param.vstartup_start = (unsigned int)v->v_startup[input_idx]; hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; @@ -1302,12 +1304,12 @@ bool dcn_validate_bandwidth( */ bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9; - bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit; + bw_limit_pass = (v->total_data_read_bandwidth / 1000.0f) < bw_limit; PERFORMANCE_TRACE_END(); BW_VAL_TRACE_FINISH(); - if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic)) + if (bw_limit_pass && v->voltage_level <= (int)get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic)) return true; else return false; @@ -1327,19 +1329,19 @@ void dcn_bw_update_from_pplib_fclks( vmax0p9_idx = fclks->num_levels > 0 ? fclks->num_levels - 1 : 0; dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = - 32 * (fclks->data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0; + 32 * (fclks->data[vmin0p65_idx].clocks_in_khz / 1000.0f) / 1000.0f; dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * - (fclks->data[vmid0p72_idx].clocks_in_khz / 1000.0) - * ddr4_dram_factor_single_Channel / 1000.0; + (fclks->data[vmid0p72_idx].clocks_in_khz / 1000.0f) + * ddr4_dram_factor_single_Channel / 1000.0f; dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels * - (fclks->data[vnom0p8_idx].clocks_in_khz / 1000.0) - * ddr4_dram_factor_single_Channel / 1000.0; + (fclks->data[vnom0p8_idx].clocks_in_khz / 1000.0f) + * ddr4_dram_factor_single_Channel / 1000.0f; dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels * - (fclks->data[vmax0p9_idx].clocks_in_khz / 1000.0) - * ddr4_dram_factor_single_Channel / 1000.0; + (fclks->data[vmax0p9_idx].clocks_in_khz / 1000.0f) + * ddr4_dram_factor_single_Channel / 1000.0f; } void dcn_bw_update_from_pplib_dcfclks( @@ -1347,10 +1349,10 @@ void dcn_bw_update_from_pplib_dcfclks( struct dm_pp_clock_levels_with_voltage *dcfclks) { if (dcfclks->num_levels >= 3) { - dc->dcn_soc->dcfclkv_min0p65 = dcfclks->data[0].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_mid0p72 = dcfclks->data[dcfclks->num_levels - 3].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_nom0p8 = dcfclks->data[dcfclks->num_levels - 2].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_max0p9 = dcfclks->data[dcfclks->num_levels - 1].clocks_in_khz / 1000.0; + dc->dcn_soc->dcfclkv_min0p65 = dcfclks->data[0].clocks_in_khz / 1000.0f; + dc->dcn_soc->dcfclkv_mid0p72 = dcfclks->data[dcfclks->num_levels - 3].clocks_in_khz / 1000.0f; + dc->dcn_soc->dcfclkv_nom0p8 = dcfclks->data[dcfclks->num_levels - 2].clocks_in_khz / 1000.0f; + dc->dcn_soc->dcfclkv_max0p9 = dcfclks->data[dcfclks->num_levels - 1].clocks_in_khz / 1000.0f; } } @@ -1360,9 +1362,9 @@ void dcn_get_soc_clks( int *min_dcfclk_khz, int *socclk_khz) { - *min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32; - *min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000; - *socclk_khz = dc->dcn_soc->socclk * 1000; + *min_fclk_khz = (int)(dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000.0f / 32.0f); + *min_dcfclk_khz = (int)(dc->dcn_soc->dcfclkv_min0p65 * 1000.0f); + *socclk_khz = (int)(dc->dcn_soc->socclk * 1000.0f); } void dcn_bw_notify_pplib_of_wm_ranges( @@ -1391,15 +1393,15 @@ void dcn_bw_notify_pplib_of_wm_ranges( ranges.num_reader_wm_sets = WM_SET_COUNT; ranges.num_writer_wm_sets = WM_SET_COUNT; ranges.reader_wm_sets[0].wm_inst = WM_A; - ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000; - ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000; - ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000; - ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000; + ranges.reader_wm_sets[0].min_drain_clk_mhz = (uint16_t)(min_dcfclk_khz / 1000); + ranges.reader_wm_sets[0].max_drain_clk_mhz = (uint16_t)(overdrive / 1000); + ranges.reader_wm_sets[0].min_fill_clk_mhz = (uint16_t)(min_fclk_khz / 1000); + ranges.reader_wm_sets[0].max_fill_clk_mhz = (uint16_t)(overdrive / 1000); ranges.writer_wm_sets[0].wm_inst = WM_A; - ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000; - ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000; - ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000; - ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000; + ranges.writer_wm_sets[0].min_fill_clk_mhz = (uint16_t)(socclk_khz / 1000); + ranges.writer_wm_sets[0].max_fill_clk_mhz = (uint16_t)(overdrive / 1000); + ranges.writer_wm_sets[0].min_drain_clk_mhz = (uint16_t)(min_fclk_khz / 1000); + ranges.writer_wm_sets[0].max_drain_clk_mhz = (uint16_t)(overdrive / 1000); if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) { ranges.reader_wm_sets[0].wm_inst = WM_A; @@ -1583,14 +1585,14 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc) dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency; dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width; - dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte; - dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte; - dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels; - dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines; - dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte; + dc->dml.ip.rob_buffer_size_kbytes = (unsigned int)dc->dcn_ip->rob_buffer_size_in_kbyte; + dc->dml.ip.det_buffer_size_kbytes = (unsigned int)dc->dcn_ip->det_buffer_size_in_kbyte; + dc->dml.ip.dpp_output_buffer_pixels = (unsigned int)dc->dcn_ip->dpp_output_buffer_pixels; + dc->dml.ip.opp_output_buffer_lines = (unsigned int)dc->dcn_ip->opp_output_buffer_lines; + dc->dml.ip.pixel_chunk_size_kbytes = (unsigned int)dc->dcn_ip->pixel_chunk_size_in_kbyte; dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes; - dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size; - dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size; + dc->dml.ip.pte_chunk_size_kbytes = (unsigned int)dc->dcn_ip->pte_chunk_size; + dc->dml.ip.meta_chunk_size_kbytes = (unsigned int)dc->dcn_ip->meta_chunk_size; dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size; dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size; dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index e82f2d531211..ed7c989a5b13 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -990,7 +990,8 @@ void dcn20_populate_dml_writeback_from_context(struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) { - int pipe_cnt, i; + unsigned int i; + int pipe_cnt; dc_assert_fp_enabled(); @@ -1036,15 +1037,15 @@ void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params, dc_assert_fp_enabled(); for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { - wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + wb_arb_params->cli_watermark[k] = (unsigned int)(get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + wb_arb_params->pstate_watermark[k] = (unsigned int)(get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); } - wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */ + wb_arb_params->time_per_pixel = (unsigned int)(16.0 * 1000.0 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000)); /* 4 bit fraction, ms */ } static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { if (!context->res_ctx.pipe_ctx[i].stream) continue; @@ -1104,7 +1105,7 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc } static void dcn20_adjust_freesync_v_startup( - const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start) + const struct dc_crtc_timing *dc_crtc_timing, unsigned int *vstartup_start) { struct dc_crtc_timing patched_crtc_timing; uint32_t asic_blank_end = 0; @@ -1134,7 +1135,7 @@ static void dcn20_adjust_freesync_v_startup( /* The newVStartUp is 1 line before vsync point */ newVstartup = asic_blank_end + 1; - *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start); + *vstartup_start = (((int)newVstartup > *vstartup_start) ? (int)newVstartup : *vstartup_start); } void dcn20_calculate_dlg_params(struct dc *dc, @@ -1143,23 +1144,24 @@ void dcn20_calculate_dlg_params(struct dc *dc, int pipe_cnt, int vlevel) { - int i, pipe_idx, active_hubp_count = 0; + int pipe_idx, active_hubp_count = 0; + unsigned int i; dc_assert_fp_enabled(); /* Writeback MCIF_WB arbitration parameters */ dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); - context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; - context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; - context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; - context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; + context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(context->bw_ctx.dml.vba.DISPCLK * 1000.0); + context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(context->bw_ctx.dml.vba.DCFCLK * 1000.0); + context->bw_ctx.bw.dcn.clk.socclk_khz = (int)(context->bw_ctx.dml.vba.SOCCLK * 1000.0); + context->bw_ctx.bw.dcn.clk.dramclk_khz = (int)(context->bw_ctx.dml.vba.DRAMSpeed * 1000.0 / 16.0); - if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) + if ((int)dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; - context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; - context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; + context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000.0); + context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(context->bw_ctx.dml.vba.FabricClock * 1000.0); context->bw_ctx.bw.dcn.clk.p_state_change_support = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != dm_dram_clock_change_unsupported; @@ -1173,18 +1175,18 @@ void dcn20_calculate_dlg_params(struct dc *dc, context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); - if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) - context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; + if ((unsigned int)context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) + context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)dc->debug.min_disp_clk_khz; for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { if (!context->res_ctx.pipe_ctx[i].stream) continue; if (context->res_ctx.pipe_ctx[i].plane_state) active_hubp_count++; - pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + pipes[pipe_idx].pipe.dest.vstartup_start = (unsigned int)get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + pipes[pipe_idx].pipe.dest.vupdate_offset = (unsigned int)get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + pipes[pipe_idx].pipe.dest.vupdate_width = (unsigned int)get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + pipes[pipe_idx].pipe.dest.vready_offset = (unsigned int)get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) { // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests @@ -1196,9 +1198,9 @@ void dcn20_calculate_dlg_params(struct dc *dc, } if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) - context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; + context->bw_ctx.bw.dcn.clk.dppclk_khz = (int)(pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000.0); context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = - pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; + (int)(pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000.0); context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; if (dc->ctx->dce_version < DCN_VERSION_3_1 && context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) @@ -1215,8 +1217,8 @@ void dcn20_calculate_dlg_params(struct dc *dc, /*save a original dppclock copy*/ context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; - context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; - context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; + context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = (int)(context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000.0); + context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = (int)(context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000.0); context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx; @@ -1251,7 +1253,7 @@ void dcn20_calculate_dlg_params(struct dc *dc, static void swizzle_to_dml_params( enum swizzle_mode_values swizzle, - unsigned int *sw_mode) + int *sw_mode) { switch (swizzle) { case DC_SW_LINEAR: @@ -1317,7 +1319,8 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc, enum dc_validate_mode validate_mode) { (void)validate_mode; - int pipe_cnt, i; + int pipe_cnt; + unsigned int i; bool synchronized_vblank = true; struct resource_context *res_ctx = &context->res_ctx; @@ -1402,11 +1405,12 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc, timing->h_addressable + timing->h_border_left + timing->h_border_right; pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; - pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; + pipes[pipe_cnt].pipe.dest.interlaced = (unsigned char)timing->flags.INTERLACE; pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; - pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; + pipes[pipe_cnt].pipe.dest.otg_inst = + (unsigned char)res_ctx->pipe_ctx[i].stream_res.tg->inst; pipes[pipe_cnt].dout.dp_lanes = 4; pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na; pipes[pipe_cnt].dout.is_virtual = 0; @@ -1735,7 +1739,8 @@ void dcn20_calculate_wm(struct dc *dc, struct dc_state *context, int vlevel, enum dc_validate_mode validate_mode) { - int pipe_cnt, i, pipe_idx; + int pipe_cnt, pipe_idx; + unsigned int i; dc_assert_fp_enabled(); @@ -1798,51 +1803,51 @@ void dcn20_calculate_wm(struct dc *dc, struct dc_state *context, pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; } - context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); if (vlevel < 2) { pipes[0].clks_cfg.voltage = 2; pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; } - context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); if (vlevel < 3) { pipes[0].clks_cfg.voltage = 3; pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; } - context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); pipes[0].clks_cfg.voltage = vlevel; pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0); } void dcn20_update_bounding_box(struct dc *dc, @@ -1853,7 +1858,7 @@ void dcn20_update_bounding_box(struct dc *dc, { int num_calculated_states = 0; int min_dcfclk = 0; - int i; + unsigned int i; dc_assert_fp_enabled(); @@ -1879,7 +1884,7 @@ void dcn20_update_bounding_box(struct dc *dc, bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000; // FCLK:UCLK ratio is 1.08 - min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080, + min_fclk_required_by_uclk = (int)div_u64(((unsigned long long)uclk_states[i]) * 1080, 1000000); bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? @@ -1914,7 +1919,7 @@ void dcn20_update_bounding_box(struct dc *dc, void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb, struct pp_smu_nv_clock_table max_clocks) { - int i; + unsigned int i; dc_assert_fp_enabled(); @@ -2134,8 +2139,8 @@ void dcn20_fpu_set_wm_ranges(int i, { dc_assert_fp_enabled(); - ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; - ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; + ranges->reader_wm_sets[i].min_fill_clk_mhz = (uint16_t)((i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0); + ranges->reader_wm_sets[i].max_fill_clk_mhz = (uint16_t)(loaded_bb->clock_limits[i].dram_speed_mts / 16); } void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v, @@ -2158,7 +2163,7 @@ int dcn21_populate_dml_pipes_from_context(struct dc *dc, enum dc_validate_mode validate_mode) { uint32_t pipe_cnt; - int i; + unsigned int i; dc_assert_fp_enabled(); @@ -2212,7 +2217,7 @@ static void calculate_wm_set_for_vlevel(int vlevel, { double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; - ASSERT(vlevel < dml->soc.num_states); + ASSERT(vlevel < (int)dml->soc.num_states); /* only pipe 0 is read for voltage and dcf/soc clocks */ pipes[0].clks_cfg.voltage = vlevel; pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; @@ -2222,14 +2227,14 @@ static void calculate_wm_set_for_vlevel(int vlevel, dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; - wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; - wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; - wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; - wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; - wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; + wm_set->urgent_ns = (uint32_t)(get_wm_urgent(dml, pipes, pipe_cnt) * 1000.0); + wm_set->cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000.0); + wm_set->cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000.0); + wm_set->cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000.0); + wm_set->pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000.0); + wm_set->frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000.0); + wm_set->frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000.0); + wm_set->urgent_latency_ns = (uint32_t)(get_urgent_latency(dml, pipes, pipe_cnt) * 1000.0); dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; } @@ -2240,7 +2245,8 @@ static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context, int vlevel_req, enum dc_validate_mode validate_mode) { - int pipe_cnt, i, pipe_idx; + int pipe_cnt, pipe_idx; + unsigned int i; int vlevel, vlevel_max; struct wm_range_table_entry *table_entry; struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; @@ -2476,7 +2482,8 @@ void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) { - int pipe_cnt, i, j; + int pipe_cnt; + unsigned int i, j; double max_calc_writeback_dispclk; double writeback_dispclk; struct writeback_st dout_wb = {0}; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index f5f636afe33c..ac37a2134351 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -326,7 +326,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -519,13 +519,13 @@ static bool CalculatePrefetchSchedule( double LinesToRequestPrefetchPixelData = 0; if (ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor); - DISPCLKCycles = DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)DISPCLKDelaySubtotal; if (DPPCLK == 0.0 || DISPCLK == 0.0) return true; @@ -545,7 +545,7 @@ static bool CalculatePrefetchSchedule( *DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / HTotal, 1); *DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * HTotal)); - *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); + *VUpdateOffsetPix = (unsigned int)dml_ceil(HTotal / 4.0, 1); TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK); *VUpdateWidthPix = (14.0 / DCFCLKDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock; @@ -574,10 +574,10 @@ static bool CalculatePrefetchSchedule( if (VStartup * LineTime < Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) { MyError = true; - *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (Tsetup + TWait - + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime; + *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (unsigned int)((Tsetup + TWait + + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime); } else - *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = 0.0; + *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (unsigned int)0.0; } else Tdm = 0; @@ -828,14 +828,13 @@ static double CalculatePrefetchSourceLines( if (!mode_lib->vba.IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) - MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill - 2) % SwathHeight); else - MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) - % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill + SwathHeight - 2) % SwathHeight); + MaxPartialSwath = (unsigned int)dml_max(1U, MaxPartialSwath); } else { @@ -843,13 +842,12 @@ static double CalculatePrefetchSourceLines( dml_print( "WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)dml_ceil(*VInitPreFill / SwathHeight, 1); if (*VInitPreFill > 1.0) - MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill - 1) % SwathHeight); else - MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1) - % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill + SwathHeight - 1) % SwathHeight); } return *MaxNumSwath * SwathHeight + MaxPartialSwath; @@ -899,34 +897,34 @@ static unsigned int CalculateVMAndRowBytes( MetaRequestHeight = 8 * BlockHeight256Bytes; MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection == dm_horz) { - *meta_row_height = MetaRequestHeight; - MetaSurfWidth = dml_ceil((double) SwathWidth - 1, MetaRequestWidth) - + MetaRequestWidth; - *MetaRowByte = MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)MetaRequestHeight; + MetaSurfWidth = (unsigned int)(dml_ceil((double) SwathWidth - 1, MetaRequestWidth) + + MetaRequestWidth); + *MetaRowByte = (unsigned int)(MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0); } else { - *meta_row_height = MetaRequestWidth; - MetaSurfHeight = dml_ceil((double) SwathWidth - 1, MetaRequestHeight) - + MetaRequestHeight; - *MetaRowByte = MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)MetaRequestWidth; + MetaSurfHeight = (unsigned int)(dml_ceil((double) SwathWidth - 1, MetaRequestHeight) + + MetaRequestHeight); + *MetaRowByte = (unsigned int)(MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0); } if (ScanDirection == dm_horz) { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } else { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil( (double) ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } if (GPUVMEnable == true) { - MetaPTEBytesFrame = (dml_ceil( + MetaPTEBytesFrame = (unsigned int)((dml_ceil( (double) (DCCMetaSurfaceBytes - VMMPageSize) / (8 * VMMPageSize), - 1) + 1) * 64; + 1) + 1) * 64); MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1); } else { MetaPTEBytesFrame = 0; @@ -960,7 +958,7 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) { if (ScanDirection == dm_horz) { DPDE0BytesFrame = - 64 + (unsigned int)(64 * (dml_ceil( ((Pitch * (dml_ceil( @@ -972,10 +970,10 @@ static unsigned int CalculateVMAndRowBytes( - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } else { DPDE0BytesFrame = - 64 + (unsigned int)(64 * (dml_ceil( ((Pitch * (dml_ceil( @@ -987,7 +985,7 @@ static unsigned int CalculateVMAndRowBytes( - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2); } else { @@ -1007,7 +1005,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeight = 1; - PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel; + PixelPTEReqWidth = (unsigned int)8.0 * VMMPageSize / BytePerPixel; PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (MacroTileSizeBytes == 4096) { @@ -1036,7 +1034,7 @@ static unsigned int CalculateVMAndRowBytes( EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs; if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = + *dpte_row_height = (unsigned int)( dml_min( 128, 1 @@ -1049,21 +1047,21 @@ static unsigned int CalculateVMAndRowBytes( * 65536.0 / BytePerPixel) / Pitch), - 1)); + 1))); *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil( + * (unsigned int)(dml_ceil( (double) (Pitch * *dpte_row_height - 1) / PixelPTEReqWidth, 1) + 1); } else if (ScanDirection == dm_horz) { *dpte_row_height = PixelPTEReqHeight; *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1) + * (unsigned int)(dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1) + 1); } else { - *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_height = (unsigned int)dml_min(PixelPTEReqWidth, *MacroTileWidth); *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil( + * (unsigned int)(dml_ceil( ((double) SwathWidth - 1) / PixelPTEReqHeight, 1) + 1); @@ -1539,10 +1537,10 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer / mode_lib->vba.PixelClock[k]) / mode_lib->vba.VRatio[k]; if (mode_lib->vba.BytePerPixelDETC[k] > 0) { - mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k] + mode_lib->vba.LinesInDETC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeC[k] / mode_lib->vba.BytePerPixelDETC[k] - / (mode_lib->vba.SwathWidthY[k] / 2); - mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor( + / (mode_lib->vba.SwathWidthY[k] / 2)); + mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = (unsigned int)dml_floor( mode_lib->vba.LinesInDETC[k], mode_lib->vba.SwathHeightC[k]); mode_lib->vba.FullDETBufferingTimeC[k] = @@ -1811,7 +1809,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), @@ -1821,22 +1819,22 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.OutputFormat[k]); } else { mode_lib->vba.DSCDelay[k] = - 2 + (unsigned int)(2 * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), - slices / 2.0, + (unsigned int)(slices / 2.0), mode_lib->vba.OutputFormat[k]) + dscComputeDelay( - mode_lib->vba.OutputFormat[k])); + mode_lib->vba.OutputFormat[k]))); } - mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k] + mode_lib->vba.DSCDelay[k] = (unsigned int)(mode_lib->vba.DSCDelay[k] * mode_lib->vba.PixelClock[k] - / mode_lib->vba.PixelClockBackEnd[k]; + / mode_lib->vba.PixelClockBackEnd[k]); } else { mode_lib->vba.DSCDelay[k] = 0; } @@ -1860,8 +1858,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), - dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), &mode_lib->vba.BlockHeight256BytesY[k], &mode_lib->vba.BlockHeight256BytesC[k], &mode_lib->vba.BlockWidth256BytesY[k], @@ -1873,11 +1871,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.BlockWidth256BytesY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], - mode_lib->vba.SwathWidthY[k], + (unsigned int)mode_lib->vba.SwathWidthY[k], mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, @@ -1913,13 +1911,13 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.BlockWidth256BytesC[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil( + (unsigned int)dml_ceil( mode_lib->vba.BytePerPixelDETC[k], 2), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k] / 2, mode_lib->vba.ViewportHeight[k] / 2, - mode_lib->vba.SwathWidthY[k] / 2, + (unsigned int)mode_lib->vba.SwathWidthY[k] / 2, mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, @@ -1989,7 +1987,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / mode_lib->vba.DISPCLK; } else mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; @@ -2008,7 +2006,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.WritebackLumaVTaps[j], mode_lib->vba.WritebackChromaHTaps[j], mode_lib->vba.WritebackChromaVTaps[j], - mode_lib->vba.WritebackDestinationWidth[j]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[j]) / mode_lib->vba.DISPCLK); } } @@ -2023,7 +2021,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.VStartupLines = 13; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - mode_lib->vba.MaxVStartupLines[k] = + mode_lib->vba.MaxVStartupLines[k] = (unsigned int)( mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max( 1.0, @@ -2031,11 +2029,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), - 1)); + 1))); } for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) - mode_lib->vba.MaximumMaxVStartupLines = dml_max( + mode_lib->vba.MaximumMaxVStartupLines = (unsigned int)dml_max( mode_lib->vba.MaximumMaxVStartupLines, mode_lib->vba.MaxVStartupLines[k]); @@ -2111,7 +2109,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer - mode_lib->vba.VActive[k], mode_lib->vba.HTotal[k], mode_lib->vba.MaxInterDCNTileRepeaters, - dml_min( + (unsigned int)dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[k]), mode_lib->vba.GPUVMMaxPageTableLevels, @@ -2123,11 +2121,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.UrgentExtraLatency, mode_lib->vba.TCalc, - mode_lib->vba.PDEAndMetaPTEBytesFrame[k], - mode_lib->vba.MetaRowByte[k], - mode_lib->vba.PixelPTEBytesPerRow[k], + (unsigned int)mode_lib->vba.PDEAndMetaPTEBytesFrame[k], + (unsigned int)mode_lib->vba.MetaRowByte[k], + (unsigned int)mode_lib->vba.PixelPTEBytesPerRow[k], mode_lib->vba.PrefetchSourceLinesY[k], - mode_lib->vba.SwathWidthY[k], + (unsigned int)mode_lib->vba.SwathWidthY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.VInitPreFillY[k], mode_lib->vba.MaxNumSwathY[k], @@ -2157,7 +2155,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer &mode_lib->vba.VUpdateWidthPix[k], &mode_lib->vba.VReadyOffsetPix[k]); if (mode_lib->vba.BlendingAndTiming[k] == k) { - mode_lib->vba.VStartup[k] = dml_min( + mode_lib->vba.VStartup[k] = (unsigned int)dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[k]); if (mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata @@ -2166,7 +2164,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; } } else { - mode_lib->vba.VStartup[k] = + mode_lib->vba.VStartup[k] = (unsigned int) dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); @@ -2253,10 +2251,10 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer ImmediateFlipBytes[k] = 0; if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { - ImmediateFlipBytes[k] = + ImmediateFlipBytes[k] = (unsigned int)( mode_lib->vba.PDEAndMetaPTEBytesFrame[k] + mode_lib->vba.MetaRowByte[k] - + mode_lib->vba.PixelPTEBytesPerRow[k]; + + mode_lib->vba.PixelPTEBytesPerRow[k]); } } mode_lib->vba.TotImmediateFlipBytes = 0; @@ -2264,8 +2262,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes - + ImmediateFlipBytes[k]; + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + + ImmediateFlipBytes[k]); } } for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { @@ -2284,8 +2282,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.VRatio[k], mode_lib->vba.Tno_bw[k], mode_lib->vba.PDEAndMetaPTEBytesFrame[k], - mode_lib->vba.MetaRowByte[k], - mode_lib->vba.PixelPTEBytesPerRow[k], + (unsigned int)mode_lib->vba.MetaRowByte[k], + (unsigned int)mode_lib->vba.PixelPTEBytesPerRow[k], mode_lib->vba.DCCEnable[k], mode_lib->vba.dpte_row_height[k], mode_lib->vba.meta_row_height[k], @@ -2409,7 +2407,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer double MaxDETBufferingTimeY; double ActiveDRAMClockChangeLatencyMarginY; - mode_lib->vba.LBLatencyHidingSourceLinesY = + mode_lib->vba.LBLatencyHidingSourceLinesY = (unsigned int)( dml_min( mode_lib->vba.MaxLineBufferLines, (unsigned int) dml_floor( @@ -2419,9 +2417,9 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer / dml_max( mode_lib->vba.HRatio[k], 1.0)), - 1)) - (mode_lib->vba.vtaps[k] - 1); + 1)) -(mode_lib->vba.vtaps[k] - 1)); - mode_lib->vba.LBLatencyHidingSourceLinesC = + mode_lib->vba.LBLatencyHidingSourceLinesC = (unsigned int)( dml_min( mode_lib->vba.MaxLineBufferLines, (unsigned int) dml_floor( @@ -2434,7 +2432,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer / 2, 1.0)), 1)) - - (mode_lib->vba.VTAPsChroma[k] - 1); + -(mode_lib->vba.VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / mode_lib->vba.VRatio[k] @@ -2691,14 +2689,14 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { if (mode_lib->vba.BlendingAndTiming[k] == k) { - unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) - * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; + unsigned int Margin = (unsigned int)((mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) + * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]); if (FirstMainPlane) { VStartupMargin = Margin; FirstMainPlane = false; } else - VStartupMargin = dml_min(VStartupMargin, Margin); + VStartupMargin = (unsigned int)dml_min(VStartupMargin, Margin); } if (mode_lib->vba.UseMaximumVStartup) { @@ -2896,26 +2894,26 @@ static void dml20_DisplayPipeConfiguration(struct display_mode_lib *mode_lib) if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { - mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)MaximumSwathHeightY; + mode_lib->vba.SwathHeightC[k] = (unsigned int)MaximumSwathHeightC; } else { - mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)MinimumSwathHeightY; + mode_lib->vba.SwathHeightC[k] = (unsigned int)MinimumSwathHeightC; } if (mode_lib->vba.SwathHeightC[k] == 0) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024; - mode_lib->vba.DETBufferSizeC[k] = 0; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] * 1024); + mode_lib->vba.DETBufferSizeC[k] = 0; } else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 2; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 2; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 2); + mode_lib->vba.DETBufferSizeC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 2); } else { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 * 2 / 3; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 3; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 * 2 / 3); + mode_lib->vba.DETBufferSizeC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 3); } } } @@ -3233,23 +3231,23 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 6) return BPP_INVALID; else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1.0 / 16) - return 1.5 * DSCInputBitPerComponent - 1.0 / 16; + return (unsigned int)(1.5 * DSCInputBitPerComponent - 1.0 / 16); else - return dml_floor(16 * DecimalBPP, 1) / 16; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16); } else if (Format == dm_n422) { if (DecimalBPP < 7) return BPP_INVALID; else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1.0 / 16) - return 2 * DSCInputBitPerComponent - 1.0 / 16; + return (unsigned int)(2 * DSCInputBitPerComponent - 1.0 / 16); else - return dml_floor(16 * DecimalBPP, 1) / 16; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16); } else { if (DecimalBPP < 8) return BPP_INVALID; else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1.0 / 16) - return 3 * DSCInputBitPerComponent - 1.0 / 16; + return (unsigned int)(3 * DSCInputBitPerComponent - 1.0 / 16); else - return dml_floor(16 * DecimalBPP, 1) / 16; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16); } } else if (Format == dm_420) { if (DecimalBPP >= 18) @@ -3288,8 +3286,8 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l { struct vba_vars_st *locals = &mode_lib->vba; - int i; - unsigned int j, k, m; + int idx; + unsigned int i, j, k, m; /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ @@ -3752,8 +3750,8 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelInDETY[k], 1.0), - dml_ceil(locals->BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETC[k], 2.0), &locals->Read256BlockHeightY[k], &locals->Read256BlockHeightC[k], &locals->Read256BlockWidthY[k], @@ -3930,7 +3928,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->DISPCLK_DPPCLK_Support[i][j] = false; } } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; if (j == 1) { @@ -3985,7 +3983,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l || mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) locals->DISPCLK_DPPCLK_Support[i][j] = false; } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; } @@ -4239,17 +4237,17 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l || locals->RequiresDSC[i][k] == false) { mode_lib->vba.slices = 0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { - mode_lib->vba.slices = dml_ceil( + mode_lib->vba.slices = (unsigned int)dml_ceil( mode_lib->vba.PixelClockBackEnd[k] / 400.0, 4.0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { - mode_lib->vba.slices = 8.0; + mode_lib->vba.slices = (unsigned int)8.0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { - mode_lib->vba.slices = 4.0; + mode_lib->vba.slices = (unsigned int)4.0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { - mode_lib->vba.slices = 2.0; + mode_lib->vba.slices = (unsigned int)2.0; } else { - mode_lib->vba.slices = 1.0; + mode_lib->vba.slices = (unsigned int)1.0; } if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE || locals->OutputBppPerState[i][k] == BPP_INVALID) { @@ -4263,7 +4261,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil( + (unsigned int)dml_ceil( mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), @@ -4276,7 +4274,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 2.0 * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), + (unsigned int)dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), mode_lib->vba.slices / 2, mode_lib->vba.OutputFormat[k]) + dscComputeDelay(mode_lib->vba.OutputFormat[k])); @@ -4302,9 +4300,9 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (j = 0; j < 2; j++) { for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) - locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); + locals->SwathWidthYPerState[i][j][k] = (unsigned int)dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); else - locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; + locals->SwathWidthYPerState[i][j][k] = (unsigned int)locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k]; locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY) + locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k]; @@ -4324,11 +4322,11 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte[0] * 1024.0 / 2) { - locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k]; - locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k]; + locals->SwathHeightYPerState[i][j][k] = (unsigned int)locals->MaxSwathHeightY[k]; + locals->SwathHeightCPerState[i][j][k] = (unsigned int)locals->MaxSwathHeightC[k]; } else { - locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k]; - locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k]; + locals->SwathHeightYPerState[i][j][k] = (unsigned int)locals->MinSwathHeightY[k]; + locals->SwathHeightCPerState[i][j][k] = (unsigned int)locals->MinSwathHeightC[k]; } if (locals->BytePerPixelInDETC[k] == 0) { @@ -4343,16 +4341,16 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); } - locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines, + locals->EffectiveLBLatencyHidingSourceLinesLuma = (unsigned int)dml_min(locals->MaxLineBufferLines, dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] / dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1); - locals->EffectiveLBLatencyHidingSourceLinesChroma = dml_min(locals->MaxLineBufferLines, + locals->EffectiveLBLatencyHidingSourceLinesChroma = (unsigned int)dml_min(locals->MaxLineBufferLines, dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] / 2 / dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1); - locals->EffectiveDETLBLinesLuma = dml_floor(locals->LinesInDETLuma + dml_min( + locals->EffectiveDETLBLinesLuma = (unsigned int)dml_floor(locals->LinesInDETLuma + dml_min( locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] * locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i][0], locals->EffectiveLBLatencyHidingSourceLinesLuma), @@ -4507,7 +4505,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.Read256BlockWidthY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], @@ -4546,17 +4544,17 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.Read256BlockWidthY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), mode_lib->vba.SourceScan[k], - mode_lib->vba.ViewportWidth[k] / 2.0, - mode_lib->vba.ViewportHeight[k] / 2.0, - mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0, + (unsigned int)(mode_lib->vba.ViewportWidth[k] / 2.0), + (unsigned int)(mode_lib->vba.ViewportHeight[k] / 2.0), + (unsigned int)(mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0), mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, mode_lib->vba.PDEProcessingBufIn64KBReqs, mode_lib->vba.PitchC[k], - 0.0, + (unsigned int)0.0, &mode_lib->vba.MacroTileWidthC[k], &mode_lib->vba.MetaRowBytesC, &mode_lib->vba.DPTEBytesPerRowC, @@ -4575,8 +4573,8 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l &mode_lib->vba.MaxNumSwC[k]); } else { mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0; - mode_lib->vba.MetaRowBytesC = 0.0; - mode_lib->vba.DPTEBytesPerRowC = 0.0; + mode_lib->vba.MetaRowBytesC = (unsigned int)0.0; + mode_lib->vba.DPTEBytesPerRowC = (unsigned int)0.0; locals->PrefetchLinesC[0][0][k] = 0.0; locals->PTEBufferSizeNotExceededC[i][j][k] = true; locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma; @@ -4632,7 +4630,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; } else { locals->WritebackDelay[i][k] = 0.0; } @@ -4649,7 +4647,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackLumaVTaps[m], mode_lib->vba.WritebackChromaHTaps[m], mode_lib->vba.WritebackChromaVTaps[m], - mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); + (unsigned int)mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); } } } @@ -4714,7 +4712,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.ProjectedDCFCLKDeepSleep[0][0], - mode_lib->vba.DSCDelayPerState[i][k], + (unsigned int)mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], @@ -4724,14 +4722,14 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal, - mode_lib->vba.SwathWidthYPerState[i][j][k] - / mode_lib->vba.HRatio[k], + (unsigned int)(mode_lib->vba.SwathWidthYPerState[i][j][k] + / mode_lib->vba.HRatio[k]), mode_lib->vba.OutputFormat[k], mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k], mode_lib->vba.HTotal[k], mode_lib->vba.MaxInterDCNTileRepeaters, - mode_lib->vba.MaximumVStartup[0][0][k], + (unsigned int)mode_lib->vba.MaximumVStartup[0][0][k], mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMEnable, mode_lib->vba.DynamicMetadataEnable[k], @@ -4741,9 +4739,9 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.ExtraLatency, mode_lib->vba.TimeCalc, - mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], - mode_lib->vba.MetaRowBytes[0][0][k], - mode_lib->vba.DPTEBytesPerRow[0][0][k], + (unsigned int)mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], + (unsigned int)mode_lib->vba.MetaRowBytes[0][0][k], + (unsigned int)mode_lib->vba.DPTEBytesPerRow[0][0][k], mode_lib->vba.PrefetchLinesY[0][0][k], mode_lib->vba.SwathWidthYPerState[i][j][k], mode_lib->vba.BytePerPixelInDETY[k], @@ -4852,16 +4850,16 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.PrefetchBW[k]); } for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - mode_lib->vba.ImmediateFlipBytes[k] = 0.0; + mode_lib->vba.ImmediateFlipBytes[k] = (unsigned int)0.0; if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { mode_lib->vba.ImmediateFlipBytes[k] = - mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k] + (unsigned int)(mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k] + mode_lib->vba.MetaRowBytes[0][0][k] - + mode_lib->vba.DPTEBytesPerRow[0][0][k]; + + mode_lib->vba.DPTEBytesPerRow[0][0][k]); } } - mode_lib->vba.TotImmediateFlipBytes = 0.0; + mode_lib->vba.TotImmediateFlipBytes = 0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { @@ -4887,8 +4885,8 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.VRatio[k], mode_lib->vba.Tno_bw[k], mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], - mode_lib->vba.MetaRowBytes[0][0][k], - mode_lib->vba.DPTEBytesPerRow[0][0][k], + (unsigned int)mode_lib->vba.MetaRowBytes[0][0][k], + (unsigned int)mode_lib->vba.DPTEBytesPerRow[0][0][k], mode_lib->vba.DCCEnable[k], mode_lib->vba.dpte_row_height[k], mode_lib->vba.meta_row_height[k], @@ -5018,7 +5016,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { + for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) { for (j = 0; j < 2; j++) { enum dm_validation_status status = DML_VALIDATION_OK; @@ -5026,21 +5024,21 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l status = DML_FAIL_SCALE_RATIO_TAP; } else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) { status = DML_FAIL_SOURCE_PIXEL_FORMAT; - } else if (locals->ViewportSizeSupport[i][0] != true) { + } else if (locals->ViewportSizeSupport[idx][0] != true) { status = DML_FAIL_VIEWPORT_SIZE; - } else if (locals->DIOSupport[i] != true) { + } else if (locals->DIOSupport[idx] != true) { status = DML_FAIL_DIO_SUPPORT; - } else if (locals->NotEnoughDSCUnits[i] != false) { + } else if (locals->NotEnoughDSCUnits[idx] != false) { status = DML_FAIL_NOT_ENOUGH_DSC; - } else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) { + } else if (locals->DSCCLKRequiredMoreThanSupported[idx] != false) { status = DML_FAIL_DSC_CLK_REQUIRED; - } else if (locals->UrgentLatencySupport[i][j] != true) { + } else if (locals->UrgentLatencySupport[idx][j] != true) { status = DML_FAIL_URGENT_LATENCY; - } else if (locals->ROBSupport[i][0] != true) { + } else if (locals->ROBSupport[idx][0] != true) { status = DML_FAIL_REORDERING_BUFFER; - } else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) { + } else if (locals->DISPCLK_DPPCLK_Support[idx][j] != true) { status = DML_FAIL_DISPCLK_DPPCLK; - } else if (locals->TotalAvailablePipesSupport[i][j] != true) { + } else if (locals->TotalAvailablePipesSupport[idx][j] != true) { status = DML_FAIL_TOTAL_AVAILABLE_PIPES; } else if (mode_lib->vba.NumberOfOTGSupport != true) { status = DML_FAIL_NUM_OTG; @@ -5054,24 +5052,24 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l status = DML_FAIL_CURSOR_SUPPORT; } else if (mode_lib->vba.PitchSupport != true) { status = DML_FAIL_PITCH_SUPPORT; - } else if (locals->PrefetchSupported[i][j] != true) { + } else if (locals->PrefetchSupported[idx][j] != true) { status = DML_FAIL_PREFETCH_SUPPORT; - } else if (locals->TotalVerticalActiveBandwidthSupport[i][0] != true) { + } else if (locals->TotalVerticalActiveBandwidthSupport[idx][0] != true) { status = DML_FAIL_TOTAL_V_ACTIVE_BW; - } else if (locals->VRatioInPrefetchSupported[i][j] != true) { + } else if (locals->VRatioInPrefetchSupported[idx][j] != true) { status = DML_FAIL_V_RATIO_PREFETCH; - } else if (locals->PTEBufferSizeNotExceeded[i][j] != true) { + } else if (locals->PTEBufferSizeNotExceeded[idx][j] != true) { status = DML_FAIL_PTE_BUFFER_SIZE; } else if (mode_lib->vba.NonsupportedDSCInputBPC != false) { status = DML_FAIL_DSC_INPUT_BPC; } if (status == DML_VALIDATION_OK) { - locals->ModeSupport[i][j] = true; + locals->ModeSupport[idx][j] = true; } else { - locals->ModeSupport[i][j] = false; + locals->ModeSupport[idx][j] = false; } - locals->ValidationStatus[i] = status; + locals->ValidationStatus[idx] = status; } } { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 95b0a3501880..a6b8b5ddd945 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -350,7 +350,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -510,13 +510,13 @@ static bool CalculateDelayAfterScaler( } if (ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor); - DISPCLKCycles = DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)DISPCLKDelaySubtotal; if (DPPCLK == 0.0 || DISPCLK == 0.0) return true; @@ -609,7 +609,7 @@ static bool CalculatePrefetchSchedule( double TimeForFetchingRowInVBlank = 0; double LinesToRequestPrefetchPixelData = 0; - *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); + *VUpdateOffsetPix = (unsigned int)dml_ceil(HTotal / 4.0, 1); TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK); *VUpdateWidthPix = (14.0 / DCFCLKDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock; @@ -889,14 +889,13 @@ static double CalculatePrefetchSourceLines( if (!mode_lib->vba.IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) - MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill - 2) % SwathHeight); else - MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) - % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill + SwathHeight - 2) % SwathHeight); + MaxPartialSwath = (unsigned int)dml_max(1U, MaxPartialSwath); } else { @@ -904,13 +903,12 @@ static double CalculatePrefetchSourceLines( dml_print( "WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)dml_ceil(*VInitPreFill / SwathHeight, 1); if (*VInitPreFill > 1.0) - MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill - 1) % SwathHeight); else - MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1) - % SwathHeight; + MaxPartialSwath = (unsigned int)((unsigned int)(*VInitPreFill + SwathHeight - 1) % SwathHeight); } return *MaxNumSwath * SwathHeight + MaxPartialSwath; @@ -960,34 +958,34 @@ static unsigned int CalculateVMAndRowBytes( MetaRequestHeight = 8 * BlockHeight256Bytes; MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection == dm_horz) { - *meta_row_height = MetaRequestHeight; - MetaSurfWidth = dml_ceil((double) SwathWidth - 1, MetaRequestWidth) - + MetaRequestWidth; - *MetaRowByte = MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)MetaRequestHeight; + MetaSurfWidth = (unsigned int)(dml_ceil((double) SwathWidth - 1, MetaRequestWidth) + + MetaRequestWidth); + *MetaRowByte = (unsigned int)(MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0); } else { - *meta_row_height = MetaRequestWidth; - MetaSurfHeight = dml_ceil((double) SwathWidth - 1, MetaRequestHeight) - + MetaRequestHeight; - *MetaRowByte = MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)MetaRequestWidth; + MetaSurfHeight = (unsigned int)(dml_ceil((double) SwathWidth - 1, MetaRequestHeight) + + MetaRequestHeight); + *MetaRowByte = (unsigned int)(MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0); } if (ScanDirection == dm_horz) { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } else { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil( (double) ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } if (GPUVMEnable == true) { - MetaPTEBytesFrame = (dml_ceil( + MetaPTEBytesFrame = (unsigned int)((dml_ceil( (double) (DCCMetaSurfaceBytes - VMMPageSize) / (8 * VMMPageSize), - 1) + 1) * 64; + 1) + 1) * 64); MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1); } else { MetaPTEBytesFrame = 0; @@ -1021,7 +1019,7 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) { if (ScanDirection == dm_horz) { DPDE0BytesFrame = - 64 + (unsigned int)(64 * (dml_ceil( ((Pitch * (dml_ceil( @@ -1033,10 +1031,10 @@ static unsigned int CalculateVMAndRowBytes( - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } else { DPDE0BytesFrame = - 64 + (unsigned int)(64 * (dml_ceil( ((Pitch * (dml_ceil( @@ -1048,7 +1046,7 @@ static unsigned int CalculateVMAndRowBytes( - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2); } else { @@ -1068,7 +1066,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeight = 1; - PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel; + PixelPTEReqWidth = (unsigned int)8.0 * VMMPageSize / BytePerPixel; PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (MacroTileSizeBytes == 4096) { @@ -1097,7 +1095,7 @@ static unsigned int CalculateVMAndRowBytes( EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs; if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = + *dpte_row_height = (unsigned int)( dml_min( 128, 1 @@ -1110,21 +1108,21 @@ static unsigned int CalculateVMAndRowBytes( * 65536.0 / BytePerPixel) / Pitch), - 1)); + 1))); *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil( + * (unsigned int)(dml_ceil( (double) (Pitch * *dpte_row_height - 1) / PixelPTEReqWidth, 1) + 1); } else if (ScanDirection == dm_horz) { *dpte_row_height = PixelPTEReqHeight; *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1) + * (unsigned int)(dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1) + 1); } else { - *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_height = (unsigned int)dml_min(PixelPTEReqWidth, *MacroTileWidth); *PixelPTEBytesPerRow = PTERequestSize - * (dml_ceil( + * (unsigned int)(dml_ceil( ((double) SwathWidth - 1) / PixelPTEReqHeight, 1) + 1); @@ -1576,10 +1574,10 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP / mode_lib->vba.PixelClock[k]) / mode_lib->vba.VRatio[k]; if (mode_lib->vba.BytePerPixelDETC[k] > 0) { - mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k] + mode_lib->vba.LinesInDETC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeC[k] / mode_lib->vba.BytePerPixelDETC[k] - / (mode_lib->vba.SwathWidthY[k] / 2); - mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor( + / (mode_lib->vba.SwathWidthY[k] / 2)); + mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = (unsigned int)dml_floor( mode_lib->vba.LinesInDETC[k], mode_lib->vba.SwathHeightC[k]); mode_lib->vba.FullDETBufferingTimeC[k] = @@ -1848,7 +1846,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), @@ -1862,18 +1860,18 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), - slices / 2.0, + (unsigned int)(slices / 2.0), mode_lib->vba.OutputFormat[k]) + dscComputeDelay( mode_lib->vba.OutputFormat[k])); } - mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k] + mode_lib->vba.DSCDelay[k] = (unsigned int)(mode_lib->vba.DSCDelay[k] * mode_lib->vba.PixelClock[k] - / mode_lib->vba.PixelClockBackEnd[k]; + / mode_lib->vba.PixelClockBackEnd[k]); } else { mode_lib->vba.DSCDelay[k] = 0; } @@ -1897,8 +1895,8 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), - dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), &mode_lib->vba.BlockHeight256BytesY[k], &mode_lib->vba.BlockHeight256BytesC[k], &mode_lib->vba.BlockWidth256BytesY[k], @@ -1910,11 +1908,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.BlockWidth256BytesY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], - mode_lib->vba.SwathWidthY[k], + (unsigned int)mode_lib->vba.SwathWidthY[k], mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, @@ -1950,13 +1948,13 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.BlockWidth256BytesC[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil( + (unsigned int)dml_ceil( mode_lib->vba.BytePerPixelDETC[k], 2), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k] / 2, mode_lib->vba.ViewportHeight[k] / 2, - mode_lib->vba.SwathWidthY[k] / 2, + (unsigned int)mode_lib->vba.SwathWidthY[k] / 2, mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, @@ -2026,7 +2024,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / mode_lib->vba.DISPCLK; } else mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; @@ -2045,7 +2043,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.WritebackLumaVTaps[j], mode_lib->vba.WritebackChromaHTaps[j], mode_lib->vba.WritebackChromaVTaps[j], - mode_lib->vba.WritebackDestinationWidth[j]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[j]) / mode_lib->vba.DISPCLK); } } @@ -2060,7 +2058,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.VStartupLines = 13; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - mode_lib->vba.MaxVStartupLines[k] = + mode_lib->vba.MaxVStartupLines[k] = (unsigned int)( mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max( 1.0, @@ -2068,11 +2066,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), - 1)); + 1))); } for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) - mode_lib->vba.MaximumMaxVStartupLines = dml_max( + mode_lib->vba.MaximumMaxVStartupLines = (unsigned int)dml_max( mode_lib->vba.MaximumMaxVStartupLines, mode_lib->vba.MaxVStartupLines[k]); @@ -2129,8 +2127,8 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k], mode_lib->vba.DPPCLK[k], mode_lib->vba.DISPCLK, mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelay[k], mode_lib->vba.DPPPerPlane[k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal, - mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], - mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k], + (unsigned int)(mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k]), mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], + (unsigned int)mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP, &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]); mode_lib->vba.ErrorResult[k] = @@ -2146,7 +2144,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP - mode_lib->vba.VActive[k], mode_lib->vba.HTotal[k], mode_lib->vba.MaxInterDCNTileRepeaters, - dml_min( + (unsigned int)dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[k]), mode_lib->vba.GPUVMMaxPageTableLevels, @@ -2158,11 +2156,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.UrgentExtraLatency, mode_lib->vba.TCalc, - mode_lib->vba.PDEAndMetaPTEBytesFrame[k], - mode_lib->vba.MetaRowByte[k], - mode_lib->vba.PixelPTEBytesPerRow[k], + (unsigned int)mode_lib->vba.PDEAndMetaPTEBytesFrame[k], + (unsigned int)mode_lib->vba.MetaRowByte[k], + (unsigned int)mode_lib->vba.PixelPTEBytesPerRow[k], mode_lib->vba.PrefetchSourceLinesY[k], - mode_lib->vba.SwathWidthY[k], + (unsigned int)mode_lib->vba.SwathWidthY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.VInitPreFillY[k], mode_lib->vba.MaxNumSwathY[k], @@ -2192,7 +2190,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP &mode_lib->vba.VReadyOffsetPix[k]); if (mode_lib->vba.BlendingAndTiming[k] == k) { - mode_lib->vba.VStartup[k] = dml_min( + mode_lib->vba.VStartup[k] = (unsigned int)dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[k]); if (mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata @@ -2201,7 +2199,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; } } else { - mode_lib->vba.VStartup[k] = + mode_lib->vba.VStartup[k] = (unsigned int) dml_min( mode_lib->vba.VStartupLines, mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); @@ -2288,10 +2286,10 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP ImmediateFlipBytes[k] = 0; if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { - ImmediateFlipBytes[k] = + ImmediateFlipBytes[k] = (unsigned int)( mode_lib->vba.PDEAndMetaPTEBytesFrame[k] + mode_lib->vba.MetaRowByte[k] - + mode_lib->vba.PixelPTEBytesPerRow[k]; + + mode_lib->vba.PixelPTEBytesPerRow[k]); } } mode_lib->vba.TotImmediateFlipBytes = 0; @@ -2319,8 +2317,8 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP mode_lib->vba.VRatio[k], mode_lib->vba.Tno_bw[k], mode_lib->vba.PDEAndMetaPTEBytesFrame[k], - mode_lib->vba.MetaRowByte[k], - mode_lib->vba.PixelPTEBytesPerRow[k], + (unsigned int)mode_lib->vba.MetaRowByte[k], + (unsigned int)mode_lib->vba.PixelPTEBytesPerRow[k], mode_lib->vba.DCCEnable[k], mode_lib->vba.dpte_row_height[k], mode_lib->vba.meta_row_height[k], @@ -2444,7 +2442,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP double MaxDETBufferingTimeY; double ActiveDRAMClockChangeLatencyMarginY; - mode_lib->vba.LBLatencyHidingSourceLinesY = + mode_lib->vba.LBLatencyHidingSourceLinesY = (unsigned int)( dml_min( mode_lib->vba.MaxLineBufferLines, (unsigned int) dml_floor( @@ -2454,9 +2452,9 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP / dml_max( mode_lib->vba.HRatio[k], 1.0)), - 1)) - (mode_lib->vba.vtaps[k] - 1); + 1)) -(mode_lib->vba.vtaps[k] - 1)); - mode_lib->vba.LBLatencyHidingSourceLinesC = + mode_lib->vba.LBLatencyHidingSourceLinesC = (unsigned int)( dml_min( mode_lib->vba.MaxLineBufferLines, (unsigned int) dml_floor( @@ -2469,7 +2467,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP / 2, 1.0)), 1)) - - (mode_lib->vba.VTAPsChroma[k] - 1); + -(mode_lib->vba.VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / mode_lib->vba.VRatio[k] @@ -2631,7 +2629,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP && mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) { SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = - mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; + (float)mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; } } @@ -2765,14 +2763,14 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { if (mode_lib->vba.BlendingAndTiming[k] == k) { - unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) - * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; + unsigned int Margin = (unsigned int)((mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) + * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]); if (FirstMainPlane) { VStartupMargin = Margin; FirstMainPlane = false; } else - VStartupMargin = dml_min(VStartupMargin, Margin); + VStartupMargin = (unsigned int)dml_min(VStartupMargin, Margin); } if (mode_lib->vba.UseMaximumVStartup) { @@ -2970,26 +2968,26 @@ static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib) if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { - mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)MaximumSwathHeightY; + mode_lib->vba.SwathHeightC[k] = (unsigned int)MaximumSwathHeightC; } else { - mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)MinimumSwathHeightY; + mode_lib->vba.SwathHeightC[k] = (unsigned int)MinimumSwathHeightC; } if (mode_lib->vba.SwathHeightC[k] == 0) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024; - mode_lib->vba.DETBufferSizeC[k] = 0; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] * 1024); + mode_lib->vba.DETBufferSizeC[k] = 0; } else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 2; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 2; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 2); + mode_lib->vba.DETBufferSizeC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 2); } else { - mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 * 2 / 3; - mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0] - * 1024.0 / 3; + mode_lib->vba.DETBufferSizeY[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 * 2 / 3); + mode_lib->vba.DETBufferSizeC[k] = (unsigned int)(mode_lib->vba.DETBufferSizeInKByte[0] + * 1024.0 / 3); } } } @@ -3309,9 +3307,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 6) return BPP_INVALID; else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1.0 / 16.0) - return 1.5 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(1.5 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 6 || DesiredBPP < 6 @@ -3319,7 +3317,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)DesiredBPP; } } } else if (Format == dm_n422) { @@ -3327,9 +3325,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 7) return BPP_INVALID; else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1.0 / 16.0) - return 2 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(2 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 7 || DesiredBPP < 7 @@ -3337,7 +3335,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)DesiredBPP; } } } else { @@ -3345,9 +3343,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 8) return BPP_INVALID; else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1.0 / 16.0) - return 3 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(3 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 8 || DesiredBPP < 8 @@ -3355,7 +3353,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)DesiredBPP; } } } @@ -3396,8 +3394,8 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode { struct vba_vars_st *locals = &mode_lib->vba; - int i; - unsigned int j, k, m; + int idx; + unsigned int i, j, k, m; /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ @@ -3860,8 +3858,8 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelInDETY[k], 1.0), - dml_ceil(locals->BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETC[k], 2.0), &locals->Read256BlockHeightY[k], &locals->Read256BlockHeightC[k], &locals->Read256BlockWidthY[k], @@ -4045,7 +4043,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode locals->DISPCLK_DPPCLK_Support[i][j] = false; } } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; if (j == 1) { @@ -4100,7 +4098,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode || mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) locals->DISPCLK_DPPCLK_Support[i][j] = false; } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; } @@ -4361,17 +4359,17 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode || locals->RequiresDSC[i][k] == false) { mode_lib->vba.slices = 0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { - mode_lib->vba.slices = dml_ceil( + mode_lib->vba.slices = (unsigned int)dml_ceil( mode_lib->vba.PixelClockBackEnd[k] / 400.0, 4.0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { - mode_lib->vba.slices = 8.0; + mode_lib->vba.slices = (unsigned int)8.0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { - mode_lib->vba.slices = 4.0; + mode_lib->vba.slices = (unsigned int)4.0; } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { - mode_lib->vba.slices = 2.0; + mode_lib->vba.slices = (unsigned int)2.0; } else { - mode_lib->vba.slices = 1.0; + mode_lib->vba.slices = (unsigned int)1.0; } if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE || locals->OutputBppPerState[i][k] == BPP_INVALID) { @@ -4385,7 +4383,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil( + (unsigned int)dml_ceil( mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), @@ -4398,7 +4396,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode 2.0 * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), + (unsigned int)dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), mode_lib->vba.slices / 2, mode_lib->vba.OutputFormat[k]) + dscComputeDelay(mode_lib->vba.OutputFormat[k])); @@ -4424,9 +4422,9 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode for (j = 0; j < 2; j++) { for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) - locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); + locals->SwathWidthYPerState[i][j][k] = (unsigned int)dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); else - locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; + locals->SwathWidthYPerState[i][j][k] = (unsigned int)locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k]; locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY) + locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k]; @@ -4446,11 +4444,11 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode } if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte[0] * 1024.0 / 2) { - locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k]; - locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k]; + locals->SwathHeightYPerState[i][j][k] = (unsigned int)locals->MaxSwathHeightY[k]; + locals->SwathHeightCPerState[i][j][k] = (unsigned int)locals->MaxSwathHeightC[k]; } else { - locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k]; - locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k]; + locals->SwathHeightYPerState[i][j][k] = (unsigned int)locals->MinSwathHeightY[k]; + locals->SwathHeightCPerState[i][j][k] = (unsigned int)locals->MinSwathHeightC[k]; } if (locals->BytePerPixelInDETC[k] == 0) { @@ -4465,16 +4463,16 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); } - locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines, + locals->EffectiveLBLatencyHidingSourceLinesLuma = (unsigned int)dml_min(locals->MaxLineBufferLines, dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] / dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1); - locals->EffectiveLBLatencyHidingSourceLinesChroma = dml_min(locals->MaxLineBufferLines, + locals->EffectiveLBLatencyHidingSourceLinesChroma = (unsigned int)dml_min(locals->MaxLineBufferLines, dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] / 2 / dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1); - locals->EffectiveDETLBLinesLuma = dml_floor(locals->LinesInDETLuma + dml_min( + locals->EffectiveDETLBLinesLuma = (unsigned int)dml_floor(locals->LinesInDETLuma + dml_min( locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] * locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i][0], locals->EffectiveLBLatencyHidingSourceLinesLuma), @@ -4630,7 +4628,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.Read256BlockWidthY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], @@ -4669,17 +4667,17 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.Read256BlockWidthY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), mode_lib->vba.SourceScan[k], - mode_lib->vba.ViewportWidth[k] / 2.0, - mode_lib->vba.ViewportHeight[k] / 2.0, - mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0, + (unsigned int)(mode_lib->vba.ViewportWidth[k] / 2.0), + (unsigned int)(mode_lib->vba.ViewportHeight[k] / 2.0), + (unsigned int)(mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0), mode_lib->vba.GPUVMEnable, mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsLuma, mode_lib->vba.PDEProcessingBufIn64KBReqs, mode_lib->vba.PitchC[k], - 0.0, + (unsigned int)0.0, &mode_lib->vba.MacroTileWidthC[k], &mode_lib->vba.MetaRowBytesC, &mode_lib->vba.DPTEBytesPerRowC, @@ -4698,8 +4696,8 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode &mode_lib->vba.MaxNumSwC[k]); } else { mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0; - mode_lib->vba.MetaRowBytesC = 0.0; - mode_lib->vba.DPTEBytesPerRowC = 0.0; + mode_lib->vba.MetaRowBytesC = (unsigned int)0.0; + mode_lib->vba.DPTEBytesPerRowC = (unsigned int)0.0; locals->PrefetchLinesC[0][0][k] = 0.0; locals->PTEBufferSizeNotExceededC[i][j][k] = true; locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma; @@ -4755,7 +4753,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; } else { locals->WritebackDelay[i][k] = 0.0; } @@ -4772,7 +4770,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.WritebackLumaVTaps[m], mode_lib->vba.WritebackChromaHTaps[m], mode_lib->vba.WritebackChromaVTaps[m], - mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); + (unsigned int)mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); } } } @@ -4833,10 +4831,10 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBWPerState[i][0], mode_lib->vba.ReadBandwidthLuma[k], mode_lib->vba.ReadBandwidthChroma[k], mode_lib->vba.MaxTotalVActiveRDBandwidth, mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k], - mode_lib->vba.RequiredDPPCLK[i][j][k], mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], + (unsigned int)mode_lib->vba.RequiredDPPCLK[i][j][k], (unsigned int)mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], (unsigned int)mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal, - mode_lib->vba.SwathWidthYPerState[i][j][k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], - mode_lib->vba.SwathWidthYSingleDPP[k], mode_lib->vba.BytePerPixelInDETY[k], mode_lib->vba.BytePerPixelInDETC[k], mode_lib->vba.SwathHeightYThisState[k], mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP, + (unsigned int)(mode_lib->vba.SwathWidthYPerState[i][j][k] / mode_lib->vba.HRatio[k]), mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], + (unsigned int)mode_lib->vba.SwathWidthYSingleDPP[k], mode_lib->vba.BytePerPixelInDETY[k], mode_lib->vba.BytePerPixelInDETC[k], mode_lib->vba.SwathHeightYThisState[k], mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP, &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]); mode_lib->vba.IsErrorResult[i][j][k] = @@ -4852,7 +4850,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode - mode_lib->vba.VActive[k], mode_lib->vba.HTotal[k], mode_lib->vba.MaxInterDCNTileRepeaters, - mode_lib->vba.MaximumVStartup[0][0][k], + (unsigned int)mode_lib->vba.MaximumVStartup[0][0][k], mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMEnable, mode_lib->vba.DynamicMetadataEnable[k], @@ -4862,9 +4860,9 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.ExtraLatency, mode_lib->vba.TimeCalc, - mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], - mode_lib->vba.MetaRowBytes[0][0][k], - mode_lib->vba.DPTEBytesPerRow[0][0][k], + (unsigned int)mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], + (unsigned int)mode_lib->vba.MetaRowBytes[0][0][k], + (unsigned int)mode_lib->vba.DPTEBytesPerRow[0][0][k], mode_lib->vba.PrefetchLinesY[0][0][k], mode_lib->vba.SwathWidthYPerState[i][j][k], mode_lib->vba.BytePerPixelInDETY[k], @@ -4972,16 +4970,16 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.PrefetchBW[k]); } for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - mode_lib->vba.ImmediateFlipBytes[k] = 0.0; + mode_lib->vba.ImmediateFlipBytes[k] = (unsigned int)0.0; if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { - mode_lib->vba.ImmediateFlipBytes[k] = + mode_lib->vba.ImmediateFlipBytes[k] = (unsigned int)( mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k] + mode_lib->vba.MetaRowBytes[0][0][k] - + mode_lib->vba.DPTEBytesPerRow[0][0][k]; + + mode_lib->vba.DPTEBytesPerRow[0][0][k]); } } - mode_lib->vba.TotImmediateFlipBytes = 0.0; + mode_lib->vba.TotImmediateFlipBytes = 0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { @@ -5007,8 +5005,8 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode mode_lib->vba.VRatio[k], mode_lib->vba.Tno_bw[k], mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k], - mode_lib->vba.MetaRowBytes[0][0][k], - mode_lib->vba.DPTEBytesPerRow[0][0][k], + (unsigned int)mode_lib->vba.MetaRowBytes[0][0][k], + (unsigned int)mode_lib->vba.DPTEBytesPerRow[0][0][k], mode_lib->vba.DCCEnable[k], mode_lib->vba.dpte_row_height[k], mode_lib->vba.meta_row_height[k], @@ -5135,7 +5133,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { + for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) { for (j = 0; j < 2; j++) { enum dm_validation_status status = DML_VALIDATION_OK; @@ -5143,21 +5141,21 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode status = DML_FAIL_SCALE_RATIO_TAP; } else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) { status = DML_FAIL_SOURCE_PIXEL_FORMAT; - } else if (locals->ViewportSizeSupport[i][0] != true) { + } else if (locals->ViewportSizeSupport[idx][0] != true) { status = DML_FAIL_VIEWPORT_SIZE; - } else if (locals->DIOSupport[i] != true) { + } else if (locals->DIOSupport[idx] != true) { status = DML_FAIL_DIO_SUPPORT; - } else if (locals->NotEnoughDSCUnits[i] != false) { + } else if (locals->NotEnoughDSCUnits[idx] != false) { status = DML_FAIL_NOT_ENOUGH_DSC; - } else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) { + } else if (locals->DSCCLKRequiredMoreThanSupported[idx] != false) { status = DML_FAIL_DSC_CLK_REQUIRED; - } else if (locals->UrgentLatencySupport[i][j] != true) { + } else if (locals->UrgentLatencySupport[idx][j] != true) { status = DML_FAIL_URGENT_LATENCY; - } else if (locals->ROBSupport[i][0] != true) { + } else if (locals->ROBSupport[idx][0] != true) { status = DML_FAIL_REORDERING_BUFFER; - } else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) { + } else if (locals->DISPCLK_DPPCLK_Support[idx][j] != true) { status = DML_FAIL_DISPCLK_DPPCLK; - } else if (locals->TotalAvailablePipesSupport[i][j] != true) { + } else if (locals->TotalAvailablePipesSupport[idx][j] != true) { status = DML_FAIL_TOTAL_AVAILABLE_PIPES; } else if (mode_lib->vba.NumberOfOTGSupport != true) { status = DML_FAIL_NUM_OTG; @@ -5171,24 +5169,24 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode status = DML_FAIL_CURSOR_SUPPORT; } else if (mode_lib->vba.PitchSupport != true) { status = DML_FAIL_PITCH_SUPPORT; - } else if (locals->PrefetchSupported[i][j] != true) { + } else if (locals->PrefetchSupported[idx][j] != true) { status = DML_FAIL_PREFETCH_SUPPORT; - } else if (locals->TotalVerticalActiveBandwidthSupport[i][0] != true) { + } else if (locals->TotalVerticalActiveBandwidthSupport[idx][0] != true) { status = DML_FAIL_TOTAL_V_ACTIVE_BW; - } else if (locals->VRatioInPrefetchSupported[i][j] != true) { + } else if (locals->VRatioInPrefetchSupported[idx][j] != true) { status = DML_FAIL_V_RATIO_PREFETCH; - } else if (locals->PTEBufferSizeNotExceeded[i][j] != true) { + } else if (locals->PTEBufferSizeNotExceeded[idx][j] != true) { status = DML_FAIL_PTE_BUFFER_SIZE; } else if (mode_lib->vba.NonsupportedDSCInputBPC != false) { status = DML_FAIL_DSC_INPUT_BPC; } if (status == DML_VALIDATION_OK) { - locals->ModeSupport[i][j] = true; + locals->ModeSupport[idx][j] = true; } else { - locals->ModeSupport[i][j] = false; + locals->ModeSupport[idx][j] = false; } - locals->ValidationStatus[i] = status; + locals->ValidationStatus[idx] = status; } } { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c index 591d9618bdc0..59edfcf27d91 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c @@ -196,13 +196,13 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), + 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), + 1) - 3); } rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); @@ -222,11 +222,11 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma } else { - detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), - 256, - 0) / 64.0; // 2/3 to chroma + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), + 256, + 0) / 64.0); // 2/3 to chroma } } rq_regs->plane1_base_address = detile_buf_plane1_addr; @@ -451,8 +451,8 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height - + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -601,7 +601,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, if (surf_linear) { unsigned int dpte_row_height; - log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries + log2_dpte_row_height_linear = (unsigned int)dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries / bytes_per_element, dpte_buf_in_pte_reqs * dpte_req_width) @@ -671,7 +671,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); } @@ -1018,11 +1018,11 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, if (dout->dsc_enable) { double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dispclk_delay_subtotal += dsc_delay; + dispclk_delay_subtotal += (unsigned int)dsc_delay; } - pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz - + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; + pixel_rate_delay_subtotal = (unsigned int)(dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz + + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz); vstartup_start = dst->vstartup_start; if (interlaced) { @@ -1043,7 +1043,7 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, // TODO: Where is this coming from? if (interlaced) - vstartup_start = vstartup_start / 2; + vstartup_start = (unsigned int)(vstartup_start / 2); // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? if (vstartup_start >= min_vblank) { @@ -1062,8 +1062,8 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, min_vblank); } - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_y_after_scaler = (unsigned int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", @@ -1376,57 +1376,57 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); - disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); + disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2)); - disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); - disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); + disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19)); + disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19)); disp_dlg_regs->refcyc_per_pte_group_vblank_l = - (unsigned int) (dst_y_per_row_vblank * (double) htotal - * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); + (unsigned int)(dst_y_per_row_vblank * (double) htotal + * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank - * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int)(dst_y_per_row_vblank + * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_c); ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13)); } disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = - (unsigned int) (dst_y_per_row_vblank * (double) htotal - * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); + (unsigned int)(dst_y_per_row_vblank * (double) htotal + * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now - disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal - * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; - disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal - * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; + disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int)((dst_y_per_row_flip * htotal + * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l); + disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int)((dst_y_per_row_flip * htotal + * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip - * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; - disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip - * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; + disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int)((dst_y_per_row_flip + * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int)((dst_y_per_row_flip + * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c); } - disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l - / (double) vratio_l * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)(((double) dpte_row_height_l + / (double) vratio_l * dml_pow(2, 2))); ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); if (dual_plane) { - disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c - / (double) vratio_c * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int)(((double) dpte_row_height_c + / (double) vratio_c * dml_pow(2, 2))); if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", __func__, @@ -1435,38 +1435,38 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, } } - disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l - / (double) vratio_l * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int)(((double) meta_row_height_l + / (double) vratio_l * dml_pow(2, 2))); ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now - disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l - / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_l); + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(((double) dpte_row_height_l + / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_l)); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l - / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq - / (double) meta_chunks_per_row_ub_l); + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(((double) meta_row_height_l + / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq + / (double) meta_chunks_per_row_ub_l)); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_nom_c = - (unsigned int) ((double) dpte_row_height_c / (double) vratio_c - * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_pte_group_nom_c = + (unsigned int)(((double) dpte_row_height_c / (double) vratio_c + * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_c)); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); // TODO: Is this the right calculation? Does htotal need to be halved? - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = - (unsigned int) ((double) meta_row_height_c / (double) vratio_c - * (double) htotal * ref_freq_to_pix_freq - / (double) meta_chunks_per_row_ub_c); + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = + (unsigned int)(((double) meta_row_height_c / (double) vratio_c + * (double) htotal * ref_freq_to_pix_freq + / (double) meta_chunks_per_row_ub_c)); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, @@ -1490,22 +1490,22 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off - disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c - * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int)(refcyc_per_req_delivery_pre_l + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int)(refcyc_per_req_delivery_l + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int)(refcyc_per_req_delivery_pre_c + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int)(refcyc_per_req_delivery_c + * dml_pow(2, 10)); disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = - (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 - * dml_pow(2, 10)); + (unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int)(refcyc_per_req_delivery_cur0 + * dml_pow(2, 10)); disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = - (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 - * dml_pow(2, 10)); + (unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int)(refcyc_per_req_delivery_cur1 + * dml_pow(2, 10)); disp_ttu_regs->qos_level_low_wm = 0; ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal @@ -1520,7 +1520,7 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1557,7 +1557,7 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); @@ -1620,7 +1620,7 @@ static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, cur_req_size = 256; } - cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double) cur_req_size / ((double) cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; cur_req_per_width = cur_width_ub / (double) cur_req_width; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c index d4dddc9d535a..1d2e477da032 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c @@ -196,13 +196,13 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), + 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), + 1) - 3); } rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); @@ -222,11 +222,11 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma } else { - detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), - 256, - 0) / 64.0; // 2/3 to chroma + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), + 256, + 0) / 64.0); // 2/3 to chroma } } rq_regs->plane1_base_address = detile_buf_plane1_addr; @@ -451,8 +451,8 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height - + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -601,7 +601,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, if (surf_linear) { unsigned int dpte_row_height; - log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries + log2_dpte_row_height_linear = (unsigned int)dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries / bytes_per_element, dpte_buf_in_pte_reqs * dpte_req_width) @@ -671,7 +671,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); } @@ -1019,11 +1019,11 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, if (dout->dsc_enable) { double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dispclk_delay_subtotal += dsc_delay; + dispclk_delay_subtotal += (unsigned int)dsc_delay; } - pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz - + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; + pixel_rate_delay_subtotal = (unsigned int)(dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz + + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz); vstartup_start = dst->vstartup_start; if (interlaced) { @@ -1044,7 +1044,7 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, // TODO: Where is this coming from? if (interlaced) - vstartup_start = vstartup_start / 2; + vstartup_start = (unsigned int)(vstartup_start / 2); // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? if (vstartup_start >= min_vblank) { @@ -1063,8 +1063,8 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, min_vblank); } - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_y_after_scaler = (unsigned int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", @@ -1377,57 +1377,57 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); - disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); - disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); + disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2)); - disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); - disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); + disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19)); + disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19)); disp_dlg_regs->refcyc_per_pte_group_vblank_l = - (unsigned int) (dst_y_per_row_vblank * (double) htotal - * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); + (unsigned int)(dst_y_per_row_vblank * (double) htotal + * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank - * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int)(dst_y_per_row_vblank + * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_c); ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13)); } disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = - (unsigned int) (dst_y_per_row_vblank * (double) htotal - * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); + (unsigned int)(dst_y_per_row_vblank * (double) htotal + * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now - disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal - * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; - disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal - * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; + disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int)((dst_y_per_row_flip * htotal + * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l); + disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int)((dst_y_per_row_flip * htotal + * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip - * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; - disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip - * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; + disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int)((dst_y_per_row_flip + * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int)((dst_y_per_row_flip + * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c); } - disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l - / (double) vratio_l * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)(((double) dpte_row_height_l + / (double) vratio_l * dml_pow(2, 2))); ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); if (dual_plane) { - disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c - / (double) vratio_c * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int)(((double) dpte_row_height_c + / (double) vratio_c * dml_pow(2, 2))); if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", __func__, @@ -1436,38 +1436,38 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, } } - disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l - / (double) vratio_l * dml_pow(2, 2)); + disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int)(((double) meta_row_height_l + / (double) vratio_l * dml_pow(2, 2))); ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now - disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l - / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_l); + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(((double) dpte_row_height_l + / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_l)); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l - / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq - / (double) meta_chunks_per_row_ub_l); + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(((double) meta_row_height_l + / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq + / (double) meta_chunks_per_row_ub_l)); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { - disp_dlg_regs->refcyc_per_pte_group_nom_c = - (unsigned int) ((double) dpte_row_height_c / (double) vratio_c - * (double) htotal * ref_freq_to_pix_freq - / (double) dpte_groups_per_row_ub_c); + disp_dlg_regs->refcyc_per_pte_group_nom_c = + (unsigned int)(((double) dpte_row_height_c / (double) vratio_c + * (double) htotal * ref_freq_to_pix_freq + / (double) dpte_groups_per_row_ub_c)); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); // TODO: Is this the right calculation? Does htotal need to be halved? - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = - (unsigned int) ((double) meta_row_height_c / (double) vratio_c - * (double) htotal * ref_freq_to_pix_freq - / (double) meta_chunks_per_row_ub_c); + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = + (unsigned int)(((double) meta_row_height_c / (double) vratio_c + * (double) htotal * ref_freq_to_pix_freq + / (double) meta_chunks_per_row_ub_c)); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, @@ -1491,22 +1491,22 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off - disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c - * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c - * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int)(refcyc_per_req_delivery_pre_l + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int)(refcyc_per_req_delivery_l + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int)(refcyc_per_req_delivery_pre_c + * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int)(refcyc_per_req_delivery_c + * dml_pow(2, 10)); disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = - (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 - * dml_pow(2, 10)); + (unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int)(refcyc_per_req_delivery_cur0 + * dml_pow(2, 10)); disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = - (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); - disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 - * dml_pow(2, 10)); + (unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); + disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int)(refcyc_per_req_delivery_cur1 + * dml_pow(2, 10)); disp_ttu_regs->qos_level_low_wm = 0; ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal @@ -1521,7 +1521,7 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1558,7 +1558,7 @@ void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); @@ -1621,7 +1621,7 @@ static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, cur_req_size = 256; } - cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double) cur_req_size / ((double) cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; cur_req_per_width = cur_width_ub / (double) cur_req_width; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index 11570a0c9427..961b705acfa9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -296,7 +296,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double UrgentOutOfOrderReturn, double ReturnBW, bool GPUVMEnable, - int dpte_group_bytes[], + unsigned int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, @@ -307,7 +307,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, - int DPPPerPlane[], + unsigned int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], double SwathWidthSingleDPPY[], @@ -346,7 +346,7 @@ static void CalculateDCFCLKDeepSleep( double BytePerPixelDETC[], double VRatio[], double SwathWidthY[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double HRatio[], double PixelClock[], double PSCL_THROUGHPUT[], @@ -390,7 +390,7 @@ static void CalculatePixelDeliveryTimes( double VRatioPrefetchC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double HRatio[], double PixelClock[], double PSCL_THROUGHPUT[], @@ -436,7 +436,7 @@ static void CalculateMetaAndPTETimes( unsigned int meta_row_height[], unsigned int meta_req_width[], unsigned int meta_req_height[], - int dpte_group_bytes[], + unsigned int dpte_group_bytes[], unsigned int PTERequestSizeY[], unsigned int PTERequestSizeC[], unsigned int PixelPTEReqWidthY[], @@ -477,8 +477,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, int HostVMMaxPageTableLevels, @@ -521,7 +521,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -729,22 +729,22 @@ static bool CalculatePrefetchSchedule( } if (myPipe->ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + DPPCLKDelayCNVCFormater + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor); - DISPCLKCycles = DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)(DISPCLKDelaySubtotal); if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) return true; - *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK - + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay; + *DSTXAfterScaler = (unsigned int)(DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay); - if (myPipe->DPPPerPlane > 1) - *DSTXAfterScaler = *DSTXAfterScaler + ScalerRecoutWidth; + if (myPipe->DPPPerPlane > 1) + *DSTXAfterScaler = (unsigned int)(*DSTXAfterScaler + ScalerRecoutWidth); if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && ProgressiveToInterlaceUnitInOPP)) *DSTYAfterScaler = 1; @@ -755,7 +755,7 @@ static bool CalculatePrefetchSchedule( *DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1); *DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal)); - *VUpdateOffsetPix = dml_ceil(myPipe->HTotal / 4.0, 1); + *VUpdateOffsetPix = (unsigned int)(dml_ceil(myPipe->HTotal / 4.0, 1)); TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / myPipe->DPPCLK + 3.0 / myPipe->DISPCLK); *VUpdateWidthPix = (14.0 / myPipe->DCFCLKDeepSleep + 12.0 / myPipe->DPPCLK + TotalRepeaterDelayTime) * myPipe->PixelClock; @@ -783,11 +783,11 @@ static bool CalculatePrefetchSchedule( Tdmsks = Tdmsks / 2; if (VStartup * LineTime < Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) { - MyError = true; - *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (Tsetup + TWait - + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime; + MyError = (unsigned int)(true); + *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (unsigned int)((Tsetup + TWait + + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime); } else - *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = 0.0; + *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (unsigned int)(0U); } else Tdm = 0; @@ -808,13 +808,13 @@ static bool CalculatePrefetchSchedule( Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime; if (myPipe->SourceScan == dm_horz) { - *swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockWidth256BytesY) + myPipe->BlockWidth256BytesY; + *swath_width_luma_ub = (unsigned int)(dml_ceil(SwathWidthY - 1, myPipe->BlockWidth256BytesY) + myPipe->BlockWidth256BytesY); if (myPipe->BlockWidth256BytesC > 0) - *swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->BlockWidth256BytesC; + *swath_width_chroma_ub = (unsigned int)(dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->BlockWidth256BytesC); } else { - *swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeight256BytesY; + *swath_width_luma_ub = (unsigned int)(dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeight256BytesY); if (myPipe->BlockHeight256BytesC > 0) - *swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->BlockHeight256BytesC; + *swath_width_chroma_ub = (unsigned int)(dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->BlockHeight256BytesC); } prefetch_bw_oto = (PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC * *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) / Tsw_oto; @@ -1228,14 +1228,14 @@ static double CalculatePrefetchSourceLines( if (!mode_lib->vba.IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; else MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)(dml_max(1U, MaxPartialSwath)); } else { @@ -1243,7 +1243,7 @@ static double CalculatePrefetchSourceLines( dml_print( "WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)(dml_ceil(*VInitPreFill / SwathHeight, 1)); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; @@ -1252,7 +1252,7 @@ static double CalculatePrefetchSourceLines( % SwathHeight; } - return *MaxNumSwath * SwathHeight + MaxPartialSwath; + return (unsigned int)(*MaxNumSwath * SwathHeight + MaxPartialSwath); } static unsigned int CalculateVMAndRowBytes( @@ -1307,34 +1307,34 @@ static unsigned int CalculateVMAndRowBytes( *MetaRequestHeight = 8 * BlockHeight256Bytes; *MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection == dm_horz) { - *meta_row_height = *MetaRequestHeight; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) - + *MetaRequestWidth; - *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)(*MetaRequestHeight); + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + + *MetaRequestWidth); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0); } else { - *meta_row_height = *MetaRequestWidth; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) - + *MetaRequestHeight; - *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_height = (unsigned int)(*MetaRequestWidth); + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + + *MetaRequestHeight); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0); } if (ScanDirection == dm_horz) { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } else { - DCCMetaSurfaceBytes = DCCMetaPitch + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil( (double) ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel - / 256; + / 256); } if (GPUVMEnable == true) { - *MetaPTEBytesFrame = (dml_ceil( + *MetaPTEBytesFrame = (unsigned int)((dml_ceil( (double) (DCCMetaSurfaceBytes - VMMPageSize) / (8 * VMMPageSize), - 1) + 1) * 64; + 1) + 1) * 64); MPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) - 2); } else { *MetaPTEBytesFrame = 0; @@ -1367,9 +1367,9 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && (mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) > 2) { if (ScanDirection == dm_horz) { - *DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1); + *DPDE0BytesFrame = (unsigned int)(64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1)); } else { - *DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1); + *DPDE0BytesFrame = (unsigned int)(64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1)); } ExtraDPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) - 3); } else { @@ -1390,7 +1390,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeightPTEs = 1; *PixelPTEReqHeight = 1; - *PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel; + *PixelPTEReqWidth = (unsigned int)(8.0 * VMMPageSize / BytePerPixel); *PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (MacroTileSizeBytes == 4096) { @@ -1417,20 +1417,20 @@ static unsigned int CalculateVMAndRowBytes( } if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = dml_min(128, + *dpte_row_height = (unsigned int)dml_min(128, 1 << (unsigned int) dml_floor( dml_log2( (double) PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); - *dpte_row_width_ub = (dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (unsigned int)((dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else if (ScanDirection == dm_horz) { *dpte_row_height = *PixelPTEReqHeight; - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (unsigned int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else { - *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight; + *dpte_row_height = (unsigned int)(dml_min(*PixelPTEReqWidth, *MacroTileWidth)); + *dpte_row_width_ub = (unsigned int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; } if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop) @@ -1805,7 +1805,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), @@ -1819,18 +1819,18 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], bpp, - dml_ceil( + (unsigned int)dml_ceil( (double) mode_lib->vba.HActive[k] / mode_lib->vba.NumberOfDSCSlices[k], 1), - slices / 2.0, + (unsigned int)(slices / 2.0), mode_lib->vba.OutputFormat[k]) + dscComputeDelay( mode_lib->vba.OutputFormat[k])); } - locals->DSCDelay[k] = locals->DSCDelay[k] + locals->DSCDelay[k] = (unsigned int)(locals->DSCDelay[k] * mode_lib->vba.PixelClock[k] - / mode_lib->vba.PixelClockBackEnd[k]; + / mode_lib->vba.PixelClockBackEnd[k]); } else { locals->DSCDelay[k] = 0; } @@ -1856,8 +1856,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelDETY[k], 1), - dml_ceil(locals->BytePerPixelDETC[k], 2), + (unsigned int)dml_ceil(locals->BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(locals->BytePerPixelDETC[k], 2), &locals->BlockHeight256BytesY[k], &locals->BlockHeight256BytesC[k], &locals->BlockWidth256BytesY[k], @@ -1886,13 +1886,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman locals->BlockWidth256BytesC[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil( + (unsigned int)dml_ceil( locals->BytePerPixelDETC[k], 2), mode_lib->vba.SourceScan[k], - mode_lib->vba.ViewportWidth[k] / 2, + (unsigned int)(mode_lib->vba.ViewportWidth[k] / 2), mode_lib->vba.ViewportHeight[k] / 2, - locals->SwathWidthY[k] / 2, + (unsigned int)(locals->SwathWidthY[k] / 2), mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxPageTableLevels, @@ -1945,11 +1945,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman locals->BlockWidth256BytesY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelDETY[k], 1), + (unsigned int)dml_ceil(locals->BytePerPixelDETY[k], 1), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], - locals->SwathWidthY[k], + (unsigned int)locals->SwathWidthY[k], mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxPageTableLevels, @@ -2053,7 +2053,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / mode_lib->vba.DISPCLK; } else locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; @@ -2072,7 +2072,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.WritebackLumaVTaps[j], mode_lib->vba.WritebackChromaHTaps[j], mode_lib->vba.WritebackChromaVTaps[j], - mode_lib->vba.WritebackDestinationWidth[j]) + (unsigned int)mode_lib->vba.WritebackDestinationWidth[j]) / mode_lib->vba.DISPCLK); } } @@ -2087,11 +2087,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.VStartupLines = 13; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - locals->MaxVStartupLines[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1)); + locals->MaxVStartupLines[k] = (unsigned int)(mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1))); } for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) - locals->MaximumMaxVStartupLines = dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k]); + locals->MaximumMaxVStartupLines = (unsigned int)(dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k])); // We don't really care to iterate between the various prefetch modes //mode_lib->vba.PrefetchERROR = CalculateMinAndMaxPrefetchMode(mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &mode_lib->vba.MinPrefetchMode, &mode_lib->vba.MaxPrefetchMode); @@ -2177,7 +2177,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman / mode_lib->vba.HRatio[k]), mode_lib->vba.OutputFormat[k], mode_lib->vba.MaxInterDCNTileRepeaters, - dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]), + (unsigned int)dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]), locals->MaxVStartupLines[k], mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMEnable, @@ -2189,11 +2189,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.UrgentLatency, mode_lib->vba.UrgentExtraLatency, mode_lib->vba.TCalc, - locals->PDEAndMetaPTEBytesFrame[k], - locals->MetaRowByte[k], - locals->PixelPTEBytesPerRow[k], + (unsigned int)locals->PDEAndMetaPTEBytesFrame[k], + (unsigned int)locals->MetaRowByte[k], + (unsigned int)locals->PixelPTEBytesPerRow[k], locals->PrefetchSourceLinesY[k], - locals->SwathWidthY[k], + (unsigned int)locals->SwathWidthY[k], locals->BytePerPixelDETY[k], locals->VInitPreFillY[k], locals->MaxNumSwathY[k], @@ -2226,7 +2226,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman &mode_lib->vba.VUpdateWidthPix[k], &mode_lib->vba.VReadyOffsetPix[k]); if (mode_lib->vba.BlendingAndTiming[k] == k) { - locals->VStartup[k] = dml_min( + locals->VStartup[k] = (unsigned int)dml_min( mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]); if (locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata @@ -2236,7 +2236,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } } else { locals->VStartup[k] = - dml_min( + (unsigned int)dml_min( mode_lib->vba.VStartupLines, locals->MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); } @@ -2256,13 +2256,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.DETBufferSizeInKByte[0], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], - locals->SwathWidthY[k], + (unsigned int)locals->SwathWidthY[k], mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], mode_lib->vba.UrgentLatency, mode_lib->vba.CursorBufferSize, mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1], - dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), + (unsigned int)dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), mode_lib->vba.VRatio[k], locals->VRatioPrefetchY[k], locals->VRatioPrefetchC[k], @@ -2333,7 +2333,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.TotImmediateFlipBytes = 0; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k] + locals->PixelPTEBytesPerRow[k]; + mode_lib->vba.TotImmediateFlipBytes = (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k] + locals->PixelPTEBytesPerRow[k]); } for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { CalculateFlipSchedule( @@ -2600,7 +2600,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman locals->BlockHeight256BytesY[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SurfaceTiling[k], - locals->BytePerPixelDETY[k], + (unsigned int)locals->BytePerPixelDETY[k], mode_lib->vba.SourceScan[k], &locals->DCCYMaxUncompressedBlock[k], &locals->DCCYMaxCompressedBlock[k], @@ -2722,7 +2722,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.FrameTimeForMinFullDETBufferingTime = (double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; - locals->BytePerPixelYCriticalPlane = dml_ceil(locals->BytePerPixelDETY[k], 1); + locals->BytePerPixelYCriticalPlane = (unsigned int)(dml_ceil(locals->BytePerPixelDETY[k], 1)); locals->SwathWidthYCriticalPlane = locals->SwathWidthY[k]; locals->LinesToFinishSwathTransferStutterCriticalPlane = mode_lib->vba.SwathHeightY[k] - (locals->LinesInDETY[k] - locals->LinesInDETYRoundedDownToSwath[k]); @@ -2993,11 +2993,11 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { - mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)(MaximumSwathHeightY); + mode_lib->vba.SwathHeightC[k] = (unsigned int)(MaximumSwathHeightC); } else { - mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; - mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; + mode_lib->vba.SwathHeightY[k] = (unsigned int)(MinimumSwathHeightY); + mode_lib->vba.SwathHeightC[k] = (unsigned int)(MinimumSwathHeightC); } CalculateDETBufferSize( @@ -3317,9 +3317,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 6) return BPP_INVALID; else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1.0 / 16.0) - return 1.5 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(1.5 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 6 || DesiredBPP < 6 @@ -3327,7 +3327,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)(DesiredBPP); } } } else if (Format == dm_n422) { @@ -3335,9 +3335,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 7) return BPP_INVALID; else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1.0 / 16.0) - return 2 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(2 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 7 || DesiredBPP < 7 @@ -3345,7 +3345,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)(DesiredBPP); } } } else { @@ -3353,9 +3353,9 @@ static unsigned int TruncToValidBPP( if (DecimalBPP < 8) return BPP_INVALID; else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1.0 / 16.0) - return 3 * DSCInputBitPerComponent - 1.0 / 16.0; + return (unsigned int)(3 * DSCInputBitPerComponent - 1.0 / 16.0); else - return dml_floor(16 * DecimalBPP, 1) / 16.0; + return (unsigned int)(dml_floor(16 * DecimalBPP, 1) / 16.0); } else { if (DecimalBPP < 8 || DesiredBPP < 8 @@ -3363,7 +3363,7 @@ static unsigned int TruncToValidBPP( || DecimalBPP < DesiredBPP) { return BPP_INVALID; } else { - return DesiredBPP; + return (unsigned int)(DesiredBPP); } } } @@ -3462,18 +3462,18 @@ static noinline void CalculatePrefetchSchedulePerPlane( mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, &myPipe, - locals->DSCDelayPerState[i][k], + (unsigned int)locals->DSCDelayPerState[i][k], mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal, - locals->SwathWidthYThisState[k] / mode_lib->vba.HRatio[k], + (unsigned int)(locals->SwathWidthYThisState[k] / mode_lib->vba.HRatio[k]), mode_lib->vba.OutputFormat[k], mode_lib->vba.MaxInterDCNTileRepeaters, - dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[0][0][k]), - locals->MaximumVStartup[0][0][k], + (unsigned int)dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[0][0][k]), + (unsigned int)locals->MaximumVStartup[0][0][k], mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMEnable, &myHostVM, @@ -3484,11 +3484,11 @@ static noinline void CalculatePrefetchSchedulePerPlane( mode_lib->vba.UrgentLatency, mode_lib->vba.ExtraLatency, mode_lib->vba.TimeCalc, - locals->PDEAndMetaPTEBytesPerFrame[0][0][k], - locals->MetaRowBytes[0][0][k], - locals->DPTEBytesPerRow[0][0][k], + (unsigned int)locals->PDEAndMetaPTEBytesPerFrame[0][0][k], + (unsigned int)locals->MetaRowBytes[0][0][k], + (unsigned int)locals->DPTEBytesPerRow[0][0][k], locals->PrefetchLinesY[0][0][k], - locals->SwathWidthYThisState[k], + (unsigned int)locals->SwathWidthYThisState[k], locals->BytePerPixelInDETY[k], locals->PrefillY[k], locals->MaxNumSwY[k], @@ -3525,8 +3525,8 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l { struct vba_vars_st *locals = &mode_lib->vba; - int i; - unsigned int j, k, m; + int idx; + unsigned int i, j, k, m; /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ @@ -3951,8 +3951,8 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l Calculate256BBlockSizes( mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelInDETY[k], 1.0), - dml_ceil(locals->BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETC[k], 2.0), &locals->Read256BlockHeightY[k], &locals->Read256BlockHeightC[k], &locals->Read256BlockWidthY[k], @@ -4141,7 +4141,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->DISPCLK_DPPCLK_Support[i][j] = false; } } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)(0.0); for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; if (j == 1) { @@ -4196,7 +4196,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l || mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) locals->DISPCLK_DPPCLK_Support[i][j] = false; } - locals->TotalNumberOfActiveDPP[i][j] = 0.0; + locals->TotalNumberOfActiveDPP[i][j] = (unsigned int)(0.0); for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; } @@ -4455,19 +4455,19 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.slices = 0; } else if (locals->RequiresDSC[i][k] == 0 || locals->RequiresDSC[i][k] == false) { - mode_lib->vba.slices = 0; + mode_lib->vba.slices = (unsigned int)(0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { - mode_lib->vba.slices = dml_ceil( + mode_lib->vba.slices = (unsigned int)dml_ceil( mode_lib->vba.PixelClockBackEnd[k] / 400.0, 4.0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { - mode_lib->vba.slices = 8.0; + mode_lib->vba.slices = (unsigned int)(8.0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { - mode_lib->vba.slices = 4.0; + mode_lib->vba.slices = (unsigned int)(4.0); } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { - mode_lib->vba.slices = 2.0; + mode_lib->vba.slices = (unsigned int)(2.0); } else { - mode_lib->vba.slices = 1.0; + mode_lib->vba.slices = (unsigned int)(1.0); } if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE || locals->OutputBppPerState[i][k] == BPP_INVALID) { @@ -4481,7 +4481,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil( + (unsigned int)dml_ceil( mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), @@ -4494,7 +4494,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 2.0 * (dscceComputeDelay( mode_lib->vba.DSCInputBitPerComponent[k], mode_lib->vba.bpp, - dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), + (unsigned int)dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), mode_lib->vba.slices / 2, mode_lib->vba.OutputFormat[k]) + dscComputeDelay(mode_lib->vba.OutputFormat[k])); @@ -4569,13 +4569,13 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } if (mode_lib->vba.RoundedUpMaxSwathSizeBytesY + mode_lib->vba.RoundedUpMaxSwathSizeBytesC <= mode_lib->vba.DETBufferSizeInKByte[0] * 1024.0 / 2.0) { - locals->SwathHeightYThisState[k] = locals->MaxSwathHeightY[k]; - locals->SwathHeightCThisState[k] = locals->MaxSwathHeightC[k]; + locals->SwathHeightYThisState[k] = (unsigned int)(locals->MaxSwathHeightY[k]); + locals->SwathHeightCThisState[k] = (unsigned int)(locals->MaxSwathHeightC[k]); } else { locals->SwathHeightYThisState[k] = - locals->MinSwathHeightY[k]; + (unsigned int)locals->MinSwathHeightY[k]; locals->SwathHeightCThisState[k] = - locals->MinSwathHeightC[k]; + (unsigned int)locals->MinSwathHeightC[k]; } } @@ -4607,11 +4607,11 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->Read256BlockWidthC[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelInDETC[k], 2.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETC[k], 2.0), mode_lib->vba.SourceScan[k], - mode_lib->vba.ViewportWidth[k] / 2.0, - mode_lib->vba.ViewportHeight[k] / 2.0, - locals->SwathWidthYThisState[k] / 2.0, + (unsigned int)(mode_lib->vba.ViewportWidth[k] / 2.0), + (unsigned int)(mode_lib->vba.ViewportHeight[k] / 2.0), + (unsigned int)(locals->SwathWidthYThisState[k] / 2.0), mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxPageTableLevels, @@ -4619,7 +4619,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.VMMPageSize, mode_lib->vba.PTEBufferSizeInRequestsChroma, mode_lib->vba.PitchC[k], - 0.0, + 0, &locals->MacroTileWidthC[k], &mode_lib->vba.MetaRowBytesC, &mode_lib->vba.DPTEBytesPerRowC, @@ -4650,8 +4650,8 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma; } else { mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0; - mode_lib->vba.MetaRowBytesC = 0.0; - mode_lib->vba.DPTEBytesPerRowC = 0.0; + mode_lib->vba.MetaRowBytesC = (unsigned int)(0.0); + mode_lib->vba.DPTEBytesPerRowC = (unsigned int)(0.0); locals->PrefetchLinesC[0][0][k] = 0.0; locals->PTEBufferSizeNotExceededC[i][j][k] = true; locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma; @@ -4663,11 +4663,11 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l locals->Read256BlockWidthY[k], mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceTiling[k], - dml_ceil(locals->BytePerPixelInDETY[k], 1.0), + (unsigned int)dml_ceil(locals->BytePerPixelInDETY[k], 1.0), mode_lib->vba.SourceScan[k], mode_lib->vba.ViewportWidth[k], mode_lib->vba.ViewportHeight[k], - locals->SwathWidthYThisState[k], + (unsigned int)locals->SwathWidthYThisState[k], mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxPageTableLevels, @@ -4756,7 +4756,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackLumaVTaps[k], mode_lib->vba.WritebackChromaHTaps[k], mode_lib->vba.WritebackChromaVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; + (unsigned int)mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; } else { locals->WritebackDelay[i][k] = 0.0; } @@ -4773,7 +4773,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackLumaVTaps[m], mode_lib->vba.WritebackChromaHTaps[m], mode_lib->vba.WritebackChromaVTaps[m], - mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); + (unsigned int)mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]); } } } @@ -4809,14 +4809,14 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0; mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - unsigned int m; + unsigned int cursor_idx; locals->cursor_bw[k] = 0; locals->cursor_bw_pre[k] = 0; - for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) { - locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] + for (cursor_idx = 0; cursor_idx < mode_lib->vba.NumberOfCursors[k]; cursor_idx++) { + locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][cursor_idx] * mode_lib->vba.CursorBPP[k][cursor_idx] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; - locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] + locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][cursor_idx] * mode_lib->vba.CursorBPP[k][cursor_idx] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPreY[i][j][k]; } @@ -4824,12 +4824,12 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DETBufferSizeInKByte[0], locals->SwathHeightYThisState[k], locals->SwathHeightCThisState[k], - locals->SwathWidthYThisState[k], + (unsigned int)locals->SwathWidthYThisState[k], mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], mode_lib->vba.UrgentLatency, mode_lib->vba.CursorBufferSize, mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1], - dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), + (unsigned int)dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), mode_lib->vba.VRatio[k], locals->VRatioPreY[i][j][k], locals->VRatioPreC[i][j][k], @@ -4922,10 +4922,10 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l + locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); } - mode_lib->vba.TotImmediateFlipBytes = 0.0; + mode_lib->vba.TotImmediateFlipBytes = (unsigned int)(0.0); for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes - + locals->PDEAndMetaPTEBytesPerFrame[0][0][k] + locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k]; + mode_lib->vba.TotImmediateFlipBytes = (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + + locals->PDEAndMetaPTEBytesPerFrame[0][0][k] + locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k]); } for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { @@ -5138,7 +5138,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { + for (idx = mode_lib->vba.soc.num_states; idx >= 0; idx--) { for (j = 0; j < 2; j++) { enum dm_validation_status status = DML_VALIDATION_OK; @@ -5146,19 +5146,19 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l status = DML_FAIL_SCALE_RATIO_TAP; } else if (!mode_lib->vba.SourceFormatPixelAndScanSupport) { status = DML_FAIL_SOURCE_PIXEL_FORMAT; - } else if (!locals->ViewportSizeSupport[i][0]) { + } else if (!locals->ViewportSizeSupport[idx][0]) { status = DML_FAIL_VIEWPORT_SIZE; - } else if (!locals->DIOSupport[i]) { + } else if (!locals->DIOSupport[idx]) { status = DML_FAIL_DIO_SUPPORT; - } else if (locals->NotEnoughDSCUnits[i]) { + } else if (locals->NotEnoughDSCUnits[idx]) { status = DML_FAIL_NOT_ENOUGH_DSC; - } else if (locals->DSCCLKRequiredMoreThanSupported[i]) { + } else if (locals->DSCCLKRequiredMoreThanSupported[idx]) { status = DML_FAIL_DSC_CLK_REQUIRED; - } else if (!locals->ROBSupport[i][0]) { + } else if (!locals->ROBSupport[idx][0]) { status = DML_FAIL_REORDERING_BUFFER; - } else if (!locals->DISPCLK_DPPCLK_Support[i][j]) { + } else if (!locals->DISPCLK_DPPCLK_Support[idx][j]) { status = DML_FAIL_DISPCLK_DPPCLK; - } else if (!locals->TotalAvailablePipesSupport[i][j]) { + } else if (!locals->TotalAvailablePipesSupport[idx][j]) { status = DML_FAIL_TOTAL_AVAILABLE_PIPES; } else if (!mode_lib->vba.NumberOfOTGSupport) { status = DML_FAIL_NUM_OTG; @@ -5172,27 +5172,27 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l status = DML_FAIL_CURSOR_SUPPORT; } else if (!mode_lib->vba.PitchSupport) { status = DML_FAIL_PITCH_SUPPORT; - } else if (!locals->TotalVerticalActiveBandwidthSupport[i][0]) { + } else if (!locals->TotalVerticalActiveBandwidthSupport[idx][0]) { status = DML_FAIL_TOTAL_V_ACTIVE_BW; - } else if (!locals->PTEBufferSizeNotExceeded[i][j]) { + } else if (!locals->PTEBufferSizeNotExceeded[idx][j]) { status = DML_FAIL_PTE_BUFFER_SIZE; } else if (mode_lib->vba.NonsupportedDSCInputBPC) { status = DML_FAIL_DSC_INPUT_BPC; } else if ((mode_lib->vba.HostVMEnable - && !locals->ImmediateFlipSupportedForState[i][j])) { + && !locals->ImmediateFlipSupportedForState[idx][j])) { status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP; - } else if (!locals->PrefetchSupported[i][j]) { + } else if (!locals->PrefetchSupported[idx][j]) { status = DML_FAIL_PREFETCH_SUPPORT; - } else if (!locals->VRatioInPrefetchSupported[i][j]) { + } else if (!locals->VRatioInPrefetchSupported[idx][j]) { status = DML_FAIL_V_RATIO_PREFETCH; } if (status == DML_VALIDATION_OK) { - locals->ModeSupport[i][j] = true; + locals->ModeSupport[idx][j] = true; } else { - locals->ModeSupport[i][j] = false; + locals->ModeSupport[idx][j] = false; } - locals->ValidationStatus[i] = status; + locals->ValidationStatus[idx] = status; } } { @@ -5257,7 +5257,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double UrgentOutOfOrderReturn, double ReturnBW, bool GPUVMEnable, - int dpte_group_bytes[], + unsigned int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, @@ -5268,7 +5268,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, - int DPPPerPlane[], + unsigned int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], double SwathWidthSingleDPPY[], @@ -5373,13 +5373,13 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( for (k = 0; k < NumberOfActivePlanes; ++k) { - mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines, + mode_lib->vba.LBLatencyHidingSourceLinesY = (unsigned int)(dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - - (vtaps[k] - 1); + - (vtaps[k] - 1)); - mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines, + mode_lib->vba.LBLatencyHidingSourceLinesC = (unsigned int)(dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / 2 / dml_max(HRatio[k] / 2, 1.0)), 1)) - - (VTAPsChroma[k] - 1); + - (VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]); @@ -5412,12 +5412,12 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( &DETBufferSizeC); LinesInDETY[k] = (double)DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; - LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + LinesInDETYRoundedDownToSwath[k] = (unsigned int)(dml_floor(LinesInDETY[k], SwathHeightY[k])); FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k]; if (BytePerPixelDETC[k] > 0) { LinesInDETC = (double)DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0); - LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); + LinesInDETCRoundedDownToSwath = (unsigned int)(dml_floor(LinesInDETC, SwathHeightC[k])); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / (VRatio[k] / 2); } else { @@ -5543,7 +5543,7 @@ static void CalculateDCFCLKDeepSleep( double BytePerPixelDETC[], double VRatio[], double SwathWidthY[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double HRatio[], double PixelClock[], double PSCL_THROUGHPUT[], @@ -5749,7 +5749,7 @@ static void CalculatePixelDeliveryTimes( double VRatioPrefetchC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double HRatio[], double PixelClock[], double PSCL_THROUGHPUT[], @@ -5870,7 +5870,7 @@ static void CalculateMetaAndPTETimes( unsigned int meta_row_height[], unsigned int meta_req_width[], unsigned int meta_req_height[], - int dpte_group_bytes[], + unsigned int dpte_group_bytes[], unsigned int PTERequestSizeY[], unsigned int PTERequestSizeC[], unsigned int PixelPTEReqWidthY[], @@ -5939,10 +5939,10 @@ static void CalculateMetaAndPTETimes( for (k = 0; k < NumberOfActivePlanes; ++k) { if (DCCEnable[k] == true) { - meta_chunk_width = MetaChunkSize * 1024 * 256 - / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]; - min_meta_chunk_width = MinMetaChunkSizeBytes * 256 - / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]; + meta_chunk_width = (unsigned int)(MetaChunkSize * 1024 * 256 + / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]); + min_meta_chunk_width = (unsigned int)(MinMetaChunkSizeBytes * 256 + / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]); meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width; meta_row_remainder = meta_row_width[k] % meta_chunk_width; if (SourceScan[k] == dm_horz) { @@ -5978,7 +5978,7 @@ static void CalculateMetaAndPTETimes( dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k]; } - dpte_groups_per_row_luma_ub = dml_ceil( + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil( (float) dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] @@ -6002,7 +6002,7 @@ static void CalculateMetaAndPTETimes( / PTERequestSizeC[k] * PixelPTEReqHeightC[k]; } - dpte_groups_per_row_chroma_ub = dml_ceil( + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil( (float) dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); @@ -6032,34 +6032,32 @@ static void CalculateMetaAndPTETimes( if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { if (DCCEnable[k] == false) { if (BytePerPixelDETC[k] > 0) { - num_group_per_lower_vm_stage = + num_group_per_lower_vm_stage = (unsigned int)( dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = - dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (unsigned int)dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (GPUVMMaxPageTableLevels == 1) { if (BytePerPixelDETC[k] > 0) { - num_group_per_lower_vm_stage = + num_group_per_lower_vm_stage = (unsigned int)( dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = - dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (unsigned int)dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (BytePerPixelDETC[k] > 0) { - num_group_per_lower_vm_stage = + num_group_per_lower_vm_stage = (unsigned int)( dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = + num_group_per_lower_vm_stage = (unsigned int)( dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)); } } } @@ -6128,8 +6126,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, int HostVMMaxPageTableLevels, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c index 8a611b3bec33..189b0157fcf3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c @@ -174,19 +174,19 @@ static void extract_rq_regs( extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor( + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor( dml_log2(rq_param->dlg.rq_l.dpte_row_height), - 1) - 3; + 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor( + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor( dml_log2(rq_param->dlg.rq_c.dpte_row_height), - 1) - 3; + 1) - 3); } - rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); - rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); + rq_regs->rq_regs_l.swath_height = (unsigned int)dml_log2(rq_param->dlg.rq_l.swath_height); + rq_regs->rq_regs_c.swath_height = (unsigned int)dml_log2(rq_param->dlg.rq_c.swath_height); // FIXME: take the max between luma, chroma chunk size? // okay for now, as we are setting chunk_bytes to 8kb anyways @@ -202,12 +202,12 @@ static void extract_rq_regs( if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma } else { - detile_buf_plane1_addr = dml_round_to_multiple( + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple( (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 256, - 0) / 64.0; // 2/3 to chroma + 0) / 64.0); // 2/3 to chroma } } rq_regs->plane1_base_address = detile_buf_plane1_addr; @@ -443,8 +443,8 @@ static void get_meta_and_pte_attr( // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height - + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -599,7 +599,7 @@ static void get_meta_and_pte_attr( if (surf_linear) { unsigned int dpte_row_height; - log2_dpte_row_height_linear = dml_floor( + log2_dpte_row_height_linear = (unsigned int)dml_floor( dml_log2( dml_min( 64 * 1024 * pde_buf_entries @@ -678,7 +678,7 @@ static void get_meta_and_pte_attr( // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil( (double) dpte_row_width_ub / dpte_group_width, 1); } @@ -718,18 +718,18 @@ static void get_surf_rq_param( access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed hactive_half = pipe_param->dest.hactive / 2; if (is_chroma) { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; - src_hactive_half = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_half; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width); + src_hactive_half = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_half); } else { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; - src_hactive_half = pipe_param->scale_ratio_depth.hscl_ratio * hactive_half; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width); + src_hactive_half = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * hactive_half); } if (access_dir == 0) { - vp_width = dml_min(full_src_vp_width, src_hactive_half); + vp_width = (unsigned int)dml_min(full_src_vp_width, src_hactive_half); dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); } else { - vp_height = dml_min(full_src_vp_width, src_hactive_half); + vp_height = (unsigned int)dml_min(full_src_vp_width, src_hactive_half); dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); } @@ -1058,11 +1058,11 @@ static void dml_rq_dlg_get_dlg_params( if (dout->dsc_enable) { double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dispclk_delay_subtotal += dsc_delay; + dispclk_delay_subtotal += (unsigned int)dsc_delay; } - pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz - + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; + pixel_rate_delay_subtotal = (unsigned int)(dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz + + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz); vstartup_start = dst->vstartup_start; if (interlaced) { @@ -1105,8 +1105,8 @@ static void dml_rq_dlg_get_dlg_params( min_vblank); } - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_y_after_scaler = (unsigned int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); dml_print( @@ -1446,7 +1446,7 @@ static void dml_rq_dlg_get_dlg_params( // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); @@ -1506,23 +1506,23 @@ static void dml_rq_dlg_get_dlg_params( * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; } - disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; - disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; - disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); - disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // Clamp to max for now if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)dml_pow(2, 23) - 1; if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)dml_pow(2, 23) - 1; if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)dml_pow(2, 23) - 1; if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)dml_pow(2, 23) - 1; disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2)); ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); @@ -1553,12 +1553,12 @@ static void dml_rq_dlg_get_dlg_params( / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)dml_pow(2, 23) - 1; disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)dml_pow(2, 23) - 1; if (dual_plane) { disp_dlg_regs->refcyc_per_pte_group_nom_c = @@ -1566,7 +1566,7 @@ static void dml_rq_dlg_get_dlg_params( * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)dml_pow(2, 23) - 1; // TODO: Is this the right calculation? Does htotal need to be halved? disp_dlg_regs->refcyc_per_meta_chunk_nom_c = @@ -1574,7 +1574,7 @@ static void dml_rq_dlg_get_dlg_params( * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_c); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)dml_pow(2, 23) - 1; } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( @@ -1628,7 +1628,7 @@ static void dml_rq_dlg_get_dlg_params( disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1668,7 +1668,7 @@ void dml21_rq_dlg_get_dlg_reg( mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes( + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes( mode_lib, e2e_pipe_param, num_pipes); @@ -1734,7 +1734,7 @@ static void calculate_ttu_cursor( cur_req_size = 256; } - cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double) cur_req_size / ((double) cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; cur_req_per_width = cur_width_ub / (double) cur_req_width; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c index 0cdd60869ce1..0ba388c6aec1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c @@ -181,7 +181,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { void dcn30_fpu_populate_dml_writeback_from_context( struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) { - int pipe_cnt, i, j; + int pipe_cnt; + unsigned int i, j; double max_calc_writeback_dispclk; double writeback_dispclk; struct writeback_st dout_wb = {0}; @@ -279,11 +280,11 @@ void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, dc_assert_fp_enabled(); for (i = 0; i < ARRAY_SIZE(wb_arb_params->cli_watermark); i++) { - wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; - wb_arb_params->pstate_watermark[i] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000; + wb_arb_params->cli_watermark[i] = (unsigned int)(get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000); + wb_arb_params->pstate_watermark[i] = (unsigned int)(get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000); } - wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */ + wb_arb_params->dram_speed_change_duration = (unsigned int)(dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz); /* num_clock_cycles = us * MHz */ } void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) @@ -308,6 +309,7 @@ void dcn30_fpu_calculate_wm_and_dlg( { int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; int i, pipe_idx; + unsigned int pipe_i, state_i; double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported; unsigned int dummy_latency_index = 0; @@ -367,14 +369,14 @@ void dcn30_fpu_calculate_wm_and_dlg( context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; } - context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); pipes[0].clks_cfg.voltage = vlevel; pipes[0].clks_cfg.dcfclk_mhz = dcfclk; @@ -406,7 +408,7 @@ void dcn30_fpu_calculate_wm_and_dlg( * pstate latency overridden to 5us */ if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { - unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; + unsigned int min_dram_speed_mts = (unsigned int)context->bw_ctx.dml.vba.DRAMSpeed; unsigned int min_dram_speed_mts_margin = 160; context->bw_ctx.dml.soc.dram_clock_change_latency_us = @@ -437,14 +439,14 @@ void dcn30_fpu_calculate_wm_and_dlg( context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; } - context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); if (!pstate_en) { /* The only difference between A and C is p-state latency, if p-state is not supported we want to @@ -460,23 +462,23 @@ void dcn30_fpu_calculate_wm_and_dlg( * Set A calculated last so that following calculations are based on Set A */ dc->res_pool->funcs->update_soc_for_wm_a(dc, context); - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); } - context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; + context->perf_params.stutter_period_us = (unsigned int)context->bw_ctx.dml.vba.StutterPeriod; /* Make set D = set A until set D is enabled */ context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; - for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { - if (!context->res_ctx.pipe_ctx[i].stream) + for (pipe_i = 0, pipe_idx = 0; pipe_i < dc->res_pool->pipe_count; pipe_i++) { + if (!context->res_ctx.pipe_ctx[pipe_i].stream) continue; pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); @@ -500,9 +502,9 @@ void dcn30_fpu_calculate_wm_and_dlg( context->bw_ctx.dml.vba.DRAMSpeed <= 1700 && context->bw_ctx.dml.vba.DRAMSpeed >= 1500) { - for (i = 0; i < dc->dml.soc.num_states; i++) { - if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) { - context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts; + for (state_i = 0; state_i < dc->dml.soc.num_states; state_i++) { + if (dc->dml.soc.clock_limits[state_i].dram_speed_mts > 1700) { + context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[state_i].dram_speed_mts; break; } } @@ -532,13 +534,13 @@ void dcn30_fpu_update_max_clk(struct dc_bounding_box_max_clk *dcn30_bb_max_clk) dc_assert_fp_enabled(); if (!dcn30_bb_max_clk->max_dcfclk_mhz) - dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; + dcn30_bb_max_clk->max_dcfclk_mhz = (int)dcn3_0_soc.clock_limits[0].dcfclk_mhz; if (!dcn30_bb_max_clk->max_dispclk_mhz) - dcn30_bb_max_clk->max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; + dcn30_bb_max_clk->max_dispclk_mhz = (int)dcn3_0_soc.clock_limits[0].dispclk_mhz; if (!dcn30_bb_max_clk->max_dppclk_mhz) - dcn30_bb_max_clk->max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; + dcn30_bb_max_clk->max_dppclk_mhz = (int)dcn3_0_soc.clock_limits[0].dppclk_mhz; if (!dcn30_bb_max_clk->max_phyclk_mhz) - dcn30_bb_max_clk->max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; + dcn30_bb_max_clk->max_phyclk_mhz = (int)dcn3_0_soc.clock_limits[0].phyclk_mhz; } void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, @@ -557,12 +559,12 @@ void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; if (optimal_fclk) - *optimal_fclk = bw_from_dram / - (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_fclk = (unsigned int)(bw_from_dram / + (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100))); if (optimal_dcfclk) - *optimal_dcfclk = bw_from_dram / - (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_dcfclk = (unsigned int)(bw_from_dram / + (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100))); } void dcn30_fpu_update_bw_bounding_box(struct dc *dc, @@ -662,7 +664,7 @@ void dcn3_fpu_build_wm_range_table(struct clk_mgr *base) double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us; double sr_exit_time_us = base->ctx->dc->dml.soc.sr_exit_time_us; double sr_enter_plus_exit_time_us = base->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; - uint16_t min_uclk_mhz = base->bw_params->clk_table.entries[0].memclk_mhz; + uint16_t min_uclk_mhz = (uint16_t)base->bw_params->clk_table.entries[0].memclk_mhz; dc_assert_fp_enabled(); @@ -719,9 +721,9 @@ void dcn3_fpu_build_wm_range_table(struct clk_mgr *base) base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; } -void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip) +void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *soc_bb) { - (void)dcn3_0_ip; + (void)soc_bb; dc_assert_fp_enabled(); if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 634982173190..f0b1bfb408f6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -285,8 +285,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -327,7 +327,7 @@ static void CalculateUrgentBurstFactor( static void UseMinimumDCFCLK( struct display_mode_lib *mode_lib, struct vba_vars_st *v, - int MaxPrefetchMode, + unsigned int MaxPrefetchMode, int ReorderingBytes); static void CalculatePixelDeliveryTimes( @@ -345,7 +345,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][2], @@ -366,39 +366,39 @@ static void CalculatePixelDeliveryTimes( double CursorRequestDeliveryTimePrefetch[]); static void CalculateMetaAndPTETimes( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -421,52 +421,52 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], double TimePerVMRequestFlip[]); static void CalculateStutterEfficiency( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, long ROBBufferSizeInKByte, double TotalDataReadBandwidth, double DCFCLK, double ReturnBW, double SRExitTime, bool SynchronizedVBlank, - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double DCCRateLuma[], double DCCRateChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -479,46 +479,46 @@ static void CalculateStutterEfficiency( static void CalculateSwathAndDETConfiguration( bool ForceSingleDPP, - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, unsigned int DETBufferSizeInKByte, double MaximumSwathWidthLuma[], double MaximumSwathWidthChroma[], enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], bool *ViewportSizeSupport); static void CalculateSwathWidth( bool ForceSingleDPP, - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], unsigned int ViewportWidth[], @@ -528,22 +528,22 @@ static void CalculateSwathWidth( unsigned int SurfaceHeightY[], unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[]); static double CalculateExtraLatency( @@ -558,8 +558,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, double HostVMMinPageSize, @@ -572,9 +572,9 @@ static double CalculateExtraLatencyBytes( int MetaChunkSize, bool GPUVMEnable, bool HostVMEnable, - int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfActivePlanes, + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, double HostVMMinPageSize, @@ -630,7 +630,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -866,13 +866,13 @@ static bool CalculatePrefetchSchedule( v->Tdmdl_vm[k] = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true ? TWait + Tvm_trips : 0); if (myPipe->ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor); - DISPCLKCycles = v->DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)v->DISPCLKDelaySubtotal; if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) return true; @@ -1302,14 +1302,14 @@ static void CalculateDCCConfiguration( horz_div_c = 0; if (BytePerPixelC == 0) { - swath_buf_size = DETBufferSize / 2 - 2 * 256; + swath_buf_size = (long)(DETBufferSize / 2 - 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l)); detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l)); } else { - swath_buf_size = DETBufferSize / 2 - 2 * 2 * 256; + swath_buf_size = (long)(DETBufferSize / 2 - 2 * 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l) @@ -1332,14 +1332,15 @@ static void CalculateDCCConfiguration( MAS_vp_horz_limit = 5760; MAS_vp_vert_limit = (BytePerPixelC > 0 ? 2880 : 5760); - max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); - max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); + max_vp_horz_width = (long)dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); + max_vp_vert_height = (long)dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); eff_surf_width_l = - (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma); + (SurfaceWidthLuma > (unsigned long)max_vp_horz_width ? + (unsigned long)max_vp_horz_width : SurfaceWidthLuma); eff_surf_width_c = eff_surf_width_l / (1 + yuv420); eff_surf_height_l = ( - SurfaceHeightLuma > max_vp_vert_height ? - max_vp_vert_height : SurfaceHeightLuma); + SurfaceHeightLuma > (unsigned long)max_vp_vert_height ? + (unsigned long)max_vp_vert_height : SurfaceHeightLuma); eff_surf_height_c = eff_surf_height_l / (1 + yuv420); full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY; @@ -1354,10 +1355,10 @@ static void CalculateDCCConfiguration( } if (SourcePixelFormat == dm_420_10) { - full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); - full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); - full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); - full_swath_bytes_vert_wc_c = dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); + full_swath_bytes_horz_wc_l = (long)dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); + full_swath_bytes_horz_wc_c = (long)dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); + full_swath_bytes_vert_wc_l = (long)dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); + full_swath_bytes_vert_wc_c = (long)dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); } if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) { @@ -1537,14 +1538,14 @@ static double CalculatePrefetchSourceLines( if (!mode_lib->vba.IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; else MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)dml_max(1U, MaxPartialSwath); } else { @@ -1552,7 +1553,7 @@ static double CalculatePrefetchSourceLines( dml_print( "WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)dml_ceil(*VInitPreFill / SwathHeight, 1); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; @@ -1617,9 +1618,9 @@ static unsigned int CalculateVMAndRowBytes( if (HostVMMinPageSize < 2048) { HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); } else { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } } @@ -1627,19 +1628,19 @@ static unsigned int CalculateVMAndRowBytes( *MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection != dm_vert) { *meta_row_height = *MetaRequestHeight; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) - + *MetaRequestWidth; - *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + + *MetaRequestWidth); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0); } else { *meta_row_height = *MetaRequestWidth; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) - + *MetaRequestHeight; - *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + + *MetaRequestHeight); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0); } - DCCMetaSurfaceBytes = DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) - + 64 * BlockHeight256Bytes) * BytePerPixel / 256; + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + + 64 * BlockHeight256Bytes) * BytePerPixel / 256); if (GPUVMEnable == true) { - *MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64; + *MetaPTEBytesFrame = (unsigned int)((dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64); MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1); } else { *MetaPTEBytesFrame = 0; @@ -1663,9 +1664,9 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) { if (ScanDirection != dm_vert) { - *DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1); + *DPDE0BytesFrame = (unsigned int)(64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1)); } else { - *DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1); + *DPDE0BytesFrame = (unsigned int)(64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1)); } ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2); } else { @@ -1683,7 +1684,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeightPTEs = 1; *PixelPTEReqHeight = 1; - *PixelPTEReqWidth = 32768.0 / BytePerPixel; + *PixelPTEReqWidth = (unsigned int)(32768.0 / BytePerPixel); *PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) { @@ -1704,16 +1705,16 @@ static unsigned int CalculateVMAndRowBytes( if (PTEBufferSizeInRequests == 0) *dpte_row_height = 1; else - *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); - *dpte_row_width_ub = (dml_ceil(((double) SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_height = (unsigned int)dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); + *dpte_row_width_ub = (unsigned int)((dml_ceil(((double) SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else if (ScanDirection != dm_vert) { *dpte_row_height = *PixelPTEReqHeight; - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (unsigned int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else { - *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight; + *dpte_row_height = (unsigned int)dml_min(*PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_width_ub = (unsigned int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; } if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop) @@ -1793,9 +1794,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } @@ -2002,7 +2003,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DPPCLK, v->ReadBandwidthPlaneLuma, v->ReadBandwidthPlaneChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->DCFCLKDeepSleep); // DSCCLK @@ -2038,7 +2039,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) { v->DSCDelay[k] = dscceComputeDelay(v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) @@ -2046,21 +2047,21 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) { v->DSCDelay[k] = 2 * dscceComputeDelay(v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 2.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 2.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); } else { v->DSCDelay[k] = 4 * dscceComputeDelay(v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 4.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 4.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); } - v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; + v->DSCDelay[k] = (unsigned int)(v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]); } else { v->DSCDelay[k] = 0; } @@ -2102,13 +2103,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], v->DCCMetaPitchC[k], @@ -2159,13 +2160,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -2232,13 +2233,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } - ReorderBytes = v->NumberOfChannels * dml_max3( + ReorderBytes = (long)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); v->UrgentExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (long)v->RoundTripPingLatencyCycles, ReorderBytes, v->DCFCLK, v->TotalActiveDPP, @@ -2266,9 +2267,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (long)v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationHeight[k], + (long)v->WritebackSourceHeight[k], v->HTotal[k]) / v->DISPCLK; } else v->WritebackDelay[v->VoltageLevel][k] = 0; @@ -2281,9 +2282,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[j], v->WritebackVRatio[j], v->WritebackVTaps[j], - v->WritebackDestinationWidth[j], - v->WritebackDestinationHeight[j], - v->WritebackSourceHeight[j], + (long)v->WritebackDestinationWidth[j], + (long)v->WritebackDestinationHeight[j], + (long)v->WritebackSourceHeight[j], v->HTotal[k]) / v->DISPCLK); } } @@ -2296,12 +2297,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j]; for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->MaxVStartupLines[k] = v->VTotal[k] - v->VActive[k] - dml_max(1.0, dml_ceil((double) v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1)); + v->MaxVStartupLines[k] = (unsigned int)(v->VTotal[k] - v->VActive[k] - dml_max(1.0, dml_ceil((double) v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1))); } v->MaximumMaxVStartupLines = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) - v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); + v->MaximumMaxVStartupLines = (unsigned int)dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); if (v->DRAMClockChangeLatencyOverride > 0.0) { v->FinalDRAMClockChangeLatency = v->DRAMClockChangeLatencyOverride; @@ -2354,21 +2355,21 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman &myPipe, v->DSCDelay[k], (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), - dml_min(v->VStartupLines, v->MaxVStartupLines[k]), + (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]), v->MaxVStartupLines[k], v->UrgentLatency, v->UrgentExtraLatency, v->TCalc, - v->PDEAndMetaPTEBytesFrame[k], - v->MetaRowByte[k], - v->PixelPTEBytesPerRow[k], + (unsigned int)v->PDEAndMetaPTEBytesFrame[k], + (unsigned int)v->MetaRowByte[k], + (unsigned int)v->PixelPTEBytesPerRow[k], v->PrefetchSourceLinesY[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->BytePerPixelY[k], v->VInitPreFillY[k], v->MaxNumSwathY[k], v->PrefetchSourceLinesC[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->VInitPreFillC[k], v->MaxNumSwathC[k], v->swath_width_luma_ub[k], @@ -2389,17 +2390,17 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK); v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[k]; v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[k]; - v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[k] / 4.0, 1); - v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); + v->VUpdateOffsetPix[k] = (unsigned int)dml_ceil(v->HTotal[k] / 4.0, 1); + v->VStartup[k] = (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]); } else { int x = v->BlendingAndTiming[k]; double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK); v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[x]; v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[x]; - v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[x] / 4.0, 1); + v->VUpdateOffsetPix[k] = (unsigned int)dml_ceil(v->HTotal[x] / 4.0, 1); if (!v->MaxVStartupLines[x]) v->MaxVStartupLines[x] = v->MaxVStartupLines[k]; - v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[x]); + v->VStartup[k] = (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[x]); } } @@ -2524,7 +2525,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->TotImmediateFlipBytes = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]); + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k])); } for (k = 0; k < v->NumberOfActivePlanes; ++k) { CalculateFlipSchedule( @@ -2887,18 +2888,18 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) // Display Pipe Configuration double BytePerPixDETY[DC__NUM_DPP__MAX] = { 0 }; double BytePerPixDETC[DC__NUM_DPP__MAX] = { 0 }; - int BytePerPixY[DC__NUM_DPP__MAX] = { 0 }; - int BytePerPixC[DC__NUM_DPP__MAX] = { 0 }; - int Read256BytesBlockHeightY[DC__NUM_DPP__MAX] = { 0 }; - int Read256BytesBlockHeightC[DC__NUM_DPP__MAX] = { 0 }; - int Read256BytesBlockWidthY[DC__NUM_DPP__MAX] = { 0 }; - int Read256BytesBlockWidthC[DC__NUM_DPP__MAX] = { 0 }; + unsigned int BytePerPixY[DC__NUM_DPP__MAX] = { 0 }; + unsigned int BytePerPixC[DC__NUM_DPP__MAX] = { 0 }; + unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX] = { 0 }; + unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX] = { 0 }; + unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX] = { 0 }; + unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX] = { 0 }; double dummy1[DC__NUM_DPP__MAX] = { 0 }; double dummy2[DC__NUM_DPP__MAX] = { 0 }; double dummy3[DC__NUM_DPP__MAX] = { 0 }; double dummy4[DC__NUM_DPP__MAX] = { 0 }; - int dummy5[DC__NUM_DPP__MAX] = { 0 }; - int dummy6[DC__NUM_DPP__MAX] = { 0 }; + unsigned int dummy5[DC__NUM_DPP__MAX] = { 0 }; + unsigned int dummy6[DC__NUM_DPP__MAX] = { 0 }; bool dummy7[DC__NUM_DPP__MAX] = { 0 }; bool dummysinglestring = 0; unsigned int k; @@ -3380,9 +3381,9 @@ static double TruncToValidBPP( void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) { struct vba_vars_st *v = &mode_lib->vba; - int MinPrefetchMode, MaxPrefetchMode; - int i, start_state; - unsigned int j, k, m; + unsigned int MinPrefetchMode, MaxPrefetchMode; + int idx, start_state; + unsigned int i, j, k, m; bool EnoughWritebackUnits = true; bool WritebackModeSupport = true; bool ViewportExceedsSurface = false; @@ -3590,9 +3591,9 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { @@ -3631,15 +3632,15 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l int MaximumSwathWidthSupportChroma = 0; if (v->SurfaceTiling[k] == dm_sw_linear) { - MaximumSwathWidthSupportLuma = 8192.0; + MaximumSwathWidthSupportLuma = (int)8192.0; } else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) { - MaximumSwathWidthSupportLuma = 2880.0; + MaximumSwathWidthSupportLuma = (int)2880.0; } else { - MaximumSwathWidthSupportLuma = 5760.0; + MaximumSwathWidthSupportLuma = (int)5760.0; } if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) { - MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma / 2.0; + MaximumSwathWidthSupportChroma = (int)(MaximumSwathWidthSupportLuma / 2.0); } else { MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma; } @@ -3837,7 +3838,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->DISPCLK_DPPCLK_Support[i][j] = false; } } - v->TotalNumberOfActiveDPP[i][j] = 0.0; + v->TotalNumberOfActiveDPP[i][j] = (unsigned int)0.0; for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k]; } @@ -3875,7 +3876,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (k = 0; k < v->NumberOfActivePlanes; ++k) { if (v->BlendingAndTiming[k] == k) { if (v->PixelClockBackEnd[k] > 3200) { - v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); + v->NumberOfDSCSlices[k] = (unsigned int)dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); } else if (v->PixelClockBackEnd[k] > 1360) { v->NumberOfDSCSlices[k] = 8; } else if (v->PixelClockBackEnd[k] > 680) { @@ -3932,7 +3933,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->PHYCLKPerState[i] >= 270.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 2700, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -3952,7 +3953,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 5400, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -3972,7 +3973,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 8100, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -3994,7 +3995,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 8100, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4073,7 +4074,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->DSCDelayPerState[i][k] = dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -4082,7 +4083,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 2, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -4091,7 +4092,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * (dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 4, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); @@ -4163,8 +4164,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (k = 0; k < v->NumberOfActivePlanes; ++k) { v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k]; v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k]; - v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k]; - v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k]; + v->SwathWidthYAllStates[i][j][k] = (unsigned int)v->SwathWidthYThisState[k]; + v->SwathWidthCAllStates[i][j][k] = (unsigned int)v->SwathWidthCThisState[k]; v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k]; v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k]; v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k]; @@ -4186,8 +4187,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; } v->TotalNumberOfDCCActiveDPP[i][j] = 0; @@ -4218,16 +4219,16 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], - 0.0, + (unsigned int)0, &v->MacroTileWidthC[k], &v->MetaRowBytesC, &v->DPTEBytesPerRowC, @@ -4260,8 +4261,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma; v->PTEBufferSizeInRequestsForChroma = 0; v->PDEAndMetaPTEBytesPerFrameC = 0.0; - v->MetaRowBytesC = 0.0; - v->DPTEBytesPerRowC = 0.0; + v->MetaRowBytesC = (unsigned int)0; + v->DPTEBytesPerRowC = (unsigned int)0; v->PrefetchLinesC[i][j][k] = 0.0; v->PTEBufferSizeNotExceededC[i][j][k] = true; } @@ -4274,13 +4275,13 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -4408,7 +4409,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->RequiredDPPCLKThisState, v->ReadBandwidthLuma, v->ReadBandwidthChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->ProjectedDCFCLKDeepSleep[i][j]); } } @@ -4426,9 +4427,9 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (long)v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationHeight[k], + (long)v->WritebackSourceHeight[k], v->HTotal[k]) / v->RequiredDISPCLK[i][j]; } else { v->WritebackDelayTime[k] = 0.0; @@ -4443,9 +4444,9 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHRatio[m], v->WritebackVRatio[m], v->WritebackVTaps[m], - v->WritebackDestinationWidth[m], - v->WritebackDestinationHeight[m], - v->WritebackSourceHeight[m], + (long)v->WritebackDestinationWidth[m], + (long)v->WritebackDestinationHeight[m], + (long)v->WritebackSourceHeight[m], v->HTotal[m]) / v->RequiredDISPCLK[i][j]); } } @@ -4467,11 +4468,11 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - ReorderingBytes = v->NumberOfChannels + ReorderingBytes = (long)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); v->FinalDRAMClockChangeLatency = (v->DRAMClockChangeLatencyOverride > 0 ? v->DRAMClockChangeLatencyOverride : v->DRAMClockChangeLatency); for (i = start_state; i < mode_lib->soc.num_states; ++i) { @@ -4549,7 +4550,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (i = start_state; i < mode_lib->soc.num_states; ++i) { for (j = 0; j <= 1; ++j) { - int NextPrefetchModeState = MinPrefetchMode; + unsigned int NextPrefetchModeState = MinPrefetchMode; v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j]; @@ -4567,13 +4568,13 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; v->ODMCombineEnabled[k] = v->ODMCombineEnablePerState[i][k]; } v->ExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (long)v->RoundTripPingLatencyCycles, ReorderingBytes, v->DCFCLKState[i][j], v->TotalNumberOfActiveDPP[i][j], @@ -4623,23 +4624,23 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib, k, &myPipe, - v->DSCDelayPerState[i][k], - v->SwathWidthYThisState[k] / v->HRatio[k], - dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), - v->MaximumVStartup[i][j][k], + (unsigned int)v->DSCDelayPerState[i][k], + (unsigned int)(v->SwathWidthYThisState[k] / v->HRatio[k]), + (unsigned int)dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), + (unsigned int)v->MaximumVStartup[i][j][k], v->UrgLatency[i], v->ExtraLatency, v->TimeCalc, - v->PDEAndMetaPTEBytesPerFrame[i][j][k], - v->MetaRowBytes[i][j][k], - v->DPTEBytesPerRow[i][j][k], + (unsigned int)v->PDEAndMetaPTEBytesPerFrame[i][j][k], + (unsigned int)v->MetaRowBytes[i][j][k], + (unsigned int)v->DPTEBytesPerRow[i][j][k], v->PrefetchLinesY[i][j][k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->BytePerPixelY[k], v->PrefillY[k], v->MaxNumSwY[k], v->PrefetchLinesC[i][j][k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->PrefillC[k], v->MaxNumSwC[k], v->swath_width_luma_ub_this_state[k], @@ -4751,10 +4752,10 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * v->UrgentBurstFactorChromaPre[k]) + v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]); } - v->TotImmediateFlipBytes = 0.0; + v->TotImmediateFlipBytes = (unsigned int)0; for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] - + v->MetaRowBytes[i][j][k] + v->DPTEBytesPerRow[i][j][k]); + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + + v->MetaRowBytes[i][j][k] + v->DPTEBytesPerRow[i][j][k])); } for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { @@ -4913,33 +4914,39 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = v->soc.num_states - 1; i >= start_state; i--) { + for (idx = v->soc.num_states - 1; idx >= start_state; idx--) { for (j = 0; j < 2; j++) { - if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1 - && v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1 - && v->NotEnoughDSCUnits[i] == 0 - && v->DTBCLKRequiredMoreThanSupported[i] == 0 - && v->ROBSupport[i][j] == 1 && v->DISPCLK_DPPCLK_Support[i][j] == 1 && v->TotalAvailablePipesSupport[i][j] == 1 + if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 + && v->ViewportSizeSupport[idx][j] == 1 + && v->DIOSupport[idx] == 1 && v->ODMCombine4To1SupportCheckOK[idx] == 1 + && v->NotEnoughDSCUnits[idx] == 0 + && v->DTBCLKRequiredMoreThanSupported[idx] == 0 + && v->ROBSupport[idx][j] == 1 && v->DISPCLK_DPPCLK_Support[idx][j] == 1 + && v->TotalAvailablePipesSupport[idx][j] == 1 && EnoughWritebackUnits == 1 && WritebackModeSupport == 1 - && v->WritebackLatencySupport == 1 && v->WritebackScaleRatioAndTapsSupport == 1 && v->CursorSupport == 1 && v->PitchSupport == 1 - && ViewportExceedsSurface == 0 && v->PrefetchSupported[i][j] == 1 && v->DynamicMetadataSupported[i][j] == 1 - && v->TotalVerticalActiveBandwidthSupport[i][j] == 1 && v->VRatioInPrefetchSupported[i][j] == 1 - && v->PTEBufferSizeNotExceeded[i][j] == 1 && v->NonsupportedDSCInputBPC == 0 + && v->WritebackLatencySupport == 1 && v->WritebackScaleRatioAndTapsSupport == 1 + && v->CursorSupport == 1 && v->PitchSupport == 1 + && ViewportExceedsSurface == 0 && v->PrefetchSupported[idx][j] == 1 + && v->DynamicMetadataSupported[idx][j] == 1 + && v->TotalVerticalActiveBandwidthSupport[idx][j] == 1 + && v->VRatioInPrefetchSupported[idx][j] == 1 + && v->PTEBufferSizeNotExceeded[idx][j] == 1 && v->NonsupportedDSCInputBPC == 0 && ((v->HostVMEnable == 0 && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) - || v->ImmediateFlipSupportedForState[i][j] == true)) { - v->ModeSupport[i][j] = true; + || v->ImmediateFlipSupportedForState[idx][j] == true)) { + v->ModeSupport[idx][j] = true; } else { - v->ModeSupport[i][j] = false; + v->ModeSupport[idx][j] = false; } } } { unsigned int MaximumMPCCombine = 0; - for (i = v->soc.num_states; i >= start_state; i--) { - if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) { - v->VoltageLevel = i; - v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true; - if (v->ModeSupport[i][1] == true) { + for (idx = v->soc.num_states; idx >= start_state; idx--) { + if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true + || v->ModeSupport[idx][1] == true) { + v->VoltageLevel = idx; + v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true; + if (v->ModeSupport[idx][1] == true) { MaximumMPCCombine = 1; } else { MaximumMPCCombine = 0; @@ -5038,20 +5045,20 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->LBLatencyHidingSourceLinesY = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); + v->LBLatencyHidingSourceLinesY = (unsigned int)(dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1)); - v->LBLatencyHidingSourceLinesC = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); + v->LBLatencyHidingSourceLinesC = (unsigned int)(dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]); EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]); LinesInDETY[k] = (double) DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k]; - LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + LinesInDETYRoundedDownToSwath[k] = (unsigned int)dml_floor(LinesInDETY[k], SwathHeightY[k]); FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; if (BytePerPixelDETC[k] > 0) { LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; - LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); + LinesInDETCRoundedDownToSwath = (unsigned int)dml_floor(LinesInDETC, SwathHeightC[k]); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k]; } else { LinesInDETC = 0; @@ -5146,8 +5153,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -5299,7 +5306,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][2], @@ -5380,7 +5387,7 @@ static void CalculatePixelDeliveryTimes( for (k = 0; k < NumberOfActivePlanes; ++k) { int cursor_req_per_width = 0; - cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); + cursor_req_per_width = (int)dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); if (NumberOfCursors[k] > 0) { if (VRatio[k] <= 1) { CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width; @@ -5400,39 +5407,39 @@ static void CalculatePixelDeliveryTimes( } static void CalculateMetaAndPTETimes( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -5509,7 +5516,7 @@ static void CalculateMetaAndPTETimes( } else { meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; - meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma; + meta_chunk_per_row_int_chroma = (unsigned int)((double) meta_row_width_chroma[k] / meta_chunk_width_chroma); meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma; if (SourceScan[k] != dm_vert) { meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k]; @@ -5542,7 +5549,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k]; } - dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; @@ -5556,7 +5563,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k]; } - dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; @@ -5577,18 +5584,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -5604,32 +5611,32 @@ static void CalculateVMGroupAndRequestTimes( if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { if (DCCEnable[k] == false) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) - / (double) (vm_group_bytes[k]), 1); + / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) + num_group_per_lower_vm_stage = (int)dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (GPUVMMaxPageTableLevels == 1) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) - / (double) (vm_group_bytes[k]), 1); + / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) + num_group_per_lower_vm_stage = (int)dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + num_group_per_lower_vm_stage = (int)(2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + (int)dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)); } } } @@ -5686,34 +5693,34 @@ static void CalculateVMGroupAndRequestTimes( } static void CalculateStutterEfficiency( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, long ROBBufferSizeInKByte, double TotalDataReadBandwidth, double DCFCLK, double ReturnBW, double SRExitTime, bool SynchronizedVBlank, - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double DCCRateLuma[], double DCCRateChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -5840,49 +5847,49 @@ static void CalculateStutterEfficiency( static void CalculateSwathAndDETConfiguration( bool ForceSingleDPP, - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, unsigned int DETBufferSizeInKByte, double MaximumSwathWidthLuma[], double MaximumSwathWidthChroma[], enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], bool *ViewportSizeSupport) { (void)HRatioChroma; - int MaximumSwathHeightY[DC__NUM_DPP__MAX] = { 0 }; - int MaximumSwathHeightC[DC__NUM_DPP__MAX] = { 0 }; - int MinimumSwathHeightY = 0; - int MinimumSwathHeightC = 0; + unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX] = { 0 }; + unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX] = { 0 }; + unsigned int MinimumSwathHeightY = 0; + unsigned int MinimumSwathHeightC = 0; long RoundedUpMaxSwathSizeBytesY = 0; long RoundedUpMaxSwathSizeBytesC = 0; long RoundedUpMinSwathSizeBytesY = 0; @@ -5891,7 +5898,7 @@ static void CalculateSwathAndDETConfiguration( long RoundedUpSwathSizeBytesC = 0; double SwathWidthSingleDPP[DC__NUM_DPP__MAX] = { 0 }; double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX] = { 0 }; - int k; + unsigned int k; CalculateSwathWidth( ForceSingleDPP, @@ -5962,39 +5969,39 @@ static void CalculateSwathAndDETConfiguration( } } - RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] - * MaximumSwathHeightY[k]; - RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] - * MinimumSwathHeightY; + RoundedUpMaxSwathSizeBytesY = (long)(swath_width_luma_ub[k] * BytePerPixDETY[k] + * MaximumSwathHeightY[k]); + RoundedUpMinSwathSizeBytesY = (long)(swath_width_luma_ub[k] * BytePerPixDETY[k] + * MinimumSwathHeightY); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesY = dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); - RoundedUpMinSwathSizeBytesY = dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); + RoundedUpMaxSwathSizeBytesY = (long)dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); + RoundedUpMinSwathSizeBytesY = (long)dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); } - RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] - * MaximumSwathHeightC[k]; - RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] - * MinimumSwathHeightC; + RoundedUpMaxSwathSizeBytesC = (long)(swath_width_chroma_ub[k] * BytePerPixDETC[k] + * MaximumSwathHeightC[k]); + RoundedUpMinSwathSizeBytesC = (long)(swath_width_chroma_ub[k] * BytePerPixDETC[k] + * MinimumSwathHeightC); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesC = dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); - RoundedUpMinSwathSizeBytesC = dml_ceil(RoundedUpMinSwathSizeBytesC, 256); + RoundedUpMaxSwathSizeBytesC = (long)dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); + RoundedUpMinSwathSizeBytesC = (long)dml_ceil(RoundedUpMinSwathSizeBytesC, 256); } if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC - <= DETBufferSizeInKByte * 1024 / 2) { + <= (long)DETBufferSizeInKByte * 1024 / 2) { SwathHeightY[k] = MaximumSwathHeightY[k]; SwathHeightC[k] = MaximumSwathHeightC[k]; RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY; RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC; } else if (RoundedUpMaxSwathSizeBytesY >= 1.5 * RoundedUpMaxSwathSizeBytesC && RoundedUpMinSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC - <= DETBufferSizeInKByte * 1024 / 2) { + <= (long)DETBufferSizeInKByte * 1024 / 2) { SwathHeightY[k] = MinimumSwathHeightY; SwathHeightC[k] = MaximumSwathHeightC[k]; RoundedUpSwathSizeBytesY = RoundedUpMinSwathSizeBytesY; RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC; } else if (RoundedUpMaxSwathSizeBytesY < 1.5 * RoundedUpMaxSwathSizeBytesC && RoundedUpMaxSwathSizeBytesY + RoundedUpMinSwathSizeBytesC - <= DETBufferSizeInKByte * 1024 / 2) { + <= (long)DETBufferSizeInKByte * 1024 / 2) { SwathHeightY[k] = MaximumSwathHeightY[k]; SwathHeightC[k] = MinimumSwathHeightC; RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY; @@ -6018,7 +6025,7 @@ static void CalculateSwathAndDETConfiguration( } if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC - > DETBufferSizeInKByte * 1024 / 2 + > (long)DETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k] || (SwathHeightC[k] > 0 && SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) { @@ -6032,7 +6039,7 @@ static void CalculateSwathAndDETConfiguration( static void CalculateSwathWidth( bool ForceSingleDPP, - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], unsigned int ViewportWidth[], @@ -6042,22 +6049,22 @@ static void CalculateSwathWidth( unsigned int SurfaceHeightY[], unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[]) { @@ -6107,17 +6114,17 @@ static void CalculateSwathWidth( SwathWidthC[k] = SwathWidthSingleDPPC[k]; } - surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); - surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); + surface_width_ub_l = (long)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); + surface_height_ub_l = (long)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); if (SourceScan[k] != dm_vert) { MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k]; MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k]; - swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (long) dml_ceil(SwathWidthY[k] - 1, + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_width_ub_l, (long) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); if (BytePerPixC[k] > 0) { - surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); - swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, (long) dml_ceil(SwathWidthC[k] - 1, + surface_width_ub_c = (long)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_width_ub_c, (long) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]); } else { swath_width_chroma_ub[k] = 0; @@ -6125,11 +6132,11 @@ static void CalculateSwathWidth( } else { MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k]; MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k]; - swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (long) dml_ceil(SwathWidthY[k] - 1, + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_height_ub_l, (long) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); if (BytePerPixC[k] > 0) { - surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); - swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, (long) dml_ceil(SwathWidthC[k] - 1, + surface_height_ub_c = (long)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_height_ub_c, (long) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]); } else { swath_width_chroma_ub[k] = 0; @@ -6150,8 +6157,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, double HostVMMinPageSize, @@ -6185,9 +6192,9 @@ static double CalculateExtraLatencyBytes( int MetaChunkSize, bool GPUVMEnable, bool HostVMEnable, - int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfActivePlanes, + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, double HostVMMinPageSize, @@ -6203,9 +6210,9 @@ static double CalculateExtraLatencyBytes( if (HostVMMinPageSize < 2048) { HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); } else { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } } else { HostVMInefficiencyFactor = 1; @@ -6244,7 +6251,7 @@ static double CalculateUrgentLatency( static noinline_for_stack void UseMinimumDCFCLK( struct display_mode_lib *mode_lib, struct vba_vars_st *v, - int MaxPrefetchMode, + unsigned int MaxPrefetchMode, int ReorderingBytes) { double NormalEfficiency = 0; @@ -6269,7 +6276,7 @@ static noinline_for_stack void UseMinimumDCFCLK( double ExtraLatencyBytes = 0; double ExtraLatencyCycles = 0; double DCFCLKRequiredForPeakBandwidth = 0; - int NoOfDPPState[DC__NUM_DPP__MAX] = { 0 }; + unsigned int NoOfDPPState[DC__NUM_DPP__MAX] = { 0 }; double MinimumTvmPlus2Tr0 = 0; TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c index 472ac5ee165f..a373df0aebf1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c @@ -120,13 +120,13 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), + 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), - 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), + 1) - 3); } rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); @@ -146,11 +146,11 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, if (rq_param->yuv420) { if ((double)rq_param->misc.rq_l.stored_swath_bytes / (double)rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma } else { - detile_buf_plane1_addr = dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), 256, - 0) / 64.0; // 2/3 to chroma + 0) / 64.0); // 2/3 to chroma } } rq_regs->plane1_base_address = detile_buf_plane1_addr; @@ -177,10 +177,10 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib, full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; if (rq_param->yuv420_10bpc) { - full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, + full_swath_bytes_packed_l = (unsigned int)dml_round_to_multiple((unsigned int)(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256; - full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, + full_swath_bytes_packed_c = (unsigned int)dml_round_to_multiple((unsigned int)(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256; } @@ -400,8 +400,8 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height - + dml_ceil((double)(log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + + dml_ceil((double)(log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -573,7 +573,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, if (surf_linear) { unsigned int dpte_row_height = 0; - log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); + log2_dpte_row_height_linear = (unsigned int)dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma); dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs); @@ -645,7 +645,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double)dpte_row_width_ub / dpte_group_width, + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil((double)dpte_row_width_ub / dpte_group_width, 1); } @@ -670,7 +670,7 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib, vp_height = pipe_param->src.viewport_height_c; data_pitch = pipe_param->src.data_pitch_c; meta_pitch = pipe_param->src.meta_pitch_c; - surface_height = pipe_param->src.surface_height_y / 2.0; + surface_height = (unsigned int)(pipe_param->src.surface_height_y / 2.0); } else { vp_width = pipe_param->src.viewport_width / ppe; vp_height = pipe_param->src.viewport_height; @@ -687,18 +687,18 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib, access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine*2); if (is_chroma) { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm); } else { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm); } if (access_dir == 0) { - vp_width = dml_min(full_src_vp_width, src_hactive_odm); + vp_width = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); } else { - vp_height = dml_min(full_src_vp_width, src_hactive_odm); + vp_height = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); } dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width); @@ -833,7 +833,7 @@ static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, cur_req_size = 256; } - cur_req_width = (double)cur_req_size / ((double)cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double)cur_req_size / ((double)cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double)cur_src_width / (double)cur_req_width, 1) * (double)cur_req_width; cur_req_per_width = cur_width_ub / (double)cur_req_width; @@ -1123,11 +1123,11 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, if (dout->dsc_enable) { double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dispclk_delay_subtotal += dsc_delay; + dispclk_delay_subtotal += (unsigned int)dsc_delay; } - pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz - + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; + pixel_rate_delay_subtotal = (unsigned int)(dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz) + + (unsigned int)(dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz); vstartup_start = dst->vstartup_start; if (interlaced) { @@ -1167,8 +1167,8 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, min_vblank); } - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + dst_y_after_scaler = (int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); if (dst_y_after_scaler < 0) dst_y_after_scaler = 0; @@ -1552,7 +1552,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8); - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2)); @@ -1601,23 +1601,23 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; } - disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; - disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; - disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); - disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // Clamp to max for now if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)((double)dpte_row_height_l / (double)vratio_l * dml_pow(2, 2)); @@ -1646,12 +1646,12 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq / (double)dpte_groups_per_row_ub_l); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)((double)meta_row_height_l / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq / (double)meta_chunks_per_row_ub_l); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { disp_dlg_regs->refcyc_per_pte_group_nom_c = @@ -1659,7 +1659,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, * (double)htotal * ref_freq_to_pix_freq / (double)dpte_groups_per_row_ub_c); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); // TODO: Is this the right calculation? Does htotal need to be halved? disp_dlg_regs->refcyc_per_meta_chunk_nom_c = @@ -1667,7 +1667,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, * (double)htotal * ref_freq_to_pix_freq / (double)meta_chunks_per_row_ub_c); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int)dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int)dml_floor(refcyc_per_line_delivery_pre_l, @@ -1721,7 +1721,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1755,7 +1755,7 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c index 1aaa77265eed..c4b73acd7140 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c @@ -298,7 +298,7 @@ static void calculate_wm_set_for_vlevel(int vlevel, { double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; - ASSERT(vlevel < dml->soc.num_states); + ASSERT(vlevel < (int)dml->soc.num_states); /* only pipe 0 is read for voltage and dcf/soc clocks */ pipes[0].clks_cfg.voltage = vlevel; pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; @@ -308,14 +308,14 @@ static void calculate_wm_set_for_vlevel(int vlevel, dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; - wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; - wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; - wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; - wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; - wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; - wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; + wm_set->urgent_ns = (uint32_t)(get_wm_urgent(dml, pipes, pipe_cnt) * 1000); + wm_set->cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000); + wm_set->cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000); + wm_set->cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000); + wm_set->pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000); + wm_set->frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000); + wm_set->frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000); + wm_set->urgent_latency_ns = (uint32_t)(get_urgent_latency(dml, pipes, pipe_cnt) * 1000); dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; } @@ -326,7 +326,8 @@ void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool); struct clk_limit_table *clk_table = &bw_params->clk_table; unsigned int i, closest_clk_lvl; - int j = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0; + int j = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; dc_assert_fp_enabled(); @@ -405,8 +406,8 @@ void dcn301_fpu_set_wm_ranges(int i, { dc_assert_fp_enabled(); - ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; - ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; + ranges->reader_wm_sets[i].min_fill_clk_mhz = (uint16_t)((i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0); + ranges->reader_wm_sets[i].max_fill_clk_mhz = (uint16_t)(loaded_bb->clock_limits[i].dram_speed_mts / 16); } void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info) @@ -429,7 +430,7 @@ void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc, int pipe_cnt, int vlevel_req) { - int i, pipe_idx; + unsigned int i, pipe_idx; int vlevel, vlevel_max; struct wm_range_table_entry *table_entry; struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c index 8d7c59ec701d..90a7b29ebe74 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c @@ -182,14 +182,14 @@ static void dcn302_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; if (optimal_fclk) - *optimal_fclk = bw_from_dram / + *optimal_fclk = (unsigned int)(bw_from_dram / (dcn3_02_soc.fabric_datapath_to_dcn_data_return_bytes * - (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); + (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100))); if (optimal_dcfclk) - *optimal_dcfclk = bw_from_dram / + *optimal_dcfclk = (unsigned int)(bw_from_dram / (dcn3_02_soc.return_bus_width_bytes * - (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100)); + (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100))); } void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) @@ -218,7 +218,7 @@ void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; if (bw_params->clk_table.entries[0].memclk_mhz) { - int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; + unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; for (i = 0; i < MAX_NUM_DPM_LVL; i++) { if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) @@ -231,13 +231,13 @@ void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; } if (!max_dcfclk_mhz) - max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; + max_dcfclk_mhz = (int)dcn3_02_soc.clock_limits[0].dcfclk_mhz; if (!max_dispclk_mhz) - max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz; + max_dispclk_mhz = (int)dcn3_02_soc.clock_limits[0].dispclk_mhz; if (!max_dppclk_mhz) - max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; + max_dppclk_mhz = (int)dcn3_02_soc.clock_limits[0].dppclk_mhz; if (!max_phyclk_mhz) - max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; + max_phyclk_mhz = (int)dcn3_02_soc.clock_limits[0].phyclk_mhz; if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { /* If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array */ diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c index b5d3fd4c3694..e42419c7868d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c @@ -178,13 +178,13 @@ static void dcn303_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; if (optimal_fclk) - *optimal_fclk = bw_from_dram / + *optimal_fclk = (unsigned int)(bw_from_dram / (dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes * - (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); + (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100))); if (optimal_dcfclk) - *optimal_dcfclk = bw_from_dram / - (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_dcfclk = (unsigned int)(bw_from_dram / + (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100))); } @@ -214,7 +214,7 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; if (bw_params->clk_table.entries[0].memclk_mhz) { - int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; + unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; for (i = 0; i < MAX_NUM_DPM_LVL; i++) { if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) @@ -227,13 +227,13 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; } if (!max_dcfclk_mhz) - max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; + max_dcfclk_mhz = (int)dcn3_03_soc.clock_limits[0].dcfclk_mhz; if (!max_dispclk_mhz) - max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz; + max_dispclk_mhz = (int)dcn3_03_soc.clock_limits[0].dispclk_mhz; if (!max_dppclk_mhz) - max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; + max_dppclk_mhz = (int)dcn3_03_soc.clock_limits[0].dppclk_mhz; if (!max_phyclk_mhz) - max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz; + max_phyclk_mhz = (int)dcn3_03_soc.clock_limits[0].phyclk_mhz; if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c index ad23215da9f8..f9b2da6b2bb8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c @@ -485,9 +485,12 @@ void dcn31_calculate_wm_and_dlg_fp( int pipe_cnt, int vlevel) { - int i, pipe_idx, total_det = 0, active_hubp_count = 0; + int total_det = 0, active_hubp_count = 0; + unsigned int i, pipe_idx; double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; uint32_t cstate_enter_plus_exit_z8_ns; + uint32_t minimum_z8_residency_time_ns = + (uint32_t)dc->debug.minimum_z8_residency_time * 1000U; dc_assert_fp_enabled(); @@ -499,7 +502,7 @@ void dcn31_calculate_wm_and_dlg_fp( * Override any clocks that can block S0i3 to min here */ if (pipe_cnt == 0) { - context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 + context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)dcfclk; // always should be vlevel 0 return; } @@ -508,11 +511,11 @@ void dcn31_calculate_wm_and_dlg_fp( pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; cstate_enter_plus_exit_z8_ns = - get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + (uint32_t)(get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_time && - cstate_enter_plus_exit_z8_ns < dc->debug.minimum_z8_residency_time * 1000) - cstate_enter_plus_exit_z8_ns = dc->debug.minimum_z8_residency_time * 1000; + cstate_enter_plus_exit_z8_ns < minimum_z8_residency_time_ns) + cstate_enter_plus_exit_z8_ns = minimum_z8_residency_time_ns; /* Set A: * All clocks min required @@ -520,16 +523,16 @@ void dcn31_calculate_wm_and_dlg_fp( * Set A calculated last so that following calculations are based on Set A */ dc->res_pool->funcs->update_soc_for_wm_a(dc, context); - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = (uint32_t)(get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; @@ -578,7 +581,7 @@ void dcn31_calculate_wm_and_dlg_fp( continue; context->res_ctx.pipe_ctx[i].det_buffer_size_kb = - get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + (int)get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); if (context->res_ctx.pipe_ctx[i].det_buffer_size_kb > 384) context->res_ctx.pipe_ctx[i].det_buffer_size_kb /= 2; total_det += context->res_ctx.pipe_ctx[i].det_buffer_size_kb; @@ -592,7 +595,7 @@ void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; struct clk_limit_table *clk_table = &bw_params->clk_table; unsigned int i, closest_clk_lvl; - int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; int j; dc_assert_fp_enabled(); @@ -668,7 +671,7 @@ void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) { struct clk_limit_table *clk_table = &bw_params->clk_table; - int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0; dc_assert_fp_enabled(); @@ -731,7 +734,7 @@ void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; struct clk_limit_table *clk_table = &bw_params->clk_table; unsigned int i, closest_clk_lvl; - int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; int j; dc_assert_fp_enabled(); @@ -810,7 +813,7 @@ int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc) { dc_assert_fp_enabled(); - return soc->clock_limits[0].dispclk_mhz * 10000.0 / (1.0 + soc->dcn_downspread_percent / 100.0); + return (int)(soc->clock_limits[0].dispclk_mhz * 10000.0 / (1.0 + soc->dcn_downspread_percent / 100.0)); } int dcn_get_approx_det_segs_required_for_pstate( diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 9833467722b9..f9224a433220 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -157,7 +157,7 @@ static bool CalculatePrefetchSchedule( double *Tdmdl_vm, double *Tdmdl, double *TSetup, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix); static double RoundToDFSGranularityUp(double Clock, double VCOSpeed); @@ -218,19 +218,19 @@ static unsigned int CalculateVMAndRowBytes( unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, - int *dpte_row_width_ub, + unsigned int *dpte_row_width_ub, unsigned int *dpte_row_height, unsigned int *MetaRequestWidth, unsigned int *MetaRequestHeight, unsigned int *meta_row_width, unsigned int *meta_row_height, - int *vm_group_bytes, + unsigned int *vm_group_bytes, unsigned int *dpte_group_bytes, unsigned int *PixelPTEReqWidth, unsigned int *PixelPTEReqHeight, unsigned int *PTERequestSize, - int *DPDE0BytesFrame, - int *MetaPTEBytesFrame); + unsigned int *DPDE0BytesFrame, + unsigned int *MetaPTEBytesFrame); static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime); static void CalculateRowBandwidth( bool GPUVMEnable, @@ -285,7 +285,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( double *Tdmbf, double *Tdmec, double *Tdmsks, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix); @@ -318,8 +318,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -377,7 +377,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], @@ -402,35 +402,35 @@ static void CalculateMetaAndPTETimes( bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -453,18 +453,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -492,29 +492,29 @@ static void CalculateStutterEfficiency( bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -539,32 +539,32 @@ static void CalculateSwathAndDETConfiguration( enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], @@ -574,31 +574,31 @@ static void CalculateSwathWidth( int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], - int HActive[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], + unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[]); + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[]); static double CalculateExtraLatency( int RoundTripPingLatencyCycles, @@ -612,8 +612,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels); @@ -627,8 +627,8 @@ static double CalculateExtraLatencyBytes( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels); @@ -652,7 +652,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( int CompressedBufferSegmentSizeInkByteFinal, enum output_encoder_class *Output, bool *UnboundedRequestEnabled, - int *CompressedBufferSizeInkByte); + unsigned int *CompressedBufferSizeInkByte); static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output); @@ -700,7 +700,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -869,7 +869,7 @@ static bool CalculatePrefetchSchedule( double *Tdmdl_vm, double *Tdmdl, double *TSetup, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) { @@ -985,13 +985,13 @@ static bool CalculatePrefetchSchedule( *Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0); if (myPipe->ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor); - DISPCLKCycles = DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)DISPCLKDelaySubtotal; if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) return true; @@ -1510,10 +1510,10 @@ static void CalculateDCCConfiguration( double detile_buf_vp_horz_limit; double detile_buf_vp_vert_limit; - int MAS_vp_horz_limit; - int MAS_vp_vert_limit; - int max_vp_horz_width; - int max_vp_vert_height; + unsigned int MAS_vp_horz_limit; + unsigned int MAS_vp_vert_limit; + unsigned int max_vp_horz_width; + unsigned int max_vp_vert_height; int eff_surf_width_l; int eff_surf_width_c; int eff_surf_height_l; @@ -1554,11 +1554,11 @@ static void CalculateDCCConfiguration( horz_div_c = 0; if (BytePerPixelC == 0) { - swath_buf_size = DETBufferSize / 2 - 2 * 256; + swath_buf_size = (int)(DETBufferSize / 2 - 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l)); detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l)); } else { - swath_buf_size = DETBufferSize / 2 - 2 * 2 * 256; + swath_buf_size = (int)(DETBufferSize / 2 - 2 * 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l) + (double) RequestHeight256ByteChroma * BytePerPixelC / (1 + horz_div_c) / (1 + yuv420)); @@ -1576,8 +1576,8 @@ static void CalculateDCCConfiguration( MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 5760; MAS_vp_vert_limit = (BytePerPixelC > 0 ? 2880 : 5760); - max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); - max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); + max_vp_horz_width = (int)dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); + max_vp_vert_height = (int)dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); eff_surf_width_l = (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma); eff_surf_width_c = eff_surf_width_l / (1 + yuv420); eff_surf_height_l = (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma); @@ -1594,10 +1594,10 @@ static void CalculateDCCConfiguration( } if (SourcePixelFormat == dm_420_10) { - full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); - full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); - full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); - full_swath_bytes_vert_wc_c = dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); + full_swath_bytes_horz_wc_l = (int)dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); + full_swath_bytes_horz_wc_c = (int)dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); + full_swath_bytes_vert_wc_l = (int)dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); + full_swath_bytes_vert_wc_c = (int)dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); } if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) { @@ -1760,20 +1760,20 @@ static double CalculatePrefetchSourceLines( if (!v->IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; else MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)dml_max(1U, MaxPartialSwath); } else { if (ViewportYStart != 0) dml_print("WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)dml_ceil(*VInitPreFill / SwathHeight, 1); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; @@ -1818,19 +1818,19 @@ static unsigned int CalculateVMAndRowBytes( unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, - int *dpte_row_width_ub, + unsigned int *dpte_row_width_ub, unsigned int *dpte_row_height, unsigned int *MetaRequestWidth, unsigned int *MetaRequestHeight, unsigned int *meta_row_width, unsigned int *meta_row_height, - int *vm_group_bytes, + unsigned int *vm_group_bytes, unsigned int *dpte_group_bytes, unsigned int *PixelPTEReqWidth, unsigned int *PixelPTEReqHeight, unsigned int *PTERequestSize, - int *DPDE0BytesFrame, - int *MetaPTEBytesFrame) + unsigned int *DPDE0BytesFrame, + unsigned int *MetaPTEBytesFrame) { (void)SourcePixelFormat; struct vba_vars_st *v = &mode_lib->vba; @@ -1848,9 +1848,9 @@ static unsigned int CalculateVMAndRowBytes( if (HostVMMinPageSize < 2048) { HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); } else { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } } @@ -1858,16 +1858,16 @@ static unsigned int CalculateVMAndRowBytes( *MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection != dm_vert) { *meta_row_height = *MetaRequestHeight; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth; - *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0); } else { *meta_row_height = *MetaRequestWidth; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight; - *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0); } - DCCMetaSurfaceBytes = DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256; + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256); if (GPUVMEnable == true) { - *MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64; + *MetaPTEBytesFrame = (int)((dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64); MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1); } else { *MetaPTEBytesFrame = 0; @@ -1891,17 +1891,17 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) { if (ScanDirection != dm_vert) { - *DPDE0BytesFrame = 64 + *DPDE0BytesFrame = (int)(64 * (dml_ceil( ((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } else { - *DPDE0BytesFrame = 64 + *DPDE0BytesFrame = (int)(64 * (dml_ceil( ((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2); } else { @@ -1929,7 +1929,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeightPTEs = 1; *PixelPTEReqHeight = 1; - *PixelPTEReqWidth = 32768.0 / BytePerPixel; + *PixelPTEReqWidth = (unsigned int)(32768.0 / BytePerPixel); *PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) { @@ -1947,16 +1947,16 @@ static unsigned int CalculateVMAndRowBytes( } if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); - *dpte_row_width_ub = (dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_height = (unsigned int)dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); + *dpte_row_width_ub = (int)((dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else if (ScanDirection != dm_vert) { *dpte_row_height = *PixelPTEReqHeight; - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else { - *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight; + *dpte_row_height = (unsigned int)dml_min(*PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_width_ub = (int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; } @@ -2041,9 +2041,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } @@ -2229,7 +2229,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DPPCLK, v->ReadBandwidthPlaneLuma, v->ReadBandwidthPlaneChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->DCFCLKDeepSleep); // DSCCLK @@ -2266,7 +2266,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DSCDelay[k] = dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -2275,8 +2275,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman * (dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 2.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 2.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); } else { @@ -2284,12 +2284,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman * (dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 4.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 4.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); } - v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; + v->DSCDelay[k] = (unsigned int)(v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]); } else { v->DSCDelay[k] = 0; } @@ -2330,13 +2330,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], v->DCCMetaPitchC[k], @@ -2387,13 +2387,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -2459,11 +2459,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman NoChromaPlanes = false; } - ReorderBytes = v->NumberOfChannels + ReorderBytes = (int)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); VMDataOnlyReturnBW = dml_min( dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn) @@ -2489,7 +2489,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman HostVMInefficiencyFactor = v->ReturnBW / VMDataOnlyReturnBW; v->UrgentExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (int)v->RoundTripPingLatencyCycles, ReorderBytes, v->DCFCLK, v->TotalActiveDPP, @@ -2517,9 +2517,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (int)v->WritebackDestinationWidth[k], + (int)v->WritebackDestinationHeight[k], + (int)v->WritebackSourceHeight[k], v->HTotal[k]) / v->DISPCLK; } else v->WritebackDelay[v->VoltageLevel][k] = 0; @@ -2533,9 +2533,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[j], v->WritebackVRatio[j], v->WritebackVTaps[j], - v->WritebackDestinationWidth[j], - v->WritebackDestinationHeight[j], - v->WritebackSourceHeight[j], + (int)v->WritebackDestinationWidth[j], + (int)v->WritebackDestinationHeight[j], + (int)v->WritebackSourceHeight[j], v->HTotal[k]) / v->DISPCLK); } } @@ -2548,7 +2548,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j]; for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->MaxVStartupLines[k] = + v->MaxVStartupLines[k] = (unsigned int)( (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ? dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) : v->VTotal[k] - v->VActive[k] @@ -2557,7 +2557,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman dml_ceil( (double) v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), - 1)); + 1))); if (v->MaxVStartupLines[k] > 1023) v->MaxVStartupLines[k] = 1023; @@ -2570,7 +2570,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->MaximumMaxVStartupLines = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) - v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); + v->MaximumMaxVStartupLines = (unsigned int)dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); // VBA_DELTA // We don't really care to iterate between the various prefetch modes @@ -2639,7 +2639,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), v->OutputFormat[k], v->MaxInterDCNTileRepeaters, - dml_min(v->VStartupLines, v->MaxVStartupLines[k]), + (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]), v->MaxVStartupLines[k], v->GPUVMMaxPageTableLevels, v->GPUVMEnable, @@ -2653,15 +2653,15 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->UrgentLatency, v->UrgentExtraLatency, v->TCalc, - v->PDEAndMetaPTEBytesFrame[k], - v->MetaRowByte[k], - v->PixelPTEBytesPerRow[k], + (unsigned int)v->PDEAndMetaPTEBytesFrame[k], + (unsigned int)v->MetaRowByte[k], + (unsigned int)v->PixelPTEBytesPerRow[k], v->PrefetchSourceLinesY[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->VInitPreFillY[k], v->MaxNumSwathY[k], v->PrefetchSourceLinesC[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->VInitPreFillC[k], v->MaxNumSwathC[k], v->swath_width_luma_ub[k], @@ -2692,7 +2692,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]); #endif - v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); + v->VStartup[k] = (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]); } v->NoEnoughUrgentLatencyHiding = false; @@ -2846,8 +2846,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->TotImmediateFlipBytes = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes - + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]); + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k])); } for (k = 0; k < v->NumberOfActivePlanes; ++k) { CalculateFlipSchedule( @@ -3159,10 +3159,10 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP); - v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VFrontPorch[k]) / 2.0, 1.0) : v->VTotal[k]) + v->MIN_DST_Y_NEXT_START[k] = (unsigned int)(((isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VFrontPorch[k]) / 2.0, 1.0) : v->VTotal[k]) - v->VFrontPorch[k]) + dml_max(1.0, dml_ceil(v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1.0)) - + dml_floor(4.0 * v->TSetup[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0; + + dml_floor(4.0 * v->TSetup[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0); v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]); @@ -3278,18 +3278,18 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) // Display Pipe Configuration double BytePerPixDETY[DC__NUM_DPP__MAX]; double BytePerPixDETC[DC__NUM_DPP__MAX]; - int BytePerPixY[DC__NUM_DPP__MAX]; - int BytePerPixC[DC__NUM_DPP__MAX]; - int Read256BytesBlockHeightY[DC__NUM_DPP__MAX]; - int Read256BytesBlockHeightC[DC__NUM_DPP__MAX]; - int Read256BytesBlockWidthY[DC__NUM_DPP__MAX]; - int Read256BytesBlockWidthC[DC__NUM_DPP__MAX]; + unsigned int BytePerPixY[DC__NUM_DPP__MAX]; + unsigned int BytePerPixC[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX]; double dummy1[DC__NUM_DPP__MAX]; double dummy2[DC__NUM_DPP__MAX]; double dummy3[DC__NUM_DPP__MAX]; double dummy4[DC__NUM_DPP__MAX]; - int dummy5[DC__NUM_DPP__MAX]; - int dummy6[DC__NUM_DPP__MAX]; + unsigned int dummy5[DC__NUM_DPP__MAX]; + unsigned int dummy6[DC__NUM_DPP__MAX]; bool dummy7[DC__NUM_DPP__MAX]; bool dummysinglestring; @@ -3429,7 +3429,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( double *Tdmbf, double *Tdmec, double *Tdmsks, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) { @@ -3438,7 +3438,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / DPPCLK + 3 / DISPCLK); *VUpdateWidthPix = dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock, 1.0); *VReadyOffsetPix = dml_ceil(dml_max(150.0 / DPPCLK, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / DPPCLK) * PixelClock, 1.0); - *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); + *VUpdateOffsetPix = (unsigned int)dml_ceil(HTotal / 4.0, 1); *TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock; *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; *Tdmec = HTotal / PixelClock; @@ -3723,17 +3723,17 @@ static noinline void CalculatePrefetchSchedulePerPlane( mode_lib, HostVMInefficiencyFactor, &myPipe, - v->DSCDelayPerState[i][k], + (unsigned int)v->DSCDelayPerState[i][k], v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater, v->DPPCLKDelaySCL, v->DPPCLKDelaySCLLBOnly, v->DPPCLKDelayCNVCCursor, v->DISPCLKDelaySubtotal, - v->SwathWidthYThisState[k] / v->HRatio[k], + (unsigned int)(v->SwathWidthYThisState[k] / v->HRatio[k]), v->OutputFormat[k], v->MaxInterDCNTileRepeaters, - dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), - v->MaximumVStartup[i][j][k], + (unsigned int)dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), + (unsigned int)v->MaximumVStartup[i][j][k], v->GPUVMMaxPageTableLevels, v->GPUVMEnable, v->HostVMEnable, @@ -3746,15 +3746,15 @@ static noinline void CalculatePrefetchSchedulePerPlane( v->UrgLatency[i], v->ExtraLatency, v->TimeCalc, - v->PDEAndMetaPTEBytesPerFrame[i][j][k], - v->MetaRowBytes[i][j][k], - v->DPTEBytesPerRow[i][j][k], + (unsigned int)v->PDEAndMetaPTEBytesPerFrame[i][j][k], + (unsigned int)v->MetaRowBytes[i][j][k], + (unsigned int)v->DPTEBytesPerRow[i][j][k], v->PrefetchLinesY[i][j][k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->PrefillY[k], v->MaxNumSwY[k], v->PrefetchLinesC[i][j][k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->PrefillC[k], v->MaxNumSwC[k], v->swath_width_luma_ub_this_state[k], @@ -3783,9 +3783,10 @@ static noinline void CalculatePrefetchSchedulePerPlane( &v->VReadyOffsetPix[k]); } -static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[]) +static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, unsigned int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[]) { - int i, total_pipes = 0; + int total_pipes = 0; + unsigned int i; for (i = 0; i < NumberOfActivePlanes; i++) total_pipes += NoOfDPPThisState[i]; DETBufferSizeInKByte[0] = ((config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB) / 64 / total_pipes) * 64; @@ -3800,10 +3801,10 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l { struct vba_vars_st *v = &mode_lib->vba; - int i, j; - unsigned int k, m; + int idx; + unsigned int i, j, k, m; int ReorderingBytes; - int MinPrefetchMode = 0, MaxPrefetchMode = 2; + unsigned int MinPrefetchMode = 0, MaxPrefetchMode = 2; bool NoChroma = true; bool EnoughWritebackUnits = true; bool P2IWith420 = false; @@ -3954,9 +3955,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } for (k = 0; k < v->NumberOfActivePlanes; k++) { @@ -4003,17 +4004,17 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l int MaximumSwathWidthSupportChroma; if (v->SurfaceTiling[k] == dm_sw_linear) { - MaximumSwathWidthSupportLuma = 8192.0; + MaximumSwathWidthSupportLuma = (int)8192.0; } else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) { - MaximumSwathWidthSupportLuma = 2880.0; + MaximumSwathWidthSupportLuma = (int)2880.0; } else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) { - MaximumSwathWidthSupportLuma = 3840.0; + MaximumSwathWidthSupportLuma = (int)3840.0; } else { - MaximumSwathWidthSupportLuma = 5760.0; + MaximumSwathWidthSupportLuma = (int)5760.0; } if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) { - MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma / 2.0; + MaximumSwathWidthSupportChroma = (int)(MaximumSwathWidthSupportLuma / 2.0); } else { MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma; } @@ -4245,7 +4246,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->DISPCLK_DPPCLK_Support[i][j] = false; } } - v->TotalNumberOfActiveDPP[i][j] = 0.0; + v->TotalNumberOfActiveDPP[i][j] = 0; for (k = 0; k < v->NumberOfActivePlanes; k++) { v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k]; } @@ -4282,7 +4283,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (k = 0; k < v->NumberOfActivePlanes; ++k) { if (v->BlendingAndTiming[k] == k) { if (v->PixelClockBackEnd[k] > 3200) { - v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); + v->NumberOfDSCSlices[k] = (unsigned int)dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); } else if (v->PixelClockBackEnd[k] > 1360) { v->NumberOfDSCSlices[k] = 8; } else if (v->PixelClockBackEnd[k] > 680) { @@ -4344,7 +4345,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 10000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4363,7 +4364,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 10000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4386,7 +4387,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 13500, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4405,7 +4406,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 13500, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4428,7 +4429,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 20000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4447,7 +4448,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 20000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4470,7 +4471,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->PHYCLKPerState[i] >= 270.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 2700, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4490,7 +4491,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 5400, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4510,7 +4511,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 8100, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4608,7 +4609,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->DSCDelayPerState[i][k] = dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -4617,7 +4618,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * (dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 2, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); @@ -4626,7 +4627,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * (dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 4, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); @@ -4716,14 +4717,14 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->RequiredDPPCLKThisState, v->ReadBandwidthLuma, v->ReadBandwidthChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->ProjectedDCFCLKDeepSleep[i][j]); for (k = 0; k < v->NumberOfActivePlanes; ++k) { v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k]; v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k]; - v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k]; - v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k]; + v->SwathWidthYAllStates[i][j][k] = (unsigned int)v->SwathWidthYThisState[k]; + v->SwathWidthCAllStates[i][j][k] = (unsigned int)v->SwathWidthCThisState[k]; v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k]; v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k]; v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k]; @@ -4748,8 +4749,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; } v->TotalNumberOfDCCActiveDPP[i][j] = 0; @@ -4782,16 +4783,16 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], - 0.0, + 0, &v->MacroTileWidthC[k], &v->MetaRowBytesC, &v->DPTEBytesPerRowC, @@ -4824,8 +4825,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma; v->PTEBufferSizeInRequestsForChroma = 0; v->PDEAndMetaPTEBytesPerFrameC = 0.0; - v->MetaRowBytesC = 0.0; - v->DPTEBytesPerRowC = 0.0; + v->MetaRowBytesC = 0; + v->DPTEBytesPerRowC = 0; v->PrefetchLinesC[i][j][k] = 0.0; v->PTEBufferSizeNotExceededC[i][j][k] = true; } @@ -4838,13 +4839,13 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -4978,9 +4979,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (int)v->WritebackDestinationWidth[k], + (int)v->WritebackDestinationHeight[k], + (int)v->WritebackSourceHeight[k], v->HTotal[k]) / v->RequiredDISPCLK[i][j]; } else { v->WritebackDelayTime[k] = 0.0; @@ -4995,9 +4996,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->WritebackHRatio[m], v->WritebackVRatio[m], v->WritebackVTaps[m], - v->WritebackDestinationWidth[m], - v->WritebackDestinationHeight[m], - v->WritebackSourceHeight[m], + (int)v->WritebackDestinationWidth[m], + (int)v->WritebackDestinationHeight[m], + (int)v->WritebackSourceHeight[m], v->HTotal[m]) / v->RequiredDISPCLK[i][j]); } } @@ -5030,11 +5031,11 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - ReorderingBytes = v->NumberOfChannels + ReorderingBytes = (int)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); for (i = 0; i < v->soc.num_states; ++i) { for (j = 0; j <= 1; ++j) { @@ -5118,7 +5119,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l double HostVMInefficiencyFactor = 1; int NextPrefetchModeState = MinPrefetchMode; bool UnboundedRequestEnabledThisState = false; - int CompressedBufferSizeInkByteThisState = 0; + unsigned int CompressedBufferSizeInkByteThisState = 0; double dummy; v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j]; @@ -5137,8 +5138,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; } VMDataOnlyReturnBWPerState = dml_min( @@ -5152,7 +5153,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l HostVMInefficiencyFactor = v->ReturnBWPerState[i][j] / VMDataOnlyReturnBWPerState; v->ExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (int)v->RoundTripPingLatencyCycles, ReorderingBytes, v->DCFCLKState[i][j], v->TotalNumberOfActiveDPP[i][j], @@ -5285,11 +5286,11 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l * v->UrgentBurstFactorChromaPre[k]) + v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]); } - v->TotImmediateFlipBytes = 0.0; + v->TotImmediateFlipBytes = 0; for (k = 0; k < v->NumberOfActivePlanes; k++) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k] - + v->DPTEBytesPerRow[i][j][k]); + + v->DPTEBytesPerRow[i][j][k])); } for (k = 0; k < v->NumberOfActivePlanes; k++) { @@ -5451,46 +5452,53 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = v->soc.num_states - 1; i >= 0; i--) { + for (idx = (int)v->soc.num_states - 1; idx >= 0; idx--) { for (j = 0; j < 2; j++) { - if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true - && v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP - && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false - && v->DTBCLKRequiredMoreThanSupported[i] == false - && v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true - && v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true + if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true + && v->ViewportSizeSupport[idx][j] == true + && v->LinkCapacitySupport[idx] == true && !P2IWith420 + && !DSCOnlyIfNecessaryWithBPP + && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[idx] == true + && v->NotEnoughDSCUnits[idx] == false + && v->DTBCLKRequiredMoreThanSupported[idx] == false + && v->ROBSupport[idx][j] == true && v->DISPCLK_DPPCLK_Support[idx][j] == true + && v->TotalAvailablePipesSupport[idx][j] == true && EnoughWritebackUnits == true && v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true - && v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false - && v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true - && v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true - && v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false + && v->CursorSupport == true && v->PitchSupport == true + && ViewportExceedsSurface == false + && v->PrefetchSupported[idx][j] == true + && v->DynamicMetadataSupported[idx][j] == true + && v->TotalVerticalActiveBandwidthSupport[idx][j] == true + && v->VRatioInPrefetchSupported[idx][j] == true + && v->PTEBufferSizeNotExceeded[idx][j] == true + && v->NonsupportedDSCInputBPC == false && ((v->HostVMEnable == false && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) - || v->ImmediateFlipSupportedForState[i][j] == true) + || v->ImmediateFlipSupportedForState[idx][j] == true) && FMTBufferExceeded == false) { - v->ModeSupport[i][j] = true; + v->ModeSupport[idx][j] = true; } else { - v->ModeSupport[i][j] = false; + v->ModeSupport[idx][j] = false; #ifdef __DML_VBA_DEBUG__ if (v->ScaleRatioAndTapsSupport == false) dml_print("DML SUPPORT: ScaleRatioAndTapsSupport failed"); if (v->SourceFormatPixelAndScanSupport == false) dml_print("DML SUPPORT: SourceFormatPixelAndScanSupport failed"); - if (v->ViewportSizeSupport[i][j] == false) + if (v->ViewportSizeSupport[idx][j] == false) dml_print("DML SUPPORT: ViewportSizeSupport failed"); - if (v->LinkCapacitySupport[i] == false) + if (v->LinkCapacitySupport[idx] == false) dml_print("DML SUPPORT: LinkCapacitySupport failed"); - if (v->ODMCombine4To1SupportCheckOK[i] == false) + if (v->ODMCombine4To1SupportCheckOK[idx] == false) dml_print("DML SUPPORT: DSC422NativeNotSupported failed"); - if (v->NotEnoughDSCUnits[i] == true) + if (v->NotEnoughDSCUnits[idx] == true) dml_print("DML SUPPORT: NotEnoughDSCUnits"); - if (v->DTBCLKRequiredMoreThanSupported[i] == true) + if (v->DTBCLKRequiredMoreThanSupported[idx] == true) dml_print("DML SUPPORT: DTBCLKRequiredMoreThanSupported"); - if (v->ROBSupport[i][j] == false) + if (v->ROBSupport[idx][j] == false) dml_print("DML SUPPORT: ROBSupport failed"); - if (v->DISPCLK_DPPCLK_Support[i][j] == false) + if (v->DISPCLK_DPPCLK_Support[idx][j] == false) dml_print("DML SUPPORT: DISPCLK_DPPCLK_Support failed"); - if (v->TotalAvailablePipesSupport[i][j] == false) + if (v->TotalAvailablePipesSupport[idx][j] == false) dml_print("DML SUPPORT: DSC422NativeNotSupported failed"); if (EnoughWritebackUnits == false) dml_print("DML SUPPORT: DSC422NativeNotSupported failed"); @@ -5504,21 +5512,21 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l dml_print("DML SUPPORT: PitchSupport failed"); if (ViewportExceedsSurface == true) dml_print("DML SUPPORT: ViewportExceedsSurface failed"); - if (v->PrefetchSupported[i][j] == false) + if (v->PrefetchSupported[idx][j] == false) dml_print("DML SUPPORT: PrefetchSupported failed"); - if (v->DynamicMetadataSupported[i][j] == false) + if (v->DynamicMetadataSupported[idx][j] == false) dml_print("DML SUPPORT: DSC422NativeNotSupported failed"); - if (v->TotalVerticalActiveBandwidthSupport[i][j] == false) + if (v->TotalVerticalActiveBandwidthSupport[idx][j] == false) dml_print("DML SUPPORT: TotalVerticalActiveBandwidthSupport failed"); - if (v->VRatioInPrefetchSupported[i][j] == false) + if (v->VRatioInPrefetchSupported[idx][j] == false) dml_print("DML SUPPORT: VRatioInPrefetchSupported failed"); - if (v->PTEBufferSizeNotExceeded[i][j] == false) + if (v->PTEBufferSizeNotExceeded[idx][j] == false) dml_print("DML SUPPORT: PTEBufferSizeNotExceeded failed"); if (v->NonsupportedDSCInputBPC == true) dml_print("DML SUPPORT: NonsupportedDSCInputBPC failed"); if (!((v->HostVMEnable == false && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) - || v->ImmediateFlipSupportedForState[i][j] == true)) + || v->ImmediateFlipSupportedForState[idx][j] == true)) dml_print("DML SUPPORT: ImmediateFlipRequirement failed"); if (FMTBufferExceeded == true) dml_print("DML SUPPORT: FMTBufferExceeded failed"); @@ -5529,11 +5537,12 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l { unsigned int MaximumMPCCombine = 0; - for (i = v->soc.num_states; i >= 0; i--) { - if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) { - v->VoltageLevel = i; - v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true; - if (v->ModeSupport[i][0] == true) { + for (idx = (int)v->soc.num_states; idx >= 0; idx--) { + if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true + || v->ModeSupport[idx][1] == true) { + v->VoltageLevel = idx; + v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true; + if (v->ModeSupport[idx][0] == true) { MaximumMPCCombine = 0; } else { MaximumMPCCombine = 1; @@ -5541,7 +5550,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine]; - for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { + for (k = 0; k < v->NumberOfActivePlanes; k++) { v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k]; v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k]; } @@ -5599,7 +5608,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank; double WritebackDRAMClockChangeLatencyHiding; double TotalPixelBW = 0.0; - int k, j; + unsigned int k, j; v->UrgentWatermark = UrgentLatency + ExtraLatency; @@ -5644,13 +5653,13 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( for (k = 0; k < v->NumberOfActivePlanes; ++k) { double EffectiveDETBufferSizeY = DETBufferSizeY[k]; - v->LBLatencyHidingSourceLinesY = dml_min( + v->LBLatencyHidingSourceLinesY = (unsigned int)(dml_min( (double) v->MaxLineBufferLines, - dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); + dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1)); - v->LBLatencyHidingSourceLinesC = dml_min( + v->LBLatencyHidingSourceLinesC = (unsigned int)(dml_min( (double) v->MaxLineBufferLines, - dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); + dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]); @@ -5662,11 +5671,11 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( } LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; - LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + LinesInDETYRoundedDownToSwath[k] = (unsigned int)dml_floor(LinesInDETY[k], SwathHeightY[k]); FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; if (BytePerPixelDETC[k] > 0) { LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; - LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); + LinesInDETCRoundedDownToSwath = (unsigned int)dml_floor(LinesInDETC, SwathHeightC[k]); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k]; } else { LinesInDETC = 0; @@ -5765,8 +5774,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -5787,7 +5796,7 @@ static void CalculateDCFCLKDeepSleep( double DisplayPipeLineDeliveryTimeLuma; double DisplayPipeLineDeliveryTimeChroma; double ReadBandwidth = 0.0; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { @@ -5917,7 +5926,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], @@ -5938,7 +5947,7 @@ static void CalculatePixelDeliveryTimes( double CursorRequestDeliveryTimePrefetch[]) { double req_per_swath_ub; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { if (VRatio[k] <= 1) { @@ -6012,7 +6021,7 @@ static void CalculatePixelDeliveryTimes( for (k = 0; k < NumberOfActivePlanes; ++k) { int cursor_req_per_width; - cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); + cursor_req_per_width = (int)dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); if (NumberOfCursors[k] > 0) { if (VRatio[k] <= 1) { CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width; @@ -6041,35 +6050,35 @@ static void CalculateMetaAndPTETimes( bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -6146,7 +6155,7 @@ static void CalculateMetaAndPTETimes( } else { meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; - meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma; + meta_chunk_per_row_int_chroma = (unsigned int)((double) meta_row_width_chroma[k] / meta_chunk_width_chroma); meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma; if (SourceScan[k] != dm_vert) { meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k]; @@ -6179,7 +6188,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k]; } - dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; @@ -6193,7 +6202,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k]; } - dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; @@ -6214,18 +6223,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -6235,34 +6244,34 @@ static void CalculateVMGroupAndRequestTimes( (void)dpte_row_width_chroma_ub; int num_group_per_lower_vm_stage; int num_req_per_lower_vm_stage; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { if (DCCEnable[k] == false) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (GPUVMMaxPageTableLevels == 1) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + num_group_per_lower_vm_stage = (int)(2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)); } } } @@ -6333,29 +6342,29 @@ static void CalculateStutterEfficiency( bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -6573,8 +6582,8 @@ static void CalculateStutterEfficiency( #endif *StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100; *Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100; - *NumberOfStutterBurstsPerFrame = (*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); - *Z8NumberOfStutterBurstsPerFrame = (*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); + *NumberOfStutterBurstsPerFrame = (int)(*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); + *Z8NumberOfStutterBurstsPerFrame = (int)(*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); } else { *StutterEfficiencyNotIncludingVBlank = 0.; *Z8StutterEfficiencyNotIncludingVBlank = 0.; @@ -6640,48 +6649,48 @@ static void CalculateSwathAndDETConfiguration( enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], bool *ViewportSizeSupport) { (void)HRatioChroma; - int MaximumSwathHeightY[DC__NUM_DPP__MAX]; - int MaximumSwathHeightC[DC__NUM_DPP__MAX]; - int MinimumSwathHeightY; - int MinimumSwathHeightC; - int RoundedUpMaxSwathSizeBytesY; - int RoundedUpMaxSwathSizeBytesC; - int RoundedUpMinSwathSizeBytesY; - int RoundedUpMinSwathSizeBytesC; - int RoundedUpSwathSizeBytesY; - int RoundedUpSwathSizeBytesC; + unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX]; + unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX]; + unsigned int MinimumSwathHeightY; + unsigned int MinimumSwathHeightC; + unsigned int RoundedUpMaxSwathSizeBytesY; + unsigned int RoundedUpMaxSwathSizeBytesC; + unsigned int RoundedUpMinSwathSizeBytesY; + unsigned int RoundedUpMinSwathSizeBytesC; + unsigned int RoundedUpSwathSizeBytesY; + unsigned int RoundedUpSwathSizeBytesC; double SwathWidthSingleDPP[DC__NUM_DPP__MAX]; double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX]; int k; @@ -6755,17 +6764,17 @@ static void CalculateSwathAndDETConfiguration( } } - RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]; - RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY; + RoundedUpMaxSwathSizeBytesY = (int)(swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]); + RoundedUpMinSwathSizeBytesY = (int)(swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesY = dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); - RoundedUpMinSwathSizeBytesY = dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); + RoundedUpMaxSwathSizeBytesY = (int)dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); + RoundedUpMinSwathSizeBytesY = (int)dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); } - RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]; - RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC; + RoundedUpMaxSwathSizeBytesC = (int)(swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]); + RoundedUpMinSwathSizeBytesC = (int)(swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesC = dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); - RoundedUpMinSwathSizeBytesC = dml_ceil(RoundedUpMinSwathSizeBytesC, 256); + RoundedUpMaxSwathSizeBytesC = (int)dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); + RoundedUpMinSwathSizeBytesC = (int)dml_ceil(RoundedUpMinSwathSizeBytesC, 256); } if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) { @@ -6794,14 +6803,14 @@ static void CalculateSwathAndDETConfiguration( { double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); if (SwathHeightC[k] == 0) { - DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024; + DETBufferSizeY[k] = (unsigned int)(actDETBufferSizeInKByte * 1024); DETBufferSizeC[k] = 0; } else if (RoundedUpSwathSizeBytesY <= 1.5 * RoundedUpSwathSizeBytesC) { - DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2; - DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2; + DETBufferSizeY[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 2); + DETBufferSizeC[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 2); } else { - DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024); - DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3; + DETBufferSizeY[k] = (unsigned int)dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024); + DETBufferSizeC[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 3); } if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k] @@ -6820,31 +6829,31 @@ static void CalculateSwathWidth( int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], - int HActive[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], + unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[]) + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[]) { (void)BytePerPixY; enum odm_combine_mode MainPlaneODMCombine; @@ -6901,8 +6910,8 @@ static void CalculateSwathWidth( SwathWidthC[k] = SwathWidthSingleDPPC[k]; } { - int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); - int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); + int surface_width_ub_l = (int)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); + int surface_height_ub_l = (int)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l); @@ -6911,11 +6920,11 @@ static void CalculateSwathWidth( if (SourceScan[k] != dm_vert) { MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k]; MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k]; - swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); + swath_width_luma_ub[k] = (int)dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); if (BytePerPixC[k] > 0) { - int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); + int surface_width_ub_c = (int)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); - swath_width_chroma_ub[k] = dml_min( + swath_width_chroma_ub[k] = (int)dml_min( surface_width_ub_c, (int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]); } else { @@ -6924,11 +6933,11 @@ static void CalculateSwathWidth( } else { MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k]; MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k]; - swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); + swath_width_luma_ub[k] = (int)dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); if (BytePerPixC[k] > 0) { - int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); + int surface_height_ub_c = (int)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); - swath_width_chroma_ub[k] = dml_min( + swath_width_chroma_ub[k] = (int)dml_min( surface_height_ub_c, (int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]); } else { @@ -6951,8 +6960,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) @@ -6997,8 +7006,8 @@ static double CalculateExtraLatencyBytes( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) @@ -7010,9 +7019,9 @@ static double CalculateExtraLatencyBytes( if (HostVMMinPageSize < 2048) { HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); } else { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } } else { HostVMDynamicLevels = 0; @@ -7052,7 +7061,9 @@ static noinline_for_stack void UseMinimumDCFCLK( int ReorderingBytes) { struct vba_vars_st *v = &mode_lib->vba; - int dummy1, i, j, k; + unsigned int dummy1; + unsigned int j, k; + unsigned int i; double NormalEfficiency, dummy2, dummy3; double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; @@ -7070,7 +7081,7 @@ static noinline_for_stack void UseMinimumDCFCLK( double ExtraLatencyBytes; double ExtraLatencyCycles; double DCFCLKRequiredForPeakBandwidth; - int NoOfDPPState[DC__NUM_DPP__MAX]; + unsigned int NoOfDPPState[DC__NUM_DPP__MAX]; double MinimumTvmPlus2Tr0; TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; @@ -7079,9 +7090,8 @@ static noinline_for_stack void UseMinimumDCFCLK( + v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]); } - for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) { + for (k = 0; k < v->NumberOfActivePlanes; ++k) NoOfDPPState[k] = v->NoOfDPP[i][j][k]; - } MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime); NonDPTEBandwidth = v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j]; @@ -7182,9 +7192,8 @@ static noinline_for_stack void UseMinimumDCFCLK( } } DCFCLKRequiredForPeakBandwidth = 0; - for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) { + for (k = 0; k < v->NumberOfActivePlanes; ++k) DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k]; - } MinimumTvmPlus2Tr0 = v->UrgLatency[i] * (v->GPUVMEnable == true ? (v->HostVMEnable == true ? @@ -7217,12 +7226,12 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( int CompressedBufferSegmentSizeInkByteFinal, enum output_encoder_class *Output, bool *UnboundedRequestEnabled, - int *CompressedBufferSizeInkByte) + unsigned int *CompressedBufferSizeInkByte) { double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); *UnboundedRequestEnabled = UnboundedRequest(UseUnboundedRequestingFinal, TotalActiveDPP, NoChromaPlanes, Output[0]); - *CompressedBufferSizeInkByte = ( + *CompressedBufferSizeInkByte = (int)( *UnboundedRequestEnabled == true ? ConfigReturnBufferSizeInKByte - TotalActiveDPP * actDETBufferSizeInKByte : ConfigReturnBufferSizeInKByte - MaxNumDPP * actDETBufferSizeInKByte); @@ -7235,7 +7244,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( dml_print("DML::%s: UseUnboundedRequestingFinal = %d\n", __func__, UseUnboundedRequestingFinal); dml_print("DML::%s: actDETBufferSizeInKByte = %f\n", __func__, actDETBufferSizeInKByte); dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, *UnboundedRequestEnabled); - dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte); + dml_print("DML::%s: CompressedBufferSizeInkByte = %u\n", __func__, *CompressedBufferSizeInkByte); #endif } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c index dfa1bc31eb0a..ada80b3086ff 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c @@ -117,11 +117,11 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_s extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3); } rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); @@ -141,12 +141,12 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_s // Note: detile_buf_plane1_addr is in unit of 1KB if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr); #endif } else { - detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0; // 2/3 to luma + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0); // 2/3 to luma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/3 chroma)\n", __func__, detile_buf_plane1_addr); #endif @@ -189,8 +189,8 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_p #endif if (rq_param->yuv420_10bpc) { - full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; - full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; + full_swath_bytes_packed_l = (unsigned int)(dml_round_to_multiple((unsigned int)(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256); + full_swath_bytes_packed_c = (unsigned int)(dml_round_to_multiple((unsigned int)(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256); #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_l); dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_c); @@ -421,7 +421,7 @@ static void get_meta_and_pte_attr( // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -574,7 +574,7 @@ static void get_meta_and_pte_attr( if (surf_linear) { unsigned int dpte_row_height; - log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); + log2_dpte_row_height_linear = (unsigned int)(dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1)); dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma); dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs); @@ -640,7 +640,7 @@ static void get_meta_and_pte_attr( // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); } static void get_surf_rq_param( @@ -665,7 +665,7 @@ static void get_surf_rq_param( vp_height = pipe_param->src.viewport_height_c; data_pitch = pipe_param->src.data_pitch_c; meta_pitch = pipe_param->src.meta_pitch_c; - surface_height = pipe_param->src.surface_height_y / 2.0; + surface_height = (unsigned int)(pipe_param->src.surface_height_y / 2.0); } else { vp_width = pipe_param->src.viewport_width / ppe; vp_height = pipe_param->src.viewport_height; @@ -683,18 +683,18 @@ static void get_surf_rq_param( access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine * 2); if (is_chroma) { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm); } else { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm); } if (access_dir == 0) { - vp_width = dml_min(full_src_vp_width, src_hactive_odm); + vp_width = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); } else { - vp_height = dml_min(full_src_vp_width, src_hactive_odm); + vp_height = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); } @@ -814,7 +814,7 @@ static void calculate_ttu_cursor( cur_req_size = 256; } - cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double) cur_req_size / ((double) cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; cur_req_per_width = cur_width_ub / (double) cur_req_width; hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor @@ -1051,8 +1051,8 @@ static void dml_rq_dlg_get_dlg_params( if (interlaced) vstartup_start = vstartup_start / 2; - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_y_after_scaler = (unsigned int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA // do some adjustment on the dst_after scaler to account for odm combine mode dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); @@ -1278,9 +1278,9 @@ static void dml_rq_dlg_get_dlg_params( } if (src->dynamic_metadata_enable && src->gpuvm) - disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + disp_dlg_regs->refcyc_per_vm_dmdata = (unsigned int)(get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA - disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + disp_dlg_regs->dmdata_dl_delta = (unsigned int)(get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA // TTU - Luma / Chroma if (access_dir) { // vertical access @@ -1386,8 +1386,8 @@ static void dml_rq_dlg_get_dlg_params( src->cur0_src_width, (enum cursor_bpp) (src->cur0_bpp)); - vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + vba__refcyc_per_req_delivery_pre_cur0 = (float)(get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + vba__refcyc_per_req_delivery_cur0 = (float)(get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0); dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_cur0); @@ -1407,7 +1407,7 @@ static void dml_rq_dlg_get_dlg_params( // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8); - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); @@ -1444,23 +1444,23 @@ static void dml_rq_dlg_get_dlg_params( disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; } - disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA - disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA // Clamp to max for now if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2)); ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); @@ -1484,23 +1484,23 @@ static void dml_rq_dlg_get_dlg_params( disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); // TODO: Is this the right calculation? Does htotal need to be halved? disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_c); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); @@ -1541,7 +1541,7 @@ static void dml_rq_dlg_get_dlg_params( disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1572,7 +1572,7 @@ void dml31_rq_dlg_get_dlg_reg( dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); print__dlg_sys_params_st(mode_lib, &dlg_sys_param); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c index ab016c294ba7..2f9ae79da731 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c @@ -185,7 +185,7 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p struct _vcs_dpi_voltage_scaling_st *clock_limits = dcn3_14_soc.clock_limits; unsigned int i, closest_clk_lvl; - int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; int j; dc_assert_fp_enabled(); @@ -284,11 +284,11 @@ static bool is_dual_plane(enum surface_pixel_format format) static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) { unsigned int num_lines = 0; - unsigned int lines_time_in_ns = 1000.0 * - (((float)timing->h_total * 1000.0) / - ((float)timing->pix_clk_100hz / 10.0)); + double lines_time_in_ns = 1000.0 * + (((double)timing->h_total * 1000.0) / + ((double)timing->pix_clk_100hz / 10.0)); - num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); + num_lines = (unsigned int)dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); return num_lines; } @@ -308,7 +308,8 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + int pipe_cnt; + unsigned int i; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; bool upscaled = false; @@ -409,15 +410,15 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c context->bw_ctx.dml.ip.odm_combine_4to1_supported = true; for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream) + if (!cur_pipe->stream) continue; - if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && - pipe->stream->apply_seamless_boot_optimization) { + if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && + cur_pipe->stream->apply_seamless_boot_optimization) { - if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { + if (cur_pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; break; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index 033fde774337..dd9dc0c8cb43 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -166,7 +166,7 @@ static bool CalculatePrefetchSchedule( double *Tdmdl_vm, double *Tdmdl, double *TSetup, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix); static double RoundToDFSGranularityUp(double Clock, double VCOSpeed); @@ -227,19 +227,19 @@ static unsigned int CalculateVMAndRowBytes( unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, - int *dpte_row_width_ub, + unsigned int *dpte_row_width_ub, unsigned int *dpte_row_height, unsigned int *MetaRequestWidth, unsigned int *MetaRequestHeight, unsigned int *meta_row_width, unsigned int *meta_row_height, - int *vm_group_bytes, + unsigned int *vm_group_bytes, unsigned int *dpte_group_bytes, unsigned int *PixelPTEReqWidth, unsigned int *PixelPTEReqHeight, unsigned int *PTERequestSize, - int *DPDE0BytesFrame, - int *MetaPTEBytesFrame); + unsigned int *DPDE0BytesFrame, + unsigned int *MetaPTEBytesFrame); static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime); static void CalculateRowBandwidth( bool GPUVMEnable, @@ -294,7 +294,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( double *Tdmbf, double *Tdmec, double *Tdmsks, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix); @@ -327,8 +327,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -386,7 +386,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], @@ -407,39 +407,39 @@ static void CalculatePixelDeliveryTimes( double CursorRequestDeliveryTimePrefetch[]); static void CalculateMetaAndPTETimes( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -462,18 +462,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -501,29 +501,29 @@ static void CalculateStutterEfficiency( bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -547,32 +547,32 @@ static void CalculateSwathAndDETConfiguration( enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], @@ -582,31 +582,31 @@ static void CalculateSwathWidth( int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], - int HActive[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], + unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[]); + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[]); static double CalculateExtraLatency( int RoundTripPingLatencyCycles, @@ -620,8 +620,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels); @@ -635,8 +635,8 @@ static double CalculateExtraLatencyBytes( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels); @@ -660,7 +660,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( int CompressedBufferSegmentSizeInkByteFinal, enum output_encoder_class *Output, bool *UnboundedRequestEnabled, - int *CompressedBufferSizeInkByte); + unsigned int *CompressedBufferSizeInkByte); static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output); static unsigned int CalculateMaxVStartup( @@ -718,7 +718,7 @@ static unsigned int dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -887,7 +887,7 @@ static bool CalculatePrefetchSchedule( double *Tdmdl_vm, double *Tdmdl, double *TSetup, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) { @@ -1003,13 +1003,13 @@ static bool CalculatePrefetchSchedule( *Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0); if (myPipe->ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor); - DISPCLKCycles = DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)DISPCLKDelaySubtotal; if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) return true; @@ -1527,14 +1527,14 @@ static void CalculateDCCConfiguration( double detile_buf_vp_horz_limit; double detile_buf_vp_vert_limit; - int MAS_vp_horz_limit; - int MAS_vp_vert_limit; - int max_vp_horz_width; - int max_vp_vert_height; - int eff_surf_width_l; - int eff_surf_width_c; - int eff_surf_height_l; - int eff_surf_height_c; + unsigned int MAS_vp_horz_limit; + unsigned int MAS_vp_vert_limit; + unsigned int max_vp_horz_width; + unsigned int max_vp_vert_height; + unsigned int eff_surf_width_l; + unsigned int eff_surf_width_c; + unsigned int eff_surf_height_l; + unsigned int eff_surf_height_c; int full_swath_bytes_horz_wc_l; int full_swath_bytes_horz_wc_c; @@ -1571,11 +1571,11 @@ static void CalculateDCCConfiguration( horz_div_c = 0; if (BytePerPixelC == 0) { - swath_buf_size = DETBufferSize / 2 - 2 * 256; + swath_buf_size = (int)(DETBufferSize / 2 - 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l)); detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l)); } else { - swath_buf_size = DETBufferSize / 2 - 2 * 2 * 256; + swath_buf_size = (int)(DETBufferSize / 2 - 2 * 2 * 256); detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l) + (double) RequestHeight256ByteChroma * BytePerPixelC / (1 + horz_div_c) / (1 + yuv420)); @@ -1593,8 +1593,8 @@ static void CalculateDCCConfiguration( MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 5760; MAS_vp_vert_limit = (BytePerPixelC > 0 ? 2880 : 5760); - max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); - max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); + max_vp_horz_width = (int)dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); + max_vp_vert_height = (int)dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); eff_surf_width_l = (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma); eff_surf_width_c = eff_surf_width_l / (1 + yuv420); eff_surf_height_l = (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma); @@ -1611,10 +1611,10 @@ static void CalculateDCCConfiguration( } if (SourcePixelFormat == dm_420_10) { - full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); - full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); - full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); - full_swath_bytes_vert_wc_c = dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); + full_swath_bytes_horz_wc_l = (int)dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); + full_swath_bytes_horz_wc_c = (int)dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); + full_swath_bytes_vert_wc_l = (int)dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); + full_swath_bytes_vert_wc_c = (int)dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256); } if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) { @@ -1777,20 +1777,20 @@ static double CalculatePrefetchSourceLines( if (!v->IgnoreViewportPositioning) { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; + *MaxNumSwath = (unsigned int)(dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight; else MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight; - MaxPartialSwath = dml_max(1U, MaxPartialSwath); + MaxPartialSwath = (unsigned int)dml_max(1U, MaxPartialSwath); } else { if (ViewportYStart != 0) dml_print("WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n"); - *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); + *MaxNumSwath = (unsigned int)dml_ceil(*VInitPreFill / SwathHeight, 1); if (*VInitPreFill > 1.0) MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight; @@ -1835,19 +1835,19 @@ static unsigned int CalculateVMAndRowBytes( unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, - int *dpte_row_width_ub, + unsigned int *dpte_row_width_ub, unsigned int *dpte_row_height, unsigned int *MetaRequestWidth, unsigned int *MetaRequestHeight, unsigned int *meta_row_width, unsigned int *meta_row_height, - int *vm_group_bytes, + unsigned int *vm_group_bytes, unsigned int *dpte_group_bytes, unsigned int *PixelPTEReqWidth, unsigned int *PixelPTEReqHeight, unsigned int *PTERequestSize, - int *DPDE0BytesFrame, - int *MetaPTEBytesFrame) + unsigned int *DPDE0BytesFrame, + unsigned int *MetaPTEBytesFrame) { (void)SourcePixelFormat; struct vba_vars_st *v = &mode_lib->vba; @@ -1865,9 +1865,9 @@ static unsigned int CalculateVMAndRowBytes( if (HostVMMinPageSize < 2048) { HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; } else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); } else { - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } } @@ -1875,16 +1875,16 @@ static unsigned int CalculateVMAndRowBytes( *MetaRequestWidth = 8 * BlockWidth256Bytes; if (ScanDirection != dm_vert) { *meta_row_height = *MetaRequestHeight; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth; - *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0); } else { *meta_row_height = *MetaRequestWidth; - *meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight; - *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + *meta_row_width = (unsigned int)(dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight); + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0); } - DCCMetaSurfaceBytes = DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256; + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256); if (GPUVMEnable == true) { - *MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64; + *MetaPTEBytesFrame = (int)((dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64); MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1); } else { *MetaPTEBytesFrame = 0; @@ -1908,17 +1908,17 @@ static unsigned int CalculateVMAndRowBytes( if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) { if (ScanDirection != dm_vert) { - *DPDE0BytesFrame = 64 + *DPDE0BytesFrame = (int)(64 * (dml_ceil( ((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } else { - *DPDE0BytesFrame = 64 + *DPDE0BytesFrame = (int)(64 * (dml_ceil( ((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), - 1) + 1); + 1) + 1)); } ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2); } else { @@ -1946,7 +1946,7 @@ static unsigned int CalculateVMAndRowBytes( if (SurfaceTiling == dm_sw_linear) { PixelPTEReqHeightPTEs = 1; *PixelPTEReqHeight = 1; - *PixelPTEReqWidth = 32768.0 / BytePerPixel; + *PixelPTEReqWidth = (unsigned int)(32768.0 / BytePerPixel); *PTERequestSize = 64; FractionOfPTEReturnDrop = 0; } else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) { @@ -1964,16 +1964,16 @@ static unsigned int CalculateVMAndRowBytes( } if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); - *dpte_row_width_ub = (dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_height = (unsigned int)dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); + *dpte_row_width_ub = (int)((dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else if (ScanDirection != dm_vert) { *dpte_row_height = *PixelPTEReqHeight; - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else { - *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); - *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight; + *dpte_row_height = (unsigned int)dml_min(*PixelPTEReqWidth, *MacroTileWidth); + *dpte_row_width_ub = (int)((dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight); *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; } @@ -2059,9 +2059,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } @@ -2247,7 +2247,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DPPCLK, v->ReadBandwidthPlaneLuma, v->ReadBandwidthPlaneChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->DCFCLKDeepSleep); // DSCCLK @@ -2284,7 +2284,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->DSCDelay[k] = dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -2293,8 +2293,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman * (dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 2.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 2.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); } else { @@ -2302,13 +2302,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman * (dscceComputeDelay( v->DSCInputBitPerComponent[k], BPP, - dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), - v->NumberOfDSCSlices[k] / 4.0, + (unsigned int)dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1), + (unsigned int)(v->NumberOfDSCSlices[k] / 4.0), v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); } - v->DSCDelay[k] = v->DSCDelay[k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelay[k] / v->HActive[k], 1); - v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; + v->DSCDelay[k] = (unsigned int)(v->DSCDelay[k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelay[k] / v->HActive[k], 1)); + v->DSCDelay[k] = (unsigned int)(v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]); } else { v->DSCDelay[k] = 0; } @@ -2349,13 +2349,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], v->DCCMetaPitchC[k], @@ -2406,13 +2406,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -2478,11 +2478,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman NoChromaPlanes = false; } - ReorderBytes = v->NumberOfChannels + ReorderBytes = (int)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); VMDataOnlyReturnBW = dml_min( dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn) @@ -2508,7 +2508,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman HostVMInefficiencyFactor = v->ReturnBW / VMDataOnlyReturnBW; v->UrgentExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (int)v->RoundTripPingLatencyCycles, ReorderBytes, v->DCFCLK, v->TotalActiveDPP, @@ -2536,9 +2536,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (int)v->WritebackDestinationWidth[k], + (int)v->WritebackDestinationHeight[k], + (int)v->WritebackSourceHeight[k], v->HTotal[k]) / v->DISPCLK; } else v->WritebackDelay[v->VoltageLevel][k] = 0; @@ -2552,9 +2552,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->WritebackHRatio[j], v->WritebackVRatio[j], v->WritebackVTaps[j], - v->WritebackDestinationWidth[j], - v->WritebackDestinationHeight[j], - v->WritebackSourceHeight[j], + (int)v->WritebackDestinationWidth[j], + (int)v->WritebackDestinationHeight[j], + (int)v->WritebackSourceHeight[j], v->HTotal[k]) / v->DISPCLK); } } @@ -2588,7 +2588,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->MaximumMaxVStartupLines = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) - v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); + v->MaximumMaxVStartupLines = (unsigned int)dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); // VBA_DELTA // We don't really care to iterate between the various prefetch modes @@ -2658,7 +2658,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), v->OutputFormat[k], v->MaxInterDCNTileRepeaters, - dml_min(v->VStartupLines, v->MaxVStartupLines[k]), + (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]), v->MaxVStartupLines[k], v->GPUVMMaxPageTableLevels, v->GPUVMEnable, @@ -2672,15 +2672,15 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->UrgentLatency, v->UrgentExtraLatency, v->TCalc, - v->PDEAndMetaPTEBytesFrame[k], - v->MetaRowByte[k], - v->PixelPTEBytesPerRow[k], + (unsigned int)v->PDEAndMetaPTEBytesFrame[k], + (unsigned int)v->MetaRowByte[k], + (unsigned int)v->PixelPTEBytesPerRow[k], v->PrefetchSourceLinesY[k], - v->SwathWidthY[k], + (unsigned int)v->SwathWidthY[k], v->VInitPreFillY[k], v->MaxNumSwathY[k], v->PrefetchSourceLinesC[k], - v->SwathWidthC[k], + (unsigned int)v->SwathWidthC[k], v->VInitPreFillC[k], v->MaxNumSwathC[k], v->swath_width_luma_ub[k], @@ -2711,7 +2711,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]); #endif - v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); + v->VStartup[k] = (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]); } v->NoEnoughUrgentLatencyHiding = false; @@ -2865,8 +2865,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->TotImmediateFlipBytes = 0; for (k = 0; k < v->NumberOfActivePlanes; ++k) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes - + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]); + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k])); } for (k = 0; k < v->NumberOfActivePlanes; ++k) { CalculateFlipSchedule( @@ -3179,11 +3179,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP); v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]); if (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) { - v->MIN_DST_Y_NEXT_START[k] = dml_floor((v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k]) / 2.0, 1.0); + v->MIN_DST_Y_NEXT_START[k] = (unsigned int)dml_floor((v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k]) / 2.0, 1.0); } else { v->MIN_DST_Y_NEXT_START[k] = v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k]; } - v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / ((double)v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0; + v->MIN_DST_Y_NEXT_START[k] += (unsigned int)(dml_floor(4.0 * v->TSetup[k] / ((double)v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0); if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k]) <= (isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) : @@ -3297,18 +3297,18 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) // Display Pipe Configuration double BytePerPixDETY[DC__NUM_DPP__MAX]; double BytePerPixDETC[DC__NUM_DPP__MAX]; - int BytePerPixY[DC__NUM_DPP__MAX]; - int BytePerPixC[DC__NUM_DPP__MAX]; - int Read256BytesBlockHeightY[DC__NUM_DPP__MAX]; - int Read256BytesBlockHeightC[DC__NUM_DPP__MAX]; - int Read256BytesBlockWidthY[DC__NUM_DPP__MAX]; - int Read256BytesBlockWidthC[DC__NUM_DPP__MAX]; + unsigned int BytePerPixY[DC__NUM_DPP__MAX]; + unsigned int BytePerPixC[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX]; double dummy1[DC__NUM_DPP__MAX]; double dummy2[DC__NUM_DPP__MAX]; double dummy3[DC__NUM_DPP__MAX]; double dummy4[DC__NUM_DPP__MAX]; - int dummy5[DC__NUM_DPP__MAX]; - int dummy6[DC__NUM_DPP__MAX]; + unsigned int dummy5[DC__NUM_DPP__MAX]; + unsigned int dummy6[DC__NUM_DPP__MAX]; bool dummy7[DC__NUM_DPP__MAX]; bool dummysinglestring; @@ -3535,7 +3535,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( double *Tdmbf, double *Tdmec, double *Tdmsks, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) { @@ -3544,7 +3544,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / DPPCLK + 3 / DISPCLK); *VUpdateWidthPix = dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock, 1.0); *VReadyOffsetPix = dml_ceil(dml_max(150.0 / DPPCLK, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / DPPCLK) * PixelClock, 1.0); - *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); + *VUpdateOffsetPix = (unsigned int)dml_ceil(HTotal / 4.0, 1); *TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock; *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; *Tdmec = HTotal / PixelClock; @@ -3829,17 +3829,17 @@ static noinline void CalculatePrefetchSchedulePerPlane( mode_lib, HostVMInefficiencyFactor, &myPipe, - v->DSCDelayPerState[i][k], + (unsigned int)v->DSCDelayPerState[i][k], v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater, v->DPPCLKDelaySCL, v->DPPCLKDelaySCLLBOnly, v->DPPCLKDelayCNVCCursor, v->DISPCLKDelaySubtotal, - v->SwathWidthYThisState[k] / v->HRatio[k], + (unsigned int)(v->SwathWidthYThisState[k] / v->HRatio[k]), v->OutputFormat[k], v->MaxInterDCNTileRepeaters, - dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), - v->MaximumVStartup[i][j][k], + (unsigned int)dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), + (unsigned int)v->MaximumVStartup[i][j][k], v->GPUVMMaxPageTableLevels, v->GPUVMEnable, v->HostVMEnable, @@ -3852,15 +3852,15 @@ static noinline void CalculatePrefetchSchedulePerPlane( v->UrgLatency[i], v->ExtraLatency, v->TimeCalc, - v->PDEAndMetaPTEBytesPerFrame[i][j][k], - v->MetaRowBytes[i][j][k], - v->DPTEBytesPerRow[i][j][k], + (unsigned int)v->PDEAndMetaPTEBytesPerFrame[i][j][k], + (unsigned int)v->MetaRowBytes[i][j][k], + (unsigned int)v->DPTEBytesPerRow[i][j][k], v->PrefetchLinesY[i][j][k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->PrefillY[k], v->MaxNumSwY[k], v->PrefetchLinesC[i][j][k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->PrefillC[k], v->MaxNumSwC[k], v->swath_width_luma_ub_this_state[k], @@ -3893,10 +3893,11 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ { struct vba_vars_st *v = &mode_lib->vba; - int i, j; + int j; + unsigned int i; unsigned int k, m; int ReorderingBytes; - int MinPrefetchMode = 0, MaxPrefetchMode = 2; + unsigned int MinPrefetchMode = 0, MaxPrefetchMode = 2; bool NoChroma = true; bool EnoughWritebackUnits = true; bool P2IWith420 = false; @@ -4045,9 +4046,9 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->WritebackHTaps[k], v->WritebackVTaps[k], v->WritebackSourceWidth[k], - v->WritebackDestinationWidth[k], + (long)v->WritebackDestinationWidth[k], v->HTotal[k], - v->WritebackLineBufferSize)); + (unsigned int)v->WritebackLineBufferSize)); } } for (k = 0; k < v->NumberOfActivePlanes; k++) { @@ -4094,17 +4095,17 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ int MaximumSwathWidthSupportChroma; if (v->SurfaceTiling[k] == dm_sw_linear) { - MaximumSwathWidthSupportLuma = 8192.0; + MaximumSwathWidthSupportLuma = (int)8192.0; } else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) { - MaximumSwathWidthSupportLuma = 2880.0; + MaximumSwathWidthSupportLuma = (int)2880.0; } else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) { - MaximumSwathWidthSupportLuma = 3840.0; + MaximumSwathWidthSupportLuma = (int)3840.0; } else { - MaximumSwathWidthSupportLuma = 5760.0; + MaximumSwathWidthSupportLuma = (int)5760.0; } if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) { - MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma / 2.0; + MaximumSwathWidthSupportChroma = (int)(MaximumSwathWidthSupportLuma / 2.0); } else { MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma; } @@ -4332,7 +4333,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->DISPCLK_DPPCLK_Support[i][j] = false; } } - v->TotalNumberOfActiveDPP[i][j] = 0.0; + v->TotalNumberOfActiveDPP[i][j] = 0; for (k = 0; k < v->NumberOfActivePlanes; k++) { v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k]; } @@ -4369,7 +4370,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ for (k = 0; k < v->NumberOfActivePlanes; ++k) { if (v->BlendingAndTiming[k] == k) { if (v->PixelClockBackEnd[k] > 3200) { - v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); + v->NumberOfDSCSlices[k] = (unsigned int)dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); } else if (v->PixelClockBackEnd[k] > 1360) { v->NumberOfDSCSlices[k] = 8; } else if (v->PixelClockBackEnd[k] > 680) { @@ -4431,7 +4432,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 10000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4450,7 +4451,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 10000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4473,7 +4474,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 13500, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4492,7 +4493,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 13500, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4515,7 +4516,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 20000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4534,7 +4535,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->LinkDSCEnable = true; v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 20000, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4557,7 +4558,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ if (v->PHYCLKPerState[i] >= 270.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 2700, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4577,7 +4578,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 5400, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4597,7 +4598,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) { v->Outbpp = TruncToValidBPP( (1.0 - v->Downspreading / 100.0) * 8100, - v->OutputLinkDPLanes[k], + (int)v->OutputLinkDPLanes[k], v->HTotal[k], v->HActive[k], v->PixelClockBackEnd[k], @@ -4696,7 +4697,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->DSCDelayPerState[i][k] = dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k], v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]); @@ -4705,7 +4706,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ * (dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 2, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); @@ -4714,7 +4715,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ * (dscceComputeDelay( v->DSCInputBitPerComponent[k], v->BPP, - dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), + (unsigned int)dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0), v->NumberOfDSCSlices[k] / 4, v->OutputFormat[k], v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k])); @@ -4802,14 +4803,14 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->RequiredDPPCLKThisState, v->ReadBandwidthLuma, v->ReadBandwidthChroma, - v->ReturnBusWidth, + (int)v->ReturnBusWidth, &v->ProjectedDCFCLKDeepSleep[i][j]); for (k = 0; k < v->NumberOfActivePlanes; ++k) { v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k]; v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k]; - v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k]; - v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k]; + v->SwathWidthYAllStates[i][j][k] = (unsigned int)v->SwathWidthYThisState[k]; + v->SwathWidthCAllStates[i][j][k] = (unsigned int)v->SwathWidthCThisState[k]; v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k]; v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k]; v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k]; @@ -4834,8 +4835,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; } v->TotalNumberOfDCCActiveDPP[i][j] = 0; @@ -4868,16 +4869,16 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->SurfaceTiling[k], v->BytePerPixelC[k], v->SourceScan[k], - v->SwathWidthCThisState[k], + (unsigned int)v->SwathWidthCThisState[k], v->ViewportHeightChroma[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForChroma, v->PitchC[k], - 0.0, + 0, &v->MacroTileWidthC[k], &v->MetaRowBytesC, &v->DPTEBytesPerRowC, @@ -4910,8 +4911,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma; v->PTEBufferSizeInRequestsForChroma = 0; v->PDEAndMetaPTEBytesPerFrameC = 0.0; - v->MetaRowBytesC = 0.0; - v->DPTEBytesPerRowC = 0.0; + v->MetaRowBytesC = 0; + v->DPTEBytesPerRowC = 0; v->PrefetchLinesC[i][j][k] = 0.0; v->PTEBufferSizeNotExceededC[i][j][k] = true; } @@ -4924,13 +4925,13 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->SurfaceTiling[k], v->BytePerPixelY[k], v->SourceScan[k], - v->SwathWidthYThisState[k], + (unsigned int)v->SwathWidthYThisState[k], v->ViewportHeight[k], v->GPUVMEnable, v->HostVMEnable, v->HostVMMaxNonCachedPageTableLevels, - v->GPUVMMinPageSize, - v->HostVMMinPageSize, + (unsigned int)v->GPUVMMinPageSize, + (unsigned int)v->HostVMMinPageSize, v->PTEBufferSizeInRequestsForLuma, v->PitchY[k], v->DCCMetaPitchY[k], @@ -5066,9 +5067,9 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->WritebackHRatio[k], v->WritebackVRatio[k], v->WritebackVTaps[k], - v->WritebackDestinationWidth[k], - v->WritebackDestinationHeight[k], - v->WritebackSourceHeight[k], + (int)v->WritebackDestinationWidth[k], + (int)v->WritebackDestinationHeight[k], + (int)v->WritebackSourceHeight[k], v->HTotal[k]) / v->RequiredDISPCLK[i][j]; } else { v->WritebackDelayTime[k] = 0.0; @@ -5083,9 +5084,9 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->WritebackHRatio[m], v->WritebackVRatio[m], v->WritebackVTaps[m], - v->WritebackDestinationWidth[m], - v->WritebackDestinationHeight[m], - v->WritebackSourceHeight[m], + (int)v->WritebackDestinationWidth[m], + (int)v->WritebackDestinationHeight[m], + (int)v->WritebackSourceHeight[m], v->HTotal[m]) / v->RequiredDISPCLK[i][j]); } } @@ -5116,11 +5117,11 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } } - ReorderingBytes = v->NumberOfChannels + ReorderingBytes = (int)(v->NumberOfChannels * dml_max3( v->UrgentOutOfOrderReturnPerChannelPixelDataOnly, v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - v->UrgentOutOfOrderReturnPerChannelVMDataOnly); + v->UrgentOutOfOrderReturnPerChannelVMDataOnly)); for (i = 0; i < v->soc.num_states; ++i) { for (j = 0; j <= 1; ++j) { @@ -5204,7 +5205,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ double HostVMInefficiencyFactor = 1; int NextPrefetchModeState = MinPrefetchMode; bool UnboundedRequestEnabledThisState = false; - int CompressedBufferSizeInkByteThisState = 0; + unsigned int CompressedBufferSizeInkByteThisState = 0; double dummy; v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j]; @@ -5223,8 +5224,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k]; v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k]; v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k]; - v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k]; - v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k]; + v->DETBufferSizeYThisState[k] = (unsigned int)v->DETBufferSizeYAllStates[i][j][k]; + v->DETBufferSizeCThisState[k] = (unsigned int)v->DETBufferSizeCAllStates[i][j][k]; } VMDataOnlyReturnBWPerState = dml_min( @@ -5238,7 +5239,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ HostVMInefficiencyFactor = v->ReturnBWPerState[i][j] / VMDataOnlyReturnBWPerState; v->ExtraLatency = CalculateExtraLatency( - v->RoundTripPingLatencyCycles, + (int)v->RoundTripPingLatencyCycles, ReorderingBytes, v->DCFCLKState[i][j], v->TotalNumberOfActiveDPP[i][j], @@ -5371,11 +5372,11 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ * v->UrgentBurstFactorChromaPre[k]) + v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]); } - v->TotImmediateFlipBytes = 0.0; + v->TotImmediateFlipBytes = 0; for (k = 0; k < v->NumberOfActivePlanes; k++) { - v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->TotImmediateFlipBytes = (unsigned int)(v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k] - + v->DPTEBytesPerRow[i][j][k]); + + v->DPTEBytesPerRow[i][j][k])); } for (k = 0; k < v->NumberOfActivePlanes; k++) { @@ -5537,30 +5538,37 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } /*Mode Support, Voltage State and SOC Configuration*/ - for (i = v->soc.num_states - 1; i >= 0; i--) { + for (int idx = (int)v->soc.num_states - 1; idx >= 0; idx--) { for (j = 0; j < 2; j++) { - if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true - && v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP - && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false - && v->DTBCLKRequiredMoreThanSupported[i] == false - && v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true - && v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true + if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true + && v->ViewportSizeSupport[idx][j] == true + && v->LinkCapacitySupport[idx] == true && !P2IWith420 + && !DSCOnlyIfNecessaryWithBPP + && !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[idx] == true + && v->NotEnoughDSCUnits[idx] == false + && v->DTBCLKRequiredMoreThanSupported[idx] == false + && v->ROBSupport[idx][j] == true && v->DISPCLK_DPPCLK_Support[idx][j] == true + && v->TotalAvailablePipesSupport[idx][j] == true && EnoughWritebackUnits == true && v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true - && v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false - && v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true - && v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true - && v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false + && v->CursorSupport == true && v->PitchSupport == true + && ViewportExceedsSurface == false + && v->PrefetchSupported[idx][j] == true + && v->DynamicMetadataSupported[idx][j] == true + && v->TotalVerticalActiveBandwidthSupport[idx][j] == true + && v->VRatioInPrefetchSupported[idx][j] == true + && v->PTEBufferSizeNotExceeded[idx][j] == true + && v->NonsupportedDSCInputBPC == false && ((v->HostVMEnable == false && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) - || v->ImmediateFlipSupportedForState[i][j] == true) + || v->ImmediateFlipSupportedForState[idx][j] == true) && FMTBufferExceeded == false) { - v->ModeSupport[i][j] = true; + v->ModeSupport[idx][j] = true; } else { - v->ModeSupport[i][j] = false; + v->ModeSupport[idx][j] = false; } } } - for (i = v->soc.num_states; i >= 0; i--) { + for (int idx = (int)v->soc.num_states; idx >= 0; idx--) { for (j = 0; j < 2; j++) { enum dm_validation_status status = DML_VALIDATION_OK; @@ -5568,7 +5576,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ status = DML_FAIL_SCALE_RATIO_TAP; } else if (!v->SourceFormatPixelAndScanSupport) { status = DML_FAIL_SOURCE_PIXEL_FORMAT; - } else if (!v->ViewportSizeSupport[i][j]) { + } else if (!v->ViewportSizeSupport[idx][j]) { status = DML_FAIL_VIEWPORT_SIZE; } else if (P2IWith420) { status = DML_FAIL_P2I_WITH_420; @@ -5576,15 +5584,15 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ status = DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP; } else if (DSC422NativeNotSupported) { status = DML_FAIL_NOT_DSC422_NATIVE; - } else if (!v->ODMCombine4To1SupportCheckOK[i]) { + } else if (!v->ODMCombine4To1SupportCheckOK[idx]) { status = DML_FAIL_ODM_COMBINE4TO1; - } else if (v->NotEnoughDSCUnits[i]) { + } else if (v->NotEnoughDSCUnits[idx]) { status = DML_FAIL_NOT_ENOUGH_DSC; - } else if (!v->ROBSupport[i][j]) { + } else if (!v->ROBSupport[idx][j]) { status = DML_FAIL_REORDERING_BUFFER; - } else if (!v->DISPCLK_DPPCLK_Support[i][j]) { + } else if (!v->DISPCLK_DPPCLK_Support[idx][j]) { status = DML_FAIL_DISPCLK_DPPCLK; - } else if (!v->TotalAvailablePipesSupport[i][j]) { + } else if (!v->TotalAvailablePipesSupport[idx][j]) { status = DML_FAIL_TOTAL_AVAILABLE_PIPES; } else if (!EnoughWritebackUnits) { status = DML_FAIL_ENOUGH_WRITEBACK_UNITS; @@ -5598,36 +5606,36 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ status = DML_FAIL_PITCH_SUPPORT; } else if (ViewportExceedsSurface) { status = DML_FAIL_VIEWPORT_EXCEEDS_SURFACE; - } else if (!v->PrefetchSupported[i][j]) { + } else if (!v->PrefetchSupported[idx][j]) { status = DML_FAIL_PREFETCH_SUPPORT; - } else if (!v->DynamicMetadataSupported[i][j]) { + } else if (!v->DynamicMetadataSupported[idx][j]) { status = DML_FAIL_DYNAMIC_METADATA; - } else if (!v->TotalVerticalActiveBandwidthSupport[i][j]) { + } else if (!v->TotalVerticalActiveBandwidthSupport[idx][j]) { status = DML_FAIL_TOTAL_V_ACTIVE_BW; - } else if (!v->VRatioInPrefetchSupported[i][j]) { + } else if (!v->VRatioInPrefetchSupported[idx][j]) { status = DML_FAIL_V_RATIO_PREFETCH; - } else if (!v->PTEBufferSizeNotExceeded[i][j]) { + } else if (!v->PTEBufferSizeNotExceeded[idx][j]) { status = DML_FAIL_PTE_BUFFER_SIZE; } else if (v->NonsupportedDSCInputBPC) { status = DML_FAIL_DSC_INPUT_BPC; } else if ((v->HostVMEnable - && !v->ImmediateFlipSupportedForState[i][j])) { + && !v->ImmediateFlipSupportedForState[idx][j])) { status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP; } else if (FMTBufferExceeded) { status = DML_FAIL_FMT_BUFFER_EXCEEDED; } - mode_lib->vba.ValidationStatus[i] = status; + mode_lib->vba.ValidationStatus[idx] = status; } } { unsigned int MaximumMPCCombine = 0; - - for (i = v->soc.num_states; i >= 0; i--) { - if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) { - v->VoltageLevel = i; - v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true; - if (v->ModeSupport[i][0] == true) { + for (int idx = (int)v->soc.num_states; idx >= 0; idx--) { + if (idx == (int)v->soc.num_states || v->ModeSupport[idx][0] == true + || v->ModeSupport[idx][1] == true) { + v->VoltageLevel = idx; + v->ModeIsSupported = v->ModeSupport[idx][0] == true || v->ModeSupport[idx][1] == true; + if (v->ModeSupport[idx][0] == true) { MaximumMPCCombine = 0; } else { MaximumMPCCombine = 1; @@ -5635,7 +5643,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } } v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine]; - for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { + for (k = 0; k < v->NumberOfActivePlanes; k++) { v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k]; v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k]; } @@ -5693,7 +5701,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank; double WritebackDRAMClockChangeLatencyHiding; double TotalPixelBW = 0.0; - int k, j; + unsigned int k, j; v->UrgentWatermark = UrgentLatency + ExtraLatency; @@ -5738,13 +5746,13 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( for (k = 0; k < v->NumberOfActivePlanes; ++k) { double EffectiveDETBufferSizeY = DETBufferSizeY[k]; - v->LBLatencyHidingSourceLinesY = dml_min( + v->LBLatencyHidingSourceLinesY = (unsigned int)(dml_min( (double) v->MaxLineBufferLines, - dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); + dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1)); - v->LBLatencyHidingSourceLinesC = dml_min( + v->LBLatencyHidingSourceLinesC = (unsigned int)(dml_min( (double) v->MaxLineBufferLines, - dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); + dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1)); EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]); @@ -5756,11 +5764,11 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( } LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; - LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + LinesInDETYRoundedDownToSwath[k] = (unsigned int)dml_floor(LinesInDETY[k], SwathHeightY[k]); FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; if (BytePerPixelDETC[k] > 0) { LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; - LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); + LinesInDETCRoundedDownToSwath = (unsigned int)dml_floor(LinesInDETC, SwathHeightC[k]); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k]; } else { LinesInDETC = 0; @@ -5859,8 +5867,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -5881,7 +5889,7 @@ static void CalculateDCFCLKDeepSleep( double DisplayPipeLineDeliveryTimeLuma; double DisplayPipeLineDeliveryTimeChroma; double ReadBandwidth = 0.0; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { @@ -6011,7 +6019,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], @@ -6032,7 +6040,7 @@ static void CalculatePixelDeliveryTimes( double CursorRequestDeliveryTimePrefetch[]) { double req_per_swath_ub; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { if (VRatio[k] <= 1) { @@ -6107,7 +6115,7 @@ static void CalculatePixelDeliveryTimes( for (k = 0; k < NumberOfActivePlanes; ++k) { int cursor_req_per_width; - cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); + cursor_req_per_width = (int)dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1); if (NumberOfCursors[k] > 0) { if (VRatio[k] <= 1) { CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width; @@ -6132,39 +6140,39 @@ static void CalculatePixelDeliveryTimes( } static void CalculateMetaAndPTETimes( - int NumberOfActivePlanes, + unsigned int NumberOfActivePlanes, bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -6198,7 +6206,7 @@ static void CalculateMetaAndPTETimes( unsigned int dpte_groups_per_row_luma_ub; unsigned int dpte_group_width_chroma; unsigned int dpte_groups_per_row_chroma_ub; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k]; @@ -6241,7 +6249,7 @@ static void CalculateMetaAndPTETimes( } else { meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; - meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma; + meta_chunk_per_row_int_chroma = (unsigned int)((double) meta_row_width_chroma[k] / meta_chunk_width_chroma); meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma; if (SourceScan[k] != dm_vert) { meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k]; @@ -6274,7 +6282,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k]; } - dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1); time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; @@ -6288,7 +6296,7 @@ static void CalculateMetaAndPTETimes( } else { dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k]; } - dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1); time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub; @@ -6309,18 +6317,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -6330,34 +6338,34 @@ static void CalculateVMGroupAndRequestTimes( (void)dpte_row_width_chroma_ub; int num_group_per_lower_vm_stage; int num_req_per_lower_vm_stage; - int k; + unsigned int k; for (k = 0; k < NumberOfActivePlanes; ++k) { if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { if (DCCEnable[k] == false) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (GPUVMMaxPageTableLevels == 1) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); } } else { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + num_group_per_lower_vm_stage = (int)(2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) - + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); + num_group_per_lower_vm_stage = (int)(1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)); } } } @@ -6428,29 +6436,29 @@ static void CalculateStutterEfficiency( bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -6668,8 +6676,8 @@ static void CalculateStutterEfficiency( #endif *StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100; *Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100; - *NumberOfStutterBurstsPerFrame = (*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); - *Z8NumberOfStutterBurstsPerFrame = (*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); + *NumberOfStutterBurstsPerFrame = (int)(*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); + *Z8NumberOfStutterBurstsPerFrame = (int)(*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0); } else { *StutterEfficiencyNotIncludingVBlank = 0.; *Z8StutterEfficiencyNotIncludingVBlank = 0.; @@ -6734,48 +6742,48 @@ static void CalculateSwathAndDETConfiguration( enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], bool *ViewportSizeSupport) { (void)HRatioChroma; - int MaximumSwathHeightY[DC__NUM_DPP__MAX]; - int MaximumSwathHeightC[DC__NUM_DPP__MAX]; + unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX]; + unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX]; int MinimumSwathHeightY; int MinimumSwathHeightC; - int RoundedUpMaxSwathSizeBytesY; - int RoundedUpMaxSwathSizeBytesC; - int RoundedUpMinSwathSizeBytesY; - int RoundedUpMinSwathSizeBytesC; - int RoundedUpSwathSizeBytesY; - int RoundedUpSwathSizeBytesC; + unsigned int RoundedUpMaxSwathSizeBytesY; + unsigned int RoundedUpMaxSwathSizeBytesC; + unsigned int RoundedUpMinSwathSizeBytesY; + unsigned int RoundedUpMinSwathSizeBytesC; + unsigned int RoundedUpSwathSizeBytesY; + unsigned int RoundedUpSwathSizeBytesC; double SwathWidthSingleDPP[DC__NUM_DPP__MAX]; double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX]; int k; @@ -6845,17 +6853,17 @@ static void CalculateSwathAndDETConfiguration( } } - RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]; - RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY; + RoundedUpMaxSwathSizeBytesY = (int)(swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]); + RoundedUpMinSwathSizeBytesY = (int)(swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesY = dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); - RoundedUpMinSwathSizeBytesY = dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); + RoundedUpMaxSwathSizeBytesY = (int)dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256); + RoundedUpMinSwathSizeBytesY = (int)dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256); } - RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]; - RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC; + RoundedUpMaxSwathSizeBytesC = (int)(swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]); + RoundedUpMinSwathSizeBytesC = (int)(swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC); if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesC = dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); - RoundedUpMinSwathSizeBytesC = dml_ceil(RoundedUpMinSwathSizeBytesC, 256); + RoundedUpMaxSwathSizeBytesC = (int)dml_ceil(RoundedUpMaxSwathSizeBytesC, 256); + RoundedUpMinSwathSizeBytesC = (int)dml_ceil(RoundedUpMinSwathSizeBytesC, 256); } if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) { @@ -6885,14 +6893,14 @@ static void CalculateSwathAndDETConfiguration( double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); if (SwathHeightC[k] == 0) { - DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024; + DETBufferSizeY[k] = (unsigned int)(actDETBufferSizeInKByte * 1024); DETBufferSizeC[k] = 0; } else if (RoundedUpSwathSizeBytesY <= 1.5 * RoundedUpSwathSizeBytesC) { - DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2; - DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2; + DETBufferSizeY[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 2); + DETBufferSizeC[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 2); } else { - DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024); - DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3; + DETBufferSizeY[k] = (unsigned int)dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024); + DETBufferSizeC[k] = (unsigned int)(actDETBufferSizeInKByte * 1024 / 3); } if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k] @@ -6911,31 +6919,31 @@ static void CalculateSwathWidth( int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], - int HActive[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], + unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[]) + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[]) { (void)BytePerPixY; enum odm_combine_mode MainPlaneODMCombine; @@ -6991,8 +6999,8 @@ static void CalculateSwathWidth( SwathWidthC[k] = SwathWidthSingleDPPC[k]; } { - int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); - int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); + int surface_width_ub_l = (int)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); + int surface_height_ub_l = (int)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l); @@ -7001,11 +7009,11 @@ static void CalculateSwathWidth( if (SourceScan[k] != dm_vert) { MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k]; MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k]; - swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); + swath_width_luma_ub[k] = (int)dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); if (BytePerPixC[k] > 0) { - int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); + int surface_width_ub_c = (int)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); - swath_width_chroma_ub[k] = dml_min( + swath_width_chroma_ub[k] = (int)dml_min( surface_width_ub_c, (int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]); } else { @@ -7014,11 +7022,11 @@ static void CalculateSwathWidth( } else { MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k]; MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k]; - swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); + swath_width_luma_ub[k] = (int)dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); if (BytePerPixC[k] > 0) { - int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); + int surface_height_ub_c = (int)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); - swath_width_chroma_ub[k] = dml_min( + swath_width_chroma_ub[k] = (int)dml_min( surface_height_ub_c, (int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]); } else { @@ -7041,8 +7049,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) @@ -7087,8 +7095,8 @@ static double CalculateExtraLatencyBytes( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) @@ -7100,9 +7108,9 @@ static double CalculateExtraLatencyBytes( if (HostVMMinPageSize < 2048) HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); else - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } else { HostVMDynamicLevels = 0; } @@ -7139,7 +7147,8 @@ static noinline_for_stack void UseMinimumDCFCLK( int ReorderingBytes) { struct vba_vars_st *v = &mode_lib->vba; - int dummy1, i, j, k; + unsigned int dummy1, j; + unsigned int i, k; double NormalEfficiency, dummy2, dummy3; double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; @@ -7157,7 +7166,7 @@ static noinline_for_stack void UseMinimumDCFCLK( double ExtraLatencyBytes; double ExtraLatencyCycles; double DCFCLKRequiredForPeakBandwidth; - int NoOfDPPState[DC__NUM_DPP__MAX]; + unsigned int NoOfDPPState[DC__NUM_DPP__MAX]; double MinimumTvmPlus2Tr0; TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; @@ -7166,7 +7175,7 @@ static noinline_for_stack void UseMinimumDCFCLK( + v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]); } - for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) + for (k = 0; k < v->NumberOfActivePlanes; ++k) NoOfDPPState[k] = v->NoOfDPP[i][j][k]; MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime); @@ -7269,7 +7278,7 @@ static noinline_for_stack void UseMinimumDCFCLK( } } DCFCLKRequiredForPeakBandwidth = 0; - for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) + for (k = 0; k < v->NumberOfActivePlanes; ++k) DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k]; MinimumTvmPlus2Tr0 = v->UrgLatency[i] @@ -7305,12 +7314,12 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( int CompressedBufferSegmentSizeInkByteFinal, enum output_encoder_class *Output, bool *UnboundedRequestEnabled, - int *CompressedBufferSizeInkByte) + unsigned int *CompressedBufferSizeInkByte) { double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); *UnboundedRequestEnabled = UnboundedRequest(UseUnboundedRequestingFinal, TotalActiveDPP, NoChromaPlanes, Output[0]); - *CompressedBufferSizeInkByte = ( + *CompressedBufferSizeInkByte = (int)( *UnboundedRequestEnabled == true ? ConfigReturnBufferSizeInKByte - TotalActiveDPP * actDETBufferSizeInKByte : ConfigReturnBufferSizeInKByte - MaxNumDPP * actDETBufferSizeInKByte); @@ -7352,15 +7361,15 @@ static unsigned int CalculateMaxVStartup( unsigned int vblank_size = 0; double line_time_us = HTotal / PixelClock; unsigned int vblank_actual = VTotal - VActive; - unsigned int vblank_nom_default_in_line = dml_floor(VBlankNomDefaultUS / line_time_us, 1.0); + unsigned int vblank_nom_default_in_line = (unsigned int)dml_floor(VBlankNomDefaultUS / line_time_us, 1.0); unsigned int vblank_nom_input = VBlankNom; //dml_min(VBlankNom, vblank_nom_default_in_line); unsigned int vblank_avail = vblank_nom_input == 0 ? vblank_nom_default_in_line : vblank_nom_input; vblank_size = (unsigned int) dml_min(vblank_actual, vblank_avail); if (Interlace && !ProgressiveTointerlaceUnitinOPP) - MaxVStartup = dml_floor(vblank_size / 2.0, 1.0); + MaxVStartup = (unsigned int)dml_floor(vblank_size / 2.0, 1.0); else - MaxVStartup = vblank_size - dml_max(1.0, dml_ceil(WritebackDelayTime / line_time_us, 1.0)); + MaxVStartup = (unsigned int)(vblank_size - dml_max(1.0, dml_ceil(WritebackDelayTime / line_time_us, 1.0))); if (MaxVStartup > 1023) MaxVStartup = 1023; return MaxVStartup; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c index 40a916c2a9c6..ec745c2d6c81 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c @@ -205,11 +205,11 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_s extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3); if (rq_param->yuv420) { extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3); } rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); @@ -229,12 +229,12 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_s // Note: detile_buf_plane1_addr is in unit of 1KB if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr); #endif } else { - detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0; // 2/3 to luma + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0); // 2/3 to luma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/3 chroma)\n", __func__, detile_buf_plane1_addr); #endif @@ -277,8 +277,8 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_p #endif if (rq_param->yuv420_10bpc) { - full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; - full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256; + full_swath_bytes_packed_l = (unsigned int)(dml_round_to_multiple((unsigned int)(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256); + full_swath_bytes_packed_c = (unsigned int)(dml_round_to_multiple((unsigned int)(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0), 256, 1) + 256); #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_l); dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_c); @@ -509,7 +509,7 @@ static void get_meta_and_pte_attr( // "/2" is like square root // blk is vertical biased if (tiling != dm_sw_linear) - log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + log2_blk_height = (unsigned int)(log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1)); else log2_blk_height = 0; // blk height of 1 @@ -662,7 +662,7 @@ static void get_meta_and_pte_attr( if (surf_linear) { unsigned int dpte_row_height; - log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); + log2_dpte_row_height_linear = (unsigned int)dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma); dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs); @@ -728,7 +728,7 @@ static void get_meta_and_pte_attr( // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, // the upper bound for the dpte groups per row is as follows. - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); } static void get_surf_rq_param( @@ -753,7 +753,7 @@ static void get_surf_rq_param( vp_height = pipe_param->src.viewport_height_c; data_pitch = pipe_param->src.data_pitch_c; meta_pitch = pipe_param->src.meta_pitch_c; - surface_height = pipe_param->src.surface_height_y / 2.0; + surface_height = (unsigned int)(pipe_param->src.surface_height_y / 2.0); } else { vp_width = pipe_param->src.viewport_width / ppe; vp_height = pipe_param->src.viewport_height; @@ -771,18 +771,18 @@ static void get_surf_rq_param( access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine * 2); if (is_chroma) { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm); } else { - full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; - src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm; + full_src_vp_width = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width); + src_hactive_odm = (unsigned int)(pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm); } if (access_dir == 0) { - vp_width = dml_min(full_src_vp_width, src_hactive_odm); + vp_width = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); } else { - vp_height = dml_min(full_src_vp_width, src_hactive_odm); + vp_height = (unsigned int)dml_min(full_src_vp_width, src_hactive_odm); dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); } @@ -901,7 +901,7 @@ static void calculate_ttu_cursor( cur_req_size = 256; } - cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); + cur_req_width = (unsigned int)((double) cur_req_size / ((double) cur_bit_per_pixel / 8.0)); cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width; cur_req_per_width = cur_width_ub / (double) cur_req_width; hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor @@ -1042,7 +1042,7 @@ static void dml_rq_dlg_get_dlg_params( double refcyc_per_req_delivery_cur0; double refcyc_per_req_delivery_pre_cur1; double refcyc_per_req_delivery_cur1; - unsigned int vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA + unsigned int vba__min_dst_y_next_start = (unsigned int)get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA unsigned int vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA @@ -1075,7 +1075,7 @@ static void dml_rq_dlg_get_dlg_params( dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; disp_dlg_regs->min_dst_y_next_start_us = (vba__min_dst_y_next_start * dst->hactive) / (unsigned int) dst->pixel_rate_mhz; - disp_dlg_regs->min_dst_y_next_start = vba__min_dst_y_next_start * dml_pow(2, 2); + disp_dlg_regs->min_dst_y_next_start = (unsigned int)(vba__min_dst_y_next_start * dml_pow(2, 2)); ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); @@ -1138,8 +1138,8 @@ static void dml_rq_dlg_get_dlg_params( if (interlaced) vstartup_start = vstartup_start / 2; - dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA - dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_x_after_scaler = (unsigned int)get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dst_y_after_scaler = (unsigned int)get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA // do some adjustment on the dst_after scaler to account for odm combine mode dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); @@ -1366,9 +1366,9 @@ static void dml_rq_dlg_get_dlg_params( } if (src->dynamic_metadata_enable && src->gpuvm) - disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + disp_dlg_regs->refcyc_per_vm_dmdata = (unsigned int)(get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA - disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + disp_dlg_regs->dmdata_dl_delta = (unsigned int)(get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA // TTU - Luma / Chroma if (access_dir) { // vertical access @@ -1474,8 +1474,8 @@ static void dml_rq_dlg_get_dlg_params( src->cur0_src_width, (enum cursor_bpp) (src->cur0_bpp)); - vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA + vba__refcyc_per_req_delivery_pre_cur0 = (float)(get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + vba__refcyc_per_req_delivery_cur0 = (float)(get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0); dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_cur0); @@ -1495,7 +1495,7 @@ static void dml_rq_dlg_get_dlg_params( // Assignment to register structures disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line ASSERT(disp_dlg_regs->dst_y_after_scaler < 8); - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); @@ -1532,23 +1532,23 @@ static void dml_rq_dlg_get_dlg_params( disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; } - disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA - disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA // Clamp to max for now if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2)); ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); @@ -1572,23 +1572,23 @@ static void dml_rq_dlg_get_dlg_params( disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); // TODO: Is this the right calculation? Does htotal need to be halved? disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_c); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); @@ -1629,7 +1629,7 @@ static void dml_rq_dlg_get_dlg_params( disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); @@ -1660,7 +1660,7 @@ void dml314_rq_dlg_get_dlg_reg( dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes); - dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); + dlg_sys_param.total_flip_bytes = (unsigned int)get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes); print__dlg_sys_params_st(mode_lib, &dlg_sys_param); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index eb199215d298..1b1ab6a6d53a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -191,21 +191,24 @@ void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr) double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; /* For min clocks use as reported by PM FW and report those as min */ - uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; - uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; + uint16_t min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; + uint16_t min_dcfclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; uint16_t setb_min_uclk_mhz = min_uclk_mhz; - uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; + uint16_t dcfclk_mhz_for_the_second_state = + (uint16_t)clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; dc_assert_fp_enabled(); /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */ - if (dcfclk_mhz_for_the_second_state) - clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; - else - clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; + if (dcfclk_mhz_for_the_second_state) { + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = + (uint16_t)dcfclk_mhz_for_the_second_state; + } else + clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = + (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) - setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; + setb_min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; /* Set A - Normal - default values */ clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; @@ -297,7 +300,7 @@ int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, dcn32_subvp_in_use(dc, context)) vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; - if (vlevel < context->bw_ctx.dml.vba.soc.num_states && + if (vlevel < (int)context->bw_ctx.dml.vba.soc.num_states && vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) break; @@ -347,13 +350,13 @@ void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, if (pipe->plane_state && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { pipes[pipe_idx].pipe.dest.vstartup_start = - get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + (unsigned int)get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipes[pipe_idx].pipe.dest.vupdate_offset = - get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + (unsigned int)get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipes[pipe_idx].pipe.dest.vupdate_width = - get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + (unsigned int)get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipes[pipe_idx].pipe.dest.vready_offset = - get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + (unsigned int)get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; } pipe_idx++; @@ -367,18 +370,18 @@ static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st * float sdp_bw_kbytes_sec; float limiting_bw_kbytes_sec; - memory_bw_kbytes_sec = entry->dram_speed_mts * + memory_bw_kbytes_sec = (float)(entry->dram_speed_mts * dcn3_2_soc.num_chans * dcn3_2_soc.dram_channel_width_bytes * - ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); + ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); - fabric_bw_kbytes_sec = entry->fabricclk_mhz * + fabric_bw_kbytes_sec = (float)(entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * - ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); + ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); - sdp_bw_kbytes_sec = entry->dcfclk_mhz * + sdp_bw_kbytes_sec = (float)(entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * - ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); + ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); limiting_bw_kbytes_sec = memory_bw_kbytes_sec; @@ -394,23 +397,23 @@ static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st * static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) { if (entry->dcfclk_mhz > 0) { - float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); + float bw_on_sdp = (float)(entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); - entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); - entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans * - dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); + entry->fabricclk_mhz = (float)(bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100))); + entry->dram_speed_mts = (float)(bw_on_sdp / (dcn3_2_soc.num_chans * + dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100))); } else if (entry->fabricclk_mhz > 0) { - float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); + float bw_on_fabric = (float)(entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); - entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); - entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans * - dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); + entry->dcfclk_mhz = (float)(bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100))); + entry->dram_speed_mts = (float)(bw_on_fabric / (dcn3_2_soc.num_chans * + dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100))); } else if (entry->dram_speed_mts > 0) { - float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans * - dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); + float bw_on_dram = (float)(entry->dram_speed_mts * dcn3_2_soc.num_chans * + dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); - entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); - entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); + entry->fabricclk_mhz = (float)(bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100))); + entry->dcfclk_mhz = (float)(bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100))); } } @@ -418,8 +421,8 @@ static void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *t unsigned int *num_entries, struct _vcs_dpi_voltage_scaling_st *entry) { - int i = 0; - int index = 0; + unsigned int i = 0; + unsigned int index = 0; dc_assert_fp_enabled(); @@ -476,8 +479,8 @@ void dcn32_set_phantom_stream_timing(struct dc *dc, uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines; unsigned int num_dpp; unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; - unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; - unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; + unsigned int dcfclk = (unsigned int)context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; + unsigned int socclk = (unsigned int)context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; struct vba_vars_st *vba = &context->bw_ctx.dml.vba; struct dc_stream_state *main_stream = ref_pipe->stream; @@ -497,10 +500,10 @@ void dcn32_set_phantom_stream_timing(struct dc *dc, } // Calculate lines required for pstate allow width and FW processing delays - pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us + + pstate_width_fw_delay_lines = (uint32_t)(((double)(dc->caps.subvp_fw_processing_delay_us + dc->caps.subvp_pstate_allow_width_us) / 1000000) * (ref_pipe->stream->timing.pix_clk_100hz * 100) / - (double)ref_pipe->stream->timing.h_total; + (double)ref_pipe->stream->timing.h_total); // Update clks_cfg for calling into recalculate pipes[0].clks_cfg.voltage = vlevel; @@ -512,8 +515,8 @@ void dcn32_set_phantom_stream_timing(struct dc *dc, /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned * to 2 swaths (i.e. 16 lines) */ - phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) + - pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines; + phantom_vactive = (uint32_t)(get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) + + pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines); // W/A for DCC corruption with certain high resolution timings. // Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive. @@ -524,7 +527,7 @@ void dcn32_set_phantom_stream_timing(struct dc *dc, phantom_vactive += dc->debug.subvp_extra_lines; // For backporch of phantom pipe, use vstartup of the main pipe - phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + phantom_bp = (uint32_t)get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); phantom_stream->dst.y = 0; phantom_stream->dst.height = phantom_vactive; @@ -534,7 +537,7 @@ void dcn32_set_phantom_stream_timing(struct dc *dc, * phantom for this case. */ phantom_stream->src.y = 0; - phantom_stream->src.height = (double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height; + phantom_stream->src.height = (int)((double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height); phantom_stream->timing.v_addressable = phantom_vactive; phantom_stream->timing.v_front_porch = 1; @@ -615,9 +618,9 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, continue; // Round up - refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + + refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 + pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) - / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); + / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total)); /* SubVP pipe candidate requirements: * - Refresh rate < 120hz * - Not able to switch in vactive naturally (switching in active means the @@ -644,8 +647,8 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, pipe = &context->res_ctx.pipe_ctx[i]; if (num_pipes <= free_pipes) { struct dc_stream_state *stream = pipe->stream; - unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / - (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; + unsigned int frame_us = (unsigned int)((stream->timing.v_total * stream->timing.h_total / + (double)(stream->timing.pix_clk_100hz * 100)) * 1000000); if (frame_us > max_frame_time) { *index = i; max_frame_time = frame_us; @@ -747,10 +750,10 @@ static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) phantom->timing.v_addressable; // Round up when calculating microschedule time (+ 1 at the end) - time_us = (microschedule_lines * phantom->timing.h_total) / + time_us = (uint32_t)((microschedule_lines * phantom->timing.h_total) / (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us + - dc->caps.subvp_fw_processing_delay_us + 1; + dc->caps.subvp_fw_processing_delay_us + 1); if (time_us > max_microschedule_us) max_microschedule_us = time_us; @@ -762,19 +765,19 @@ static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) break; } } - vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / - (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / - (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * + vactive1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / + (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000); + vactive2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / + (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000); + vblank1_us = (int32_t)((((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * subvp_pipes[0]->stream->timing.h_total) / - (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * + (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000); + vblank2_us = (int32_t)((((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * subvp_pipes[1]->stream->timing.h_total) / - (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; + (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000); - if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us && - (vactive2_us - vblank1_us) / 2 > max_microschedule_us) + if ((vactive1_us - vblank2_us) / 2 > (int32_t)max_microschedule_us && + (vactive2_us - vblank1_us) / 2 > (int32_t)max_microschedule_us) return true; return false; @@ -852,19 +855,19 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context) main_timing = &pipe->stream->timing; phantom_timing = &phantom_stream->timing; drr_timing = &drr_pipe->stream->timing; - prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / + prefetch_us = (uint16_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + - dc->caps.subvp_prefetch_end_to_mall_start_us; - subvp_active_us = main_timing->v_addressable * main_timing->h_total / - (double)(main_timing->pix_clk_100hz * 100) * 1000000; - drr_frame_us = drr_timing->v_total * drr_timing->h_total / - (double)(drr_timing->pix_clk_100hz * 100) * 1000000; + dc->caps.subvp_prefetch_end_to_mall_start_us); + subvp_active_us = (uint16_t)(main_timing->v_addressable * main_timing->h_total / + (double)(main_timing->pix_clk_100hz * 100) * 1000000); + drr_frame_us = (uint16_t)(drr_timing->v_total * drr_timing->h_total / + (double)(drr_timing->pix_clk_100hz * 100) * 1000000); // P-State allow width and FW delays already included phantom_timing->v_addressable - mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / - (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; + mall_region_us = (uint16_t)(phantom_timing->v_addressable * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000); stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; - drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / - (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); + drr_stretched_vblank_us = (uint16_t)((drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / + (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us)); max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; } @@ -901,7 +904,7 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) struct pipe_ctx *subvp_pipe = NULL; bool found = false; bool schedulable = false; - uint32_t i = 0; + uint8_t i = 0; uint8_t vblank_index = 0; uint16_t prefetch_us = 0; uint16_t mall_region_us = 0; @@ -947,18 +950,18 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing; // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe // Also include the prefetch end to mallstart delay time - prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / + prefetch_us = (uint16_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + - dc->caps.subvp_prefetch_end_to_mall_start_us; + dc->caps.subvp_prefetch_end_to_mall_start_us); // P-State allow width and FW delays already included phantom_timing->v_addressable - mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / - (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; - vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / - (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; - vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / - (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; - subvp_active_us = main_timing->v_addressable * main_timing->h_total / - (double)(main_timing->pix_clk_100hz * 100) * 1000000; + mall_region_us = (uint16_t)(phantom_timing->v_addressable * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000); + vblank_frame_us = (uint16_t)(vblank_timing->v_total * vblank_timing->h_total / + (double)(vblank_timing->pix_clk_100hz * 100) * 1000000); + vblank_blank_us = (uint16_t)((vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / + (double)(vblank_timing->pix_clk_100hz * 100) * 1000000); + subvp_active_us = (uint16_t)(main_timing->v_addressable * main_timing->h_total / + (double)(main_timing->pix_clk_100hz * 100) * 1000000); max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, @@ -986,7 +989,7 @@ static bool subvp_subvp_admissable(struct dc *dc, struct dc_state *context) { bool result = false; - uint32_t i; + uint8_t i; uint8_t subvp_count = 0; uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0; uint64_t refresh_rate = 0; @@ -1013,8 +1016,8 @@ static bool subvp_subvp_admissable(struct dc *dc, } if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) || - (min_refresh >= subvp_high_refresh_list.min_refresh && - max_refresh <= subvp_high_refresh_list.max_refresh))) + (min_refresh >= (uint32_t)subvp_high_refresh_list.min_refresh && + max_refresh <= (uint32_t)subvp_high_refresh_list.max_refresh))) result = true; return result; @@ -1092,7 +1095,7 @@ static bool subvp_validate_static_schedulability(struct dc *dc, static void assign_subvp_index(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; int index = 0; for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -1100,7 +1103,7 @@ static void assign_subvp_index(struct dc *dc, struct dc_state *context) if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) { - pipe_ctx->subvp_index = index++; + pipe_ctx->subvp_index = (uint8_t)index++; } else { pipe_ctx->subvp_index = 0; } @@ -1224,7 +1227,8 @@ static bool update_pipe_slice_table_with_split_flags( */ struct pipe_ctx *pipe; bool odm; - int dc_pipe_idx, dml_pipe_idx = 0; + unsigned int dc_pipe_idx; + int dml_pipe_idx = 0; bool updated = false; for (dc_pipe_idx = 0; @@ -1396,7 +1400,7 @@ static void try_odm_power_optimization_and_revalidate( display_e2e_pipe_params_st *pipes, int *split, bool *merge, - unsigned int *vlevel, + int *vlevel, int pipe_cnt) { int i; @@ -1466,7 +1470,7 @@ static bool dcn32_full_validate_bw_helper(struct dc *dc, *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); /* This may adjust vlevel and maxMpcComb */ - if (*vlevel < context->bw_ctx.dml.soc.num_states) { + if (*vlevel < (int)context->bw_ctx.dml.soc.num_states) { *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); vba->VoltageLevel = *vlevel; } @@ -1527,14 +1531,14 @@ static bool dcn32_full_validate_bw_helper(struct dc *dc, /* Check that vlevel requested supports pstate or not * if not, select the lowest vlevel that supports it */ - for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { + for (i = *vlevel; i < (int)context->bw_ctx.dml.soc.num_states; i++) { if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) { *vlevel = i; break; } } - if (*vlevel < context->bw_ctx.dml.soc.num_states + if (*vlevel < (int)context->bw_ctx.dml.soc.num_states && subvp_validate_static_schedulability(dc, context, *vlevel)) found_supported_config = true; if (found_supported_config) { @@ -1566,7 +1570,7 @@ static bool dcn32_full_validate_bw_helper(struct dc *dc, *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); /* This may adjust vlevel and maxMpcComb */ - if (*vlevel < context->bw_ctx.dml.soc.num_states) { + if (*vlevel < (int)context->bw_ctx.dml.soc.num_states) { *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); vba->VoltageLevel = *vlevel; } @@ -1599,7 +1603,7 @@ static bool dcn32_full_validate_bw_helper(struct dc *dc, static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { if (!context->res_ctx.pipe_ctx[i].stream) @@ -1614,7 +1618,8 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) { - int i, pipe_idx, active_hubp_count = 0; + int pipe_idx, active_hubp_count = 0; + unsigned int i; bool usr_retraining_support = false; bool unbounded_req_enabled = false; struct vba_vars_st *vba = &context->bw_ctx.dml.vba; @@ -1624,12 +1629,12 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, /* Writeback MCIF_WB arbitration parameters */ dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); - context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; - context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; - context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; - context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; - context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; - context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; + context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(context->bw_ctx.dml.vba.DISPCLK * 1000); + context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(context->bw_ctx.dml.vba.DCFCLK * 1000); + context->bw_ctx.bw.dcn.clk.socclk_khz = (int)(context->bw_ctx.dml.vba.SOCCLK * 1000); + context->bw_ctx.bw.dcn.clk.dramclk_khz = (int)(context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16); + context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000); + context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(context->bw_ctx.dml.vba.FabricClock * 1000); context->bw_ctx.bw.dcn.clk.p_state_change_support = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != dm_dram_clock_change_unsupported; @@ -1641,7 +1646,7 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); - context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; + context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = (int)(context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000); if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported) context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; else @@ -1650,8 +1655,8 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; ASSERT(usr_retraining_support); - if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) - context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; + if ((unsigned int)context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) + context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)dc->debug.min_disp_clk_khz; unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt); @@ -1670,13 +1675,13 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, continue; if (context->res_ctx.pipe_ctx[i].plane_state) active_hubp_count++; - pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, + pipes[pipe_idx].pipe.dest.vstartup_start = (unsigned int)get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, + pipes[pipe_idx].pipe.dest.vupdate_offset = (unsigned int)get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, + pipes[pipe_idx].pipe.dest.vupdate_width = (unsigned int)get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); - pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, + pipes[pipe_idx].pipe.dest.vready_offset = (unsigned int)get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) { @@ -1684,20 +1689,20 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; context->res_ctx.pipe_ctx[i].unbounded_req = false; } else { - context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, + context->res_ctx.pipe_ctx[i].det_buffer_size_kb = (int)get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled; } if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) - context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; + context->bw_ctx.bw.dcn.clk.dppclk_khz = (int)(pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000); if (context->res_ctx.pipe_ctx[i].plane_state) - context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; + context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = (int)(pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000); else context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; - context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); + context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = (unsigned int)get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0) context->res_ctx.pipe_ctx[i].has_vactive_margin = true; @@ -1740,10 +1745,10 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, /*save a original dppclock copy*/ context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; - context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz - * 1000; - context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz - * 1000; + context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = (int)(context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz + * 1000); + context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = (int)(context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz + * 1000); context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context); @@ -1779,7 +1784,7 @@ static struct pipe_ctx *dcn32_find_split_pipe( if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[old_index]; - pipe->pipe_idx = old_index; + pipe->pipe_idx = (uint8_t)old_index; } if (!pipe) @@ -1788,7 +1793,7 @@ static struct pipe_ctx *dcn32_find_split_pipe( && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { if (context->res_ctx.pipe_ctx[i].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[i]; - pipe->pipe_idx = i; + pipe->pipe_idx = (uint8_t)i; break; } } @@ -1803,7 +1808,7 @@ static struct pipe_ctx *dcn32_find_split_pipe( for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { if (context->res_ctx.pipe_ctx[i].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[i]; - pipe->pipe_idx = i; + pipe->pipe_idx = (uint8_t)i; break; } } @@ -1846,13 +1851,13 @@ static bool dcn32_split_stream_for_mpc_or_odm( *sec_pipe = *pri_pipe; - sec_pipe->pipe_idx = pipe_idx; + sec_pipe->pipe_idx = (uint8_t)pipe_idx; sec_pipe->plane_res.mi = pool->mis[pipe_idx]; sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; - sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; + sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; sec_pipe->stream_res.dsc = NULL; if (odm) { if (pri_pipe->next_odm_pipe) { @@ -1904,7 +1909,8 @@ static bool dcn32_apply_merge_split_flags_helper( int *split, bool *merge) { - int i, pipe_idx; + int pipe_idx; + unsigned int i; bool newly_split[MAX_PIPES] = { false }; struct vba_vars_st *vba = &context->bw_ctx.dml.vba; @@ -2165,7 +2171,7 @@ bool dcn32_internal_validate_bw(struct dc *dc, context->bw_ctx.dml.validate_max_state = false; - if (vlevel < context->bw_ctx.dml.soc.num_states) { + if (vlevel < (int)context->bw_ctx.dml.soc.num_states) { memset(split, 0, sizeof(split)); memset(merge, 0, sizeof(merge)); vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); @@ -2179,7 +2185,7 @@ bool dcn32_internal_validate_bw(struct dc *dc, if (vlevel == context->bw_ctx.dml.soc.num_states) goto validate_fail; - for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0, pipe_idx = 0; i < (int)dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; @@ -2210,7 +2216,7 @@ bool dcn32_internal_validate_bw(struct dc *dc, if (repopulate_pipes) { int flag_max_mpc_comb = vba->maxMpcComb; int flag_vlevel = vlevel; - int i; + int j; pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); if (!dc->config.enable_windowed_mpo_odm) @@ -2225,19 +2231,20 @@ bool dcn32_internal_validate_bw(struct dc *dc, dm_prefetch_support_uclk_fclk_and_stutter_if_possible; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); + const int num_states = (int)context->bw_ctx.dml.soc.num_states; - if (vlevel == context->bw_ctx.dml.soc.num_states) { + if (vlevel == num_states) { /* failed after DET size changes */ goto validate_fail; } else if (flag_max_mpc_comb == 0 && flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) { /* check the context constructed with pipe split flags is still valid*/ bool flags_valid = false; - for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { - if (vba->ModeSupport[i][flag_max_mpc_comb]) { + for (j = flag_vlevel; j < (int)context->bw_ctx.dml.soc.num_states; j++) { + if (vba->ModeSupport[j][flag_max_mpc_comb]) { vba->maxMpcComb = flag_max_mpc_comb; - vba->VoltageLevel = i; - vlevel = i; + vba->VoltageLevel = j; + vlevel = j; flags_valid = true; break; } @@ -2267,7 +2274,8 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, int pipe_cnt, int vlevel) { - int i, pipe_idx, vlevel_temp = 0; + int pipe_idx, vlevel_temp = 0; + unsigned int i; double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed; @@ -2276,7 +2284,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, dm_dram_clock_change_unsupported; unsigned int dummy_latency_index = 0; int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; - unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; + unsigned int min_dram_speed_mts = (unsigned int)context->bw_ctx.dml.vba.DRAMSpeed; bool subvp_in_use = dcn32_subvp_in_use(dc, context); unsigned int min_dram_speed_mts_margin; bool need_fclk_lat_as_dummy = false; @@ -2405,16 +2413,16 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; } - context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = (uint32_t)(get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = (uint32_t)(get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); /* Set D: * All clocks min. @@ -2469,7 +2477,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, } if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { - min_dram_speed_mts = dram_speed_from_validation; + min_dram_speed_mts = (unsigned int)dram_speed_from_validation; min_dram_speed_mts_margin = 160; context->bw_ctx.dml.soc.dram_clock_change_latency_us = @@ -2501,20 +2509,20 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; } - context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state. * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM * value. */ - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = (uint32_t)(get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) { /* The only difference between A and C is p-state latency, if p-state is not supported @@ -2526,7 +2534,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported */ - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = (uint32_t)(get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); } else { /* Set A: * All clocks min. @@ -2540,16 +2548,16 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; - context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = (uint32_t)(get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = (uint32_t)(get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = (uint32_t)(get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); + context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = (uint32_t)(get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); } /* Make set D = set A since we do not optimized watermarks for MALL */ @@ -2574,7 +2582,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, pipe_idx++; } - context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; + context->perf_params.stutter_period_us = (unsigned int)context->bw_ctx.dml.vba.StutterPeriod; /* for proper prefetch calculations, if dummy lat > fclk lat, use fclk lat = dummy lat */ if (need_fclk_lat_as_dummy) @@ -2608,18 +2616,18 @@ static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; if (optimal_fclk) - *optimal_fclk = bw_from_dram / - (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_fclk = (unsigned int)(bw_from_dram / + (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100))); if (optimal_dcfclk) - *optimal_dcfclk = bw_from_dram / - (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_dcfclk = (unsigned int)(bw_from_dram / + (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100))); } static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, unsigned int index) { - int i; + unsigned int i; if (*num_entries == 0) return; @@ -2660,13 +2668,13 @@ void dcn32_patch_dpm_table(struct clk_bw_params *bw_params) * 0, will cause it to skip building the clock table. */ if (max_dcfclk_mhz == 0) - bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; + bw_params->clk_table.entries[0].dcfclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dcfclk_mhz; if (max_dispclk_mhz == 0) - bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; + bw_params->clk_table.entries[0].dispclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dispclk_mhz; if (max_dtbclk_mhz == 0) - bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz; + bw_params->clk_table.entries[0].dtbclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dtbclk_mhz; if (max_uclk_mhz == 0) - bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16; + bw_params->clk_table.entries[0].memclk_mhz = (unsigned int)(dcn3_2_soc.clock_limits[0].dram_speed_mts / 16); } static void swap_table_entries(struct _vcs_dpi_voltage_scaling_st *first_entry, @@ -2686,9 +2694,9 @@ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int end_index = 0; unsigned int current_bw = 0; - for (int i = 0; i < (*num_entries - 1); i++) { + for (unsigned int i = 0; i < (*num_entries - 1); i++) { if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { - current_bw = table[i].net_bw_in_kbytes_sec; + current_bw = (unsigned int)table[i].net_bw_in_kbytes_sec; start_index = i; end_index = ++i; @@ -2697,8 +2705,8 @@ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, } if (start_index != end_index) { - for (int j = start_index; j < end_index; j++) { - for (int k = start_index; k < end_index; k++) { + for (unsigned int j = start_index; j < end_index; j++) { + for (unsigned int k = start_index; k < end_index; k++) { if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) swap_table_entries(&table[k], &table[k+1]); } @@ -2717,7 +2725,7 @@ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, */ static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { - for (int i = 0; i < (*num_entries - 1); i++) { + for (unsigned int i = 0; i < (*num_entries - 1); i++) { if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) || (table[i].fabricclk_mhz > table[i+1].fabricclk_mhz)) @@ -2765,7 +2773,8 @@ static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit, static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { - int i, j; + int i; + unsigned int j; struct _vcs_dpi_voltage_scaling_st entry = {0}; struct clk_limit_table_entry max_clk_data = {0}; @@ -2835,12 +2844,12 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz; if (max_clk_data.fclk_mhz == 0) - max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz * + max_clk_data.fclk_mhz = (unsigned int)(max_clk_data.dcfclk_mhz * dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / - dcn3_2_soc.pct_ideal_fabric_bw_after_urgent; + dcn3_2_soc.pct_ideal_fabric_bw_after_urgent); if (max_clk_data.phyclk_mhz == 0) - max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; + max_clk_data.phyclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].phyclk_mhz; *num_entries = 0; entry.dispclk_mhz = max_clk_data.dispclk_mhz; @@ -2852,8 +2861,8 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; // Insert all the DCFCLK STAs - for (i = 0; i < num_dcfclk_stas; i++) { - entry.dcfclk_mhz = dcfclk_sta_targets[i]; + for (j = 0; j < num_dcfclk_stas; j++) { + entry.dcfclk_mhz = dcfclk_sta_targets[j]; entry.fabricclk_mhz = 0; entry.dram_speed_mts = 0; @@ -2872,10 +2881,10 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk insert_entry_into_table_sorted(table, num_entries, &entry); // Insert the UCLK DPMS - for (i = 0; i < num_uclk_dpms; i++) { + for (j = 0; j < num_uclk_dpms; j++) { entry.dcfclk_mhz = 0; entry.fabricclk_mhz = 0; - entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; + entry.dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; get_optimal_ntuple(&entry); entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); @@ -2884,9 +2893,9 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // If FCLK is coarse grained, insert individual DPMs. if (num_fclk_dpms > 2) { - for (i = 0; i < num_fclk_dpms; i++) { + for (j = 0; j < num_fclk_dpms; j++) { entry.dcfclk_mhz = 0; - entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; + entry.fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; entry.dram_speed_mts = 0; get_optimal_ntuple(&entry); @@ -2976,7 +2985,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. i = 0; - while (i < *num_entries - 1) { + while (i < ((int)*num_entries - 1)) { if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && table[i].dram_speed_mts == table[i + 1].dram_speed_mts) @@ -3093,9 +3102,12 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); } - if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) - dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = - dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) { + unsigned int dram_channel_width_bytes = (unsigned int)dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + + dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = dram_channel_width_bytes; + dcn3_2_soc.dram_channel_width_bytes = dram_channel_width_bytes; + } /* DML DSC delay factor workaround */ dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; @@ -3142,13 +3154,13 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa if (min_dcfclk > dcfclk_sta_targets[0]) dcfclk_sta_targets[0] = min_dcfclk; if (!max_dcfclk_mhz) - max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; + max_dcfclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dcfclk_mhz; if (!max_dispclk_mhz) - max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; + max_dispclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dispclk_mhz; if (!max_dppclk_mhz) - max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz; + max_dppclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].dppclk_mhz; if (!max_phyclk_mhz) - max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; + max_phyclk_mhz = (unsigned int)dcn3_2_soc.clock_limits[0].phyclk_mhz; if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array @@ -3365,8 +3377,8 @@ bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe) refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 + (uint64_t)pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1); - refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); - refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total); + refresh_rate = (uint32_t)div_u64(refresh_rate, pipe->stream->timing.v_total); + refresh_rate = (uint32_t)div_u64(refresh_rate, pipe->stream->timing.h_total); if (refresh_rate >= min_refresh && refresh_rate <= max_refresh && dcn32_check_native_scaling_for_res(pipe, width, height)) { @@ -3411,9 +3423,9 @@ bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context if (!pipe_ctx->stream) continue; - refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 + + refresh_rate = (unsigned int)((pipe_ctx->stream->timing.pix_clk_100hz * 100 + pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1) - / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total); + / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total)); if (refresh_rate < min_refresh) min_refresh = refresh_rate; @@ -3421,9 +3433,9 @@ bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream && pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) { - refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + + refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 + pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) - / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); + / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total)); if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) { for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) { uint32_t width = subvp_high_refresh_list.res[i].width; @@ -3543,8 +3555,8 @@ bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, stru /* Every plane (apart from the ones driven by the FPO pipes) needs to have active margin * in order for us to have found a valid "vactive" config for FPO + Vactive */ - blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total / - (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000; + blank_us = (unsigned int)(((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total / + (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000); if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] < vactive_margin_req_us || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed || blank_us >= dc->debug.fpo_vactive_max_blank_us) { vactive_found = false; @@ -3572,7 +3584,7 @@ void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context) if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 && num_mclk_levels > 1) { context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16; - context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; + context->bw_ctx.bw.dcn.clk.dramclk_khz = (int)(context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16); } } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 0782a34689a0..505b5a5f212e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -92,8 +92,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.WritebackHTaps[k], mode_lib->vba.WritebackVTaps[k], mode_lib->vba.WritebackSourceWidth[k], - mode_lib->vba.WritebackDestinationWidth[k], - mode_lib->vba.HTotal[k], mode_lib->vba.WritebackLineBufferSize, + (long)mode_lib->vba.WritebackDestinationWidth[k], + mode_lib->vba.HTotal[k], (unsigned int)mode_lib->vba.WritebackLineBufferSize, mode_lib->vba.DISPCLKDPPCLKVCOSpeed)); } } @@ -305,8 +305,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman .dummy_boolean); /* bool *ViewportSizeSupport */ } - v->CompBufReservedSpaceZs = v->CompBufReservedSpaceKBytes * 1024.0 / 256.0; - v->CompBufReservedSpace64B = v->CompBufReservedSpaceKBytes * 1024.0 / 64.0; + v->CompBufReservedSpaceZs = (unsigned int)(v->CompBufReservedSpaceKBytes * 1024.0 / 256.0); + v->CompBufReservedSpace64B = (unsigned int)(v->CompBufReservedSpaceKBytes * 1024.0 / 64.0); // DCFCLK Deep Sleep dml32_CalculateDCFCLKDeepSleep( @@ -326,7 +326,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.DPPCLK, v->ReadBandwidthSurfaceLuma, v->ReadBandwidthSurfaceChroma, - mode_lib->vba.ReturnBusWidth, + (int)mode_lib->vba.ReturnBusWidth, /* Output */ &v->DCFCLKDeepSleep); @@ -479,7 +479,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.HostVMMaxNonCachedPageTableLevels, mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMMinPageSizeKBytes, - mode_lib->vba.HostVMMinPageSize, + (unsigned int)mode_lib->vba.HostVMMinPageSize, /* Output */ v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean_array2[0], // Boolean PTEBufferSizeNotExceeded[] @@ -528,12 +528,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } - v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes = mode_lib->vba.NumberOfChannels + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes = (unsigned int)(mode_lib->vba.NumberOfChannels * dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly, mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly); + mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly)); - v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.VMDataOnlyReturnBW = dml32_get_return_bw_mbps_vm_only( + v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.VMDataOnlyReturnBW = (unsigned int)dml32_get_return_bw_mbps_vm_only( &mode_lib->vba.soc, mode_lib->vba.VoltageLevel, mode_lib->vba.DCFCLK, @@ -577,7 +577,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman } v->UrgentExtraLatency = dml32_CalculateExtraLatency( - mode_lib->vba.RoundTripPingLatencyCycles, + (int)mode_lib->vba.RoundTripPingLatencyCycles, v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes, mode_lib->vba.DCFCLK, mode_lib->vba.TotalActiveDPP, @@ -591,7 +591,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.DPPPerPlane, v->dpte_group_bytes, v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor, - mode_lib->vba.HostVMMinPageSize, + (unsigned int)mode_lib->vba.HostVMMinPageSize, mode_lib->vba.HostVMMaxNonCachedPageTableLevels); mode_lib->vba.TCalc = 24.0 / v->DCFCLKDeepSleep; @@ -605,9 +605,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.WritebackHRatio[k], mode_lib->vba.WritebackVRatio[k], mode_lib->vba.WritebackVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k], - mode_lib->vba.WritebackDestinationHeight[k], - mode_lib->vba.WritebackSourceHeight[k], + (long)mode_lib->vba.WritebackDestinationWidth[k], + (int)mode_lib->vba.WritebackDestinationHeight[k], + (int)mode_lib->vba.WritebackSourceHeight[k], mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK; } else v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; @@ -622,9 +622,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.WritebackHRatio[j], mode_lib->vba.WritebackVRatio[j], mode_lib->vba.WritebackVTaps[j], - mode_lib->vba.WritebackDestinationWidth[j], - mode_lib->vba.WritebackDestinationHeight[j], - mode_lib->vba.WritebackSourceHeight[j], + (int)mode_lib->vba.WritebackDestinationWidth[j], + (int)mode_lib->vba.WritebackDestinationHeight[j], + (int)mode_lib->vba.WritebackSourceHeight[j], mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK); } } @@ -693,12 +693,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.UseUnboundedRequesting); for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { - v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] && + v->MaxVStartupLines[k] = (unsigned int)(((mode_lib->vba.Interlace[k] && !mode_lib->vba.ProgressiveToInterlaceUnitInOPP) ? dml_floor((mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) / 2.0, 1.0) : mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) - dml_max(1.0, dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k] - / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1)); + / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1))); // Clamp to max OTG vstartup register limit if (v->MaxVStartupLines[k] > 1023) @@ -714,7 +714,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman v->MaximumMaxVStartupLines = 0; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) - v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); + v->MaximumMaxVStartupLines = (unsigned int)dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]); ImmediateFlipRequirementFinal = false; @@ -789,21 +789,21 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman &v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe, v->DSCDelay[k], (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), - dml_min(v->VStartupLines, v->MaxVStartupLines[k]), + (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]), v->MaxVStartupLines[k], v->UrgentLatency, v->UrgentExtraLatency, v->TCalc, - v->PDEAndMetaPTEBytesFrame[k], - v->MetaRowByte[k], - v->PixelPTEBytesPerRow[k], + (unsigned int)v->PDEAndMetaPTEBytesFrame[k], + (unsigned int)v->MetaRowByte[k], + (unsigned int)v->PixelPTEBytesPerRow[k], v->PrefetchSourceLinesY[k], - v->SwathWidthY[k], - v->VInitPreFillY[k], + (unsigned int)v->SwathWidthY[k], + (unsigned int)v->VInitPreFillY[k], v->MaxNumSwathY[k], v->PrefetchSourceLinesC[k], - v->SwathWidthC[k], - v->VInitPreFillC[k], + (unsigned int)v->SwathWidthC[k], + (unsigned int)v->VInitPreFillC[k], v->MaxNumSwathC[k], v->swath_width_luma_ub[k], v->swath_width_chroma_ub[k], @@ -839,7 +839,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman dml_print("DML::%s: k=%0d Prefetch calculation errResult=%0d\n", __func__, k, mode_lib->vba.ErrorResult[k]); #endif - v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); + v->VStartup[k] = (unsigned int)dml_min(v->VStartupLines, v->MaxVStartupLines[k]); } for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { @@ -1019,18 +1019,18 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.TotImmediateFlipBytes = 0; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) { - mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + mode_lib->vba.TotImmediateFlipBytes = (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + mode_lib->vba.DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] - + v->MetaRowByte[k]); + + v->MetaRowByte[k])); if (v->use_one_row_for_frame_flip[k][0][0]) { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes - + 2 * v->PixelPTEBytesPerRow[k]; + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + + 2 * v->PixelPTEBytesPerRow[k]); } else { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes - + v->PixelPTEBytesPerRow[k]; + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + + v->PixelPTEBytesPerRow[k]); } } } @@ -1042,10 +1042,10 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxNonCachedPageTableLevels, mode_lib->vba.GPUVMEnable, - mode_lib->vba.HostVMMinPageSize, - v->PDEAndMetaPTEBytesFrame[k], - v->MetaRowByte[k], - v->PixelPTEBytesPerRow[k], + (unsigned int)mode_lib->vba.HostVMMinPageSize, + (unsigned int)v->PDEAndMetaPTEBytesFrame[k], + (unsigned int)v->MetaRowByte[k], + (unsigned int)v->PixelPTEBytesPerRow[k], mode_lib->vba.BandwidthAvailableForImmediateFlip, mode_lib->vba.TotImmediateFlipBytes, mode_lib->vba.SourcePixelFormat[k], @@ -1439,14 +1439,14 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman isInterlaceTiming = (mode_lib->vba.Interlace[k] && !mode_lib->vba.ProgressiveToInterlaceUnitInOPP); - v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] - + v->MIN_DST_Y_NEXT_START[k] = (unsigned int)(((isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] - mode_lib->vba.VFrontPorch[k]) / 2.0, 1.0) : mode_lib->vba.VTotal[k]) - mode_lib->vba.VFrontPorch[k]) + dml_max(1.0, dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0)) + dml_floor(4.0 * v->TSetup[k] / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), 1.0) / 4.0; + / mode_lib->vba.PixelClock[k]), 1.0) / 4.0); v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]); @@ -1724,7 +1724,8 @@ static void mode_support_configuration(struct vba_vars_st *v, void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) { struct vba_vars_st *v = &mode_lib->vba; - int i, j, start_state; + int i, start_state; + unsigned int j; unsigned int k, m; unsigned int MaximumMPCCombine; unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth; @@ -1931,7 +1932,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 || mode_lib->vba.SourcePixelFormat[k] == dm_420_10 || mode_lib->vba.SourcePixelFormat[k] == dm_420_12) { - v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma / 2.0; + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = (unsigned int)(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma / 2.0); } else { v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma; } @@ -2030,7 +2031,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.MPCCombineMethodIncompatible = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage && v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible; - for (i = start_state; i < v->soc.num_states; i++) { + for (i = start_state; i < (int)v->soc.num_states; i++) { for (j = 0; j < 2; j++) { mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0; mode_lib->vba.TotalAvailablePipesSupport[i][j] = true; @@ -2103,7 +2104,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeNoDSC, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeDSC, mode_lib->vba.DSCEnable[k], - mode_lib->vba.OutputLinkDPLanes[k], + (int)mode_lib->vba.OutputLinkDPLanes[k], mode_lib->vba.OutputLinkDPRate[k], /* Output */ @@ -2237,9 +2238,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackHTaps[k], mode_lib->vba.WritebackVTaps[k], mode_lib->vba.WritebackSourceWidth[k], - mode_lib->vba.WritebackDestinationWidth[k], + (long)mode_lib->vba.WritebackDestinationWidth[k], mode_lib->vba.HTotal[k], - mode_lib->vba.WritebackLineBufferSize, + (unsigned int)mode_lib->vba.WritebackLineBufferSize, mode_lib->vba.DISPCLKDPPCLKVCOSpeed)); } } @@ -2307,7 +2308,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - for (i = start_state; i < v->soc.num_states; ++i) { + for (i = start_state; i < (int)v->soc.num_states; ++i) { mode_lib->vba.ExceededMultistreamSlots[i] = false; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) { @@ -2410,7 +2411,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - for (i = start_state; i < v->soc.num_states; ++i) { + for (i = start_state; i < (int)v->soc.num_states; ++i) { mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { if (mode_lib->vba.BlendingAndTiming[k] == k @@ -2427,7 +2428,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - for (i = start_state; i < v->soc.num_states; ++i) { + for (i = start_state; i < (int)v->soc.num_states; ++i) { mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true; mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true; for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { @@ -2445,7 +2446,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - for (i = start_state; i < v->soc.num_states; i++) { + for (i = start_state; i < (int)v->soc.num_states; i++) { mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false; for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { if (mode_lib->vba.BlendingAndTiming[k] == k) { @@ -2482,7 +2483,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l /* Check DSC Unit and Slices Support */ v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0; - for (i = start_state; i < v->soc.num_states; ++i) { + for (i = start_state; i < (int)v->soc.num_states; ++i) { mode_lib->vba.NotEnoughDSCUnits[i] = false; mode_lib->vba.NotEnoughDSCSlices[i] = false; v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0; @@ -2517,7 +2518,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } /*DSC Delay per state*/ - for (i = start_state; i < v->soc.num_states; ++i) { + for (i = start_state; i < (int)v->soc.num_states; ++i) { for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement( mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k], @@ -2531,7 +2532,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) { - for (j = 0; j <= mode_lib->vba.NumberOfActiveSurfaces - 1; j++) { + for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; j++) { if (mode_lib->vba.BlendingAndTiming[k] == m && mode_lib->vba.RequiresDSC[i][m] == true) { mode_lib->vba.DSCDelayPerState[i][k] = @@ -2622,8 +2623,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.swath_width_luma_ub_this_state[k]; mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k] = mode_lib->vba.swath_width_chroma_ub_this_state[k]; - mode_lib->vba.SwathWidthYAllStates[i][j][k] = mode_lib->vba.SwathWidthYThisState[k]; - mode_lib->vba.SwathWidthCAllStates[i][j][k] = mode_lib->vba.SwathWidthCThisState[k]; + mode_lib->vba.SwathWidthYAllStates[i][j][k] = (unsigned int)mode_lib->vba.SwathWidthYThisState[k]; + mode_lib->vba.SwathWidthCAllStates[i][j][k] = (unsigned int)mode_lib->vba.SwathWidthCThisState[k]; mode_lib->vba.SwathHeightYAllStates[i][j][k] = mode_lib->vba.SwathHeightYThisState[k]; mode_lib->vba.SwathHeightCAllStates[i][j][k] = mode_lib->vba.SwathHeightCThisState[k]; mode_lib->vba.UnboundedRequestEnabledAllStates[i][j] = @@ -2682,7 +2683,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.SurfaceSizeInMALL, &mode_lib->vba.ExceededMALLSize); - for (i = start_state; i < v->soc.num_states; i++) { + for (i = start_state; i < (int)v->soc.num_states; i++) { for (j = 0; j < 2; j++) { for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { mode_lib->vba.swath_width_luma_ub_this_state[k] = @@ -2696,9 +2697,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DETBufferSizeInKByteThisState[k] = mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k]; mode_lib->vba.DETBufferSizeYThisState[k] = - mode_lib->vba.DETBufferSizeYAllStates[i][j][k]; + (unsigned int)mode_lib->vba.DETBufferSizeYAllStates[i][j][k]; mode_lib->vba.DETBufferSizeCThisState[k] = - mode_lib->vba.DETBufferSizeCAllStates[i][j][k]; + (unsigned int)mode_lib->vba.DETBufferSizeCAllStates[i][j][k]; mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k]; mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k]; } @@ -2772,7 +2773,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.HostVMMaxNonCachedPageTableLevels, mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.GPUVMMinPageSizeKBytes, - mode_lib->vba.HostVMMinPageSize, + (unsigned int)mode_lib->vba.HostVMMinPageSize, /* Output */ mode_lib->vba.PTEBufferSizeNotExceededPerState, @@ -2901,7 +2902,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.RequiredDPPCLKThisState, mode_lib->vba.ReadBandwidthLuma, mode_lib->vba.ReadBandwidthChroma, - mode_lib->vba.ReturnBusWidth, + (int)mode_lib->vba.ReturnBusWidth, /* Output */ &mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j]); @@ -2921,9 +2922,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackHRatio[k], mode_lib->vba.WritebackVRatio[k], mode_lib->vba.WritebackVTaps[k], - mode_lib->vba.WritebackDestinationWidth[k], - mode_lib->vba.WritebackDestinationHeight[k], - mode_lib->vba.WritebackSourceHeight[k], + (long)mode_lib->vba.WritebackDestinationWidth[k], + (int)mode_lib->vba.WritebackDestinationHeight[k], + (int)mode_lib->vba.WritebackSourceHeight[k], mode_lib->vba.HTotal[k]) / mode_lib->vba.RequiredDISPCLK[i][j]; } else { @@ -2940,9 +2941,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.WritebackHRatio[m], mode_lib->vba.WritebackVRatio[m], mode_lib->vba.WritebackVTaps[m], - mode_lib->vba.WritebackDestinationWidth[m], - mode_lib->vba.WritebackDestinationHeight[m], - mode_lib->vba.WritebackSourceHeight[m], + (int)mode_lib->vba.WritebackDestinationWidth[m], + (int)mode_lib->vba.WritebackDestinationHeight[m], + (int)mode_lib->vba.WritebackSourceHeight[m], mode_lib->vba.HTotal[m]) / mode_lib->vba.RequiredDISPCLK[i][j]); } @@ -2979,10 +2980,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l } } - v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes = mode_lib->vba.NumberOfChannels + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes = (unsigned int)(mode_lib->vba.NumberOfChannels * dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly, mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData, - mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly); + mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly)); dml32_CalculateMinAndMaxPrefetchMode(mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal, &mode_lib->vba.MinPrefetchMode, @@ -3060,8 +3061,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DRAMClockChangeLatency, mode_lib->vba.FCLKChangeLatency, mode_lib->vba.SREnterPlusExitTime, - mode_lib->vba.ReturnBusWidth, - mode_lib->vba.RoundTripPingLatencyCycles, + (int)mode_lib->vba.ReturnBusWidth, + (int)mode_lib->vba.RoundTripPingLatencyCycles, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes, mode_lib->vba.PixelChunkSizeInKByte, mode_lib->vba.MetaChunkSize, @@ -3069,7 +3070,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.GPUVMMaxPageTableLevels, mode_lib->vba.HostVMEnable, mode_lib->vba.NumberOfActiveSurfaces, - mode_lib->vba.HostVMMinPageSize, + (unsigned int)mode_lib->vba.HostVMMinPageSize, mode_lib->vba.HostVMMaxNonCachedPageTableLevels, mode_lib->vba.DynamicMetadataVMEnabled, mode_lib->vba.ImmediateFlipRequiredFinal, @@ -3187,9 +3188,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DETBufferSizeInKByteThisState[k] = mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k]; mode_lib->vba.DETBufferSizeYThisState[k] = - mode_lib->vba.DETBufferSizeYAllStates[i][j][k]; + (unsigned int)mode_lib->vba.DETBufferSizeYAllStates[i][j][k]; mode_lib->vba.DETBufferSizeCThisState[k] = - mode_lib->vba.DETBufferSizeCAllStates[i][j][k]; + (unsigned int)mode_lib->vba.DETBufferSizeCAllStates[i][j][k]; } mode_lib->vba.VActiveBandwithSupport[i][j] = dml32_CalculateVActiveBandwithSupport( @@ -3236,14 +3237,14 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l / v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.VMDataOnlyReturnBWPerState; mode_lib->vba.ExtraLatency = dml32_CalculateExtraLatency( - mode_lib->vba.RoundTripPingLatencyCycles, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes, + (int)mode_lib->vba.RoundTripPingLatencyCycles, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes, mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.TotalNumberOfActiveDPP[i][j], mode_lib->vba.PixelChunkSizeInKByte, mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j], mode_lib->vba.MetaChunkSize, mode_lib->vba.ReturnBWPerState[i][j], mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable, mode_lib->vba.NumberOfActiveSurfaces, mode_lib->vba.NoOfDPPThisState, mode_lib->vba.dpte_group_bytes, - v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor, mode_lib->vba.HostVMMinPageSize, + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor, (unsigned int)mode_lib->vba.HostVMMinPageSize, mode_lib->vba.HostVMMaxNonCachedPageTableLevels); v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NextPrefetchModeState = mode_lib->vba.MinPrefetchMode; @@ -3295,23 +3296,23 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l k, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor, &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe, - v->DSCDelayPerState[i][k], - v->SwathWidthYThisState[k] / v->HRatio[k], - dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), - v->MaximumVStartup[i][j][k], + (unsigned int)v->DSCDelayPerState[i][k], + (unsigned int)(v->SwathWidthYThisState[k] / v->HRatio[k]), + (unsigned int)dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), + (unsigned int)v->MaximumVStartup[i][j][k], v->UrgLatency[i], v->ExtraLatency, v->TimeCalc, - v->PDEAndMetaPTEBytesPerFrame[i][j][k], - v->MetaRowBytes[i][j][k], - v->DPTEBytesPerRow[i][j][k], + (unsigned int)v->PDEAndMetaPTEBytesPerFrame[i][j][k], + (unsigned int)v->MetaRowBytes[i][j][k], + (unsigned int)v->DPTEBytesPerRow[i][j][k], v->PrefetchLinesY[i][j][k], - v->SwathWidthYThisState[k], - v->PrefillY[k], + (unsigned int)v->SwathWidthYThisState[k], + (unsigned int)v->PrefillY[k], v->MaxNumSwY[k], v->PrefetchLinesC[i][j][k], - v->SwathWidthCThisState[k], - v->PrefillC[k], + (unsigned int)v->SwathWidthCThisState[k], + (unsigned int)v->PrefillC[k], v->MaxNumSwC[k], v->swath_width_luma_ub_this_state[k], v->swath_width_chroma_ub_this_state[k], @@ -3451,23 +3452,23 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.UrgentBurstFactorChromaPre, mode_lib->vba.UrgentBurstFactorCursorPre); - mode_lib->vba.TotImmediateFlipBytes = 0.0; + mode_lib->vba.TotImmediateFlipBytes = 0; for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { if (!(mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_not_required)) { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + mode_lib->vba.NoOfDPP[i][j][k] * mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k] - + mode_lib->vba.MetaRowBytes[i][j][k]; + + mode_lib->vba.MetaRowBytes[i][j][k]); if (mode_lib->vba.use_one_row_for_frame_flip[i][j][k]) { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes + 2 - * mode_lib->vba.DPTEBytesPerRow[i][j][k]; + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + 2 + * mode_lib->vba.DPTEBytesPerRow[i][j][k]); } else { mode_lib->vba.TotImmediateFlipBytes = - mode_lib->vba.TotImmediateFlipBytes - + mode_lib->vba.DPTEBytesPerRow[i][j][k]; + (unsigned int)(mode_lib->vba.TotImmediateFlipBytes + + mode_lib->vba.DPTEBytesPerRow[i][j][k]); } } } @@ -3480,7 +3481,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.HostVMEnable, mode_lib->vba.HostVMMaxNonCachedPageTableLevels, mode_lib->vba.GPUVMEnable, - mode_lib->vba.HostVMMinPageSize, + (unsigned int)mode_lib->vba.HostVMMinPageSize, mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k], mode_lib->vba.MetaRowBytes[i][j][k], mode_lib->vba.DPTEBytesPerRow[i][j][k], @@ -3722,9 +3723,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.DETBufferSizeInKByte[k] = mode_lib->vba.DETBufferSizeInKByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; mode_lib->vba.DETBufferSizeY[k] = - mode_lib->vba.DETBufferSizeYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + (unsigned int)mode_lib->vba.DETBufferSizeYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; mode_lib->vba.DETBufferSizeC[k] = - mode_lib->vba.DETBufferSizeCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; + (unsigned int)mode_lib->vba.DETBufferSizeCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; mode_lib->vba.OutputType[k] = mode_lib->vba.OutputTypePerState[mode_lib->vba.VoltageLevel][k]; mode_lib->vba.OutputRate[k] = mode_lib->vba.OutputRatePerState[mode_lib->vba.VoltageLevel][k]; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index 5e72966a8daf..15f5248340a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -62,7 +62,7 @@ unsigned int dml32_dscceComputeDelay( pixelsPerClock = 1; //initial transmit delay as per PPS - initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); + initalXmitDelay = (unsigned int)dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock); //compute ssm delay if (bpc == 8) @@ -514,8 +514,8 @@ void dml32_CalculateSwathAndDETConfiguration( swath_width_chroma_ub); for (k = 0; k < NumberOfActiveSurfaces; ++k) { - RoundedUpMaxSwathSizeBytesY[k] = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]; - RoundedUpMaxSwathSizeBytesC[k] = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]; + RoundedUpMaxSwathSizeBytesY[k] = (unsigned int)(swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k]); + RoundedUpMaxSwathSizeBytesC[k] = (unsigned int)(swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k]); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%0d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]); dml_print("DML::%s: k=%0d swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]); @@ -531,8 +531,8 @@ void dml32_CalculateSwathAndDETConfiguration( #endif if (SourcePixelFormat[k] == dm_420_10) { - RoundedUpMaxSwathSizeBytesY[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256); - RoundedUpMaxSwathSizeBytesC[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256); + RoundedUpMaxSwathSizeBytesY[k] = (unsigned int)dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256); + RoundedUpMaxSwathSizeBytesC[k] = (unsigned int)dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256); } } @@ -656,7 +656,7 @@ void dml32_CalculateSwathAndDETConfiguration( #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%0d 2/3 DET for plane0, 1/3 for plane1\n", __func__, k); #endif - DETBufferSizeY[k] = dml_floor(DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024); + DETBufferSizeY[k] = (unsigned int)dml_floor(DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024); DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 - DETBufferSizeY[k]; } @@ -786,14 +786,14 @@ void dml32_CalculateSwathWidth( SwathWidthC[k] = SwathWidthdoubleDPPC[k]; } - surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); - surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); + surface_width_ub_l = (unsigned int)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]); + surface_height_ub_l = (unsigned int)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]); if (!IsVertical(SourceRotation[k])) { MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k]; MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k]; if (ViewportStationary[k] && DPPPerSurface[k] == 1) { - swath_width_luma_ub[k] = dml_min(surface_width_ub_l, + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_width_ub_l, dml_floor(ViewportXStart[k] + SwathWidthY[k] + Read256BytesBlockWidthY[k] - 1, @@ -801,22 +801,22 @@ void dml32_CalculateSwathWidth( dml_floor(ViewportXStart[k], Read256BytesBlockWidthY[k])); } else { - swath_width_luma_ub[k] = dml_min(surface_width_ub_l, + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_width_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]); } if (BytePerPixC[k] > 0) { - surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); + surface_width_ub_c = (unsigned int)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]); if (ViewportStationary[k] && DPPPerSurface[k] == 1) { - swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_width_ub_c, dml_floor(ViewportXStartC[k] + SwathWidthC[k] + Read256BytesBlockWidthC[k] - 1, Read256BytesBlockWidthC[k]) - dml_floor(ViewportXStartC[k], Read256BytesBlockWidthC[k])); } else { - swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_width_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]); @@ -829,25 +829,25 @@ void dml32_CalculateSwathWidth( MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k]; if (ViewportStationary[k] && DPPPerSurface[k] == 1) { - swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] + + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] + SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1, Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k])); } else { - swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1, + swath_width_luma_ub[k] = (unsigned int)dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]); } if (BytePerPixC[k] > 0) { - surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); + surface_height_ub_c = (unsigned int)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]); if (ViewportStationary[k] && DPPPerSurface[k] == 1) { - swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_height_ub_c, dml_floor(ViewportYStartC[k] + SwathWidthC[k] + Read256BytesBlockHeightC[k] - 1, Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], Read256BytesBlockHeightC[k])); } else { - swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, + swath_width_chroma_ub[k] = (unsigned int)dml_min(surface_height_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]); } @@ -956,7 +956,7 @@ void dml32_CalculateDETBufferSize( if (DETSizeOverride[0] > 0) { DETBufferSizeInKByte[0] = DETSizeOverride[0]; } else { - DETBufferSizeInKByte[0] = dml_max(nomDETInKByte, dml_ceil(2.0 * + DETBufferSizeInKByte[0] = (unsigned int)dml_max((unsigned int)nomDETInKByte, dml_ceil(2.0 * ((double) RoundedUpMaxSwathSizeBytesY[0] + (double) RoundedUpMaxSwathSizeBytesC[0]) / 1024.0, 64.0)); } @@ -993,7 +993,7 @@ void dml32_CalculateDETBufferSize( #endif if (minDET_pipe == 0) { - minDET_pipe = dml_max(128, dml_ceil(((double)RoundedUpMaxSwathSizeBytesY[k] + + minDET_pipe = (unsigned int)dml_max(128, dml_ceil(((double)RoundedUpMaxSwathSizeBytesY[k] + (double)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, 64)); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%0d minDET_pipe = %d (assume each plane take half DET)\n", @@ -1106,7 +1106,7 @@ void dml32_CalculateDETBufferSize( //dml_print("DML::%s: j=%d, tmp1 = %f\n", __func__, j, tmp1); //dml_print("DML::%s: j=%d, tmp2 = %f\n", __func__, j, tmp2); - NextDETBufferPieceInKByte = dml_min( + NextDETBufferPieceInKByte = (unsigned int)dml_min( dml_round((double) DETBufferSizePoolInKByte * (ReadBandwidthLuma[NextSurfaceToAssignDETPiece] + ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) / @@ -1379,7 +1379,7 @@ void dml32_CalculateOutputLink( *RequiresFEC = false; *OutBpp = dml32_TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, false, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &dummy); //OutputTypeAndRate = "HDMI"; *OutputType = dm_output_type_hdmi; @@ -1407,7 +1407,7 @@ void dml32_CalculateOutputLink( *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && PHYCLKD32PerState < 13500.0 / 32 && DSCEnable == true && ForcedOutputLinkBPP == 0) { @@ -1417,7 +1417,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " UHBR10"; @@ -1429,7 +1429,7 @@ void dml32_CalculateOutputLink( *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == true && @@ -1440,7 +1440,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " UHBR13p5"; @@ -1452,7 +1452,7 @@ void dml32_CalculateOutputLink( *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 20000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) { *RequiresDSC = true; @@ -1461,7 +1461,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " UHBR20"; @@ -1475,7 +1475,7 @@ void dml32_CalculateOutputLink( *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 2700, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == true && ForcedOutputLinkBPP == 0) { @@ -1487,7 +1487,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " HBR"; @@ -1499,7 +1499,7 @@ void dml32_CalculateOutputLink( *OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 5400, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, - DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, + DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == true && @@ -1513,7 +1513,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " HBR2"; @@ -1525,7 +1525,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, - AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, + (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) { @@ -1538,7 +1538,7 @@ void dml32_CalculateOutputLink( OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, - NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout, + NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots); } //OutputTypeAndRate = Output & " HBR3"; @@ -1654,7 +1654,7 @@ double dml32_TruncToValidBPP( MaxLinkBPP = 2 * MaxLinkBPP; } - *RequiredSlots = dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1); + *RequiredSlots = (unsigned int)dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1); if (DesiredBPP == 0) { if (DSCEnable) { @@ -1734,22 +1734,22 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, if (DSCEnabled == true && OutputBpp != 0) { if (ODMMode == dm_odm_combine_mode_4to1) { DSCDelayRequirement_val = 4 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, - dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices / 4, + (unsigned int)dml_ceil(HActive / NumberOfDSCSlices, 1), (unsigned int)(NumberOfDSCSlices / 4), OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output)); } else if (ODMMode == dm_odm_combine_mode_2to1) { DSCDelayRequirement_val = 2 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, - dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices / 2, + (unsigned int)dml_ceil(HActive / NumberOfDSCSlices, 1), (unsigned int)(NumberOfDSCSlices / 2), OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output)); } else { DSCDelayRequirement_val = dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, - dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices, + (unsigned int)dml_ceil(HActive / NumberOfDSCSlices, 1), (unsigned int)NumberOfDSCSlices, OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output); } - DSCDelayRequirement_val = DSCDelayRequirement_val + (HTotal - HActive) * - dml_ceil((double)DSCDelayRequirement_val / HActive, 1); + DSCDelayRequirement_val = (unsigned int)(DSCDelayRequirement_val + (HTotal - HActive) * + dml_ceil((double)DSCDelayRequirement_val / HActive, 1)); - DSCDelayRequirement_val = DSCDelayRequirement_val * PixelClock / PixelClockBackEnd; + DSCDelayRequirement_val = (unsigned int)(DSCDelayRequirement_val * PixelClock / PixelClockBackEnd); } else { DSCDelayRequirement_val = 0; @@ -1765,7 +1765,7 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, dml_print("DML::%s: DSCDelayRequirement_val = %d\n", __func__, DSCDelayRequirement_val); #endif - return dml_ceil(DSCDelayRequirement_val * dsc_delay_factor_wa, 1); + return (unsigned int)dml_ceil(DSCDelayRequirement_val * dsc_delay_factor_wa, 1); } void dml32_CalculateSurfaceSizeInMall( @@ -1811,16 +1811,16 @@ void dml32_CalculateSurfaceSizeInMall( for (k = 0; k < NumberOfActiveSurfaces; ++k) { if (ViewportStationary[k]) { - SurfaceSizeInMALL[k] = dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]), + SurfaceSizeInMALL[k] = (unsigned int)(dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1, ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k], ReadBlockWidthY[k])) * dml_min(dml_ceil(SurfaceHeightY[k], ReadBlockHeightY[k]), dml_floor(ViewportYStartY[k] + ViewportHeightY[k] + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) - - dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) * BytesPerPixelY[k]; + dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) * BytesPerPixelY[k]); if (ReadBlockWidthC[k] > 0) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]), dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) - @@ -1829,10 +1829,10 @@ void dml32_CalculateSurfaceSizeInMall( dml_floor(ViewportYStartC[k] + ViewportHeightC[k] + ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) - dml_floor(ViewportYStartC[k], ReadBlockHeightC[k])) * - BytesPerPixelC[k]; + BytesPerPixelC[k]); } if (DCCEnable[k] == true) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + (dml_min(dml_ceil(DCCMetaPitchY[k], 8 * Read256BytesBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + 8 * Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k]) @@ -1841,9 +1841,9 @@ void dml32_CalculateSurfaceSizeInMall( Read256BytesBlockHeightY[k]), dml_floor(ViewportYStartY[k] + ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1, 8 * Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStartY[k], 8 * - Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256) + (64 * 1024); + Read256BytesBlockHeightY[k])) *BytesPerPixelY[k] / 256) + (64 * 1024)); if (Read256BytesBlockWidthC[k] > 0) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + dml_min(dml_ceil(DCCMetaPitchC[k], 8 * Read256BytesBlockWidthC[k]), dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + 8 @@ -1858,41 +1858,41 @@ void dml32_CalculateSurfaceSizeInMall( Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], 8 * Read256BytesBlockHeightC[k])) * - BytesPerPixelC[k] / 256; + BytesPerPixelC[k] / 256); } } } else { - SurfaceSizeInMALL[k] = dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + + SurfaceSizeInMALL[k] = (unsigned int)(dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) * dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * - BytesPerPixelY[k]; + BytesPerPixelY[k]); if (ReadBlockWidthC[k] > 0) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) * dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) * - BytesPerPixelC[k]; + BytesPerPixelC[k]); } if (DCCEnable[k] == true) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + (dml_ceil(dml_min(DCCMetaPitchY[k], ViewportWidthY[k] + 8 * Read256BytesBlockWidthY[k] - 1), 8 * Read256BytesBlockWidthY[k]) * dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1), 8 * - Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256) + (64 * 1024); + Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256) + (64 * 1024)); if (Read256BytesBlockWidthC[k] > 0) { - SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] + + SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] + dml_ceil(dml_min(DCCMetaPitchC[k], ViewportWidthC[k] + 8 * Read256BytesBlockWidthC[k] - 1), 8 * Read256BytesBlockWidthC[k]) * dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 * Read256BytesBlockHeightC[k] - 1), 8 * Read256BytesBlockHeightC[k]) * - BytesPerPixelC[k] / 256; + BytesPerPixelC[k] / 256); } } } @@ -2321,51 +2321,51 @@ unsigned int dml32_CalculateVMAndRowBytes( if (HostVMMinPageSize < 2048) HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); else - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } *MetaRequestHeight = 8 * BlockHeight256Bytes; *MetaRequestWidth = 8 * BlockWidth256Bytes; if (SurfaceTiling == dm_sw_linear) { *meta_row_height = 32; - *meta_row_width = dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, *MetaRequestWidth) - - dml_floor(ViewportXStart, *MetaRequestWidth); + *meta_row_width = (unsigned int)(dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, *MetaRequestWidth) + - dml_floor(ViewportXStart, *MetaRequestWidth)); } else if (!IsVertical(SourceRotation)) { *meta_row_height = *MetaRequestHeight; if (ViewportStationary && NumberOfDPPs == 1) { - *meta_row_width = dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, - *MetaRequestWidth) - dml_floor(ViewportXStart, *MetaRequestWidth); + *meta_row_width = (unsigned int)(dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, + *MetaRequestWidth) - dml_floor(ViewportXStart, *MetaRequestWidth)); } else { - *meta_row_width = dml_ceil(SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth; + *meta_row_width = (unsigned int)(dml_ceil(SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth); } - *MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0; + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0); } else { *meta_row_height = *MetaRequestWidth; if (ViewportStationary && NumberOfDPPs == 1) { - *meta_row_width = dml_floor(ViewportYStart + ViewportHeight + *MetaRequestHeight - 1, - *MetaRequestHeight) - dml_floor(ViewportYStart, *MetaRequestHeight); + *meta_row_width = (unsigned int)(dml_floor(ViewportYStart + ViewportHeight + *MetaRequestHeight - 1, + *MetaRequestHeight) - dml_floor(ViewportYStart, *MetaRequestHeight)); } else { - *meta_row_width = dml_ceil(SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight; + *meta_row_width = (unsigned int)(dml_ceil(SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight); } - *MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0; + *MetaRowByte = (unsigned int)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0); } if (ViewportStationary && (NumberOfDPPs == 1 || !IsVertical(SourceRotation))) { - vp_height_meta_ub = dml_floor(ViewportYStart + ViewportHeight + 64 * BlockHeight256Bytes - 1, - 64 * BlockHeight256Bytes) - dml_floor(ViewportYStart, 64 * BlockHeight256Bytes); + vp_height_meta_ub = (unsigned int)(dml_floor(ViewportYStart + ViewportHeight + 64 * BlockHeight256Bytes - 1, + 64 * BlockHeight256Bytes) - dml_floor(ViewportYStart, 64 * BlockHeight256Bytes)); } else if (!IsVertical(SourceRotation)) { - vp_height_meta_ub = dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes; + vp_height_meta_ub = (unsigned int)(dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes); } else { - vp_height_meta_ub = dml_ceil(SwathWidth - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes; + vp_height_meta_ub = (unsigned int)(dml_ceil(SwathWidth - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes); } - DCCMetaSurfaceBytes = DCCMetaPitch * vp_height_meta_ub * BytePerPixel / 256.0; + DCCMetaSurfaceBytes = (unsigned int)(DCCMetaPitch * vp_height_meta_ub * BytePerPixel / 256.0); if (GPUVMEnable == true) { - *MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / - (8 * 4.0 * 1024), 1) + 1) * 64; + *MetaPTEBytesFrame = (unsigned int)((dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / + (8 * 4.0 * 1024), 1) + 1) * 64); MPDEBytesFrame = 128 * (GPUVMMaxPageTableLevels - 1); } else { *MetaPTEBytesFrame = 0; @@ -2382,16 +2382,16 @@ unsigned int dml32_CalculateVMAndRowBytes( if (GPUVMEnable == true && GPUVMMaxPageTableLevels > 1) { if (ViewportStationary && (NumberOfDPPs == 1 || !IsVertical(SourceRotation))) { - vp_height_dpte_ub = dml_floor(ViewportYStart + ViewportHeight + + vp_height_dpte_ub = (unsigned int)(dml_floor(ViewportYStart + ViewportHeight + MacroTileHeight - 1, MacroTileHeight) - - dml_floor(ViewportYStart, MacroTileHeight); + dml_floor(ViewportYStart, MacroTileHeight)); } else if (!IsVertical(SourceRotation)) { - vp_height_dpte_ub = dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight; + vp_height_dpte_ub = (unsigned int)dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight; } else { - vp_height_dpte_ub = dml_ceil(SwathWidth - 1, MacroTileHeight) + MacroTileHeight; + vp_height_dpte_ub = (unsigned int)dml_ceil(SwathWidth - 1, MacroTileHeight) + MacroTileHeight; } - *DPDE0BytesFrame = 64 * (dml_ceil((Pitch * vp_height_dpte_ub * BytePerPixel - MacroTileSizeBytes) / - (8 * 2097152), 1) + 1); + *DPDE0BytesFrame = (unsigned int)(64 * (dml_ceil((Pitch * vp_height_dpte_ub * BytePerPixel - MacroTileSizeBytes) / + (8 * 2097152), 1) + 1)); ExtraDPDEBytesFrame = 128 * (GPUVMMaxPageTableLevels - 2); } else { *DPDE0BytesFrame = 0; @@ -2449,14 +2449,14 @@ unsigned int dml32_CalculateVMAndRowBytes( #endif *dpte_row_height_one_row_per_frame = vp_height_dpte_ub; - *dpte_row_width_ub_one_row_per_frame = (dml_ceil(((double)Pitch * (double)*dpte_row_height_one_row_per_frame / + *dpte_row_width_ub_one_row_per_frame = (unsigned int)((dml_ceil(((double)Pitch * (double)*dpte_row_height_one_row_per_frame / (double) *PixelPTEReqHeight - 1) / (double) *PixelPTEReqWidth, 1) + 1) * - (double) *PixelPTEReqWidth; + (double) *PixelPTEReqWidth); *PixelPTEBytesPerRow_one_row_per_frame = *dpte_row_width_ub_one_row_per_frame / *PixelPTEReqWidth * *PTERequestSize; if (SurfaceTiling == dm_sw_linear) { - *dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * + *dpte_row_height = (unsigned int)dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: dpte_row_height = %d (1)\n", __func__, @@ -2470,9 +2470,9 @@ unsigned int dml32_CalculateVMAndRowBytes( *PixelPTEReqWidth / Pitch), 1)); dml_print("DML::%s: dpte_row_height = %d\n", __func__, *dpte_row_height); #endif - *dpte_row_width_ub = dml_ceil(((double) Pitch * (double) *dpte_row_height - 1), + *dpte_row_width_ub = (unsigned int)dml_ceil(((double) Pitch * (double) *dpte_row_height - 1), (double) *PixelPTEReqWidth) + *PixelPTEReqWidth; - *PixelPTEBytesPerRow = *dpte_row_width_ub / (double)*PixelPTEReqWidth * (double)*PTERequestSize; + *PixelPTEBytesPerRow = (unsigned int)(*dpte_row_width_ub / (double)*PixelPTEReqWidth * (double)*PTERequestSize); // VBA_DELTA, VBA doesn't have programming value for pte row height linear. *dpte_row_height_linear = 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * @@ -2484,27 +2484,27 @@ unsigned int dml32_CalculateVMAndRowBytes( *dpte_row_height = *PixelPTEReqHeight; if (GPUVMMinPageSizeKBytes > 64) { - *dpte_row_width_ub = (dml_ceil((Pitch * *dpte_row_height / *PixelPTEReqHeight - 1) / - *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth; + *dpte_row_width_ub = (unsigned int)((dml_ceil((Pitch * *dpte_row_height / *PixelPTEReqHeight - 1) / + *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth); } else if (ViewportStationary && (NumberOfDPPs == 1)) { - *dpte_row_width_ub = dml_floor(ViewportXStart + SwathWidth + + *dpte_row_width_ub = (unsigned int)(dml_floor(ViewportXStart + SwathWidth + *PixelPTEReqWidth - 1, *PixelPTEReqWidth) - - dml_floor(ViewportXStart, *PixelPTEReqWidth); + dml_floor(ViewportXStart, *PixelPTEReqWidth)); } else { - *dpte_row_width_ub = (dml_ceil((SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * - *PixelPTEReqWidth; + *dpte_row_width_ub = (unsigned int)((dml_ceil((SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * + *PixelPTEReqWidth); } *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize; } else { - *dpte_row_height = dml_min(*PixelPTEReqWidth, MacroTileWidth); + *dpte_row_height = (unsigned int)dml_min(*PixelPTEReqWidth, MacroTileWidth); if (ViewportStationary && (NumberOfDPPs == 1)) { - *dpte_row_width_ub = dml_floor(ViewportYStart + ViewportHeight + *PixelPTEReqHeight - 1, - *PixelPTEReqHeight) - dml_floor(ViewportYStart, *PixelPTEReqHeight); + *dpte_row_width_ub = (unsigned int)(dml_floor(ViewportYStart + ViewportHeight + *PixelPTEReqHeight - 1, + *PixelPTEReqHeight) - dml_floor(ViewportYStart, *PixelPTEReqHeight)); } else { - *dpte_row_width_ub = (dml_ceil((SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) - * *PixelPTEReqHeight; + *dpte_row_width_ub = (unsigned int)((dml_ceil((SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) + * *PixelPTEReqHeight); } *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize; @@ -2584,16 +2584,16 @@ double dml32_CalculatePrefetchSourceLines( } sw0_tmp = SwathHeight - (vp_start_rot % SwathHeight); if (sw0_tmp < *VInitPreFill) - *MaxNumSwath = dml_ceil((*VInitPreFill - sw0_tmp) / SwathHeight, 1) + 1; + *MaxNumSwath = (unsigned int)dml_ceil((*VInitPreFill - sw0_tmp) / SwathHeight, 1) + 1; else *MaxNumSwath = 1; - MaxPartialSwath = dml_max(1, (unsigned int) (vp_start_rot + *VInitPreFill - 1) % SwathHeight); + MaxPartialSwath = (unsigned int)dml_max(1, (unsigned int) (vp_start_rot + *VInitPreFill - 1) % SwathHeight); } else { - *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1; + *MaxNumSwath = (unsigned int)dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1; if (*VInitPreFill > 1) - MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill - 2) % SwathHeight); + MaxPartialSwath = (unsigned int)dml_max(1, (unsigned int) (*VInitPreFill - 2) % SwathHeight); else - MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight); + MaxPartialSwath = (unsigned int)dml_max(1, (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight); } numLines = *MaxNumSwath * SwathHeight + MaxPartialSwath; @@ -2954,7 +2954,7 @@ void dml32_UseMinimumDCFCLK( unsigned int VTotal[], unsigned int VActive[], unsigned int DynamicMetadataTransmittedBytes[], - unsigned int DynamicMetadataLinesBeforeActiveRequired[], + int DynamicMetadataLinesBeforeActiveRequired[], bool Interlace[], double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX], double RequiredDISPCLK[][2], @@ -3180,9 +3180,9 @@ unsigned int dml32_CalculateExtraLatencyBytes(unsigned int ReorderingBytes, if (HostVMMinPageSize < 2048) HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels; else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1); else - HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); + HostVMDynamicLevels = (unsigned int)dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2); } else { HostVMDynamicLevels = 0; } @@ -3196,7 +3196,7 @@ unsigned int dml32_CalculateExtraLatencyBytes(unsigned int ReorderingBytes, (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor; } } - return ret; + return (unsigned int)ret; } void dml32_CalculateVUpdateAndDynamicMetadataParameters( @@ -3228,7 +3228,7 @@ void dml32_CalculateVUpdateAndDynamicMetadataParameters( dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / Dppclk + TotalRepeaterDelayTime) * PixelClock, 1.0); *VReadyOffsetPix = dml_ceil(dml_max(150.0 / Dppclk, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / Dppclk) * PixelClock, 1.0); - *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1.0); + *VUpdateOffsetPix = (unsigned int)dml_ceil(HTotal / 4.0, 1.0); *TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock; *Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / Dispclk; *Tdmec = HTotal / PixelClock; @@ -3491,7 +3491,7 @@ bool dml32_CalculatePrefetchSchedule( double prefetch_sw_bytes; double bytes_pp; double dep_bytes; - unsigned int max_vratio_pre = v->MaxVRatioPre; + unsigned int max_vratio_pre = (unsigned int)v->MaxVRatioPre; double min_Lsw; double Tsw_est1 = 0; double Tsw_est3 = 0; @@ -3567,13 +3567,13 @@ bool dml32_CalculatePrefetchSchedule( v->GPUVMEnable == true ? TWait + Tvm_trips : 0); if (myPipe->ScalerEnabled) - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL); else - DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly; + DPPCycles = (unsigned int)(DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly); - DPPCycles = DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor; + DPPCycles = (unsigned int)(DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor); - DISPCLKCycles = v->DISPCLKDelaySubtotal; + DISPCLKCycles = (unsigned int)v->DISPCLKDelaySubtotal; if (myPipe->Dppclk == 0.0 || myPipe->Dispclk == 0.0) return true; @@ -4416,8 +4416,8 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( for (k = 0; k < v->NumberOfActiveSurfaces; ++k) { - LBLatencyHidingSourceLinesY[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); - LBLatencyHidingSourceLinesC[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); + LBLatencyHidingSourceLinesY[k] = (unsigned int)(dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1)); + LBLatencyHidingSourceLinesC[k] = (unsigned int)(dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1)); #ifdef __DML_VBA_DEBUG__ @@ -4440,7 +4440,7 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( } LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; - LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); + LinesInDETYRoundedDownToSwath[k] = (unsigned int)dml_floor(LinesInDETY[k], SwathHeightY[k]); FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; ActiveClockChangeLatencyHidingY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY @@ -4454,7 +4454,7 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( if (BytePerPixelDETC[k] > 0) { LinesInDETC[k] = DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; - LinesInDETCRoundedDownToSwath[k] = dml_floor(LinesInDETC[k], SwathHeightC[k]); + LinesInDETCRoundedDownToSwath[k] = (unsigned int)dml_floor(LinesInDETC[k], SwathHeightC[k]); FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k]; ActiveClockChangeLatencyHidingC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC @@ -4614,9 +4614,9 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( unsigned int src_y_pstate_c; unsigned int src_y_ahead_l, src_y_ahead_c, sub_vp_lines_l, sub_vp_lines_c; - dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (v->HTotal[k] / v->PixelClock[k]), 1); - src_y_pstate_l = dml_ceil(dst_y_pstate * v->VRatio[k], SwathHeightY[k]); - src_y_ahead_l = dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k]; + dst_y_pstate = (unsigned int)dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (v->HTotal[k] / v->PixelClock[k]), 1); + src_y_pstate_l = (unsigned int)dml_ceil(dst_y_pstate * v->VRatio[k], SwathHeightY[k]); + src_y_ahead_l = (unsigned int)(dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k]); sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + v->meta_row_height[k]; #ifdef __DML_VBA_DEBUG__ @@ -4634,10 +4634,10 @@ dml_print("DML::%s: k=%d, sub_vp_lines_l = %d\n", __func__, k, sub_vp_lines_l SubViewportLinesNeededInMALL[k] = sub_vp_lines_l; if (BytePerPixelDETC[k] > 0) { - src_y_pstate_c = dml_ceil(dst_y_pstate * v->VRatioChroma[k], SwathHeightC[k]); - src_y_ahead_c = dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k]; + src_y_pstate_c = (unsigned int)dml_ceil(dst_y_pstate * v->VRatioChroma[k], SwathHeightC[k]); + src_y_ahead_c = (unsigned int)(dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k]); sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + v->meta_row_height_chroma[k]; - SubViewportLinesNeededInMALL[k] = dml_max(sub_vp_lines_l, sub_vp_lines_c); + SubViewportLinesNeededInMALL[k] = (unsigned int)dml_max(sub_vp_lines_l, sub_vp_lines_c); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: k=%d, src_y_pstate_c = %d\n", __func__, k, src_y_pstate_c); @@ -4852,7 +4852,7 @@ void dml32_CalculatePixelDeliveryTimes( for (k = 0; k < NumberOfActiveSurfaces; ++k) { unsigned int cursor_req_per_width; - cursor_req_per_width = dml_ceil((double) CursorWidth[k][0] * (double) CursorBPP[k][0] / + cursor_req_per_width = (unsigned int)dml_ceil((double) CursorWidth[k][0] * (double) CursorBPP[k][0] / 256.0 / 8.0, 1.0); if (NumberOfCursors[k] > 0) { if (VRatio[k] <= 1) { @@ -5000,8 +5000,8 @@ void dml32_CalculateMetaAndPTETimes( meta_row_height_chroma[k]; min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k]; - meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / - meta_chunk_width_chroma; + meta_chunk_per_row_int_chroma = (unsigned int)((double) meta_row_width_chroma[k] / + meta_chunk_width_chroma); meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma; if (!IsVertical(SourceRotation[k])) { meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - @@ -5035,18 +5035,18 @@ void dml32_CalculateMetaAndPTETimes( for (k = 0; k < NumberOfActiveSurfaces; ++k) { if (GPUVMEnable == true) { if (!IsVertical(SourceRotation[k])) { - dpte_group_width_luma = (double) dpte_group_bytes[k] / - (double) PTERequestSizeY[k] * PixelPTEReqWidthY[k]; + dpte_group_width_luma = (unsigned int)((double) dpte_group_bytes[k] / + (double) PTERequestSizeY[k] * PixelPTEReqWidthY[k]); } else { - dpte_group_width_luma = (double) dpte_group_bytes[k] / - (double) PTERequestSizeY[k] * PixelPTEReqHeightY[k]; + dpte_group_width_luma = (unsigned int)((double) dpte_group_bytes[k] / + (double) PTERequestSizeY[k] * PixelPTEReqHeightY[k]); } if (use_one_row_for_frame[k]) { - dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] / + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil((double) dpte_row_width_luma_ub[k] / (double) dpte_group_width_luma / 2.0, 1.0); } else { - dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] / + dpte_groups_per_row_luma_ub = (unsigned int)dml_ceil((double) dpte_row_width_luma_ub[k] / (double) dpte_group_width_luma, 1.0); } #ifdef __DML_VBA_DEBUG__ @@ -5080,18 +5080,18 @@ void dml32_CalculateMetaAndPTETimes( time_per_pte_group_flip_chroma[k] = 0; } else { if (!IsVertical(SourceRotation[k])) { - dpte_group_width_chroma = (double) dpte_group_bytes[k] / - (double) PTERequestSizeC[k] * PixelPTEReqWidthC[k]; + dpte_group_width_chroma = (unsigned int)((double) dpte_group_bytes[k] / + (double) PTERequestSizeC[k] * PixelPTEReqWidthC[k]); } else { - dpte_group_width_chroma = (double) dpte_group_bytes[k] / - (double) PTERequestSizeC[k] * PixelPTEReqHeightC[k]; + dpte_group_width_chroma = (unsigned int)((double) dpte_group_bytes[k] / + (double) PTERequestSizeC[k] * PixelPTEReqHeightC[k]); } if (use_one_row_for_frame[k]) { - dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] / + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil((double) dpte_row_width_chroma_ub[k] / (double) dpte_group_width_chroma / 2.0, 1.0); } else { - dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] / + dpte_groups_per_row_chroma_ub = (unsigned int)dml_ceil((double) dpte_row_width_chroma_ub[k] / (double) dpte_group_width_chroma, 1.0); } #ifdef __DML_VBA_DEBUG__ @@ -5210,32 +5210,32 @@ void dml32_CalculateVMGroupAndRequestTimes( if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { if (DCCEnable[k] == false) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)(dml_ceil( (double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1.0) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / - (double) (vm_group_bytes[k]), 1.0); + (double) (vm_group_bytes[k]), 1.0)); } else { - num_group_per_lower_vm_stage = dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)dml_ceil( (double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1.0); } } else { if (GPUVMMaxPageTableLevels == 1) { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)(dml_ceil( (double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1.0) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / - (double) (vm_group_bytes[k]), 1.0); + (double) (vm_group_bytes[k]), 1.0)); } else { - num_group_per_lower_vm_stage = dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)dml_ceil( (double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1.0); } } else { if (BytePerPixelC[k] > 0) { - num_group_per_lower_vm_stage = 2 + dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)(2 + dml_ceil( (double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / @@ -5243,13 +5243,13 @@ void dml32_CalculateVMGroupAndRequestTimes( dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / - (double) (vm_group_bytes[k]), 1); + (double) (vm_group_bytes[k]), 1)); } else { - num_group_per_lower_vm_stage = 1 + dml_ceil( + num_group_per_lower_vm_stage = (unsigned int)(1 + dml_ceil( (double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) + dml_ceil( (double) (meta_pte_bytes_per_frame_ub_l[k]) / - (double) (vm_group_bytes[k]), 1); + (double) (vm_group_bytes[k]), 1)); } } } @@ -5424,8 +5424,8 @@ void dml32_CalculateDCCConfiguration( MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 6144; MAS_vp_vert_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : (BytePerPixelY == 8 ? 3072 : 6144); - max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); - max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); + max_vp_horz_width = (unsigned int)dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); + max_vp_vert_height = (unsigned int)dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); eff_surf_width_l = (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma); eff_surf_width_c = eff_surf_width_l / (1 + yuv420); eff_surf_height_l = (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma); @@ -5442,10 +5442,10 @@ void dml32_CalculateDCCConfiguration( } if (SourcePixelFormat == dm_420_10) { - full_swath_bytes_horz_wc_l = dml_ceil((double) full_swath_bytes_horz_wc_l * 2.0 / 3.0, 256.0); - full_swath_bytes_horz_wc_c = dml_ceil((double) full_swath_bytes_horz_wc_c * 2.0 / 3.0, 256.0); - full_swath_bytes_vert_wc_l = dml_ceil((double) full_swath_bytes_vert_wc_l * 2.0 / 3.0, 256.0); - full_swath_bytes_vert_wc_c = dml_ceil((double) full_swath_bytes_vert_wc_c * 2.0 / 3.0, 256.0); + full_swath_bytes_horz_wc_l = (unsigned int)dml_ceil((double) full_swath_bytes_horz_wc_l * 2.0 / 3.0, 256.0); + full_swath_bytes_horz_wc_c = (unsigned int)dml_ceil((double) full_swath_bytes_horz_wc_c * 2.0 / 3.0, 256.0); + full_swath_bytes_vert_wc_l = (unsigned int)dml_ceil((double) full_swath_bytes_vert_wc_l * 2.0 / 3.0, 256.0); + full_swath_bytes_vert_wc_c = (unsigned int)dml_ceil((double) full_swath_bytes_vert_wc_c * 2.0 / 3.0, 256.0); } if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) { @@ -5631,7 +5631,7 @@ void dml32_CalculateStutterEfficiency( bool Interlace[], double MinTTUVBlank[], unsigned int DPPPerSurface[], - unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeY[], unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], @@ -5663,10 +5663,10 @@ void dml32_CalculateStutterEfficiency( /* Output */ double *StutterEfficiencyNotIncludingVBlank, double *StutterEfficiency, - unsigned int *NumberOfStutterBurstsPerFrame, + int *NumberOfStutterBurstsPerFrame, double *Z8StutterEfficiencyNotIncludingVBlank, double *Z8StutterEfficiency, - unsigned int *Z8NumberOfStutterBurstsPerFrame, + int *Z8NumberOfStutterBurstsPerFrame, double *StutterPeriod, bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE) { @@ -5994,10 +5994,10 @@ void dml32_CalculateStutterEfficiency( 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100; *Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100; - *NumberOfStutterBurstsPerFrame = ( + *NumberOfStutterBurstsPerFrame = (unsigned int)( *StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalSurface / *StutterPeriod, 1) : 0); - *Z8NumberOfStutterBurstsPerFrame = ( + *Z8NumberOfStutterBurstsPerFrame = (unsigned int)( *Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalSurface / *StutterPeriod, 1) : 0); } else { @@ -6073,11 +6073,11 @@ void dml32_CalculateStutterEfficiency( dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame); #endif - SwathSizeCriticalSurface = BytePerPixelYCriticalSurface * SwathHeightYCriticalSurface - * dml_ceil(SwathWidthYCriticalSurface, BlockWidth256BytesYCriticalSurface); + SwathSizeCriticalSurface = (unsigned int)(BytePerPixelYCriticalSurface * SwathHeightYCriticalSurface + * dml_ceil(SwathWidthYCriticalSurface, BlockWidth256BytesYCriticalSurface)); LastChunkOfSwathSize = SwathSizeCriticalSurface % (PixelChunkSizeInKByte * 1024); - MissingPartOfLastSwathOfDETSize = dml_ceil(DETBufferSizeYCriticalSurface, SwathSizeCriticalSurface) - - DETBufferSizeYCriticalSurface; + MissingPartOfLastSwathOfDETSize = (unsigned int)(dml_ceil(DETBufferSizeYCriticalSurface, SwathSizeCriticalSurface) + - DETBufferSizeYCriticalSurface); *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = !(!UnboundedRequestEnabled && (NumberOfActiveSurfaces == 1) && doublePlaneCriticalSurface && doublePipeCriticalSurface && (LastChunkOfSwathSize > 0) @@ -6107,9 +6107,9 @@ void dml32_CalculateMaxDETAndMinCompressedBufferSize( bool det_buff_size_override_en = nomDETInKByteOverrideEnable; unsigned int det_buff_size_override_val = nomDETInKByteOverrideValue; - *MaxTotalDETInKByte = dml_ceil(((double)ConfigReturnBufferSizeInKByte + + *MaxTotalDETInKByte = (unsigned int)dml_ceil(((double)ConfigReturnBufferSizeInKByte + (double) ROBBufferSizeInKByte) * 4.0 / 5.0, 64); - *nomDETInKByte = dml_floor((double) *MaxTotalDETInKByte / (double) MaxNumDPP, 64); + *nomDETInKByte = (unsigned int)dml_floor((double) *MaxTotalDETInKByte / (double) MaxNumDPP, 64); *MinCompressedBufferSizeInKByte = ConfigReturnBufferSizeInKByte - *MaxTotalDETInKByte; #ifdef __DML_VBA_DEBUG__ @@ -6318,7 +6318,7 @@ bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurface enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[], enum unbounded_requesting_policy UseUnboundedRequesting) { - int k; + unsigned int k; double SwathSizeAllSurfaces = 0; double SwathSizeAllSurfacesInFetchTimeUs; double DETSwathLatencyHidingUs; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h index 5d34735df83d..9ea36f3ff27c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h @@ -614,7 +614,7 @@ void dml32_UseMinimumDCFCLK( unsigned int VTotal[], unsigned int VActive[], unsigned int DynamicMetadataTransmittedBytes[], - unsigned int DynamicMetadataLinesBeforeActiveRequired[], + int DynamicMetadataLinesBeforeActiveRequired[], bool Interlace[], double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX], double RequiredDISPCLK[][2], @@ -1013,7 +1013,7 @@ void dml32_CalculateStutterEfficiency( bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], - unsigned int DPPPerSurface[], + unsigned int DPPPerSurface[], unsigned int DETBufferSizeY[], unsigned int BytePerPixelY[], double BytePerPixelDETY[], @@ -1046,10 +1046,10 @@ void dml32_CalculateStutterEfficiency( /* Output */ double *StutterEfficiencyNotIncludingVBlank, double *StutterEfficiency, - unsigned int *NumberOfStutterBurstsPerFrame, + int *NumberOfStutterBurstsPerFrame, double *Z8StutterEfficiencyNotIncludingVBlank, double *Z8StutterEfficiency, - unsigned int *Z8NumberOfStutterBurstsPerFrame, + int *Z8NumberOfStutterBurstsPerFrame, double *StutterPeriod, bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c index 6c75aa82327a..bde043373d5d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c @@ -73,17 +73,17 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, dml_print("DML_DLG::%s: Calculation for pipe[%d] start, num_pipes=%d\n", __func__, pipe_idx, num_pipes); - pixel_chunk_bytes = get_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA - min_pixel_chunk_bytes = get_min_pixel_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA + pixel_chunk_bytes = (uint32_t)(get_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024); // From VBA + min_pixel_chunk_bytes = (uint32_t)get_min_pixel_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA if (pixel_chunk_bytes == 64 * 1024) min_pixel_chunk_bytes = 0; - meta_chunk_bytes = get_meta_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA - min_meta_chunk_bytes = get_min_meta_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA + meta_chunk_bytes = (uint32_t)(get_meta_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024); // From VBA + min_meta_chunk_bytes = (uint32_t)get_min_meta_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA - dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA - mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + dpte_group_bytes = (uint32_t)get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA + mpte_group_bytes = (uint32_t)get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA p1_pixel_chunk_bytes = pixel_chunk_bytes; p1_min_pixel_chunk_bytes = min_pixel_chunk_bytes; @@ -93,10 +93,10 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, p1_mpte_group_bytes = mpte_group_bytes; if ((enum source_format_class) src->source_format == dm_rgbe_alpha) - p1_pixel_chunk_bytes = get_alpha_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; + p1_pixel_chunk_bytes = (uint32_t)(get_alpha_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024); - rq_regs->rq_regs_l.chunk_size = dml_log2(pixel_chunk_bytes) - 10; - rq_regs->rq_regs_c.chunk_size = dml_log2(p1_pixel_chunk_bytes) - 10; + rq_regs->rq_regs_l.chunk_size = (uint32_t)(dml_log2(pixel_chunk_bytes) - 10); + rq_regs->rq_regs_c.chunk_size = (uint32_t)(dml_log2(p1_pixel_chunk_bytes) - 10); if (min_pixel_chunk_bytes == 0) rq_regs->rq_regs_l.min_chunk_size = 0; @@ -108,8 +108,8 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, else rq_regs->rq_regs_c.min_chunk_size = dml_log2(p1_min_pixel_chunk_bytes) - 8 + 1; - rq_regs->rq_regs_l.meta_chunk_size = dml_log2(meta_chunk_bytes) - 10; - rq_regs->rq_regs_c.meta_chunk_size = dml_log2(p1_meta_chunk_bytes) - 10; + rq_regs->rq_regs_l.meta_chunk_size = (uint32_t)(dml_log2(meta_chunk_bytes) - 10); + rq_regs->rq_regs_c.meta_chunk_size = (uint32_t)(dml_log2(p1_meta_chunk_bytes) - 10); if (min_meta_chunk_bytes == 0) rq_regs->rq_regs_l.min_meta_chunk_size = 0; @@ -121,32 +121,32 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, else rq_regs->rq_regs_c.min_meta_chunk_size = dml_log2(p1_min_meta_chunk_bytes) - 6 + 1; - rq_regs->rq_regs_l.dpte_group_size = dml_log2(dpte_group_bytes) - 6; + rq_regs->rq_regs_l.dpte_group_size = (uint32_t)(dml_log2(dpte_group_bytes) - 6); rq_regs->rq_regs_l.mpte_group_size = dml_log2(mpte_group_bytes) - 6; rq_regs->rq_regs_c.dpte_group_size = dml_log2(p1_dpte_group_bytes) - 6; rq_regs->rq_regs_c.mpte_group_size = dml_log2(p1_mpte_group_bytes) - 6; - detile_buf_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024; + detile_buf_size_in_bytes = (unsigned int)(get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024); detile_buf_plane1_addr = 0; - pte_row_height_linear = get_dpte_row_height_linear_l(mode_lib, e2e_pipe_param, num_pipes, + pte_row_height_linear = (unsigned int)get_dpte_row_height_linear_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); if (src->sw_mode == dm_sw_linear) ASSERT(pte_row_height_linear >= 8); - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(pte_row_height_linear), 1) - 3; + rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(pte_row_height_linear), 1) - 3); if (dual_plane) { - unsigned int p1_pte_row_height_linear = get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param, + unsigned int p1_pte_row_height_linear = (unsigned int)get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); if (src->sw_mode == dm_sw_linear) ASSERT(p1_pte_row_height_linear >= 8); - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(p1_pte_row_height_linear), 1) - 3; + rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(dml_floor(dml_log2(p1_pte_row_height_linear), 1) - 3); } - rq_regs->rq_regs_l.swath_height = dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); - rq_regs->rq_regs_c.swath_height = dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); + rq_regs->rq_regs_l.swath_height = (unsigned int)dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); + rq_regs->rq_regs_c.swath_height = (unsigned int)dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); // FIXME: take the max between luma, chroma chunk size? // okay for now, as we are setting pixel_chunk_bytes to 8kb anyways @@ -168,19 +168,19 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, // Note: detile_buf_plane1_addr is in unit of 1KB if (dual_plane) { if (is_phantom_pipe) { - detile_buf_plane1_addr = ((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma } else { if (stored_swath_l_bytes / stored_swath_c_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr); #endif } else { - detile_buf_plane1_addr = + detile_buf_plane1_addr = (unsigned int)( dml_round_to_multiple( (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), - 1024, 0) / 1024.0; // 2/3 to luma + 1024, 0) / 1024.0); // 2/3 to luma #ifdef __DML_RQ_DLG_CALC_DEBUG__ dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/3 chroma)\n", __func__, detile_buf_plane1_addr); @@ -276,7 +276,7 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA - min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); + min_dst_y_next_start = (unsigned int)get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); dml_print("DML_DLG: %s: min_dst_y_next_start = %d\n", __func__, min_dst_y_next_start); @@ -284,14 +284,14 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); - vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, + vready_after_vcount0 = (unsigned int)get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA dlg_regs->vready_after_vcount0 = vready_after_vcount0; dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, dlg_regs->vready_after_vcount0); - dst_x_after_scaler = dml_ceil(get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); - dst_y_after_scaler = dml_ceil(get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); + dst_x_after_scaler = (unsigned int)dml_ceil(get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); + dst_y_after_scaler = (unsigned int)dml_ceil(get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); // do some adjustment on the dst_after scaler to account for odm combine mode dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); @@ -398,15 +398,15 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, } if (src->dynamic_metadata_enable && src->gpuvm) - dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, - pipe_idx) * refclk_freq_in_mhz; // From VBA + dlg_regs->refcyc_per_vm_dmdata = (unsigned int)(get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz); // From VBA - dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) - * refclk_freq_in_mhz; // From VBA + dlg_regs->dmdata_dl_delta = (unsigned int)(get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) + * refclk_freq_in_mhz); // From VBA - refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, - pipe_idx) * refclk_freq_in_mhz; // From VBA + refcyc_per_req_delivery_pre_l = (unsigned int)(get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + refcyc_per_req_delivery_l = (unsigned int)(get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz); // From VBA dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l); dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, refcyc_per_req_delivery_l); @@ -437,11 +437,11 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, } // Assign to register structures - dlg_regs->min_dst_y_next_start = min_dst_y_next_start * dml_pow(2, 2); + dlg_regs->min_dst_y_next_start = (unsigned int)(min_dst_y_next_start * dml_pow(2, 2)); ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line - dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk + dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); @@ -456,14 +456,14 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_flip); dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, dlg_regs->dst_y_per_row_flip); - dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, - num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, - pipe_idx) * refclk_freq_in_mhz; // From VBA - dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, - pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA - dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, - pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA + dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, + num_pipes, pipe_idx) * refclk_freq_in_mhz); // From VBA + dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz); // From VBA + dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA + dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, + pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA // From VBA dst_y_per_pte_row_nom_l = get_dst_y_per_pte_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); @@ -500,22 +500,22 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, refcyc_per_meta_chunk_flip_c = get_refcyc_per_meta_chunk_flip_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA - dlg_regs->dst_y_per_pte_row_nom_l = dst_y_per_pte_row_nom_l * dml_pow(2, 2); - dlg_regs->dst_y_per_pte_row_nom_c = dst_y_per_pte_row_nom_c * dml_pow(2, 2); - dlg_regs->dst_y_per_meta_row_nom_l = dst_y_per_meta_row_nom_l * dml_pow(2, 2); - dlg_regs->dst_y_per_meta_row_nom_c = dst_y_per_meta_row_nom_c * dml_pow(2, 2); - dlg_regs->refcyc_per_pte_group_nom_l = refcyc_per_pte_group_nom_l; - dlg_regs->refcyc_per_pte_group_nom_c = refcyc_per_pte_group_nom_c; - dlg_regs->refcyc_per_pte_group_vblank_l = refcyc_per_pte_group_vblank_l; - dlg_regs->refcyc_per_pte_group_vblank_c = refcyc_per_pte_group_vblank_c; - dlg_regs->refcyc_per_pte_group_flip_l = refcyc_per_pte_group_flip_l; - dlg_regs->refcyc_per_pte_group_flip_c = refcyc_per_pte_group_flip_c; - dlg_regs->refcyc_per_meta_chunk_nom_l = refcyc_per_meta_chunk_nom_l; - dlg_regs->refcyc_per_meta_chunk_nom_c = refcyc_per_meta_chunk_nom_c; - dlg_regs->refcyc_per_meta_chunk_vblank_l = refcyc_per_meta_chunk_vblank_l; - dlg_regs->refcyc_per_meta_chunk_vblank_c = refcyc_per_meta_chunk_vblank_c; - dlg_regs->refcyc_per_meta_chunk_flip_l = refcyc_per_meta_chunk_flip_l; - dlg_regs->refcyc_per_meta_chunk_flip_c = refcyc_per_meta_chunk_flip_c; + dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)(dst_y_per_pte_row_nom_l * dml_pow(2, 2)); + dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int)(dst_y_per_pte_row_nom_c * dml_pow(2, 2)); + dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int)(dst_y_per_meta_row_nom_l * dml_pow(2, 2)); + dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int)(dst_y_per_meta_row_nom_c * dml_pow(2, 2)); + dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)refcyc_per_pte_group_nom_l; + dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)refcyc_per_pte_group_nom_c; + dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int)refcyc_per_pte_group_vblank_l; + dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int)refcyc_per_pte_group_vblank_c; + dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int)refcyc_per_pte_group_flip_l; + dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int)refcyc_per_pte_group_flip_c; + dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)refcyc_per_meta_chunk_nom_l; + dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)refcyc_per_meta_chunk_nom_c; + dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int)refcyc_per_meta_chunk_vblank_l; + dlg_regs->refcyc_per_meta_chunk_vblank_c = (unsigned int)refcyc_per_meta_chunk_vblank_c; + dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int)refcyc_per_meta_chunk_flip_l; + dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int)refcyc_per_meta_chunk_flip_c; dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1); dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1); @@ -548,7 +548,7 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, ttu_regs->qos_ramp_disable_l = 0; ttu_regs->qos_ramp_disable_c = 0; ttu_regs->qos_ramp_disable_cur0 = 0; - ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); // CHECK for HW registers' range, assert or clamp ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); @@ -556,16 +556,16 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); if (dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1); if (dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1); if (dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1); ASSERT(dlg_regs->dst_y_after_scaler < (unsigned int) 8); ASSERT(dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); @@ -581,10 +581,10 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, ASSERT(dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17)); if (dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { if (dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } ASSERT(dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); if (dual_plane) { @@ -592,10 +592,10 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, } if (dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (dual_plane) { if (dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) - dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; + dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1); } ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_c < (unsigned int)dml_pow(2, 13)); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c index e0a1dc89ce43..f4d826e0d13a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c @@ -162,20 +162,20 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) { if (entry->dcfclk_mhz > 0) { - float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); + float bw_on_sdp = (float)(entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); entry->fabricclk_mhz = bw_on_sdp / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans * dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); } else if (entry->fabricclk_mhz > 0) { - float bw_on_fabric = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); + float bw_on_fabric = (float)(entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans * dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); } else if (entry->dram_speed_mts > 0) { - float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans * - dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); + float bw_on_dram = (float)(entry->dram_speed_mts * dcn3_21_soc.num_chans * + dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); entry->fabricclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); entry->dcfclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); @@ -189,12 +189,12 @@ static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st * float sdp_bw_kbytes_sec; float limiting_bw_kbytes_sec; - memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans * - dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); + memory_bw_kbytes_sec = (float)(entry->dram_speed_mts * dcn3_21_soc.num_chans * + dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); - fabric_bw_kbytes_sec = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100); + fabric_bw_kbytes_sec = (float)(entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100)); - sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100); + sdp_bw_kbytes_sec = (float)(entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100)); limiting_bw_kbytes_sec = memory_bw_kbytes_sec; @@ -211,8 +211,8 @@ static void dcn321_insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scalin unsigned int *num_entries, struct _vcs_dpi_voltage_scaling_st *entry) { - int i = 0; - int index = 0; + unsigned int i = 0; + unsigned int index = 0; dc_assert_fp_enabled(); @@ -237,7 +237,7 @@ static void dcn321_insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scalin static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, unsigned int index) { - int i; + unsigned int i; if (*num_entries == 0) return; @@ -265,19 +265,19 @@ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int end_index = 0; unsigned int current_bw = 0; - for (int i = 0; i < (*num_entries - 1); i++) { + for (unsigned int i = 0; i + 1 < *num_entries; i++) { if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { - current_bw = table[i].net_bw_in_kbytes_sec; + current_bw = (unsigned int)table[i].net_bw_in_kbytes_sec; start_index = i; end_index = ++i; - while ((i < (*num_entries - 1)) && (table[i+1].net_bw_in_kbytes_sec == current_bw)) + while ((i + 1 < *num_entries) && (table[i+1].net_bw_in_kbytes_sec == current_bw)) end_index = ++i; } if (start_index != end_index) { - for (int j = start_index; j < end_index; j++) { - for (int k = start_index; k < end_index; k++) { + for (unsigned int j = start_index; j < end_index; j++) { + for (unsigned int k = start_index; k < end_index; k++) { if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) swap_table_entries(&table[k], &table[k+1]); } @@ -296,7 +296,7 @@ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, */ static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { - for (int i = 0; i < (*num_entries - 1); i++) { + for (unsigned int i = 0; i + 1 < *num_entries; i++) { if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) { if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) || (table[i].fabricclk_mhz > table[i+1].fabricclk_mhz)) @@ -344,7 +344,8 @@ static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit, static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { - int i, j; + int i; + unsigned int j, k; struct _vcs_dpi_voltage_scaling_st entry = {0}; struct clk_limit_table_entry max_clk_data = {0}; @@ -414,12 +415,12 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz; if (max_clk_data.fclk_mhz == 0) - max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz * + max_clk_data.fclk_mhz = (unsigned int)(max_clk_data.dcfclk_mhz * dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / - dcn3_21_soc.pct_ideal_fabric_bw_after_urgent; + dcn3_21_soc.pct_ideal_fabric_bw_after_urgent); if (max_clk_data.phyclk_mhz == 0) - max_clk_data.phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; + max_clk_data.phyclk_mhz = (unsigned int)dcn3_21_soc.clock_limits[0].phyclk_mhz; *num_entries = 0; entry.dispclk_mhz = max_clk_data.dispclk_mhz; @@ -431,8 +432,8 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; // Insert all the DCFCLK STAs - for (i = 0; i < num_dcfclk_stas; i++) { - entry.dcfclk_mhz = dcfclk_sta_targets[i]; + for (k = 0; k < num_dcfclk_stas; k++) { + entry.dcfclk_mhz = dcfclk_sta_targets[k]; entry.fabricclk_mhz = 0; entry.dram_speed_mts = 0; @@ -451,10 +452,10 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk dcn321_insert_entry_into_table_sorted(table, num_entries, &entry); // Insert the UCLK DPMS - for (i = 0; i < num_uclk_dpms; i++) { + for (k = 0; k < num_uclk_dpms; k++) { entry.dcfclk_mhz = 0; entry.fabricclk_mhz = 0; - entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; + entry.dram_speed_mts = bw_params->clk_table.entries[k].memclk_mhz * 16; get_optimal_ntuple(&entry); entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry); @@ -463,9 +464,9 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // If FCLK is coarse grained, insert individual DPMs. if (num_fclk_dpms > 2) { - for (i = 0; i < num_fclk_dpms; i++) { + for (k = 0; k < num_fclk_dpms; k++) { entry.dcfclk_mhz = 0; - entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; + entry.fabricclk_mhz = bw_params->clk_table.entries[k].fclk_mhz; entry.dram_speed_mts = 0; get_optimal_ntuple(&entry); @@ -489,7 +490,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // ratios (by derate, are exact). // Remove states that require higher clocks than are supported - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) { if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz || table[i].fabricclk_mhz > max_clk_data.fclk_mhz || table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16) @@ -519,7 +520,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // coarse grained DPMs and remove duplicates. // Round up UCLKs - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) { for (j = 0; j < num_uclk_dpms; j++) { if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; @@ -530,7 +531,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // If FCLK is coarse grained, round up to next DPMs if (num_fclk_dpms > 2) { - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) { for (j = 0; j < num_fclk_dpms; j++) { if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; @@ -541,7 +542,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk } // Otherwise, round up to minimum. else { - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) { if (table[i].fabricclk_mhz < min_fclk_mhz) { table[i].fabricclk_mhz = min_fclk_mhz; } @@ -549,7 +550,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk } // Round DCFCLKs up to minimum - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) { if (table[i].dcfclk_mhz < min_dcfclk_mhz) { table[i].dcfclk_mhz = min_dcfclk_mhz; } @@ -557,7 +558,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. i = 0; - while (i < *num_entries - 1) { + while (i < (int)*num_entries - 1) { if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && table[i].dram_speed_mts == table[i + 1].dram_speed_mts) @@ -567,9 +568,8 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk } // Fix up the state indicies - for (i = *num_entries - 1; i >= 0 ; i--) { + for (i = (int)*num_entries - 1; i >= 0 ; i--) table[i].state = i; - } return 0; } @@ -588,12 +588,12 @@ static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; if (optimal_fclk) - *optimal_fclk = bw_from_dram / - (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_fclk = (unsigned int)(bw_from_dram / + (dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100))); if (optimal_dcfclk) - *optimal_dcfclk = bw_from_dram / - (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); + *optimal_dcfclk = (unsigned int)(bw_from_dram / + (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100))); } /** dcn321_update_bw_bounding_box @@ -688,9 +688,12 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); } - if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) - dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = - dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) { + unsigned int dram_channel_width_bytes = (unsigned int)dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; + + dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = dram_channel_width_bytes; + dcn3_21_soc.dram_channel_width_bytes = dram_channel_width_bytes; + } /* DML DSC delay factor workaround */ dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; @@ -729,13 +732,13 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; } if (!max_dcfclk_mhz) - max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz; + max_dcfclk_mhz = (unsigned int)dcn3_21_soc.clock_limits[0].dcfclk_mhz; if (!max_dispclk_mhz) - max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz; + max_dispclk_mhz = (unsigned int)dcn3_21_soc.clock_limits[0].dispclk_mhz; if (!max_dppclk_mhz) - max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; + max_dppclk_mhz = (unsigned int)dcn3_21_soc.clock_limits[0].dppclk_mhz; if (!max_phyclk_mhz) - max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; + max_phyclk_mhz = (unsigned int)dcn3_21_soc.clock_limits[0].phyclk_mhz; if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index 7f40048dd67d..c15fbc18bfdf 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -233,7 +233,7 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc, struct clk_limit_table *clk_table = &bw_params->clk_table; struct _vcs_dpi_voltage_scaling_st *clock_limits = dc->scratch.update_bw_bounding_box.clock_limits; - int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; dc_assert_fp_enabled(); @@ -357,21 +357,21 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc, dc->dml2_options.bbox_overrides.clks_table.num_states = clk_table->num_entries; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = - clock_limits[i].dcfclk_mhz; + (unsigned int)clock_limits[i].dcfclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz = - clock_limits[i].fabricclk_mhz; + (unsigned int)clock_limits[i].fabricclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz = - clock_limits[i].dispclk_mhz; + (unsigned int)clock_limits[i].dispclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz = - clock_limits[i].dppclk_mhz; + (unsigned int)clock_limits[i].dppclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz = - clock_limits[i].socclk_mhz; + (unsigned int)clock_limits[i].socclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz = clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio; - dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts; + dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = (unsigned int)clock_limits[i].dram_speed_mts; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz = - clock_limits[i].dtbclk_mhz; + (unsigned int)clock_limits[i].dtbclk_mhz; dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = clk_table->num_entries; dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = @@ -415,11 +415,11 @@ static bool is_dual_plane(enum surface_pixel_format format) static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) { unsigned int num_lines = 0; - unsigned int lines_time_in_ns = 1000.0 * - (((float)timing->h_total * 1000.0) / - ((float)timing->pix_clk_100hz / 10.0)); + double lines_time_in_ns = 1000.0 * + (((double)timing->h_total * 1000.0) / + ((double)timing->pix_clk_100hz / 10.0)); - num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); + num_lines = (unsigned int)dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); return num_lines; } @@ -440,7 +440,8 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + unsigned int i; + int pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; bool upscaled = false; @@ -550,16 +551,16 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, } for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream) + if (!cur_pipe->stream) continue; - if (pipe->stream->signal == SIGNAL_TYPE_EDP && + if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && - pipe->stream->apply_seamless_boot_optimization) { + cur_pipe->stream->apply_seamless_boot_optimization) { - if (pipe->stream->apply_boot_odm_mode == + if (cur_pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c index 73c2aee57f28..6552b26de845 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c @@ -266,7 +266,7 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc, struct clk_limit_table *clk_table = &bw_params->clk_table; struct _vcs_dpi_voltage_scaling_st *clock_limits = dc->scratch.update_bw_bounding_box.clock_limits; - int max_dispclk_mhz = 0, max_dppclk_mhz = 0; + unsigned int max_dispclk_mhz = 0, max_dppclk_mhz = 0; dc_assert_fp_enabled(); @@ -390,20 +390,20 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc, dc->dml2_options.bbox_overrides.clks_table.num_states = clk_table->num_entries; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = - clock_limits[i].dcfclk_mhz; + (unsigned int)clock_limits[i].dcfclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz = - clock_limits[i].fabricclk_mhz; + (unsigned int)clock_limits[i].fabricclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz = - clock_limits[i].dispclk_mhz; + (unsigned int)clock_limits[i].dispclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz = - clock_limits[i].dppclk_mhz; + (unsigned int)clock_limits[i].dppclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz = - clock_limits[i].socclk_mhz; + (unsigned int)clock_limits[i].socclk_mhz; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz = clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio; - dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts; + dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = (unsigned int)clock_limits[i].dram_speed_mts; dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz = - clock_limits[i].dtbclk_mhz; + (unsigned int)clock_limits[i].dtbclk_mhz; dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = clk_table->num_entries; dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = @@ -447,11 +447,11 @@ static bool is_dual_plane(enum surface_pixel_format format) static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) { unsigned int num_lines = 0; - unsigned int lines_time_in_ns = 1000.0 * - (((float)timing->h_total * 1000.0) / - ((float)timing->pix_clk_100hz / 10.0)); + double lines_time_in_ns = 1000.0 * + (((double)timing->h_total * 1000.0) / + ((double)timing->pix_clk_100hz / 10.0)); - num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); + num_lines = (unsigned int)dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); return num_lines; } @@ -472,7 +472,8 @@ int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc, display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + int pipe_cnt; + unsigned int i; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; bool upscaled = false; @@ -582,16 +583,16 @@ int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc, } for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream) + if (!cur_pipe->stream) continue; - if (pipe->stream->signal == SIGNAL_TYPE_EDP && + if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && - pipe->stream->apply_seamless_boot_optimization) { + cur_pipe->stream->apply_seamless_boot_optimization) { - if (pipe->stream->apply_boot_odm_mode == + if (cur_pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index 85453bbb4f9b..c42884dc16b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -246,7 +246,7 @@ unsigned int get_total_surface_size_in_mall_bytes( unsigned int num_pipes) { unsigned int k; - unsigned int size = 0.0; + unsigned int size = 0; recalculate_params(mode_lib, pipes, num_pipes); for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) size += mode_lib->vba.SurfaceSizeInMALL[k]; @@ -304,7 +304,7 @@ bool get_is_phantom_pipe(struct display_mode_lib *mode_lib, const display_e2e_pi static void fetch_socbb_params(struct display_mode_lib *mode_lib) { soc_bounding_box_st *soc = &mode_lib->vba.soc; - int i; + unsigned int i; // SOC Bounding Box Parameters mode_lib->vba.ReturnBusWidth = soc->return_bus_width_bytes; @@ -343,7 +343,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib) mode_lib->vba.FCLKChangeLatency = soc->fclk_change_latency_us; mode_lib->vba.USRRetrainingLatency = soc->usr_retraining_latency_us; mode_lib->vba.SMNLatency = soc->smn_latency_us; - mode_lib->vba.MALLAllocatedForDCNFinal = soc->mall_allocated_for_dcn_mbytes; + mode_lib->vba.MALLAllocatedForDCNFinal = (unsigned int)soc->mall_allocated_for_dcn_mbytes; mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE = soc->pct_ideal_dram_bw_after_urgent_strobe; mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation = @@ -946,7 +946,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) */ static void cache_debug_params(struct display_mode_lib *mode_lib) { - int k = 0; + unsigned int k = 0; for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) mode_lib->vba.CachedActiveDRAMClockChangeLatencyMargin[k] = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 07993741f5e6..cde84dfb0953 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -472,7 +472,7 @@ struct vba_vars_st { unsigned int VTotal[DC__NUM_DPP__MAX]; unsigned int VTotal_Max[DC__NUM_DPP__MAX]; unsigned int VTotal_Min[DC__NUM_DPP__MAX]; - int DPPPerPlane[DC__NUM_DPP__MAX]; + unsigned int DPPPerPlane[DC__NUM_DPP__MAX]; double PixelClock[DC__NUM_DPP__MAX]; double PixelClockBackEnd[DC__NUM_DPP__MAX]; bool DCCEnable[DC__NUM_DPP__MAX]; @@ -739,7 +739,7 @@ struct vba_vars_st { /* ms locals */ double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2]; unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; - int NoOfDPPThisState[DC__NUM_DPP__MAX]; + unsigned int NoOfDPPThisState[DC__NUM_DPP__MAX]; enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; double SwathWidthYThisState[DC__NUM_DPP__MAX]; unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; @@ -900,7 +900,7 @@ struct vba_vars_st { int PTEBufferSizeInRequestsForChroma; // Missing from VBA - int dpte_group_bytes_chroma; + unsigned int dpte_group_bytes_chroma; unsigned int vm_group_bytes_chroma; double dst_x_after_scaler; double dst_y_after_scaler; @@ -1100,8 +1100,8 @@ struct vba_vars_st { unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX]; bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX]; bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; - int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX]; - int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX]; + unsigned int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX]; + unsigned int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX]; double UrgLatency[DC__VOLTAGE_STATES]; double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; @@ -1172,7 +1172,7 @@ struct vba_vars_st { int ConfigReturnBufferSizeInKByte; enum unbounded_requesting_policy UseUnboundedRequesting; int CompressedBufferSegmentSizeInkByte; - int CompressedBufferSizeInkByte; + unsigned int CompressedBufferSizeInkByte; int MetaFIFOSizeInKEntries; int ZeroSizeBufferEntries; int COMPBUF_RESERVED_SPACE_64B; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c index cf194bcba455..ff5cb04db9dd 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c @@ -261,12 +261,12 @@ void dml1_extract_rq_regs( if (rq_param->yuv420) { if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { - detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); /* half to chroma */ + detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 64.0); /* half to chroma */ } else { - detile_buf_plane1_addr = dml_round_to_multiple( + detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple( (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 256, - 0) / 64.0; /* 2/3 to chroma */ + 0) / 64.0); /* 2/3 to chroma */ } } rq_regs->plane1_base_address = detile_buf_plane1_addr; @@ -447,7 +447,7 @@ static void dml1_rq_dlg_get_row_heights( */ if (tiling != dm_sw_linear) log2_blk_height = log2_blk256_height - + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + + (unsigned int)dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); else log2_blk_height = 0; /* blk height of 1 */ @@ -522,7 +522,7 @@ static void dml1_rq_dlg_get_row_heights( * round the result down to a power of two. */ if (surf_linear) { - log2_dpte_row_height_linear = dml_floor( + log2_dpte_row_height_linear = (unsigned int)dml_floor( dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); @@ -686,7 +686,7 @@ static void get_surf_rq_param( */ if (pipe_src_param->sw_mode != dm_sw_linear) log2_blk_height = log2_blk256_height - + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); + + (unsigned int)dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); else log2_blk_height = 0; /* blk height of 1 */ @@ -848,7 +848,7 @@ static void get_surf_rq_param( * round the result down to a power of two. */ if (surf_linear) { - log2_dpte_row_height_linear = dml_floor( + log2_dpte_row_height_linear = (unsigned int)dml_floor( dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); @@ -922,7 +922,7 @@ static void get_surf_rq_param( /* since dpte groups are only aligned to dpte_req_width and not dpte_group_width, * the upper bound for the dpte groups per row is as follows. */ - rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( + rq_dlg_param->dpte_groups_per_row_ub = (unsigned int)dml_ceil( (double) dpte_row_width_ub / dpte_group_width, 1); @@ -1248,8 +1248,8 @@ void dml1_rq_dlg_get_dlg_params( dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; - pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz - + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; + pixel_rate_delay_subtotal = (unsigned int)(dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz + + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz); vstartup_start = e2e_pipe_param->pipe.dest.vstartup_start; @@ -1439,7 +1439,7 @@ void dml1_rq_dlg_get_dlg_params( } disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; /* in terms of line */ - disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; /* in terms of refclk */ + disp_dlg_regs->refcyc_x_after_scaler = (unsigned int)(dst_x_after_scaler * ref_freq_to_pix_freq); /* in terms of refclk */ ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); DTRACE( "DLG: %s: disp_dlg_regs->dst_y_after_scaler = 0x%0x", @@ -1576,19 +1576,19 @@ void dml1_rq_dlg_get_dlg_params( / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1); disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) - disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; + disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1); if (mode_422) { swath_width_pixels_ub_l = swath_width_ub_l * 2; /* *2 for 2 pixel per element */ @@ -1844,7 +1844,7 @@ void dml1_rq_dlg_get_dlg_params( cur0_req_size = 256; } - cur0_req_width = (double) cur0_req_size / ((double) cur0_bit_per_pixel / 8.0); + cur0_req_width = (unsigned int)((double) cur0_req_size / ((double) cur0_bit_per_pixel / 8.0)); cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1) * (double) cur0_req_width; cur0_req_per_width = cur0_width_ub / (double) cur0_req_width; @@ -1917,7 +1917,7 @@ void dml1_rq_dlg_get_dlg_params( disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs->qos_ramp_disable_cur0 = 0; - disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; + disp_ttu_regs->min_ttu_vblank = (unsigned int)(min_ttu_vblank * refclk_freq_in_mhz); ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); print__ttu_regs_st(mode_lib, disp_ttu_regs); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h index 6b2ab4ec2b5f..be6ebf53d9a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h @@ -31,7 +31,7 @@ static inline double dml_min(double a, double b) { - return (double) dcn_bw_min2(a, b); + return (double)dcn_bw_min2((float)a, (float)b); } static inline double dml_min3(double a, double b, double c) @@ -46,7 +46,7 @@ static inline double dml_min4(double a, double b, double c, double d) static inline double dml_max(double a, double b) { - return (double) dcn_bw_max2(a, b); + return (double)dcn_bw_max2((float)a, (float)b); } static inline double dml_max3(double a, double b, double c) @@ -68,14 +68,14 @@ static inline double dml_ceil(double a, double granularity) { if (granularity == 0) return 0; - return (double) dcn_bw_ceil2(a, granularity); + return (double)dcn_bw_ceil2((float)a, (float)granularity); } static inline double dml_floor(double a, double granularity) { if (granularity == 0) return 0; - return (double) dcn_bw_floor2(a, granularity); + return (double)dcn_bw_floor2((float)a, (float)granularity); } static inline double dml_round(double a) @@ -103,31 +103,31 @@ static inline int dml_log2(double x) static inline double dml_pow(double a, int exp) { - return (double) dcn_bw_pow(a, exp); + return (double)dcn_bw_pow((float)a, (float)exp); } static inline double dml_fmod(double f, int val) { - return (double) dcn_bw_mod(f, val); + return (double)dcn_bw_mod((float)f, (float)val); } static inline double dml_ceil_2(double f) { - return (double) dcn_bw_ceil2(f, 2); + return (double)dcn_bw_ceil2((float)f, 2.0f); } static inline double dml_ceil_ex(double x, double granularity) { if (granularity == 0) return 0; - return (double) dcn_bw_ceil2(x, granularity); + return (double)dcn_bw_ceil2((float)x, (float)granularity); } static inline double dml_floor_ex(double x, double granularity) { if (granularity == 0) return 0; - return (double) dcn_bw_floor2(x, granularity); + return (double)dcn_bw_floor2((float)x, (float)granularity); } static inline unsigned int dml_round_to_multiple(unsigned int num, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index ef75eb7d5adc..b8fc27a5361e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -96,7 +96,7 @@ static void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, if (!table) return; - index = (bpp - table[0].bpp) * 2; + index = (int)((bpp - table[0].bpp) * 2); /* requested size is bigger than the table */ if (index >= table_size) { @@ -112,50 +112,50 @@ static void get_ofs_set(qp_set ofs, enum colour_mode mode, float bpp) int *p = ofs; if (mode == CM_444 || mode == CM_RGB) { - *p++ = (bpp <= 6) ? (0) : ((((bpp >= 8) && (bpp <= 12))) ? (2) : ((bpp >= 15) ? (10) : ((((bpp > 6) && (bpp < 8))) ? (0 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (2 + dsc_roundf((bpp - 12) * (8 / 3.0)))))); - *p++ = (bpp <= 6) ? (-2) : ((((bpp >= 8) && (bpp <= 12))) ? (0) : ((bpp >= 15) ? (8) : ((((bpp > 6) && (bpp < 8))) ? (-2 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (0 + dsc_roundf((bpp - 12) * (8 / 3.0)))))); - *p++ = (bpp <= 6) ? (-2) : ((((bpp >= 8) && (bpp <= 12))) ? (0) : ((bpp >= 15) ? (6) : ((((bpp > 6) && (bpp < 8))) ? (-2 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (0 + dsc_roundf((bpp - 12) * (6 / 3.0)))))); - *p++ = (bpp <= 6) ? (-4) : ((((bpp >= 8) && (bpp <= 12))) ? (-2) : ((bpp >= 15) ? (4) : ((((bpp > 6) && (bpp < 8))) ? (-4 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (-2 + dsc_roundf((bpp - 12) * (6 / 3.0)))))); - *p++ = (bpp <= 6) ? (-6) : ((((bpp >= 8) && (bpp <= 12))) ? (-4) : ((bpp >= 15) ? (2) : ((((bpp > 6) && (bpp < 8))) ? (-6 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (-4 + dsc_roundf((bpp - 12) * (6 / 3.0)))))); - *p++ = (bpp <= 12) ? (-6) : ((bpp >= 15) ? (0) : (-6 + dsc_roundf((bpp - 12) * (6 / 3.0)))); - *p++ = (bpp <= 12) ? (-8) : ((bpp >= 15) ? (-2) : (-8 + dsc_roundf((bpp - 12) * (6 / 3.0)))); - *p++ = (bpp <= 12) ? (-8) : ((bpp >= 15) ? (-4) : (-8 + dsc_roundf((bpp - 12) * (4 / 3.0)))); - *p++ = (bpp <= 12) ? (-8) : ((bpp >= 15) ? (-6) : (-8 + dsc_roundf((bpp - 12) * (2 / 3.0)))); - *p++ = (bpp <= 12) ? (-10) : ((bpp >= 15) ? (-8) : (-10 + dsc_roundf((bpp - 12) * (2 / 3.0)))); + *p++ = (int)((bpp <= 6) ? (0) : ((((bpp >= 8) && (bpp <= 12))) ? (2) : ((bpp >= 15) ? (10) : ((((bpp > 6) && (bpp < 8))) ? (0 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (2 + dsc_roundf((bpp - 12) * (8 / 3.0))))))); + *p++ = (int)((bpp <= 6) ? (-2) : ((((bpp >= 8) && (bpp <= 12))) ? (0) : ((bpp >= 15) ? (8) : ((((bpp > 6) && (bpp < 8))) ? (-2 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (0 + dsc_roundf((bpp - 12) * (8 / 3.0))))))); + *p++ = (int)((bpp <= 6) ? (-2) : ((((bpp >= 8) && (bpp <= 12))) ? (0) : ((bpp >= 15) ? (6) : ((((bpp > 6) && (bpp < 8))) ? (-2 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (0 + dsc_roundf((bpp - 12) * (6 / 3.0))))))); + *p++ = (int)((bpp <= 6) ? (-4) : ((((bpp >= 8) && (bpp <= 12))) ? (-2) : ((bpp >= 15) ? (4) : ((((bpp > 6) && (bpp < 8))) ? (-4 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (-2 + dsc_roundf((bpp - 12) * (6 / 3.0))))))); + *p++ = (int)((bpp <= 6) ? (-6) : ((((bpp >= 8) && (bpp <= 12))) ? (-4) : ((bpp >= 15) ? (2) : ((((bpp > 6) && (bpp < 8))) ? (-6 + dsc_roundf((bpp - 6) * (2 / 2.0))) : (-4 + dsc_roundf((bpp - 12) * (6 / 3.0))))))); + *p++ = (int)((bpp <= 12) ? (-6) : ((bpp >= 15) ? (0) : (-6 + dsc_roundf((bpp - 12) * (6 / 3.0))))); + *p++ = (int)((bpp <= 12) ? (-8) : ((bpp >= 15) ? (-2) : (-8 + dsc_roundf((bpp - 12) * (6 / 3.0))))); + *p++ = (int)((bpp <= 12) ? (-8) : ((bpp >= 15) ? (-4) : (-8 + dsc_roundf((bpp - 12) * (4 / 3.0))))); + *p++ = (int)((bpp <= 12) ? (-8) : ((bpp >= 15) ? (-6) : (-8 + dsc_roundf((bpp - 12) * (2 / 3.0))))); + *p++ = (int)((bpp <= 12) ? (-10) : ((bpp >= 15) ? (-8) : (-10 + dsc_roundf((bpp - 12) * (2 / 3.0))))); *p++ = -10; - *p++ = (bpp <= 6) ? (-12) : ((bpp >= 8) ? (-10) : (-12 + dsc_roundf((bpp - 6) * (2 / 2.0)))); + *p++ = (int)((bpp <= 6) ? (-12) : ((bpp >= 8) ? (-10) : (-12 + dsc_roundf((bpp - 6) * (2 / 2.0))))); *p++ = -12; *p++ = -12; *p++ = -12; } else if (mode == CM_422) { - *p++ = (bpp <= 8) ? (2) : ((bpp >= 10) ? (10) : (2 + dsc_roundf((bpp - 8) * (8 / 2.0)))); - *p++ = (bpp <= 8) ? (0) : ((bpp >= 10) ? (8) : (0 + dsc_roundf((bpp - 8) * (8 / 2.0)))); - *p++ = (bpp <= 8) ? (0) : ((bpp >= 10) ? (6) : (0 + dsc_roundf((bpp - 8) * (6 / 2.0)))); - *p++ = (bpp <= 8) ? (-2) : ((bpp >= 10) ? (4) : (-2 + dsc_roundf((bpp - 8) * (6 / 2.0)))); - *p++ = (bpp <= 8) ? (-4) : ((bpp >= 10) ? (2) : (-4 + dsc_roundf((bpp - 8) * (6 / 2.0)))); - *p++ = (bpp <= 8) ? (-6) : ((bpp >= 10) ? (0) : (-6 + dsc_roundf((bpp - 8) * (6 / 2.0)))); - *p++ = (bpp <= 8) ? (-8) : ((bpp >= 10) ? (-2) : (-8 + dsc_roundf((bpp - 8) * (6 / 2.0)))); - *p++ = (bpp <= 8) ? (-8) : ((bpp >= 10) ? (-4) : (-8 + dsc_roundf((bpp - 8) * (4 / 2.0)))); - *p++ = (bpp <= 8) ? (-8) : ((bpp >= 10) ? (-6) : (-8 + dsc_roundf((bpp - 8) * (2 / 2.0)))); - *p++ = (bpp <= 8) ? (-10) : ((bpp >= 10) ? (-8) : (-10 + dsc_roundf((bpp - 8) * (2 / 2.0)))); + *p++ = (int)((bpp <= 8) ? (2) : ((bpp >= 10) ? (10) : (2 + dsc_roundf((bpp - 8) * (8 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (0) : ((bpp >= 10) ? (8) : (0 + dsc_roundf((bpp - 8) * (8 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (0) : ((bpp >= 10) ? (6) : (0 + dsc_roundf((bpp - 8) * (6 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-2) : ((bpp >= 10) ? (4) : (-2 + dsc_roundf((bpp - 8) * (6 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-4) : ((bpp >= 10) ? (2) : (-4 + dsc_roundf((bpp - 8) * (6 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-6) : ((bpp >= 10) ? (0) : (-6 + dsc_roundf((bpp - 8) * (6 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-8) : ((bpp >= 10) ? (-2) : (-8 + dsc_roundf((bpp - 8) * (6 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-8) : ((bpp >= 10) ? (-4) : (-8 + dsc_roundf((bpp - 8) * (4 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-8) : ((bpp >= 10) ? (-6) : (-8 + dsc_roundf((bpp - 8) * (2 / 2.0))))); + *p++ = (int)((bpp <= 8) ? (-10) : ((bpp >= 10) ? (-8) : (-10 + dsc_roundf((bpp - 8) * (2 / 2.0))))); *p++ = -10; - *p++ = (bpp <= 6) ? (-12) : ((bpp >= 7) ? (-10) : (-12 + dsc_roundf((bpp - 6) * (2.0 / 1)))); + *p++ = (int)((bpp <= 6) ? (-12) : ((bpp >= 7) ? (-10) : (-12 + dsc_roundf((bpp - 6) * (2.0 / 1))))); *p++ = -12; *p++ = -12; *p++ = -12; } else { - *p++ = (bpp <= 6) ? (2) : ((bpp >= 8) ? (10) : (2 + dsc_roundf((bpp - 6) * (8 / 2.0)))); - *p++ = (bpp <= 6) ? (0) : ((bpp >= 8) ? (8) : (0 + dsc_roundf((bpp - 6) * (8 / 2.0)))); - *p++ = (bpp <= 6) ? (0) : ((bpp >= 8) ? (6) : (0 + dsc_roundf((bpp - 6) * (6 / 2.0)))); - *p++ = (bpp <= 6) ? (-2) : ((bpp >= 8) ? (4) : (-2 + dsc_roundf((bpp - 6) * (6 / 2.0)))); - *p++ = (bpp <= 6) ? (-4) : ((bpp >= 8) ? (2) : (-4 + dsc_roundf((bpp - 6) * (6 / 2.0)))); - *p++ = (bpp <= 6) ? (-6) : ((bpp >= 8) ? (0) : (-6 + dsc_roundf((bpp - 6) * (6 / 2.0)))); - *p++ = (bpp <= 6) ? (-8) : ((bpp >= 8) ? (-2) : (-8 + dsc_roundf((bpp - 6) * (6 / 2.0)))); - *p++ = (bpp <= 6) ? (-8) : ((bpp >= 8) ? (-4) : (-8 + dsc_roundf((bpp - 6) * (4 / 2.0)))); - *p++ = (bpp <= 6) ? (-8) : ((bpp >= 8) ? (-6) : (-8 + dsc_roundf((bpp - 6) * (2 / 2.0)))); - *p++ = (bpp <= 6) ? (-10) : ((bpp >= 8) ? (-8) : (-10 + dsc_roundf((bpp - 6) * (2 / 2.0)))); + *p++ = (int)((bpp <= 6) ? (2) : ((bpp >= 8) ? (10) : (2 + dsc_roundf((bpp - 6) * (8 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (0) : ((bpp >= 8) ? (8) : (0 + dsc_roundf((bpp - 6) * (8 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (0) : ((bpp >= 8) ? (6) : (0 + dsc_roundf((bpp - 6) * (6 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-2) : ((bpp >= 8) ? (4) : (-2 + dsc_roundf((bpp - 6) * (6 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-4) : ((bpp >= 8) ? (2) : (-4 + dsc_roundf((bpp - 6) * (6 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-6) : ((bpp >= 8) ? (0) : (-6 + dsc_roundf((bpp - 6) * (6 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-8) : ((bpp >= 8) ? (-2) : (-8 + dsc_roundf((bpp - 6) * (6 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-8) : ((bpp >= 8) ? (-4) : (-8 + dsc_roundf((bpp - 6) * (4 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-8) : ((bpp >= 8) ? (-6) : (-8 + dsc_roundf((bpp - 6) * (2 / 2.0))))); + *p++ = (int)((bpp <= 6) ? (-10) : ((bpp >= 8) ? (-8) : (-10 + dsc_roundf((bpp - 6) * (2 / 2.0))))); *p++ = -10; - *p++ = (bpp <= 4) ? (-12) : ((bpp >= 5) ? (-10) : (-12 + dsc_roundf((bpp - 4) * (2 / 1.0)))); + *p++ = (int)((bpp <= 4) ? (-12) : ((bpp >= 5) ? (-10) : (-12 + dsc_roundf((bpp - 4) * (2 / 1.0))))); *p++ = -12; *p++ = -12; *p++ = -12; @@ -179,7 +179,7 @@ void _do_calc_rc_params(struct rc_params *rc, dc_assert_fp_enabled(); - bpp = ((float)drm_bpp / 16.0); + bpp = (float)((float)drm_bpp / 16.0); /* in native_422 or native_420 modes, the bits_per_pixel is double the * target bpp (the latter is what calc_rc_params expects) */ @@ -189,29 +189,29 @@ void _do_calc_rc_params(struct rc_params *rc, rc->rc_quant_incr_limit0 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == 1 && cm == CM_444) ? 1 : 0); rc->rc_quant_incr_limit1 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == 1 && cm == CM_444) ? 1 : 0); - bpp_group = MODE_SELECT(bpp, bpp * 2.0, bpp * 2.0); + bpp_group = MODE_SELECT(bpp, bpp * 2.0f, bpp * 2.0f); switch (cm) { case CM_420: - rc->initial_fullness_offset = (bpp >= 6) ? (2048) : ((bpp <= 4) ? (6144) : ((((bpp > 4) && (bpp <= 5))) ? (6144 - dsc_roundf((bpp - 4) * (512))) : (5632 - dsc_roundf((bpp - 5) * (3584))))); + rc->initial_fullness_offset = (int)((bpp >= 6) ? (2048) : ((bpp <= 4) ? (6144) : ((((bpp > 4) && (bpp <= 5))) ? (6144 - dsc_roundf((bpp - 4) * (512))) : (5632 - dsc_roundf((bpp - 5) * (3584)))))); rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((3 * bpc * 3) - (3 * bpp_group))); rc->second_line_bpg_offset = median3(0, 12, (int)((3 * bpc * 3) - (3 * bpp_group))); break; case CM_422: - rc->initial_fullness_offset = (bpp >= 8) ? (2048) : ((bpp <= 7) ? (5632) : (5632 - dsc_roundf((bpp - 7) * (3584)))); + rc->initial_fullness_offset = (int)((bpp >= 8) ? (2048) : ((bpp <= 7) ? (5632) : (5632 - dsc_roundf((bpp - 7) * (3584))))); rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((3 * bpc * 4) - (3 * bpp_group))); rc->second_line_bpg_offset = 0; break; case CM_444: case CM_RGB: - rc->initial_fullness_offset = (bpp >= 12) ? (2048) : ((bpp <= 8) ? (6144) : ((((bpp > 8) && (bpp <= 10))) ? (6144 - dsc_roundf((bpp - 8) * (512 / 2))) : (5632 - dsc_roundf((bpp - 10) * (3584 / 2))))); + rc->initial_fullness_offset = (int)((bpp >= 12) ? (2048) : ((bpp <= 8) ? (6144) : ((((bpp > 8) && (bpp <= 10))) ? (6144 - dsc_roundf((bpp - 8) * (512 / 2))) : (5632 - dsc_roundf((bpp - 10) * (3584 / 2)))))); rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)(((3 * bpc + (cm == CM_444 ? 0 : 2)) * 3) - (3 * bpp_group))); rc->second_line_bpg_offset = 0; break; } - initial_xmit_delay_factor = (cm == CM_444 || cm == CM_RGB) ? 1.0 : 2.0; - rc->initial_xmit_delay = dsc_roundf(8192.0/2.0/bpp/initial_xmit_delay_factor); + initial_xmit_delay_factor = (float)((cm == CM_444 || cm == CM_RGB) ? 1.0 : 2.0); + rc->initial_xmit_delay = (int)dsc_roundf(8192.0/2.0/bpp/initial_xmit_delay_factor); if (cm == CM_422 || cm == CM_420) slice_width /= 2; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/README.md b/drivers/gpu/drm/amd/display/dc/dml2_0/README.md new file mode 100644 index 000000000000..9e8814fbe52f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/README.md @@ -0,0 +1,31 @@ +# DML2_0 (Display Mode Library 2.0) repository + +## Category to Directory Mapping + +```yaml +directory_categories: + app_tools: + - dml21/build/ + - dml21/src/dml2_unit_test/ + - utils/ + + driver_hw_dependent: + - dml21/inc/bounding_boxes/ + - dml21/src/dml2_cga/ + - dml21/src/dml2_core/ + - dml21/src/dml2_dpmm/ + - dml21/src/dml2_mcg/ + - dml21/src/dml2_pmo/ + - dml21/src/dml2_standalone_libraries/ + - dml21/src/dml2_utm_soc_bb/ + + driver_hw_independent: + - ./ + - dml21/ + - dml21/inc/ + - dml21/src/dml2_top/ + - dml21/src/inc/ + + undefined: + - .github/ +``` diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c index 698d62fb9cf7..241406e9e85a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c @@ -1119,10 +1119,10 @@ static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st * if (p->myPipe->Dppclk == 0.0 || p->myPipe->Dispclk == 0.0) return true; - *p->DSTXAfterScaler = (dml_uint_t) dml_round(s->DPPCycles * p->myPipe->PixelClock / p->myPipe->Dppclk + s->DISPCLKCycles * p->myPipe->PixelClock / p->myPipe->Dispclk + p->DSCDelay, 1.0); + *p->DSTXAfterScaler = (dml_uint_t) dml_round(s->DPPCycles * p->myPipe->PixelClock / p->myPipe->Dppclk + s->DISPCLKCycles * p->myPipe->PixelClock / p->myPipe->Dispclk + p->DSCDelay, true); *p->DSTXAfterScaler = (dml_uint_t) dml_round(*p->DSTXAfterScaler + (p->myPipe->ODMMode != dml_odm_mode_bypass ? 18 : 0) + (p->myPipe->DPPPerSurface - 1) * p->DPP_RECOUT_WIDTH + ((p->myPipe->ODMMode == dml_odm_mode_split_1to2 || p->myPipe->ODMMode == dml_odm_mode_mso_1to2) ? (dml_float_t)p->myPipe->HActive / 2.0 : 0) + - ((p->myPipe->ODMMode == dml_odm_mode_mso_1to4) ? (dml_float_t)p->myPipe->HActive * 3.0 / 4.0 : 0), 1.0); + ((p->myPipe->ODMMode == dml_odm_mode_mso_1to4) ? (dml_float_t)p->myPipe->HActive * 3.0 / 4.0 : 0), true); #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: DPPCycles = %u\n", __func__, s->DPPCycles); @@ -2626,18 +2626,18 @@ static dml_uint_t CalculateVMAndRowBytes( *PixelPTEBytesPerRow_one_row_per_frame = (dml_uint_t)((dml_float_t) *dpte_row_width_ub_one_row_per_frame / (dml_float_t) *PixelPTEReqWidth * *PTERequestSize); if (SurfaceTiling == dml_sw_linear) { - *dpte_row_height = (dml_uint_t)(dml_min(128, 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1))); + *dpte_row_height = (dml_uint_t)(dml_min(128, (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)))); dml_print("DML::%s: dpte_row_height term 1 = %u\n", __func__, PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch); dml_print("DML::%s: dpte_row_height term 2 = %f\n", __func__, dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch)); dml_print("DML::%s: dpte_row_height term 3 = %f\n", __func__, dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); - dml_print("DML::%s: dpte_row_height term 4 = %u\n", __func__, 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); + dml_print("DML::%s: dpte_row_height term 4 = %u\n", __func__, (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1))); dml_print("DML::%s: dpte_row_height = %u\n", __func__, *dpte_row_height); *dpte_row_width_ub = (dml_uint_t)(dml_ceil(((dml_float_t) Pitch * (dml_float_t) *dpte_row_height - 1), (dml_float_t) *PixelPTEReqWidth) + *PixelPTEReqWidth); *PixelPTEBytesPerRow = (dml_uint_t)((dml_float_t) *dpte_row_width_ub / (dml_float_t) *PixelPTEReqWidth * *PTERequestSize); // VBA_DELTA, VBA doesn't have programming value for pte row height linear. - *dpte_row_height_linear = 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * PixelPTEReqWidth_linear / Pitch), 1); + *dpte_row_height_linear = (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * PixelPTEReqWidth_linear / Pitch), 1)); if (*dpte_row_height_linear > 128) *dpte_row_height_linear = 128; @@ -4301,7 +4301,7 @@ static void CalculateSwathAndDETConfiguration(struct display_mode_lib_scratch_st *p->compbuf_reserved_space_64b = 2 * p->PixelChunkSizeInKByte * 1024 / 64; if (*p->UnboundedRequestEnabled) { - *p->compbuf_reserved_space_64b = dml_max(*p->compbuf_reserved_space_64b, + *p->compbuf_reserved_space_64b = (dml_uint_t)dml_max(*p->compbuf_reserved_space_64b, (dml_float_t)(p->ROBBufferSizeInKByte * 1024/64) - (dml_float_t)(RoundedUpSwathSizeBytesY[SurfaceDoingUnboundedRequest] * TTUFIFODEPTH / MAXIMUMCOMPRESSION/64)); } @@ -6178,9 +6178,9 @@ static void CalculateImmediateFlipBandwithSupport( static dml_uint_t MicroSecToVertLines(dml_uint_t num_us, dml_uint_t h_total, dml_float_t pixel_clock) { - dml_uint_t lines_time_in_ns = 1000.0 * (h_total * 1000.0) / (pixel_clock * 1000.0); + dml_uint_t lines_time_in_ns = (dml_uint_t)(1000.0 * (h_total * 1000.0) / (pixel_clock * 1000.0)); - return dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); + return (dml_uint_t)dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0); } /// @brief Calculate the maximum vstartup for mode support and mode programming consideration @@ -6207,9 +6207,9 @@ static dml_uint_t CalculateMaxVStartup( // + 2 is because // 1 -> VStartup_start should be 1 line before VSync // 1 -> always reserve 1 line between start of VBlank to VStartup signal - dml_uint_t vblank_nom_vsync_capped = dml_max(vblank_nom_input, + dml_uint_t vblank_nom_vsync_capped = (dml_uint_t)dml_max(vblank_nom_input, timing->VTotal[plane_idx] - timing->VActive[plane_idx] - timing->VFrontPorch[plane_idx] + 2); - dml_uint_t vblank_nom_max_allowed_capped = dml_min(vblank_nom_vsync_capped, max_allowed_vblank_nom); + dml_uint_t vblank_nom_max_allowed_capped = (dml_uint_t)dml_min(vblank_nom_vsync_capped, max_allowed_vblank_nom); dml_uint_t vblank_avail = (vblank_nom_max_allowed_capped == 0) ? vblank_nom_default_in_line : vblank_nom_max_allowed_capped; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c index b2fada6c44c3..3939a0d8b835 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c @@ -80,7 +80,7 @@ static inline float dcn_bw_pow(float a, float exp) /*ASSERT(exp == (int)exp);*/ if ((int)exp == 0) return 1; - temp = dcn_bw_pow(a, (int)(exp / 2)); + temp = dcn_bw_pow(a, (float)(exp / 2)); if (((int)exp % 2) == 0) { return temp * temp; } else { @@ -110,7 +110,7 @@ dml_float_t dml_ceil(dml_float_t x, dml_float_t granularity) if (granularity == 0) return 0; //return (dml_float_t) (ceil(x / granularity) * granularity); - return (dml_float_t)dcn_bw_ceil2(x, granularity); + return (dml_float_t)dcn_bw_ceil2((float)x, (float)granularity); } dml_float_t dml_floor(dml_float_t x, dml_float_t granularity) @@ -118,7 +118,7 @@ dml_float_t dml_floor(dml_float_t x, dml_float_t granularity) if (granularity == 0) return 0; //return (dml_float_t) (floor(x / granularity) * granularity); - return (dml_float_t)dcn_bw_floor2(x, granularity); + return (dml_float_t)dcn_bw_floor2((float)x, (float)granularity); } dml_float_t dml_min(dml_float_t x, dml_float_t y) @@ -168,12 +168,12 @@ dml_float_t dml_max5(dml_float_t a, dml_float_t b, dml_float_t c, dml_float_t d, } dml_float_t dml_log(dml_float_t x, dml_float_t base) { - return (dml_float_t) (_log(x) / _log(base)); + return (dml_float_t) (_log((float)x) / _log((float)base)); } dml_float_t dml_log2(dml_float_t x) { - return (dml_float_t) (_log(x) / _log(2)); + return (dml_float_t) (_log((float)x) / _log(2.0f)); } dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding) @@ -184,19 +184,19 @@ dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding) // else { // return round(val); double round_pt = 0.5; - double ceil = dml_ceil(val, 1); - double floor = dml_floor(val, 1); + double ceil = dml_ceil(val, 1.0); + double floor = dml_floor(val, 1.0); if (val - floor >= round_pt) - return ceil; + return (dml_float_t)ceil; else - return floor; + return (dml_float_t)floor; // } } dml_float_t dml_pow(dml_float_t base, int exp) { - return (dml_float_t) dcn_bw_pow(base, exp); + return (dml_float_t) dcn_bw_pow((float)base, (float)exp); } dml_uint_t dml_round_to_multiple(dml_uint_t num, dml_uint_t multiple, dml_bool_t up) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index 476030193f14..25557c99a28e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -90,6 +90,8 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf struct pipe_ctx *pipe_ctx, struct dml2_context *dml_ctx) { + const unsigned int min_v_front_porch = (stream->timing.flags.INTERLACE != 0) ? 2 : 1; + unsigned int hblank_start, vblank_start; uint64_t min_hardware_refresh_in_uhz; uint32_t pix_clk_100hz; @@ -97,7 +99,8 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding; timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; timing->h_front_porch = stream->timing.h_front_porch; - timing->v_front_porch = stream->timing.v_front_porch; + timing->v_front_porch = stream->timing.v_front_porch > min_v_front_porch ? + stream->timing.v_front_porch : min_v_front_porch; timing->pixel_clock_khz = stream->timing.pix_clk_100hz / 10; if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10; @@ -116,7 +119,7 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf if (hblank_start < stream->timing.h_addressable) timing->h_blank_end = 0; - vblank_start = stream->timing.v_total - stream->timing.v_front_porch; + vblank_start = timing->v_total - timing->v_front_porch; timing->v_blank_end = vblank_start - stream->timing.v_addressable - stream->timing.v_border_top - stream->timing.v_border_bottom; @@ -610,6 +613,7 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm plane->composition.viewport.stationary = false; +#ifndef TRIM_CM2 if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { plane->tdlut.setup_for_tdlut = true; @@ -640,7 +644,39 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm break; } } +#else + if (plane_state->cm.flags.bits.lut3d_dma_enable) { + plane->tdlut.setup_for_tdlut = true; + switch (plane_state->cm.lut3d_dma.swizzle) { + case CM_LUT_3D_SWIZZLE_LINEAR_RGB: + case CM_LUT_3D_SWIZZLE_LINEAR_BGR: + plane->tdlut.tdlut_addressing_mode = dml2_tdlut_sw_linear; + break; + case CM_LUT_1D_PACKED_LINEAR: + plane->tdlut.tdlut_addressing_mode = dml2_tdlut_simple_linear; + break; + } + + switch (plane_state->cm.lut3d_dma.size) { + case CM_LUT_SIZE_171717: + plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube; + break; + case CM_LUT_SIZE_333333: + plane->tdlut.tdlut_width_mode = dml2_tdlut_width_33_cube; + break; + // handling when use case and HW support available + case CM_LUT_SIZE_454545: + case CM_LUT_SIZE_656565: + break; + case CM_LUT_SIZE_NONE: + case CM_LUT_SIZE_999: + default: + //plane->tdlut.tdlut_width_mode = dml2_tdlut_width_flatten; // dml2_tdlut_width_flatten undefined + break; + } + } +#endif // TRIM_CM2 plane->tdlut.setup_for_tdlut |= dml_ctx->config.force_tdlut_enable; plane->dynamic_meta_data.enable = false; @@ -848,10 +884,10 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.socclk_khz; context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz; context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz; - context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency; - context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency; - context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency; - context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = (int)in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period; context->bw_ctx.bw.dcn.clk.zstate_support = in_ctx->v21.mode_programming.programming->z8_stutter.supported_in_blank; /*ignore meets_eco since it is not used*/ } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c index 732de97335fa..835fece1d46a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c @@ -267,7 +267,7 @@ static struct dc_stream_state *dml21_add_phantom_stream(struct dml2_context *dml phantom_stream->dst.height = stream_programming->phantom_stream.descriptor.timing.v_active; phantom_stream->src.y = 0; - phantom_stream->src.height = (double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height; + phantom_stream->src.height = (int)((double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height); phantom_stream->use_dynamic_meta = false; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h index 98b26116cdc1..dff903a103db 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h @@ -19,7 +19,6 @@ enum dml2_project_id { dml2_project_dcn4x_stage1, dml2_project_dcn4x_stage2, dml2_project_dcn4x_stage2_auto_drr_svp, - dml2_project_dcn40, dml2_project_dcn42, }; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c index 6cad99c21139..67e307fa4310 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c @@ -21,7 +21,6 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance case dml2_project_dcn4x_stage1: result = false; break; - case dml2_project_dcn40: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: out->initialize = &core_dcn4_initialize; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c index 39965ff2e111..be0517e10104 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c @@ -33,7 +33,6 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance out->map_watermarks = &dummy_map_watermarks; result = true; break; - case dml2_project_dcn40: case dml2_project_dcn4x_stage2: out->map_mode_to_soc_dpm = &dpmm_dcn3_map_mode_to_soc_dpm; out->map_watermarks = &dummy_map_watermarks; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c index 3eaeff39ee79..ef8b75fed9a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c @@ -22,7 +22,7 @@ static bool build_min_clk_table_coarse_grained(const struct dml2_soc_bb *soc_bb, min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], &soc_bb->clk_table.dram_config, soc_bb->clk_table.wck_ratio.clk_values_khz[i]); min_table->dram_bw_table.entries[i].min_uclk_khz = soc_bb->clk_table.uclk.clk_values_khz[i]; - } else { + } else if (soc_bb->clk_table.uclk.num_clk_values > 0) { min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = min_table->dram_bw_table.entries[soc_bb->clk_table.uclk.num_clk_values - 1].pre_derate_dram_bw_kbps; min_table->dram_bw_table.entries[i].min_uclk_khz = soc_bb->clk_table.uclk.clk_values_khz[soc_bb->clk_table.uclk.num_clk_values - 1]; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c index fb0b0ac547c7..270283332cc1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c @@ -27,7 +27,6 @@ bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance * out->build_min_clock_table = &dummy_build_min_clock_table; result = true; break; - case dml2_project_dcn40: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: out->build_min_clock_table = &mcg_dcn4_build_min_clock_table; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c index 83802aac11cd..af2ba7d08a61 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c @@ -3,8 +3,8 @@ // Copyright 2024 Advanced Micro Devices, Inc. #include "dml2_pmo_factory.h" -#include "dml2_pmo_dcn3.h" #include "dml2_pmo_dcn4_fams2.h" +#include "dml2_pmo_dcn3.h" #include "dml2_external_lib_deps.h" static bool dummy_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out) @@ -40,7 +40,6 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance * out->optimize_dcc_mcache = pmo_dcn4_fams2_optimize_dcc_mcache; result = true; break; - case dml2_project_dcn40: case dml2_project_dcn4x_stage2: out->initialize = pmo_dcn3_initialize; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c index a6c5031f69c1..04860b6790df 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c @@ -17,7 +17,6 @@ bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out) case dml2_project_dcn4x_stage1: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: - case dml2_project_dcn40: case dml2_project_dcn42: return dml2_top_soc15_initialize_instance(in_out); case dml2_project_invalid: diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h deleted file mode 100644 index 14d0ae03dce6..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: MIT -// -// Copyright 2024 Advanced Micro Devices, Inc. - -#ifndef __DML2_TOP_LEGACY_H__ -#define __DML2_TOP_LEGACY_H__ -#include "dml2_internal_shared_types.h" -bool dml2_top_legacy_initialize_instance(struct dml2_initialize_instance_in_out *in_out); -#endif /* __DML2_TOP_LEGACY_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c index 9bbe4e058be7..4543a60a0683 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c @@ -244,9 +244,9 @@ static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context continue; // Round up - refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + + refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 + pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) - / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); + / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total)); /* SubVP pipe candidate requirements: * - Refresh rate < 120hz * - Not able to switch in vactive naturally (switching in active means the @@ -264,8 +264,8 @@ static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context pipe = &context->res_ctx.pipe_ctx[i]; if (num_pipes <= free_pipes) { struct dc_stream_state *stream = pipe->stream; - unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / - (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; + unsigned int frame_us = (unsigned int)((stream->timing.v_total * stream->timing.h_total / + (double)(stream->timing.pix_clk_100hz * 100)) * 1000000); if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) { *index = i; max_frame_time = frame_us; @@ -382,8 +382,8 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c phantom->timing.v_addressable; // Round up when calculating microschedule time (+ 1 at the end) - time_us = (microschedule_lines * phantom->timing.h_total) / - (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 + + time_us = (uint32_t)((microschedule_lines * phantom->timing.h_total) / + (double)(phantom->timing.pix_clk_100hz * 100) * 1000000) + ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us + ctx->config.svp_pstate.subvp_fw_processing_delay_us + 1; if (time_us > max_microschedule_us) @@ -402,16 +402,16 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c if (index < 2 || !subvp_pipes[0] || !subvp_pipes[1]) return false; - vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / - (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / - (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * + vactive1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / + (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000); + vactive2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / + (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000); + vblank1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * subvp_pipes[0]->stream->timing.h_total) / - (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; - vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * + (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100) * 1000000); + vblank2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * subvp_pipes[1]->stream->timing.h_total) / - (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; + (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100) * 1000000); if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us && (vactive2_us - vblank1_us) / 2 > max_microschedule_us) @@ -445,13 +445,13 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context struct dc_crtc_timing *main_timing = NULL; struct dc_crtc_timing *phantom_timing = NULL; struct dc_stream_state *phantom_stream; - int16_t prefetch_us = 0; - int16_t mall_region_us = 0; - int16_t drr_frame_us = 0; // nominal frame time - int16_t subvp_active_us = 0; - int16_t stretched_drr_us = 0; - int16_t drr_stretched_vblank_us = 0; - int16_t max_vblank_mallregion = 0; + int32_t prefetch_us = 0; + int32_t mall_region_us = 0; + int32_t drr_frame_us = 0; // nominal frame time + int32_t subvp_active_us = 0; + int32_t stretched_drr_us = 0; + int32_t drr_stretched_vblank_us = 0; + int32_t max_vblank_mallregion = 0; // Find SubVP pipe for (i = 0; i < ctx->config.dcn_pipe_count; i++) { @@ -475,19 +475,19 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream); main_timing = &pipe->stream->timing; phantom_timing = &phantom_stream->timing; - prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / + prefetch_us = (int32_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + - ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us; - subvp_active_us = main_timing->v_addressable * main_timing->h_total / - (double)(main_timing->pix_clk_100hz * 100) * 1000000; - drr_frame_us = drr_timing->v_total * drr_timing->h_total / - (double)(drr_timing->pix_clk_100hz * 100) * 1000000; + ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us); + subvp_active_us = (int32_t)(main_timing->v_addressable * main_timing->h_total / + (double)(main_timing->pix_clk_100hz * 100) * 1000000); + drr_frame_us = (int32_t)(drr_timing->v_total * drr_timing->h_total / + (double)(drr_timing->pix_clk_100hz * 100) * 1000000); // P-State allow width and FW delays already included phantom_timing->v_addressable - mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / - (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; + mall_region_us = (int32_t)(phantom_timing->v_addressable * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000); stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US; - drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / - (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); + drr_stretched_vblank_us = (int32_t)((drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / + (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us)); max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the @@ -526,12 +526,12 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state * bool schedulable = false; uint32_t i = 0; uint8_t vblank_index = 0; - uint16_t prefetch_us = 0; - uint16_t mall_region_us = 0; - uint16_t vblank_frame_us = 0; - uint16_t subvp_active_us = 0; - uint16_t vblank_blank_us = 0; - uint16_t max_vblank_mallregion = 0; + uint32_t prefetch_us = 0; + uint32_t mall_region_us = 0; + uint32_t vblank_frame_us = 0; + uint32_t subvp_active_us = 0; + uint32_t vblank_blank_us = 0; + uint32_t max_vblank_mallregion = 0; struct dc_crtc_timing *main_timing = NULL; struct dc_crtc_timing *phantom_timing = NULL; struct dc_crtc_timing *vblank_timing = NULL; @@ -581,24 +581,27 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state * vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing; // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe // Also include the prefetch end to mallstart delay time - prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / + prefetch_us = (uint32_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + - ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us; + ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us); // P-State allow width and FW delays already included phantom_timing->v_addressable - mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / - (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; - vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / - (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; - vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / - (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; - subvp_active_us = main_timing->v_addressable * main_timing->h_total / - (double)(main_timing->pix_clk_100hz * 100) * 1000000; + mall_region_us = (uint32_t)(phantom_timing->v_addressable * phantom_timing->h_total / + (double)(phantom_timing->pix_clk_100hz * 100) * 1000000); + vblank_frame_us = (uint32_t)(vblank_timing->v_total * vblank_timing->h_total / + (double)(vblank_timing->pix_clk_100hz * 100) * 1000000); + vblank_blank_us = (uint32_t)((vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / + (double)(vblank_timing->pix_clk_100hz * 100) * 1000000); + subvp_active_us = (uint32_t)(main_timing->v_addressable * main_timing->h_total / + (double)(main_timing->pix_clk_100hz * 100) * 1000000); max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; + const uint64_t required_us = (uint64_t)prefetch_us + + (uint64_t)vblank_frame_us + + (uint64_t)max_vblank_mallregion; // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, // and the max of (VBLANK blanking time, MALL region) // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0) - if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0) + if ((uint64_t)subvp_active_us > required_us) schedulable = true; } return schedulable; @@ -694,10 +697,10 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state } // Calculate lines required for pstate allow width and FW processing delays - pstate_width_fw_delay_lines = ((double)(ctx->config.svp_pstate.subvp_fw_processing_delay_us + + pstate_width_fw_delay_lines = (uint32_t)(((double)(ctx->config.svp_pstate.subvp_fw_processing_delay_us + ctx->config.svp_pstate.subvp_pstate_allow_width_us) / 1000000) * (ref_pipe->stream->timing.pix_clk_100hz * 100) / - (double)ref_pipe->stream->timing.h_total; + (double)ref_pipe->stream->timing.h_total); // DML calculation for MALL region doesn't take into account FW delay // and required pstate allow width for multi-display cases @@ -712,7 +715,7 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state fp_and_sync_width_time = (phantom_stream->timing.v_front_porch + phantom_stream->timing.v_sync_width) * line_time; if ((svp_vstartup * line_time) + fp_and_sync_width_time > cvt_rb_vblank_max) { - svp_vstartup = (cvt_rb_vblank_max - fp_and_sync_width_time) / line_time; + svp_vstartup = (unsigned int)((cvt_rb_vblank_max - fp_and_sync_width_time) / line_time); } // For backporch of phantom pipe, use vstartup of the main pipe diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c index ef693f608d59..ab2964811c5b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c @@ -123,9 +123,9 @@ int dml2_policy_build_synthetic_soc_states(struct dml2_policy_build_synthetic_so struct dml2_policy_build_synthetic_soc_states_params *p) { int i, j; - unsigned int min_fclk_mhz = p->in_states->state_array[0].fabricclk_mhz; - unsigned int min_dcfclk_mhz = p->in_states->state_array[0].dcfclk_mhz; - unsigned int min_socclk_mhz = p->in_states->state_array[0].socclk_mhz; + unsigned int min_fclk_mhz = (unsigned int)p->in_states->state_array[0].fabricclk_mhz; + unsigned int min_dcfclk_mhz = (unsigned int)p->in_states->state_array[0].dcfclk_mhz; + unsigned int min_socclk_mhz = (unsigned int)p->in_states->state_array[0].socclk_mhz; int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c index 8e0997441ee0..0d8ff236c6d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c @@ -508,11 +508,11 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, /* DCFCLK stas values are project specific */ if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) || (dml2->v20.dml_core_ctx.project == dml_project_dcn321)) { - p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz; + p->dcfclk_stas_mhz[0] = (int)p->in_states->state_array[0].dcfclk_mhz; p->dcfclk_stas_mhz[1] = 615; p->dcfclk_stas_mhz[2] = 906; p->dcfclk_stas_mhz[3] = 1324; - p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz; + p->dcfclk_stas_mhz[4] = (int)p->in_states->state_array[1].dcfclk_mhz; } else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && dml2->v20.dml_core_ctx.project != dml_project_dcn36 && dml2->v20.dml_core_ctx.project != dml_project_dcn351) { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c index 86567e232415..5ed14f694fb0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c @@ -255,7 +255,7 @@ static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, str pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx); pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx); - ASSERT(pipe_ctx->stream_res.tg->inst >= 0 && pipe_ctx->stream_res.tg->inst <= 0xFF); + ASSERT(pipe_ctx->stream_res.tg->inst <= 0xFF); pipe_ctx->pipe_dlg_param.otg_inst = (unsigned char)pipe_ctx->stream_res.tg->inst; pipe_ctx->pipe_dlg_param.hactive = hactive; @@ -333,7 +333,7 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont } context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb; - context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000; + context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = (int)(dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000); if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz) context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz; @@ -362,10 +362,10 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; - context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz - * 1000; - context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz - * 1000; + context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = (int)(in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz + * 1000); + context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = (int)(in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz + * 1000); if (dc->config.forced_clocks || dc->debug.max_disp_clk) { context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; @@ -375,18 +375,18 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx) { - watermark->urgent_ns = dml_get_wm_urgent(dml_core_ctx) * 1000; - watermark->cstate_pstate.cstate_enter_plus_exit_ns = dml_get_wm_stutter_enter_exit(dml_core_ctx) * 1000; - watermark->cstate_pstate.cstate_exit_ns = dml_get_wm_stutter_exit(dml_core_ctx) * 1000; - watermark->cstate_pstate.pstate_change_ns = dml_get_wm_dram_clock_change(dml_core_ctx) * 1000; - watermark->pte_meta_urgent_ns = dml_get_wm_memory_trip(dml_core_ctx) * 1000; - watermark->frac_urg_bw_nom = dml_get_fraction_of_urgent_bandwidth(dml_core_ctx) * 1000; - watermark->frac_urg_bw_flip = dml_get_fraction_of_urgent_bandwidth_imm_flip(dml_core_ctx) * 1000; - watermark->urgent_latency_ns = dml_get_urgent_latency(dml_core_ctx) * 1000; - watermark->cstate_pstate.fclk_pstate_change_ns = dml_get_wm_fclk_change(dml_core_ctx) * 1000; - watermark->usr_retraining_ns = dml_get_wm_usr_retraining(dml_core_ctx) * 1000; - watermark->cstate_pstate.cstate_enter_plus_exit_z8_ns = dml_get_wm_z8_stutter_enter_exit(dml_core_ctx) * 1000; - watermark->cstate_pstate.cstate_exit_z8_ns = dml_get_wm_z8_stutter(dml_core_ctx) * 1000; + watermark->urgent_ns = (uint32_t)(dml_get_wm_urgent(dml_core_ctx) * 1000); + watermark->cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(dml_get_wm_stutter_enter_exit(dml_core_ctx) * 1000); + watermark->cstate_pstate.cstate_exit_ns = (uint32_t)(dml_get_wm_stutter_exit(dml_core_ctx) * 1000); + watermark->cstate_pstate.pstate_change_ns = (uint32_t)(dml_get_wm_dram_clock_change(dml_core_ctx) * 1000); + watermark->pte_meta_urgent_ns = (uint32_t)(dml_get_wm_memory_trip(dml_core_ctx) * 1000); + watermark->frac_urg_bw_nom = (uint32_t)(dml_get_fraction_of_urgent_bandwidth(dml_core_ctx) * 1000); + watermark->frac_urg_bw_flip = (uint32_t)(dml_get_fraction_of_urgent_bandwidth_imm_flip(dml_core_ctx) * 1000); + watermark->urgent_latency_ns = (uint32_t)(dml_get_urgent_latency(dml_core_ctx) * 1000); + watermark->cstate_pstate.fclk_pstate_change_ns = (uint32_t)(dml_get_wm_fclk_change(dml_core_ctx) * 1000); + watermark->usr_retraining_ns = (uint32_t)(dml_get_wm_usr_retraining(dml_core_ctx) * 1000); + watermark->cstate_pstate.cstate_enter_plus_exit_z8_ns = (uint32_t)(dml_get_wm_z8_stutter_enter_exit(dml_core_ctx) * 1000); + watermark->cstate_pstate.cstate_exit_z8_ns = (uint32_t)(dml_get_wm_z8_stutter(dml_core_ctx) * 1000); } unsigned int dml2_calc_max_scaled_time( @@ -434,9 +434,9 @@ void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib for (j = 0 ; j < 4; j++) { /*current dml only has one set of watermark, need to follow up*/ bw_writeback->mcif_wb_arb[i].cli_watermark[j] = - dml_get_wm_writeback_urgent(dml_core_ctx) * 1000; + (unsigned int)(dml_get_wm_writeback_urgent(dml_core_ctx) * 1000); bw_writeback->mcif_wb_arb[i].pstate_watermark[j] = - dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000; + (unsigned int)(dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000); } if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) { /* time_per_pixel should be in u6.6 format */ @@ -450,7 +450,7 @@ void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib wbif_mode, wb_arb_params->cli_watermark[0]); /*not required any more*/ bw_writeback->mcif_wb_arb[i].dram_speed_change_duration = - dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000; + (unsigned int)(dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000); } } diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c index 2bdd063cc1e1..53b21adc6267 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c @@ -307,7 +307,7 @@ void dpp1_cm_set_output_csc_default( { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); const uint16_t *regval = NULL; - int arr_size; + uint32_t arr_size; regval = find_color_matrix(colorspace, &arr_size); if (regval == NULL) { @@ -824,7 +824,7 @@ void dpp1_program_input_lut( struct dpp *dpp_base, const struct dc_gamma *gamma) { - int i; + unsigned int i; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); bool rama_occupied = false; uint32_t ram_num; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c index 0d2c9fcd3362..b9adf8433b36 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c @@ -256,7 +256,7 @@ static void dpp1_dscl_set_scaler_filter( for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { for (pair = 0; pair < tap_pairs; pair++) { even_coef = filter[phase * taps + 2 * pair]; - if ((pair * 2 + 1) < taps) + if ((uint32_t)(pair * 2 + 1) < taps) odd_coef = filter[phase * taps + 2 * pair + 1]; else odd_coef = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index e7880fc61b4a..2ebc738c37f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -517,11 +517,16 @@ bool dpp3_get_optimal_number_of_taps( else if (max_taps_c < min_taps_c) return false; - if (scl_data->taps.v_taps > max_taps_y) - scl_data->taps.v_taps = max_taps_y; + { + uint32_t max_supported_taps_y = (uint32_t)max_taps_y; + uint32_t max_supported_taps_c = (uint32_t)max_taps_c; - if (scl_data->taps.v_taps_c > max_taps_c) - scl_data->taps.v_taps_c = max_taps_c; + if (scl_data->taps.v_taps > max_supported_taps_y) + scl_data->taps.v_taps = max_supported_taps_y; + + if (scl_data->taps.v_taps_c > max_supported_taps_c) + scl_data->taps.v_taps_c = max_supported_taps_c; + } if (!dpp->ctx->dc->debug.always_scale) { if (IDENTITY_RATIO(scl_data->ratios.horz)) { @@ -543,7 +548,7 @@ bool dpp3_get_optimal_number_of_taps( static void dpp3_deferred_update(struct dpp *dpp_base) { - int bypass_state; + uint32_t bypass_state; struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); if (dpp_base->deferred_reg_writes.bits.disable_dscl) { @@ -598,6 +603,7 @@ static void dpp3_power_on_blnd_lut( if (power_on) { REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0); REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5); + dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false; } else { dpp_base->ctx->dc->optimized_required = true; dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true; @@ -615,6 +621,7 @@ static void dpp3_power_on_hdr3dlut( if (power_on) { REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0); REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5); + dpp_base->deferred_reg_writes.bits.disable_3dlut = false; } else { dpp_base->ctx->dc->optimized_required = true; dpp_base->deferred_reg_writes.bits.disable_3dlut = true; @@ -632,6 +639,7 @@ static void dpp3_power_on_shaper( if (power_on) { REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0); REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5); + dpp_base->deferred_reg_writes.bits.disable_shaper = false; } else { dpp_base->ctx->dc->optimized_required = true; dpp_base->deferred_reg_writes.bits.disable_shaper = true; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c index 8170a86ad0ea..e01d8e9672fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c @@ -136,6 +136,7 @@ static void dpp3_power_on_gamcor_lut( if (dpp_base->ctx->dc->caps.ips_v2_support) REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, 1); REG_WAIT(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, 0, 1, 5); + dpp_base->deferred_reg_writes.bits.disable_gamcor = false; } else { dpp_base->ctx->dc->optimized_required = true; dpp_base->deferred_reg_writes.bits.disable_gamcor = true; @@ -317,7 +318,7 @@ void dpp3_set_hdr_multiplier( static void program_gamut_remap( struct dcn3_dpp *dpp, const uint16_t *regval, - int select) + unsigned int select) { uint16_t selection = 0; struct color_matrices_reg gam_regs; @@ -379,7 +380,7 @@ void dpp3_cm_set_gamut_remap( { struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); int i = 0; - int gamut_mode; + uint32_t gamut_mode; if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) /* Bypass if type is bypass or hw */ diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c index 4f3b48ed8679..340111e3deac 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c @@ -176,7 +176,7 @@ static void dpp401_program_cursor_csc( struct color_matrices_reg cur_matrix_regs; unsigned int i; const uint16_t *regval = NULL; - int arr_size = sizeof(dpp_input_csc_matrix) / sizeof(struct dpp_input_csc_matrix); + unsigned int arr_size = sizeof(dpp_input_csc_matrix) / sizeof(struct dpp_input_csc_matrix); if (color_space < COLOR_SPACE_YCBCR601) { REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS); diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 8b7e55e337d3..62994aecf499 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -161,6 +161,7 @@ static void dpp401_power_on_dscl( REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 100); } else REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5); + dpp->base.deferred_reg_writes.bits.disable_dscl = false; } else { if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) { dpp->base.ctx->dc->optimized_required = true; @@ -253,7 +254,7 @@ static void dpp401_dscl_set_scaler_filter( for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { for (pair = 0; pair < tap_pairs; pair++) { even_coef = filter[phase * taps + 2 * pair]; - if ((pair * 2 + 1) < taps) + if ((uint32_t)(pair * 2 + 1) < taps) odd_coef = filter[phase * taps + 2 * pair + 1]; else odd_coef = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c index c126fb9d5bfa..f60e084068c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c @@ -269,10 +269,10 @@ static void dpp42_dpp_setup( tbl_entry.color_space = input_color_space; - if (color_space >= COLOR_SPACE_YCBCR601) - select = INPUT_CSC_SELECT_ICSC; - else + if (dpp3_should_bypass_post_csc_for_colorspace(color_space)) select = INPUT_CSC_SELECT_BYPASS; + else + select = INPUT_CSC_SELECT_ICSC; dpp3_program_post_csc(dpp_base, color_space, select, &tbl_entry); @@ -280,6 +280,14 @@ static void dpp42_dpp_setup( dpp3_program_post_csc(dpp_base, color_space, select, NULL); } } +static void dcn42_dpp_force_disable_cursor(struct dpp *dpp_base) +{ + struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); + + /* Force disable cursor */ + REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, 0); + dpp_base->pos.cur0_ctl.bits.cur0_enable = 0; +} static struct dpp_funcs dcn42_dpp_funcs = { .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, @@ -302,6 +310,7 @@ static struct dpp_funcs dcn42_dpp_funcs = { .dpp_cm_hist_control = dpp42_dpp_cm_hist_control, .dpp_cm_hist_read = dpp42_dpp_cm_hist_read, .dpp_read_reg_state = dpp30_read_reg_state, + .dpp_force_disable_cursor = dcn42_dpp_force_disable_cursor, }; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 8dfb6dd14eb2..9aa5adb15103 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -858,19 +858,20 @@ static bool decide_dsc_target_bpp_x16( int *target_bpp_x16) { struct dc_dsc_bw_range range; + uint32_t target_bandwidth_kbps_u = (uint32_t)target_bandwidth_kbps; *target_bpp_x16 = 0; if (decide_dsc_bandwidth_range(policy->min_target_bpp * 16, policy->max_target_bpp * 16, num_slices_h, dsc_common_caps, timing, link_encoding, &range)) { - if (target_bandwidth_kbps >= range.stream_kbps) { + if (target_bandwidth_kbps_u >= range.stream_kbps) { if (policy->enable_dsc_when_not_needed || options->force_dsc_when_not_needed) /* enable max bpp even dsc is not needed */ *target_bpp_x16 = range.max_target_bpp_x16; - } else if (target_bandwidth_kbps >= range.max_kbps) { + } else if (target_bandwidth_kbps_u >= range.max_kbps) { /* use max target bpp allowed */ *target_bpp_x16 = range.max_target_bpp_x16; - } else if (target_bandwidth_kbps >= range.min_kbps) { + } else if (target_bandwidth_kbps_u >= range.min_kbps) { /* use target bpp that can take entire target bandwidth */ *target_bpp_x16 = compute_bpp_x16_from_target_bandwidth( target_bandwidth_kbps, timing, num_slices_h, @@ -1053,10 +1054,11 @@ static bool setup_dsc_config( int max_slices_h = 0; int num_slices_h = 0; int pic_width; + uint32_t pic_width_u; int slice_width; int target_bpp; int sink_per_slice_throughput_mps; - int branch_max_throughput_mps = 0; + uint32_t branch_max_throughput_mps = 0; bool is_dsc_possible = false; int pic_height; int slice_height; @@ -1066,12 +1068,13 @@ static bool setup_dsc_config( dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy, link_encoding); pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; + pic_width_u = (uint32_t)pic_width; pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; if (!dsc_sink_caps->is_dsc_supported) goto done; - if (dsc_sink_caps->branch_max_line_width && dsc_sink_caps->branch_max_line_width < pic_width) + if (dsc_sink_caps->branch_max_line_width && dsc_sink_caps->branch_max_line_width < pic_width_u) goto done; // Intersect decoder with encoder DSC caps and validate DSC settings @@ -1333,7 +1336,7 @@ uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing, uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps( const struct dc_crtc_timing *timing, - const int num_slices_h, + const uint32_t num_slices_h, const bool is_dp) { struct fixed31_32 max_dsc_overhead; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 6e1e759462bf..cede9588bad8 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -168,8 +168,9 @@ bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct ds { struct dsc_optc_config dsc_optc_cfg; struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); + uint32_t max_image_width = (uint32_t)dsc20->max_image_width; - if (dsc_cfg->pic_width > dsc20->max_image_width) + if (dsc_cfg->pic_width > max_image_width) return false; return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); @@ -227,9 +228,9 @@ bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) { struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); - int dsc_clock_en; - int dsc_fw_config; - int enabled_opp_pipe; + uint32_t dsc_clock_en; + uint32_t dsc_fw_config; + uint32_t enabled_opp_pipe; DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); @@ -252,7 +253,7 @@ void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) void dsc2_disable(struct display_stream_compressor *dsc) { struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); - int dsc_clock_en; + uint32_t dsc_clock_en; DC_LOG_DSC("disable DSC %d", dsc->inst); @@ -405,20 +406,20 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; - dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; - dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; - dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; + dsc_reg_vals->pps.dsc_version_minor = (u8)dsc_cfg->dc_dsc_cfg.version_minor; + dsc_reg_vals->pps.pic_width = (u16)dsc_cfg->pic_width; + dsc_reg_vals->pps.pic_height = (u16)dsc_cfg->pic_height; dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; - dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; + dsc_reg_vals->pps.line_buf_depth = (u8)dsc_cfg->dc_dsc_cfg.linebuf_depth; dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0; // Need to find the ceiling value for the slice width - dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h; + dsc_reg_vals->pps.slice_width = (u16)((dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h); // TODO: in addition to validating slice height (pic height must be divisible by slice height), // see what happens when the same condition doesn't apply for slice_width/pic_width. - dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; + dsc_reg_vals->pps.slice_height = (u16)(dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v); ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { @@ -428,9 +429,9 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) - dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; + dsc_reg_vals->pps.bits_per_pixel = (u16)dsc_reg_vals->bpp_x32; else - dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; + dsc_reg_vals->pps.bits_per_pixel = (u16)(dsc_reg_vals->bpp_x32 >> 1); dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c index 17acb64a9d80..d84c3399d386 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c @@ -79,9 +79,9 @@ void dsc35_construct(struct dcn20_dsc *dsc, static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe) { struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); - int dsc_clock_en; - int dsc_fw_config; - int enabled_opp_pipe; + uint32_t dsc_clock_en; + uint32_t dsc_fw_config; + uint32_t enabled_opp_pipe; DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); @@ -96,7 +96,7 @@ static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe) REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { - DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); + DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe); ASSERT(0); } diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 41c3b814b6bd..749547960046 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -119,8 +119,9 @@ bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct { struct dsc_optc_config dsc_optc_cfg; struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); + uint32_t max_image_width = (uint32_t)dsc401->max_image_width; - if (dsc_cfg->pic_width > dsc401->max_image_width) + if (dsc_cfg->pic_width > max_image_width) return false; return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg); @@ -144,16 +145,16 @@ void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_c void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe) { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - int dsc_clock_en; - int dsc_fw_config; - int enabled_opp_pipe; + uint32_t dsc_clock_en; + uint32_t dsc_fw_config; + uint32_t enabled_opp_pipe; DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { - DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); + DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe); ASSERT(0); } @@ -169,7 +170,7 @@ void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe) void dsc401_disable(struct display_stream_compressor *dsc) { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - int dsc_clock_en; + uint32_t dsc_clock_en; DC_LOG_DSC("disable DSC %d", dsc->inst); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index 59864130cf83..6c07d9a87bfe 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -72,27 +72,27 @@ static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_param { int i; - dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0; - dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1; - dsc_cfg->initial_offset = rc->initial_fullness_offset; - dsc_cfg->initial_xmit_delay = rc->initial_xmit_delay; - dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset; - dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset; - dsc_cfg->flatness_min_qp = rc->flatness_min_qp; - dsc_cfg->flatness_max_qp = rc->flatness_max_qp; + dsc_cfg->rc_quant_incr_limit0 = (u8)rc->rc_quant_incr_limit0; + dsc_cfg->rc_quant_incr_limit1 = (u8)rc->rc_quant_incr_limit1; + dsc_cfg->initial_offset = (u16)rc->initial_fullness_offset; + dsc_cfg->initial_xmit_delay = (u16)rc->initial_xmit_delay; + dsc_cfg->first_line_bpg_offset = (u8)rc->first_line_bpg_offset; + dsc_cfg->second_line_bpg_offset = (u8)rc->second_line_bpg_offset; + dsc_cfg->flatness_min_qp = (u8)rc->flatness_min_qp; + dsc_cfg->flatness_max_qp = (u8)rc->flatness_max_qp; for (i = 0; i < QP_SET_SIZE; ++i) { - dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]; - dsc_cfg->rc_range_params[i].range_max_qp = rc->qp_max[i]; + dsc_cfg->rc_range_params[i].range_min_qp = (u8)rc->qp_min[i]; + dsc_cfg->rc_range_params[i].range_max_qp = (u8)rc->qp_max[i]; /* Truncate 8-bit signed value to 6-bit signed value */ dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i]; } - dsc_cfg->rc_model_size = rc->rc_model_size; - dsc_cfg->rc_edge_factor = rc->rc_edge_factor; - dsc_cfg->rc_tgt_offset_high = rc->rc_tgt_offset_hi; - dsc_cfg->rc_tgt_offset_low = rc->rc_tgt_offset_lo; + dsc_cfg->rc_model_size = (u16)rc->rc_model_size; + dsc_cfg->rc_edge_factor = (u8)rc->rc_edge_factor; + dsc_cfg->rc_tgt_offset_high = (u8)rc->rc_tgt_offset_hi; + dsc_cfg->rc_tgt_offset_low = (u8)rc->rc_tgt_offset_lo; for (i = 0; i < QP_SET_SIZE - 1; ++i) - dsc_cfg->rc_buf_thresh[i] = rc->rc_buf_thresh[i]; + dsc_cfg->rc_buf_thresh[i] = (u16)rc->rc_buf_thresh[i]; } int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, @@ -103,7 +103,8 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct drm_dsc_config dsc_cfg; dsc_params->pps = *pps; - dsc_params->pps.initial_scale_value = 8 * rc->rc_model_size / (rc->rc_model_size - rc->initial_fullness_offset); + dsc_params->pps.initial_scale_value = (u8)(8 * rc->rc_model_size / + (rc->rc_model_size - rc->initial_fullness_offset)); copy_pps_fields(&dsc_cfg, &dsc_params->pps); copy_rc_to_cfg(&dsc_cfg, rc); diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c index a2c46350e44e..95f8b7c7d657 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c @@ -646,6 +646,9 @@ enum gpio_result dal_ddc_change_mode( enum gpio_ddc_line dal_ddc_get_line( const struct ddc *ddc) { + if (!ddc) + return GPIO_DDC_LINE_UNKNOWN; + return (enum gpio_ddc_line)dal_gpio_get_enum(ddc->pin_data); } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c index 86d60986d669..a76884a069e8 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c @@ -36,7 +36,7 @@ #undef FN #define FN(reg_name, field_name) \ - ddc->shifts->field_name, ddc->masks->field_name + gpio_reg_shift(ddc->shifts->field_name), ddc->masks->field_name #define CTX \ ddc->base.base.ctx diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c index 7f137cb96895..5db83920e367 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c @@ -37,7 +37,7 @@ #undef FN #define FN(reg_name, field_name) \ - generic->shifts->field_name, generic->masks->field_name + gpio_reg_shift(generic->shifts->field_name), generic->masks->field_name #define CTX \ generic->base.base.ctx diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c index f0d400972897..07651dc7e205 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c @@ -32,7 +32,7 @@ #undef FN #define FN(reg_name, field_name) \ - gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask + gpio_reg_shift(gpio->regs->field_name ## _shift), gpio->regs->field_name ## _mask #define CTX \ gpio->base.ctx diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h index bca0cef18ff9..5b551068cdd6 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h @@ -141,4 +141,13 @@ enum gpio_result dal_hw_gpio_change_mode( void dal_hw_gpio_close( struct hw_gpio_pin *ptr); +/* + * Shared helper used by all GPIO register helpers that pass a field shift + * (stored as uint32_t) into register functions that expect uint8_t. + */ +static inline uint8_t gpio_reg_shift(uint32_t shift) +{ + return (uint8_t)shift; +} + #endif diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c index 79e107904e21..2cb960e517ae 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c @@ -35,7 +35,7 @@ #undef FN #define FN(reg_name, field_name) \ - hpd->shifts->field_name, hpd->masks->field_name + gpio_reg_shift(hpd->shifts->field_name), hpd->masks->field_name #define CTX \ hpd->base.base.ctx diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c index 92ed130aeaec..79d6ab8ed71c 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c @@ -468,7 +468,7 @@ static void dcn31_hpo_dp_stream_enc_update_dp_info_packets( &info_frame->spd, true); - if (info_frame->hdrsmd.valid) + if (info_frame->hdrsmd.valid && !info_frame->firmware_controlled_hdr_info_packet) enc->vpg->funcs->update_generic_info_packet( enc->vpg, 3, /* packetIndex */ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c index 97ef8281a476..d683d0740c13 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c @@ -638,27 +638,27 @@ void hubbub1_update_dchub( SDPIF_FB_BASE, 0x0FFFF); REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + SDPIF_AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22)); REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + SDPIF_AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22)); REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); + SDPIF_AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1) >> 22)); break; case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + SDPIF_AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22)); REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + SDPIF_AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22)); REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); + SDPIF_AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1) >> 22)); break; case FRAME_BUFFER_MODE_LOCAL_ONLY: /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c index 5c6f7ddafd6b..053a08b6d3a3 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c @@ -398,17 +398,17 @@ int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub, struct dcn_vmid_page_table_config phys_config; REG_SET(DCN_VM_FB_LOCATION_BASE, 0, - FB_BASE, pa_config->system_aperture.fb_base >> 24); + FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base)); REG_SET(DCN_VM_FB_LOCATION_TOP, 0, - FB_TOP, pa_config->system_aperture.fb_top >> 24); + FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top)); REG_SET(DCN_VM_FB_OFFSET, 0, - FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); + FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset)); REG_SET(DCN_VM_AGP_BOT, 0, - AGP_BOT, pa_config->system_aperture.agp_bot >> 24); + AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot)); REG_SET(DCN_VM_AGP_TOP, 0, - AGP_TOP, pa_config->system_aperture.agp_top >> 24); + AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top)); REG_SET(DCN_VM_AGP_BASE, 0, - AGP_BASE, pa_config->system_aperture.agp_base >> 24); + AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base)); REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF); @@ -447,36 +447,36 @@ void hubbub2_update_dchub(struct hubbub *hubbub, /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ REG_UPDATE(DCN_VM_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 24); + AGP_BASE, ADDR_HI24(dh_data->zfb_phys_addr_base)); /*This field defines the bottom range of the AGP aperture and represents the 24*/ /*MSBs, bits [47:24] of the 48 address bits*/ REG_UPDATE(DCN_VM_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 24); + AGP_BOT, ADDR_HI24(dh_data->zfb_mc_base_addr)); /*This field defines the top range of the AGP aperture and represents the 24*/ /*MSBs, bits [47:24] of the 48 address bits*/ REG_UPDATE(DCN_VM_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 24); + AGP_TOP, ADDR_HI24(dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1)); break; case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ REG_UPDATE(DCN_VM_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 24); + AGP_BASE, ADDR_HI24(dh_data->zfb_phys_addr_base)); /*This field defines the bottom range of the AGP aperture and represents the 24*/ /*MSBs, bits [47:24] of the 48 address bits*/ REG_UPDATE(DCN_VM_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 24); + AGP_BOT, ADDR_HI24(dh_data->zfb_mc_base_addr)); /*This field defines the top range of the AGP aperture and represents the 24*/ /*MSBs, bits [47:24] of the 48 address bits*/ REG_UPDATE(DCN_VM_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 24); + AGP_TOP, ADDR_HI24(dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1)); break; case FRAME_BUFFER_MODE_LOCAL_ONLY: /*Should not touch FB LOCATION (should be done by VBIOS)*/ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h index 46d8f5c70750..6223dfaee270 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h @@ -141,4 +141,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub, void hubbub2_read_state(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state); +/* Extract bits [47:24] of a physical address for hardware register fields */ +#define ADDR_HI24(a) ((uint32_t)((uint64_t)(a) >> 24)) + #endif diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c index e4496ad203b2..d790d6ee359a 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c @@ -111,17 +111,17 @@ int hubbub21_init_dchub(struct hubbub *hubbub, struct dcn_vmid_page_table_config phys_config; REG_SET(DCN_VM_FB_LOCATION_BASE, 0, - FB_BASE, pa_config->system_aperture.fb_base >> 24); + FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base)); REG_SET(DCN_VM_FB_LOCATION_TOP, 0, - FB_TOP, pa_config->system_aperture.fb_top >> 24); + FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top)); REG_SET(DCN_VM_FB_OFFSET, 0, - FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); + FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset)); REG_SET(DCN_VM_AGP_BOT, 0, - AGP_BOT, pa_config->system_aperture.agp_bot >> 24); + AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot)); REG_SET(DCN_VM_AGP_TOP, 0, - AGP_TOP, pa_config->system_aperture.agp_top >> 24); + AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top)); REG_SET(DCN_VM_AGP_BASE, 0, - AGP_BASE, pa_config->system_aperture.agp_base >> 24); + AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base)); if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c index 181a93dc46e6..6a7c1bee5747 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c @@ -68,17 +68,17 @@ int hubbub3_init_dchub_sys_ctx(struct hubbub *hubbub, struct dcn_vmid_page_table_config phys_config; REG_SET(DCN_VM_FB_LOCATION_BASE, 0, - FB_BASE, pa_config->system_aperture.fb_base >> 24); + FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base)); REG_SET(DCN_VM_FB_LOCATION_TOP, 0, - FB_TOP, pa_config->system_aperture.fb_top >> 24); + FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top)); REG_SET(DCN_VM_FB_OFFSET, 0, - FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); + FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset)); REG_SET(DCN_VM_AGP_BOT, 0, - AGP_BOT, pa_config->system_aperture.agp_bot >> 24); + AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot)); REG_SET(DCN_VM_AGP_TOP, 0, - AGP_TOP, pa_config->system_aperture.agp_top >> 24); + AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top)); REG_SET(DCN_VM_AGP_BASE, 0, - AGP_BASE, pa_config->system_aperture.agp_base >> 24); + AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base)); if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c index 3c298192f359..79cb506be5cb 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c @@ -910,17 +910,17 @@ int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub, struct dcn_vmid_page_table_config phys_config; REG_SET(DCN_VM_FB_LOCATION_BASE, 0, - FB_BASE, pa_config->system_aperture.fb_base >> 24); + FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base)); REG_SET(DCN_VM_FB_LOCATION_TOP, 0, - FB_TOP, pa_config->system_aperture.fb_top >> 24); + FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top)); REG_SET(DCN_VM_FB_OFFSET, 0, - FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); + FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset)); REG_SET(DCN_VM_AGP_BOT, 0, - AGP_BOT, pa_config->system_aperture.agp_bot >> 24); + AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot)); REG_SET(DCN_VM_AGP_TOP, 0, - AGP_TOP, pa_config->system_aperture.agp_top >> 24); + AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top)); REG_SET(DCN_VM_AGP_BASE, 0, - AGP_BASE, pa_config->system_aperture.agp_base >> 24); + AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base)); if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c index 3b9542c08f3d..bf30a1bb61b7 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c @@ -617,7 +617,9 @@ bool hubbub401_dcc_support_swizzle( swizzle_supported = true; break; case DC_ADDR3_SW_64KB_2D: + case DC_ADDR3_SW_64KB_2D_Z: case DC_ADDR3_SW_256KB_2D: + case DC_ADDR3_SW_256KB_2D_Z: swizzle_supported = true; break; default: @@ -833,7 +835,7 @@ bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub, struct dc_surface_dcc_cap *output) { struct dc *dc = hubbub->ctx->dc; - const unsigned int max_dcc_plane_width = dc->caps.dcc_plane_width_limit; + const int max_dcc_plane_width = (int)dc->caps.dcc_plane_width_limit; /* DCN4_Programming_Guide_DCHUB.docx, Section 5.11.2.2 */ enum dcc_control dcc_control; unsigned int plane0_bpe, plane1_bpe; @@ -1198,6 +1200,7 @@ bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs bool wm_pending = false; uint32_t temp; + bool allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req != 0; /* request backpressure and outstanding return threshold (unused)*/ //REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs->req_stall_threshold); @@ -1205,8 +1208,8 @@ bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs /* P-State stall threshold */ REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold); - if (safe_to_lower || arb_regs->allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { - hubbub2->allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req; + if (safe_to_lower || allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { + hubbub2->allow_sdpif_rate_limit_when_cstate_req = allow_sdpif_rate_limit_when_cstate_req; /* only update the required bits */ REG_GET(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, &temp); diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c index 73b6b0ffcb74..ddfc60e845a4 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c @@ -503,6 +503,7 @@ static bool dcn42_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb bool wm_pending = false; uint32_t temp; + bool allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req != 0; /* request backpressure and outstanding return threshold (unused)*/ //REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs->req_stall_threshold); @@ -510,8 +511,8 @@ static bool dcn42_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb /* 401 delta: do not update P-State stall threshold (handled by fw) */ // REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold); - if (safe_to_lower || arb_regs->allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { - hubbub2->allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req; + if (safe_to_lower || allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { + hubbub2->allow_sdpif_rate_limit_when_cstate_req = allow_sdpif_rate_limit_when_cstate_req; /* only update the required bits */ REG_GET(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, &temp); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c index ceee5165fd6a..cf2c9f80056e 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c @@ -68,10 +68,10 @@ void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, - MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); + MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part); REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); + MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part); REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, ENABLE_L1_TLB, 1, @@ -710,7 +710,7 @@ void hubp2_dmdata_load( uint32_t dmdata_sw_size, const uint32_t *dmdata_sw_data) { - int i; + unsigned int i; struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); /* load dmdata into HUBP buffer in SW mode */ diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c index 08ea0a1b9e7f..67828505939a 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c @@ -238,10 +238,10 @@ static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, - MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); + MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part); REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); + MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part); REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, ENABLE_L1_TLB, 1, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index e2708e30eb1b..3e5ae0eae39f 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c @@ -55,10 +55,10 @@ void hubp3_set_vm_system_aperture_settings(struct hubp *hubp, mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, - MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); + MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part); REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); + MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part); REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, ENABLE_L1_TLB, 1, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index 5a816442deee..302515128358 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -41,12 +41,12 @@ hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name void hubp401_program_3dlut_fl_addr(struct hubp *hubp, - const struct dc_plane_address *address) + const struct dc_plane_address address) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address->lut3d.addr.high_part); - REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address->lut3d.addr.low_part); + REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part); + REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address.lut3d.addr.low_part); } void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group) @@ -63,55 +63,42 @@ void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable) REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, enable ? 1 : 0); } -int hubp401_get_3dlut_fl_done(struct hubp *hubp) +uint32_t hubp401_get_3dlut_fl_done(struct hubp *hubp) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - int ret; + uint32_t ret; REG_GET(HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, &ret); return ret; } -static void hubp401_get_3dlut_fl_xbar_map( - const enum dc_cm_lut_pixel_format format, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_y_g, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cb_b, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cr_r) -{ - switch (format) { - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: - /* BGRA */ - *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; - *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; - break; - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: - case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: - default: - /* RGBA */ - *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; - *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; - break; - } -} - -void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, - const enum dc_cm_lut_pixel_format format) +void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g = 0; - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b = 0; - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r = 0; + REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, addr_mode); +} - hubp401_get_3dlut_fl_xbar_map(format, - &bit_slice_y_g, - &bit_slice_cb_b, - &bit_slice_cr_r); +void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, width); +} + +void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, protection_bits); +} + +void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); REG_UPDATE_3(HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SELECT_Y_G, bit_slice_y_g, @@ -119,122 +106,62 @@ void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, HUBP_3DLUT_CROSSBAR_SELECT_CR_R, bit_slice_cr_r); } -static enum hubp_3dlut_fl_width hubp401_get_3dlut_fl_width( - const enum dc_cm_lut_size size, - const enum dc_cm_lut_swizzle swizzle) -{ - enum hubp_3dlut_fl_width width = 0; - - switch (size) { - case CM_LUT_SIZE_333333: - ASSERT(swizzle != CM_LUT_1D_PACKED_LINEAR); - width = hubp_3dlut_fl_width_33; - break; - case CM_LUT_SIZE_171717: - if (swizzle != CM_LUT_1D_PACKED_LINEAR) { - width = hubp_3dlut_fl_width_17; - } else { - width = hubp_3dlut_fl_width_17_transformed; - } - break; - default: - width = 0; - break; - } - - return width; -} - -static enum hubp_3dlut_fl_format hubp401_get_3dlut_fl_format( - const enum dc_cm_lut_pixel_format dc_format) -{ - enum hubp_3dlut_fl_format hubp_format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - - switch (dc_format) { - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: - hubp_format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - break; - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: - hubp_format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; - break; - case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: - hubp_format = hubp_3dlut_fl_format_float_fp1_5_10; - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - return hubp_format; -} - -static enum hubp_3dlut_fl_addressing_mode hubp401_get_3dlut_fl_addr_mode( - const enum dc_cm_lut_swizzle swizzle) -{ - enum hubp_3dlut_fl_addressing_mode addr_mode; - - switch (swizzle) { - case CM_LUT_1D_PACKED_LINEAR: - addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; - break; - case CM_LUT_3D_SWIZZLE_LINEAR_RGB: - case CM_LUT_3D_SWIZZLE_LINEAR_BGR: - default: - addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - } - - return addr_mode; -} - -static enum hubp_3dlut_fl_mode hubp401_get_3dlut_fl_mode( - const enum dc_cm_lut_swizzle swizzle) -{ - enum hubp_3dlut_fl_mode mode; - - switch (swizzle) { - case CM_LUT_3D_SWIZZLE_LINEAR_RGB: - mode = hubp_3dlut_fl_mode_native_1; - break; - case CM_LUT_3D_SWIZZLE_LINEAR_BGR: - mode = hubp_3dlut_fl_mode_native_2; - break; - case CM_LUT_1D_PACKED_LINEAR: - mode = hubp_3dlut_fl_mode_transform; - break; - default: - mode = hubp_3dlut_fl_mode_disable; - break; - } - - return mode; -} - -void hubp401_program_3dlut_fl_config(struct hubp *hubp, - const struct dc_3dlut_dma *config) +void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - enum hubp_3dlut_fl_width width = hubp401_get_3dlut_fl_width(config->size, config->swizzle); - enum hubp_3dlut_fl_format format = hubp401_get_3dlut_fl_format(config->format); - enum hubp_3dlut_fl_addressing_mode addr_mode = hubp401_get_3dlut_fl_addr_mode(config->swizzle); - enum hubp_3dlut_fl_mode mode = hubp401_get_3dlut_fl_mode(config->swizzle); + REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, bias, HUBP0_3DLUT_FL_SCALE, scale); +} + +void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mode); +} + +void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format); +} + +void hubp401_program_3dlut_fl_config( + struct hubp *hubp, + struct hubp_fl_3dlut_config *cfg) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + uint32_t mpc_width = {(cfg->width == 17) ? 0 : 1}; + uint32_t width = {cfg->width}; + + if (cfg->layout == DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR) + width = (cfg->width == 17) ? 4916 : 35940; REG_UPDATE_2(_3DLUT_FL_CONFIG, - HUBP0_3DLUT_FL_MODE, mode, - HUBP0_3DLUT_FL_FORMAT, format); + HUBP0_3DLUT_FL_MODE, cfg->mode, + HUBP0_3DLUT_FL_FORMAT, cfg->format); REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, - HUBP0_3DLUT_FL_BIAS, config->bias, - HUBP0_3DLUT_FL_SCALE, config->scale); + HUBP0_3DLUT_FL_BIAS, cfg->bias, + HUBP0_3DLUT_FL_SCALE, cfg->scale); - REG_UPDATE_3(HUBP_3DLUT_CONTROL, - HUBP_3DLUT_WIDTH, width, - HUBP_3DLUT_ADDRESSING_MODE, addr_mode, - HUBP_3DLUT_TMZ, config->addr.tmz_surface); + REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, + HUBP_3DLUT_ADDRESS_HIGH, cfg->address.lut3d.addr.high_part); + REG_UPDATE(HUBP_3DLUT_ADDRESS_LOW, + HUBP_3DLUT_ADDRESS_LOW, cfg->address.lut3d.addr.low_part); + + //cross bar + REG_UPDATE_8(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_MPC_WIDTH, mpc_width, + HUBP_3DLUT_WIDTH, width, + HUBP_3DLUT_CROSSBAR_SELECT_CR_R, cfg->crossbar_bit_slice_cr_r, + HUBP_3DLUT_CROSSBAR_SELECT_Y_G, cfg->crossbar_bit_slice_y_g, + HUBP_3DLUT_CROSSBAR_SELECT_CB_B, cfg->crossbar_bit_slice_cb_b, + HUBP_3DLUT_ADDRESSING_MODE, cfg->addr_mode, + HUBP_3DLUT_TMZ, cfg->protection_bits, + HUBP_3DLUT_ENABLE, cfg->enabled ? 1 : 0); } void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor) @@ -1135,13 +1062,19 @@ static struct hubp_funcs dcn401_hubp_funcs = { .hubp_update_mall_sel = hubp401_update_mall_sel, .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, .hubp_program_mcache_id_and_split_coordinate = hubp401_program_mcache_id_and_split_coordinate, + .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale, + .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode, + .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format, .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, - .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, + .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode, + .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width, + .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected, .hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar, .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, .hubp_clear_tiling = hubp401_clear_tiling, + .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, .hubp_read_reg_state = hubp3_read_reg_state }; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h index 043948f64b86..4116834c552d 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h @@ -324,21 +324,36 @@ bool hubp401_construct( void hubp401_init(struct hubp *hubp); -int hubp401_get_3dlut_fl_done(struct hubp *hubp); +uint32_t hubp401_get_3dlut_fl_done(struct hubp *hubp); void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable); +void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale); + void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, - const enum dc_cm_lut_pixel_format format); + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); + +void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits); + +void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width); + +void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable); void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group); -void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address *address); +void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address address); -void hubp401_program_3dlut_fl_config(struct hubp *hubp, - const struct dc_3dlut_dma *config); +void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format); + +void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode); + +void hubp401_program_3dlut_fl_config( + struct hubp *hubp, + struct hubp_fl_3dlut_config *cfg); void hubp401_clear_tiling(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c index ad6badcceb12..e4602c3ddc66 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c @@ -311,84 +311,19 @@ static void hubp42_program_surface_config( hubp42_program_pixel_format(hubp, format); } -static void hubp42_get_3dlut_fl_xbar_map( - const enum dc_cm_lut_pixel_format format, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_y_g, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cb_b, - enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cr_r) -{ - switch (format) { - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: - case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: - /* BGRA */ - *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; - *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; - break; - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: - case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: - case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: - default: - /* RGBA */ - *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; - *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; - break; - } -} - void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp, - const enum dc_cm_lut_pixel_format format) + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g = 0; - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b = 0; - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r = 0; - - hubp42_get_3dlut_fl_xbar_map(format, - &bit_slice_g, - &bit_slice_b, - &bit_slice_r); - REG_UPDATE_3(HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SEL_R, bit_slice_r, HUBP_3DLUT_CROSSBAR_SEL_G, bit_slice_g, HUBP_3DLUT_CROSSBAR_SEL_B, bit_slice_b); } -static uint32_t hubp42_get_3dlut_fl_mpc_width( - const enum dc_cm_lut_size size) -{ - uint32_t width = 0; - - switch (size) { - case CM_LUT_SIZE_333333: - width = 1; - break; - case CM_LUT_SIZE_171717: - default: - width = 0; - break; - } - - return width; -} - -void hubp42_program_3dlut_fl_config(struct hubp *hubp, - const struct dc_3dlut_dma *config) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - uint32_t mpc_width = hubp42_get_3dlut_fl_mpc_width(config->size); - - REG_UPDATE(HUBP_3DLUT_CONTROL, - HUBP_3DLUT_MPC_WIDTH, mpc_width); - - hubp401_program_3dlut_fl_config(hubp, config); -} - static bool hubp42_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, @@ -670,10 +605,15 @@ struct hubp_funcs dcn42_hubp_funcs = { .hubp_set_flip_int = hubp1_set_flip_int, .hubp_in_blank = hubp1_in_blank, .program_extended_blank = hubp31_program_extended_blank_value, + .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale, + .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode, + .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format, .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, - .hubp_program_3dlut_fl_config = hubp42_program_3dlut_fl_config, .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, + .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode, + .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width, + .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected, .hubp_program_3dlut_fl_crossbar = hubp42_program_3dlut_fl_crossbar, .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, .hubp_clear_tiling = hubp3_clear_tiling, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h index 88bb1337ab9d..f0e614136228 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h @@ -58,11 +58,11 @@ bool hubp42_construct( const struct dcn_hubp2_shift *hubp_shift, const struct dcn_hubp2_mask *hubp_mask); -void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp, - const enum dc_cm_lut_pixel_format format); - -void hubp42_program_3dlut_fl_config(struct hubp *hubp, - const struct dc_3dlut_dma *config); +void hubp42_program_3dlut_fl_crossbar( + struct hubp *hubp, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b); void hubp42_read_state(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 5273ca09fe12..d81271b870bb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -504,7 +504,7 @@ dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, } j = 0; - for (k = 0; k < (region_end - region_start); k++) { + for (k = 0; k < (uint32_t)(region_end - region_start); k++) { increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); start_index = (region_start + k + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; @@ -665,16 +665,45 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) } static void -dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable) +dce110_external_encoder_control(enum bp_external_encoder_control_action action, + struct dc_link *link, + struct dc_crtc_timing *timing) { - struct dc_link *link = pipe_ctx->stream->link; + struct dc *dc = link->ctx->dc; struct dc_bios *bios = link->ctx->dc_bios; - struct bp_encoder_control encoder_control = {0}; + const struct dc_link_settings *link_settings = &link->cur_link_settings; + enum bp_result bp_result = BP_RESULT_OK; + struct bp_external_encoder_control ext_cntl = { + .action = action, + .connector_obj_id = link->link_enc->connector, + .encoder_id = link->ext_enc_id, + .lanes_number = link_settings->lane_count, + .link_rate = link_settings->link_rate, - encoder_control.action = enable ? ENCODER_CONTROL_ENABLE : ENCODER_CONTROL_DISABLE; - encoder_control.engine_id = link->link_enc->analog_engine; - encoder_control.pixel_clock = pipe_ctx->stream->timing.pix_clk_100hz / 10; - bios->funcs->encoder_control(bios, &encoder_control); + /* Use signal type of the real link encoder, ie. DP */ + .signal = link->connector_signal, + + /* We don't know the timing yet when executing the SETUP action, + * so use a reasonably high default value. It seems that ENABLE + * can change the actual pixel clock but doesn't work with higher + * pixel clocks than what SETUP was called with. + */ + .pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000, + .color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888, + }; + DC_LOGGER_INIT(dc->ctx); + + bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl); + + if (bp_result != BP_RESULT_OK) + DC_LOG_ERROR("Failed to execute external encoder action: 0x%x\n", action); +} + +static void +dce110_prepare_ddc(struct dc_link *link) +{ + if (link->ext_enc_id.id) + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DDC_SETUP, link, NULL); } static bool @@ -684,7 +713,8 @@ dce110_dac_load_detect(struct dc_link *link) struct link_encoder *link_enc = link->link_enc; enum bp_result bp_result; - bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine); + bp_result = bios->funcs->dac_load_detection( + bios, link_enc->analog_engine, link->ext_enc_id); return bp_result == BP_RESULT_OK; } @@ -700,7 +730,6 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) uint32_t early_control = 0; struct timing_generator *tg = pipe_ctx->stream_res.tg; - link_hwss->setup_stream_attribute(pipe_ctx); link_hwss->setup_stream_encoder(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); @@ -719,8 +748,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) tg->funcs->set_early_control(tg, early_control); - if (dc_is_rgb_signal(pipe_ctx->stream->signal)) - dce110_dac_encoder_control(pipe_ctx, true); + if (link->ext_enc_id.id) + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_ENABLE, link, timing); } static enum bp_result link_transmitter_control( @@ -858,7 +887,7 @@ void dce110_edp_power_control( DC_LOG_HW_RESUME_S3( "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", __func__, remaining_min_edp_poweroff_time_ms); - msleep(remaining_min_edp_poweroff_time_ms); + msleep((unsigned int)remaining_min_edp_poweroff_time_ms); DC_LOG_HW_RESUME_S3( "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", __func__, remaining_min_edp_poweroff_time_ms); @@ -883,7 +912,7 @@ void dce110_edp_power_control( cntl.coherent = false; cntl.lanes_number = LANE_COUNT_FOUR; cntl.hpd_sel = link->link_enc->hpd_source; - pwrseq_instance = link->panel_cntl->pwrseq_inst; + pwrseq_instance = (uint8_t)link->panel_cntl->pwrseq_inst; if (ctx->dc->ctx->dmub_srv && ctx->dc->debug.dmub_command_table) { @@ -952,7 +981,7 @@ void dce110_edp_wait_for_T12( t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12 if (time_since_edp_poweroff_ms < t12_duration) - msleep(t12_duration - time_since_edp_poweroff_ms); + msleep((unsigned int)(t12_duration - time_since_edp_poweroff_ms)); } } /*todo: cloned in stream enc, fix*/ @@ -1021,8 +1050,9 @@ void dce110_edp_backlight_control( */ /* dc_service_sleep_in_milliseconds(50); */ /*edp 1.2*/ - if (link->panel_cntl) - pwrseq_instance = link->panel_cntl->pwrseq_inst; + if (link->panel_cntl) { + pwrseq_instance = (uint8_t)link->panel_cntl->pwrseq_inst; + } if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { if (!link->dc->config.edp_no_power_sequencing) @@ -1219,8 +1249,8 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) link_enc->transmitter - TRANSMITTER_UNIPHY_A); } - if (dc_is_rgb_signal(pipe_ctx->stream->signal)) - dce110_dac_encoder_control(pipe_ctx, false); + if (link->ext_enc_id.id) + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DISABLE, link, NULL); } void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, @@ -1439,11 +1469,11 @@ void build_audio_output( audio_output->crtc_info.pixel_repetition = 1; audio_output->crtc_info.interlaced = - stream->timing.flags.INTERLACE; + (stream->timing.flags.INTERLACE != 0); audio_output->crtc_info.refresh_rate = - (stream->timing.pix_clk_100hz*100)/ - (stream->timing.h_total*stream->timing.v_total); + (uint16_t)((stream->timing.pix_clk_100hz*100)/ + (stream->timing.h_total*stream->timing.v_total)); audio_output->crtc_info.color_depth = stream->timing.display_color_depth; @@ -1603,22 +1633,6 @@ static enum dc_status dce110_enable_stream_timing( return DC_OK; } -static void -dce110_select_crtc_source(struct pipe_ctx *pipe_ctx) -{ - struct dc_link *link = pipe_ctx->stream->link; - struct dc_bios *bios = link->ctx->dc_bios; - struct bp_crtc_source_select crtc_source_select = {0}; - enum engine_id engine_id = link->link_enc->preferred_engine; - - if (dc_is_rgb_signal(pipe_ctx->stream->signal)) - engine_id = link->link_enc->analog_engine; - crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst; - crtc_source_select.color_depth = pipe_ctx->stream->timing.display_color_depth; - crtc_source_select.engine_id = engine_id; - crtc_source_select.sink_signal = pipe_ctx->stream->signal; - bios->funcs->select_crtc_source(bios, &crtc_source_select); -} enum dc_status dce110_apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, @@ -1639,10 +1653,6 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( hws->funcs.disable_stream_gating(dc, pipe_ctx); } - if (pipe_ctx->stream->signal == SIGNAL_TYPE_RGB) { - dce110_select_crtc_source(pipe_ctx); - } - if (pipe_ctx->stream_res.audio != NULL) { struct audio_output audio_output = {0}; @@ -1722,8 +1732,7 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( pipe_ctx->stream_res.tg->funcs->set_static_screen_control( pipe_ctx->stream_res.tg, event_triggers, 2); - if (!dc_is_virtual_signal(pipe_ctx->stream->signal) && - !dc_is_rgb_signal(pipe_ctx->stream->signal)) + if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.tg->inst); @@ -1778,20 +1787,22 @@ static void power_down_encoders(struct dc *dc) for (i = 0; i < dc->link_count; i++) { struct dc_link *link = dc->links[i]; - struct link_encoder *link_enc = link->link_enc; + struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link); enum signal_type signal = link->connector_signal; dc->link_srv->blank_dp_stream(link, false); if (signal != SIGNAL_TYPE_EDP) signal = SIGNAL_TYPE_NONE; - if (link->ep_type == DISPLAY_ENDPOINT_PHY) + if (link->ep_type == DISPLAY_ENDPOINT_PHY && link_enc) link_enc->funcs->disable_output(link_enc, signal); if (link->fec_state == dc_link_fec_enabled) { - link_enc->funcs->fec_set_enable(link_enc, false); - link_enc->funcs->fec_set_ready(link_enc, false); - link->fec_state = dc_link_fec_not_ready; + if (link_enc && link_enc->funcs->fec_set_enable && link_enc->funcs->fec_set_ready) { + link_enc->funcs->fec_set_enable(link_enc, false); + link_enc->funcs->fec_set_ready(link_enc, false); + link->fec_state = dc_link_fec_not_ready; + } } link->link_status.link_active = false; @@ -1801,7 +1812,7 @@ static void power_down_encoders(struct dc *dc) static void power_down_controllers(struct dc *dc) { - int i; + unsigned int i; for (i = 0; i < dc->res_pool->timing_generator_count; i++) { dc->res_pool->timing_generators[i]->funcs->disable_crtc( @@ -1811,7 +1822,7 @@ static void power_down_controllers(struct dc *dc) static void power_down_clock_sources(struct dc *dc) { - int i; + unsigned int i; if (dc->res_pool->dp_clock_source->funcs->cs_power_down( dc->res_pool->dp_clock_source) == false) @@ -1820,7 +1831,7 @@ static void power_down_clock_sources(struct dc *dc) for (i = 0; i < dc->res_pool->clk_src_count; i++) { if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( dc->res_pool->clock_sources[i]) == false) - dm_error("Failed to power down pll! (clk src index=%d)\n", i); + dm_error("Failed to power down pll! (clk src index=%u)\n", i); } } @@ -1839,7 +1850,7 @@ static void power_down_all_hw_blocks(struct dc *dc) static void disable_vga_and_power_gate_all_controllers( struct dc *dc) { - int i; + uint8_t i; struct timing_generator *tg; struct dc_context *ctx = dc->ctx; @@ -1869,7 +1880,7 @@ static void get_edp_streams(struct dc_state *context, struct dc_stream_state **edp_streams, int *edp_stream_num) { - int i; + uint8_t i; *edp_stream_num = 0; for (i = 0; i < context->stream_count; i++) { @@ -1907,13 +1918,13 @@ static void clean_up_dsc_blocks(struct dc *dc) struct stream_encoder *se = NULL; struct dccg *dccg = dc->res_pool->dccg; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; - int i; + unsigned int i; if (!dc->caps.is_apu || dc->ctx->dce_version < DCN_VERSION_3_15) return; /*VBIOS supports dsc starts from dcn315*/ - for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) { struct dcn_dsc_state s = {0}; dsc = dc->res_pool->dscs[i]; @@ -1991,7 +2002,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) struct pipe_ctx *pipe_ctx = NULL; struct dce_hwseq *hws = dc->hwseq; int edp_with_sink_num; - unsigned int edp_num; + unsigned int j, edp_num; int edp_stream_num; int i; bool can_apply_edp_fast_boot = false; @@ -2011,8 +2022,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) /* Check fastboot support, disable on DCE 6-8-10 because of blank screens */ if (edp_num && edp_stream_num && dc->ctx->dce_version > DCE_VERSION_10_0) { - for (i = 0; i < edp_num; i++) { - edp_link = edp_links[i]; + for (j = 0; j < edp_num; j++) { + edp_link = edp_links[j]; if (edp_link != edp_streams[0]->link) continue; // enable fastboot if backend is enabled on eDP @@ -2115,9 +2126,11 @@ static uint32_t compute_pstate_blackout_duration( const struct dc_stream_state *stream) { uint32_t total_dest_line_time_ns; + int64_t pstate_blackout_duration_ns64; uint32_t pstate_blackout_duration_ns; - pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; + pstate_blackout_duration_ns64 = (1000 * blackout_duration.value) >> 24; + pstate_blackout_duration_ns = (uint32_t)pstate_blackout_duration_ns64; total_dest_line_time_ns = 1000000UL * (stream->timing.h_total * 10) / @@ -2251,7 +2264,7 @@ static void get_position(struct pipe_ctx **pipe_ctx, static void set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) { - unsigned int i; + int i; unsigned int triggers = 0; if (params->triggers.overlay_update) @@ -2538,7 +2551,7 @@ enum dc_status dce110_apply_ctx_to_hw( struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status status; - int i; + unsigned int i; bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state); bool is_hpo_acquired = resource_is_hpo_acquired(context); @@ -2574,7 +2587,7 @@ enum dc_status dce110_apply_ctx_to_hw( } hws->funcs.enable_display_power_gating( - dc, i, dc->ctx->dc_bios, + dc, (uint8_t)i, dc->ctx->dc_bios, PIPE_GATING_CONTROL_DISABLE); } @@ -2904,7 +2917,7 @@ static void dce110_init_pipes(struct dc *dc, struct dc_state *context) static void dce110_init_hw(struct dc *dc) { - int i; + unsigned int i; struct dc_bios *bp; struct transform *xfm; struct abm *abm; @@ -2919,10 +2932,10 @@ static void dce110_init_hw(struct dc *dc) xfm->funcs->transform_reset(xfm); hws->funcs.enable_display_power_gating( - dc, i, bp, + dc, (uint8_t)i, bp, PIPE_GATING_CONTROL_INIT); hws->funcs.enable_display_power_gating( - dc, i, bp, + dc, (uint8_t)i, bp, PIPE_GATING_CONTROL_DISABLE); hws->funcs.enable_display_pipe_clock_gating( dc->ctx, @@ -3126,7 +3139,7 @@ static void dce110_apply_ctx_for_surface( int num_planes, struct dc_state *context) { - int i; + unsigned int i; if (num_planes == 0) return; @@ -3180,7 +3193,7 @@ static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct p return; hws->funcs.enable_display_power_gating( - dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); + dc, (uint8_t)fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); dc->res_pool->transforms[fe_idx]->funcs->transform_reset( dc->res_pool->transforms[fe_idx]); @@ -3376,6 +3389,15 @@ void dce110_enable_tmds_link_output(struct dc_link *link, link->phy_state.symclk_state = SYMCLK_ON_TX_ON; } +static void dce110_enable_analog_link_output( + struct dc_link *link, + uint32_t pix_clk_100hz) +{ + link->link_enc->funcs->enable_analog_output( + link->link_enc, + pix_clk_100hz); +} + void dce110_enable_dp_link_output( struct dc_link *link, const struct link_resource *link_res, @@ -3423,6 +3445,11 @@ void dce110_enable_dp_link_output( } } + if (link->ext_enc_id.id) { + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_INIT, link, NULL); + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_SETUP, link, NULL); + } + if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) { if (dc->clk_mgr->funcs->notify_link_rate_change) dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); @@ -3513,8 +3540,10 @@ static const struct hw_sequencer_funcs dce110_funcs = { .enable_lvds_link_output = dce110_enable_lvds_link_output, .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, + .enable_analog_link_output = dce110_enable_analog_link_output, .disable_link_output = dce110_disable_link_output, .dac_load_detect = dce110_dac_load_detect, + .prepare_ddc = dce110_prepare_ddc, }; static const struct hwseq_private_funcs dce110_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c index 0689bbf12ad8..fbe34d1bb39a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c @@ -208,24 +208,24 @@ static void dce120_update_dchub( FB_BASE, 0x0FFFF); REG_UPDATE(DCHUB_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22)); REG_UPDATE(DCHUB_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22)); REG_UPDATE(DCHUB_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); + AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22)); break; case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ REG_UPDATE(DCHUB_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22)); REG_UPDATE(DCHUB_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22)); REG_UPDATE(DCHUB_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22); + AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22)); break; case FRAME_BUFFER_MODE_LOCAL_ONLY: /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 756ce8379538..1733f551248e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -181,6 +181,7 @@ void dcn10_set_wait_for_update_needed_for_pipe(struct dc *dc, struct pipe_ctx *p uint32_t vupdate_start, vupdate_end; struct crtc_position position; unsigned int vpos, cur_frame; + uint32_t max_frame_count; if (!pipe_ctx->stream || !pipe_ctx->stream_res.tg || @@ -197,7 +198,8 @@ void dcn10_set_wait_for_update_needed_for_pipe(struct dc *dc, struct pipe_ctx *p struct optc *optc1 = DCN10TG_FROM_TG(tg); - ASSERT(optc1->max_frame_count != 0); + max_frame_count = optc1->tg_mask->OTG_FRAME_COUNT >> optc1->tg_shift->OTG_FRAME_COUNT; + ASSERT(max_frame_count != 0); if (tg->funcs->is_tg_enabled && !tg->funcs->is_tg_enabled(tg)) return; @@ -209,8 +211,8 @@ void dcn10_set_wait_for_update_needed_for_pipe(struct dc *dc, struct pipe_ctx *p if (vpos < vupdate_start) { pipe_ctx->wait_frame_count = cur_frame; } else { - if (cur_frame + 1 > optc1->max_frame_count) - pipe_ctx->wait_frame_count = cur_frame + 1 - optc1->max_frame_count; + if (cur_frame + 1 > max_frame_count) + pipe_ctx->wait_frame_count = cur_frame + 1 - max_frame_count; else pipe_ctx->wait_frame_count = cur_frame + 1; } @@ -225,7 +227,7 @@ void dcn10_lock_all_pipes(struct dc *dc, struct pipe_ctx *pipe_ctx; struct pipe_ctx *old_pipe_ctx; struct timing_generator *tg; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -298,7 +300,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx) { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; DTN_INFO( "HUBP: format addr_hi width height rot mir sw_mode dcc_en blank_en clock_en ttu_dis underflow min_ttu_vblank qos_low_wm qos_high_wm\n"); @@ -456,7 +458,7 @@ static void dcn10_log_color_state(struct dc *dc, struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; bool is_gamut_remap_available = false; - int i; + unsigned int i; DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode" " GAMUT adjust " @@ -616,7 +618,8 @@ void dcn10_log_hw_state(struct dc *dc, { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; - int i; + int j; + unsigned int i; DTN_INFO_BEGIN(); @@ -686,8 +689,8 @@ void dcn10_log_hw_state(struct dc *dc, // dcn_dsc_state struct field bytes_per_pixel was renamed to bits_per_pixel // TODO: Update golden log header to reflect this name change DTN_INFO("DSC: CLOCK_EN SLICE_WIDTH Bytes_pp\n"); - for (i = 0; i < pool->res_cap->num_dsc; i++) { - struct display_stream_compressor *dsc = pool->dscs[i]; + for (j = 0; j < pool->res_cap->num_dsc; j++) { + struct display_stream_compressor *dsc = pool->dscs[j]; struct dcn_dsc_state s = {0}; dsc->funcs->dsc_read_state(dsc, &s); @@ -1059,7 +1062,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[0]; - int i; + unsigned int i; if (dc->debug.disable_stutter) return; @@ -1089,7 +1092,7 @@ void dcn10_bios_golden_init(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct dc_bios *bp = dc->ctx->dc_bios; - int i; + unsigned int i; bool allow_self_fresh_force_enable = true; if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc)) @@ -1130,7 +1133,7 @@ static void false_optc_underflow_wa( const struct dc_stream_state *stream, struct timing_generator *tg) { - int i; + unsigned int i; bool underflow; if (!dc->hwseq->wa.false_optc_underflow) @@ -1157,7 +1160,7 @@ static void false_optc_underflow_wa( static int calculate_vready_offset_for_group(struct pipe_ctx *pipe) { struct pipe_ctx *other_pipe; - int vready_offset = pipe->pipe_dlg_param.vready_offset; + unsigned int vready_offset = pipe->pipe_dlg_param.vready_offset; /* Always use the largest vready_offset of all connected pipes */ for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { @@ -1290,7 +1293,7 @@ static void dcn10_reset_back_end_for_pipe( struct dc_state *context) { (void)context; - int i; + unsigned int i; struct dc_link *link; DC_LOGGER_INIT(dc->ctx); if (pipe_ctx->stream_res.stream_enc == NULL) { @@ -1574,7 +1577,7 @@ void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx void dcn10_init_pipes(struct dc *dc, struct dc_state *context) { - int i; + uint8_t i; struct dce_hwseq *hws = dc->hwseq; struct hubbub *hubbub = dc->res_pool->hubbub; bool can_apply_seamless_boot = false; @@ -1677,7 +1680,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context) pipe_ctx->plane_res.hubp = hubp; pipe_ctx->plane_res.dpp = dpp; - pipe_ctx->plane_res.mpcc_inst = dpp->inst; + pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst; hubp->mpcc_id = dpp->inst; hubp->opp_id = OPP_ID_INVALID; hubp->power_gated = false; @@ -1764,7 +1767,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context) void dcn10_init_hw(struct dc *dc) { - int i; + unsigned int i; struct abm *abm = dc->res_pool->abm; struct dmcu *dmcu = dc->res_pool->dmcu; struct dce_hwseq *hws = dc->hwseq; @@ -2095,22 +2098,22 @@ static void log_tf(struct dc_context *ctx, // DC_LOG_GAMMA is default logging of all hw points // DC_LOG_ALL_GAMMA logs all points, not only hw points // DC_LOG_ALL_TF_POINTS logs all channels of the tf - int i = 0; + unsigned int i = 0; DC_LOG_GAMMA("Gamma Correction TF"); DC_LOG_ALL_GAMMA("Logging all tf points..."); DC_LOG_ALL_TF_CHANNELS("Logging all channels..."); for (i = 0; i < hw_points_num; i++) { - DC_LOG_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value); - DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value); - DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value); + DC_LOG_GAMMA("R\t%u\t%llu", i, tf->tf_pts.red[i].value); + DC_LOG_ALL_TF_CHANNELS("G\t%u\t%llu", i, tf->tf_pts.green[i].value); + DC_LOG_ALL_TF_CHANNELS("B\t%u\t%llu", i, tf->tf_pts.blue[i].value); } for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) { - DC_LOG_ALL_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value); - DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value); - DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value); + DC_LOG_ALL_GAMMA("R\t%u\t%llu", i, tf->tf_pts.red[i].value); + DC_LOG_ALL_TF_CHANNELS("G\t%u\t%llu", i, tf->tf_pts.green[i].value); + DC_LOG_ALL_TF_CHANNELS("B\t%u\t%llu", i, tf->tf_pts.blue[i].value); } } @@ -2258,7 +2261,7 @@ void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock) struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_cursor = 1; - inst_flags.opp_inst = pipe->stream_res.opp->inst; + inst_flags.opp_inst = (uint8_t)pipe->stream_res.opp->inst; dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, lock, @@ -2278,7 +2281,7 @@ static bool wait_for_reset_trigger_to_occur( /* To avoid endless loop we wait at most * frames_to_wait_on_triggered_reset frames for the reset to occur. */ const uint32_t frames_to_wait_on_triggered_reset = 10; - int i; + unsigned int i; for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { @@ -2290,7 +2293,7 @@ static bool wait_for_reset_trigger_to_occur( if (tg->funcs->did_triggered_reset_occur(tg)) { rc = true; /* usually occurs at i=1 */ - DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", + DC_SYNC_INFO("GSL: reset occurred at wait count: %u\n", i); break; } @@ -2383,7 +2386,7 @@ static uint8_t get_clock_divider(struct pipe_ctx *pipe, } clock_divider *= numpipes; - return clock_divider; + return (uint8_t)clock_divider; } static int dcn10_align_pixel_clocks(struct dc *dc, int group_size, @@ -2458,7 +2461,7 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size, dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk( dc->res_pool->dp_clock_source, grouped_pipes[i]->stream_res.tg->inst, - phase[i], modulo[i]); + (unsigned int)phase[i], (unsigned int)modulo[i]); dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz( dc->res_pool->dp_clock_source, grouped_pipes[i]->stream_res.tg->inst, &pclk); @@ -2484,7 +2487,8 @@ void dcn10_enable_vblanks_synchronization( (void)group_index; struct output_pixel_processor *opp; struct timing_generator *tg; - int i, width = 0, height = 0, master; + int i, master; + uint32_t width = 0, height = 0; DC_LOGGER_INIT(dc->ctx); @@ -2550,7 +2554,8 @@ void dcn10_enable_timing_synchronization( (void)group_index; struct output_pixel_processor *opp; struct timing_generator *tg; - int i, width = 0, height = 0; + int i; + uint32_t width = 0, height = 0; DC_LOGGER_INIT(dc->ctx); @@ -3263,7 +3268,7 @@ void dcn10_wait_for_pending_cleared(struct dc *dc, { struct pipe_ctx *pipe_ctx; struct timing_generator *tg; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -3294,7 +3299,7 @@ void dcn10_post_unlock_program_front_end( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -3466,7 +3471,7 @@ void dcn10_get_position(struct pipe_ctx **pipe_ctx, void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) { - unsigned int i; + int i; unsigned int triggers = 0; if (params->triggers.surface_update) @@ -3516,7 +3521,7 @@ void dcn10_config_stereo_parameters( } } flags->RIGHT_EYE_POLARITY =\ - stream->timing.flags.RIGHT_EYE_3D_POLARITY; + (stream->timing.flags.RIGHT_EYE_3D_POLARITY != 0); if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) flags->FRAME_PACKED = 1; } @@ -3553,7 +3558,7 @@ void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) { - int i; + unsigned int i; for (i = 0; i < res_pool->pipe_count; i++) { if (res_pool->hubps[i]->inst == mpcc_inst) @@ -3635,8 +3640,8 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) if (dc->hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied) { struct dce_hwseq *hwseq = dc->hwseq; - struct timing_generator *tg = dc->res_pool->timing_generators[0]; - unsigned int cur_frame = tg->funcs->get_frame_count(tg); + struct timing_generator *wa_tg = dc->res_pool->timing_generators[0]; + unsigned int cur_frame = wa_tg->funcs->get_frame_count(wa_tg); if (cur_frame != hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame) { struct hubbub *hubbub = dc->res_pool->hubbub; @@ -3794,7 +3799,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) // Swap axis and mirror vertically else if (param.rotation == ROTATION_ANGLE_270) { uint32_t temp_y = pos_cpy.y; - int viewport_height = + uint32_t viewport_height = pipe_ctx->plane_res.scl_data.viewport.height; int viewport_y = pipe_ctx->plane_res.scl_data.viewport.y; @@ -4121,7 +4126,7 @@ void dcn10_get_clock(struct dc *dc, void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits) { struct resource_pool *pool = dc->res_pool; - int i; + unsigned int i; for (i = 0; i < pool->pipe_count; i++) { struct hubp *hubp = pool->hubps[i]; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c index 079c226c1097..b5e82e190124 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c @@ -118,6 +118,8 @@ static const struct hwseq_private_funcs dcn10_private_funcs = { .dsc_pg_control = NULL, .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, + .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, + .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, }; void dcn10_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 288e4edaa9a2..07c53a8e73b5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -79,7 +79,7 @@ void dcn20_log_color_state(struct dc *dc, struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; bool is_gamut_remap_available = false; - int i; + unsigned int i; DTN_INFO("DPP: DGAM mode SHAPER mode 3DLUT mode 3DLUT bit depth" " 3DLUT size RGAM mode GAMUT adjust " @@ -235,7 +235,7 @@ void dcn20_setup_gsl_group_as_lock( group_idx = find_free_gsl_group(dc); ASSERT(group_idx != 0); - pipe_ctx->stream_res.gsl_group = group_idx; + pipe_ctx->stream_res.gsl_group = (uint8_t)group_idx; /* set gsl group reg field and mark resource used */ switch (group_idx) { @@ -400,6 +400,7 @@ void dcn20_init_blank( struct output_pixel_processor *bottom_opp = NULL; uint32_t num_opps, opp_id_src0, opp_id_src1; uint32_t otg_active_width = 0, otg_active_height = 0; + unsigned int num_opp_cap = (unsigned int)dc->res_pool->res_cap->num_opp; /* program opp dpg blank color */ color_space = COLOR_SPACE_SRGB; @@ -413,7 +414,7 @@ void dcn20_init_blank( /* get the OPTC source */ tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); - if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { + if (opp_id_src0 >= num_opp_cap) { ASSERT(false); return; } @@ -426,7 +427,7 @@ void dcn20_init_blank( if (num_opps == 2) { otg_active_width = otg_active_width / 2; - if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { + if (opp_id_src1 >= num_opp_cap) { ASSERT(false); return; } @@ -826,7 +827,7 @@ enum dc_status dcn20_enable_stream_timing( unsigned int event_triggers = 0; int opp_cnt = 1; int opp_inst[MAX_PIPES] = {0}; - bool interlace = stream->timing.flags.INTERLACE; + bool interlace = (stream->timing.flags.INTERLACE != 0); int i; struct mpc_dwb_flow_control flow_control; struct mpc *mpc = dc->res_pool->mpc; @@ -1405,9 +1406,9 @@ void dcn20_pipe_control_lock( } if (flip_immediate && lock) { - const int TIMEOUT_FOR_FLIP_PENDING_US = 100000; + const unsigned int TIMEOUT_FOR_FLIP_PENDING_US = 100000U; unsigned int polling_interval_us = 1; - int i; + unsigned int i; temp_pipe = pipe; while (temp_pipe) { @@ -1452,7 +1453,7 @@ void dcn20_pipe_control_lock( struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_pipe = 1; - inst_flags.otg_inst = pipe->stream_res.tg->inst; + inst_flags.otg_inst = (uint8_t)pipe->stream_res.tg->inst; if (pipe->plane_state != NULL) hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; @@ -1870,7 +1871,7 @@ void dcn20_update_dchubp_dpp( static int dcn20_calculate_vready_offset_for_group(struct pipe_ctx *pipe) { struct pipe_ctx *other_pipe; - int vready_offset = pipe->pipe_dlg_param.vready_offset; + unsigned int vready_offset = pipe->pipe_dlg_param.vready_offset; /* Always use the largest vready_offset of all connected pipes */ for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { @@ -2038,7 +2039,7 @@ void dcn20_program_front_end_for_ctx( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; unsigned int prev_hubp_count = 0; unsigned int hubp_count = 0; struct dce_hwseq *hws = dc->hwseq; @@ -2242,7 +2243,7 @@ void dcn20_post_unlock_program_front_end( unsigned int timeout_us = 100000; unsigned int polling_interval_us = 1; struct dce_hwseq *hwseq = dc->hwseq; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) && @@ -2266,7 +2267,7 @@ void dcn20_post_unlock_program_front_end( if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) { struct hubp *hubp = pipe->plane_res.hubp; - int j = 0; + unsigned int j = 0; for (j = 0; j < timeout_us / polling_interval_us && hubp->funcs->hubp_is_flip_pending(hubp); j++) @@ -2285,7 +2286,7 @@ void dcn20_post_unlock_program_front_end( if (resource_is_pipe_type(old_pipe, OTG_MASTER) && resource_is_pipe_type(pipe, OTG_MASTER) && resource_get_odm_slice_count(old_pipe) < resource_get_odm_slice_count(pipe) && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) { - int j = 0; + unsigned int j = 0; struct timing_generator *tg = pipe->stream_res.tg; if (tg->funcs->get_optc_double_buffer_pending) { @@ -2420,7 +2421,7 @@ void dcn20_optimize_bandwidth( struct dc_state *context) { struct hubbub *hubbub = dc->res_pool->hubbub; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; @@ -2438,10 +2439,13 @@ void dcn20_optimize_bandwidth( dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, true); - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + if (dc->clk_mgr->dc_mode_softmax_enabled) { + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if (dc->clk_mgr->clks.dramclk_khz > softmax_memclk_khz && + context->bw_ctx.bw.dcn.clk.dramclk_khz <= softmax_memclk_khz) dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); + } /* increase compbuf size */ if (hubbub->funcs->program_compbuf_size) @@ -2478,7 +2482,7 @@ bool dcn20_update_bandwidth( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; struct dce_hwseq *hws = dc->hwseq; /* recalculate DML parameters */ @@ -2733,7 +2737,8 @@ void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); // Call Helper to track VMID use - vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); + vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, + (uint8_t)pipe_ctx->plane_res.hubp->inst); pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( pipe_ctx->plane_res.hubp, @@ -3126,7 +3131,7 @@ void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) void dcn20_fpga_init_hw(struct dc *dc) { - int i, j; + uint8_t i, j; struct dce_hwseq *hws = dc->hwseq; struct resource_pool *res_pool = dc->res_pool; struct dc_state *context = dc->current_state; @@ -3199,7 +3204,7 @@ void dcn20_fpga_init_hw(struct dc *dc) pipe_ctx->plane_res.hubp = hubp; pipe_ctx->plane_res.dpp = dpp; - pipe_ctx->plane_res.mpcc_inst = dpp->inst; + pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst; hubp->mpcc_id = dpp->inst; hubp->opp_id = OPP_ID_INVALID; hubp->power_gated = false; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c index ad253c586ea1..1797a91b0186 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c @@ -136,6 +136,8 @@ static const struct hwseq_private_funcs dcn20_private_funcs = { .dccg_init = dcn20_dccg_init, .set_blend_lut = dcn20_set_blend_lut, .set_shaper_3dlut = dcn20_set_shaper_3dlut, + .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, + .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, }; void dcn20_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c index 062745389d9a..476c2112afec 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c @@ -146,10 +146,10 @@ bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_pipe.header.type = DMUB_CMD__ABM; cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE; - cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; - cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst; - cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option; - cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst; + cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = (uint8_t)otg_inst; + cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = (uint8_t)pwrseq_inst; + cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = (uint8_t)option; + cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = (uint8_t)panel_inst; cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary; cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data); @@ -287,7 +287,7 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, bool dcn21_is_abm_supported(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) { - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 2aa0f1de8103..3c70d685ba65 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -79,7 +79,7 @@ void dcn30_log_color_state(struct dc *dc, struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; bool is_gamut_remap_available = false; - int i; + unsigned int i; DTN_INFO("DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode" " 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode" @@ -262,7 +262,7 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx, struct dc *dc = pipe_ctx->stream->ctx->dc; struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; bool result = false; - int acquired_rmu = 0; + uint32_t acquired_rmu = 0; int mpcc_id_projected = 0; const struct pwl_params *shaper_lut = NULL; @@ -439,7 +439,7 @@ static void dcn30_set_writeback( ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); ASSERT(wb_info->wb_enabled); ASSERT(wb_info->mpcc_inst >= 0); - ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); + ASSERT(wb_info->mpcc_inst < (int)dc->res_pool->mpcc_count); mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; mcif_buf_params = &wb_info->mcif_buf_params; @@ -581,7 +581,7 @@ void dcn30_program_all_writeback_pipes_in_tree( struct dc_writeback_info wb_info; struct dwbc *dwb; struct dc_stream_status *stream_status = NULL; - int i_wb, i_pipe, i_stream; + unsigned int i_wb, i_pipe, i_stream; DC_LOG_DWB("%s", __func__); ASSERT(stream); @@ -593,7 +593,9 @@ void dcn30_program_all_writeback_pipes_in_tree( } ASSERT(stream_status); - ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); + // Assert non-negative signed capacity first. + ASSERT(dc->res_pool->res_cap->num_dwb >= 0); + ASSERT(stream->num_wb_info <= (unsigned int)dc->res_pool->res_cap->num_dwb); /* For each writeback pipe */ for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) { @@ -645,7 +647,7 @@ void dcn30_init_hw(struct dc *dc) struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; - int i; + unsigned int i; unsigned int edp_num; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; @@ -978,7 +980,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) cursor_cache_enable ? &cursor_attr : NULL)) { unsigned int v_total = stream->adjust.v_total_max ? stream->adjust.v_total_max : stream->timing.v_total; - unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * + unsigned int refresh_hz = (unsigned int)div_u64((unsigned long long)stream->timing.pix_clk_100hz * 100LL, (v_total * stream->timing.h_total)); /* @@ -1006,9 +1008,9 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) unsigned int denom = refresh_hz * 6528; unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us; - tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * + tmr_delay = (uint32_t)(div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), - denom) - 64LL; + denom) - 64LL); /* In some cases the stutter period is really big (tiny modes) in these * cases MALL cant be enabled, So skip these cases to avoid a ASSERT() @@ -1030,9 +1032,9 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) } denom *= 2; - tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * + tmr_delay = (uint32_t)(div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), - denom) - 64LL; + denom) - 64LL); } /* Copy HW cursor */ @@ -1062,9 +1064,9 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part; cmd.mall.cursor_copy_dst.quad_part = (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047; - cmd.mall.cursor_width = cursor_attr.width; - cmd.mall.cursor_height = cursor_attr.height; - cmd.mall.cursor_pitch = cursor_attr.pitch; + cmd.mall.cursor_width = (uint16_t)cursor_attr.width; + cmd.mall.cursor_height = (uint16_t)cursor_attr.height; + cmd.mall.cursor_pitch = (uint16_t)cursor_attr.pitch; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); @@ -1197,10 +1199,13 @@ void dcn30_prepare_bandwidth(struct dc *dc, context->bw_ctx.bw.dcn.clk.p_state_change_support = false; } - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + if (dc->clk_mgr->dc_mode_softmax_enabled) { + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz && + context->bw_ctx.bw.dcn.clk.dramclk_khz > softmax_memclk_khz) dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); + } dcn20_prepare_bandwidth(dc, context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index 5cbae0cdda96..9834d3075487 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -145,6 +145,8 @@ static const struct hwseq_private_funcs dcn30_private_funcs = { .wait_for_blank_complete = dcn20_wait_for_blank_complete, .set_blend_lut = dcn30_set_blend_lut, .set_shaper_3dlut = dcn20_set_shaper_3dlut, + .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, + .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, }; void dcn30_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index 33cc48cd0196..a570333aeac1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -142,6 +142,8 @@ static const struct hwseq_private_funcs dcn301_private_funcs = { .wait_for_blank_complete = dcn20_wait_for_blank_complete, .set_blend_lut = dcn30_set_blend_lut, .set_shaper_3dlut = dcn20_set_shaper_3dlut, + .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, + .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, }; void dcn301_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index b4afb2bc4493..71643ccf23d9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -72,7 +72,7 @@ static void enable_memory_low_power(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; - int i; + unsigned int i; if (dc->debug.enable_mem_low_power.bits.dmcu) { // Force ERAM to shutdown if DMCU is not enabled @@ -116,7 +116,7 @@ void dcn31_init_hw(struct dc *dc) struct resource_pool *res_pool = dc->res_pool; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; - int i; + unsigned int i; if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); @@ -399,6 +399,9 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.hpo_dp_stream_enc, &pipe_ctx->stream_res.encoder_info_frame); + pipe_ctx->stream_res.encoder_info_frame.firmware_controlled_hdr_info_packet + = pipe_ctx->stream->firmware_controlled_hdr_info_packet; + pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( pipe_ctx->stream_res.hpo_dp_stream_enc, &pipe_ctx->stream_res.encoder_info_frame); @@ -409,6 +412,9 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.stream_enc, &pipe_ctx->stream_res.encoder_info_frame); + pipe_ctx->stream_res.encoder_info_frame.firmware_controlled_hdr_info_packet + = pipe_ctx->stream->firmware_controlled_hdr_info_packet; + pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( pipe_ctx->stream_res.stream_enc, &pipe_ctx->stream_res.encoder_info_frame); @@ -665,7 +671,7 @@ void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) { - unsigned int i; + int i; unsigned int triggers = 0; if (params->triggers.surface_update) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c index e56b9a46aecf..b14e6e60b878 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c @@ -147,6 +147,8 @@ static const struct hwseq_private_funcs dcn31_private_funcs = { .set_blend_lut = dcn30_set_blend_lut, .set_shaper_3dlut = dcn20_set_shaper_3dlut, .setup_hpo_hw_control = dcn31_setup_hpo_hw_control, + .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, + .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, }; void dcn31_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 858a06b03b57..09dfbb16dd29 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -147,7 +147,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) // Given any pipe_ctx, return the total ODM combine factor, and optionally return // the OPPids which are used -static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) +static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances) { unsigned int opp_count = 1; struct pipe_ctx *odm_pipe; @@ -211,7 +211,7 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx if (pipe_ctx->stream_res.dsc) { struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); + update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0); /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && @@ -232,60 +232,60 @@ void dcn314_dsc_pg_control( uint32_t pwr_status = power_on ? 0 : 2; uint32_t org_ip_request_cntl = 0; - if (hws->ctx->dc->debug.disable_dsc_power_gate) - return; - if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( hws->ctx->dc->res_pool->dccg, dsc_inst); - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + if (!hws->ctx->dc->debug.disable_dsc_power_gate) { - switch (dsc_inst) { - case 0: /* DSC0 */ - REG_UPDATE(DOMAIN16_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); - REG_WAIT(DOMAIN16_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 1: /* DSC1 */ - REG_UPDATE(DOMAIN17_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + switch (dsc_inst) { + case 0: /* DSC0 */ + REG_UPDATE(DOMAIN16_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN17_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 2: /* DSC2 */ - REG_UPDATE(DOMAIN18_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN16_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 1: /* DSC1 */ + REG_UPDATE(DOMAIN17_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN18_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 3: /* DSC3 */ - REG_UPDATE(DOMAIN19_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN17_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 2: /* DSC2 */ + REG_UPDATE(DOMAIN18_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN19_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - default: - BREAK_TO_DEBUGGER(); - break; + REG_WAIT(DOMAIN18_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 3: /* DSC3 */ + REG_UPDATE(DOMAIN19_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN19_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); - if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( @@ -419,7 +419,7 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc if (dcn314_is_pipe_dig_fifo_on(pipe)) continue; pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); - reset_sync_context_for_pipe(dc, context, i); + reset_sync_context_for_pipe(dc, context, (uint8_t)i); otg_disabled[i] = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index 9900c87b4567..d782080883ab 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -154,6 +154,8 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .setup_hpo_hw_control = dcn31_setup_hpo_hw_control, .calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values, .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio, + .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, + .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, }; void dcn314_hw_sequencer_construct(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index b45ceb570a5c..415b3f875f0d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -226,7 +226,7 @@ static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) */ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) { - int i; + unsigned int i; uint32_t num_ways = 0; uint32_t mall_ss_size_bytes = 0; @@ -351,7 +351,7 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) */ void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; bool enable_subvp = false; if (!dc->ctx || !dc->ctx->dmub_srv) @@ -607,7 +607,7 @@ bool dcn32_set_output_transfer_func(struct dc *dc, */ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; /* Unforce p-state for each pipe if it is not FPO or SubVP. * For FPO and SubVP, if it's already forced disallow, leave @@ -674,7 +674,7 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context) */ void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); bool cache_cursor = false; @@ -728,7 +728,7 @@ void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) */ void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; struct dce_hwseq *hws = dc->hwseq; // Don't force p-state disallow -- can't block dummy p-state @@ -793,7 +793,7 @@ void dcn32_init_hw(struct dc *dc) struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; - int i; + unsigned int i; unsigned int edp_num; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; @@ -1119,7 +1119,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) * Given any pipe_ctx, return the total ODM combine factor, and optionally return * the OPPids which are used * */ -static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) +static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances) { unsigned int opp_count = 1; struct pipe_ctx *odm_pipe; @@ -1175,7 +1175,7 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx * if (pipe_ctx->stream_res.dsc) { struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); + dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0); /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && @@ -1277,7 +1277,7 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_ if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal)) && dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) { pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); - reset_sync_context_for_pipe(dc, context, i); + reset_sync_context_for_pipe(dc, context, (uint8_t)i); otg_disabled[i] = true; } } @@ -1655,6 +1655,7 @@ void dcn32_init_blank( uint32_t num_opps, opp_id_src0, opp_id_src1; uint32_t otg_active_width = 0, otg_active_height = 0; uint32_t i; + unsigned int num_opp_cap = (unsigned int)dc->res_pool->res_cap->num_opp; /* program opp dpg blank color */ color_space = COLOR_SPACE_SRGB; @@ -1668,12 +1669,12 @@ void dcn32_init_blank( /* get the OPTC source */ tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); - if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { + if (opp_id_src0 >= num_opp_cap) { ASSERT(false); return; } - for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { + for (i = 0; i < num_opp_cap; i++) { if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { opp = dc->res_pool->opps[i]; break; @@ -1683,11 +1684,11 @@ void dcn32_init_blank( if (num_opps == 2) { otg_active_width = otg_active_width / 2; - if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { + if (opp_id_src1 >= num_opp_cap) { ASSERT(false); return; } - for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { + for (i = 0; i < num_opp_cap; i++) { if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) { bottom_opp = dc->res_pool->opps[i]; break; @@ -1751,7 +1752,7 @@ bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc, const struct dc_state *cur_ctx, const struct dc_state *new_ctx) { - int i; + unsigned int i; const struct pipe_ctx *cur_pipe, *new_pipe; bool is_seamless = true; @@ -1812,10 +1813,13 @@ void dcn32_prepare_bandwidth(struct dc *dc, context->bw_ctx.bw.dcn.clk.p_state_change_support = false; } - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + if (dc->clk_mgr->dc_mode_softmax_enabled) { + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz && + context->bw_ctx.bw.dcn.clk.dramclk_khz > softmax_memclk_khz) dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); + } dcn20_prepare_bandwidth(dc, context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index 849dae18b738..c68b20104773 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -163,6 +163,8 @@ static const struct hwseq_private_funcs dcn32_private_funcs = { .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy, .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw, .reset_back_end_for_pipe = dcn20_reset_back_end_for_pipe, + .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, + .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, }; void dcn32_hw_sequencer_init_functions(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index f133b52ea958..1a0123338dfa 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -145,7 +145,7 @@ void dcn35_init_hw(struct dc *dc) struct resource_pool *res_pool = dc->res_pool; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; - int i; + unsigned int i; print_pg_status(dc, __func__, ": start"); @@ -403,7 +403,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) // Given any pipe_ctx, return the total ODM combine factor, and optionally return // the OPPids which are used -static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) +static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances) { unsigned int opp_count = 1; struct pipe_ctx *odm_pipe; @@ -467,7 +467,7 @@ void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx * if (pipe_ctx->stream_res.dsc) { struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); + update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0); /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && @@ -621,7 +621,7 @@ void dcn35_z10_restore(const struct dc *dc) void dcn35_init_pipes(struct dc *dc, struct dc_state *context) { - int i; + uint8_t i; struct dce_hwseq *hws = dc->hwseq; struct hubbub *hubbub = dc->res_pool->hubbub; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; @@ -725,7 +725,7 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context) pipe_ctx->plane_res.hubp = hubp; pipe_ctx->plane_res.dpp = dpp; - pipe_ctx->plane_res.mpcc_inst = dpp->inst; + pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst; hubp->mpcc_id = dpp->inst; hubp->opp_id = OPP_ID_INVALID; hubp->power_gated = false; @@ -904,6 +904,13 @@ void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) return; + if (dc->debug.disable_dpp_power_gate) { + /* Workaround for use case when disabled power gating set to 1 */ + /* Force disable cursor if power gating is disabled */ + struct dpp *dpp = pipe_ctx->plane_res.dpp; + if (dpp && dpp->funcs->dpp_force_disable_cursor) + dpp->funcs->dpp_force_disable_cursor(dpp); + } if (hws->funcs.plane_atomic_disable) hws->funcs.plane_atomic_disable(dc, pipe_ctx); @@ -923,14 +930,15 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, bool hpo_frl_stream_enc_acquired = false; bool hpo_dp_stream_enc_acquired = false; int i = 0, j = 0; + unsigned int ui = 0, uj = 0; unsigned int edp_num = 0; struct dc_link *edp_links[MAX_NUM_EDP] = { NULL }; memset(update_state, 0, sizeof(struct pg_block_update)); - for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) { - if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] && - dc->res_pool->hpo_dp_stream_enc[i]) { + for (ui = 0; ui < dc->res_pool->hpo_dp_stream_enc_count; ui++) { + if (context->res_ctx.is_hpo_dp_stream_enc_acquired[ui] && + dc->res_pool->hpo_dp_stream_enc[ui]) { hpo_dp_stream_enc_acquired = true; break; } @@ -941,11 +949,11 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, update_state->pg_res_update[PG_DWB] = true; - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + for (ui = 0; ui < dc->res_pool->pipe_count; ui++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[ui]; for (j = 0; j < PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++) - update_state->pg_pipe_res_update[j][i] = true; + update_state->pg_pipe_res_update[j][ui] = true; if (!pipe_ctx) continue; @@ -968,9 +976,9 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, /* All HUBP/DPP instances must be powered if the DSC inst != HUBP inst */ if (!pipe_ctx->top_pipe && pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) { - for (j = 0; j < dc->res_pool->pipe_count; ++j) { - update_state->pg_pipe_res_update[PG_HUBP][j] = false; - update_state->pg_pipe_res_update[PG_DPP][j] = false; + for (uj = 0; uj < dc->res_pool->pipe_count; ++uj) { + update_state->pg_pipe_res_update[PG_HUBP][uj] = false; + update_state->pg_pipe_res_update[PG_DPP][uj] = false; } } } @@ -990,10 +998,10 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, } /*domain24 controls all the otg, mpc, opp, as long as one otg is still up, avoid enabling OTG PG*/ - for (i = 0; i < dc->res_pool->timing_generator_count; i++) { - struct timing_generator *tg = dc->res_pool->timing_generators[i]; + for (ui = 0; ui < dc->res_pool->timing_generator_count; ui++) { + struct timing_generator *tg = dc->res_pool->timing_generators[ui]; if (tg && tg->funcs->is_tg_enabled(tg)) { - update_state->pg_pipe_res_update[PG_OPTC][i] = false; + update_state->pg_pipe_res_update[PG_OPTC][ui] = false; break; } } @@ -1027,10 +1035,11 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, bool hpo_frl_stream_enc_acquired = false; bool hpo_dp_stream_enc_acquired = false; int i = 0, j = 0; + unsigned int ui = 0, uj = 0; memset(update_state, 0, sizeof(struct pg_block_update)); - for (i = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < (int)dc->res_pool->pipe_count; i++) { struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; @@ -1104,9 +1113,9 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, if (dc->links[i]->type != dc_connection_none) update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true; - for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) { - if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] && - dc->res_pool->hpo_dp_stream_enc[i]) { + for (ui = 0; ui < dc->res_pool->hpo_dp_stream_enc_count; ui++) { + if (context->res_ctx.is_hpo_dp_stream_enc_acquired[ui] && + dc->res_pool->hpo_dp_stream_enc[ui]) { hpo_dp_stream_enc_acquired = true; break; } @@ -1119,8 +1128,8 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true; if (dc->caps.sequential_ono) { - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; + for (ui = 0; ui < dc->res_pool->pipe_count; ui++) { + struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[ui]; if (new_pipe->stream_res.dsc && !new_pipe->top_pipe && update_state->pg_pipe_res_update[PG_DSC][new_pipe->stream_res.dsc->inst]) { @@ -1130,9 +1139,9 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, /* All HUBP/DPP instances must be powered if the DSC inst != HUBP inst */ if (new_pipe->plane_res.hubp && new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) { - for (j = 0; j < dc->res_pool->pipe_count; ++j) { - update_state->pg_pipe_res_update[PG_HUBP][j] = true; - update_state->pg_pipe_res_update[PG_DPP][j] = true; + for (uj = 0; uj < dc->res_pool->pipe_count; ++uj) { + update_state->pg_pipe_res_update[PG_HUBP][uj] = true; + update_state->pg_pipe_res_update[PG_DPP][uj] = true; } } } @@ -1179,6 +1188,7 @@ void dcn35_hw_block_power_down(struct dc *dc, struct pg_block_update *update_state) { int i = 0; + unsigned int pipe_idx = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; if (!pg_cntl) @@ -1192,11 +1202,11 @@ void dcn35_hw_block_power_down(struct dc *dc, } if (!dc->caps.sequential_ono) { - for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (update_state->pg_pipe_res_update[PG_HUBP][i] && - update_state->pg_pipe_res_update[PG_DPP][i]) { + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + if (update_state->pg_pipe_res_update[PG_HUBP][pipe_idx] && + update_state->pg_pipe_res_update[PG_DPP][pipe_idx]) { if (pg_cntl->funcs->hubp_dpp_pg_control) - pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false); + pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, pipe_idx, false); } } @@ -1255,7 +1265,7 @@ void dcn35_hw_block_power_down(struct dc *dc, void dcn35_hw_block_power_up(struct dc *dc, struct pg_block_update *update_state) { - int i = 0; + unsigned int i = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; if (!pg_cntl) @@ -1268,7 +1278,7 @@ void dcn35_hw_block_power_up(struct dc *dc, pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true); if (!dc->caps.sequential_ono) { - for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) + for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) if (update_state->pg_pipe_res_update[PG_DSC][i]) { if (pg_cntl->funcs->dsc_pg_control) pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true); @@ -1297,7 +1307,7 @@ void dcn35_hw_block_power_up(struct dc *dc, void dcn35_root_clock_control(struct dc *dc, struct pg_block_update *update_state, bool power_on) { - int i = 0; + unsigned int i = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; if (!pg_cntl) @@ -1321,7 +1331,7 @@ void dcn35_root_clock_control(struct dc *dc, dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on); } - for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) { if (update_state->pg_pipe_res_update[PG_DSC][i]) { if (power_on) { if (dc->res_pool->dccg->funcs->enable_dsc) @@ -1442,7 +1452,7 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx, void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) { - unsigned int i; + int i; unsigned int triggers = 0; if (params->triggers.surface_update) @@ -1562,7 +1572,8 @@ bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) */ static void dcn35_calc_blocks_to_ungate_for_hw_release(struct dc *dc, struct pg_block_update *update_state) { - int i = 0, j = 0; + unsigned int i = 0; + int j = 0; memset(update_state, 0, sizeof(struct pg_block_update)); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c index 93fe5b262a3d..8720e47fb33a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c @@ -152,7 +152,7 @@ void dcn351_hw_block_power_down(struct dc *dc, void dcn351_hw_block_power_up(struct dc *dc, struct pg_block_update *update_state) { - int i = 0; + unsigned int i = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; if (!pg_cntl || dc->debug.ignore_pg) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 9768b8f6b6fb..c6b62870c46e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -95,6 +95,10 @@ void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx) unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; + //For now assert if location is not pre-blend + if (pipe_ctx->plane_state) + ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE); + // program MPCC_MCM_FIRST_GAMUT_REMAP memset(&mpc_adjust, 0, sizeof(mpc_adjust)); mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; @@ -139,7 +143,7 @@ void dcn401_init_hw(struct dc *dc) struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; - int i; + unsigned int i; unsigned int edp_num; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; @@ -374,6 +378,240 @@ void dcn401_init_hw(struct dc *dc) } } +static void dcn401_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx, + enum MCM_LUT_XABLE *shaper_xable, + enum MCM_LUT_XABLE *lut3d_xable, + enum MCM_LUT_XABLE *lut1d_xable) +{ + enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL; + bool lut1d_enable = false; + struct mpc *mpc = dc->res_pool->mpc; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + + if (!pipe_ctx->plane_state) + return; + shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting; + lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable; + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; + + *lut1d_xable = lut1d_enable ? MCM_LUT_ENABLE : MCM_LUT_DISABLE; + + switch (shaper_3dlut_setting) { + case DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL: + *lut3d_xable = *shaper_xable = MCM_LUT_DISABLE; + break; + case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER: + *lut3d_xable = MCM_LUT_DISABLE; + *shaper_xable = MCM_LUT_ENABLE; + break; + case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT: + *lut3d_xable = *shaper_xable = MCM_LUT_ENABLE; + break; + } +} + +void dcn401_populate_mcm_luts(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_cm2_func_luts mcm_luts, + bool lut_bank_a) +{ + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + int mpcc_id = hubp->inst; + struct mpc *mpc = dc->res_pool->mpc; + union mcm_lut_params m_lut_params; + enum dc_cm2_transfer_func_source lut3d_src = mcm_luts.lut3d_data.lut3d_src; + enum hubp_3dlut_fl_format format = 0; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_width width = 0; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = 0; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = 0; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = 0; + enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE; + enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE; + enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE; + bool rval; + + dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); + + /* 1D LUT */ + if (mcm_luts.lut1d_func) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) + m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; + else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, + mcm_luts.lut1d_func, + &dpp_base->regamma_params, false); + m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + } + if (m_lut_params.pwl) { + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id); + } + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id); + } + + /* Shaper */ + if (mcm_luts.shaper && mcm_luts.lut3d_data.mpc_3dlut_enable) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (mcm_luts.shaper->type == TF_TYPE_HWPWL) + m_lut_params.pwl = &mcm_luts.shaper->pwl; + else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + ASSERT(false); + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, + mcm_luts.shaper, + &dpp_base->regamma_params, true); + m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + } + if (m_lut_params.pwl) { + if (mpc->funcs->mcm.populate_lut) + mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id); + } + } + + /* 3DLUT */ + switch (lut3d_src) { + case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, false); + + if (mcm_luts.lut3d_data.lut3d_func && mcm_luts.lut3d_data.lut3d_func->state.bits.initialized) { + m_lut_params.lut3d = &mcm_luts.lut3d_data.lut3d_func->lut_3d; + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, + mpcc_id); + } + break; + case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: + switch (mcm_luts.lut3d_data.gpu_mem_params.size) { + case DC_CM2_GPU_MEM_SIZE_333333: + if (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33) + width = hubp_3dlut_fl_width_33; + break; + case DC_CM2_GPU_MEM_SIZE_171717: + width = hubp_3dlut_fl_width_17; + break; + case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: + width = hubp_3dlut_fl_width_transformed; + break; + default: + //TODO: handle default case + break; + } + + //check for support + if (mpc->funcs->mcm.is_config_supported && + !mpc->funcs->mcm.is_config_supported(width)) + break; + + if (mpc->funcs->program_lut_read_write_control) + mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id); + + if (hubp->funcs->hubp_program_3dlut_fl_addr) + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr); + + if (mpc->funcs->mcm.program_bit_depth) + mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id); + + switch (mcm_luts.lut3d_data.gpu_mem_params.layout) { + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: + mode = hubp_3dlut_fl_mode_native_1; + addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: + mode = hubp_3dlut_fl_mode_native_2; + addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: + mode = hubp_3dlut_fl_mode_transform; + addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; + break; + default: + mode = hubp_3dlut_fl_mode_disable; + addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + } + if (hubp->funcs->hubp_program_3dlut_fl_mode) + hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode); + + if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode) + hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode); + + switch (mcm_luts.lut3d_data.gpu_mem_params.format_params.format) { + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: + format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: + format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: + format = hubp_3dlut_fl_format_float_fp1_5_10; + break; + } + if (hubp->funcs->hubp_program_3dlut_fl_format) + hubp->funcs->hubp_program_3dlut_fl_format(hubp, format); + if (hubp->funcs->hubp_update_3dlut_fl_bias_scale && + mpc->funcs->mcm.program_bias_scale) { + mpc->funcs->mcm.program_bias_scale(mpc, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale, + mpcc_id); + hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale); + } + + //navi 4x has a bug and r and blue are swapped and need to be worked around here in + //TODO: need to make a method for get_xbar per asic OR do the workaround in program_crossbar for 4x + switch (mcm_luts.lut3d_data.gpu_mem_params.component_order) { + case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA: + default: + crossbar_bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; + crossbar_bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + crossbar_bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; + break; + } + + if (hubp->funcs->hubp_program_3dlut_fl_crossbar) + hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, + crossbar_bit_slice_cr_r, + crossbar_bit_slice_y_g, + crossbar_bit_slice_cb_b); + + if (mpc->funcs->mcm.program_lut_read_write_control) + mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id); + + if (mpc->funcs->mcm.program_3dlut_size) + mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id); + + if (mpc->funcs->update_3dlut_fast_load_select) + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); + + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); + else { + if (mpc->funcs->program_lut_mode) { + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + } + } + break; + + } +} + void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx) { (void)dc; @@ -387,167 +625,51 @@ void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx) bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) { - struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc; struct dpp *dpp_base = pipe_ctx->plane_res.dpp; - struct hubp *hubp = pipe_ctx->plane_res.hubp; - const struct dc_plane_cm *cm = &plane_state->cm; - int mpcc_id = hubp->inst; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; struct mpc *mpc = dc->res_pool->mpc; - union mcm_lut_params m_lut_params; - struct dc_3dlut_dma lut3d_dma; - bool lut_enable; - bool lut_bank_a; + bool result; + const struct pwl_params *lut_params = NULL; bool rval; - bool result = true; - /* decide LUT bank based on current in use */ - mpc->funcs->get_lut_mode(mpc, MCM_LUT_1DLUT, mpcc_id, &lut_enable, &lut_bank_a); - if (!lut_enable) { - mpc->funcs->get_lut_mode(mpc, MCM_LUT_SHAPER, mpcc_id, &lut_enable, &lut_bank_a); - } - if (!lut_enable) { - mpc->funcs->get_lut_mode(mpc, MCM_LUT_3DLUT, mpcc_id, &lut_enable, &lut_bank_a); + if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { + dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a); + return true; } - /* switch to the next bank */ - if (lut_enable) { - lut_bank_a = !lut_bank_a; - } - - /* MCM location fixed to pre-blend */ mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); - - /* 1D LUT */ - lut_enable = cm->flags.bits.blend_enable; - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (lut_enable) { - if (cm->blend_func.type == TF_TYPE_HWPWL) - m_lut_params.pwl = &cm->blend_func.pwl; - else if (cm->blend_func.type == TF_TYPE_DISTRIBUTED_POINTS) { - rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, - &cm->blend_func, - &dpp_base->regamma_params, - false); - m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; - } - - if (!m_lut_params.pwl) { - lut_enable = false; - } - } else { - lut_enable = false; + pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; + // 1D LUT + if (plane_state->blend_tf.type == TF_TYPE_HWPWL) + lut_params = &plane_state->blend_tf.pwl; + else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->blend_tf, + &dpp_base->regamma_params, false); + lut_params = rval ? &dpp_base->regamma_params : NULL; } + result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); + lut_params = NULL; - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut_enable, lut_bank_a, CM_LUT_SIZE_NONE, mpcc_id); - if (lut_enable && mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, &m_lut_params, lut_bank_a, mpcc_id); - - /* Shaper */ - lut_enable = cm->flags.bits.shaper_enable; - if (lut_enable) { - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (cm->shaper_func.type == TF_TYPE_HWPWL) - m_lut_params.pwl = &cm->shaper_func.pwl; - else if (cm->shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { - ASSERT(false); - rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, - &cm->shaper_func, - &dpp_base->shaper_params, - true); - m_lut_params.pwl = rval ? &dpp_base->shaper_params : NULL; - } - if (!m_lut_params.pwl) { - lut_enable = false; - } - } else { - lut_enable = false; + // Shaper + if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL) + lut_params = &plane_state->in_shaper_func.pwl; + else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { + // TODO: dpp_base replace + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->in_shaper_func, + &dpp_base->shaper_params, true); + lut_params = rval ? &dpp_base->shaper_params : NULL; } + result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, lut_enable, lut_bank_a, CM_LUT_SIZE_NONE, mpcc_id); - if (lut_enable && mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_SHAPER, &m_lut_params, lut_bank_a, mpcc_id); - - /* NOTE: Toggling from DMA->Host is not supported atomically as hardware - * blocks writes until 3DLUT FL mode is cleared from HUBP on VUpdate. - * Expectation is either option is used consistently. - */ - - /* 3DLUT */ - lut_enable = cm->flags.bits.lut3d_enable; - if (lut_enable && cm->flags.bits.lut3d_dma_enable) { - /* Fast (DMA) Load Mode */ - /* MPC */ - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut_enable, lut_bank_a, cm->lut3d_dma.size, mpcc_id); - - /* only supports 12 bit */ - if (mpc->funcs->program_lut_read_write_control) - mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, 12, mpcc_id); - - if (mpc->funcs->update_3dlut_fast_load_select) - mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); - - /* HUBP */ - if (hubp->funcs->hubp_program_3dlut_fl_config) - hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); - - if (hubp->funcs->hubp_program_3dlut_fl_crossbar) - hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, cm->lut3d_dma.format); - - if (hubp->funcs->hubp_program_3dlut_fl_addr) - hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); - - if (hubp->funcs->hubp_enable_3dlut_fl) { - hubp->funcs->hubp_enable_3dlut_fl(hubp, true); - } else { - /* GPU memory only supports fast load path */ - BREAK_TO_DEBUGGER(); - lut_enable = false; - result = false; - } - } else { - /* Legacy (Host) Load Mode */ - memset(&m_lut_params, 0, sizeof(m_lut_params)); - - if (cm->flags.bits.lut3d_enable && cm->lut3d_func.state.bits.initialized) { - m_lut_params.lut3d = &cm->lut3d_func.lut_3d; - } else { - lut_enable = false; - } - - /* MPC */ - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, - MCM_LUT_3DLUT, - lut_enable, - lut_bank_a, - cm->lut3d_func.lut_3d.use_tetrahedral_9 ? CM_LUT_SIZE_999 : CM_LUT_SIZE_171717, - mpcc_id); - - if (lut_enable) { - if (mpc->funcs->program_lut_read_write_control) - mpc->funcs->program_lut_read_write_control(mpc, - MCM_LUT_3DLUT, - lut_bank_a, - cm->lut3d_func.lut_3d.use_12bits ? 12 : 10, - mpcc_id); - - if (mpc->funcs->update_3dlut_fast_load_select) - mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, 0xf); - - if (mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, &m_lut_params, lut_bank_a, mpcc_id); - } - - /* HUBP */ - memset(&lut3d_dma, 0, sizeof(lut3d_dma)); - if (hubp->funcs->hubp_program_3dlut_fl_config) - hubp->funcs->hubp_program_3dlut_fl_config(hubp, &lut3d_dma); - - if (hubp->funcs->hubp_enable_3dlut_fl) - hubp->funcs->hubp_enable_3dlut_fl(hubp, false); + // 3D + if (mpc->funcs->program_3dlut) { + if (plane_state->lut3d_func.state.bits.initialized == 1) + result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id); + else + result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); } return result; @@ -1157,8 +1279,8 @@ static bool dcn401_check_no_memory_request_for_cab(struct dc *dc) static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) { - int i; - uint8_t num_ways = 0; + unsigned int i; + uint32_t num_ways = 0; uint32_t mall_ss_size_bytes = 0; mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; @@ -1189,7 +1311,8 @@ static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state * bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable) { union dmub_rb_cmd cmd; - uint8_t ways, i; + uint32_t ways; + uint8_t i; int j; bool mall_ss_unsupported = false; struct dc_plane_state *plane = NULL; @@ -1242,7 +1365,7 @@ bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable) } if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; - cmd.cab.cab_alloc_ways = ways; + cmd.cab.cab_alloc_ways = (uint8_t)ways; DC_LOG_MALL("cab allocation: %d ways. CAB action: DCN_SS_FIT_IN_CAB\n", ways); } else { cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB; @@ -1298,10 +1421,13 @@ void dcn401_prepare_bandwidth(struct dc *dc, context->bw_ctx.bw.dcn.clk.p_state_change_support = false; } - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + if (dc->clk_mgr->dc_mode_softmax_enabled) { + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz && + context->bw_ctx.bw.dcn.clk.dramclk_khz > softmax_memclk_khz) dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); + } /* Increase clocks */ dc->clk_mgr->funcs->update_clocks( @@ -1347,7 +1473,7 @@ void dcn401_optimize_bandwidth( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; struct hubbub *hubbub = dc->res_pool->hubbub; /* enable fams2 if needed */ @@ -1367,10 +1493,13 @@ void dcn401_optimize_bandwidth( hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, true); } - if (dc->clk_mgr->dc_mode_softmax_enabled) - if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && - context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) + if (dc->clk_mgr->dc_mode_softmax_enabled) { + int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000; + + if (dc->clk_mgr->clks.dramclk_khz > softmax_memclk_khz && + context->bw_ctx.bw.dcn.clk.dramclk_khz <= softmax_memclk_khz) dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); + } /* increase compbuf size */ if (hubbub->funcs->program_compbuf_segments) @@ -1433,12 +1562,15 @@ void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params) void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable) { bool fams2_info_required; + bool fams2_enabled; + bool fams2_legacy_no_fams2; if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable) return; - fams2_info_required = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable; - fams2_info_required |= context->bw_ctx.bw.dcn.fams2_global_config.features.bits.legacy_method_no_fams2; + fams2_enabled = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable != 0u; + fams2_legacy_no_fams2 = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.legacy_method_no_fams2 != 0u; + fams2_info_required = fams2_enabled || fams2_legacy_no_fams2; dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_info_required); } @@ -1470,7 +1602,7 @@ static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context, if (otg_master->stream_res.dsc) dcn32_update_dsc_on_stream(otg_master, - otg_master->stream->timing.flags.DSC); + otg_master->stream->timing.flags.DSC != 0u); if (old_otg_master && old_otg_master->stream_res.dsc) { for (i = 0; i < old_opp_head_count; i++) { old_pipe = old_opp_heads[i]; @@ -1818,15 +1950,19 @@ void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx) * This is meant to work around a known HW issue where VREADY will cancel the pending 3DLUT_ENABLE signal regardless * of whether OTG lock is currently being held or not. */ + if (!pipe_ctx) + return; + struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL }; struct pipe_ctx *odm_pipe, *mpc_pipe; int i, wa_pipe_ct = 0; for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) { for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe->bottom_pipe) { - if (mpc_pipe->plane_state && - mpc_pipe->plane_state->cm.flags.bits.lut3d_enable && - mpc_pipe->plane_state->cm.flags.bits.lut3d_dma_enable) { + if (mpc_pipe->plane_state && mpc_pipe->plane_state->mcm_luts.lut3d_data.lut3d_src + == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM + && mpc_pipe->plane_state->mcm_shaper_3dlut_setting + == DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT) { wa_pipes[wa_pipe_ct++] = mpc_pipe; } } @@ -2337,7 +2473,7 @@ void dcn401_program_front_end_for_ctx( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; unsigned int prev_hubp_count = 0; unsigned int hubp_count = 0; struct dce_hwseq *hws = dc->hwseq; @@ -2504,7 +2640,7 @@ void dcn401_post_unlock_program_front_end( unsigned int timeout_us = 100000; unsigned int polling_interval_us = 1; struct dce_hwseq *hwseq = dc->hwseq; - int i; + unsigned int i; for (i = 0; i < dc->res_pool->pipe_count; i++) if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) && @@ -2528,7 +2664,7 @@ void dcn401_post_unlock_program_front_end( if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) { struct hubp *hubp = pipe->plane_res.hubp; - int j = 0; + unsigned int j = 0; for (j = 0; j < timeout_us / polling_interval_us && hubp->funcs->hubp_is_flip_pending(hubp); j++) @@ -2547,7 +2683,7 @@ void dcn401_post_unlock_program_front_end( if (resource_is_pipe_type(old_pipe, OTG_MASTER) && resource_is_pipe_type(pipe, OTG_MASTER) && resource_get_odm_slice_count(old_pipe) < resource_get_odm_slice_count(pipe) && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) { - int j = 0; + unsigned int j = 0; struct timing_generator *tg = pipe->stream_res.tg; if (tg->funcs->get_optc_double_buffer_pending) { @@ -2632,7 +2768,7 @@ bool dcn401_update_bandwidth( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; struct dce_hwseq *hws = dc->hwseq; /* recalculate DML parameters */ @@ -3133,9 +3269,10 @@ void dcn401_program_all_writeback_pipes_in_tree_sequence( struct block_sequence_state *seq_state) { struct dwbc *dwb; - int i_wb, i_pipe; + unsigned int i_wb, i_pipe; + unsigned int num_dwb_cap = (unsigned int)dc->res_pool->res_cap->num_dwb; - if (!stream || stream->num_wb_info > dc->res_pool->res_cap->num_dwb) + if (!stream || (unsigned int)stream->num_wb_info > num_dwb_cap) return; /* For each writeback pipe */ @@ -3297,7 +3434,7 @@ void dcn401_setup_gsl_group_as_lock_sequence( group_idx = find_free_gsl_group(dc); ASSERT(group_idx != 0); - pipe_ctx->stream_res.gsl_group = group_idx; + pipe_ctx->stream_res.gsl_group = (uint8_t)group_idx; /* set gsl group reg field and mark resource used */ switch (group_idx) { @@ -3783,7 +3920,7 @@ void dcn401_update_mpcc_sequence(struct dc *dc, static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) { - int i; + unsigned int i; for (i = 0; i < res_pool->pipe_count; i++) { if (res_pool->hubps[i]->inst == mpcc_inst) @@ -3858,7 +3995,7 @@ void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx, void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context, struct block_sequence_state *seq_state) { - int i; + unsigned int i; unsigned int num_ways = dcn401_calculate_cab_allocation(dc, context); bool cache_cursor = false; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index 5d0dfb36f3e1..0908a791832b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -167,6 +167,8 @@ static const struct hwseq_private_funcs dcn401_private_funcs = { .perform_3dlut_wa_unlock = dcn401_perform_3dlut_wa_unlock, .program_pipe_sequence = dcn401_program_pipe_sequence, .dc_ip_request_cntl = dcn401_dc_ip_request_cntl, + .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, + .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, }; void dcn401_hw_sequencer_init_functions(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c index 46f2f9833d9e..cabfac151940 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -35,7 +35,6 @@ #include "dc_stream_priv.h" #include "dcn35/dcn35_hwseq.h" #include "dcn42/dcn42_hwseq.h" -#include "dce/dmub_hw_lock_mgr.h" #include "dio/dcn10/dcn10_dio.h" #define DC_LOGGER \ @@ -65,7 +64,7 @@ void dcn42_init_hw(struct dc *dc) struct dce_hwseq *hws = dc->hwseq; struct dc_bios *dcb = dc->ctx->dc_bios; struct resource_pool *res_pool = dc->res_pool; - int i; + unsigned int i; unsigned int edp_num; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; @@ -394,6 +393,68 @@ void dcn42_program_cm_hist( plane_state->cm_hist_control, plane_state->color_space); } +static void dc_get_lut_xbar( + enum dc_cm2_gpu_mem_pixel_component_order order, + enum hubp_3dlut_fl_crossbar_bit_slice *cr_r, + enum hubp_3dlut_fl_crossbar_bit_slice *y_g, + enum hubp_3dlut_fl_crossbar_bit_slice *cb_b) +{ + switch (order) { + case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA: + *cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; + *y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; + break; + case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA: + *cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; + *y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; + break; + } +} + +static void dc_get_lut_mode( + enum dc_cm2_gpu_mem_layout layout, + enum hubp_3dlut_fl_mode *mode, + enum hubp_3dlut_fl_addressing_mode *addr_mode) +{ + switch (layout) { + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: + *mode = hubp_3dlut_fl_mode_native_1; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: + *mode = hubp_3dlut_fl_mode_native_2; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: + *mode = hubp_3dlut_fl_mode_transform; + *addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; + break; + default: + *mode = hubp_3dlut_fl_mode_disable; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + } +} + +static void dc_get_lut_format( + enum dc_cm2_gpu_mem_format dc_format, + enum hubp_3dlut_fl_format *format) +{ + switch (dc_format) { + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: + *format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: + *format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: + *format = hubp_3dlut_fl_format_float_fp1_5_10; + break; + } +} + static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc) { if (mpc->funcs->rmcm.power_on_shaper_3dlut && @@ -404,17 +465,119 @@ static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc) return false; } +static bool is_rmcm_3dlut_fl_supported(struct dc *dc, enum dc_cm2_gpu_mem_size size) +{ + if (!dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut) + return false; + if (size == DC_CM2_GPU_MEM_SIZE_171717) + return dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 != 0u; + else if (size == DC_CM2_GPU_MEM_SIZE_333333) + return dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 != 0u; + return false; +} + +static void dcn42_set_mcm_location_post_blend(struct dc *dc, struct pipe_ctx *pipe_ctx, bool bPostBlend) +{ + struct mpc *mpc = dc->res_pool->mpc; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + + if (!pipe_ctx->plane_state) + return; + + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = (bPostBlend) ? + MPCC_MOVABLE_CM_LOCATION_AFTER : + MPCC_MOVABLE_CM_LOCATION_BEFORE; +} + +static void dcn42_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx, + enum MCM_LUT_XABLE *shaper_xable, + enum MCM_LUT_XABLE *lut3d_xable, + enum MCM_LUT_XABLE *lut1d_xable) +{ + enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL; + bool lut1d_enable = false; + struct mpc *mpc = dc->res_pool->mpc; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + + if (!pipe_ctx->plane_state) + return; + shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting; + lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable; + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; + + *lut1d_xable = lut1d_enable ? MCM_LUT_ENABLE : MCM_LUT_DISABLE; + + switch (shaper_3dlut_setting) { + case DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL: + *lut3d_xable = *shaper_xable = MCM_LUT_DISABLE; + break; + case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER: + *lut3d_xable = MCM_LUT_DISABLE; + *shaper_xable = MCM_LUT_ENABLE; + break; + case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT: + *lut3d_xable = *shaper_xable = MCM_LUT_ENABLE; + break; + } +} + +static void fl_get_lut_mode( + enum dc_cm2_gpu_mem_layout layout, + enum dc_cm2_gpu_mem_size size, + enum hubp_3dlut_fl_mode *mode, + enum hubp_3dlut_fl_addressing_mode *addr_mode, + enum hubp_3dlut_fl_width *width) +{ + *width = hubp_3dlut_fl_width_17; + + if (size == DC_CM2_GPU_MEM_SIZE_333333) + *width = hubp_3dlut_fl_width_33; + + switch (layout) { + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: + *mode = hubp_3dlut_fl_mode_native_1; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: + *mode = hubp_3dlut_fl_mode_native_2; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: + *mode = hubp_3dlut_fl_mode_transform; + *addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; + break; + default: + *mode = hubp_3dlut_fl_mode_disable; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + } +} + bool dcn42_program_rmcm_luts( struct hubp *hubp, struct pipe_ctx *pipe_ctx, - const struct dc_plane_cm *cm, + enum dc_cm2_transfer_func_source lut3d_src, + struct dc_cm2_func_luts *mcm_luts, struct mpc *mpc, + bool lut_bank_a, int mpcc_id) { struct dpp *dpp_base = pipe_ctx->plane_res.dpp; union mcm_lut_params m_lut_params = {0}; + enum MCM_LUT_XABLE shaper_xable, lut3d_xable = MCM_LUT_DISABLE, lut1d_xable; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum hubp_3dlut_fl_format format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; + enum hubp_3dlut_fl_width width = hubp_3dlut_fl_width_17; + struct dc *dc = hubp->ctx->dc; + struct hubp_fl_3dlut_config fl_config; struct mpc_fl_3dlut_config mpc_fl_config; struct dc_stream_state *stream = pipe_ctx->stream; @@ -422,23 +585,25 @@ bool dcn42_program_rmcm_luts( // true->false when it can be allocated at DI time struct dc_rmcm_3dlut *rmcm_3dlut = dc_stream_get_3dlut_for_stream(dc, stream, false); - bool lut_bank_a = true; // TODO get from HW - //check to see current pipe is part of a stream with allocated rmcm 3dlut if (!rmcm_3dlut) return false; + rmcm_3dlut->protection_bits = mcm_luts->lut3d_data.rmcm_tmz; + + dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); + /* Shaper */ - if (cm->flags.bits.shaper_enable) { + if (mcm_luts->shaper) { memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (cm->shaper_func.type == TF_TYPE_HWPWL) { - m_lut_params.pwl = &cm->shaper_func.pwl; - } else if (cm->shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { + if (mcm_luts->shaper->type == TF_TYPE_HWPWL) { + m_lut_params.pwl = &mcm_luts->shaper->pwl; + } else if (mcm_luts->shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { ASSERT(false); cm_helper_translate_curve_to_hw_format( dc->ctx, - &cm->shaper_func, + mcm_luts->shaper, &dpp_base->shaper_params, true); m_lut_params.pwl = &dpp_base->shaper_params; } @@ -454,21 +619,58 @@ bool dcn42_program_rmcm_luts( } /* 3DLUT */ - if (!cm->flags.bits.lut3d_dma_enable) { + switch (lut3d_src) { + case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: memset(&m_lut_params, 0, sizeof(m_lut_params)); // Don't know what to do in this case. - } else { - if (!dc_is_rmcm_3dlut_supported(hubp, mpc)) + //case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: + break; + case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: + fl_get_lut_mode(mcm_luts->lut3d_data.gpu_mem_params.layout, + mcm_luts->lut3d_data.gpu_mem_params.size, + &mode, + &addr_mode, + &width); + + if (!dc_is_rmcm_3dlut_supported(hubp, mpc) || + !mpc->funcs->rmcm.is_config_supported( + (width == hubp_3dlut_fl_width_17 || + width == hubp_3dlut_fl_width_transformed) ? 17 : 33)) return false; + // setting native or transformed mode, + dc_get_lut_mode(mcm_luts->lut3d_data.gpu_mem_params.layout, &mode, &addr_mode); + //seems to be only for the MCM - mpc_fl_config.enabled = cm->flags.bits.lut3d_enable; - mpc_fl_config.size = cm->lut3d_dma.size; + dc_get_lut_format(mcm_luts->lut3d_data.gpu_mem_params.format_params.format, &format); + + dc_get_lut_xbar( + mcm_luts->lut3d_data.gpu_mem_params.component_order, + &crossbar_bit_slice_cr_r, + &crossbar_bit_slice_y_g, + &crossbar_bit_slice_cb_b); + + fl_config.mode = mode; + fl_config.enabled = lut3d_xable != MCM_LUT_DISABLE; + fl_config.address = mcm_luts->lut3d_data.gpu_mem_params.addr; + fl_config.format = format; + fl_config.crossbar_bit_slice_y_g = crossbar_bit_slice_y_g; + fl_config.crossbar_bit_slice_cb_b = crossbar_bit_slice_cb_b; + fl_config.crossbar_bit_slice_cr_r = crossbar_bit_slice_cr_r; + fl_config.width = width; + fl_config.protection_bits = rmcm_3dlut->protection_bits; + fl_config.addr_mode = addr_mode; + fl_config.layout = mcm_luts->lut3d_data.gpu_mem_params.layout; + fl_config.bias = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.bias; + fl_config.scale = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.scale; + + mpc_fl_config.enabled = fl_config.enabled; + mpc_fl_config.width = width; mpc_fl_config.select_lut_bank_a = lut_bank_a; - mpc_fl_config.bit_depth = 0; + mpc_fl_config.bit_depth = mcm_luts->lut3d_data.gpu_mem_params.bit_depth; mpc_fl_config.hubp_index = hubp->inst; - mpc_fl_config.bias = cm->lut3d_dma.bias; - mpc_fl_config.scale = cm->lut3d_dma.scale; + mpc_fl_config.bias = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.bias; + mpc_fl_config.scale = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.scale; //1. power down the block mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, false); @@ -476,49 +678,274 @@ bool dcn42_program_rmcm_luts( //2. program RMCM - 3dlut reg programming mpc->funcs->rmcm.fl_3dlut_configure(mpc, &mpc_fl_config, mpcc_id); - /* HUBP */ - if (hubp->funcs->hubp_program_3dlut_fl_config) - hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); - - if (hubp->funcs->hubp_program_3dlut_fl_addr) - hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &fl_config); //3. power on the block mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, true); + + break; + default: + return false; } return true; } -bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state) +void dcn42_populate_mcm_luts(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_cm2_func_luts mcm_luts, + bool lut_bank_a) { - struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc; + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; struct hubp *hubp = pipe_ctx->plane_res.hubp; - const struct dc_plane_cm *cm = &plane_state->cm; - struct mpc *mpc = dc->res_pool->mpc; int mpcc_id = hubp->inst; - bool result; + struct mpc *mpc = dc->res_pool->mpc; + union mcm_lut_params m_lut_params; + enum dc_cm2_transfer_func_source lut3d_src = mcm_luts.lut3d_data.lut3d_src; + enum hubp_3dlut_fl_format format = 0; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_width width = 0; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = 0; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = 0; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = 0; + enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE; + enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE; + enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE; + bool rval; - /* MCM */ - result = dcn401_set_mcm_luts(pipe_ctx, plane_state); + dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); - /* RMCM */ - if (cm->flags.bits.rmcm_enable && cm->flags.bits.lut3d_dma_enable) { - /* TODO - move RMCM to its own block */ + //MCM - setting its location (Before/After) blender + //set to post blend (true) + dcn42_set_mcm_location_post_blend( + dc, + pipe_ctx, + mcm_luts.lut3d_data.mpc_mcm_post_blend); + + //RMCM - 3dLUT+Shaper + if (mcm_luts.lut3d_data.rmcm_3dlut_enable && + is_rmcm_3dlut_fl_supported(dc, mcm_luts.lut3d_data.gpu_mem_params.size)) { dcn42_program_rmcm_luts( hubp, pipe_ctx, - cm, + lut3d_src, + &mcm_luts, mpc, + lut_bank_a, mpcc_id); } + /* 1D LUT */ + if (mcm_luts.lut1d_func) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) + m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; + else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, + mcm_luts.lut1d_func, + &dpp_base->regamma_params, false); + m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + } + if (m_lut_params.pwl) { + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id); + } + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id); + } + + /* Shaper */ + if (mcm_luts.shaper && mcm_luts.lut3d_data.mpc_3dlut_enable) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (mcm_luts.shaper->type == TF_TYPE_HWPWL) + m_lut_params.pwl = &mcm_luts.shaper->pwl; + else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + ASSERT(false); + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, + mcm_luts.shaper, + &dpp_base->regamma_params, true); + m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + } + if (m_lut_params.pwl) { + if (mpc->funcs->mcm.populate_lut) + mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id); + } + } + + /* 3DLUT */ + switch (lut3d_src) { + case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, false); + + if (mcm_luts.lut3d_data.lut3d_func && mcm_luts.lut3d_data.lut3d_func->state.bits.initialized) { + m_lut_params.lut3d = &mcm_luts.lut3d_data.lut3d_func->lut_3d; + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, + mpcc_id); + } + break; + case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: + switch (mcm_luts.lut3d_data.gpu_mem_params.size) { + case DC_CM2_GPU_MEM_SIZE_333333: + width = hubp_3dlut_fl_width_33; + break; + case DC_CM2_GPU_MEM_SIZE_171717: + width = hubp_3dlut_fl_width_17; + break; + case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: + width = hubp_3dlut_fl_width_transformed; + break; + default: + //TODO: Handle default case + break; + } + + //check for support + if (mpc->funcs->mcm.is_config_supported && + !mpc->funcs->mcm.is_config_supported(width)) + break; + + if (mpc->funcs->program_lut_read_write_control) + mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id); + + if (hubp->funcs->hubp_program_3dlut_fl_addr) + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr); + + if (mpc->funcs->mcm.program_bit_depth) + mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id); + + dc_get_lut_mode(mcm_luts.lut3d_data.gpu_mem_params.layout, &mode, &addr_mode); + if (hubp->funcs->hubp_program_3dlut_fl_mode) + hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode); + + if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode) + hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode); + + switch (mcm_luts.lut3d_data.gpu_mem_params.format_params.format) { + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: + format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: + format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: + format = hubp_3dlut_fl_format_float_fp1_5_10; + break; + } + if (hubp->funcs->hubp_program_3dlut_fl_format) + hubp->funcs->hubp_program_3dlut_fl_format(hubp, format); + if (hubp->funcs->hubp_update_3dlut_fl_bias_scale && + mpc->funcs->mcm.program_bias_scale) { + mpc->funcs->mcm.program_bias_scale(mpc, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale, + mpcc_id); + hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale); + } + + //navi 4x has a bug and r and blue are swapped and need to be worked around here in + //TODO: need to make a method for get_xbar per asic OR do the workaround in program_crossbar for 4x + dc_get_lut_xbar( + mcm_luts.lut3d_data.gpu_mem_params.component_order, + &crossbar_bit_slice_cr_r, + &crossbar_bit_slice_y_g, + &crossbar_bit_slice_cb_b); + + if (hubp->funcs->hubp_program_3dlut_fl_crossbar) + hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, + crossbar_bit_slice_cr_r, + crossbar_bit_slice_y_g, + crossbar_bit_slice_cb_b); + + if (mpc->funcs->mcm.program_lut_read_write_control) + mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id); + + if (mpc->funcs->mcm.program_3dlut_size) + mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id); + + if (mpc->funcs->update_3dlut_fast_load_select) + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); + + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); + else { + if (mpc->funcs->program_lut_mode) { + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + } + } + break; + } +} + +bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) +{ + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; + struct mpc *mpc = dc->res_pool->mpc; + bool result; + const struct pwl_params *lut_params = NULL; + bool rval; + + if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { + dcn42_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a); + return true; + } + + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; + // 1D LUT + if (plane_state->blend_tf.type == TF_TYPE_HWPWL) + lut_params = &plane_state->blend_tf.pwl; + else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->blend_tf, + &dpp_base->regamma_params, false); + lut_params = rval ? &dpp_base->regamma_params : NULL; + } + result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); + lut_params = NULL; + + // Shaper + if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL) + lut_params = &plane_state->in_shaper_func.pwl; + else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { + // TODO: dpp_base replace + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->in_shaper_func, + &dpp_base->shaper_params, true); + lut_params = rval ? &dpp_base->shaper_params : NULL; + } + result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); + + // 3D + if (mpc->funcs->program_3dlut) { + if (plane_state->lut3d_func.state.bits.initialized == 1) + result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id); + else + result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); + } + return result; } void dcn42_hardware_release(struct dc *dc) { dcn35_hardware_release(dc); + dc_dmub_srv_release_hw(dc); } static int count_active_streams(const struct dc *dc) @@ -540,7 +967,8 @@ void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, { bool hpo_frl_stream_enc_acquired = false; bool hpo_dp_stream_enc_acquired = false; - int i = 0, j = 0; + unsigned int i = 0; + int j = 0; memset(update_state, 0, sizeof(struct pg_block_update)); @@ -663,7 +1091,8 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, struct pg_block_update *update_state) { bool hpo_dp_stream_enc_acquired = false; - int i = 0, j = 0; + unsigned int i = 0; + int j = 0; memset(update_state, 0, sizeof(struct pg_block_update)); @@ -795,6 +1224,7 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, struct pg_block_update *update_state) { int i = 0; + int pipe_count = dc->res_pool->pipe_count; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; bool block_disabled = true; @@ -808,7 +1238,7 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, pg_cntl->funcs->hpo_pg_control(pg_cntl, false); } - for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { + for (i = pipe_count - 1; i >= 0; i--) { if (update_state->pg_pipe_res_update[PG_HUBP][i] && update_state->pg_pipe_res_update[PG_DPP][i]) { if (pg_cntl->funcs->hubp_dpp_pg_control) @@ -828,7 +1258,7 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, } } - for (i = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < pipe_count; i++) { if (!update_state->pg_pipe_res_update[PG_MPCC][i] || !update_state->pg_pipe_res_update[PG_OPP][i] || !update_state->pg_pipe_res_update[PG_OPTC][i]) { @@ -883,7 +1313,7 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, void dcn42_hw_block_power_up(struct dc *dc, struct pg_block_update *update_state) { - int i = 0; + unsigned int i = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; bool block_enabled = false; @@ -917,7 +1347,7 @@ void dcn42_hw_block_power_up(struct dc *dc, pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true); } - for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) { if (update_state->pg_pipe_res_update[PG_DSC][i]) { if (pg_cntl->funcs->dsc_pg_control) pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true); @@ -944,7 +1374,7 @@ void dcn42_hw_block_power_up(struct dc *dc, void dcn42_root_clock_control(struct dc *dc, struct pg_block_update *update_state, bool power_on) { - int i = 0; + unsigned int i = 0; struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; if (!pg_cntl) @@ -968,7 +1398,7 @@ void dcn42_root_clock_control(struct dc *dc, dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on); } - for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) { if (update_state->pg_pipe_res_update[PG_DSC][i]) { if (power_on) { if (dc->res_pool->dccg->funcs->enable_dsc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h index c4cfeed45b19..0539ee0ffaee 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h @@ -18,11 +18,18 @@ void dcn42_program_cm_hist( bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); +void dcn42_populate_mcm_luts(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_cm2_func_luts mcm_luts, + bool lut_bank_a); + bool dcn42_program_rmcm_luts( struct hubp *hubp, struct pipe_ctx *pipe_ctx, - const struct dc_plane_cm *cm, + enum dc_cm2_transfer_func_source lut3d_src, + struct dc_cm2_func_luts *mcm_luts, struct mpc *mpc, + bool lut_bank_a, int mpcc_id); void dcn42_hardware_release(struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index d1dba7ffcd9b..4b9fcb87e60d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -33,6 +33,7 @@ #include "inc/core_status.h" #include "inc/hw/hw_shared.h" #include "dsc/dsc.h" +#include "link_service_types.h" struct pipe_ctx; struct dc_state; @@ -52,7 +53,13 @@ struct drr_params; struct dc_underflow_debug_data; struct dsc_optc_config; struct vm_system_aperture_param; -struct memory_qos; +struct dc_measured_memory_qos; +struct stream_encoder; +struct hpo_dp_stream_encoder; +struct hpo_frl_stream_encoder; +struct link_training_settings; +struct dc_link; +struct dc_crtc_timing; struct subvp_pipe_control_lock_fast_params { struct dc *dc; bool lock; @@ -91,6 +98,21 @@ struct program_gamut_remap_params { struct pipe_ctx *pipe_ctx; }; +struct hubp_enable_3dlut_fl_params { + struct hubp *hubp; +}; + +struct tg_setup_vertical_interrupt0_params { + struct timing_generator *tg; + uint32_t start_line; + uint32_t end_line; +}; + +struct update_info_frame_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + struct program_manual_trigger_params { struct pipe_ctx *pipe_ctx; }; @@ -707,11 +729,37 @@ struct abort_cursor_offload_update_params { struct pipe_ctx *pipe_ctx; }; +struct cursor_lock_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; + bool lock; +}; + +struct setup_periodic_interrupt_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct send_cursor_info_to_dmu_params { + struct pipe_ctx *pipe_ctx; + int pipe_idx; +}; + struct set_cursor_attribute_params { struct dc *dc; struct pipe_ctx *pipe_ctx; }; +struct hubp_set_cursor_attributes_params { + struct hubp *hubp; + const struct dc_cursor_attributes *attributes; +}; + +struct dpp_set_cursor_attributes_params { + struct dpp *dpp; + struct dc_cursor_attributes *attributes; +}; + struct set_cursor_position_params { struct dc *dc; struct pipe_ctx *pipe_ctx; @@ -739,6 +787,113 @@ struct phantom_hubp_post_enable_params { struct hubp *hubp; }; +struct begin_cursor_offload_update_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct update_cursor_offload_pipe_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct commit_cursor_offload_update_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct stream_enc_update_hdmi_info_packets_params { + struct pipe_ctx *pipe_ctx; +}; + +struct hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params { + struct pipe_ctx *pipe_ctx; +}; + +struct hpo_dp_stream_enc_update_dp_info_packets_params { + struct pipe_ctx *pipe_ctx; +}; + +struct stream_enc_update_dp_info_packets_sdp_line_num_params { + struct pipe_ctx *pipe_ctx; +}; + +struct stream_enc_update_dp_info_packets_params { + struct pipe_ctx *pipe_ctx; +}; + +struct dsc_set_config_simple_params { + struct display_stream_compressor *dsc; + struct dsc_config dsc_cfg; + struct dsc_optc_config dsc_optc_cfg; +}; + +struct stream_enc_dp_set_dsc_config_params { + struct stream_encoder *stream_enc; + const struct dsc_optc_config *dsc_optc_cfg; +}; + +struct hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params { + struct hpo_dp_stream_encoder *hpo_dp_stream_enc; + bool immediate_update; + uint8_t *dsc_packed_pps; + bool pps_sdp_stream; +}; + +struct stream_enc_dp_set_dsc_pps_info_packet_params { + struct stream_encoder *stream_enc; + bool immediate_update; + uint8_t *dsc_packed_pps; + bool pps_sdp_stream; +}; + +struct dp_trace_source_sequence_params { + struct dc_link *link; + enum dpcd_source_sequence source; +}; + +struct set_dmdata_attributes_params { + struct hubp *hubp; + struct dc_dmdata_attributes attr; +}; + +struct link_increase_mst_payload_params { + struct pipe_ctx *pipe_ctx; + uint32_t mst_stream_bw; +}; + +struct link_reduce_mst_payload_params { + struct pipe_ctx *pipe_ctx; + uint32_t mst_stream_bw; +}; + +struct dp_set_test_pattern_params { + struct dc_link *link; + enum dp_test_pattern test_pattern; + enum dp_test_pattern_color_space test_pattern_color_space; + const struct link_training_settings *p_link_settings; + const unsigned char *p_custom_pattern; + unsigned int cust_pattern_size; +}; + +struct link_set_dpms_off_params { + struct pipe_ctx *pipe_ctx; +}; + +struct disable_audio_stream_params { + struct pipe_ctx *pipe_ctx; +}; + +struct prepare_bandwidth_params { + struct dc *dc; + struct dc_state *context; +}; + +struct link_set_dpms_on_params { + struct dc_state *state; + struct pipe_ctx *pipe_ctx; +}; + union block_sequence_params { struct update_plane_addr_params update_plane_addr_params; struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; @@ -747,6 +902,9 @@ union block_sequence_params { struct program_triplebuffer_params program_triplebuffer_params; struct set_input_transfer_func_params set_input_transfer_func_params; struct program_gamut_remap_params program_gamut_remap_params; + struct hubp_enable_3dlut_fl_params hubp_enable_3dlut_fl_params; + struct tg_setup_vertical_interrupt0_params tg_setup_vertical_interrupt0_params; + struct update_info_frame_params update_info_frame_params; struct program_manual_trigger_params program_manual_trigger_params; struct send_dmcub_cmd_params send_dmcub_cmd_params; struct setup_dpp_params setup_dpp_params; @@ -855,12 +1013,38 @@ union block_sequence_params { struct dpp_set_scaler_params dpp_set_scaler_params; struct hubp_mem_program_viewport_params hubp_mem_program_viewport_params; struct abort_cursor_offload_update_params abort_cursor_offload_update_params; + struct cursor_lock_params cursor_lock_params; + struct setup_periodic_interrupt_params setup_periodic_interrupt_params; + struct send_cursor_info_to_dmu_params send_cursor_info_to_dmu_params; struct set_cursor_attribute_params set_cursor_attribute_params; + struct hubp_set_cursor_attributes_params hubp_set_cursor_attributes_params; + struct dpp_set_cursor_attributes_params dpp_set_cursor_attributes_params; struct set_cursor_position_params set_cursor_position_params; struct set_cursor_sdr_white_level_params set_cursor_sdr_white_level_params; struct program_output_csc_params program_output_csc_params; struct hubp_set_blank_params hubp_set_blank_params; struct phantom_hubp_post_enable_params phantom_hubp_post_enable_params; + struct begin_cursor_offload_update_params begin_cursor_offload_update_params; + struct update_cursor_offload_pipe_params update_cursor_offload_pipe_params; + struct commit_cursor_offload_update_params commit_cursor_offload_update_params; + struct stream_enc_update_hdmi_info_packets_params stream_enc_update_hdmi_info_packets_params; + struct hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num_params; + struct hpo_dp_stream_enc_update_dp_info_packets_params hpo_dp_stream_enc_update_dp_info_packets_params; + struct stream_enc_update_dp_info_packets_sdp_line_num_params stream_enc_update_dp_info_packets_sdp_line_num_params; + struct stream_enc_update_dp_info_packets_params stream_enc_update_dp_info_packets_params; + struct dsc_set_config_simple_params dsc_set_config_simple_params; + struct stream_enc_dp_set_dsc_config_params stream_enc_dp_set_dsc_config_params; + struct hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params hpo_dp_stream_enc_dp_set_dsc_pps_info_packet_params; + struct stream_enc_dp_set_dsc_pps_info_packet_params stream_enc_dp_set_dsc_pps_info_packet_params; + struct dp_trace_source_sequence_params dp_trace_source_sequence_params; + struct set_dmdata_attributes_params set_dmdata_attributes_params; + struct link_increase_mst_payload_params link_increase_mst_payload_params; + struct link_reduce_mst_payload_params link_reduce_mst_payload_params; + struct dp_set_test_pattern_params dp_set_test_pattern_params; + struct link_set_dpms_off_params link_set_dpms_off_params; + struct disable_audio_stream_params disable_audio_stream_params; + struct prepare_bandwidth_params prepare_bandwidth_params; + struct link_set_dpms_on_params link_set_dpms_on_params; }; enum block_sequence_func { @@ -871,6 +1055,11 @@ enum block_sequence_func { HUBP_UPDATE_PLANE_ADDR, DPP_SET_INPUT_TRANSFER_FUNC, DPP_PROGRAM_GAMUT_REMAP, + HUBP_ENABLE_3DLUT_FL, + OTG_SETUP_VERTICAL_INTERRUPT, + HWSS_SETUP_PERIODIC_INTERRUPT, + HWSS_UPDATE_INFO_FRAME, + HUBP_SET_DMDATA_ATTRIBUTES, OPTC_PROGRAM_MANUAL_TRIGGER, DMUB_SEND_DMCUB_CMD, DPP_SETUP_DPP, @@ -975,13 +1164,37 @@ enum block_sequence_func { DPP_SET_SCALER, HUBP_MEM_PROGRAM_VIEWPORT, ABORT_CURSOR_OFFLOAD_UPDATE, + HWSS_CURSOR_LOCK, + HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE, + HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE, + HWSS_UPDATE_CURSOR_OFFLOAD_PIPE, + DC_SEND_CURSOR_INFO_TO_DMU, SET_CURSOR_ATTRIBUTE, + HUBP_SET_CURSOR_ATTRIBUTES, + DPP_SET_CURSOR_ATTRIBUTES, SET_CURSOR_POSITION, SET_CURSOR_SDR_WHITE_LEVEL, PROGRAM_OUTPUT_CSC, HUBP_SET_LEGACY_TILING_COMPAT_LEVEL, HUBP_SET_BLANK, PHANTOM_HUBP_POST_ENABLE, + STREAM_ENC_UPDATE_HDMI_INFO_PACKETS, + HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM, + HPO_DP_STREAM_ENC_UPDATE_DP_INFO_PACKETS, + STREAM_ENC_UPDATE_DP_INFO_PACKETS_SDP_LINE_NUM, + STREAM_ENC_UPDATE_DP_INFO_PACKETS, + DSC_SET_CONFIG_SIMPLE, + STREAM_ENC_DP_SET_DSC_CONFIG, + HPO_DP_STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET, + STREAM_ENC_DP_SET_DSC_PPS_INFO_PACKET, + LINK_INCREASE_MST_PAYLOAD, + LINK_REDUCE_MST_PAYLOAD, + DP_TRACE_SOURCE_SEQUENCE, + DP_SET_TEST_PATTERN, + LINK_SET_DPMS_OFF, + DISABLE_AUDIO_STREAM, + PREPARE_BANDWIDTH, + LINK_SET_DPMS_ON, /* This must be the last value in this enum, add new ones above */ HWSS_BLOCK_SEQUENCE_FUNC_COUNT }; @@ -1303,12 +1516,12 @@ struct hw_sequencer_funcs { /** * measure_memory_qos - Measure memory QoS metrics * @dc: DC structure - * @qos: Pointer to memory_qos struct to populate with measured values + * @qos: Pointer to dc_measured_memory_qos struct to populate with measured values * - * Populates the provided memory_qos struct with peak bandwidth, average bandwidth, + * Populates the provided dc_measured_memory_qos struct with peak bandwidth, average bandwidth, * max latency, min latency, and average latency from hardware performance counters. */ - void (*measure_memory_qos)(struct dc *dc, struct memory_qos *qos); + void (*measure_memory_qos)(struct dc *dc, struct dc_measured_memory_qos *qos); }; @@ -1455,6 +1668,40 @@ void hwss_dsc_calculate_and_set_config(union block_sequence_params *params); void hwss_dsc_enable_with_opp(union block_sequence_params *params); +void hwss_dsc_set_config_simple(union block_sequence_params *params); + +void hwss_stream_enc_update_hdmi_info_packets(union block_sequence_params *params); + +void hwss_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params); + +void hwss_hpo_dp_stream_enc_update_dp_info_packets(union block_sequence_params *params); + +void hwss_stream_enc_update_dp_info_packets_sdp_line_num(union block_sequence_params *params); + +void hwss_stream_enc_update_dp_info_packets(union block_sequence_params *params); + +void hwss_stream_enc_dp_set_dsc_config(union block_sequence_params *params); + +void hwss_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params); + +void hwss_stream_enc_dp_set_dsc_pps_info_packet(union block_sequence_params *params); + +void hwss_set_dmdata_attributes(union block_sequence_params *params); + +void hwss_dp_trace_source_sequence(union block_sequence_params *params); + +void hwss_link_increase_mst_payload(union block_sequence_params *params); + +void hwss_link_reduce_mst_payload(union block_sequence_params *params); + +void hwss_dp_set_test_pattern(union block_sequence_params *params); + +void hwss_link_set_dpms_off(union block_sequence_params *params); + +void hwss_prepare_bandwidth(struct dc *dc, union block_sequence_params *params); + +void hwss_link_set_dpms_on(union block_sequence_params *params); + void hwss_program_tg(union block_sequence_params *params); void hwss_tg_program_global_sync(union block_sequence_params *params); @@ -1463,6 +1710,12 @@ void hwss_tg_wait_for_state(union block_sequence_params *params); void hwss_tg_set_vtg_params(union block_sequence_params *params); +void hwss_hubp_enable_3dlut_fl(union block_sequence_params *params); + +void hwss_update_info_frame(struct dc *dc, union block_sequence_params *params); + +void hwss_tg_setup_vertical_interrupt0(union block_sequence_params *params); + void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params); void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params); @@ -1603,12 +1856,20 @@ void hwss_hubp_mem_program_viewport(union block_sequence_params *params); void hwss_abort_cursor_offload_update(union block_sequence_params *params); +void hwss_send_cursor_info_to_dmu(union block_sequence_params *params); + void hwss_set_cursor_attribute(union block_sequence_params *params); +void hwss_hubp_set_cursor_attributes(union block_sequence_params *params); + +void hwss_dpp_set_cursor_attributes(union block_sequence_params *params); + void hwss_set_cursor_position(union block_sequence_params *params); void hwss_set_cursor_sdr_white_level(union block_sequence_params *params); +void hwss_program_gamut_remap(union block_sequence_params *params); + void hwss_program_output_csc(union block_sequence_params *params); void hwss_hubp_set_legacy_tiling_compat_level(union block_sequence_params *params); @@ -1617,6 +1878,18 @@ void hwss_hubp_set_blank(union block_sequence_params *params); void hwss_phantom_hubp_post_enable(union block_sequence_params *params); +void hwss_cursor_lock(union block_sequence_params *params); + +void hwss_begin_cursor_offload_update(union block_sequence_params *params); + +void hwss_commit_cursor_offload_update(union block_sequence_params *params); + +void hwss_update_cursor_offload_pipe(union block_sequence_params *params); + +void hwss_setup_periodic_interrupt(struct dc *dc, union block_sequence_params *params); + +void hwss_disable_audio_stream(struct dc *dc, union block_sequence_params *params); + void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock); @@ -1695,6 +1968,9 @@ void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state, void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, struct timing_generator *tg, struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); +void hwss_add_vertical_interrupt_setup(struct block_sequence_state *seq_state, + struct timing_generator *tg, uint32_t start_line, uint32_t end_line); + void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state, struct timing_generator *tg, int start_line); @@ -2012,6 +2288,14 @@ void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, struct dc *dc, struct pipe_ctx *pipe_ctx); +void hwss_add_hubp_set_cursor_attributes(struct block_sequence_state *seq_state, + struct hubp *hubp, + const struct dc_cursor_attributes *attributes); + +void hwss_add_dpp_set_cursor_attributes(struct block_sequence_state *seq_state, + struct dpp *dpp, + struct dc_cursor_attributes *attributes); + void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, struct dc *dc, struct pipe_ctx *pipe_ctx); @@ -2056,4 +2340,105 @@ void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq enum dc_pixel_encoding pixel_encoding, bool is_otg_master); +void hwss_add_hubp_enable_3dlut_fl(struct block_sequence_state *seq_state, + struct hubp *hubp); + +void hwss_add_begin_cursor_offload_update(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_cursor_lock(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool lock); + +void hwss_add_send_update_cursor_info_to_dmu(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + int index); + +void hwss_add_update_cursor_offload_pipe(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_commit_cursor_offload_update(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_stream_enc_update_hdmi_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_hpo_dp_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_stream_enc_update_dp_info_packets_sdp_line_num(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_stream_enc_update_dp_info_packets(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_dsc_set_config(struct block_sequence_state *seq_state, + struct display_stream_compressor *dsc, + const struct dsc_config *dsc_cfg, + const struct dsc_optc_config *dsc_optc_cfg); + +void hwss_add_stream_enc_dp_set_dsc_config(struct block_sequence_state *seq_state, + struct stream_encoder *stream_enc, + const struct dsc_optc_config *dsc_optc_cfg); + +void hwss_add_hpo_dp_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, + struct hpo_dp_stream_encoder *hpo_dp_stream_enc, + bool immediate_update, + uint8_t *dsc_packed_pps, + bool pps_sdp_stream); + +void hwss_add_stream_enc_dp_set_dsc_pps_info_packet(struct block_sequence_state *seq_state, + struct stream_encoder *stream_enc, + bool immediate_update, + uint8_t *dsc_packed_pps, + bool pps_sdp_stream); + +void hwss_add_setup_periodic_interrupt(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_dp_trace_source_sequence(struct block_sequence_state *seq_state, + struct dc_link *link, + enum dpcd_source_sequence source); + +void hwss_add_set_dmdata_attributes(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_link_increase_mst_payload(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + uint32_t mst_stream_bw); + +void hwss_add_link_reduce_mst_payload(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, + uint32_t mst_stream_bw); + +void hwss_add_dp_set_test_pattern(struct block_sequence_state *seq_state, + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size); + +void hwss_add_link_set_dpms_off(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_disable_audio_stream(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_prepare_bandwidth(struct block_sequence_state *seq_state, + struct dc *dc, + struct dc_state *context); + +void hwss_add_link_set_dpms_on(struct block_sequence_state *seq_state, + struct dc_state *state, + struct pipe_ctx *pipe_ctx); + #endif /* __DC_HW_SEQUENCER_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h index d1656c9d50df..3fdd9a770334 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h +++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h @@ -79,7 +79,7 @@ static inline struct bw_fixed bw_int_to_fixed(int64_t value) static inline int32_t bw_fixed_to_int(struct bw_fixed value) { - return BW_FIXED_GET_INTEGER_PART(value.value); + return (int32_t)BW_FIXED_GET_INTEGER_PART(value.value); } struct bw_fixed bw_frc_to_fixed(int64_t num, int64_t denum); @@ -126,7 +126,7 @@ static inline struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw static inline struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct bw_fixed arg2) { struct bw_fixed res; - div64_u64_rem(arg1.value, arg2.value, (uint64_t *)&res.value); + div64_u64_rem((uint64_t)arg1.value, (uint64_t)arg2.value, (uint64_t *)&res.value); return res; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index e960ca9062ad..a99e1937f8ce 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -707,7 +707,7 @@ struct dc_bounding_box_max_clk { int max_phyclk_mhz; }; -struct memory_qos { +struct dc_measured_memory_qos { uint32_t peak_bw_mbps; uint32_t avg_bw_mbps; uint32_t max_latency_ns; @@ -715,4 +715,12 @@ struct memory_qos { uint32_t avg_latency_ns; }; +struct dc_requested_memory_qos { + uint32_t bandwidth_lb_in_mbps; + uint32_t calculated_avg_bw_in_mbps; + uint32_t max_latency_ub_in_ns; + uint32_t avg_latency_ub_in_ns; + uint32_t max_bw_budget_in_mbps; +}; + #endif /* _CORE_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 21224fd6b36d..dcce81e3d97c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -28,6 +28,7 @@ #define __DAL_CLK_MGR_H__ #include "dc.h" +#include "core_types.h" #include "dm_pp_smu.h" /* Constants */ @@ -362,6 +363,27 @@ struct clk_mgr_funcs { uint32_t (*set_smartmux_switch)(struct clk_mgr *clk_mgr, uint32_t pins_to_set); unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type); + /** + * override_memory_bandwidth_request - Override the DCN nominal memory + * bandwidth request sent to PMFW, independent of the current display + * mode. For debug use only. + * @clk_mgr: clock manager instance + * @bw_kbps: requested bandwidth in kbps; 0 clears the override + * + * Return: capped bandwidth value actually applied (kbps) + */ + unsigned int (*override_memory_bandwidth_request)( + struct clk_mgr *clk_mgr, + unsigned int bw_kbps); + /** + * get_requested_memory_qos - Retrieve current QoS request from the clock manager's + * current clock state, reflecting any active bandwidth overrides. + * @clk_mgr: clock manager instance + * @qos: pointer to dc_requested_memory_qos structure to populate + */ + void (*get_requested_memory_qos)( + struct clk_mgr *clk_mgr, + struct dc_requested_memory_qos *qos); }; struct clk_mgr { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 2a5a81d15950..1c18898aa475 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -89,7 +89,7 @@ enum hubp_3dlut_fl_addressing_mode { enum hubp_3dlut_fl_width { hubp_3dlut_fl_width_17 = 17, hubp_3dlut_fl_width_33 = 33, - hubp_3dlut_fl_width_17_transformed = 4916, //mpc default + hubp_3dlut_fl_width_transformed = 4916, //mpc default }; enum hubp_3dlut_fl_crossbar_bit_slice { @@ -99,6 +99,22 @@ enum hubp_3dlut_fl_crossbar_bit_slice { hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3 }; +struct hubp_fl_3dlut_config { + bool enabled; + enum hubp_3dlut_fl_width width; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_format format; + uint16_t bias; + uint16_t scale; + struct dc_plane_address address; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum dc_cm2_gpu_mem_layout layout; + uint8_t protection_bits; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r; +}; + struct hubp { const struct hubp_funcs *funcs; struct dc_context *ctx; @@ -133,7 +149,7 @@ struct surface_flip_registers { uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; - bool tmz_surface; + uint8_t tmz_surface; bool immediate; uint8_t vmid; bool grph_stereo; @@ -273,15 +289,24 @@ struct hubp_funcs { void (*hubp_wait_pipe_read_start)(struct hubp *hubp); void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); + void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale); + void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp, + enum hubp_3dlut_fl_mode mode); + void (*hubp_program_3dlut_fl_format)(struct hubp *hubp, + enum hubp_3dlut_fl_format format); void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp, - const struct dc_plane_address *address); - void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, - const struct dc_3dlut_dma *config); + const struct dc_plane_address address); void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group); void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable); + void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); + void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width); + void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits); void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp, - enum dc_cm_lut_pixel_format format); - int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); + uint32_t (*hubp_get_3dlut_fl_done)(struct hubp *hubp); + void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg); void (*hubp_clear_tiling)(struct hubp *hubp); uint32_t (*hubp_get_current_read_line)(struct hubp *hubp); uint32_t (*hubp_get_det_config_error)(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index f5617674bea8..54eb2eba68bf 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -54,7 +54,6 @@ #include "dc_hw_types.h" #include "hw_shared.h" #include "transform.h" -#include "dc_types.h" #define MAX_MPCC 6 #define MAX_OPP 6 @@ -102,6 +101,13 @@ enum mpcc_movable_cm_location { MPCC_MOVABLE_CM_LOCATION_AFTER, }; +enum MCM_LUT_XABLE { + MCM_LUT_DISABLE, + MCM_LUT_DISABLED = MCM_LUT_DISABLE, + MCM_LUT_ENABLE, + MCM_LUT_ENABLED = MCM_LUT_ENABLE, +}; + enum MCM_LUT_ID { MCM_LUT_3DLUT, MCM_LUT_1DLUT, @@ -110,7 +116,7 @@ enum MCM_LUT_ID { struct mpc_fl_3dlut_config { bool enabled; - enum dc_cm_lut_size size; + uint16_t width; bool select_lut_bank_a; uint16_t bit_depth; int hubp_index; @@ -1069,11 +1075,8 @@ struct mpc_funcs { * * void */ - void (*populate_lut)(struct mpc *mpc, - const enum MCM_LUT_ID id, - const union mcm_lut_params *params, - const bool lut_bank_a, - const int mpcc_id); + void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id); /** * @program_lut_read_write_control: @@ -1084,18 +1087,13 @@ struct mpc_funcs { * - [in/out] mpc - MPC context. * - [in] id * - [in] lut_bank_a - * - [in] bit_depth * - [in] mpcc_id * * Return: * * void */ - void (*program_lut_read_write_control)(struct mpc *mpc, - const enum MCM_LUT_ID id, - const bool lut_bank_a, - const unsigned int bit_depth, - const int mpcc_id); + void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id); /** * @program_lut_mode: @@ -1105,44 +1103,33 @@ struct mpc_funcs { * Parameters: * - [in/out] mpc - MPC context. * - [in] id - * - [in] enable + * - [in] xable * - [in] lut_bank_a - * - [in] size * - [in] mpcc_id * * Return: * * void */ - void (*program_lut_mode)(struct mpc *mpc, - const enum MCM_LUT_ID id, - const bool enable, - const bool lut_bank_a, - const enum dc_cm_lut_size size, - const int mpcc_id); - + void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable, + bool lut_bank_a, int mpcc_id); /** - * @get_lut_mode: - * - * Obtains enablement and ram bank status. - * - * Parameters: - * - [in/out] mpc - MPC context. - * - [in] id - * - [in] mpcc_id - * - [out] enable - * - [out] lut_bank_a - * - * Return: - * - * void - */ - void (*get_lut_mode)(struct mpc *mpc, - const enum MCM_LUT_ID id, - const int mpcc_id, - bool *enable, - bool *lut_bank_a); + * @mcm: + * + * MPC MCM new HW sequential programming functions + */ + struct { + void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id); + void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); + void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); + bool (*is_config_supported)(uint32_t width); + void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, + bool lut_bank_a, bool enabled, int mpcc_id); + + void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id); + } mcm; /** * @rmcm: @@ -1155,11 +1142,9 @@ struct mpc_funcs { void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, bool enabled, int mpcc_id); - void (*program_lut_mode)(struct mpc *mpc, - bool enable, - bool lut_bank_a, - int mpcc_id); - void (*program_3dlut_size)(struct mpc *mpc, const enum dc_cm_lut_size size, int mpcc_id); + void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_XABLE xable, + bool lut_bank_a, int mpcc_id); + void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id); void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); bool (*is_config_supported)(uint32_t width); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index e1428a83ecbc..73cc34ea7726 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -356,8 +356,8 @@ struct opp_funcs { void (*opp_program_dpg_dimensions)( struct output_pixel_processor *opp, - int width, - int height); + uint32_t width, + uint32_t height); bool (*dpg_is_blanked)( struct output_pixel_processor *opp); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h index 0d5a8358a778..7f371cbb35cd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h @@ -68,7 +68,6 @@ struct optc { int pstate_keepout; struct dc_crtc_timing orginal_patched_timing; enum signal_type signal; - uint32_t max_frame_count; }; void optc1_read_otg_state(struct timing_generator *optc, struct dcn_otg_state *s); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 27f950ae45ee..a9bf960dacbc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -93,6 +93,7 @@ struct encoder_info_frame { /* Adaptive Sync SDP*/ struct dc_info_packet adaptive_sync; struct enc_sdp_line_num sdp_line_num; + bool firmware_controlled_hdr_info_packet; }; struct encoder_unblank_param { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 2f70bb476c97..3a80369cde16 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -32,9 +32,9 @@ struct dc_bios; /* Contains CRTC vertical/horizontal pixel counters */ struct crtc_position { - int32_t vertical_count; - int32_t horizontal_count; - int32_t nominal_vcount; + uint32_t vertical_count; + uint32_t horizontal_count; + uint32_t nominal_vcount; }; struct dcp_gsl_params { @@ -321,7 +321,7 @@ struct timing_generator { const struct timing_generator_funcs *funcs; struct dc_bios *bp; struct dc_context *ctx; - int inst; + uint32_t inst; }; struct dc_crtc_timing; diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_service.h b/drivers/gpu/drm/amd/display/dc/inc/link_service.h index 57bb82e94942..d0609443af49 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_service.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_service.h @@ -110,7 +110,7 @@ struct link_service { struct dc_sink *(*add_remote_sink)( struct dc_link *link, const uint8_t *edid, - int len, + unsigned int len, struct dc_sink_init_data *init_data); void (*remove_remote_sink)(struct dc_link *link, struct dc_sink *sink); bool (*get_hpd_state)(struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h index 26cb1459b743..7a1ecb8d986f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h +++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h @@ -155,63 +155,63 @@ * read given register and fill in field value in output parameter */ #define REG_GET(reg_name, field, val) \ generic_reg_get(CTX, REG(reg_name), \ - FN(reg_name, field), val) + FN(reg_name, field), (uint32_t *)val) #define REG_GET_2(reg_name, f1, v1, f2, v2) \ generic_reg_get2(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2) #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \ generic_reg_get3(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3) #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \ generic_reg_get4(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3, \ - FN(reg_name, f4), v4) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3, \ + FN(reg_name, f4), (uint32_t *)v4) #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ generic_reg_get5(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3, \ - FN(reg_name, f4), v4, \ - FN(reg_name, f5), v5) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3, \ + FN(reg_name, f4), (uint32_t *)v4, \ + FN(reg_name, f5), (uint32_t *)v5) #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ generic_reg_get6(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3, \ - FN(reg_name, f4), v4, \ - FN(reg_name, f5), v5, \ - FN(reg_name, f6), v6) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3, \ + FN(reg_name, f4), (uint32_t *)v4, \ + FN(reg_name, f5), (uint32_t *)v5, \ + FN(reg_name, f6), (uint32_t *)v6) #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ generic_reg_get7(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3, \ - FN(reg_name, f4), v4, \ - FN(reg_name, f5), v5, \ - FN(reg_name, f6), v6, \ - FN(reg_name, f7), v7) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3, \ + FN(reg_name, f4), (uint32_t *)v4, \ + FN(reg_name, f5), (uint32_t *)v5, \ + FN(reg_name, f6), (uint32_t *)v6, \ + FN(reg_name, f7), (uint32_t *)v7) #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ generic_reg_get8(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3, \ - FN(reg_name, f4), v4, \ - FN(reg_name, f5), v5, \ - FN(reg_name, f6), v6, \ - FN(reg_name, f7), v7, \ - FN(reg_name, f8), v8) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3, \ + FN(reg_name, f4), (uint32_t *)v4, \ + FN(reg_name, f5), (uint32_t *)v5, \ + FN(reg_name, f6), (uint32_t *)v6, \ + FN(reg_name, f7), (uint32_t *)v7, \ + FN(reg_name, f8), (uint32_t *)v8) /* macro to poll and wait for a register field to read back given value */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h index 23daf98b8aa8..6a97a3e28bd2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h @@ -8,9 +8,26 @@ #include "dc.h" #include "dml_top_soc_parameter_types.h" +/* Forward declarations — callers that dereference these structs must include + * the full UTM model headers themselves. */ +struct utm_qos_model; +struct utm_qos_model_dchub_v2; + struct soc_and_ip_translator_funcs { - void (*get_soc_bb)(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config); + void (*get_soc_bb)( + struct dml2_soc_bb *soc_bb, + const struct dc *dc, + const struct dml2_configuration_options *config); void (*get_ip_caps)(struct dml2_ip_capabilities *dml_ip_caps); + /** + * get_utm_qos_model - Return the static UTM QoS model for this DCN + * generation. Caller provides storage for @qos_model and @dchub. + * @qos_model: output — populated with SoC bounding box and SOP table + * @dchub: output — populated with DCHUB client extension data + */ + void (*get_utm_qos_model)( + struct utm_qos_model *qos_model, + struct utm_qos_model_dchub_v2 *dchub); }; struct soc_and_ip_translator { diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index 015f3659cf77..8958d286dde1 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -210,7 +210,7 @@ bool dce110_vblank_set(struct irq_service *irq_service, dc_interrupt_to_irq_source(irq_service->ctx->dc, info->src_id, info->ext_id); - uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; + unsigned int pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; struct timing_generator *tg; diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index 060460abc377..ae6ed3a52d53 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -199,7 +199,6 @@ static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video unsigned int channel_count; unsigned int channel = 0; unsigned int modes = 0; - unsigned int sampling_rate_in_hz = 0; // get audio test mode and test pattern parameters core_link_read_dpcd( @@ -232,38 +231,10 @@ static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video } } - // translate sampling rate - switch (dpcd_test_mode.bits.sampling_rate) { - case AUDIO_SAMPLING_RATE_32KHZ: - sampling_rate_in_hz = 32000; - break; - case AUDIO_SAMPLING_RATE_44_1KHZ: - sampling_rate_in_hz = 44100; - break; - case AUDIO_SAMPLING_RATE_48KHZ: - sampling_rate_in_hz = 48000; - break; - case AUDIO_SAMPLING_RATE_88_2KHZ: - sampling_rate_in_hz = 88200; - break; - case AUDIO_SAMPLING_RATE_96KHZ: - sampling_rate_in_hz = 96000; - break; - case AUDIO_SAMPLING_RATE_176_4KHZ: - sampling_rate_in_hz = 176400; - break; - case AUDIO_SAMPLING_RATE_192KHZ: - sampling_rate_in_hz = 192000; - break; - default: - sampling_rate_in_hz = 0; - break; - } - link->audio_test_data.flags.test_requested = 1; link->audio_test_data.flags.disable_video = disable_video; - link->audio_test_data.sampling_rate = sampling_rate_in_hz; - link->audio_test_data.channel_count = channel_count; + link->audio_test_data.sampling_rate = (uint8_t)dpcd_test_mode.bits.sampling_rate; + link->audio_test_data.channel_count = (uint8_t)channel_count; link->audio_test_data.pattern_type = test_pattern; if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) { @@ -885,7 +856,7 @@ bool dp_set_test_pattern( struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_dig = 1; - inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; + inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv, true, @@ -933,7 +904,7 @@ bool dp_set_test_pattern( struct dmub_hw_lock_inst_flags inst_flags = { 0 }; hw_locks.bits.lock_dig = 1; - inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; + inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv, false, diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c index dbbedeeed298..04df75114dd5 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c @@ -63,7 +63,7 @@ void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx, time_slot_in_ms = dc_fixpt_from_fraction(32 * 4, link_bw_in_kbps); mtp_cnt_per_h_blank = dc_fixpt_div(h_blank_in_ms, dc_fixpt_mul_int(time_slot_in_ms, 64)); - hblank_min_symbol_width = dc_fixpt_floor( + hblank_min_symbol_width = (uint16_t)dc_fixpt_floor( dc_fixpt_mul(mtp_cnt_per_h_blank, throttled_vcp_size)); } @@ -98,7 +98,7 @@ void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx) &stream->timing, stream->output_color_space, stream->use_vsc_sdp_for_colorimetry, - stream->timing.flags.DSC, + (stream->timing.flags.DSC != 0), false); link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 794dd6a95918..1ac6a22fecfe 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -290,12 +290,12 @@ static bool i2c_read( struct i2c_payload payloads[2] = { { .write = true, - .address = address, + .address = (uint8_t)address, .length = 1, .data = &offs_data }, { .write = false, - .address = address, + .address = (uint8_t)address, .length = len, .data = buffer } }; @@ -524,7 +524,7 @@ static void read_current_link_settings_on_detect(struct dc_link *link) uint8_t link_rate_set = 0; uint32_t read_dpcd_retry_cnt = 10; enum dc_status status = DC_ERROR_UNEXPECTED; - int i; + unsigned int i; union max_down_spread max_down_spread = {0}; // Read DPCD 00101h to find out the number of lanes currently set @@ -655,7 +655,7 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link) unsigned long long enter_timestamp; unsigned long long finish_timestamp; unsigned long long time_taken_in_ns; - int tries_taken; + unsigned int tries_taken; /** * this function will only exist if we are on dcn21 (is_in_alt_mode is a @@ -1562,7 +1562,7 @@ static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink struct dc_sink *link_add_remote_sink( struct dc_link *link, const uint8_t *edid, - int len, + unsigned int len, struct dc_sink_init_data *init_data) { struct dc_sink *dc_sink; @@ -1619,7 +1619,7 @@ struct dc_sink *link_add_remote_sink( void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) { - int i; + unsigned int i; if (!link->sink_count) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.h b/drivers/gpu/drm/amd/display/dc/link/link_detection.h index 1ab29476060b..e8d29fa1550d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.h +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.h @@ -32,7 +32,7 @@ bool link_detect_connection_type(struct dc_link *link, struct dc_sink *link_add_remote_sink( struct dc_link *link, const uint8_t *edid, - int len, + unsigned int len, struct dc_sink_init_data *init_data); void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink); bool link_reset_cur_dp_mst_topology(struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index e12c25896364..21f64946b993 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -546,24 +546,24 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; /* stream encoder index */ - config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; + config.stream_enc_idx = (uint8_t)(pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA); if (dp_is_128b_132b_signal(pipe_ctx)) config.stream_enc_idx = - pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; + (uint8_t)(pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0); /* dig back end */ config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; /* link encoder index */ - config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; + config.link_enc_idx = (uint8_t)(link_enc->transmitter - TRANSMITTER_UNIPHY_A); if (dp_is_128b_132b_signal(pipe_ctx)) - config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; + config.link_enc_idx = (uint8_t)pipe_ctx->link_res.hpo_dp_link_enc->inst; /* dio output index is dpia index for DPIA endpoint & dcio index by default */ if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) - config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; + config.dio_output_idx = (uint8_t)(pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1); else - config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; + config.dio_output_idx = (uint8_t)(link_enc->transmitter - TRANSMITTER_UNIPHY_A); /* phy index */ @@ -1411,7 +1411,7 @@ static bool write_128b_132b_sst_payload_allocation_table( if (allocate) { avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); - req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); + req_slot_count = (uint8_t)dc_fixpt_ceil(avg_time_slots_per_mtp); /// Validation should filter out modes that exceed link BW ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); if (req_slot_count > MAX_MTP_SLOT_COUNT) @@ -1811,7 +1811,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) write_scdc_data( stream->link->ddc, stream->phy_pix_clk, - stream->timing.flags.LTE_340MCSC_SCRAMBLE); + (stream->timing.flags.LTE_340MCSC_SCRAMBLE != 0)); memset(&stream->link->cur_link_settings, 0, sizeof(struct dc_link_settings)); @@ -2016,9 +2016,7 @@ static enum dc_status enable_link_dp_mst( return enable_link_dp(state, pipe_ctx); } -static enum dc_status enable_link_analog( - struct dc_state *state, - struct pipe_ctx *pipe_ctx) +static enum dc_status enable_link_analog(struct pipe_ctx *pipe_ctx) { struct dc_link *link = pipe_ctx->stream->link; @@ -2083,7 +2081,7 @@ static enum dc_status enable_link( status = DC_OK; break; case SIGNAL_TYPE_RGB: - status = enable_link_analog(state, pipe_ctx); + status = enable_link_analog(pipe_ctx); break; case SIGNAL_TYPE_VIRTUAL: status = enable_link_virtual(pipe_ctx); @@ -2099,10 +2097,10 @@ static enum dc_status enable_link( return status; } -static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) +static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int stream_bw) { struct dc_link *link = stream->sink->link; - int req_bw = bw; + int req_bw = stream_bw; DC_LOGGER_INIT(link->ctx->logger); @@ -2110,39 +2108,38 @@ static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, i return false; if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { - int sink_index = 0; - int i = 0; + int sink_index = -1; + unsigned int i = 0; for (i = 0; i < link->sink_count; i++) { if (link->remote_sinks[i] == NULL) continue; - if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) + if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) { + DC_LOG_DEBUG("%s: add remote_sink=%s, request_bw=%d\n", __func__, + (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), + link->dpia_bw_alloc_config.remote_sink_req_bw[i]); + req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; - else + } else sink_index = i; } - link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; - } + if (sink_index >= 0) + link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = stream_bw; + else + DC_LOG_WARNING("%s: stream sink_id=%u not found in remote_sinks[]\n", + __func__, stream->sink->sink_id); - link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link); - req_bw += link->dpia_bw_alloc_config.dp_overhead; + if (req_bw) { + link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link); + req_bw += link->dpia_bw_alloc_config.dp_overhead; + } else + link->dpia_bw_alloc_config.dp_overhead = 0; + } link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); - if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { - int i = 0; - - for (i = 0; i < link->sink_count; i++) { - if (link->remote_sinks[i] == NULL) - continue; - DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, - (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), - link->dpia_bw_alloc_config.remote_sink_req_bw[i]); - } - } - return true; } diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 7e7682d7dfc8..032c97660658 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -381,7 +381,7 @@ static bool encoder_is_external_dp( static void link_destruct(struct dc_link *link) { - int i; + unsigned int i; if (link->ddc) link_destroy_ddc_service(&link->ddc); @@ -516,7 +516,7 @@ static bool construct_phy(struct dc_link *link, sizeof(struct dc_link_settings)); link->link_id = - bios->funcs->get_connector_id(bios, init_params->connector_index); + bios->funcs->get_connector_id(bios, (uint8_t)init_params->connector_index); link->ep_type = DISPLAY_ENDPOINT_PHY; @@ -544,7 +544,7 @@ static bool construct_phy(struct dc_link *link, if (bios->funcs->get_disp_connector_caps_info) { bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info); - link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY; + link->is_internal_display = (disp_connect_caps_info.INTERNAL_DISPLAY != 0); DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display); } @@ -568,7 +568,9 @@ static bool construct_phy(struct dc_link *link, goto ddc_create_fail; } - if (!link->ddc->ddc_pin) { + /* Embedded display connectors such as LVDS may not have DDC. */ + if (!link->ddc->ddc_pin && + !dc_is_embedded_signal(link->connector_signal)) { DC_ERROR("Failed to get I2C info for connector!\n"); goto ddc_create_fail; } @@ -895,7 +897,7 @@ static bool construct_dpia(struct dc_link *link, } /* Set dpia port index : 0 to number of dpia ports */ - link->ddc_hw_inst = init_params->connector_index; + link->ddc_hw_inst = (uint8_t)init_params->connector_index; // Assign Dpia preferred eng_id if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index eb791285ed06..ec083e8b75b4 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -302,9 +302,11 @@ static bool dp_validate_mode_timing( req_bw = dc_bandwidth_in_kbps_from_timing(timing, dc_link_get_highest_encoding_format(link)); max_bw = dp_link_bandwidth_kbps(link, link_setting); + uint32_t max_uncompressed_pixel_rate_100hz = + link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.max_uncompressed_pixel_rate_cap * 10000U; bool is_max_uncompressed_pixel_rate_exceeded = link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.valid && - timing->pix_clk_100hz > link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.max_uncompressed_pixel_rate_cap * 10000; + timing->pix_clk_100hz > max_uncompressed_pixel_rate_100hz; if (is_max_uncompressed_pixel_rate_exceeded && !timing->flags.DSC) { return false; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c index a66217e54a09..a0ea853f5f64 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c @@ -96,7 +96,7 @@ static void i2c_payloads_add( for (pos = 0; pos < len; pos += payload_size) { struct i2c_payload payload = { .write = write, - .address = address, + .address = (uint8_t)address, .length = DDC_MIN(payload_size, len - pos), .data = data + pos }; dal_vector_append(&payloads->payloads, &payload); @@ -384,8 +384,7 @@ bool link_query_ddc_data( i2c_payloads_add( &payloads, address, read_size, read_buf, false); - command.number_of_payloads = - i2c_payloads_get_count(&payloads); + command.number_of_payloads = (uint8_t)i2c_payloads_get_count(&payloads); success = dm_helpers_submit_i2c( ddc->ctx, @@ -402,12 +401,7 @@ int link_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *payload, enum aux_return_code_type *operation_result) { - if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc || - !ddc->ddc_pin) { - return dce_aux_transfer_dmub_raw(ddc, payload, operation_result); - } else { - return dce_aux_transfer_raw(ddc, payload, operation_result); - } + return dce_aux_transfer_raw(ddc, payload, operation_result); } uint32_t link_get_fixed_vs_pe_retimer_write_address(struct dc_link *link) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 782a45caa13d..817b4010edcb 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -1353,7 +1353,7 @@ bool dp_overwrite_extended_receiver_cap(struct dc_link *link) union down_stream_port_count down_strm_port_count; union edp_configuration_cap edp_config_cap; - int i; + unsigned int i; for (i = 0; i < read_dpcd_retry_cnt; i++) { status = core_link_read_dpcd( @@ -1713,7 +1713,7 @@ enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link) CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); // Identify closest LTTPR to determine if workarounds required for known embedded LTTPR - closest_lttpr_offset = dp_get_closest_lttpr_offset(lttpr_count); + closest_lttpr_offset = dp_get_closest_lttpr_offset((uint8_t)lttpr_count); core_link_read_dpcd(link, (DP_LTTPR_IEEE_OUI + closest_lttpr_offset), link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui)); @@ -1752,7 +1752,7 @@ static bool retrieve_link_cap(struct dc_link *link) union dp_downstream_port_present ds_port = { 0 }; enum dc_status status = DC_ERROR_UNEXPECTED; uint32_t read_dpcd_retry_cnt = 20; - int i; + unsigned int i; struct dp_sink_hw_fw_revision dp_hw_fw_revision; const uint32_t post_oui_delay = 30; // 30ms bool is_fec_supported = false; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c index 766b54631c79..da227889e007 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c @@ -119,7 +119,7 @@ bool dpia_query_hpd_status(struct dc_link *link) /* prepare QUERY_HPD command */ cmd.query_hpd.header.type = DMUB_CMD__QUERY_HPD_STATE; cmd.query_hpd.header.payload_bytes = sizeof(cmd.query_hpd.data); - cmd.query_hpd.data.instance = link->link_id.enum_id - ENUM_ID_1; + cmd.query_hpd.data.instance = (uint8_t)(link->link_id.enum_id - ENUM_ID_1); cmd.query_hpd.data.ch_type = AUX_CHANNEL_DPIA; /* Query dpia hpd status from dmub */ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c index c958d3f600c8..dd854d992692 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c @@ -112,7 +112,7 @@ static int get_estimated_bw(struct dc_link *link) return bw_estimated_bw * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity); } -static int get_non_reduced_max_link_rate(struct dc_link *link) +static uint8_t get_non_reduced_max_link_rate(struct dc_link *link) { uint8_t nrd_max_link_rate = 0; @@ -125,7 +125,7 @@ static int get_non_reduced_max_link_rate(struct dc_link *link) return nrd_max_link_rate; } -static int get_non_reduced_max_lane_count(struct dc_link *link) +static uint8_t get_non_reduced_max_lane_count(struct dc_link *link) { uint8_t nrd_max_lane_count = 0; @@ -180,7 +180,7 @@ static void dpia_bw_alloc_unplug(struct dc_link *link) static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw) { - uint8_t request_reg_val; + uint32_t request_reg_val; uint32_t temp, request_bw; if (link->dpia_bw_alloc_config.bw_granularity == 0) { @@ -197,7 +197,7 @@ static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw) request_bw = request_reg_val * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity); - if (request_bw > link->dpia_bw_alloc_config.estimated_bw) { + if (request_bw > (uint32_t)link->dpia_bw_alloc_config.estimated_bw) { DC_LOG_ERROR("%s: Link[%d]: Request BW (%d --> %d) > Estimated BW (%d)... Set to Estimated BW!", __func__, link->link_index, req_bw, request_bw, link->dpia_bw_alloc_config.estimated_bw); @@ -212,8 +212,8 @@ static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw) link->dpia_bw_alloc_config.allocated_bw = request_bw; DC_LOG_DC("%s: Link[%d]: Request BW: %d", __func__, link->link_index, request_bw); - core_link_write_dpcd(link, REQUESTED_BW, - &request_reg_val, + uint8_t requested_bw_dpcd = (uint8_t)request_reg_val; + core_link_write_dpcd(link, REQUESTED_BW, &requested_bw_dpcd, sizeof(uint8_t)); } diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c index 1860d44f63c1..54ce768ae6ad 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c @@ -65,7 +65,7 @@ bool dp_parse_link_loss_status( /*1. Check that Link Status changed, before re-training.*/ /*parse lane status*/ - for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { + for (lane = 0; lane < (uint32_t)link->cur_link_settings.lane_count; lane++) { /* check status of lanes 0,1 * changed DpcdAddress_Lane01Status (0x202) */ @@ -223,7 +223,7 @@ static void handle_hpd_irq_vesa_replay_sink(struct dc_link *link) } } -static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enable) +static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enable, bool *replay_esd_detection_needed) { union dpcd_replay_configuration replay_configuration = {0}; union dpcd_replay_configuration replay_sink_status = {0}; @@ -311,6 +311,16 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enabl *need_re_enable = true; } } + + if (link->ctx->dc->debug.enable_replay_esd_recovery) { + if (!link->replay_settings.replay_allow_active && + replay_sink_status.bits.SINK_DEVICE_REPLAY_STATUS == 0x7) { + /* If sink device replay status is 0x7 and replay is disabled, + * it means sink is in a bad state and link retraining is needed to recover + */ + *replay_esd_detection_needed = true; + } + } } void dp_handle_link_loss(struct dc_link *link) @@ -469,6 +479,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, enum dc_status result; bool status = false; bool replay_re_enable_needed = false; + bool replay_esd_detection_needed = false; if (out_link_loss) *out_link_loss = false; @@ -482,6 +493,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n", __func__, link->link_index); + handle_hpd_irq_replay_sink(link, &replay_re_enable_needed, &replay_esd_detection_needed); /* All the "handle_hpd_irq_xxx()" methods * should be called only after @@ -528,8 +540,6 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, /* PSR-related error was detected and handled */ return true; - handle_hpd_irq_replay_sink(link, &replay_re_enable_needed); - /* If PSR-related error handled, Main link may be off, * so do not handle as a normal sink status change interrupt. */ @@ -552,27 +562,30 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, * Downstream port status changed, * then DM should call DC to do the detection. * NOTE: Now includes eDP link loss detection and retraining + * Link will be retrained if panel is not EDP or + * Replay ESD recovery is needed. */ + if (link->connector_signal != SIGNAL_TYPE_EDP || replay_esd_detection_needed) { + if (dp_parse_link_loss_status( + link, + &hpd_irq_dpcd_data)) { + /* Connectivity log: link loss */ + CONN_DATA_LINK_LOSS(link, + hpd_irq_dpcd_data.raw, + sizeof(hpd_irq_dpcd_data), + "Status: "); - if (dp_parse_link_loss_status( - link, - &hpd_irq_dpcd_data)) { - /* Connectivity log: link loss */ - CONN_DATA_LINK_LOSS(link, - hpd_irq_dpcd_data.raw, - sizeof(hpd_irq_dpcd_data), - "Status: "); + if (defer_handling && has_left_work) + *has_left_work = true; + else + dp_handle_link_loss(link); - if (defer_handling && has_left_work) - *has_left_work = true; - else - dp_handle_link_loss(link); + status = false; + if (out_link_loss) + *out_link_loss = true; - status = false; - if (out_link_loss) - *out_link_loss = true; - - dp_trace_link_loss_increment(link); + dp_trace_link_loss_increment(link); + } } if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling) { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c index 96afce4ffbfa..d87f87a02d63 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c @@ -60,11 +60,10 @@ static void dp_pr_set_static_screen_param(struct dc_link *link) if (dc->current_state->res_ctx.pipe_ctx[i].stream && dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; - unsigned int vsync_rate_hz = div64_u64(div64_u64( - (stream->timing.pix_clk_100hz * (u64)100), - stream->timing.v_total), - stream->timing.h_total); - + unsigned int vsync_rate_hz = (unsigned int)div64_u64(div64_u64( + (stream->timing.pix_clk_100hz * (u64)100), + stream->timing.v_total), + stream->timing.h_total); params.triggers.cursor_update = true; params.triggers.overlay_update = true; params.triggers.surface_update = true; @@ -264,7 +263,7 @@ bool dp_pr_enable(struct dc_link *link, bool enable) cmd.pr_enable.header.type = DMUB_CMD__PR; cmd.pr_enable.header.sub_type = DMUB_CMD__PR_ENABLE; cmd.pr_enable.header.payload_bytes = sizeof(struct dmub_cmd_pr_enable_data); - cmd.pr_enable.data.panel_inst = panel_inst; + cmd.pr_enable.data.panel_inst = (uint8_t)panel_inst; cmd.pr_enable.data.enable = enable ? 1 : 0; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); @@ -301,17 +300,17 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con cmd.pr_copy_settings.header.type = DMUB_CMD__PR; cmd.pr_copy_settings.header.sub_type = DMUB_CMD__PR_COPY_SETTINGS; cmd.pr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_pr_copy_settings_data); - cmd.pr_copy_settings.data.panel_inst = panel_inst; + cmd.pr_copy_settings.data.panel_inst = (uint8_t)panel_inst; // HW inst cmd.pr_copy_settings.data.aux_inst = replay_context->aux_inst; cmd.pr_copy_settings.data.digbe_inst = replay_context->digbe_inst; cmd.pr_copy_settings.data.digfe_inst = replay_context->digfe_inst; if (pipe_ctx->plane_res.dpp) - cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst; + cmd.pr_copy_settings.data.dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst; else cmd.pr_copy_settings.data.dpp_inst = 0; if (pipe_ctx->stream_res.tg) - cmd.pr_copy_settings.data.otg_inst = pipe_ctx->stream_res.tg->inst; + cmd.pr_copy_settings.data.otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; else cmd.pr_copy_settings.data.otg_inst = 0; @@ -322,6 +321,19 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con cmd.pr_copy_settings.data.flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); cmd.pr_copy_settings.data.debug.u32All = link->replay_settings.config.debug_flags; + // ALPM settings + cmd.pr_copy_settings.data.flags.bitfields.alpm_mode = (enum dmub_alpm_mode)link->replay_settings.config.alpm_mode; + if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { + cmd.pr_copy_settings.data.auxless_alpm_data.lfps_setup_ns = (uint16_t)dc->debug.auxless_alpm_lfps_setup_ns; + cmd.pr_copy_settings.data.auxless_alpm_data.lfps_period_ns = (uint16_t)dc->debug.auxless_alpm_lfps_period_ns; + cmd.pr_copy_settings.data.auxless_alpm_data.lfps_silence_ns = (uint16_t)dc->debug.auxless_alpm_lfps_silence_ns; + cmd.pr_copy_settings.data.auxless_alpm_data.lfps_t1_t2_override_us = + (uint16_t)dc->debug.auxless_alpm_lfps_t1t2_us; + cmd.pr_copy_settings.data.auxless_alpm_data.lfps_t1_t2_offset_us = + (uint16_t)dc->debug.auxless_alpm_lfps_t1t2_offset_us; + cmd.pr_copy_settings.data.auxless_alpm_data.lttpr_count = link->dc->link_srv->dp_get_lttpr_count(link); + } + cmd.pr_copy_settings.data.su_granularity_needed = link->dpcd_caps.vesa_replay_caps.bits.PR_SU_GRANULARITY_NEEDED; cmd.pr_copy_settings.data.su_x_granularity = link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity; cmd.pr_copy_settings.data.su_y_granularity = link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity; @@ -329,9 +341,9 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps; if (pipe_ctx->stream->timing.dsc_cfg.num_slices_v > 0) - cmd.pr_copy_settings.data.dsc_slice_height = (pipe_ctx->stream->timing.v_addressable + + cmd.pr_copy_settings.data.dsc_slice_height = (uint16_t)((pipe_ctx->stream->timing.v_addressable + pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) / - pipe_ctx->stream->timing.dsc_cfg.num_slices_v; + pipe_ctx->stream->timing.dsc_cfg.num_slices_v); if (dc_is_embedded_signal(link->connector_signal)) cmd.pr_copy_settings.data.main_link_activity_option = OPTION_1C; @@ -358,7 +370,7 @@ bool dp_pr_update_state(struct dc_link *link, struct dmub_cmd_pr_update_state_da cmd.pr_update_state.header.type = DMUB_CMD__PR; cmd.pr_update_state.header.sub_type = DMUB_CMD__PR_UPDATE_STATE; cmd.pr_update_state.header.payload_bytes = sizeof(struct dmub_cmd_pr_update_state_data); - cmd.pr_update_state.data.panel_inst = panel_inst; + cmd.pr_update_state.data.panel_inst = (uint8_t)panel_inst; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); return true; @@ -379,7 +391,7 @@ bool dp_pr_set_general_cmd(struct dc_link *link, struct dmub_cmd_pr_general_cmd_ cmd.pr_general_cmd.header.type = DMUB_CMD__PR; cmd.pr_general_cmd.header.sub_type = DMUB_CMD__PR_GENERAL_CMD; cmd.pr_general_cmd.header.payload_bytes = sizeof(struct dmub_cmd_pr_general_cmd_data); - cmd.pr_general_cmd.data.panel_inst = panel_inst; + cmd.pr_general_cmd.data.panel_inst = (uint8_t)panel_inst; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); return true; @@ -397,7 +409,7 @@ bool dp_pr_get_state(const struct dc_link *link, uint64_t *state) do { // Send gpint command and wait for ack - if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, panel_inst, + if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, (uint16_t)panel_inst, &replay_state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) { // Return invalid state when GPINT times out replay_state = PR_STATE_INVALID; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index ddff0db4ce70..605bf19dc4f2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -310,7 +310,7 @@ static void maximize_lane_settings(const struct link_training_settings *lt_setti max_requested.FFE_PRESET = lane_settings[0].FFE_PRESET; /* Determine what the maximum of the requested settings are*/ - for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { + for (lane = 1; lane < (uint32_t)lt_settings->link_settings.lane_count; lane++) { if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING) max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING; @@ -568,7 +568,7 @@ enum link_training_result dp_check_link_loss_status( sizeof(dpcd_buf)); /*parse lane status*/ - for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { + for (lane = 0; lane < (uint32_t)link->cur_link_settings.lane_count; lane++) { /* * check lanes status */ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c index 66d0fb1b9b9d..4331e032416f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c @@ -132,7 +132,7 @@ void decide_8b_10b_training_settings( */ lt_settings->link_settings.link_spread = link->dp_ss_off ? LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ; - lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting); + lt_settings->eq_pattern_time = (uint16_t)get_eq_training_aux_rd_interval(link, link_setting); lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting); lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting); lt_settings->enhanced_framing = 1; @@ -140,7 +140,7 @@ void decide_8b_10b_training_settings( lt_settings->disallow_per_lane_settings = true; lt_settings->always_match_dpcd_with_hw_lane_settings = true; lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link); - lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting, lt_settings->lttpr_mode); + lt_settings->cr_pattern_time = (uint16_t)get_cr_training_aux_rd_interval(link, link_setting, lt_settings->lttpr_mode); dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); /* Some embedded LTTPRs rely on receiving TPS2 before LT to interop reliably with sensitive VGA dongles @@ -195,7 +195,7 @@ static void set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence(str * 6. Begin link training as usual * */ - uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset(lttpr_count); + uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset((uint8_t)lttpr_count); union dpcd_training_pattern dpcd_pattern = {0}; @@ -379,7 +379,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence( dpcd_set_lane_settings(link, lt_settings, offset); /* 3. wait for receiver to lock-on*/ - wait_time_microsec = dp_get_eq_aux_rd_interval(link, lt_settings, offset, retries_ch_eq); + wait_time_microsec = dp_get_eq_aux_rd_interval(link, lt_settings, offset, (uint8_t)retries_ch_eq); dp_wait_for_training_aux_rd_interval( link, @@ -408,7 +408,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence( /* 6. check CHEQ done*/ if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && dp_is_symbol_locked(lane_count, dpcd_lane_status) && - dp_check_interlane_aligned(dpcd_lane_status_updated, link, retries_ch_eq)) + dp_check_interlane_aligned(dpcd_lane_status_updated, link, (uint8_t)retries_ch_eq)) return LINK_TRAINING_SUCCESS; /* 7. update VS/PE/PC2 in lt_settings*/ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 4a2699a374b7..e06a9ac65286 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -47,9 +47,9 @@ #define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B /* Travis */ -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; +static const char DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; /* Nutmeg */ -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; +static const char DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode) { @@ -462,7 +462,7 @@ bool edp_receiver_ready_T9(struct dc_link *link) do { sinkstatus = 1; result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus)); - if (sinkstatus == 0) + if (!(sinkstatus & DP_RECEIVE_PORT_0_STATUS)) break; if (result != DC_OK) break; @@ -492,7 +492,7 @@ bool edp_receiver_ready_T7(struct dc_link *link) do { sinkstatus = 0; result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus)); - if (sinkstatus == 1) + if (sinkstatus & DP_RECEIVE_PORT_0_STATUS) break; if (result != DC_OK) break; @@ -601,12 +601,12 @@ bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active, link->psr_settings.psr_power_opt = *power_opts; if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt) - psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst); + psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, (uint8_t)panel_inst); } if (psr != NULL && link->psr_settings.psr_feature_enabled && force_static && psr->funcs->psr_force_static) - psr->funcs->psr_force_static(psr, panel_inst); + psr->funcs->psr_force_static(psr, (uint8_t)panel_inst); /* Enable or Disable PSR */ if (allow_active && link->psr_settings.psr_allow_active != *allow_active) { @@ -615,9 +615,9 @@ bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active, if (!link->psr_settings.psr_allow_active) dc_z10_restore(dc); - if (psr != NULL && link->psr_settings.psr_feature_enabled) { - psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst); - } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && + if (psr != NULL && link->psr_settings.psr_feature_enabled) + psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, (uint8_t)panel_inst); + else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled) dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait); else @@ -637,7 +637,7 @@ bool edp_get_psr_state(const struct dc_link *link, enum dc_psr_state *state) return false; if (psr != NULL && link->psr_settings.psr_feature_enabled) - psr->funcs->psr_get_state(psr, state, panel_inst); + psr->funcs->psr_get_state(psr, state, (uint8_t)panel_inst); else if (dmcu != NULL && link->psr_settings.psr_feature_enabled) dmcu->funcs->get_psr_state(dmcu, state); @@ -811,7 +811,7 @@ bool edp_setup_psr(struct dc_link *link, psr_context->smuPhyId = transmitter_to_phy_id(link); psr_context->crtcTimingVerticalTotal = stream->timing.v_total; - psr_context->vsync_rate_hz = div64_u64(div64_u64((stream-> + psr_context->vsync_rate_hz = (unsigned int)div64_u64(div64_u64((stream-> timing.pix_clk_100hz * (u64)100), stream->timing.v_total), stream->timing.h_total); @@ -885,7 +885,7 @@ bool edp_setup_psr(struct dc_link *link, if (psr) { link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, - link, psr_context, panel_inst); + link, psr_context, (uint8_t)panel_inst); link->psr_settings.psr_power_opt = 0; link->psr_settings.psr_allow_active = 0; } else { @@ -913,7 +913,7 @@ void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency, enum // PSR residency measurements only supported on DMCUB if (psr != NULL && link->psr_settings.psr_feature_enabled) - psr->funcs->psr_get_residency(psr, residency, panel_inst, mode); + psr->funcs->psr_get_residency(psr, residency, (uint8_t)panel_inst, mode); else *residency = 0; } @@ -947,7 +947,7 @@ bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active, if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts) { if (replay != NULL && link->replay_settings.replay_feature_enabled && replay->funcs->replay_set_power_opt) { - replay->funcs->replay_set_power_opt(replay, *power_opts, panel_inst); + replay->funcs->replay_set_power_opt(replay, *power_opts, (uint8_t)panel_inst); link->replay_settings.replay_power_opt_active = *power_opts; } } @@ -957,7 +957,7 @@ bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active, // TODO: Handle mux change case if force_static is set // If force_static is set, just change the replay_allow_active state directly if (replay != NULL && link->replay_settings.replay_feature_enabled) - replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst); + replay->funcs->replay_enable(replay, *allow_active, wait, (uint8_t)panel_inst); link->replay_settings.replay_allow_active = *allow_active; } @@ -975,7 +975,7 @@ bool edp_get_replay_state(const struct dc_link *link, uint64_t *state) return false; if (replay != NULL && link->replay_settings.replay_feature_enabled) - replay->funcs->replay_get_state(replay, &pr_state, panel_inst); + replay->funcs->replay_get_state(replay, &pr_state, (uint8_t)panel_inst); *state = pr_state; return true; @@ -1046,12 +1046,11 @@ bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_stat replay_context.os_request_force_ffu = link->replay_settings.config.os_request_force_ffu; link->replay_settings.replay_feature_enabled = - replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst); + replay->funcs->replay_copy_settings(replay, link, &replay_context, (uint8_t)panel_inst); if (link->replay_settings.replay_feature_enabled) { replay_config.bits.FREESYNC_PANEL_REPLAY_MODE = 1; - replay_config.bits.TIMING_DESYNC_ERROR_VERIFICATION = - link->replay_settings.config.replay_timing_sync_supported; + replay_config.bits.TIMING_DESYNC_ERROR_VERIFICATION = 0; replay_config.bits.STATE_TRANSITION_ERROR_DETECTION = 1; dm_helpers_dp_write_dpcd(link->ctx, link, DP_SINK_PR_ENABLE_AND_CONFIGURATION, @@ -1096,7 +1095,7 @@ bool edp_send_replay_cmd(struct dc_link *link, return false; if (dp_pr_get_panel_inst(dc, link, &panel_inst)) - cmd_data->panel_inst = panel_inst; + cmd_data->panel_inst = (uint8_t)panel_inst; else { DC_LOG_DC("%s(): get edp panel inst fail ", __func__); return false; @@ -1121,7 +1120,7 @@ bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal, uin if (coasting_vtotal && (link->replay_settings.coasting_vtotal != coasting_vtotal || link->replay_settings.frame_skip_number != frame_skip_number)) { - replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst, frame_skip_number); + replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, (uint8_t)panel_inst, frame_skip_number); link->replay_settings.coasting_vtotal = coasting_vtotal; link->replay_settings.frame_skip_number = frame_skip_number; } @@ -1143,7 +1142,7 @@ bool edp_replay_residency(const struct dc_link *link, return false; if (replay != NULL && link->replay_settings.replay_feature_enabled) - replay->funcs->replay_residency(replay, panel_inst, residency, is_start, mode); + replay->funcs->replay_residency(replay, (uint8_t)panel_inst, residency, is_start, mode); else *residency = 0; @@ -1168,7 +1167,7 @@ bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link, if (link->replay_settings.replay_feature_enabled && replay->funcs->replay_set_power_opt_and_coasting_vtotal) { replay->funcs->replay_set_power_opt_and_coasting_vtotal(replay, - *power_opts, panel_inst, coasting_vtotal, frame_skip_number); + *power_opts, (uint8_t)panel_inst, coasting_vtotal, frame_skip_number); link->replay_settings.replay_power_opt_active = *power_opts; link->replay_settings.coasting_vtotal = coasting_vtotal; link->replay_settings.frame_skip_number = frame_skip_number; @@ -1211,9 +1210,9 @@ int edp_get_backlight_level(const struct dc_link *link) fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight) - return panel_cntl->funcs->get_current_backlight(panel_cntl); + return (int)panel_cntl->funcs->get_current_backlight(panel_cntl); else if (abm != NULL && abm->funcs->get_current_backlight != NULL) - return (int) abm->funcs->get_current_backlight(abm); + return (int)abm->funcs->get_current_backlight(abm); else return DC_ERROR_UNEXPECTED; } @@ -1252,10 +1251,10 @@ static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link, memset(&cmd, 0, sizeof(cmd)); - link_enc_index = link->link_enc->transmitter - TRANSMITTER_UNIPHY_A; + link_enc_index = (uint8_t)(link->link_enc->transmitter - TRANSMITTER_UNIPHY_A); if (link_res->hpo_dp_link_enc) { - link_enc_index = link_res->hpo_dp_link_enc->inst; + link_enc_index = (uint8_t)link_res->hpo_dp_link_enc->inst; use_hpo_dp_link_enc = true; } diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c index 2a422e223bf2..2e0f07ec04e4 100644 --- a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c @@ -40,8 +40,8 @@ #define FN(reg_name, field_name) \ mcif_wb20->mcif_wb_shift->field_name, mcif_wb20->mcif_wb_mask->field_name -#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8 -#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40 +#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8)) +#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40)) /* wbif programming guide: * 1. set up wbif parameter: diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c index c3b089ba511a..6b6f80a3bfd5 100644 --- a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c @@ -40,8 +40,8 @@ #define FN(reg_name, field_name) \ mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name -#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8 -#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40 +#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8)) +#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40)) /* wbif programming guide: * 1. set up wbif parameter: diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c index 27e653234850..0f2294bedcc3 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c @@ -375,7 +375,7 @@ void mpc1_mpc_init(struct mpc *mpc) void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - int opp_id; + uint32_t opp_id; REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); @@ -422,7 +422,7 @@ void mpc1_init_mpcc_list_from_hw( if (out_mux == mpcc_id) tree->opp_list = mpcc; - if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) { + if (bot_sel != 0xf && bot_sel < (unsigned int)mpc10->num_mpcc) { bot_mpcc_id = bot_sel; REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel); diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c index 4e91e9f6f11a..d7a07e29d23a 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c @@ -1067,7 +1067,7 @@ static void program_gamut_remap( struct dcn30_mpc *mpc30, int mpcc_id, const uint16_t *regval, - int select) + uint32_t select) { uint16_t selection = 0; struct color_matrices_reg gam_regs; @@ -1129,7 +1129,7 @@ void mpc3_set_gamut_remap( { struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); int i = 0; - int gamut_mode; + uint32_t gamut_mode; if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) program_gamut_remap(mpc30, mpcc_id, NULL, GAMUT_REMAP_BYPASS); @@ -1201,7 +1201,7 @@ void mpc3_get_gamut_remap(struct mpc *mpc, { struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); uint16_t arr_reg_val[12] = {0}; - int select; + uint32_t select; read_gamut_remap(mpc30, mpcc_id, arr_reg_val, &select); diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c index e0617db2d0c1..ce1ee2062e41 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c @@ -73,15 +73,56 @@ void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_locati } } -void mpc401_populate_lut(struct mpc *mpc, - const enum MCM_LUT_ID id, - const union mcm_lut_params *params, - const bool lut_bank_a, - const int mpcc_id) +static enum dc_lut_mode get3dlut_config( + struct mpc *mpc, + bool *is_17x17x17, + bool *is_12bits_color_channel, + int mpcc_id) +{ + uint32_t i_mode, i_enable_10bits, lut_size; + enum dc_lut_mode mode; + struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], + MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode); + + REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits); + + switch (i_mode) { + case 0: + mode = LUT_BYPASS; + break; + case 1: + mode = LUT_RAM_A; + break; + case 2: + mode = LUT_RAM_B; + break; + default: + mode = LUT_BYPASS; + break; + } + if (i_enable_10bits > 0) + *is_12bits_color_channel = false; + else + *is_12bits_color_channel = true; + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size); + + if (lut_size == 0) + *is_17x17x17 = true; + else + *is_17x17x17 = false; + + return mode; +} + +void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id) { const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; - const struct pwl_params *lut1d = params->pwl; - const struct pwl_params *lut_shaper = params->pwl; + const struct pwl_params *lut1d = params.pwl; + const struct pwl_params *lut_shaper = params.pwl; bool is_17x17x17; bool is_12bits_color_channel; const struct dc_rgb *lut0; @@ -90,7 +131,7 @@ void mpc401_populate_lut(struct mpc *mpc, const struct dc_rgb *lut3; int lut_size0; int lut_size; - const struct tetrahedral_params *lut3d = params->lut3d; + const struct tetrahedral_params *lut3d = params.lut3d; switch (id) { case MCM_LUT_1DLUT: @@ -133,6 +174,8 @@ void mpc401_populate_lut(struct mpc *mpc, mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); + get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id); + is_17x17x17 = !lut3d->use_tetrahedral_9; is_12bits_color_channel = lut3d->use_12bits; if (is_17x17x17) { @@ -155,6 +198,8 @@ void mpc401_populate_lut(struct mpc *mpc, sizeof(lut3d->tetrahedral_9.lut1[0]); } + mpc32_select_3dlut_ram(mpc, next_mode, + is_12bits_color_channel, mpcc_id); mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id); if (is_12bits_color_channel) mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id); @@ -187,69 +232,46 @@ void mpc401_populate_lut(struct mpc *mpc, } -static uint32_t mpc401_cm_lut_size_to_3dlut_size(const enum dc_cm_lut_size cm_size) -{ - uint32_t size = 0; - - switch (cm_size) { - case CM_LUT_SIZE_999: - size = 1; - break; - case CM_LUT_SIZE_171717: - size = 0; - break; - default: - /* invalid LUT size */ - ASSERT(false); - size = 0; - break; - } - - return size; -} - void mpc401_program_lut_mode( struct mpc *mpc, const enum MCM_LUT_ID id, - const bool enable, - const bool lut_bank_a, - const enum dc_cm_lut_size size, - const int mpcc_id) + const enum MCM_LUT_XABLE xable, + bool lut_bank_a, + int mpcc_id) { - uint32_t lut_size; struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); switch (id) { case MCM_LUT_3DLUT: - if (enable) { - lut_size = mpc401_cm_lut_size_to_3dlut_size(size); - REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id], - MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2, - MPCC_MCM_3DLUT_SIZE, lut_size); - } else { - if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) - mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); + switch (xable) { + case MCM_LUT_DISABLE: REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, 0); + break; + case MCM_LUT_ENABLE: + REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2); + break; } break; case MCM_LUT_SHAPER: - if (enable) { - REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); - } else { - if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) - mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); + switch (xable) { + case MCM_LUT_DISABLE: REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, 0); + break; + case MCM_LUT_ENABLE: + REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); + break; } break; case MCM_LUT_1DLUT: - if (enable) { - REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], - MPCC_MCM_1DLUT_MODE, 2); - } else { - if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) - mpc32_power_on_blnd_lut(mpc, mpcc_id, false); + switch (xable) { + case MCM_LUT_DISABLE: REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_MODE, 0); + break; + case MCM_LUT_ENABLE: + REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], + MPCC_MCM_1DLUT_MODE, 2); + break; } REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_SELECT, lut_bank_a ? 0 : 1); @@ -257,20 +279,14 @@ void mpc401_program_lut_mode( } } -void mpc401_program_lut_read_write_control(struct mpc *mpc, - const enum MCM_LUT_ID id, - const bool lut_bank_a, - const unsigned int bit_depth, - const int mpcc_id) +void mpc401_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id) { struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); switch (id) { case MCM_LUT_3DLUT: mpc32_select_3dlut_ram_mask(mpc, 0xf, mpcc_id); - REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], - MPCC_MCM_3DLUT_30BIT_EN, (bit_depth == 10) ? 1 : 0, - MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); break; case MCM_LUT_SHAPER: mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id); @@ -562,44 +578,6 @@ void mpc401_get_gamut_remap(struct mpc *mpc, arr_reg_val, ARRAY_SIZE(arr_reg_val)); } -void mpc401_get_lut_mode(struct mpc *mpc, - const enum MCM_LUT_ID id, - const int mpcc_id, - bool *enable, - bool *lut_bank_a) -{ - struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); - - uint32_t lut_mode = 0; - uint32_t lut_select = 0; - - *enable = false; - *lut_bank_a = true; - - switch (id) { - case MCM_LUT_SHAPER: - REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], - MPCC_MCM_SHAPER_MODE_CURRENT, &lut_mode); - *enable = lut_mode != 0; - *lut_bank_a = lut_mode != 2; - break; - case MCM_LUT_1DLUT: - REG_GET_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id], - MPCC_MCM_1DLUT_MODE_CURRENT, &lut_mode, - MPCC_MCM_1DLUT_SELECT_CURRENT, &lut_select); - *enable = lut_mode != 0; - *lut_bank_a = lut_mode == 0 || lut_select == 0; - break; - case MCM_LUT_3DLUT: - default: - REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], - MPCC_MCM_3DLUT_MODE_CURRENT, &lut_mode); - *enable = lut_mode != 0; - *lut_bank_a = lut_mode != 2; - break; - } -} - static const struct mpc_funcs dcn401_mpc_funcs = { .read_mpcc_state = mpc1_read_mpcc_state, .insert_plane = mpc1_insert_plane, @@ -638,7 +616,6 @@ static const struct mpc_funcs dcn401_mpc_funcs = { .populate_lut = mpc401_populate_lut, .program_lut_read_write_control = mpc401_program_lut_read_write_control, .program_lut_mode = mpc401_program_lut_mode, - .get_lut_mode = mpc401_get_lut_mode, }; diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h index c16560c84453..6d842d7b95c7 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h @@ -206,32 +206,21 @@ void dcn401_mpc_construct(struct dcn401_mpc *mpc401, int num_rmu); void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); -void mpc401_populate_lut(struct mpc *mpc, - const enum MCM_LUT_ID id, - const union mcm_lut_params *params, - bool lut_bank_a, - int mpcc_id); +void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id); void mpc401_program_lut_mode( struct mpc *mpc, const enum MCM_LUT_ID id, - const bool enable, - const bool lut_bank_a, - const enum dc_cm_lut_size size, - const int mpcc_id); - -void mpc401_get_lut_mode(struct mpc *mpc, - const enum MCM_LUT_ID id, - const int mpcc_id, - bool *enable, - bool *lut_bank_a); + const enum MCM_LUT_XABLE xable, + bool lut_bank_a, + int mpcc_id); void mpc401_program_lut_read_write_control( struct mpc *mpc, const enum MCM_LUT_ID id, - const bool lut_bank_a, - const unsigned int bit_depth, - const int mpcc_id); + bool lut_bank_a, + int mpcc_id); void mpc401_set_gamut_remap( struct mpc *mpc, diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c index 507dbdbea600..38c0e8f96d40 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c @@ -63,6 +63,154 @@ void mpc42_update_blending( mpcc->blnd_cfg = *blnd_cfg; } +/* Shaper functions */ +void mpc42_power_on_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on) +{ + uint32_t power_status_shaper = 2; + uint32_t power_status_3dlut = 2; + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + int max_retries = 10; + + REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, + MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0); + REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, + MPCC_MCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1:0); + /* wait for memory to fully power up */ + if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { + REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); + REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); + } + + /*read status is not mandatory, it is just for debugging*/ + REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper); + REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut); + + if (power_status_shaper != 0 && power_on == true) + BREAK_TO_DEBUGGER(); + + if (power_status_3dlut != 0 && power_on == true) + BREAK_TO_DEBUGGER(); +} + +void mpc42_configure_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE(MPCC_MCM_SHAPER_SCALE_G_B[mpcc_id], + MPCC_MCM_SHAPER_SCALE_B, 0x7000); + REG_UPDATE(MPCC_MCM_SHAPER_SCALE_G_B[mpcc_id], + MPCC_MCM_SHAPER_SCALE_G, 0x7000); + REG_UPDATE(MPCC_MCM_SHAPER_SCALE_R[mpcc_id], + MPCC_MCM_SHAPER_SCALE_R, 0x7000); + REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7); + REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); + REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0); +} + + +void mpc42_program_3dlut_size(struct mpc *mpc, uint32_t width, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + uint32_t size = 0xff; + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &size); + + REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, + (width == 33) ? 2 : + (width == 17) ? 0 : 2); + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &size); +} + +void mpc42_program_3dlut_fl_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_R[mpcc_id], + MPCC_MCM_3DLUT_OUT_OFFSET_R, bias, + MPCC_MCM_3DLUT_OUT_SCALE_R, scale); + + REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_G[mpcc_id], + MPCC_MCM_3DLUT_OUT_OFFSET_G, bias, + MPCC_MCM_3DLUT_OUT_SCALE_G, scale); + + REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_B[mpcc_id], + MPCC_MCM_3DLUT_OUT_OFFSET_B, bias, + MPCC_MCM_3DLUT_OUT_SCALE_B, scale); +} + +void mpc42_program_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK, 0xF); + + //program bit_depth + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPCC_MCM_3DLUT_30BIT_EN, + (bit_depth == 10) ? 1 : 0); +} + +bool mpc42_is_config_supported(uint32_t width) +{ + if (width == 17) + return true; + + return false; +} + +void mpc42_populate_lut(struct mpc *mpc, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id) +{ + const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; + const struct pwl_params *lut_shaper = params.pwl; + + if (lut_shaper == NULL) + return; + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc42_power_on_shaper_3dlut(mpc, mpcc_id, true); + + mpc42_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id); + + if (next_mode == LUT_RAM_A) + mpc32_program_shaper_luta_settings(mpc, lut_shaper, mpcc_id); + else + mpc32_program_shaper_lutb_settings(mpc, lut_shaper, mpcc_id); + + mpc32_program_shaper_lut( + mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id); + + mpc42_power_on_shaper_3dlut(mpc, mpcc_id, false); +} + +void mpc42_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, + bool lut_bank_a, bool enabled, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + switch (id) { + case MCM_LUT_3DLUT: + REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, + (!enabled) ? 0 : + (lut_bank_a) ? 1 : 2); + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); + break; + case MCM_LUT_SHAPER: + mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id); + break; + default: + break; + } +} + /* RMCM Shaper functions */ void mpc42_power_on_rmcm_shaper_3dlut( struct mpc *mpc, @@ -526,47 +674,32 @@ void mpc42_program_rmcm_lut_read_write_control(struct mpc *mpc, const enum MCM_L } } -void mpc42_program_lut_mode(struct mpc *mpc, - bool enable, - bool lut_bank_a, - int mpcc_id) +void mpc42_program_lut_mode(struct mpc *mpc, const enum MCM_LUT_XABLE xable, + bool lut_bank_a, int mpcc_id) { struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - if (enable) { - REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); - } else { + switch (xable) { + case MCM_LUT_DISABLE: REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, 0); + break; + case MCM_LUT_ENABLE: + REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); + break; } } -static uint32_t mpc42_get_rmcm_3dlut_width( - const enum dc_cm_lut_size size) -{ - uint32_t width = 0; - - switch (size) { - case CM_LUT_SIZE_333333: - width = 2; - break; - case CM_LUT_SIZE_171717: - default: - width = 0; - break; - } - - return width; -} - -void mpc42_program_rmcm_3dlut_size(struct mpc *mpc, - const enum dc_cm_lut_size size, - int mpcc_id) +void mpc42_program_rmcm_3dlut_size(struct mpc *mpc, uint32_t width, int mpcc_id) { struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - uint32_t width = mpc42_get_rmcm_3dlut_width(size); + uint32_t size = 0xff; - REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], - MPC_RMCM_3DLUT_SIZE, width); + REG_GET(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, &size); + + REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, + (width == 33) ? 2 : 0); + + REG_GET(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, &size); } void mpc42_program_rmcm_3dlut_fast_load_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id) @@ -598,6 +731,14 @@ void mpc42_program_rmcm_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_ (bit_depth == 10) ? 1 : 0); } +bool mpc42_is_rmcm_config_supported(uint32_t width) +{ + if (width == 17 || width == 33) + return true; + + return false; +} + void mpc42_set_fl_config( struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, @@ -605,7 +746,6 @@ void mpc42_set_fl_config( { struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - uint32_t width = mpc42_get_rmcm_3dlut_width(cfg->size); /* From: Jie Zhou @@ -646,7 +786,7 @@ void mpc42_set_fl_config( //width REG_UPDATE_2(MPC_RMCM_3DLUT_MODE[mpcc_id], - MPC_RMCM_3DLUT_SIZE, width, + MPC_RMCM_3DLUT_SIZE, (cfg->width == 33) ? 2 : 0, MPC_RMCM_3DLUT_MODE, (!cfg->enabled) ? 0 : (cfg->select_lut_bank_a) ? 1 : 2); //connect to hubp @@ -659,6 +799,182 @@ void mpc42_set_fl_config( REG_UPDATE(MPC_RMCM_CNTL[mpcc_id], MPC_RMCM_CNTL, cfg->enabled ? 0 : 0xF); } +//static void rmcm_program_gamut_remap( +// struct mpc *mpc, +// unsigned int mpcc_id, +// const uint16_t *regval, +// enum mpcc_gamut_remap_id gamut_remap_block_id, +// enum mpcc_gamut_remap_mode_select mode_select) +//{ +// struct color_matrices_reg gamut_regs; +// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); +// +// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_FIRST_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_SECOND_GAMUT_REMAP) { +// mpc_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +// return; +// } +// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP) { +// +// if (regval == NULL || mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) { +// REG_SET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], 0, +// MPC_RMCM_GAMUT_REMAP_MODE, mode_select); +// return; +// } +// +// gamut_regs.shifts.csc_c11 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.masks.csc_c11 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.shifts.csc_c12 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C12_A; +// gamut_regs.masks.csc_c12 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C12_A; +// +// switch (mode_select) { +// case MPCC_GAMUT_REMAP_MODE_SELECT_1: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_A[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_A[mpcc_id]); +// break; +// case MPCC_GAMUT_REMAP_MODE_SELECT_2: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_B[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_B[mpcc_id]); +// break; +// default: +// break; +// } +// +// cm_helper_program_color_matrices( +// mpc->ctx, +// regval, +// &gamut_regs); +// +// //select coefficient set to use, set A (MODE_1) or set B (MODE_2) +// REG_SET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], 0, MPC_RMCM_GAMUT_REMAP_MODE, mode_select); +// } +//} + +//static bool is_mpc_legacy_gamut_id(enum mpcc_gamut_remap_id gamut_remap_block_id) +//{ +// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_FIRST_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_SECOND_GAMUT_REMAP) { +// return true; +// } +// return false; +//} +//static void program_gamut_remap( +// struct mpc *mpc, +// unsigned int mpcc_id, +// const uint16_t *regval, +// enum mpcc_gamut_remap_id gamut_remap_block_id, +// enum mpcc_gamut_remap_mode_select mode_select) +//{ +// if (is_mpc_legacy_gamut_id(gamut_remap_block_id)) +// mpc_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +// else +// rmcm_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +//} + +//void mpc42_set_gamut_remap( +// struct mpc *mpc, +// int mpcc_id, +// const struct mpc_grph_gamut_adjustment *adjust) +//{ +// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); +// unsigned int i = 0; +// uint32_t mode_select = 0; +// +// if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) { +// /* Bypass / Disable if type is bypass or hw */ +// program_gamut_remap(mpc, mpcc_id, NULL, +// adjust->mpcc_gamut_remap_block_id, MPCC_GAMUT_REMAP_MODE_SELECT_0); +// } else { +// struct fixed31_32 arr_matrix[12]; +// uint16_t arr_reg_val[12]; +// +// for (i = 0; i < 12; i++) +// arr_matrix[i] = adjust->temperature_matrix[i]; +// +// convert_float_matrix(arr_reg_val, arr_matrix, 12); +// +// if (is_mpc_legacy_gamut_id(adjust->mpcc_gamut_remap_block_id)) +// REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], +// MPCC_GAMUT_REMAP_MODE_CURRENT, &mode_select); +// else +// REG_GET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], +// MPC_RMCM_GAMUT_REMAP_MODE_CURRENT, &mode_select); +// +// //If current set in use not set A (MODE_1), then use set A, otherwise use set B +// if (mode_select != MPCC_GAMUT_REMAP_MODE_SELECT_1) +// mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_1; +// else +// mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_2; +// +// program_gamut_remap(mpc, mpcc_id, arr_reg_val, +// adjust->mpcc_gamut_remap_block_id, mode_select); +// } +//} + +//static void read_gamut_remap(struct mpc *mpc, +// int mpcc_id, +// uint16_t *regval, +// enum mpcc_gamut_remap_id gamut_remap_block_id, +// uint32_t *mode_select) +//{ +// struct color_matrices_reg gamut_regs = {0}; +// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); +// +// if (is_mpc_legacy_gamut_id(gamut_remap_block_id)) { +// mpc_read_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +// } +// if (gamut_remap_block_id == MPCC_RMCM_GAMUT_REMAP) { +// //current coefficient set in use +// REG_GET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], MPC_RMCM_GAMUT_REMAP_MODE, mode_select); +// +// gamut_regs.shifts.csc_c11 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.masks.csc_c11 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.shifts.csc_c12 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C12_A; +// gamut_regs.masks.csc_c12 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C12_A; +// +// switch (*mode_select) { +// case MPCC_GAMUT_REMAP_MODE_SELECT_1: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_A[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_A[mpcc_id]); +// break; +// case MPCC_GAMUT_REMAP_MODE_SELECT_2: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_B[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_B[mpcc_id]); +// break; +// default: +// break; +// } +// } +// +// if (*mode_select != MPCC_GAMUT_REMAP_MODE_SELECT_0) { +// cm_helper_read_color_matrices( +// mpc42->base.ctx, +// regval, +// &gamut_regs); +// } +//} + +//void mpc42_get_gamut_remap(struct mpc *mpc, +// int mpcc_id, +// struct mpc_grph_gamut_adjustment *adjust) +//{ +// uint16_t arr_reg_val[12] = {0}; +// uint32_t mode_select; +// +// read_gamut_remap(mpc, mpcc_id, arr_reg_val, adjust->mpcc_gamut_remap_block_id, &mode_select); +// +// if (mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) { +// adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; +// return; +// } +// +// adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; +// convert_hw_matrix(adjust->temperature_matrix, +// arr_reg_val, ARRAY_SIZE(arr_reg_val)); +//} + void mpc42_read_mpcc_state( struct mpc *mpc, int mpcc_inst, @@ -755,7 +1071,14 @@ static const struct mpc_funcs dcn42_mpc_funcs = { .populate_lut = mpc401_populate_lut, .program_lut_read_write_control = mpc401_program_lut_read_write_control, .program_lut_mode = mpc401_program_lut_mode, - .get_lut_mode = mpc401_get_lut_mode, + .mcm = { + .program_lut_read_write_control = mpc42_program_lut_read_write_control, + .program_3dlut_size = mpc42_program_3dlut_size, + .program_bias_scale = mpc42_program_3dlut_fl_bias_scale, + .program_bit_depth = mpc42_program_bit_depth, + .is_config_supported = mpc42_is_config_supported, + .populate_lut = mpc42_populate_lut, + }, .rmcm = { .enable_3dlut_fl = mpc42_enable_3dlut_fl, .update_3dlut_fast_load_select = mpc42_update_3dlut_fast_load_select, @@ -764,6 +1087,7 @@ static const struct mpc_funcs dcn42_mpc_funcs = { .program_3dlut_size = mpc42_program_rmcm_3dlut_size, .program_bias_scale = mpc42_program_rmcm_3dlut_fast_load_bias_scale, .program_bit_depth = mpc42_program_rmcm_bit_depth, + .is_config_supported = mpc42_is_rmcm_config_supported, .power_on_shaper_3dlut = mpc42_power_on_rmcm_shaper_3dlut, .populate_lut = mpc42_populate_rmcm_lut, .fl_3dlut_configure = mpc42_set_fl_config, diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h index a5f7f4f2bb3b..12a12c28e553 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h @@ -884,6 +884,49 @@ void dcn42_mpc_construct(struct dcn42_mpc *mpc401, void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst); +void mpc42_program_shaper_lutb_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id); +void mpc42_program_shaper_luta_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id); +void mpc42_configure_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id); +void mpc42_power_on_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on); +void mpc42_program_3dlut_size( + struct mpc *mpc, + uint32_t width, + int mpcc_id); +void mpc42_program_3dlut_fl_bias_scale( + struct mpc *mpc, + uint16_t bias, + uint16_t scale, + int mpcc_id); +void mpc42_program_bit_depth( + struct mpc *mpc, + uint16_t bit_depth, + int mpcc_id); +void mpc42_populate_lut( + struct mpc *mpc, + const union mcm_lut_params params, + bool lut_bank_a, + int mpcc_id); +void mpc42_program_lut_read_write_control( + struct mpc *mpc, + const enum MCM_LUT_ID id, + bool lut_bank_a, + bool enabled, + int mpcc_id); + +bool mpc42_is_config_supported(uint32_t width); + /* RMCM */ void mpc42_program_rmcm_shaper_lut( struct mpc *mpc, @@ -927,12 +970,12 @@ void mpc42_program_rmcm_lut_read_write_control( int mpcc_id); void mpc42_program_lut_mode( struct mpc *mpc, - bool enable, + const enum MCM_LUT_XABLE xable, bool lut_bank_a, int mpcc_id); void mpc42_program_rmcm_3dlut_size( struct mpc *mpc, - const enum dc_cm_lut_size size, + uint32_t width, int mpcc_id); void mpc42_program_rmcm_3dlut_fast_load_bias_scale( struct mpc *mpc, @@ -944,6 +987,8 @@ void mpc42_program_rmcm_bit_depth( uint16_t bit_depth, int mpcc_id); +bool mpc42_is_rmcm_config_supported(uint32_t width); + void mpc42_set_fl_config( struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c index ce826a5be4c7..83730bbe26a8 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c @@ -293,7 +293,7 @@ void opp2_set_disp_pattern_generator( void opp2_program_dpg_dimensions( struct output_pixel_processor *opp, - int width, int height) + uint32_t width, uint32_t height) { struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h index fb0c047c1788..8944fa6c8f79 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h @@ -156,7 +156,7 @@ void opp2_set_disp_pattern_generator( void opp2_program_dpg_dimensions( struct output_pixel_processor *opp, - int width, int height); + uint32_t width, uint32_t height); bool opp2_dpg_is_blanked(struct output_pixel_processor *opp); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c index 9e66b9b97c63..e6426ccee2d8 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c @@ -375,7 +375,7 @@ void optc1_set_vtg_params(struct timing_generator *optc, if (REG(OTG_INTERLACE_CONTROL)) { if (patched_crtc_timing.flags.INTERLACE == 1) { v_init = v_init / 2; - if ((optc1->vstartup_start/2)*2 > asic_blank_end) + if ((uint32_t)((optc1->vstartup_start/2)*2) > asic_blank_end) v_fp2 = v_fp2 / 2; } } diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c index 39ce4d4a61a1..c558b1d633f3 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c @@ -305,8 +305,8 @@ static void optc2_align_vblanks( L = div_u64(L, master_h_total); L = div_u64(L, slave_pixel_clock_100Hz); XY = div_u64(L, p); - Y = master_v_active - XY - 1; - X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider); + Y = (uint32_t)(master_v_active - XY - 1); + X = (uint32_t)div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider); /* * set master OTG to unlock when V/H diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 60e546b69a05..07895d5f4dfa 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -101,7 +101,7 @@ static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, i void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments) { struct optc *optc1 = DCN10TG_FROM_TG(tg); - int segments; + uint32_t segments; REG_GET(OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, &segments); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c index a880e4a6d165..62f45c156c32 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c @@ -621,7 +621,6 @@ void dcn35_timing_generator_init(struct optc *optc1) optc1->min_v_blank_interlace = 5; optc1->min_h_sync_width = 4; optc1->min_v_sync_width = 1; - optc1->max_frame_count = 0xFFFFFF; dcn35_timing_generator_set_fgcg( optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c index ed66a2bbb8ae..a3431ec2f058 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c @@ -283,9 +283,7 @@ void dcn42_timing_generator_init(struct optc *optc1) optc1->min_v_blank_interlace = 5; optc1->min_h_sync_width = 4; optc1->min_v_sync_width = 1; - optc1->max_frame_count = 0xFFFFFF; dcn35_timing_generator_set_fgcg( optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc); } - diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h index fc7192f01b33..8e7d65317e7c 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h @@ -164,7 +164,6 @@ SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ - SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\ SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c index f5bf5940e748..1d0181534a67 100644 --- a/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c @@ -380,7 +380,7 @@ void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on) uint32_t power_gate = power_on ? 0 : 1; uint32_t pwr_status = power_on ? 0 : 2; uint32_t org_ip_request_cntl; - int i; + unsigned int i; bool block_enabled; bool all_mpcc_disabled = true, all_opp_disabled = true; bool all_optc_disabled = true, all_stream_disabled = true; @@ -460,7 +460,7 @@ static bool pg_cntl35_mem_status(struct pg_cntl *pg_cntl) void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl) { - int i = 0; + unsigned int i = 0; bool block_enabled; pg_cntl->pg_res_enable[PG_HPO] = pg_cntl35_hpo_pg_status(pg_cntl); @@ -494,7 +494,7 @@ void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl) static void pg_cntl35_print_pg_status(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log) { - int i = 0; + unsigned int i = 0; bool block_enabled = false; DC_LOG_DEBUG("%s: %s", debug_func, debug_log); diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c index 96290538a889..729c2b653161 100644 --- a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c @@ -27,9 +27,6 @@ static bool pg_cntl42_dsc_pg_status(struct pg_cntl *pg_cntl, unsigned int dsc_in struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); uint32_t pwr_status = 0; - if (pg_cntl->ctx->dc->debug.ignore_pg) - return true; - switch (dsc_inst) { case 0: /* DSC0 */ REG_GET(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); @@ -64,9 +61,11 @@ void pg_cntl42_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc( pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->debug.disable_dsc_power_gate || - pg_cntl->ctx->dc->idle_optimizations_allowed) + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_dsc_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed; + + if (skip_pg && !power_on) return; block_enabled = pg_cntl42_dsc_pg_status(pg_cntl, dsc_inst); @@ -261,11 +260,12 @@ void pg_cntl42_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on) uint32_t power_forceon; bool block_enabled; - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->debug.disable_hpo_power_gate || - pg_cntl->ctx->dc->idle_optimizations_allowed) - return; + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_hpo_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed; + if (skip_pg && !power_on) + return; block_enabled = pg_cntl42_hpo_pg_status(pg_cntl); if (power_on) { if (block_enabled) @@ -316,9 +316,11 @@ void pg_cntl42_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on) uint32_t power_forceon; bool block_enabled; - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->idle_optimizations_allowed || - pg_cntl->ctx->dc->debug.disable_io_clk_power_gate) + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->idle_optimizations_allowed || + pg_cntl->ctx->dc->debug.disable_io_clk_power_gate; + + if (skip_pg && !power_on) return; block_enabled = pg_cntl42_io_clk_status(pg_cntl); @@ -412,9 +414,11 @@ void pg_cntl42_mem_pg_control(struct pg_cntl *pg_cntl, bool power_on) uint32_t power_forceon; bool block_enabled; - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->idle_optimizations_allowed || - pg_cntl->ctx->dc->debug.disable_mem_power_gate) + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->idle_optimizations_allowed || + pg_cntl->ctx->dc->debug.disable_mem_power_gate; + + if (skip_pg && !power_on) return; block_enabled = pg_cntl42_mem_status(pg_cntl); @@ -464,9 +468,10 @@ void pg_cntl42_dio_pg_control(struct pg_cntl *pg_cntl, bool power_on) uint32_t org_ip_request_cntl; bool block_enabled; - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->idle_optimizations_allowed || - pg_cntl->ctx->dc->debug.disable_dio_power_gate) + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->idle_optimizations_allowed || + pg_cntl->ctx->dc->debug.disable_dio_power_gate; + if (skip_pg && !power_on) return; block_enabled = pg_cntl42_dio_pg_status(pg_cntl); @@ -503,7 +508,7 @@ void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on) uint32_t power_gate = power_on ? 0 : 1; uint32_t pwr_status = power_on ? 0 : 2; uint32_t org_ip_request_cntl; - int i; + unsigned int i; bool block_enabled; bool all_mpcc_disabled = true, all_opp_disabled = true; bool all_optc_disabled = true, all_stream_disabled = true; @@ -564,7 +569,7 @@ void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on) void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl) { - int i = 0; + unsigned int i = 0; bool block_enabled; pg_cntl->pg_res_enable[PG_HPO] = pg_cntl42_hpo_pg_status(pg_cntl); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index caafebe92129..b92d4f378d60 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -804,7 +804,7 @@ static void dce100_resource_destruct(struct dce110_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -869,7 +869,7 @@ enum dc_status dce100_validate_bandwidth( enum dc_validate_mode validate_mode) { (void)validate_mode; - int i; + unsigned int i; bool at_least_one_pipe = false; struct dc_stream_state *stream = NULL; const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000); @@ -978,7 +978,7 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( const struct resource_pool *pool, struct dc_stream_state *stream) { - int i; + unsigned int i; int j = -1; struct dc_link *link = stream->link; enum engine_id preferred_engine = link->link_enc->preferred_engine; @@ -995,7 +995,7 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( /* Store first available for MST second display * in daisy chain use case */ - j = i; + j = (int)i; if (pool->stream_enc[i]->id == preferred_engine) return pool->stream_enc[i]; } @@ -1175,7 +1175,7 @@ static bool dce100_resource_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce100_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c index f83acfe7a15e..19252b25bce0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c @@ -839,7 +839,7 @@ static void dce110_resource_destruct(struct dce110_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1150,7 +1150,7 @@ static struct pipe_ctx *dce110_acquire_underlay( /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; - pipe_ctx->pipe_idx = underlay_idx; + pipe_ctx->pipe_idx = (uint8_t)underlay_idx; pipe_ctx->stream = stream; @@ -1160,7 +1160,7 @@ static struct pipe_ctx *dce110_acquire_underlay( hws->funcs.enable_display_power_gating( dc, - pipe_ctx->stream_res.tg->inst, + (uint8_t)pipe_ctx->stream_res.tg->inst, dcb, PIPE_GATING_CONTROL_DISABLE); /* @@ -1213,7 +1213,7 @@ struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link( const struct resource_pool *pool, struct dc_stream_state *stream) { - int i; + unsigned int i; int j = -1; struct dc_link *link = stream->link; @@ -1223,7 +1223,7 @@ struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link( /* Store first available for MST second display * in daisy chain use case */ - j = i; + j = (int)i; if (pool->stream_enc[i]->id == link->link_enc->preferred_engine) return pool->stream_enc[i]; @@ -1492,7 +1492,7 @@ static bool dce110_resource_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce110_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c index 458b14e4cb97..1deba53363e5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c @@ -804,7 +804,7 @@ static void dce112_resource_destruct(struct dce110_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1382,7 +1382,7 @@ static bool dce112_resource_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce112_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c index 56bbf9dc1691..38d3b87529b0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c @@ -626,7 +626,7 @@ static void dce120_resource_destruct(struct dce110_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -927,7 +927,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc) struct dm_pp_clock_levels_with_latency eng_clks = {0}; struct dm_pp_clock_levels_with_latency mem_clks = {0}; struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; - int i; + unsigned int i; unsigned int clk; unsigned int latency; /*original logic in dal3*/ @@ -1227,7 +1227,7 @@ static bool dce120_resource_construct( j++; } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce120_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index 6a25dcfcdf17..d2d56a1c4b8b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -753,7 +753,8 @@ static struct link_encoder *dce60_link_encoder_create( enc_init_data, &link_enc_feature, &link_enc_regs[link_regs_id], - &link_enc_aux_regs[enc_init_data->channel - 1], + enc_init_data->channel == CHANNEL_ID_UNKNOWN ? + NULL : &link_enc_aux_regs[enc_init_data->channel - 1], enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index 33be49b3c1b1..26820d35478a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -760,7 +760,8 @@ static struct link_encoder *dce80_link_encoder_create( enc_init_data, &link_enc_feature, &link_enc_regs[link_regs_id], - &link_enc_aux_regs[enc_init_data->channel - 1], + enc_init_data->channel == CHANNEL_ID_UNKNOWN ? + NULL : &link_enc_aux_regs[enc_init_data->channel - 1], enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; @@ -853,7 +854,7 @@ static void dce80_resource_destruct(struct dce110_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1057,7 +1058,7 @@ static bool dce80_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce80_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1257,7 +1258,7 @@ static bool dce81_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce80_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1455,7 +1456,7 @@ static bool dce83_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce80_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 0fdebe63d355..db1b6a1b92e8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -976,7 +976,7 @@ static void dcn10_resource_destruct(struct dcn10_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); kfree(pool->base.hw_i2cs[i]); @@ -1139,7 +1139,7 @@ static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer( idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; - idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; + idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst; return idle_pipe; } @@ -1181,7 +1181,8 @@ static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_st { if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && caps->max_video_width != 0 - && plane_state->src_rect.width > caps->max_video_width) + && plane_state->src_rect.width > 0 + && (unsigned int)plane_state->src_rect.width > caps->max_video_width) return DC_FAIL_SURFACE_VALIDATE; return DC_OK; @@ -1266,7 +1267,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( const struct resource_pool *pool, struct dc_stream_state *stream) { - int i; + unsigned int i; int j = -1; struct dc_link *link = stream->link; @@ -1278,7 +1279,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( */ if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL) - j = i; + j = (int)i; if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id == link->link_enc->preferred_engine) @@ -1340,7 +1341,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx) static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) { - int i; + unsigned int i; if (clks->num_levels == 0) return false; @@ -1358,7 +1359,7 @@ static bool dcn10_resource_construct( struct dc *dc, struct dcn10_resource_pool *pool) { - int i; + unsigned int i; int j; struct dc_context *ctx = dc->ctx; uint32_t pipe_fuses = read_pipe_fuses(ctx); @@ -1653,7 +1654,7 @@ static bool dcn10_resource_construct( j++; } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1735,7 +1736,7 @@ struct resource_pool *dcn10_create_resource_pool( if (!pool) return NULL; - if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn10_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; kfree(pool); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index a99829f23965..95abc4c38eae 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -1120,7 +1120,7 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1156,7 +1156,7 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1169,19 +1169,19 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1415,7 +1415,7 @@ enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_stream_state *dc_stream) { enum dc_status result = DC_OK; - int i; + unsigned int i; /* Get a DSC if required and available */ for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -1523,13 +1523,13 @@ bool dcn20_split_stream_for_odm( *next_odm_pipe = *prev_odm_pipe; - next_odm_pipe->pipe_idx = pipe_idx; + next_odm_pipe->pipe_idx = (uint8_t)pipe_idx; next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; - next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; + next_odm_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[next_odm_pipe->pipe_idx]->inst; next_odm_pipe->stream_res.dsc = NULL; if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; @@ -1580,13 +1580,13 @@ void dcn20_split_stream_for_mpc( *secondary_pipe = *primary_pipe; secondary_pipe->bottom_pipe = sec_bot_pipe; - secondary_pipe->pipe_idx = pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)pipe_idx; secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; - secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; + secondary_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[secondary_pipe->pipe_idx]->inst; secondary_pipe->stream_res.dsc = NULL; if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { ASSERT(!secondary_pipe->bottom_pipe); @@ -1636,7 +1636,8 @@ void dcn20_set_mcif_arb_params( { enum mmhubbub_wbif_mode wbif_mode; struct mcif_arb_params *wb_arb_params; - int i, j, dwb_pipe; + int j, dwb_pipe; + unsigned int i; /* Writeback MCIF_WB arbitration parameters */ dwb_pipe = 0; @@ -1680,7 +1681,7 @@ void dcn20_set_mcif_arb_params( bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) { - int i; + unsigned int i; /* Validate DSC config, dsc count validation is already done */ for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -1736,7 +1737,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; } } if (secondary_pipe == NULL && @@ -1744,7 +1745,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; } } @@ -1762,7 +1763,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; break; } } @@ -1783,7 +1784,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; break; } } @@ -1797,7 +1798,7 @@ void dcn20_merge_pipes_for_validate( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; /* merge previously split odm pipes since mode support needs to make the decision */ for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -1864,7 +1865,8 @@ int dcn20_validate_apply_pipe_split_flags( int *split, bool *merge) { - int i, pipe_idx, vlevel_split; + unsigned int i; + int pipe_idx, vlevel_split; int plane_count = 0; bool force_split = false; bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID; @@ -1897,7 +1899,7 @@ int dcn20_validate_apply_pipe_split_flags( (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) ++plane_count; } - if (plane_count > dc->res_pool->pipe_count / 2) + if ((unsigned int)plane_count > dc->res_pool->pipe_count / 2) avoid_split = true; /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */ @@ -1923,12 +1925,12 @@ int dcn20_validate_apply_pipe_split_flags( if (!context->res_ctx.pipe_ctx[i].stream) continue; - for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) + for (vlevel_split = vlevel; (unsigned int)vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && v->ModeSupport[vlevel][0]) break; /* Impossible to not split this pipe */ - if (vlevel > context->bw_ctx.dml.soc.num_states) + if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) vlevel = vlevel_split; else max_mpc_comb = 0; @@ -2064,7 +2066,8 @@ bool dcn20_fast_validate_bw( bool out = false; int split[MAX_PIPES] = { 0 }; bool merge[MAX_PIPES] = { false }; - int pipe_cnt, i, pipe_idx, vlevel; + int pipe_cnt, pipe_idx, vlevel; + unsigned int i; ASSERT(pipes); if (!pipes) @@ -2083,7 +2086,7 @@ bool dcn20_fast_validate_bw( vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); - if (vlevel > context->bw_ctx.dml.soc.num_states) + if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) goto validate_fail; vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); @@ -2216,7 +2219,7 @@ struct pipe_ctx *dcn20_acquire_free_pipe_for_layer( sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx]; sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx]; sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx]; - sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst; + sec_dpp_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[sec_dpp_pipe->pipe_idx]->inst; return sec_dpp_pipe; } @@ -2289,7 +2292,7 @@ static const struct resource_funcs dcn20_res_pool_funcs = { bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -2311,7 +2314,7 @@ bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; ASSERT(pipe_count > 0); @@ -2569,7 +2572,7 @@ static bool dcn20_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; (unsigned int)i < pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2617,12 +2620,12 @@ static bool dcn20_resource_construct( if (!dc->debug.disable_pplib_wm_range) { struct pp_smu_wm_range_sets ranges = {0}; - int i = 0; + int j = 0; ranges.num_reader_wm_sets = 0; if (loaded_bb->num_states == 1) { - ranges.reader_wm_sets[0].wm_inst = i; + ranges.reader_wm_sets[0].wm_inst = (uint8_t)j; ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; @@ -2630,15 +2633,14 @@ static bool dcn20_resource_construct( ranges.num_reader_wm_sets = 1; } else if (loaded_bb->num_states > 1) { - for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { - ranges.reader_wm_sets[i].wm_inst = i; - ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; - ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; + for (j = 0; j < 4 && (unsigned int)j < loaded_bb->num_states; j++) { + ranges.reader_wm_sets[j].wm_inst = (uint8_t)j; + ranges.reader_wm_sets[j].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; + ranges.reader_wm_sets[j].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; DC_FP_START(); - dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb); + dcn20_fpu_set_wm_ranges(j, &ranges, loaded_bb); DC_FP_END(); - - ranges.num_reader_wm_sets = i + 1; + ranges.num_reader_wm_sets = j + 1; } ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; @@ -2664,7 +2666,7 @@ static bool dcn20_resource_construct( goto create_fail; /* mem input -> ipp -> dpp -> opp -> TG */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; (unsigned int)i < pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn20_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2792,7 +2794,7 @@ static bool dcn20_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; (unsigned int)i < dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 2; @@ -2829,7 +2831,7 @@ struct resource_pool *dcn20_create_resource_pool( if (!pool) return NULL; - if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn20_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 84f6d9dc443f..b653f951e104 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -684,7 +684,7 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -719,7 +719,7 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) dal_irq_service_destroy(&pool->base.irqs); } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -732,19 +732,19 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -804,7 +804,8 @@ bool dcn21_fast_validate_bw(struct dc *dc, bool out = false; int split[MAX_PIPES] = { 0 }; bool merge[MAX_PIPES] = { false }; - int pipe_cnt, i, pipe_idx, vlevel; + int pipe_cnt, pipe_idx, vlevel; + unsigned int i; ASSERT(pipes); if (!pipes) @@ -829,7 +830,7 @@ bool dcn21_fast_validate_bw(struct dc *dc, dm_allow_self_refresh_and_mclk_switch; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); - if (vlevel > context->bw_ctx.dml.soc.num_states) { + if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) { if (allow_self_refresh_only) { /* @@ -842,7 +843,7 @@ bool dcn21_fast_validate_bw(struct dc *dc, context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = dm_allow_self_refresh; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); - if (vlevel > context->bw_ctx.dml.soc.num_states) + if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) goto validate_fail; } else { goto validate_fail; @@ -1427,7 +1428,8 @@ static bool dcn21_resource_construct( struct dc *dc, struct dcn21_resource_pool *pool) { - int i, j; + unsigned int i; + int j; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; uint32_t pipe_fuses = read_pipe_fuses(ctx); @@ -1659,7 +1661,7 @@ static bool dcn21_resource_construct( j++; } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1703,11 +1705,11 @@ static bool dcn21_resource_construct( goto create_fail; } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn21_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { BREAK_TO_DEBUGGER(); - dm_error("DC: failed to create display stream compressor %d!\n", i); + dm_error("DC: failed to create display stream compressor %u!\n", i); goto create_fail; } } @@ -1757,7 +1759,7 @@ struct resource_pool *dcn21_create_resource_pool( if (!pool) return NULL; - if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn21_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 4a864689c44f..4a7f2c5d34e6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -1111,7 +1111,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1147,7 +1147,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1160,19 +1160,19 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1195,7 +1195,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1250,7 +1250,7 @@ static struct hubp *dcn30_hubp_create( static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1274,7 +1274,7 @@ static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1355,7 +1355,8 @@ int dcn30_populate_dml_pipes_from_context( display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + int pipe_cnt; + unsigned int i; struct resource_context *res_ctx = &context->res_ctx; DC_FP_START(); @@ -1413,7 +1414,8 @@ void dcn30_set_mcif_arb_params( enum mmhubbub_wbif_mode wbif_mode; struct display_mode_lib *dml = &context->bw_ctx.dml; struct mcif_arb_params *wb_arb_params; - int i, j, dwb_pipe; + int j, dwb_pipe; + unsigned int i; /* Writeback MCIF_WB arbitration parameters */ dwb_pipe = 0; @@ -1563,13 +1565,13 @@ static bool dcn30_split_stream_for_mpc_or_odm( *sec_pipe = *pri_pipe; - sec_pipe->pipe_idx = pipe_idx; + sec_pipe->pipe_idx = (uint8_t)pipe_idx; sec_pipe->plane_res.mi = pool->mis[pipe_idx]; sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; - sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; + sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; sec_pipe->stream_res.dsc = NULL; if (odm) { if (pri_pipe->next_odm_pipe) { @@ -1623,7 +1625,7 @@ static struct pipe_ctx *dcn30_find_split_pipe( if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[old_index]; - pipe->pipe_idx = old_index; + pipe->pipe_idx = (uint8_t)old_index; } if (!pipe) @@ -1632,7 +1634,7 @@ static struct pipe_ctx *dcn30_find_split_pipe( && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { if (context->res_ctx.pipe_ctx[i].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[i]; - pipe->pipe_idx = i; + pipe->pipe_idx = (uint8_t)i; break; } } @@ -1647,7 +1649,7 @@ static struct pipe_ctx *dcn30_find_split_pipe( for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { if (context->res_ctx.pipe_ctx[i].stream == NULL) { pipe = &context->res_ctx.pipe_ctx[i]; - pipe->pipe_idx = i; + pipe->pipe_idx = (uint8_t)i; break; } } @@ -1669,7 +1671,8 @@ noinline bool dcn30_internal_validate_bw( int split[MAX_PIPES] = { 0 }; bool merge[MAX_PIPES] = { false }; bool newly_split[MAX_PIPES] = { false }; - int pipe_cnt, i, pipe_idx, vlevel = 0; + unsigned int i; + int pipe_cnt, pipe_idx, vlevel = 0; struct vba_vars_st *vba = &context->bw_ctx.dml.vba; ASSERT(pipes); @@ -1701,7 +1704,7 @@ noinline bool dcn30_internal_validate_bw( dm_allow_self_refresh_and_mclk_switch; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); /* This may adjust vlevel and maxMpcComb */ - if (vlevel < context->bw_ctx.dml.soc.num_states) + if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states) vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); } if (allow_self_refresh_only && @@ -1719,7 +1722,7 @@ noinline bool dcn30_internal_validate_bw( dm_allow_self_refresh; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); - if (vlevel < context->bw_ctx.dml.soc.num_states) { + if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states) { memset(split, 0, sizeof(split)); memset(merge, 0, sizeof(merge)); vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); @@ -2159,13 +2162,13 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params if (bw_params->clk_table.entries[0].memclk_mhz) { for (i = 0; i < MAX_NUM_DPM_LVL; i++) { - if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) + if (bw_params->clk_table.entries[i].dcfclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; - if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz) + if (bw_params->clk_table.entries[i].dispclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dispclk_mhz) dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; - if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz) + if (bw_params->clk_table.entries[i].dppclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dppclk_mhz) dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; - if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz) + if (bw_params->clk_table.entries[i].phyclk_mhz > (unsigned int)dcn30_bb_max_clk.max_phyclk_mhz) dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; } @@ -2173,14 +2176,14 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params dcn30_fpu_update_max_clk(&dcn30_bb_max_clk); DC_FP_END(); - if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + if ((unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz; num_dcfclk_sta_targets++; - } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + } else if ((unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates for (i = 0; i < num_dcfclk_sta_targets; i++) { - if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) { + if (dcfclk_sta_targets[i] > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) { dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz; break; } @@ -2232,7 +2235,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; } else { - if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { + if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) { dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; } else { @@ -2247,7 +2250,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params } while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && - optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { + optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) { dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; } @@ -2307,7 +2310,7 @@ static bool dcn30_resource_construct( struct dc *dc, struct dcn30_resource_pool *pool) { - int i; + unsigned int i; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; struct ddc_service_init_data ddc_init_data = {0}; @@ -2379,7 +2382,7 @@ static bool dcn30_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2529,7 +2532,7 @@ static bool dcn30_resource_construct( } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { pool->base.opps[i] = dcn30_opp_create(ctx, i); if (pool->base.opps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2539,7 +2542,7 @@ static bool dcn30_resource_construct( } } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { pool->base.timing_generators[i] = dcn30_timing_generator_create( ctx, i); if (pool->base.timing_generators[i] == NULL) { @@ -2559,13 +2562,13 @@ static bool dcn30_resource_construct( } /* ABM */ - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { pool->base.multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); if (pool->base.multiple_abms[i] == NULL) { - dm_error("DC: failed to create abm for pipe %d!\n", i); + dm_error("DC: failed to create abm for pipe %u!\n", i); BREAK_TO_DEBUGGER(); goto create_fail; } @@ -2578,11 +2581,11 @@ static bool dcn30_resource_construct( goto create_fail; } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn30_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { BREAK_TO_DEBUGGER(); - dm_error("DC: failed to create display stream compressor %d!\n", i); + dm_error("DC: failed to create display stream compressor %u!\n", i); goto create_fail; } } @@ -2601,7 +2604,7 @@ static bool dcn30_resource_construct( } /* AUX and I2C */ - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dcn30_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2669,7 +2672,7 @@ struct resource_pool *dcn30_create_resource_pool( if (!pool) return NULL; - if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn30_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index a74b150cbe9c..0ecd3a2fcebd 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1082,7 +1082,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1118,7 +1118,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1131,19 +1131,19 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1166,7 +1166,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1182,7 +1182,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1210,7 +1210,7 @@ static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst) static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1234,7 +1234,7 @@ static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *poo static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1358,7 +1358,7 @@ static void set_wm_ranges( struct _vcs_dpi_soc_bounding_box_st *loaded_bb) { struct pp_smu_wm_range_sets ranges = {0}; - int i; + unsigned int i; ranges.num_reader_wm_sets = 0; @@ -1372,7 +1372,7 @@ static void set_wm_ranges( ranges.num_reader_wm_sets = 1; } else if (loaded_bb->num_states > 1) { for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { - ranges.reader_wm_sets[i].wm_inst = i; + ranges.reader_wm_sets[i].wm_inst = (uint8_t)i; ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; DC_FP_START(); @@ -1444,7 +1444,8 @@ static bool dcn301_resource_construct( struct dc *dc, struct dcn301_resource_pool *pool) { - int i, j; + int j; + unsigned int i; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; uint32_t pipe_fuses = read_pipe_fuses(ctx); @@ -1506,7 +1507,7 @@ static bool dcn301_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -1676,13 +1677,13 @@ static bool dcn301_resource_construct( /* ABM (or ABMs for NV2x) */ /* TODO: */ - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { pool->base.multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); if (pool->base.multiple_abms[i] == NULL) { - dm_error("DC: failed to create abm for pipe %d!\n", i); + dm_error("DC: failed to create abm for pipe %u!\n", i); BREAK_TO_DEBUGGER(); goto create_fail; } @@ -1696,11 +1697,11 @@ static bool dcn301_resource_construct( goto create_fail; } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn301_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { BREAK_TO_DEBUGGER(); - dm_error("DC: failed to create display stream compressor %d!\n", i); + dm_error("DC: failed to create display stream compressor %u!\n", i); goto create_fail; } } @@ -1719,7 +1720,7 @@ static bool dcn301_resource_construct( } /* AUX and I2C */ - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dcn301_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1773,7 +1774,7 @@ struct resource_pool *dcn301_create_resource_pool( if (!pool) return NULL; - if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn301_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 539c5aa6bffa..f7b3947a9091 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -738,7 +738,7 @@ static const struct dcn30_dwbc_mask dwbc30_mask = { static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -773,7 +773,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1036,7 +1036,7 @@ static void dcn302_resource_destruct(struct resource_pool *pool) } } - for (i = 0; i < pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } @@ -1071,7 +1071,7 @@ static void dcn302_resource_destruct(struct resource_pool *pool) dal_irq_service_destroy(&pool->irqs); } - for (i = 0; i < pool->res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) { if (pool->engines[i] != NULL) dce110_engine_destroy(&pool->engines[i]); if (pool->hw_i2cs[i] != NULL) { @@ -1084,19 +1084,19 @@ static void dcn302_resource_destruct(struct resource_pool *pool) } } - for (i = 0; i < pool->res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) { if (pool->opps[i] != NULL) pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); } - for (i = 0; i < pool->res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) { if (pool->timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); pool->timing_generators[i] = NULL; } } - for (i = 0; i < pool->res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) { if (pool->dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->dwbc[i])); pool->dwbc[i] = NULL; @@ -1120,7 +1120,7 @@ static void dcn302_resource_destruct(struct resource_pool *pool) if (pool->dp_clock_source != NULL) dcn20_clock_source_destroy(&pool->dp_clock_source); - for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) { if (pool->mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->mpc_lut[i]); pool->mpc_lut[i] = NULL; @@ -1300,7 +1300,7 @@ static bool dcn302_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -1371,7 +1371,7 @@ static bool dcn302_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->clk_src_count; i++) { + for (i = 0; i < (int)pool->clk_src_count; i++) { if (pool->clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -1416,7 +1416,7 @@ static bool dcn302_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->pipe_count; i++) { + for (i = 0; i < (int)pool->pipe_count; i++) { pool->hubps[i] = dcn302_hubp_create(ctx, i); if (pool->hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1526,7 +1526,7 @@ static bool dcn302_resource_construct( dc->caps.max_planes = pool->pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -1560,7 +1560,7 @@ struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *ini if (!pool) return NULL; - if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn302_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return pool; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 529eccb4ed3b..429365f22622 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -699,7 +699,7 @@ static const struct dcn30_dwbc_mask dwbc30_mask = { static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -734,7 +734,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -980,7 +980,7 @@ static void dcn303_resource_destruct(struct resource_pool *pool) } } - for (i = 0; i < pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } @@ -1015,7 +1015,7 @@ static void dcn303_resource_destruct(struct resource_pool *pool) dal_irq_service_destroy(&pool->irqs); } - for (i = 0; i < pool->res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) { if (pool->engines[i] != NULL) dce110_engine_destroy(&pool->engines[i]); if (pool->hw_i2cs[i] != NULL) { @@ -1028,19 +1028,19 @@ static void dcn303_resource_destruct(struct resource_pool *pool) } } - for (i = 0; i < pool->res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) { if (pool->opps[i] != NULL) pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); } - for (i = 0; i < pool->res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) { if (pool->timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); pool->timing_generators[i] = NULL; } } - for (i = 0; i < pool->res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) { if (pool->dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->dwbc[i])); pool->dwbc[i] = NULL; @@ -1064,7 +1064,7 @@ static void dcn303_resource_destruct(struct resource_pool *pool) if (pool->dp_clock_source != NULL) dcn20_clock_source_destroy(&pool->dp_clock_source); - for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) { if (pool->mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->mpc_lut[i]); pool->mpc_lut[i] = NULL; @@ -1244,7 +1244,7 @@ static bool dcn303_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -1303,7 +1303,7 @@ static bool dcn303_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->clk_src_count; i++) { + for (i = 0; i < (int)pool->clk_src_count; i++) { if (pool->clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -1348,7 +1348,7 @@ static bool dcn303_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->pipe_count; i++) { + for (i = 0; i < (int)pool->pipe_count; i++) { pool->hubps[i] = dcn303_hubp_create(ctx, i); if (pool->hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1458,7 +1458,7 @@ static bool dcn303_resource_construct( dc->caps.max_planes = pool->pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -1492,7 +1492,7 @@ struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *ini if (!pool) return NULL; - if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn303_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return pool; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index 39944d90ea98..df3e35a6a0a5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -1146,7 +1146,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1412,7 +1412,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1446,7 +1446,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1459,19 +1459,19 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1494,7 +1494,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1510,7 +1510,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1546,7 +1546,7 @@ static struct hubp *dcn31_hubp_create( static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1570,7 +1570,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1651,7 +1651,7 @@ int dcn31x_populate_dml_pipes_from_context(struct dc *dc, enum dc_validate_mode validate_mode) { uint32_t pipe_cnt; - int i; + unsigned int i; dc_assert_fp_enabled(); @@ -1675,7 +1675,7 @@ int dcn31_populate_dml_pipes_from_context( display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + unsigned int i, pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; bool upscaled = false; @@ -1987,7 +1987,7 @@ static bool dcn31_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2076,7 +2076,7 @@ static bool dcn31_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2115,7 +2115,7 @@ static bool dcn31_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn31_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2252,7 +2252,7 @@ static bool dcn31_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -2279,7 +2279,7 @@ struct resource_pool *dcn31_create_resource_pool( if (!pool) return NULL; - if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn31_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 5acc545bbe7f..74a14c0be20f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -1204,7 +1204,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1471,7 +1471,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1504,7 +1504,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) dal_irq_service_destroy(&pool->base.irqs); } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1517,19 +1517,19 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1552,7 +1552,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1568,7 +1568,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1604,7 +1604,7 @@ static struct hubp *dcn31_hubp_create( static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1628,7 +1628,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1914,7 +1914,7 @@ static bool dcn314_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -1996,7 +1996,7 @@ static bool dcn314_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2033,7 +2033,7 @@ static bool dcn314_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn31_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2163,7 +2163,7 @@ static bool dcn314_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -2191,7 +2191,7 @@ struct resource_pool *dcn314_create_resource_pool( if (!pool) return NULL; - if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn314_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 975e14f3f5fa..30b2e73abd08 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -1145,7 +1145,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1413,7 +1413,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1447,7 +1447,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1460,19 +1460,19 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1495,7 +1495,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1511,7 +1511,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1547,7 +1547,7 @@ static struct hubp *dcn31_hubp_create( static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1571,7 +1571,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1666,7 +1666,7 @@ static int source_format_to_bpp (enum source_format_class SourcePixelFormat) static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; struct resource_context *res_ctx = &context->res_ctx; /* Only apply for dual stream scenarios with edp*/ @@ -1699,7 +1699,8 @@ static int dcn315_populate_dml_pipes_from_context( display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt, crb_idx, crb_pipes; + unsigned int i; + int pipe_cnt, crb_idx, crb_pipes; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = NULL; const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB; @@ -1739,7 +1740,7 @@ static int dcn315_populate_dml_pipes_from_context( if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) { bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS; - split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); + split_required = split_required || (unsigned int)timing->pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); /* Minimum 2 segments to allow mpc/odm combine if its used later */ @@ -1788,7 +1789,7 @@ static int dcn315_populate_dml_pipes_from_context( continue; } - bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) + bool split_required = (unsigned int)pipe->stream->timing.pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); if (remaining_det_segs > MIN_RESERVED_DET_SEGS && crb_pipes != 0) @@ -1825,7 +1826,7 @@ static int dcn315_populate_dml_pipes_from_context( (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120 - && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { + && (unsigned int)pipe->stream->timing.pix_clk_100hz < (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; pipes[0].pipe.src.unbounded_req_mode = true; @@ -1957,7 +1958,7 @@ static bool dcn315_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2026,7 +2027,7 @@ static bool dcn315_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2065,7 +2066,7 @@ static bool dcn315_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn31_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2192,7 +2193,7 @@ static bool dcn315_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -2220,7 +2221,7 @@ struct resource_pool *dcn315_create_resource_pool( if (!pool) return NULL; - if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn315_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 914d91df174c..0a6dfb44e90d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -1138,7 +1138,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1408,7 +1408,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1442,7 +1442,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1455,19 +1455,19 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1490,7 +1490,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1506,7 +1506,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1539,7 +1539,7 @@ static struct hubp *dcn31_hubp_create( static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1563,7 +1563,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1644,7 +1644,8 @@ static int dcn316_populate_dml_pipes_from_context( display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + unsigned int i; + int pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB; @@ -1833,7 +1834,7 @@ static bool dcn316_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -1900,7 +1901,7 @@ static bool dcn316_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -1939,7 +1940,7 @@ static bool dcn316_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn31_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2058,7 +2059,7 @@ static bool dcn316_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -2086,7 +2087,7 @@ struct resource_pool *dcn316_create_resource_pool( if (!pool) return NULL; - if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn316_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 82f81b586986..a6985742c950 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -92,9 +92,14 @@ #include "dml/dcn32/dcn32_fpu.h" #include "dc_state_priv.h" +#include "dc_fpu.h" #include "dml2_0/dml2_wrapper.h" +#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) +#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code +#endif + #define DC_LOGGER_INIT(logger) enum dcn32_clk_src_array_id { @@ -1419,7 +1424,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1449,7 +1454,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1462,19 +1467,19 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1497,7 +1502,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1513,7 +1518,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1539,7 +1544,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1567,7 +1572,7 @@ static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1684,7 +1689,8 @@ static void dcn32_enable_phantom_plane(struct dc *dc, if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) phantom_plane = prev_phantom_plane; else - phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state); + DC_RUN_WITH_PREEMPTION_ENABLED(phantom_plane = + dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state)); if (!phantom_plane) continue; @@ -1902,7 +1908,8 @@ int dcn32_populate_dml_pipes_from_context( display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + unsigned int i; + int pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = NULL; bool subvp_in_use = false; @@ -2302,7 +2309,7 @@ static bool dcn32_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2376,7 +2383,7 @@ static bool dcn32_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2546,7 +2553,7 @@ static bool dcn32_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -2619,7 +2626,7 @@ struct resource_pool *dcn32_create_resource_pool( if (!pool) return NULL; - if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn32_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); @@ -2747,7 +2754,7 @@ static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; - secondary_pipe->pipe_idx = preferred_pipe_idx; + secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx; } } @@ -2760,7 +2767,7 @@ static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( if ((res_ctx->pipe_ctx[i].stream == NULL) && !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { secondary_pipe = &res_ctx->pipe_ctx[i]; - secondary_pipe->pipe_idx = i; + secondary_pipe->pipe_idx = (uint8_t)i; break; } } @@ -2794,7 +2801,7 @@ static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( pipe = &old_ctx->pipe_ctx[head_index]; if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; - idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; + idle_pipe->pipe_idx = (uint8_t)pipe->bottom_pipe->pipe_idx; } else { idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); if (!idle_pipe) @@ -2808,7 +2815,7 @@ static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; - idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; + idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst; return idle_pipe; } @@ -2859,7 +2866,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe( pool, opp_head_pipe); if (free_pipe_idx >= 0) { free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx]; - free_pipe->pipe_idx = free_pipe_idx; + free_pipe->pipe_idx = (uint8_t)free_pipe_idx; free_pipe->stream = opp_head_pipe->stream; free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg; free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp; @@ -2868,7 +2875,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe( free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx]; free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx]; free_pipe->plane_res.mpcc_inst = - pool->dpps[free_pipe->pipe_idx]->inst; + (uint8_t)pool->dpps[free_pipe->pipe_idx]->inst; } else { ASSERT(opp_head_pipe); free_pipe = NULL; @@ -2890,7 +2897,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head( if (free_pipe_idx >= 0) { free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx]; - free_pipe->pipe_idx = free_pipe_idx; + free_pipe->pipe_idx = (uint8_t)free_pipe_idx; free_pipe->stream = otg_master->stream; free_pipe->stream_res.tg = otg_master->stream_res.tg; free_pipe->stream_res.dsc = NULL; @@ -2900,7 +2907,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head( free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx]; free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx]; free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx]; - free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst; + free_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[free_pipe_idx]->inst; free_pipe->dsc_padding_params = otg_master->dsc_padding_params; if (free_pipe->stream->timing.flags.DSC == 1) { dcn20_acquire_dsc(free_pipe->stream->ctx->dc, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index 4808c793590f..602a0e4e5dc0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -333,7 +333,7 @@ void dcn32_determine_det_override(struct dc *dc, continue; if (context->stream_status[i].plane_count > 0) - plane_segments = stream_segments / context->stream_status[i].plane_count; + plane_segments = (uint8_t)(stream_segments / context->stream_status[i].plane_count); else plane_segments = stream_segments; for (j = 0; j < dc->res_pool->pipe_count; j++) { @@ -382,7 +382,8 @@ void dcn32_determine_det_override(struct dc *dc, void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) { - int i, pipe_cnt; + unsigned int i; + int pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting; @@ -751,7 +752,8 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) { - int i, pipe_cnt; + unsigned int i; + int pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index c8c81870d50e..ede21363542a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -1400,7 +1400,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1429,7 +1429,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) dal_irq_service_destroy(&pool->base.irqs); } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1442,19 +1442,19 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1477,7 +1477,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1493,7 +1493,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1519,7 +1519,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1547,7 +1547,7 @@ static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *poo static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1801,7 +1801,7 @@ static bool dcn321_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -1875,7 +1875,7 @@ static bool dcn321_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2040,7 +2040,7 @@ static bool dcn321_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -2109,7 +2109,7 @@ struct resource_pool *dcn321_create_resource_pool( if (!pool) return NULL; - if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn321_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 2a1b0b152501..dcbfe18b484e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -1153,7 +1153,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1483,7 +1483,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1513,7 +1513,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1526,19 +1526,19 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1561,7 +1561,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1577,7 +1577,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1634,7 +1634,7 @@ static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1672,7 +1672,7 @@ static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1948,7 +1948,7 @@ static bool dcn35_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2037,7 +2037,7 @@ static bool dcn35_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2089,7 +2089,7 @@ static bool dcn35_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn35_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2221,7 +2221,7 @@ static bool dcn35_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -2266,7 +2266,7 @@ struct resource_pool *dcn35_create_resource_pool( if (!pool) return NULL; - if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn35_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index bfd1016aa780..7a6e8e6f0ea6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -1133,7 +1133,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1463,7 +1463,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1493,7 +1493,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1506,19 +1506,19 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1541,7 +1541,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1557,7 +1557,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1614,7 +1614,7 @@ static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1652,7 +1652,7 @@ static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1921,7 +1921,7 @@ static bool dcn351_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2009,7 +2009,7 @@ static bool dcn351_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2061,7 +2061,7 @@ static bool dcn351_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn35_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2193,7 +2193,7 @@ static bool dcn351_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -2239,7 +2239,7 @@ struct resource_pool *dcn351_create_resource_pool( if (!pool) return NULL; - if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn351_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 07a6675a7329..83f2fd660789 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -1140,7 +1140,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1470,7 +1470,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1500,7 +1500,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1513,19 +1513,19 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1548,7 +1548,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1564,7 +1564,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1621,7 +1621,7 @@ static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1659,7 +1659,7 @@ static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1918,7 +1918,7 @@ static bool dcn36_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2007,7 +2007,7 @@ static bool dcn36_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2059,7 +2059,7 @@ static bool dcn36_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn35_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2191,7 +2191,7 @@ static bool dcn36_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -2236,7 +2236,7 @@ struct resource_pool *dcn36_create_resource_pool( if (!pool) return NULL; - if (dcn36_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn36_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index cb93bfbe9e9e..e24d908bcf68 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1425,7 +1425,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn401_dsc_destroy(&pool->base.dscs[i]); } @@ -1455,7 +1455,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1468,19 +1468,19 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1503,7 +1503,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1519,7 +1519,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1545,7 +1545,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1575,7 +1575,7 @@ static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *poo static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1792,11 +1792,11 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) pixel_clk_params->dio_se_pix_per_cycle = 2; } else if (dc_is_dp_signal(stream->signal)) { /* round up to nearest power of 2, or max at 8 pixels per cycle */ - if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 8; - } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + } else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 4; - } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + } else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 2; } else { pixel_clk_params->dio_se_pix_per_cycle = 1; @@ -1806,10 +1806,10 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) int dcn401_get_power_profile(const struct dc_state *context) { - int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; + unsigned int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; int dpm_level = 0; - for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { + for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) break; @@ -2002,7 +2002,7 @@ static bool dcn401_resource_construct( dc->caps.color.dpp.ocsc = 0; dc->caps.color.mpc.gamut_remap = 1; - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; @@ -2096,7 +2096,7 @@ static bool dcn401_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2258,7 +2258,7 @@ static bool dcn401_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; @@ -2336,7 +2336,7 @@ struct resource_pool *dcn401_create_resource_pool( if (!pool) return NULL; - if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn401_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index c0d37f00fed9..1fc457cec293 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -666,7 +666,6 @@ static const struct resource_caps res_cap_dcn42 = { .num_vmid = 16, .num_mpc_3dlut = 2, .num_dsc = 4, - .num_rmcm = 2, }; static const struct dc_plane_cap plane_cap = { @@ -694,9 +693,13 @@ static const struct dc_debug_options debug_defaults_drv = { .force_abm_enable = false, .clock_trace = true, .disable_pplib_clock_request = false, + .ignore_pg = false, .disable_dpp_power_gate = true, .disable_hubp_power_gate = true, .disable_optc_power_gate = true, + .disable_dsc_power_gate = false, + .disable_dio_power_gate = true, + .disable_hpo_power_gate = true, .pipe_split_policy = MPC_SPLIT_AVOID, .force_single_disp_pipe_split = false, .disable_dcc = DCC_ENABLE, @@ -758,11 +761,11 @@ static const struct dc_debug_options debug_defaults_drv = { .min_disp_clk_khz = 50000, .static_screen_wait_frames = 2, .disable_z10 = false, - .ignore_pg = true, .disable_stutter_for_wm_program = true, .min_deep_sleep_dcfclk_khz = 8000, .replay_skip_crtc_disabled = true, .psr_skip_crtc_disable = true, + .force_odm2to1_for_edp_pixclk_mhz = 550, // Force ODM 2to1 for eDP when pixel clock is above 550MHz }; static const struct dc_check_config config_defaults = { @@ -1414,7 +1417,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn42_dsc_destroy(&pool->base.dscs[i]); } @@ -1443,7 +1446,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) dal_irq_service_destroy(&pool->base.irqs); } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1456,19 +1459,19 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1491,7 +1494,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1507,7 +1510,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1517,6 +1520,10 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) if (pool->base.pg_cntl != NULL) dcn_pg_cntl_destroy(&pool->base.pg_cntl); + + if (pool->base.replay != NULL) + dmub_replay_destroy(&pool->base.replay); + if (pool->base.dccg != NULL) dcn_dccg_destroy(&pool->base.dccg); @@ -1578,11 +1585,11 @@ static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) pixel_clk_params->dio_se_pix_per_cycle = 2; } else if (dc_is_dp_signal(stream->signal)) { /* round up to nearest power of 2, or max at 8 pixels per cycle */ - if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 8; - } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 4; - } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 2; } else { pixel_clk_params->dio_se_pix_per_cycle = 1; @@ -1592,7 +1599,7 @@ static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) static bool dcn42_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1629,7 +1636,7 @@ static void dcn42_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, static bool dcn42_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1719,9 +1726,12 @@ enum dc_status dcn42_validate_bandwidth(struct dc *dc, DC_FP_START(); + dcn42_decide_odm_override(dc, context); + out = dml2_validate(dc, context, context->bw_ctx.dml2, validate_mode); + if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { /*not required for mode enumeration*/ dcn42_decide_zstate_support(dc, context); @@ -1751,7 +1761,7 @@ static struct link_encoder *dcn42_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if ((unsigned int)(eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); @@ -1805,8 +1815,6 @@ static struct resource_funcs dcn42_res_pool_funcs = { .get_panel_config_defaults = dcn42_get_panel_config_defaults, .get_preferred_eng_id_dpia = dcn42_get_preferred_eng_id_dpia, .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, - .add_phantom_pipes = dcn32_add_phantom_pipes, - .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, .prepare_mcache_programming = dcn42_prepare_mcache_programming, .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params, .get_power_profile = dcn401_get_power_profile, @@ -1831,7 +1839,7 @@ static bool dcn42_resource_construct( struct dc *dc, struct dcn42_resource_pool *pool) { - int i, j; + unsigned int i, j; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; uint32_t pipe_fuses; @@ -1867,7 +1875,7 @@ static bool dcn42_resource_construct( num_pipes = pool->base.res_cap->num_dpp; pipe_fuses = read_pipe_fuses(ctx); - for (i = 0; i < pool->base.res_cap->num_dpp; i++) + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dpp; i++) if (pipe_fuses & 1 << i) num_pipes--; @@ -1896,27 +1904,7 @@ static bool dcn42_resource_construct( dc->caps.cursor_not_scaled = true; dc->caps.min_horizontal_blanking_period = 80; dc->caps.dmdata_alloc_size = 2048; - dc->caps.mall_size_per_mem_channel = 4; - /* total size = mall per channel * num channels * 1024 * 1024 */ - dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * - dc->ctx->dc_bios->vram_info.num_chans * 1048576; dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; - dc->caps.cache_line_size = 64; - dc->caps.cache_num_ways = 16; - - /* Calculate the available MALL space */ - dc->caps.max_cab_allocation_bytes = - dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) * - dc->caps.mall_size_per_mem_channel * 1024 * 1024; - dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; - - dc->caps.subvp_fw_processing_delay_us = 15; - dc->caps.subvp_drr_max_vblank_margin_us = 40; - dc->caps.subvp_prefetch_end_to_mall_start_us = 15; - dc->caps.subvp_swath_height_margin_lines = 16; - dc->caps.subvp_pstate_allow_width_us = 20; - dc->caps.subvp_vertical_int_margin_us = 30; - dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin dc->caps.max_slave_planes = 2; dc->caps.max_slave_yuv_planes = 2; @@ -1937,12 +1925,6 @@ static bool dcn42_resource_construct( dc->caps.max_v_total = (1 << 15) - 1; dc->caps.vtotal_limited_by_fp2 = true; - dc->caps.seamless_odm = true; - dc->caps.zstate_support = true; - dc->caps.ips_support = true; - dc->caps.max_v_total = (1 << 15) - 1; - dc->caps.vtotal_limited_by_fp2 = true; - /* Color pipeline capabilities */ dc->caps.color.dpp.dcn_arch = 1; dc->caps.color.dpp.input_lut_shared = 0; @@ -1969,7 +1951,7 @@ static bool dcn42_resource_construct( dc->caps.color.mpc.gamut_remap = 1; //configurable to be before or after BLND in MPCC - dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; + dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; dc->caps.color.mpc.num_rmcm_3dluts = 2; dc->caps.color.mpc.ogam_ram = 1; dc->caps.color.mpc.ogam_rom_caps.srgb = 0; @@ -2141,7 +2123,7 @@ static bool dcn42_resource_construct( } /* HUBPs, DPPs, OPPs, TGs, ABMs */ - for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0, j = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { /* if pipe is disabled, skip instance of HW pipe, * i.e, skip ASIC register instance */ @@ -2185,7 +2167,7 @@ static bool dcn42_resource_construct( &abm_shift, &abm_mask); if (pool->base.multiple_abms[j] == NULL) { - dm_error("DC: failed to create abm for pipe %d!\n", i); + dm_error("DC: failed to create abm for pipe %u!\n", i); BREAK_TO_DEBUGGER(); goto create_fail; } @@ -2220,11 +2202,11 @@ static bool dcn42_resource_construct( } /* DSCs */ - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn42_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { BREAK_TO_DEBUGGER(); - dm_error("DC: failed to create display stream compressor %d!\n", i); + dm_error("DC: failed to create display stream compressor %u!\n", i); goto create_fail; } } @@ -2244,7 +2226,7 @@ static bool dcn42_resource_construct( } /* AUX and I2C */ - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dcn42_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { @@ -2302,26 +2284,6 @@ static bool dcn42_resource_construct( resource_init_common_dml2_callbacks(dc, &dc->dml2_options); dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; - dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; - dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = - pool->base.funcs->calculate_mall_ways_from_bytes; - - dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; - dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us; - dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; - dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines; - - dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp; - dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch; - - dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; - dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; - dc->dml2_options.mall_cfg.max_cab_allocation_bytes = - dc->caps.max_cab_allocation_bytes; - dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE; - dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE; - dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; - dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; dc->dml2_options.max_segments_per_hubp = 24; dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB; @@ -2349,7 +2311,7 @@ struct resource_pool *dcn42_create_resource_pool( if (!pool) return NULL; - if (dcn42_resource_construct(init_data->num_virtual_links, dc, pool)) + if (dcn42_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) return &pool->base; BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h index 60acf0e423d9..fe960542d7bd 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h @@ -456,6 +456,8 @@ SRI_ARR(OTG_V_SYNC_A, OTG, inst), \ SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \ SRI_ARR(OTG_CONTROL, OTG, inst), \ + SRI_ARR(OTG_MASTER_EN, OTG, inst), \ + SRI_ARR(OTG_LONG_VBLANK_STATUS, OTG, inst), \ SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \ SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \ SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \ @@ -472,6 +474,11 @@ SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \ SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \ SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \ + SRI_ARR(OTG_COUNT_CONTROL, OTG, inst), \ + SRI_ARR(OTG_COUNT_RESET, OTG, inst), \ + SRI_ARR(OTG_CRC_SIG_BLUE_CONTROL_MASK, OTG, inst), \ + SRI_ARR(OTG_CRC_SIG_RED_GREEN_MASK, OTG, inst), \ + SRI_ARR(OTG_DRR_TIMING_INT_STATUS, OTG, inst), \ SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \ SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \ SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c index 33b9775420d3..ee330559c233 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c @@ -45,3 +45,25 @@ void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context) context->bw_ctx.bw.dcn.clk.zstate_support = support; } + +bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context) +{ + bool odm_override = false; + + DC_LOGGER_INIT(dc->ctx->logger); + if (dc->ctx->dce_environment == DCE_ENV_DIAG) + return false; + + if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { + + if (dc->debug.force_odm2to1_for_edp_pixclk_mhz != 0 && + context->streams[0]->timing.pix_clk_100hz > dc->debug.force_odm2to1_for_edp_pixclk_mhz * 10000) { + odm_override = true; + context->streams[0]->debug.force_odm_combine_segments = 2; + } + DC_LOG_SMU("odm_override: %d, eDP pixelclock: %d, force_odm2to1_for_edp_pixclk_mhz: %d\n", + odm_override, context->streams[0]->timing.pix_clk_100hz / 10000, dc->debug.force_odm2to1_for_edp_pixclk_mhz); + } + return odm_override; +} + diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h index e32103220507..aff7be777681 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h @@ -29,5 +29,5 @@ #include "core_types.h" void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context); - +bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context); #endif /* _DCN42_RESOURCE_FPU_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c index 1b397fa7e05c..89f7ccd7f81f 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c @@ -42,17 +42,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* dcfclk */ if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { - dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + dml_clk_table->dcfclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dcfclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz && dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].dcfclk_mhz < dc_bw_params->dc_mode_limit.dcfclk_mhz) { dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000; - dml_clk_table->dcfclk.num_clk_values = i + 1; + dml_clk_table->dcfclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->dcfclk.clk_values_khz[i] = 0; - dml_clk_table->dcfclk.num_clk_values = i; + dml_clk_table->dcfclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; @@ -65,17 +65,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* fclk */ if (dc_clk_table->num_entries_per_clk.num_fclk_levels) { - dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; + dml_clk_table->fclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_fclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->fclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz && dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].fclk_mhz < dc_bw_params->dc_mode_limit.fclk_mhz) { dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000; - dml_clk_table->fclk.num_clk_values = i + 1; + dml_clk_table->fclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->fclk.clk_values_khz[i] = 0; - dml_clk_table->fclk.num_clk_values = i; + dml_clk_table->fclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000; @@ -88,17 +88,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* uclk */ if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { - dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; + dml_clk_table->uclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_memclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->uclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz && dc_clk_table->entries[i].memclk_mhz > dc_bw_params->dc_mode_limit.memclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].memclk_mhz < dc_bw_params->dc_mode_limit.memclk_mhz) { dml_clk_table->uclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.memclk_mhz * 1000; - dml_clk_table->uclk.num_clk_values = i + 1; + dml_clk_table->uclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->uclk.clk_values_khz[i] = 0; - dml_clk_table->uclk.num_clk_values = i; + dml_clk_table->uclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; @@ -114,17 +114,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* dispclk */ if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { - dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; + dml_clk_table->dispclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dispclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dispclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz && dc_clk_table->entries[i].dispclk_mhz > dc_bw_params->dc_mode_limit.dispclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].dispclk_mhz < dc_bw_params->dc_mode_limit.dispclk_mhz) { dml_clk_table->dispclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dispclk_mhz * 1000; - dml_clk_table->dispclk.num_clk_values = i + 1; + dml_clk_table->dispclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->dispclk.clk_values_khz[i] = 0; - dml_clk_table->dispclk.num_clk_values = i; + dml_clk_table->dispclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; @@ -137,17 +137,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* dppclk */ if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { - dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; + dml_clk_table->dppclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dppclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dppclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dppclk_mhz && dc_clk_table->entries[i].dppclk_mhz > dc_bw_params->dc_mode_limit.dppclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].dppclk_mhz < dc_bw_params->dc_mode_limit.dppclk_mhz) { dml_clk_table->dppclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dppclk_mhz * 1000; - dml_clk_table->dppclk.num_clk_values = i + 1; + dml_clk_table->dppclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->dppclk.clk_values_khz[i] = 0; - dml_clk_table->dppclk.num_clk_values = i; + dml_clk_table->dppclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000; @@ -160,17 +160,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* dtbclk */ if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) { - dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; + dml_clk_table->dtbclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dtbclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dtbclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dtbclk_mhz && dc_clk_table->entries[i].dtbclk_mhz > dc_bw_params->dc_mode_limit.dtbclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].dtbclk_mhz < dc_bw_params->dc_mode_limit.dtbclk_mhz) { dml_clk_table->dtbclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dtbclk_mhz * 1000; - dml_clk_table->dtbclk.num_clk_values = i + 1; + dml_clk_table->dtbclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->dtbclk.clk_values_khz[i] = 0; - dml_clk_table->dtbclk.num_clk_values = i; + dml_clk_table->dtbclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; @@ -183,17 +183,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( /* socclk */ if (dc_clk_table->num_entries_per_clk.num_socclk_levels) { - dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels; + dml_clk_table->socclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_socclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->socclk.num_clk_values) { if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.socclk_mhz && dc_clk_table->entries[i].socclk_mhz > dc_bw_params->dc_mode_limit.socclk_mhz) { if (i == 0 || dc_clk_table->entries[i-1].socclk_mhz < dc_bw_params->dc_mode_limit.socclk_mhz) { dml_clk_table->socclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.socclk_mhz * 1000; - dml_clk_table->socclk.num_clk_values = i + 1; + dml_clk_table->socclk.num_clk_values = (uint8_t)(i + 1); } else { dml_clk_table->socclk.clk_values_khz[i] = 0; - dml_clk_table->socclk.num_clk_values = i; + dml_clk_table->socclk.num_clk_values = (uint8_t)i; } } else { dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000; diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c index e723b4d0aff3..e0802359829e 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c @@ -47,18 +47,18 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( * for use with dml we need to fill in using an active value aiming for >= 2x DCFCLK */ if (dc_clk_table->num_entries_per_clk.num_fclk_levels && dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { - dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; - dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + dml_clk_table->fclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + dml_clk_table->dcfclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { - if (i < dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { + if (i < (int)dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { int j, max_fclk = 0; dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; for (j = 0; j < MAX_NUM_DPM_LVL; j++) { - if (dc_clk_table->entries[j].fclk_mhz * 1000 > max_fclk) + if ((uint32_t)(dc_clk_table->entries[j].fclk_mhz * 1000) > (uint32_t)max_fclk) max_fclk = dc_clk_table->entries[j].fclk_mhz * 1000; dml_clk_table->fclk.clk_values_khz[i] = max_fclk; - if (max_fclk >= 2 * dml_clk_table->dcfclk.clk_values_khz[i]) + if ((uint32_t)max_fclk >= 2 * dml_clk_table->dcfclk.clk_values_khz[i]) break; } } else { @@ -70,7 +70,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( /* uclk */ if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { - dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; + dml_clk_table->uclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_memclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->uclk.num_clk_values) { dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; @@ -84,7 +84,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( /* dispclk */ if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { - dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; + dml_clk_table->dispclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dispclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dispclk.num_clk_values) { dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; @@ -101,7 +101,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( /* dppclk */ if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { - dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; + dml_clk_table->dppclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dppclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dppclk.num_clk_values) { dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000; @@ -117,7 +117,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( /* dtbclk */ if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) { - dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; + dml_clk_table->dtbclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dtbclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->dtbclk.num_clk_values) { dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; @@ -129,7 +129,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( /* socclk */ if (dc_clk_table->num_entries_per_clk.num_socclk_levels) { - dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels; + dml_clk_table->socclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_socclk_levels; for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { if (i < dml_clk_table->socclk.num_clk_values) { dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000; diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index fe9431cea3e5..2f68438000ea 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -329,7 +329,7 @@ union dmub_addr { /* Flattened structure containing SOC BB parameters stored in the VBIOS * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. - * This also prevents alighment issues when new parameters are added to the SoC BB. + * This also prevents alignment issues when new parameters are added to the SoC BB. * The following parameters should be added since these values can't be obtained elsewhere: * -dml2_soc_power_management_parameters * -dml2_soc_vmin_clock_limits @@ -958,7 +958,7 @@ union dmub_fw_meta { //============================================================================== #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) /** - * dmub_trace_code_t - firmware trace code, 32-bits + * typedef dmub_trace_code_t - firmware trace code, 32-bits */ typedef uint32_t dmub_trace_code_t; @@ -1170,7 +1170,7 @@ enum dmub_shared_state_feature_id { }; /** - * struct dmub_shared_state_ips_fw - Firmware signals for IPS. + * struct dmub_shared_state_ips_fw_signals - Firmware signals for IPS. */ union dmub_shared_state_ips_fw_signals { struct { @@ -1185,7 +1185,7 @@ union dmub_shared_state_ips_fw_signals { }; /** - * struct dmub_shared_state_ips_signals - Firmware signals for IPS. + * struct dmub_shared_state_ips_driver_signals - Firmware signals for IPS. */ union dmub_shared_state_ips_driver_signals { struct { @@ -1247,7 +1247,7 @@ struct dmub_shared_state_ips_driver { }; /* 248-bytes, fixed */ /** - * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. + * struct dmub_shared_state_cursor_offload_stream_v1 - Header metadata for cursor offload. */ struct dmub_shared_state_cursor_offload_stream_v1 { uint32_t last_write_idx; /**< Last write index */ @@ -1263,14 +1263,14 @@ struct dmub_shared_state_cursor_offload_v1 { }; /* 248-bytes, fixed */ /** - * enum dmub_shared_state_feature_common - Generic payload. + * struct dmub_shared_state_feature_common - Generic payload. */ struct dmub_shared_state_feature_common { uint32_t padding[62]; }; /* 248-bytes, fixed */ /** - * enum dmub_shared_state_feature_header - Feature description. + * struct dmub_shared_state_feature_header - Feature description. */ struct dmub_shared_state_feature_header { uint16_t id; /**< Feature ID */ @@ -1546,8 +1546,9 @@ enum dmub_gpint_command { * DESC: Gets IPS residency in microseconds * ARGS: 0 - Return IPS1 residency * 1 - Return IPS2 residency - * 2 - Return IPS1_RCG residency + * 2 - Return IPS0_RCG residency * 3 - Return IPS1_ONO2_ON residency + * 4 - Return IPS1_Z8_RETENTION residency * RETURN: Total residency in microseconds - lower 32 bits */ DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, @@ -1567,17 +1568,18 @@ enum dmub_gpint_command { * DESC: Gets IPS residency * ARGS: 0 - Return IPS1 residency * 1 - Return IPS2 residency - * 2 - Return IPS1_RCG residency + * 2 - Return IPS0_RCG residency * 3 - Return IPS1_ONO2_ON residency + * 4 - Return IPS1_Z8_RETENTION residency * RETURN: Total residency in milli-percent. */ DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, /** - * DESC: Gets IPS1_RCG histogram counts + * DESC: Gets IPS0_RCG histogram counts * ARGS: Bucket index * RETURN: Total count for the bucket */ - DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, + DMUB_GPINT__GET_IPS0_RCG_HISTOGRAM_COUNTER = 128, /** * DESC: Gets IPS1_ONO2_ON histogram counts * ARGS: Bucket index @@ -1588,8 +1590,9 @@ enum dmub_gpint_command { * DESC: Gets IPS entry counter during residency measurement * ARGS: 0 - Return IPS1 entry counts * 1 - Return IPS2 entry counts - * 2 - Return IPS1_RCG entry counts - * 3 - Return IPS2_ONO2_ON entry counts + * 2 - Return IPS0_RCG entry counts + * 3 - Return IPS1_ONO2_ON entry counts + * 4 - Return IPS1_Z8_RETENTION entry counts * RETURN: Entry counter for selected IPS mode */ DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, @@ -1597,8 +1600,9 @@ enum dmub_gpint_command { * DESC: Gets IPS inactive residency in microseconds * ARGS: 0 - Return IPS1_MAX residency * 1 - Return IPS2 residency - * 2 - Return IPS1_RCG residency + * 2 - Return IPS0_RCG residency * 3 - Return IPS1_ONO2_ON residency + * 4 - Return IPS1_Z8_RETENTION residency * RETURN: Total inactive residency in microseconds - lower 32 bits */ DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, @@ -1606,8 +1610,9 @@ enum dmub_gpint_command { * DESC: Gets IPS inactive residency in microseconds * ARGS: 0 - Return IPS1_MAX residency * 1 - Return IPS2 residency - * 2 - Return IPS1_RCG residency + * 2 - Return IPS0_RCG residency * 3 - Return IPS1_ONO2_ON residency + * 4 - Return IPS1_Z8_RETENTION residency * RETURN: Total inactive residency in microseconds - upper 32 bits */ DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, @@ -1615,8 +1620,9 @@ enum dmub_gpint_command { * DESC: Gets IPS residency in microseconds * ARGS: 0 - Return IPS1 residency * 1 - Return IPS2 residency - * 2 - Return IPS1_RCG residency + * 2 - Return IPS0_RCG residency * 3 - Return IPS1_ONO2_ON residency + * 4 - Return IPS1_Z8_RETENTION residency * RETURN: Total residency in microseconds - upper 32 bits */ DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, @@ -1990,7 +1996,7 @@ struct dmub_cmd_read_modify_write_sequence { #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 /** - * struct dmub_cmd_read_modify_write_sequence - Read modify write command. + * struct dmub_rb_cmd_read_modify_write - Read modify write command. */ struct dmub_rb_cmd_read_modify_write { struct dmub_cmd_header header; /**< command header */ @@ -2001,7 +2007,7 @@ struct dmub_rb_cmd_read_modify_write { }; /* - * Update a register with specified masks and values sequeunce + * Update a register with specified masks and values sequence * * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword * @@ -2182,7 +2188,7 @@ enum dmub_cmd_cab_type { }; /** - * struct dmub_rb_cmd_cab - CAB command data. + * struct dmub_rb_cmd_cab_for_ss - CAB command data. */ struct dmub_rb_cmd_cab_for_ss { struct dmub_cmd_header header; @@ -2344,24 +2350,24 @@ struct dmub_cmd_lsdma_data { uint32_t dst_mip_max : 5; uint32_t dst_swizzle_mode : 5; uint32_t dst_mip_id : 5; - uint32_t tmz : 1; uint32_t dcc : 1; + uint32_t padding1 : 1; uint32_t data_format : 6; - uint32_t padding1 : 4; + uint32_t tmz : 4; uint32_t dst_element_size : 3; uint32_t num_type : 3; uint32_t src_element_size : 3; uint32_t write_compress : 2; - uint32_t cache_policy_dst : 2; - uint32_t cache_policy_src : 2; + uint32_t cache_policy_dst : 3; + uint32_t cache_policy_src : 3; uint32_t read_compress : 2; - uint32_t src_dim : 2; - uint32_t dst_dim : 2; + uint32_t max_com : 2; uint32_t max_uncom : 1; - uint32_t max_com : 2; - uint32_t padding : 30; + uint32_t dst_dim : 2; + uint32_t src_dim : 2; + uint32_t padding : 28; } tiled_copy_data; struct lsdma_linear_copy_data { uint32_t src_lo; @@ -2371,11 +2377,13 @@ struct dmub_cmd_lsdma_data { uint32_t dst_hi; uint32_t count : 30; - uint32_t cache_policy_dst : 2; + uint32_t pad0 : 2; - uint32_t tmz : 1; - uint32_t cache_policy_src : 2; - uint32_t padding : 29; + uint32_t tmz : 4; + uint32_t cache_policy_src : 3; + uint32_t cache_policy_dst : 3; + uint32_t pad1 : 22; + // DCC fields not included because linear mode on display does not support DCC } linear_copy_data; struct lsdma_linear_sub_window_copy_data { uint32_t src_lo; @@ -2399,11 +2407,13 @@ struct dmub_cmd_lsdma_data { uint32_t src_slice_pitch; uint32_t dst_slice_pitch; - uint32_t tmz : 1; + uint32_t tmz : 4; uint32_t element_size : 3; uint32_t src_cache_policy : 3; uint32_t dst_cache_policy : 3; - uint32_t reserved0 : 22; + uint32_t reserved0 : 19; + // Linear mode on display does not support compression so DCC related fields are not included. + // The DCC fields in the command packet will be zero'd at the time of constructing the packet. } linear_sub_window_copy_data; struct lsdma_reg_write_data { uint32_t reg_addr; @@ -2867,7 +2877,7 @@ struct dmub_cmd_set_pixel_clock_data { }; /** - * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. + * struct dmub_rb_cmd_set_pixel_clock - Set pixel clock command. */ struct dmub_rb_cmd_set_pixel_clock { struct dmub_cmd_header header; /**< header */ @@ -3383,7 +3393,7 @@ struct dpia_bw_allocation_notify_data { }; /** - * union dpia_notify_data_type - DPIA Notification in Outbox command + * union dpia_notification_data - DPIA Notification in Outbox command */ union dpia_notification_data { /** @@ -3439,7 +3449,7 @@ struct dmub_rb_cmd_query_hpd_state { }; /** - * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. + * struct dmub_rb_cmd_hpd_sense_notify_data - HPD sense notification data. */ struct dmub_rb_cmd_hpd_sense_notify_data { uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ @@ -3483,7 +3493,7 @@ enum dmub_cmd_psr_type { /** * Set PSR level. - * PSR level is a 16-bit value dicated by driver that + * PSR level is a 16-bit value dictated by driver that * will enable/disable different functionality. */ DMUB_CMD__PSR_SET_LEVEL = 4, @@ -3640,7 +3650,7 @@ struct dmub_cmd_psr_copy_settings_data { */ union dmub_psr_debug_flags debug; /** - * 16-bit value dicated by driver that will enable/disable different functionality. + * 16-bit value dictated by driver that will enable/disable different functionality. */ uint16_t psr_level; /** @@ -3680,7 +3690,7 @@ struct dmub_cmd_psr_copy_settings_data { */ uint8_t aux_inst; /** - * Determines if SMU optimzations are enabled/disabled. + * Determines if SMU optimizations are enabled/disabled. */ uint8_t smu_optimizations_en; /** @@ -3797,7 +3807,7 @@ struct dmub_rb_cmd_psr_copy_settings { */ struct dmub_cmd_psr_set_level_data { /** - * 16-bit value dicated by driver that will enable/disable different functionality. + * 16-bit value dictated by driver that will enable/disable different functionality. */ uint16_t psr_level; /** @@ -4175,7 +4185,7 @@ struct dmub_rb_cmd_update_cursor_info { */ struct dmub_cmd_psr_set_vtotal_data { /** - * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. + * 16-bit value dictated by driver that indicates the vtotal in PSR active requirement when screen idle.. */ uint16_t psr_vtotal_idle; /** @@ -4189,7 +4199,7 @@ struct dmub_cmd_psr_set_vtotal_data { */ uint8_t panel_inst; /* - * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. + * 16-bit value dictated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. */ uint16_t psr_vtotal_su; /** @@ -4489,7 +4499,7 @@ struct dmub_cmd_replay_copy_settings_data { uint8_t aux_inst; /** * Panel Instance. - * Panel isntance to identify which psr_state to use + * Panel instance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4512,7 +4522,7 @@ struct dmub_cmd_replay_copy_settings_data { */ uint8_t dpphy_inst; /** - * Determines if SMU optimzations are enabled/disabled. + * Determines if SMU optimizations are enabled/disabled. */ uint8_t smu_optimizations_en; /** @@ -4602,7 +4612,7 @@ struct dmub_rb_cmd_smart_power_oled_enable_data { uint8_t enable; /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4641,7 +4651,7 @@ struct dmub_rb_cmd_replay_enable_data { uint8_t enable; /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4689,7 +4699,7 @@ struct dmub_rb_cmd_replay_enable { struct dmub_cmd_replay_set_power_opt_data { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4709,7 +4719,7 @@ struct dmub_cmd_replay_set_power_opt_data { struct dmub_cmd_replay_set_timing_sync_data { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4729,7 +4739,7 @@ struct dmub_cmd_replay_set_timing_sync_data { struct dmub_cmd_replay_set_pseudo_vtotal { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4745,7 +4755,7 @@ struct dmub_cmd_replay_set_pseudo_vtotal { struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4759,7 +4769,7 @@ struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { struct dmub_cmd_replay_set_general_cmd_data { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4796,7 +4806,7 @@ struct dmub_rb_cmd_replay_set_power_opt { */ struct dmub_cmd_replay_set_coasting_vtotal_data { /** - * 16-bit value dicated by driver that indicates the coasting vtotal. + * 16-bit value dictated by driver that indicates the coasting vtotal. */ uint16_t coasting_vtotal; /** @@ -4805,12 +4815,12 @@ struct dmub_cmd_replay_set_coasting_vtotal_data { uint8_t cmd_version; /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; /** - * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. + * 16-bit value dictated by driver that indicates the coasting vtotal high byte part. */ uint16_t coasting_vtotal_high; /** @@ -4913,7 +4923,7 @@ struct dmub_rb_cmd_replay_set_general_cmd { struct dmub_cmd_replay_frameupdate_timer_data { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -4946,7 +4956,7 @@ struct dmub_rb_cmd_replay_set_frameupdate_timer { union dmub_replay_cmd_set { /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -5122,7 +5132,7 @@ struct dmub_hw_lock_inst_flags { uint8_t opp_inst; /** * OTG HW instance for global update lock. - * TODO: Remove, and re-use otg_inst. + * TODO: Remove, and reuse otg_inst. */ uint8_t dig_inst; /** @@ -6318,7 +6328,7 @@ struct dmub_cmd_cable_id_input { }; /** - * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. + * struct dmub_cmd_cable_id_output - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. */ struct dmub_cmd_cable_id_output { uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ @@ -6513,7 +6523,7 @@ struct dmub_rb_cmd_assr_enable { enum ips_residency_mode { IPS_RESIDENCY__IPS1_MAX, IPS_RESIDENCY__IPS2, - IPS_RESIDENCY__IPS1_RCG, + IPS_RESIDENCY__IPS1_RCG, // refers to IPS0 + RCG IPS_RESIDENCY__IPS1_ONO2_ON, IPS_RESIDENCY__IPS1_Z8_RETENTION, IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS, @@ -6609,7 +6619,7 @@ struct dmub_cmd_pr_enable_data { uint8_t enable; /** * Panel Instance. - * Panel isntance to identify which replay_state to use + * Panel instance to identify which replay_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -6687,7 +6697,7 @@ struct dmub_cmd_pr_copy_settings_data { uint8_t aux_inst; /** * Panel Instance. - * Panel isntance to identify which psr_state to use + * Panel instance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -6696,7 +6706,7 @@ struct dmub_cmd_pr_copy_settings_data { */ uint8_t dpphy_inst; /** - * Determines if SMU optimzations are enabled/disabled. + * Determines if SMU optimizations are enabled/disabled. */ uint8_t smu_optimizations_en; /** @@ -6704,7 +6714,7 @@ struct dmub_cmd_pr_copy_settings_data { */ uint32_t line_time_in_ns; /* - * Use FSFT afftet pixel clk + * Use FSFT after pixel clk */ uint32_t pix_clk_100hz; /* @@ -6777,7 +6787,7 @@ union dmub_pr_runtime_flags { struct dmub_cmd_pr_update_state_data { /** * Panel Instance. - * Panel isntance to identify which psr_state to use + * Panel instance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; @@ -6799,7 +6809,7 @@ struct dmub_cmd_pr_update_state_data { struct dmub_cmd_pr_general_cmd_data { /** * Panel Instance. - * Panel isntance to identify which psr_state to use + * Panel instance to identify which psr_state to use * Currently the support is only for 0 or 1 */ uint8_t panel_inst; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c index e5a78df80d72..3444eb7d7d81 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c @@ -535,7 +535,7 @@ void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) { uint32_t *dwords = (uint32_t *)cmd; - int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; + uint32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; uint32_t msg_index; static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c index a09aa19ad379..e86fcfc74985 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c @@ -429,7 +429,7 @@ void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) { uint32_t *dwords = (uint32_t *)cmd; - int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; + uint32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; uint32_t msg_index; static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h index 990fa1f19c22..109093311984 100644 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h @@ -445,7 +445,7 @@ static inline struct fixed31_32 dc_fixpt_pow(struct fixed31_32 arg1, struct fixe */ static inline int dc_fixpt_floor(struct fixed31_32 arg) { - unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value; + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); if (arg.value >= 0) return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); @@ -459,7 +459,7 @@ static inline int dc_fixpt_floor(struct fixed31_32 arg) */ static inline int dc_fixpt_round(struct fixed31_32 arg) { - unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value; + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); const long long summand = dc_fixpt_half.value; @@ -479,7 +479,7 @@ static inline int dc_fixpt_round(struct fixed31_32 arg) */ static inline int dc_fixpt_ceil(struct fixed31_32 arg) { - unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value; + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); const long long summand = dc_fixpt_one.value - dc_fixpt_epsilon.value; diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h index 38a77fa9b4af..a0f03fb67605 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h @@ -153,6 +153,10 @@ struct embedded_panel_info { uint32_t drr_enabled; uint32_t min_drr_refresh_rate; bool realtek_eDPToLVDS; + uint16_t panel_width_mm; + uint16_t panel_height_mm; + uint16_t fake_edid_size; + const uint8_t *fake_edid; }; struct dc_firmware_info { diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c index 1f225d0d6c44..03d88e78165d 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c @@ -364,7 +364,7 @@ void precompute_pq(void) /* one-time pre-compute dePQ values - only for max pixel value 125 FP16 */ void precompute_de_pq(void) { - int i; + uint32_t i; struct fixed31_32 y; uint32_t begin_index, end_index; @@ -690,7 +690,7 @@ static bool find_software_points( static bool build_custom_gamma_mapping_coefficients_worker( const struct dc_gamma *ramp, struct pixel_gamma_point *coeff, - const struct hw_x_point *coordinates_x, + const struct hw_x_point *hw_coordinates_x, const struct gamma_pixel *axis_x, enum channel_name channel, uint32_t number_of_points) @@ -712,11 +712,11 @@ static bool build_custom_gamma_mapping_coefficients_worker( struct fixed31_32 right_pos; if (channel == CHANNEL_NAME_RED) - coord_x = coordinates_x[i].regamma_y_red; + coord_x = hw_coordinates_x[i].regamma_y_red; else if (channel == CHANNEL_NAME_GREEN) - coord_x = coordinates_x[i].regamma_y_green; + coord_x = hw_coordinates_x[i].regamma_y_green; else - coord_x = coordinates_x[i].regamma_y_blue; + coord_x = hw_coordinates_x[i].regamma_y_blue; if (!find_software_points( ramp, axis_x, coord_x, channel, @@ -783,7 +783,7 @@ static struct fixed31_32 calculate_mapped_value( struct pwl_float_data *rgb, const struct pixel_gamma_point *coeff, enum channel_name channel, - uint32_t max_index) + int32_t max_index) { const struct gamma_point *point; @@ -1425,7 +1425,7 @@ static void apply_lut_1d( uint32_t num_hw_points, struct dc_transfer_func_distributed_points *tf_pts) { - int i = 0; + uint32_t i = 0; int color = 0; struct fixed31_32 *regamma_y; struct fixed31_32 norm_y; @@ -1539,11 +1539,11 @@ static void build_evenly_distributed_points( } static inline void copy_rgb_regamma_to_coordinates_x( - struct hw_x_point *coordinates_x, + struct hw_x_point *hw_coordinates_x, uint32_t hw_points_num, const struct pwl_float_data_ex *rgb_ex) { - struct hw_x_point *coords = coordinates_x; + struct hw_x_point *coords = hw_coordinates_x; uint32_t i = 0; const struct pwl_float_data_ex *rgb_regamma = rgb_ex; @@ -1562,26 +1562,26 @@ static bool calculate_interpolated_hardware_curve( const struct dc_gamma *ramp, struct pixel_gamma_point *coeff128, struct pwl_float_data *rgb_user, - const struct hw_x_point *coordinates_x, + const struct hw_x_point *hw_coordinates_x, const struct gamma_pixel *axis_x, uint32_t number_of_points, struct dc_transfer_func_distributed_points *tf_pts) { const struct pixel_gamma_point *coeff = coeff128; - uint32_t max_entries = 3 - 1; + int32_t max_entries = 3 - 1; uint32_t i = 0; for (i = 0; i < 3; i++) { if (!build_custom_gamma_mapping_coefficients_worker( - ramp, coeff128, coordinates_x, axis_x, i, + ramp, coeff128, hw_coordinates_x, axis_x, i, number_of_points)) return false; } i = 0; - max_entries += ramp->num_entries; + max_entries += (int32_t)ramp->num_entries; /* TODO: float point case */ @@ -1635,7 +1635,7 @@ static bool map_regamma_hw_to_x_user( { /* setup to spare calculated ideal regamma values */ - int i = 0; + uint32_t i = 0; struct hw_x_point *coords = coords_x; const struct pwl_float_data_ex *regamma = rgb_regamma; @@ -1786,14 +1786,14 @@ bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps, if (input_tf->tf == TRANSFER_FUNCTION_PQ) { /* just copy current rgb_regamma into tf_pts */ struct pwl_float_data_ex *curvePt = curve; - int i = 0; + int j = 0; - while (i <= MAX_HW_POINTS) { - tf_pts->red[i] = curvePt->r; - tf_pts->green[i] = curvePt->g; - tf_pts->blue[i] = curvePt->b; + while (j <= MAX_HW_POINTS) { + tf_pts->red[j] = curvePt->r; + tf_pts->green[j] = curvePt->g; + tf_pts->blue[j] = curvePt->b; ++curvePt; - ++i; + ++j; } } else { // clamps to 0-1 diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c index 5cb979c2cf8c..1164fd96b714 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c @@ -44,7 +44,7 @@ void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size, for (i = 0; i < msg_size; i++) { if (i % bytes_per_line == 0) buf[buf_pos++] = '\n'; - sprintf(&buf[buf_pos], "%02X ", msg[i]); + sprintf((char *)&buf[buf_pos], "%02X ", msg[i]); buf_pos += byte_size; } buf[buf_pos++] = '\0'; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h b/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h new file mode 100644 index 000000000000..bf7313df585b --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h @@ -0,0 +1,47 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef MOD_COLOR_TYPES_H_ +#define MOD_COLOR_TYPES_H_ + +enum predefined_gamut_type { + gamut_type_bt709, + gamut_type_bt601, + gamut_type_adobe_rgb, + gamut_type_srgb, + gamut_type_bt2020, + gamut_type_dcip3, + gamut_type_unknown, +}; + +enum predefined_white_point_type { + white_point_type_5000k_horizon, + white_point_type_6500k_noon, + white_point_type_7500k_north_sky, + white_point_type_9300k, + white_point_type_unknown, +}; + +#endif /* MOD_COLOR_TYPES_H_ */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h index ddd64b7e4c04..11b127eb13d8 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h @@ -27,6 +27,7 @@ #define MOD_INFO_PACKET_H_ #include "dm_services.h" +#include "mod_info_packet_types.h" #include "mod_shared.h" //Forward Declarations struct dc_stream_state; @@ -47,14 +48,6 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream, struct dc_info_packet *info_packet); -enum adaptive_sync_type { - ADAPTIVE_SYNC_TYPE_NONE = 0, - ADAPTIVE_SYNC_TYPE_DP = 1, - FREESYNC_TYPE_PCON_IN_WHITELIST = 2, - FREESYNC_TYPE_PCON_NOT_IN_WHITELIST = 3, - ADAPTIVE_SYNC_TYPE_EDP = 4, -}; - enum adaptive_sync_sdp_version { AS_SDP_VER_0 = 0x0, AS_SDP_VER_1 = 0x1, diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h new file mode 100644 index 000000000000..30a5259ef36b --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h @@ -0,0 +1,37 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef MOD_INFO_PACKET_TYPES_H_ +#define MOD_INFO_PACKET_TYPES_H_ + +enum adaptive_sync_type { + ADAPTIVE_SYNC_TYPE_NONE = 0, + ADAPTIVE_SYNC_TYPE_DP = 1, + FREESYNC_TYPE_PCON_IN_WHITELIST = 2, + FREESYNC_TYPE_PCON_NOT_IN_WHITELIST = 3, + ADAPTIVE_SYNC_TYPE_EDP = 4, +}; + +#endif /* MOD_INFO_PACKET_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_power.h b/drivers/gpu/drm/amd/display/modules/inc/mod_power.h new file mode 100644 index 000000000000..f9814cf7bbdb --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_power.h @@ -0,0 +1,417 @@ +/* Copyright (c) 2019 Advanced Micro Devices, Inc. All rights reserved. */ + +#ifndef MODULES_INC_MOD_POWER_H_ +#define MODULES_INC_MOD_POWER_H_ + +#include "dm_services.h" + +struct core_power; + +struct mod_power_init_params { + + bool disable_fractional_pwm; + + /* Use nits based brightness instead of brightness percentage + */ + bool use_nits_based_brightness; + unsigned int panel_min_millinits; + unsigned int panel_max_millinits; + + unsigned int min_backlight_pwm; + unsigned int max_backlight_pwm; + + unsigned int min_abm_backlight; + unsigned int num_backlight_levels; + bool backlight_ramping_override; + unsigned int backlight_ramping_reduction; + unsigned int backlight_ramping_start; + bool def_varibright_enable; + unsigned int def_varibright_level; + unsigned int varibright_level; + unsigned int abm_config_setting; + + bool allow_psr_smu_optimizations; + + bool allow_psr_multi_disp_optimizations; + + bool use_custom_backlight_caps; + unsigned int custom_backlight_caps_config_no; + bool use_linear_backlight_curve; +}; + +struct mod_power { + int dummy; +}; + +/* VariBright settings structure */ +struct varibright_info { + unsigned int level; + bool enable; + bool activate; +}; + +struct mod_power_psr_context { + /* ddc line */ + unsigned int channel; + /* Transmitter id */ + unsigned int transmitter_id; + /* Engine Id is used for Dig Be source select */ + unsigned int engine_id; + /* Controller Id used for Dig Fe source select */ + unsigned int controller_id; + /* Pcie or Uniphy */ + unsigned int phy_type; + /* Physical PHY Id used by SMU interpretation */ + unsigned int smu_phy_id; + /* Vertical total pixels from crtc timing. + * This is used for static screen detection. + * ie. If we want to detect half a frame, + * we use this to determine the hyst lines. + */ + unsigned int crtc_timing_vertical_total; + /* PSR supported from panel capabilities and + * current display configuration + */ + bool psr_supported_display_config; + /* Whether fast link training is supported by the panel */ + bool psr_exit_link_training_required; + /* If RFB setup time is greater than the total VBLANK time, + * it is not possible for the sink to capture the video frame + * in the same frame the SDP is sent. In this case, + * the frame capture indication bit should be set and an extra + * static frame should be transmitted to the sink. + */ + bool psr_frame_capture_indication_req; + /* Set the last possible line SDP may be transmitted without violating + * the RFB setup time or entering the active video frame. + */ + unsigned int sdp_transmit_line_num_deadline; + /* The VSync rate in Hz used to calculate the + * step size for smooth brightness feature + */ + unsigned int vsync_rate_hz; + unsigned int skip_psr_wait_for_pll_lock; + unsigned int number_of_controllers; + /* Unused, for future use. To indicate that first changed frame from + * state3 shouldn't result in psr_inactive, but rather to perform + * an automatic single frame rfb_update. + */ + bool rfb_update_auto_en; + /* Number of frame before entering static screen */ + unsigned int timehyst_frames; + /* Partial frames before entering static screen */ + unsigned int hyst_lines; + /* # of repeated AUX transaction attempts to make before + * indicating failure to the driver + */ + unsigned int aux_repeats; + /* Controls hw blocks to power down during PSR active state */ + unsigned int psr_level; + /* Controls additional delay after remote frame capture before + * continuing powerd own + */ + unsigned int frame_delay; + bool allow_smu_optimizations; + bool allow_multi_disp_optimizations; + unsigned int line_time_in_us; + /* Panel self refresh 2 selective update granularity required */ + bool su_granularity_required; + /* psr2 selective update y granularity capability */ + uint8_t su_y_granularity; + uint8_t rate_control_caps; + bool os_request_force_ffu; +}; + +enum psr_event { + psr_event_invalid = 0x0, + psr_event_vsync = 0x1, + psr_event_full_screen = 0x2, + psr_event_defer_enable = 0x4, + psr_event_hw_programming = 0x8, + psr_event_test_harness_enable_psr = 0x10, + psr_event_test_harness_disable_psr = 0x20, + psr_event_mpo_video_selective_update = 0x40, + psr_event_edp_panel_off_disable_psr = 0x80, + psr_event_dynamic_display_switch = 0x100, + psr_event_big_screen_video = 0x200, + psr_event_dds_defer_stream_enable = 0x800, + psr_event_dynamic_link_rate_control = 0x1000, + psr_event_vrr_transition = 0x2000, + psr_event_pause = 0x4000, + psr_event_immediate_flip = 0x8000, + psr_event_os_request_disable = 0x10000, + psr_event_os_request_force_ffu = 0x20000, + psr_event_os_override_hold = 0x40000, + psr_event_crc_window_active = 0x80000, +}; + +enum replay_event { + replay_event_invalid = 0x0, + replay_event_vsync = 0x1, + replay_event_full_screen = 0x2, + replay_event_mpo_video_selective_update = 0x4, + replay_event_big_screen_video = 0x8, + replay_event_hw_programming = 0x10, + replay_event_edp_panel_off_disable_psr = 0x20, + replay_event_general_ui = 0x40, + replay_event_vrr = 0x80, + replay_event_prepare_vtotal = 0x100, + replay_event_test_harness_enable_replay = 0x200, + replay_event_test_harness_disable_replay = 0x400, + replay_event_test_harness_ultra_sleep = 0x800, + replay_event_immediate_flip = 0x1000, + replay_event_vrr_transition = 0x2000, + replay_event_pause = 0x4000, + replay_event_disable_replay_while_DPMS = 0x8000, + replay_event_test_harness_mode = 0x10000, + replay_event_cursor_updating = 0x20000, + replay_event_sleep_resume = 0x40000, + replay_event_disable_in_AC = 0x80000, + replay_event_disable_replay_while_detect_display = 0x100000, + replay_event_disable_replay_while_switching_mux = 0x400000, + replay_event_infopacket = 0x800000, + replay_event_os_request_disable = 0x1000000, + replay_event_os_request_force_ffu = 0x2000000, + replay_event_os_override_hold = 0x4000000, + replay_event_crc_window_active = 0x8000000, +}; + +enum replay_enable_option { + pr_enable_option_static_screen = 0x1, + pr_enable_option_mpo_video = 0x2, + pr_enable_option_full_screen_video = 0x4, + pr_enable_option_general_ui = 0x8, + pr_enable_option_full_screen = 0x10, + pr_enable_option_static_screen_coasting = 0x10000, + pr_enable_option_mpo_video_coasting = 0x20000, + pr_enable_option_full_screen_video_coasting = 0x40000, + pr_enable_option_full_screen_coasting = 0x100000, +}; + +struct mod_power *mod_power_create(struct dc *dc, + struct mod_power_init_params *init_params, + unsigned int edp_num); + +void mod_power_destroy(struct mod_power *mod_power); + +bool mod_power_hw_init(struct mod_power *mod_power); + +bool mod_power_add_stream(struct mod_power *mod_power, + struct dc_stream_state *stream, struct psr_caps *caps); + +bool mod_power_remove_stream(struct mod_power *mod_power, + const struct dc_stream_state *stream); + +bool mod_power_replace_stream(struct mod_power *mod_power, + const struct dc_stream_state *current_stream, + struct dc_stream_state *new_stream, + struct psr_caps *new_caps); + +bool mod_power_set_backlight_nits(struct mod_power *mod_power, + struct dc_stream_state *streams, + unsigned int backlight_millinit, + unsigned int transition_time_millisec, + bool skip_aux, + bool is_hdr); + +bool mod_power_set_backlight_percent(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent, + unsigned int transition_time_millisec, + bool is_hdr); + +void mod_power_update_backlight(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent); + +void mod_power_update_backlight_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit); + +bool mod_power_get_backlight_pwm(struct mod_power *mod_power, + unsigned int *backlight_pwm, + unsigned int inst); + +bool mod_power_get_backlight_nits(struct mod_power *mod_power, + unsigned int *backlight_millinit, + unsigned int inst); + +bool mod_power_get_backlight_percent(struct mod_power *mod_power, + unsigned int *backlight_millipercent, + unsigned int inst); + +bool mod_power_get_hw_target_backlight_pwm_nits( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millinit, + unsigned int inst); + +bool mod_power_get_hw_target_backlight_pwm_percent( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millipercent, + unsigned int inst); + +bool mod_power_get_hw_target_backlight_pwm( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_u16_16); + +bool mod_power_get_hw_backlight_pwm( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight); + +bool mod_power_get_hw_backlight_pwm_nits( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millinit, + unsigned int inst); + +bool mod_power_get_hw_backlight_aux_nits( + struct mod_power *mod_power, + struct dc_stream_state **streams, int num_streams, + unsigned int *backlight_millinit_avg, + unsigned int *backlight_millinit_peak); + +bool mod_power_get_hw_backlight_pwm_percent( + struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millipercent, + unsigned int inst); + +void mod_power_initialize_backlight_caps + (struct mod_power *mod_power); + +bool mod_power_get_panel_backlight_boundaries + (struct mod_power *mod_power, + unsigned int *out_min_backlight, + unsigned int *out_max_backlight, + unsigned int *out_ac_backlight_percent, + unsigned int *out_dc_backlight_percent, + unsigned int inst); + +bool mod_power_set_smooth_brightness(struct mod_power *mod_power, + bool enable_brightness, + unsigned int inst); + +bool mod_power_notify_mode_change(struct mod_power *mod_power, + const struct dc_stream_state *stream, + bool is_hdr); + +bool mod_power_get_varibright_level(struct mod_power *mod_power, + unsigned int *varibright_level); + +bool mod_power_get_varibright_hw_level(struct mod_power *mod_power, + unsigned int *varibright_level); + +bool mod_power_get_varibright_default_level(struct mod_power *mod_power, + unsigned int *varibright_level); + +bool mod_power_get_varibright_enable(struct mod_power *mod_power, + bool *varibright_enable); + +bool mod_power_varibright_activate(struct mod_power *mod_power, + bool activate, struct dc_stream_update *stream_update); + +bool mod_power_varibright_feature_enable(struct mod_power *mod_power, + bool enable, struct dc_stream_update *stream_update); + + +bool mod_power_varibright_set_level(struct mod_power *mod_power, + unsigned int level, struct dc_stream_update *stream_update); + +bool mod_power_varibright_set_hw_level(struct mod_power *mod_power, + unsigned int level, struct dc_stream_update *stream_update); + +bool mod_power_is_abm_active(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int inst); + + +bool mod_power_set_psr_event(struct mod_power *mod_power, + struct dc_stream_state *stream, bool set_event, + enum psr_event event, bool wait); + +bool mod_power_get_psr_event(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int *active_psr_events); + +bool mod_power_get_psr_state(struct mod_power *mod_power, + const struct dc_stream_state *stream, + enum dc_psr_state *state); + +bool mod_power_get_psr_enabled_status(struct mod_power *mod_power, + const struct dc_stream_state *stream, + bool *psr_enabled); + +bool mod_power_set_replay_event(struct mod_power *mod_power, + struct dc_stream_state *stream, bool set_event, + enum replay_event event, bool wait_for_disable); + +bool mod_power_get_replay_event(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int *active_replay_events); + +bool mod_power_get_replay_active_status(const struct dc_stream_state *stream, + bool *replay_active); + +bool mod_power_replay_set_coasting_vtotal(struct mod_power *mod_power, + const struct dc_stream_state *stream, + uint32_t coasting_vtotal, uint16_t frame_skip_number); + +void mod_power_replay_residency(const struct dc_stream_state *stream, + unsigned int *residency, const bool is_start, const bool is_alpm); + +bool mod_power_replay_set_power_opt_and_coasting_vtotal(struct mod_power *mod_power, + const struct dc_stream_state *stream, unsigned int active_replay_events, uint32_t coasting_vtotal, + bool is_ultra_sleep_mode, uint16_t frame_skip_number); + +void mod_power_replay_set_timing_sync_supported(struct mod_power *mod_power, + const struct dc_stream_state *stream); + +void mod_power_replay_disabled_adaptive_sync_sdp(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool force_disabled); + +void mod_power_replay_disabled_desync_error_detection(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool force_disabled); +void mod_power_set_low_rr_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool low_rr_supported); + +void mod_power_set_video_conferencing_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool video_conferencing_activate); + +void mod_power_set_live_capture_with_cvt_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool live_capture_with_cvt_activate); + +void mod_power_set_replay_continuously_resync(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool enable); + +void mod_power_set_coasting_vtotal_without_frame_update(struct mod_power *mod_power, + const struct dc_stream_state *stream, uint32_t coasting_vtotal); + + + +void mod_power_psr_residency(struct mod_power *mod_power, + const struct dc_stream_state *stream, + unsigned int *residency, + const uint8_t mode); +bool mod_power_psr_get_active_psr_events(struct mod_power *mod_power, + const struct dc_stream_state *stream, unsigned int *active_psr_events); +bool mod_power_psr_set_sink_vtotal_in_psr_active(struct mod_power *mod_power, + const struct dc_stream_state *stream, + uint16_t psr_vtotal_idle, + uint16_t psr_vtotal_su); + + + +bool mod_power_backlight_percent_to_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent, + unsigned int *backlight_millinit); +bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit, + unsigned int *backlight_millipercent); + +#endif /* MODULES_INC_MOD_POWER_H_ */ diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c index 00473c6284d5..55c7250f18d8 100644 --- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c +++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c @@ -246,7 +246,7 @@ void set_vsc_packet_colorimetry_data( break; } - info_packet->sb[16] = (pixelEncoding << 4) | colorimetryFormat; + info_packet->sb[16] = (uint8_t)((pixelEncoding << 4) | colorimetryFormat); /* Set color depth */ switch (stream->timing.display_color_depth) { diff --git a/drivers/gpu/drm/amd/display/modules/power/Makefile b/drivers/gpu/drm/amd/display/modules/power/Makefile index 9d1b22d35ece..3000f392bdbc 100644 --- a/drivers/gpu/drm/amd/display/modules/power/Makefile +++ b/drivers/gpu/drm/amd/display/modules/power/Makefile @@ -23,9 +23,9 @@ # Makefile for the 'power' sub-module of DAL. # -MOD_POWER = power_helpers.o +MOD_POWER = power_helpers.o power.o power_abm.o power_psr.o power_replay.o AMD_DAL_MOD_POWER = $(addprefix $(AMDDALPATH)/modules/power/,$(MOD_POWER)) #$(info ************ DAL POWER MODULE MAKEFILE ************) -AMD_DISPLAY_FILES += $(AMD_DAL_MOD_POWER) +AMD_DISPLAY_FILES += $(AMD_DAL_MOD_POWER) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c new file mode 100644 index 000000000000..1dd65bdf8cc9 --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/power/power.c @@ -0,0 +1,498 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "dc.h" +#include "mod_power.h" +#include "core_types.h" +#include "dmcu.h" +#include "abm.h" +#include "power_helpers.h" +#include "dce/dmub_psr.h" +#include "dal_asic_id.h" +#include "link_service.h" +#include + +#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ +#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */ + +#define MOD_POWER_MAX_CONCURRENT_STREAMS 32 +#define SMOOTH_BRIGHTNESS_ADJUSTMENT_TIME_IN_MS 500 +#define LOW_REFRESH_RATE_DURATION_US_UPPER_BOUND 25000 + +/* If system or panel does not report some sort of brightness percent to nits + * mapping, we will use following default values so backlight control using + * nits based interfaces will still work, but might not describe panel + * correctly. In this case percentage based backlight control should ideally + * be used. + * Min = 5 nits + * Max = 300 nits + */ + +static const unsigned int pwr_default_min_brightness_millinits = 1000; +static const unsigned int pwr_default_sdr_brightness_millinits = 270000; + +static const unsigned int default_ac_backlight_percent = 100; +static const unsigned int default_dc_backlight_percent = 70; + +#define MOD_POWER_TO_CORE(mod_power)\ + container_of(mod_power, struct core_power, mod_public) + +/* Given a specific dc_stream* this function finds its equivalent + * on the core_freesync->map and returns the corresponding index + */ +unsigned int map_index_from_stream(struct core_power *core_power, + const struct dc_stream_state *stream) +{ + unsigned int index = 0; + + for (index = 0; index < core_power->num_entities; index++) { + if (core_power->map[index].stream == stream) + return index; + } + /* Could not find stream requested, this is not trivial, fix when hit*/ + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "map index from stream: ERROR: core_power=%p stream=%p", + core_power, + stream); + ASSERT(false); + /* We come here only when we can't map stream index. + * In good cases, this would happen when we attempt to change + * brightness before stream creation, in which case we create a + * dummy stream with index 0. + * With external monitor connected, the index passed from this return + * is 1. Passing anything greater than 0 from here would always point + * to bad memory. + */ + return 0; +} + +bool mod_power_hw_init(struct mod_power *mod_power) +{ + /* Call backlight initialization */ + return mod_power_hw_init_backlight(mod_power); + + /* Future: Add other HW init here */ +} + +struct mod_power *mod_power_create(struct dc *dc, + struct mod_power_init_params *init_params, + unsigned int edp_num) +{ + struct core_power *core_power = NULL; + int i = 0; + unsigned int abm_max_config = 0; + unsigned int inst = 0; + bool is_brightness_range_valid = false; + + if (dc == NULL) + goto fail_dc_null; + + core_power = kzalloc(sizeof(struct core_power), GFP_KERNEL); + + if (core_power == NULL) + goto fail_alloc_context; + + core_power->edp_num = edp_num; + core_power->map = kzalloc(sizeof(struct power_entity) * MOD_POWER_MAX_CONCURRENT_STREAMS, + GFP_KERNEL); + + if (core_power->map == NULL) + goto fail_alloc_map; + + for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) { + core_power->map[i].stream = NULL; + } + + for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) { + core_power->map[i].psr_context = + kzalloc(sizeof(struct mod_power_psr_context), + GFP_KERNEL); + if (core_power->map[i].psr_context == NULL) + goto fail_construct; + } + + core_power->psr_smu_optimizations_support = init_params->allow_psr_smu_optimizations; + core_power->multi_disp_optimizations_support = init_params->allow_psr_multi_disp_optimizations; + + for (inst = 0; inst < edp_num; inst++) { + core_power->bl_prop[inst].min_abm_backlight = + init_params[inst].min_abm_backlight; + core_power->bl_prop[inst].disable_fractional_pwm = + init_params[inst].disable_fractional_pwm; + core_power->bl_prop[inst].use_linear_backlight_curve = + init_params[inst].use_linear_backlight_curve; + core_power->bl_prop[inst].use_nits_based_brightness = + init_params[inst].use_nits_based_brightness; + core_power->bl_prop[inst].backlight_ramping_override = + init_params[inst].backlight_ramping_override; + core_power->bl_prop[inst].backlight_ramping_reduction = + init_params[inst].backlight_ramping_reduction; + core_power->bl_prop[inst].backlight_ramping_start = + init_params[inst].backlight_ramping_start; + core_power->bl_prop[inst].use_custom_backlight_caps = + init_params[inst].use_custom_backlight_caps; + core_power->bl_prop[inst].custom_backlight_caps_config_no = + init_params[inst].custom_backlight_caps_config_no; + + // Do not allow less than 101 backlight levels + if (init_params[inst].num_backlight_levels < 101) + core_power->bl_prop[inst].num_backlight_levels = 101; + else + core_power->bl_prop[inst].num_backlight_levels = + init_params[inst].num_backlight_levels; + + core_power->bl_prop[inst].backlight_lut = (unsigned int *) + (kzalloc(sizeof(unsigned int) * + core_power->bl_prop[inst].num_backlight_levels, GFP_KERNEL)); + if (core_power->bl_prop[inst].backlight_lut == NULL) + goto fail_alloc_backlight_array; + } + + core_power->varibright_prop.varibright_active = false; + + core_power->varibright_prop.varibright_user_enable = + init_params->def_varibright_enable; + + // Table of ABM levels here is 1-4, but level 0 also exists as 'off' + if (init_params->varibright_level <= abm_defines_max_level) { + core_power->varibright_prop.varibright_level = + init_params->varibright_level; + + } else { + core_power->varibright_prop.varibright_level = 3; + } + if (init_params->def_varibright_level <= abm_defines_max_level) { + core_power->varibright_prop.def_varibright_level = + init_params->def_varibright_level; + } else { + core_power->varibright_prop.def_varibright_level = 3; + } + + // ABM used to contain 4 different configs. There is only 3 since ABM 2.3. + if ((dc->res_pool->dmcu != NULL) && (dc->res_pool->dmcu->dmcu_version.abm_version < 0x23)) + abm_max_config = 4; + else + abm_max_config = 3; + + if (init_params->abm_config_setting < abm_max_config) + core_power->varibright_prop.varibright_config_setting = + init_params->abm_config_setting; + else + core_power->varibright_prop.varibright_config_setting = 0; + + for (inst = 0; inst < edp_num; inst++) { + core_power->bl_prop[inst].backlight_lut[0] = init_params[inst].min_backlight_pwm; + core_power->bl_prop[inst].backlight_lut[ + core_power->bl_prop[inst].num_backlight_levels-1] = + init_params[inst].max_backlight_pwm; + core_power->bl_prop[inst].min_backlight_pwm = init_params[inst].min_backlight_pwm; + core_power->bl_prop[inst].max_backlight_pwm = init_params[inst].max_backlight_pwm; + core_power->bl_prop[inst].ac_backlight_percent = + default_ac_backlight_percent; + core_power->bl_prop[inst].dc_backlight_percent = + default_dc_backlight_percent; + core_power->bl_prop[inst].backlight_caps_valid = false; + + if (core_power->bl_prop[inst].use_nits_based_brightness) { + core_power->bl_prop[inst].min_brightness_millinits = + init_params[inst].panel_min_millinits; + core_power->bl_prop[inst].max_brightness_millinits = + init_params[inst].panel_max_millinits; + } else { + + core_power->bl_prop[inst].min_brightness_millinits = + pwr_default_min_brightness_millinits; + core_power->bl_prop[inst].max_brightness_millinits = + pwr_default_sdr_brightness_millinits; + } + + core_power->bl_prop[inst].backlight_range = + core_power->bl_prop[inst].max_backlight_pwm- + core_power->bl_prop[inst].min_backlight_pwm; + + core_power->bl_prop[inst].nits_range = + core_power->bl_prop[inst].max_brightness_millinits - + core_power->bl_prop[inst].min_brightness_millinits; + + core_power->bl_state[inst].smooth_brightness_enabled = true; + } + + /* Check if at least 1 instance in core_power is populated before failing */ + for (inst = 0; inst < edp_num; inst++) { + if (core_power->bl_prop[inst].nits_range != 0 && core_power->bl_prop[inst].backlight_range != 0) { + is_brightness_range_valid = true; + break; + } + + } + if (!is_brightness_range_valid) + goto fail_bad_brightness_range; + + core_power->num_entities = 0; + + core_power->dc = dc; + for (inst = 0; inst < edp_num; inst++) { + initialize_backlight_caps(core_power, inst); + core_power->bl_state[inst].backlight_millipercent = + core_power->bl_prop[inst].dc_backlight_percent * 1000; + core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm(core_power, + core_power->bl_state[inst].backlight_millipercent, inst); + core_power->bl_state[inst].backlight_millinit = backlight_millipercent_to_millinit(core_power, + core_power->bl_state[inst].backlight_millipercent, inst); + } + + return &core_power->mod_public; + +fail_bad_brightness_range: +fail_alloc_backlight_array: + for (inst = 0; inst < edp_num; inst++) + if (core_power->bl_prop[inst].backlight_lut) + kfree(core_power->bl_prop[inst].backlight_lut); +fail_construct: + for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) { + if (core_power->map[i].psr_context) + kfree(core_power->map[i].psr_context); + } + kfree(core_power->map); + +fail_alloc_map: + kfree(core_power); + +fail_alloc_context: +fail_dc_null: + return NULL; +} + +void mod_power_destroy(struct mod_power *mod_power) +{ + if (mod_power != NULL) { + unsigned int i; + struct core_power *core_power = + MOD_POWER_TO_CORE(mod_power); + + for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) + if (core_power->map[i].psr_context) + kfree(core_power->map[i].psr_context); + + for (i = 0; i < core_power->num_entities; i++) + if (core_power->map[i].stream) + dc_stream_release(core_power->map[i].stream); + + kfree(core_power->map); + + for (i = 0; i < MAX_NUM_EDP; i++) + if (core_power->bl_prop[i].backlight_lut) + kfree(core_power->bl_prop[i].backlight_lut); + + kfree(core_power); + } +} + +bool mod_power_add_stream(struct mod_power *mod_power, + struct dc_stream_state *stream, struct psr_caps *caps) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities < MOD_POWER_MAX_CONCURRENT_STREAMS) { + dc_stream_retain(stream); + + core_power->map[core_power->num_entities].stream = stream; + core_power->map[core_power->num_entities].caps = caps; + + // initialize cached PSR params to something "safe" (something that is + // consistent with disabled PSR state) + core_power->map[core_power->num_entities].psr_enabled = 0; + core_power->map[core_power->num_entities].psr_events = psr_event_vsync; + core_power->map[core_power->num_entities].psr_power_opt = 0; + core_power->num_entities++; + return true; + } + + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power: add_stream: ERROR: stream=%p num_entities=%u >= MOD_POWER_MAX_CONCURRENT_STREAMS", + stream, + core_power->num_entities); + + return false; +} + +bool mod_power_remove_stream(struct mod_power *mod_power, + const struct dc_stream_state *stream) +{ + unsigned int i = 0; + struct core_power *core_power = NULL; + unsigned int index = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) { + /* trying to remove a stream a second time or have not added yet */ + BREAK_TO_DEBUGGER(); + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power: remove_stream: ERROR: num_entities=0 stream=%p", + stream); + return false; + } + + index = map_index_from_stream(core_power, stream); + + if (index >= core_power->num_entities) { + /* trying to remove a stream a second time or have not added yet */ + BREAK_TO_DEBUGGER(); + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power: remove_stream: ERROR: index=%u >= num_entities=%u stream=%p", + index, + core_power->num_entities, + stream); + return false; + } + + dc_stream_release(core_power->map[index].stream); + core_power->map[index].stream = NULL; + /* To remove this entity, shift everything after down */ + for (i = index; i < core_power->num_entities - 1; i++) { + core_power->map[i].stream = core_power->map[i + 1].stream; + core_power->map[i].caps = core_power->map[i + 1].caps; + + // copy over cached parameters in case they map to PSR capable display + core_power->map[i].psr_enabled = core_power->map[i + 1].psr_enabled; + core_power->map[i].psr_events = core_power->map[i + 1].psr_events; + core_power->map[i].psr_power_opt = core_power->map[i + 1].psr_power_opt; + + memcpy(core_power->map[i].psr_context, core_power->map[i + 1].psr_context, sizeof(struct mod_power_psr_context)); + memset(core_power->map[i + 1].psr_context, 0, sizeof(struct mod_power_psr_context)); + } + core_power->num_entities--; + + return true; +} + +/* + * Replace_stream should be used when there is a mode set for existing + * display target with a valid stream. In this case might need to retain + * cached PSR state (events, power opt, en/dis) if we are dealing with PSR + * capable display. If mod_power_remove and mod_power_add are used instead, + * then stream may be assigned to a different slot and may end up with + * wrong cached PSR state. It is hard to tell which PSR events should + * persist through mode set or what psr_events should be initialized to, so + * it might be better just to retain them all. + */ +bool mod_power_replace_stream(struct mod_power *mod_power, + const struct dc_stream_state *current_stream, + struct dc_stream_state *new_stream, + struct psr_caps *new_caps) +{ + struct core_power *core_power = NULL; + unsigned int index = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) { + /* no streams exist in the table yet */ + BREAK_TO_DEBUGGER(); + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power: replace_stream: ERROR: num_entities=0 stream=%p", + current_stream); + return false; + } + + index = map_index_from_stream(core_power, current_stream); + + if (index >= core_power->num_entities) { + /* trying to replace a non-existent stream */ + BREAK_TO_DEBUGGER(); + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power: replace_stream: ERROR: index=%u >= num_entities=%u stream=%p", + index, + core_power->num_entities, + current_stream); + return false; + } + + dc_stream_release(core_power->map[index].stream); + dc_stream_retain(new_stream); + core_power->map[index].stream = new_stream; + core_power->map[index].caps = new_caps; + memset(core_power->map[index].psr_context, 0, sizeof(struct mod_power_psr_context)); + + return true; +} +bool mod_power_notify_mode_change(struct mod_power *mod_power, + const struct dc_stream_state *stream, + bool is_hdr) +{ + unsigned int stream_index = 0; + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + struct dc *dc = NULL; + unsigned int panel_inst = 0; + + if ((mod_power == NULL) || (stream == NULL)) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + if (stream_index >= core_power->num_entities) + return false; + + dc = core_power->dc; + link = dc_stream_get_link(stream); + + if (link != NULL && dc_get_edp_link_panel_inst(dc, link, &panel_inst)) { + ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); + uint8_t aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; + + mod_power_update_backlight_on_mode_change(core_power, link, panel_inst, aux_inst, is_hdr); + + /* Handle PSR notification */ + mod_power_psr_notify_mode_change(mod_power, stream, link, stream_index); + + /* Handle Replay notification */ + mod_power_replay_notify_mode_change(mod_power, dc, link, stream, stream_index); + } + + return true; +} diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c new file mode 100644 index 000000000000..b94dbb9e64a7 --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c @@ -0,0 +1,2062 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "dc.h" +#include "mod_power.h" +#include "core_types.h" +#include "dmcu.h" +#include "abm.h" +#include "power_helpers.h" +#include "dce/dmub_psr.h" +#include "dal_asic_id.h" +#include "link_service.h" +#include + +#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ +#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */ + +#define DIV_ROUNDUP(a, b) (((a)+((b)/2))/(b)) +#define bswap16_based_on_endian(big_endian, value) \ + ((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value)) + +/* Possible Min Reduction config from least aggressive to most aggressive + * 0 1 2 3 4 5 6 7 8 9 10 11 12 + * 100 98.0 94.1 94.1 85.1 80.3 75.3 69.4 60.0 57.6 50.2 49.8 40.0 % + */ +static const unsigned char min_reduction_table[13] = { +0xff, 0xfa, 0xf0, 0xf0, 0xd9, 0xcd, 0xc0, 0xb1, 0x99, 0x93, 0x80, 0x82, 0x66}; + +/* Possible Max Reduction configs from least aggressive to most aggressive + * 0 1 2 3 4 5 6 7 8 9 10 11 12 + * 96.1 89.8 85.1 80.3 69.4 64.7 64.7 50.2 39.6 30.2 30.2 30.2 19.6 % + */ +static const unsigned char max_reduction_table[13] = { +0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32}; + +/* Possible ABM 2.2 Min Reduction configs from least aggressive to most aggressive + * 0 1 2 3 4 5 6 7 8 9 10 11 12 + * 100 100 100 100 100 100 100 100 100 92.2 83.1 75.3 75.3 % + */ +static const unsigned char min_reduction_table_v_2_2[13] = { +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xd4, 0xc0, 0xc0}; + +/* Possible ABM 2.2 Max Reduction configs from least aggressive to most aggressive + * 0 1 2 3 4 5 6 7 8 9 10 11 12 + * 96.1 89.8 74.9 69.4 64.7 52.2 48.6 39.6 30.2 25.1 19.6 12.5 12.5 % + */ +static const unsigned char max_reduction_table_v_2_2[13] = { +0xf5, 0xe5, 0xbf, 0xb1, 0xa5, 0x85, 0x7c, 0x65, 0x4d, 0x40, 0x32, 0x20, 0x20}; + +/* Predefined ABM configuration sets. We may have different configuration sets + * in order to satisfy different power/quality requirements. + */ +static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_level] = { +/* ABM Level 1, ABM Level 2, ABM Level 3, ABM Level 4 */ +{ 2, 5, 7, 8 }, /* Default - Medium aggressiveness */ +{ 2, 5, 8, 11 }, /* Alt #1 - Increased aggressiveness */ +{ 0, 2, 4, 8 }, /* Alt #2 - Minimal aggressiveness */ +{ 3, 6, 10, 12 }, /* Alt #3 - Super aggressiveness */ +}; + +struct abm_parameters { + unsigned char min_reduction; + unsigned char max_reduction; + unsigned char bright_pos_gain; + unsigned char dark_pos_gain; + unsigned char brightness_gain; + unsigned char contrast_factor; + unsigned char deviation_gain; + unsigned char min_knee; + unsigned char max_knee; + unsigned short blRampReduction; + unsigned short blRampStart; +}; + +static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = { +// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart + {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xf777, 0xcccc}, + {0xde, 0x85, 0x20, 0x00, 0xe0, 0x90, 0xa8, 0x40, 0xc8, 0xf777, 0xcccc}, + {0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xeeee, 0x9999}, + {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xe333, 0xb333}, +}; + +static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = { +// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart + {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, + {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, + {0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, + {0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, +}; + +static const struct abm_parameters abm_settings_config2[abm_defines_max_level] = { +// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart + {0xf0, 0xbf, 0x20, 0x00, 0x88, 0x99, 0xb3, 0x40, 0xe0, 0x0000, 0xcccc}, + {0xd8, 0x85, 0x20, 0x00, 0x70, 0x90, 0xa8, 0x40, 0xc8, 0x0700, 0xb333}, + {0xb8, 0x58, 0x20, 0x00, 0x64, 0x88, 0x78, 0x70, 0xa0, 0x7000, 0x9999}, + {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xc333, 0xb333}, +}; + +static const struct abm_parameters * const abm_settings[] = { + abm_settings_config0, + abm_settings_config1, + abm_settings_config2, +}; + +static const struct dm_bl_data_point custom_backlight_curve0[] = { + {2, 14}, {4, 16}, {6, 18}, {8, 21}, {10, 23}, {12, 26}, {14, 29}, {16, 32}, {18, 35}, + {20, 38}, {22, 41}, {24, 44}, {26, 48}, {28, 52}, {30, 55}, {32, 59}, {34, 62}, + {36, 67}, {38, 71}, {40, 75}, {42, 80}, {44, 84}, {46, 88}, {48, 93}, {50, 98}, + {52, 103}, {54, 108}, {56, 113}, {58, 118}, {60, 123}, {62, 129}, {64, 135}, {66, 140}, + {68, 146}, {70, 152}, {72, 158}, {74, 164}, {76, 171}, {78, 177}, {80, 183}, {82, 190}, + {84, 197}, {86, 204}, {88, 211}, {90, 218}, {92, 225}, {94, 232}, {96, 240}, {98, 247}}; + +struct custom_backlight_profile { + uint8_t ac_level_percentage; + uint8_t dc_level_percentage; + uint8_t min_input_signal; + uint8_t max_input_signal; + uint8_t num_data_points; + const struct dm_bl_data_point *data_points; +}; + +static const struct custom_backlight_profile custom_backlight_profiles[] = { + {100, 32, 12, 255, ARRAY_SIZE(custom_backlight_curve0), custom_backlight_curve0}, +}; + +#define NUM_AMBI_LEVEL 5 +#define NUM_AGGR_LEVEL 4 +#define NUM_POWER_FN_SEGS 8 +#define NUM_BL_CURVE_SEGS 16 +#define IRAM_SIZE 256 + +#define IRAM_RESERVE_AREA_START_V2 0xF0 // reserve 0xF0~0xF6 are write by DMCU only +#define IRAM_RESERVE_AREA_END_V2 0xF6 // reserve 0xF0~0xF6 are write by DMCU only + +#define IRAM_RESERVE_AREA_START_V2_2 0xF0 // reserve 0xF0~0xFF are write by DMCU only +#define IRAM_RESERVE_AREA_END_V2_2 0xFF // reserve 0xF0~0xFF are write by DMCU only + +#pragma pack(push, 1) +/* NOTE: iRAM is 256B in size */ +struct iram_table_v_2 { + /* flags */ + uint16_t min_abm_backlight; /* 0x00 U16 */ + + /* parameters for ABM2.0 algorithm */ + uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */ + uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */ + uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */ + uint8_t bright_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */ + uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x52 U2.6 */ + uint8_t dark_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x66 U2.6 */ + uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x7a U0.8 */ + uint8_t deviation_gain; /* 0x7f U0.8 */ + + /* parameters for crgb conversion */ + uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */ + uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */ + uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */ + + /* parameters for custom curve */ + /* thresholds for brightness --> backlight */ + uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */ + /* offsets for brightness --> backlight */ + uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */ + + /* For reading PSR State directly from IRAM */ + uint8_t psr_state; /* 0xf0 */ + uint8_t dmcu_mcp_interface_version; /* 0xf1 */ + uint8_t dmcu_abm_feature_version; /* 0xf2 */ + uint8_t dmcu_psr_feature_version; /* 0xf3 */ + uint16_t dmcu_version; /* 0xf4 */ + uint8_t dmcu_state; /* 0xf6 */ + + uint16_t blRampReduction; /* 0xf7 */ + uint16_t blRampStart; /* 0xf9 */ + uint8_t dummy5; /* 0xfb */ + uint8_t dummy6; /* 0xfc */ + uint8_t dummy7; /* 0xfd */ + uint8_t dummy8; /* 0xfe */ + uint8_t dummy9; /* 0xff */ +}; + +struct iram_table_v_2_2 { + /* flags */ + uint16_t flags; /* 0x00 U16 */ + + /* parameters for ABM2.2 algorithm */ + uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */ + uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */ + uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */ + uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */ + uint8_t hybrid_factor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */ + uint8_t contrast_factor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */ + uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a U0.8 */ + uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x5e U0.8 */ + uint8_t min_knee[NUM_AGGR_LEVEL]; /* 0x63 U0.8 */ + uint8_t max_knee[NUM_AGGR_LEVEL]; /* 0x67 U0.8 */ + uint16_t min_abm_backlight; /* 0x6b U16 */ + uint8_t pad[19]; /* 0x6d U0.8 */ + + /* parameters for crgb conversion */ + uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */ + uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */ + uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */ + + /* parameters for custom curve */ + /* thresholds for brightness --> backlight */ + uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */ + /* offsets for brightness --> backlight */ + uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */ + + /* For reading PSR State directly from IRAM */ + uint8_t psr_state; /* 0xf0 */ + uint8_t dmcu_mcp_interface_version; /* 0xf1 */ + uint8_t dmcu_abm_feature_version; /* 0xf2 */ + uint8_t dmcu_psr_feature_version; /* 0xf3 */ + uint16_t dmcu_version; /* 0xf4 */ + uint8_t dmcu_state; /* 0xf6 */ + + uint8_t dummy1; /* 0xf7 */ + uint8_t dummy2; /* 0xf8 */ + uint8_t dummy3; /* 0xf9 */ + uint8_t dummy4; /* 0xfa */ + uint8_t dummy5; /* 0xfb */ + uint8_t dummy6; /* 0xfc */ + uint8_t dummy7; /* 0xfd */ + uint8_t dummy8; /* 0xfe */ + uint8_t dummy9; /* 0xff */ +}; +#pragma pack(pop) + +#define MOD_POWER_MAX_CONCURRENT_STREAMS 32 +#define SMOOTH_BRIGHTNESS_ADJUSTMENT_TIME_IN_MS 500 + +/* If system or panel does not report some sort of brightness percent to nits + * mapping, we will use following default values so backlight control using + * nits based interfaces will still work, but might not describe panel + * correctly. In this case percentage based backlight control should ideally + * be used. + * Min = 5 nits + * Max = 300 nits + */ + +#define MOD_POWER_TO_CORE(mod_power)\ + container_of(mod_power, struct core_power, mod_public) + +static uint16_t backlight_8_to_16(unsigned int backlight_8bit) +{ + return (uint16_t)(backlight_8bit * 0x101); +} + +unsigned int backlight_millipercent_to_millinit( + struct core_power *core_power, unsigned int millipercent, unsigned int inst) +{ + unsigned int millinit = 0; + unsigned long long numerator = 0; + + if (core_power == NULL) + return 0; + + numerator = ((unsigned long long)millipercent) * + core_power->bl_prop[inst].nits_range; + millinit = ((unsigned int)div_u64(numerator, 100000)) + + core_power->bl_prop[inst].min_brightness_millinits; + + return millinit; +} + +static unsigned int backlight_millinit_to_millipercent( + struct core_power *core_power, unsigned int millinit, unsigned int inst) +{ + unsigned int millipercent = 0; + unsigned long long numerator = 0; + + if (core_power == NULL) + return 0; + + if (millinit <= core_power->bl_prop[inst].min_brightness_millinits) + return 0; + + if (millinit >= core_power->bl_prop[inst].max_brightness_millinits) + return (100 * 1000); + + numerator = (((unsigned long long)millinit) - + core_power->bl_prop[inst].min_brightness_millinits) * 100000; + millipercent = ((unsigned int)div_u64(numerator, + core_power->bl_prop[inst].nits_range)); + + return millipercent; +} + +static unsigned int backlight_pwm_to_millipercent( + struct core_power *core_power, unsigned int pwm, unsigned int inst) +{ + unsigned int millipercent = 0; + unsigned int max_index = 0; + + if (core_power == NULL) + return 0; + + if (!core_power->bl_prop[inst].backlight_caps_valid) + return 0; + + /* Doesn't really make sense to have one single backlight level + * possible... + */ + if (core_power->bl_prop[inst].num_backlight_levels < 2) + return 0; + + max_index = core_power->bl_prop[inst].num_backlight_levels - 1; + + if (pwm <= core_power->bl_prop[inst].backlight_lut[0]) + return 0; + + if (pwm > core_power->bl_prop[inst].backlight_lut[max_index]) + return (100 * 1000); + + /* We need to do a binary search over the array for where the pwm level + * is in the lut. Based on the index we can determine percentage. + */ + unsigned int min = 0; + unsigned int max = max_index; + unsigned int mid = 0; + + while (max >= min) { + mid = (min + max) / 2; /* floor of half range */ + + if (core_power->bl_prop[inst].backlight_lut[mid] < pwm) + min = mid + 1; + else if (core_power->bl_prop[inst].backlight_lut[mid] > pwm) + max = mid - 1; + else + break; + } + + /* In this case, exact match is not found. Check if mid/min/max + * value is actually closer. + */ + if (max < min) { + unsigned int min_delta; + unsigned int mid_delta; + unsigned int max_delta; + + min_delta = (core_power->bl_prop[inst].backlight_lut[min] > pwm) ? + core_power->bl_prop[inst].backlight_lut[min] - pwm : + pwm - core_power->bl_prop[inst].backlight_lut[min]; + + mid_delta = (core_power->bl_prop[inst].backlight_lut[mid] > pwm) ? + core_power->bl_prop[inst].backlight_lut[mid] - pwm : + pwm - core_power->bl_prop[inst].backlight_lut[mid]; + + max_delta = (core_power->bl_prop[inst].backlight_lut[max] > pwm) ? + core_power->bl_prop[inst].backlight_lut[max] - pwm : + pwm - core_power->bl_prop[inst].backlight_lut[max]; + + if ((min_delta < mid_delta) && (min_delta < max_delta)) + mid = min; + + if ((max_delta < mid_delta) && (max_delta < min_delta)) + mid = max; + } + + /* No interpolation, just take closest index */ + millipercent = 1000 * 100 * mid / max_index; + + return millipercent; +} + +static unsigned int backlight_pwm_to_millinit( + struct core_power *core_power, unsigned int pwm, unsigned int inst) +{ + unsigned int millinit = 0; + + if (core_power == NULL) + return 0; + + if (pwm <= core_power->bl_prop[inst].min_backlight_pwm) + return core_power->bl_prop[inst].min_brightness_millinits; + + if (pwm >= core_power->bl_prop[inst].max_backlight_pwm) + return core_power->bl_prop[inst].max_brightness_millinits; + + millinit = ((unsigned int)div_u64(((unsigned long long)pwm - + core_power->bl_prop[inst].min_backlight_pwm) * + core_power->bl_prop[inst].nits_range, + core_power->bl_prop[inst].backlight_range)); + + millinit += core_power->bl_prop[inst].min_brightness_millinits; + + if (millinit > core_power->bl_prop[inst].max_brightness_millinits) + millinit = core_power->bl_prop[inst].max_brightness_millinits; + + return millinit; +} + +unsigned int backlight_millipercent_to_pwm( + struct core_power *core_power, unsigned int millipercent, unsigned int inst) +{ + unsigned int pwm = (unsigned int)-1; + unsigned int index = 0; + + if (core_power == NULL) + return 0; + + // Bypass the brightness mapping LUT + if (core_power->bl_prop->use_linear_backlight_curve) { + pwm = core_power->bl_prop[inst].min_backlight_pwm + + (unsigned int) div_u64((unsigned long long) millipercent * + core_power->bl_prop[inst].backlight_range, + 100000); + + if (pwm > core_power->bl_prop[inst].max_backlight_pwm) + pwm = core_power->bl_prop[inst].max_backlight_pwm; + + return pwm; + } + + if (millipercent >= (100 * 1000)) + return core_power->bl_prop[inst].backlight_lut[core_power->bl_prop[inst].num_backlight_levels - 1]; + + /* This will give the floor index. */ + index = ((core_power->bl_prop[inst].num_backlight_levels - 1) * + millipercent) / 100000; + /* Null check otherwise eDP doesn't lightup when connected to DP1 */ + if (core_power->bl_prop[inst].backlight_lut == NULL) + return pwm; + + pwm = core_power->bl_prop[inst].backlight_lut[index]; + + return pwm; +} + +static unsigned int backlight_millinit_to_pwm( + struct core_power *core_power, unsigned int millinit, unsigned int inst) +{ + unsigned int pwm = 0; + + if (core_power == NULL) + return 0; + + /* For nits based brightness, the signal will be a value + * between the minimum and maximum value. + */ + if (millinit >= core_power->bl_prop[inst].max_brightness_millinits) + return core_power->bl_prop[inst].max_backlight_pwm; + else if (millinit <= core_power->bl_prop[inst].min_brightness_millinits) + return core_power->bl_prop[inst].min_backlight_pwm; + + pwm = ((unsigned int)div_u64(((unsigned long long)millinit - + core_power->bl_prop[inst].min_brightness_millinits) * + core_power->bl_prop[inst].backlight_range, + core_power->bl_prop[inst].nits_range)); + + pwm += core_power->bl_prop[inst].min_backlight_pwm; + + if (pwm > core_power->bl_prop[inst].max_backlight_pwm) + pwm = core_power->bl_prop[inst].max_backlight_pwm; + + return pwm; +} + +static bool validate_ext_backlight_caps( + struct dm_acpi_atif_backlight_caps *ext_backlight_caps) +{ + unsigned int i; + unsigned int num_of_data_points = 0; + unsigned int last_signal_level = 0; + unsigned int last_luminance = 0; + + num_of_data_points = ext_backlight_caps->num_data_points; + + /* Validation rules: + * 1. BIOS should carry customized data points and + * the number of data points should not be larger than 99. + * 2. The max_input_signal should be larger than min_input_signal. + * 3. For each data point: + * a. luminance should be in ascending order and + * should not be 0 or 100 since the corresponding signal_level + * are assigned by min_input_signal and max_input_signal. + * b. signal_level should be in ascending order and + * be within the range of min/max_input_signal. + */ + if (num_of_data_points > BL_DATA_POINTS) + return false; + + if (ext_backlight_caps->min_input_signal >= ext_backlight_caps->max_input_signal) + return false; + + last_signal_level = ext_backlight_caps->min_input_signal; + for (i = 0; i < num_of_data_points; i++) { + unsigned int luminance = ext_backlight_caps->data_points[i].luminance; + unsigned int signal_level = ext_backlight_caps->data_points[i].signal_level; + + if ((luminance <= last_luminance) || (luminance > BL_DATA_POINTS)) + return false; + + if ((signal_level <= last_signal_level) || (signal_level >= ext_backlight_caps->max_input_signal)) + return false; + + last_signal_level = signal_level; + last_luminance = luminance; + } + + return true; +} + +/* hard coded to default backlight curve. */ +void initialize_backlight_caps(struct core_power *core_power, unsigned int inst) +{ + unsigned int i; + struct dm_acpi_atif_backlight_caps *ext_backlight_caps = NULL; + bool custom_curve_present = false; + unsigned int num_levels = 0; + struct dc *dc = NULL; + enum dm_acpi_display_type acpi_display_type = + (inst == 0) ? AcpiDisplayType_LCD1 : AcpiDisplayType_LCD2; + + if (core_power == NULL) + return; + dc = core_power->dc; + + num_levels = core_power->bl_prop[inst].num_backlight_levels; + + /* Allocate memory for ATIF output + * (do not want to use 256 bytes on the stack) + */ + ext_backlight_caps = (struct dm_acpi_atif_backlight_caps *) + (kzalloc(sizeof(struct dm_acpi_atif_backlight_caps), + GFP_KERNEL)); + + if (ext_backlight_caps == NULL) + return; + + /* Retrieve ACPI extended brightness caps */ + if (dm_query_extended_brightness_caps + (dc->ctx, acpi_display_type, ext_backlight_caps)) { + custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps); + } + + if (core_power->bl_prop[inst].use_custom_backlight_caps && + fill_custom_backlight_caps( + core_power->bl_prop[inst].custom_backlight_caps_config_no, + ext_backlight_caps)) { + custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps); + } + + if (custom_curve_present) { + unsigned int index = 1; + unsigned int num_of_data_points = ext_backlight_caps->num_data_points; + + core_power->bl_prop[inst].ac_backlight_percent = + ext_backlight_caps->ac_level_percentage; + core_power->bl_prop[inst].dc_backlight_percent = + ext_backlight_caps->dc_level_percentage; + core_power->bl_prop[inst].backlight_lut[0] = + backlight_8_to_16( + ext_backlight_caps->min_input_signal); + core_power->bl_prop[inst].backlight_lut[num_levels - 1] = + backlight_8_to_16( + ext_backlight_caps->max_input_signal); + + /* Filling translation table from data points - + * between every two provided data points we + * lineary interpolate missing values + */ + for (i = 0; i < num_of_data_points; i++) { + unsigned int luminance = + ext_backlight_caps->data_points[i].luminance; + unsigned int signal_level = + backlight_8_to_16( + ext_backlight_caps->data_points[i].signal_level); + + /* Since luminance is a percentage, scale it by num_levels*/ + luminance = (luminance * num_levels) / 101; + + /* Lineary interpolate missing values */ + if (index < luminance) { + unsigned int base_value = + core_power->bl_prop[inst].backlight_lut[index-1]; + unsigned int delta_signal = + signal_level - base_value; + unsigned int delta_luma = + luminance - index + 1; + unsigned int step = delta_signal; + + for (; index < luminance; index++) { + core_power->bl_prop[inst].backlight_lut[index] = + base_value + (step / delta_luma); + step += delta_signal; + } + } + + /* Now [index == luminance], + * so we can add data point to the translation table + */ + core_power->bl_prop[inst].backlight_lut[index++] = signal_level; + } + + /* Complete the final segment of interpolation - + * between last datapoint and maximum value + */ + if (index < num_levels - 1) { + unsigned int base_value = + core_power->bl_prop[inst].backlight_lut[index-1]; + unsigned int delta_signal = + core_power->bl_prop[inst].backlight_lut[num_levels - 1] - + base_value; + unsigned int delta_luma = num_levels - index; + unsigned int step = delta_signal; + + for (; index < num_levels - 1; index++) { + core_power->bl_prop[inst].backlight_lut[index] = + base_value + (step / delta_luma); + step += delta_signal; + } + } + /* Build backlight translation table based on default curve */ + } else { + /* Defines default backlight curve F(x) = A(x*x) + Bx + C. + * + * Backlight curve should always satisfy: + * F(0) = min, F(100) = max, + * So polynom coefficients are: + * A is 0.0255 - B/100 - min/10000 - (255-max)/10000 = + * (max - min)/10000 - B/100 + * B is adjustable factor to modify the curve. + * Bigger B results in less concave curve. + * B range is [0..(max-min)/100] + * C is backlight minimum + */ + unsigned int backlight_curve_coeff_a_factor = + num_levels * num_levels; + unsigned int backlight_curve_coeff_b = num_levels; + unsigned int delta = + core_power->bl_prop[inst].backlight_lut[num_levels - 1] - + core_power->bl_prop[inst].backlight_lut[0]; + unsigned int coeffC = core_power->bl_prop[inst].backlight_lut[0]; + unsigned int coeffB = + (backlight_curve_coeff_b < delta ? + backlight_curve_coeff_b : delta); + unsigned long long coeffA = delta - coeffB; /* coeffB is B*100 */ + + for (i = 1; i < num_levels - 1; i++) { + uint64_t lut_val = div_u64(coeffA * i * i, backlight_curve_coeff_a_factor) + + div_u64((uint64_t)coeffB * i, backlight_curve_coeff_b) + coeffC; + + ASSERT(lut_val <= 0xFFFFFFFF); + core_power->bl_prop[inst].backlight_lut[i] = (unsigned int)lut_val; + } + } + + if (ext_backlight_caps != NULL) + kfree(ext_backlight_caps); + + /* Successfully initialized */ + core_power->bl_prop[inst].backlight_caps_valid = true; +} + +static void varibright_set_level(struct core_power *core_power) +{ + if (!core_power->varibright_prop.varibright_active || + !core_power->varibright_prop.varibright_user_enable) + core_power->varibright_prop.varibright_hw_level = 0; + else + core_power->varibright_prop.varibright_hw_level = + core_power->varibright_prop.varibright_level; +} + +bool mod_power_hw_init_backlight(struct mod_power *mod_power) +{ + struct core_power *core_power = NULL; + struct dc *dc = NULL; + struct dmcu *dmcu = NULL; + struct dmcu_iram_parameters params; + unsigned int i; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + dc = core_power->dc; + + for (i = 0; i < core_power->edp_num; i++) { + params.set = core_power->varibright_prop.varibright_config_setting; + params.backlight_ramping_override = core_power->bl_prop[i].backlight_ramping_override; + params.backlight_ramping_reduction = core_power->bl_prop[i].backlight_ramping_reduction; + params.backlight_ramping_start = core_power->bl_prop[i].backlight_ramping_start; + params.backlight_lut_array = core_power->bl_prop[i].backlight_lut; + params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels; + params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight; + + dmcu = dc->res_pool->dmcu; + + // In the case where abm is implemented on dmcub, + // dmcu object will be null. + // ABM 2.4 and up are implemented on dmcub. + if (dmcu) { + //DMCU does not support multiple eDP + return dmcu_load_iram(dmcu, params); + } else if (dc->ctx->dmub_srv) { + if (!dmub_init_abm_config(dc->res_pool, params, i)) + return false; + } else + return false; + } + return true; +} + +void mod_power_update_backlight_on_mode_change( + struct core_power *core_power, + struct dc_link *link, + unsigned int panel_inst, + uint8_t aux_inst, + bool is_hdr) +{ + struct set_backlight_level_params backlight_level_params = { 0 }; + + if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || + link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) + dc_link_set_backlight_level_nits(link, core_power->bl_state[panel_inst].isHDR, + core_power->bl_state[panel_inst].backlight_millinit, 0); + + backlight_level_params.frame_ramp = 0; + + fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, + core_power->bl_state[panel_inst].backlight_pwm, link->backlight_control_type, + core_power->bl_state[panel_inst].backlight_millinit, 0, is_hdr); + + dc_link_set_backlight_level(link, &backlight_level_params); +} + +static bool set_backlight_millinits_aux(struct core_power *core_power, + struct dc_stream_state *stream, + unsigned int backlight_millinits, + unsigned int transition_time_millisec, + unsigned int inst) +{ + struct dc_link *link = NULL; + + if (core_power == NULL) + return false; + + if (stream == NULL) + return true; + + link = dc_stream_get_link(stream); + + return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR, + backlight_millinits, transition_time_millisec); +} + +static bool set_backlight(struct core_power *core_power, + struct dc_stream_state *stream, + struct set_backlight_level_params *backlight_level_params, + unsigned int inst) +{ + bool retv = false; + unsigned int frame_ramp = 0; + unsigned int vsync_rate_hz; + union dmcu_abm_set_bl_params params; + const struct dc_link *link = NULL; + unsigned int backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16; + unsigned int transition_time_millisec = backlight_level_params->transition_time_in_ms; + + if (core_power == NULL) + return false; + + core_power->bl_state[inst].backlight_pwm = backlight_pwm_u16_16; + + if (stream == NULL) + return true; + + if (stream->link->connector_signal != SIGNAL_TYPE_EDP) + return false; + + if (transition_time_millisec != 0) { + unsigned int v_total = + (stream->adjust.v_total_max == 0) ? stream->timing.v_total : stream->adjust.v_total_max; + + vsync_rate_hz = (unsigned int)div_u64(div_u64((stream-> + timing.pix_clk_100hz * 100), + v_total), + stream->timing.h_total); + + if (core_power->bl_state[inst].smooth_brightness_enabled) + frame_ramp = ((vsync_rate_hz * + transition_time_millisec) + 500) / 1000; + } + + core_power->bl_state[inst].frame_ramp = frame_ramp; + params.u32All = 0; + params.bits.gradual_change = (frame_ramp > 0); + params.bits.frame_ramp = frame_ramp; + link = dc_stream_get_link(stream); + + mod_power_set_psr_event(&core_power->mod_public, stream, true, psr_event_hw_programming, true); + mod_power_set_replay_event(&core_power->mod_public, stream, true, replay_event_hw_programming, true); + + backlight_level_params->frame_ramp = params.u32All; + retv = dc_link_set_backlight_level(link, backlight_level_params); + + mod_power_set_psr_event(&core_power->mod_public, stream, false, psr_event_hw_programming, false); + mod_power_set_replay_event(&core_power->mod_public, stream, false, replay_event_hw_programming, false); + + return retv; +} + +void fill_backlight_level_params(struct core_power *core_power, + struct set_backlight_level_params *backlight_level_params, + int panel_inst, uint8_t aux_inst, unsigned int backlight_pwm, + enum backlight_control_type backlight_control_type, + unsigned int backlight_millinit, unsigned int transition_time_millisec, + bool is_hdr) +{ + struct pwr_backlight_properties *bl_prop = &core_power->bl_prop[panel_inst]; + + backlight_level_params->aux_inst = aux_inst; + backlight_level_params->backlight_pwm_u16_16 = backlight_pwm; + backlight_level_params->control_type = backlight_control_type; + backlight_level_params->backlight_millinits = backlight_millinit; + backlight_level_params->transition_time_in_ms = transition_time_millisec; + backlight_level_params->min_luminance = bl_prop->min_brightness_millinits; + backlight_level_params->max_luminance = bl_prop->max_brightness_millinits; + backlight_level_params->min_backlight_pwm = bl_prop->min_backlight_pwm; + backlight_level_params->max_backlight_pwm = bl_prop->max_backlight_pwm; + + if (backlight_control_type == BACKLIGHT_CONTROL_AMD_AUX && !is_hdr) + backlight_level_params->control_type = BACKLIGHT_CONTROL_PWM; +} + +bool mod_power_set_backlight_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit, + unsigned int transition_time_millisec, + bool skip_aux, + bool is_hdr) +{ + struct core_power *core_power = NULL; + unsigned int backlight_pwm; + unsigned int panel_inst = 0; + struct set_backlight_level_params backlight_level_params = { 0 }; + const struct dc_link *link = NULL; + uint8_t aux_inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + link = dc_stream_get_link(stream); + + ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); + aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst)) + return false; + + if (!skip_aux) { + if (!set_backlight_millinits_aux(core_power, stream, + backlight_millinit, transition_time_millisec, panel_inst)) + return false; + } +// always send both AUX (above) and PWM (below) + core_power->bl_state[panel_inst].backlight_millinit = backlight_millinit; + + core_power->bl_state[panel_inst].backlight_millipercent = + backlight_millinit_to_millipercent( + core_power, backlight_millinit, panel_inst); + + backlight_pwm = backlight_millinit_to_pwm( + core_power, backlight_millinit, panel_inst); + + fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, backlight_pwm, + link->backlight_control_type, backlight_millinit, transition_time_millisec, is_hdr); + + return set_backlight(core_power, stream, + &backlight_level_params, panel_inst); +} + +bool mod_power_backlight_percent_to_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent, + unsigned int *backlight_millinit) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return false; + + *backlight_millinit = backlight_millipercent_to_millinit( + core_power, backlight_millipercent, inst); + return true; +} + +bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit, + unsigned int *backlight_millipercent) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return false; + + *backlight_millipercent = backlight_millinit_to_millipercent( + core_power, backlight_millinit, inst); + return true; +} + +bool mod_power_set_backlight_percent(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent, + unsigned int transition_time_millisec, + bool is_hdr) +{ + struct core_power *core_power = NULL; + struct set_backlight_level_params backlight_level_params = { 0 }; + const struct dc_link *link = NULL; + unsigned int backlight_pwm; + unsigned int panel_inst = 0; + uint8_t aux_inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + link = dc_stream_get_link(stream); + ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); + aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst)) + return false; + core_power->bl_state[panel_inst].backlight_millipercent = backlight_millipercent; + + core_power->bl_state[panel_inst].backlight_millinit = + backlight_millipercent_to_millinit( + core_power, backlight_millipercent, panel_inst); + + backlight_pwm = backlight_millipercent_to_pwm( + core_power, backlight_millipercent, panel_inst); + + fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, + aux_inst, backlight_pwm, link->backlight_control_type, + core_power->bl_state[panel_inst].backlight_millinit, transition_time_millisec, is_hdr); + + return set_backlight(core_power, stream, + &backlight_level_params, panel_inst); +} + +void mod_power_update_backlight(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return; + core_power->bl_state[inst].backlight_millipercent = backlight_millipercent; + + core_power->bl_state[inst].backlight_millinit = + backlight_millipercent_to_millinit( + core_power, backlight_millipercent, inst); + + core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm( + core_power, backlight_millipercent, inst); +} + +void mod_power_update_backlight_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return; + + core_power->bl_state[inst].backlight_millinit = backlight_millinit; + + core_power->bl_state[inst].backlight_millipercent = backlight_millinit_to_millipercent( + core_power, backlight_millinit, inst); + core_power->bl_state[inst].backlight_pwm = backlight_millinit_to_pwm( + core_power, backlight_millinit, inst); +} + +bool mod_power_get_backlight_pwm(struct mod_power *mod_power, + unsigned int *backlight_pwm, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *backlight_pwm = core_power->bl_state[inst].backlight_pwm; + + return true; +} + +bool mod_power_get_backlight_nits(struct mod_power *mod_power, + unsigned int *backlight_millinit, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *backlight_millinit = core_power->bl_state[inst].backlight_millinit; + + return true; +} + +bool mod_power_get_backlight_percent(struct mod_power *mod_power, + unsigned int *backlight_millipercent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *backlight_millipercent = core_power->bl_state[inst].backlight_millipercent; + + return true; +} + +bool mod_power_get_hw_target_backlight_pwm_nits(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millinit, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_target_backlight_pwm(mod_power, link, + &backlight_u16_16)) { + *backlight_millinit = + backlight_pwm_to_millinit(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_target_backlight_pwm_percent(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millipercent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_target_backlight_pwm(mod_power, link, + &backlight_u16_16)) { + *backlight_millipercent = + backlight_pwm_to_millipercent(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_target_backlight_pwm(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_u16_16) +{ + if (mod_power == NULL) + return false; + + *backlight_u16_16 = dc_link_get_target_backlight_pwm(link); + + return true; +} + +bool mod_power_get_hw_backlight_pwm_nits(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millinit, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) { + *backlight_millinit = + backlight_pwm_to_millinit(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_backlight_aux_nits(struct mod_power *mod_power, + struct dc_stream_state **streams, int num_streams, + unsigned int *backlight_millinit_avg, + unsigned int *backlight_millinit_peak) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + int stream_index; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power == NULL) + return false; + + if (num_streams < 1) + return true; + + for (stream_index = 0; stream_index < num_streams; stream_index++) + if (streams[stream_index]->link->connector_signal == SIGNAL_TYPE_EDP || + streams[stream_index]->link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) + break; + + if (stream_index == num_streams) + return false; + + link = dc_stream_get_link(streams[stream_index]); + if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 0) + return false; + + return dc_link_get_backlight_level_nits(link, backlight_millinit_avg, + backlight_millinit_peak); +} + +bool mod_power_get_hw_backlight_pwm_percent(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millipercent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) { + *backlight_millipercent = + backlight_pwm_to_millipercent(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_backlight_pwm(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_u16_16) +{ + if (mod_power == NULL) + return false; + + *backlight_u16_16 = dc_link_get_backlight_level(link); + + return true; +} + +bool mod_power_get_panel_backlight_boundaries( + struct mod_power *mod_power, + unsigned int *out_min_backlight, + unsigned int *out_max_backlight, + unsigned int *out_ac_backlight_percent, + unsigned int *out_dc_backlight_percent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + /* If cache was successfully updated, + * copy the values to output structure and return success + */ + if (core_power->bl_prop[inst].backlight_caps_valid) { + *out_min_backlight = core_power->bl_prop[inst].backlight_lut[0]; + *out_max_backlight = + core_power->bl_prop[inst].backlight_lut[ + core_power->bl_prop[inst].num_backlight_levels - 1]; + *out_ac_backlight_percent = + core_power->bl_prop[inst].ac_backlight_percent; + *out_dc_backlight_percent = + core_power->bl_prop[inst].dc_backlight_percent; + + return true; + } + + return false; +} + +bool mod_power_set_smooth_brightness(struct mod_power *mod_power, + bool enable_brightness, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + core_power->bl_state[inst].smooth_brightness_enabled = enable_brightness; + + return true; +} + +bool mod_power_varibright_feature_enable(struct mod_power *mod_power, bool enable, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + core_power->varibright_prop.varibright_user_enable = enable; + + /* find abm hw level to program, and save in stream update */ + varibright_set_level(core_power); + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM feature enable: enable=%u su->varibright_level=%u varibright_hw_level=%u", + (unsigned int) enable, + *stream_update->abm_level, + core_power->varibright_prop.varibright_hw_level); + return true; +} + +bool mod_power_varibright_activate(struct mod_power *mod_power, + bool activate, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + core_power->varibright_prop.varibright_active = activate; + + /* find abm hw level to program, and save in stream update */ + varibright_set_level(core_power); + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM activate: activate=%u su->varibright_level=%u", + (unsigned int) activate, + *stream_update->abm_level); + return true; +} +bool mod_power_varibright_set_level(struct mod_power *mod_power, unsigned int level, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + core_power->varibright_prop.varibright_level = level; + core_power->varibright_prop.varibright_hw_level = level; + + /* find abm hw level to program, and save in stream update */ + varibright_set_level(core_power); + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u", + level, + core_power->varibright_prop.varibright_level, + core_power->varibright_prop.varibright_hw_level, + *stream_update->abm_level); + return true; +} + +bool mod_power_varibright_set_hw_level(struct mod_power *mod_power, unsigned int level, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (level == 0 || level == ABM_LEVEL_IMMEDIATE_DISABLE) + core_power->varibright_prop.varibright_active = 0; + else + core_power->varibright_prop.varibright_active = 1; + core_power->varibright_prop.varibright_hw_level = level; + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u", + level, + core_power->varibright_prop.varibright_level, + core_power->varibright_prop.varibright_hw_level, + *stream_update->abm_level); + return true; +} + +bool mod_power_get_varibright_level(struct mod_power *mod_power, + unsigned int *varibright_level) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_level = core_power->varibright_prop.varibright_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright level: cp->varibright_level=%u", + *varibright_level); + return true; + +} + +bool mod_power_get_varibright_hw_level(struct mod_power *mod_power, + unsigned int *varibright_level) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_level = core_power->varibright_prop.varibright_hw_level; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright HW level: hw_level=%u", + *varibright_level); + return true; +} + +bool mod_power_get_varibright_default_level(struct mod_power *mod_power, + unsigned int *varibright_level) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_level = core_power->varibright_prop.def_varibright_level; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright default level: def_varibright_level=%u", + *varibright_level); + return true; +} + +bool mod_power_get_varibright_enable(struct mod_power *mod_power, + bool *varibright_enable) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_enable = core_power->varibright_prop.varibright_user_enable; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright enable state: varibright_user_enable=%u", + (unsigned int) (*varibright_enable)); + return true; +} + +bool mod_power_is_abm_active(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int inst) +{ + unsigned int user_backlight = 0; + unsigned int current_backlight = 0; + bool is_active = false; + + if (mod_power == NULL) + return false; + + mod_power_get_backlight_pwm(mod_power, &user_backlight, inst); + mod_power_get_hw_backlight_pwm(mod_power, link, ¤t_backlight); + + if (user_backlight != current_backlight) + is_active = true; + else + is_active = false; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get ABM active state: is_active=%u (user_backlight_pwm=%u, current_backlight_pwm=%u)", + (unsigned int)is_active, + user_backlight, + current_backlight); + return is_active; +} + +static void fill_backlight_transform_table(struct dmcu_iram_parameters params, + struct iram_table_v_2 *table) +{ + unsigned int i; + unsigned int num_entries = NUM_BL_CURVE_SEGS; + unsigned int lut_index; + + table->backlight_thresholds[0] = 0; + ASSERT(params.backlight_lut_array[0] <= 0xFFFF); + table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0]; + table->backlight_thresholds[num_entries-1] = 0xFFFF; + ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF); + table->backlight_offsets[num_entries-1] = + (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1]; + + /* Setup all brightness levels between 0% and 100% exclusive + * Fills brightness-to-backlight transform table. Backlight custom curve + * describes transform from brightness to backlight. It will be defined + * as set of thresholds and set of offsets, together, implying + * extrapolation of custom curve into 16 uniformly spanned linear + * segments. Each threshold/offset represented by 16 bit entry in + * format U4.10. + */ + for (i = 1; i+1 < num_entries; i++) { + lut_index = (params.backlight_lut_array_size - 1) * i / (num_entries - 1); + + ASSERT(lut_index < params.backlight_lut_array_size); + + unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries); + unsigned int offset_val = params.backlight_lut_array[lut_index]; + + ASSERT(threshold_val <= 0xFFFF); + ASSERT(offset_val <= 0xFFFF); + + table->backlight_thresholds[i] = cpu_to_be16((uint16_t)threshold_val); + table->backlight_offsets[i] = cpu_to_be16((uint16_t)offset_val); + } +} + +static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters params, + struct iram_table_v_2_2 *table, bool big_endian) +{ + unsigned int i; + unsigned int num_entries = NUM_BL_CURVE_SEGS; + unsigned int lut_index; + + table->backlight_thresholds[0] = 0; + ASSERT(params.backlight_lut_array[0] <= 0xFFFF); + table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0]; + table->backlight_thresholds[num_entries-1] = 0xFFFF; + ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF); + table->backlight_offsets[num_entries-1] = + (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1]; + + /* Setup all brightness levels between 0% and 100% exclusive + * Fills brightness-to-backlight transform table. Backlight custom curve + * describes transform from brightness to backlight. It will be defined + * as set of thresholds and set of offsets, together, implying + * extrapolation of custom curve into 16 uniformly spanned linear + * segments. Each threshold/offset represented by 16 bit entry in + * format U4.10. + */ + for (i = 1; i+1 < num_entries; i++) { + lut_index = DIV_ROUNDUP((i * params.backlight_lut_array_size), num_entries); + ASSERT(lut_index < params.backlight_lut_array_size); + + unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries); + unsigned int offset_val = params.backlight_lut_array[lut_index]; + + ASSERT(threshold_val <= 0xFFFF); + ASSERT(offset_val <= 0xFFFF); + + table->backlight_thresholds[i] = (big_endian) ? + cpu_to_be16((uint16_t)threshold_val) : cpu_to_le16((uint16_t)threshold_val); + table->backlight_offsets[i] = (big_endian) ? + cpu_to_be16((uint16_t)offset_val) : cpu_to_le16((uint16_t)offset_val); + } +} + +static void fill_iram_v_2(struct iram_table_v_2 *ram_table, struct dmcu_iram_parameters params) +{ + unsigned int set = params.set; + + ram_table->min_abm_backlight = + cpu_to_be16(params.min_abm_backlight); + ram_table->deviation_gain = 0xb3; + + ram_table->blRampReduction = + cpu_to_be16(params.backlight_ramping_reduction); + ram_table->blRampStart = + cpu_to_be16(params.backlight_ramping_start); + + ram_table->min_reduction[0][0] = min_reduction_table[abm_config[set][0]]; + ram_table->min_reduction[1][0] = min_reduction_table[abm_config[set][0]]; + ram_table->min_reduction[2][0] = min_reduction_table[abm_config[set][0]]; + ram_table->min_reduction[3][0] = min_reduction_table[abm_config[set][0]]; + ram_table->min_reduction[4][0] = min_reduction_table[abm_config[set][0]]; + ram_table->max_reduction[0][0] = max_reduction_table[abm_config[set][0]]; + ram_table->max_reduction[1][0] = max_reduction_table[abm_config[set][0]]; + ram_table->max_reduction[2][0] = max_reduction_table[abm_config[set][0]]; + ram_table->max_reduction[3][0] = max_reduction_table[abm_config[set][0]]; + ram_table->max_reduction[4][0] = max_reduction_table[abm_config[set][0]]; + + ram_table->min_reduction[0][1] = min_reduction_table[abm_config[set][1]]; + ram_table->min_reduction[1][1] = min_reduction_table[abm_config[set][1]]; + ram_table->min_reduction[2][1] = min_reduction_table[abm_config[set][1]]; + ram_table->min_reduction[3][1] = min_reduction_table[abm_config[set][1]]; + ram_table->min_reduction[4][1] = min_reduction_table[abm_config[set][1]]; + ram_table->max_reduction[0][1] = max_reduction_table[abm_config[set][1]]; + ram_table->max_reduction[1][1] = max_reduction_table[abm_config[set][1]]; + ram_table->max_reduction[2][1] = max_reduction_table[abm_config[set][1]]; + ram_table->max_reduction[3][1] = max_reduction_table[abm_config[set][1]]; + ram_table->max_reduction[4][1] = max_reduction_table[abm_config[set][1]]; + + ram_table->min_reduction[0][2] = min_reduction_table[abm_config[set][2]]; + ram_table->min_reduction[1][2] = min_reduction_table[abm_config[set][2]]; + ram_table->min_reduction[2][2] = min_reduction_table[abm_config[set][2]]; + ram_table->min_reduction[3][2] = min_reduction_table[abm_config[set][2]]; + ram_table->min_reduction[4][2] = min_reduction_table[abm_config[set][2]]; + ram_table->max_reduction[0][2] = max_reduction_table[abm_config[set][2]]; + ram_table->max_reduction[1][2] = max_reduction_table[abm_config[set][2]]; + ram_table->max_reduction[2][2] = max_reduction_table[abm_config[set][2]]; + ram_table->max_reduction[3][2] = max_reduction_table[abm_config[set][2]]; + ram_table->max_reduction[4][2] = max_reduction_table[abm_config[set][2]]; + + ram_table->min_reduction[0][3] = min_reduction_table[abm_config[set][3]]; + ram_table->min_reduction[1][3] = min_reduction_table[abm_config[set][3]]; + ram_table->min_reduction[2][3] = min_reduction_table[abm_config[set][3]]; + ram_table->min_reduction[3][3] = min_reduction_table[abm_config[set][3]]; + ram_table->min_reduction[4][3] = min_reduction_table[abm_config[set][3]]; + ram_table->max_reduction[0][3] = max_reduction_table[abm_config[set][3]]; + ram_table->max_reduction[1][3] = max_reduction_table[abm_config[set][3]]; + ram_table->max_reduction[2][3] = max_reduction_table[abm_config[set][3]]; + ram_table->max_reduction[3][3] = max_reduction_table[abm_config[set][3]]; + ram_table->max_reduction[4][3] = max_reduction_table[abm_config[set][3]]; + + ram_table->bright_pos_gain[0][0] = 0x20; + ram_table->bright_pos_gain[0][1] = 0x20; + ram_table->bright_pos_gain[0][2] = 0x20; + ram_table->bright_pos_gain[0][3] = 0x20; + ram_table->bright_pos_gain[1][0] = 0x20; + ram_table->bright_pos_gain[1][1] = 0x20; + ram_table->bright_pos_gain[1][2] = 0x20; + ram_table->bright_pos_gain[1][3] = 0x20; + ram_table->bright_pos_gain[2][0] = 0x20; + ram_table->bright_pos_gain[2][1] = 0x20; + ram_table->bright_pos_gain[2][2] = 0x20; + ram_table->bright_pos_gain[2][3] = 0x20; + ram_table->bright_pos_gain[3][0] = 0x20; + ram_table->bright_pos_gain[3][1] = 0x20; + ram_table->bright_pos_gain[3][2] = 0x20; + ram_table->bright_pos_gain[3][3] = 0x20; + ram_table->bright_pos_gain[4][0] = 0x20; + ram_table->bright_pos_gain[4][1] = 0x20; + ram_table->bright_pos_gain[4][2] = 0x20; + ram_table->bright_pos_gain[4][3] = 0x20; + ram_table->bright_neg_gain[0][0] = 0x00; + ram_table->bright_neg_gain[0][1] = 0x00; + ram_table->bright_neg_gain[0][2] = 0x00; + ram_table->bright_neg_gain[0][3] = 0x00; + ram_table->bright_neg_gain[1][0] = 0x00; + ram_table->bright_neg_gain[1][1] = 0x00; + ram_table->bright_neg_gain[1][2] = 0x00; + ram_table->bright_neg_gain[1][3] = 0x00; + ram_table->bright_neg_gain[2][0] = 0x00; + ram_table->bright_neg_gain[2][1] = 0x00; + ram_table->bright_neg_gain[2][2] = 0x00; + ram_table->bright_neg_gain[2][3] = 0x00; + ram_table->bright_neg_gain[3][0] = 0x00; + ram_table->bright_neg_gain[3][1] = 0x00; + ram_table->bright_neg_gain[3][2] = 0x00; + ram_table->bright_neg_gain[3][3] = 0x00; + ram_table->bright_neg_gain[4][0] = 0x00; + ram_table->bright_neg_gain[4][1] = 0x00; + ram_table->bright_neg_gain[4][2] = 0x00; + ram_table->bright_neg_gain[4][3] = 0x00; + ram_table->dark_pos_gain[0][0] = 0x00; + ram_table->dark_pos_gain[0][1] = 0x00; + ram_table->dark_pos_gain[0][2] = 0x00; + ram_table->dark_pos_gain[0][3] = 0x00; + ram_table->dark_pos_gain[1][0] = 0x00; + ram_table->dark_pos_gain[1][1] = 0x00; + ram_table->dark_pos_gain[1][2] = 0x00; + ram_table->dark_pos_gain[1][3] = 0x00; + ram_table->dark_pos_gain[2][0] = 0x00; + ram_table->dark_pos_gain[2][1] = 0x00; + ram_table->dark_pos_gain[2][2] = 0x00; + ram_table->dark_pos_gain[2][3] = 0x00; + ram_table->dark_pos_gain[3][0] = 0x00; + ram_table->dark_pos_gain[3][1] = 0x00; + ram_table->dark_pos_gain[3][2] = 0x00; + ram_table->dark_pos_gain[3][3] = 0x00; + ram_table->dark_pos_gain[4][0] = 0x00; + ram_table->dark_pos_gain[4][1] = 0x00; + ram_table->dark_pos_gain[4][2] = 0x00; + ram_table->dark_pos_gain[4][3] = 0x00; + ram_table->dark_neg_gain[0][0] = 0x00; + ram_table->dark_neg_gain[0][1] = 0x00; + ram_table->dark_neg_gain[0][2] = 0x00; + ram_table->dark_neg_gain[0][3] = 0x00; + ram_table->dark_neg_gain[1][0] = 0x00; + ram_table->dark_neg_gain[1][1] = 0x00; + ram_table->dark_neg_gain[1][2] = 0x00; + ram_table->dark_neg_gain[1][3] = 0x00; + ram_table->dark_neg_gain[2][0] = 0x00; + ram_table->dark_neg_gain[2][1] = 0x00; + ram_table->dark_neg_gain[2][2] = 0x00; + ram_table->dark_neg_gain[2][3] = 0x00; + ram_table->dark_neg_gain[3][0] = 0x00; + ram_table->dark_neg_gain[3][1] = 0x00; + ram_table->dark_neg_gain[3][2] = 0x00; + ram_table->dark_neg_gain[3][3] = 0x00; + ram_table->dark_neg_gain[4][0] = 0x00; + ram_table->dark_neg_gain[4][1] = 0x00; + ram_table->dark_neg_gain[4][2] = 0x00; + ram_table->dark_neg_gain[4][3] = 0x00; + + ram_table->iir_curve[0] = 0x65; + ram_table->iir_curve[1] = 0x65; + ram_table->iir_curve[2] = 0x65; + ram_table->iir_curve[3] = 0x65; + ram_table->iir_curve[4] = 0x65; + + //Gamma 2.4 + ram_table->crgb_thresh[0] = cpu_to_be16(0x13b6); + ram_table->crgb_thresh[1] = cpu_to_be16(0x1648); + ram_table->crgb_thresh[2] = cpu_to_be16(0x18e3); + ram_table->crgb_thresh[3] = cpu_to_be16(0x1b41); + ram_table->crgb_thresh[4] = cpu_to_be16(0x1d46); + ram_table->crgb_thresh[5] = cpu_to_be16(0x1f21); + ram_table->crgb_thresh[6] = cpu_to_be16(0x2167); + ram_table->crgb_thresh[7] = cpu_to_be16(0x2384); + ram_table->crgb_offset[0] = cpu_to_be16(0x2999); + ram_table->crgb_offset[1] = cpu_to_be16(0x3999); + ram_table->crgb_offset[2] = cpu_to_be16(0x4666); + ram_table->crgb_offset[3] = cpu_to_be16(0x5999); + ram_table->crgb_offset[4] = cpu_to_be16(0x6333); + ram_table->crgb_offset[5] = cpu_to_be16(0x7800); + ram_table->crgb_offset[6] = cpu_to_be16(0x8c00); + ram_table->crgb_offset[7] = cpu_to_be16(0xa000); + ram_table->crgb_slope[0] = cpu_to_be16(0x3147); + ram_table->crgb_slope[1] = cpu_to_be16(0x2978); + ram_table->crgb_slope[2] = cpu_to_be16(0x23a2); + ram_table->crgb_slope[3] = cpu_to_be16(0x1f55); + ram_table->crgb_slope[4] = cpu_to_be16(0x1c63); + ram_table->crgb_slope[5] = cpu_to_be16(0x1a0f); + ram_table->crgb_slope[6] = cpu_to_be16(0x178d); + ram_table->crgb_slope[7] = cpu_to_be16(0x15ab); + + fill_backlight_transform_table( + params, ram_table); +} + +static void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params) +{ + unsigned int set = params.set; + + ram_table->flags = 0x0; + + ram_table->min_abm_backlight = + cpu_to_be16(params.min_abm_backlight); + + ram_table->deviation_gain[0] = 0xb3; + ram_table->deviation_gain[1] = 0xa8; + ram_table->deviation_gain[2] = 0x98; + ram_table->deviation_gain[3] = 0x68; + + ram_table->min_reduction[0][0] = min_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->min_reduction[1][0] = min_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->min_reduction[2][0] = min_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->min_reduction[3][0] = min_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->min_reduction[4][0] = min_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->max_reduction[0][0] = max_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->max_reduction[1][0] = max_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->max_reduction[2][0] = max_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->max_reduction[3][0] = max_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->max_reduction[4][0] = max_reduction_table_v_2_2[abm_config[set][0]]; + + ram_table->min_reduction[0][1] = min_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->min_reduction[1][1] = min_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->min_reduction[2][1] = min_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->min_reduction[3][1] = min_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->min_reduction[4][1] = min_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->max_reduction[0][1] = max_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->max_reduction[1][1] = max_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->max_reduction[2][1] = max_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->max_reduction[3][1] = max_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->max_reduction[4][1] = max_reduction_table_v_2_2[abm_config[set][1]]; + + ram_table->min_reduction[0][2] = min_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->min_reduction[1][2] = min_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->min_reduction[2][2] = min_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->min_reduction[3][2] = min_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->min_reduction[4][2] = min_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->max_reduction[0][2] = max_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->max_reduction[1][2] = max_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->max_reduction[2][2] = max_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->max_reduction[3][2] = max_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->max_reduction[4][2] = max_reduction_table_v_2_2[abm_config[set][2]]; + + ram_table->min_reduction[0][3] = min_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->min_reduction[1][3] = min_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->min_reduction[2][3] = min_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->min_reduction[3][3] = min_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->min_reduction[4][3] = min_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->max_reduction[0][3] = max_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->max_reduction[1][3] = max_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->max_reduction[2][3] = max_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->max_reduction[3][3] = max_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->max_reduction[4][3] = max_reduction_table_v_2_2[abm_config[set][3]]; + + ram_table->bright_pos_gain[0][0] = 0x20; + ram_table->bright_pos_gain[0][1] = 0x20; + ram_table->bright_pos_gain[0][2] = 0x20; + ram_table->bright_pos_gain[0][3] = 0x20; + ram_table->bright_pos_gain[1][0] = 0x20; + ram_table->bright_pos_gain[1][1] = 0x20; + ram_table->bright_pos_gain[1][2] = 0x20; + ram_table->bright_pos_gain[1][3] = 0x20; + ram_table->bright_pos_gain[2][0] = 0x20; + ram_table->bright_pos_gain[2][1] = 0x20; + ram_table->bright_pos_gain[2][2] = 0x20; + ram_table->bright_pos_gain[2][3] = 0x20; + ram_table->bright_pos_gain[3][0] = 0x20; + ram_table->bright_pos_gain[3][1] = 0x20; + ram_table->bright_pos_gain[3][2] = 0x20; + ram_table->bright_pos_gain[3][3] = 0x20; + ram_table->bright_pos_gain[4][0] = 0x20; + ram_table->bright_pos_gain[4][1] = 0x20; + ram_table->bright_pos_gain[4][2] = 0x20; + ram_table->bright_pos_gain[4][3] = 0x20; + + ram_table->dark_pos_gain[0][0] = 0x00; + ram_table->dark_pos_gain[0][1] = 0x00; + ram_table->dark_pos_gain[0][2] = 0x00; + ram_table->dark_pos_gain[0][3] = 0x00; + ram_table->dark_pos_gain[1][0] = 0x00; + ram_table->dark_pos_gain[1][1] = 0x00; + ram_table->dark_pos_gain[1][2] = 0x00; + ram_table->dark_pos_gain[1][3] = 0x00; + ram_table->dark_pos_gain[2][0] = 0x00; + ram_table->dark_pos_gain[2][1] = 0x00; + ram_table->dark_pos_gain[2][2] = 0x00; + ram_table->dark_pos_gain[2][3] = 0x00; + ram_table->dark_pos_gain[3][0] = 0x00; + ram_table->dark_pos_gain[3][1] = 0x00; + ram_table->dark_pos_gain[3][2] = 0x00; + ram_table->dark_pos_gain[3][3] = 0x00; + ram_table->dark_pos_gain[4][0] = 0x00; + ram_table->dark_pos_gain[4][1] = 0x00; + ram_table->dark_pos_gain[4][2] = 0x00; + ram_table->dark_pos_gain[4][3] = 0x00; + + ram_table->hybrid_factor[0] = 0xff; + ram_table->hybrid_factor[1] = 0xff; + ram_table->hybrid_factor[2] = 0xff; + ram_table->hybrid_factor[3] = 0xc0; + + ram_table->contrast_factor[0] = 0x99; + ram_table->contrast_factor[1] = 0x99; + ram_table->contrast_factor[2] = 0x90; + ram_table->contrast_factor[3] = 0x80; + + ram_table->iir_curve[0] = 0x65; + ram_table->iir_curve[1] = 0x65; + ram_table->iir_curve[2] = 0x65; + ram_table->iir_curve[3] = 0x65; + ram_table->iir_curve[4] = 0x65; + + //Gamma 2.2 + ram_table->crgb_thresh[0] = cpu_to_be16(0x127c); + ram_table->crgb_thresh[1] = cpu_to_be16(0x151b); + ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5); + ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56); + ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83); + ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72); + ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0); + ram_table->crgb_thresh[7] = cpu_to_be16(0x232b); + ram_table->crgb_offset[0] = cpu_to_be16(0x2999); + ram_table->crgb_offset[1] = cpu_to_be16(0x3999); + ram_table->crgb_offset[2] = cpu_to_be16(0x4666); + ram_table->crgb_offset[3] = cpu_to_be16(0x5999); + ram_table->crgb_offset[4] = cpu_to_be16(0x6333); + ram_table->crgb_offset[5] = cpu_to_be16(0x7800); + ram_table->crgb_offset[6] = cpu_to_be16(0x8c00); + ram_table->crgb_offset[7] = cpu_to_be16(0xa000); + ram_table->crgb_slope[0] = cpu_to_be16(0x3609); + ram_table->crgb_slope[1] = cpu_to_be16(0x2dfa); + ram_table->crgb_slope[2] = cpu_to_be16(0x27ea); + ram_table->crgb_slope[3] = cpu_to_be16(0x235d); + ram_table->crgb_slope[4] = cpu_to_be16(0x2042); + ram_table->crgb_slope[5] = cpu_to_be16(0x1dc3); + ram_table->crgb_slope[6] = cpu_to_be16(0x1b1a); + ram_table->crgb_slope[7] = cpu_to_be16(0x1910); + + fill_backlight_transform_table_v_2_2( + params, ram_table, true); +} + +static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params, bool big_endian) +{ + unsigned int i, j; + unsigned int set = params.set; + + ram_table->flags = 0x0; + ram_table->min_abm_backlight = (uint16_t)((big_endian) ? + cpu_to_be16(params.min_abm_backlight) : + cpu_to_le16(params.min_abm_backlight)); + + for (i = 0; i < NUM_AGGR_LEVEL; i++) { + ram_table->hybrid_factor[i] = (uint8_t)abm_settings[set][i].brightness_gain; + ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor; + ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain; + ram_table->min_knee[i] = abm_settings[set][i].min_knee; + ram_table->max_knee[i] = abm_settings[set][i].max_knee; + + for (j = 0; j < NUM_AMBI_LEVEL; j++) { + ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction; + ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction; + ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain; + ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain; + } + } + + ram_table->iir_curve[0] = 0x65; + ram_table->iir_curve[1] = 0x65; + ram_table->iir_curve[2] = 0x65; + ram_table->iir_curve[3] = 0x65; + ram_table->iir_curve[4] = 0x65; + + //Gamma 2.2 + ram_table->crgb_thresh[0] = bswap16_based_on_endian(big_endian, 0x127c); + ram_table->crgb_thresh[1] = bswap16_based_on_endian(big_endian, 0x151b); + ram_table->crgb_thresh[2] = bswap16_based_on_endian(big_endian, 0x17d5); + ram_table->crgb_thresh[3] = bswap16_based_on_endian(big_endian, 0x1a56); + ram_table->crgb_thresh[4] = bswap16_based_on_endian(big_endian, 0x1c83); + ram_table->crgb_thresh[5] = bswap16_based_on_endian(big_endian, 0x1e72); + ram_table->crgb_thresh[6] = bswap16_based_on_endian(big_endian, 0x20f0); + ram_table->crgb_thresh[7] = bswap16_based_on_endian(big_endian, 0x232b); + ram_table->crgb_offset[0] = bswap16_based_on_endian(big_endian, 0x2999); + ram_table->crgb_offset[1] = bswap16_based_on_endian(big_endian, 0x3999); + ram_table->crgb_offset[2] = bswap16_based_on_endian(big_endian, 0x4666); + ram_table->crgb_offset[3] = bswap16_based_on_endian(big_endian, 0x5999); + ram_table->crgb_offset[4] = bswap16_based_on_endian(big_endian, 0x6333); + ram_table->crgb_offset[5] = bswap16_based_on_endian(big_endian, 0x7800); + ram_table->crgb_offset[6] = bswap16_based_on_endian(big_endian, 0x8c00); + ram_table->crgb_offset[7] = bswap16_based_on_endian(big_endian, 0xa000); + ram_table->crgb_slope[0] = bswap16_based_on_endian(big_endian, 0x3609); + ram_table->crgb_slope[1] = bswap16_based_on_endian(big_endian, 0x2dfa); + ram_table->crgb_slope[2] = bswap16_based_on_endian(big_endian, 0x27ea); + ram_table->crgb_slope[3] = bswap16_based_on_endian(big_endian, 0x235d); + ram_table->crgb_slope[4] = bswap16_based_on_endian(big_endian, 0x2042); + ram_table->crgb_slope[5] = bswap16_based_on_endian(big_endian, 0x1dc3); + ram_table->crgb_slope[6] = bswap16_based_on_endian(big_endian, 0x1b1a); + ram_table->crgb_slope[7] = bswap16_based_on_endian(big_endian, 0x1910); + + fill_backlight_transform_table_v_2_2( + params, ram_table, big_endian); +} + +bool dmub_init_abm_config(struct resource_pool *res_pool, + struct dmcu_iram_parameters params, + unsigned int inst) +{ + struct iram_table_v_2_2 ram_table; + struct abm_config_table config; + unsigned int set = params.set; + bool result = false; + uint32_t i, j = 0; + + if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) + return false; + + memset(&ram_table, 0, sizeof(ram_table)); + memset(&config, 0, sizeof(config)); + + fill_iram_v_2_3(&ram_table, params, false); + + // We must copy to structure that is aligned to 32-bit + for (i = 0; i < NUM_POWER_FN_SEGS; i++) { + config.crgb_thresh[i] = ram_table.crgb_thresh[i]; + config.crgb_offset[i] = ram_table.crgb_offset[i]; + config.crgb_slope[i] = ram_table.crgb_slope[i]; + } + + for (i = 0; i < NUM_BL_CURVE_SEGS; i++) { + config.backlight_thresholds[i] = ram_table.backlight_thresholds[i]; + config.backlight_offsets[i] = ram_table.backlight_offsets[i]; + } + + for (i = 0; i < NUM_AMBI_LEVEL; i++) + config.iir_curve[i] = ram_table.iir_curve[i]; + + for (i = 0; i < NUM_AMBI_LEVEL; i++) { + for (j = 0; j < NUM_AGGR_LEVEL; j++) { + config.min_reduction[i][j] = ram_table.min_reduction[i][j]; + config.max_reduction[i][j] = ram_table.max_reduction[i][j]; + config.bright_pos_gain[i][j] = ram_table.bright_pos_gain[i][j]; + config.dark_pos_gain[i][j] = ram_table.dark_pos_gain[i][j]; + } + } + + for (i = 0; i < NUM_AGGR_LEVEL; i++) { + config.hybrid_factor[i] = ram_table.hybrid_factor[i]; + config.contrast_factor[i] = ram_table.contrast_factor[i]; + config.deviation_gain[i] = ram_table.deviation_gain[i]; + config.min_knee[i] = ram_table.min_knee[i]; + config.max_knee[i] = ram_table.max_knee[i]; + } + + if (params.backlight_ramping_override) { + + ASSERT(params.backlight_ramping_reduction <= 0xFFFF); + ASSERT(params.backlight_ramping_start <= 0xFFFF); + for (i = 0; i < NUM_AGGR_LEVEL; i++) { + config.blRampReduction[i] = (uint16_t)params.backlight_ramping_reduction; + config.blRampStart[i] = (uint16_t)params.backlight_ramping_start; + } + } else { + for (i = 0; i < NUM_AGGR_LEVEL; i++) { + config.blRampReduction[i] = abm_settings[set][i].blRampReduction; + config.blRampStart[i] = abm_settings[set][i].blRampStart; + } + } + + config.min_abm_backlight = ram_table.min_abm_backlight; + + if (res_pool->multiple_abms[inst]) { + result = res_pool->multiple_abms[inst]->funcs->init_abm_config( + res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); + } else + result = res_pool->abm->funcs->init_abm_config( + res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0); + + return result; +} + +bool dmcu_load_iram(struct dmcu *dmcu, + struct dmcu_iram_parameters params) +{ + unsigned char ram_table[IRAM_SIZE]; + bool result = false; + + if (dmcu == NULL) + return false; + + if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu)) + return true; + + memset(&ram_table, 0, sizeof(ram_table)); + + if (dmcu->dmcu_version.abm_version == 0x24) { + fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true); + result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table), + IRAM_RESERVE_AREA_START_V2_2); + } else if (dmcu->dmcu_version.abm_version == 0x23) { + fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true); + + result = dmcu->funcs->load_iram( + dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2); + } else if (dmcu->dmcu_version.abm_version == 0x22) { + fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params); + + result = dmcu->funcs->load_iram( + dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2); + } else { + fill_iram_v_2((struct iram_table_v_2 *)ram_table, params); + + result = dmcu->funcs->load_iram( + dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2); + + if (result) + result = dmcu->funcs->load_iram( + dmcu, IRAM_RESERVE_AREA_END_V2 + 1, + (char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1, + sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1); + } + + return result; +} + +bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_backlight_caps *caps) +{ + unsigned int data_points_size; + uint64_t caps_size; + + if (config_no >= ARRAY_SIZE(custom_backlight_profiles)) + return false; + + data_points_size = custom_backlight_profiles[config_no].num_data_points + * sizeof(custom_backlight_profiles[config_no].data_points[0]); + + caps_size = sizeof(struct dm_acpi_atif_backlight_caps) - sizeof(caps->data_points) + data_points_size; + ASSERT(caps_size <= 0xFFFF); + caps->size = (uint16_t)caps_size; + caps->flags = 0; + caps->error_code = 0; + caps->ac_level_percentage = custom_backlight_profiles[config_no].ac_level_percentage; + caps->dc_level_percentage = custom_backlight_profiles[config_no].dc_level_percentage; + caps->min_input_signal = custom_backlight_profiles[config_no].min_input_signal; + caps->max_input_signal = custom_backlight_profiles[config_no].max_input_signal; + caps->num_data_points = (uint8_t)custom_backlight_profiles[config_no].num_data_points; + memcpy(caps->data_points, custom_backlight_profiles[config_no].data_points, data_points_size); + return true; +} diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index 5d444e9eb38f..bf0c5901b4ee 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -33,1072 +33,7 @@ #define bswap16_based_on_endian(big_endian, value) \ ((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value)) -/* Possible Min Reduction config from least aggressive to most aggressive - * 0 1 2 3 4 5 6 7 8 9 10 11 12 - * 100 98.0 94.1 94.1 85.1 80.3 75.3 69.4 60.0 57.6 50.2 49.8 40.0 % - */ -static const unsigned char min_reduction_table[13] = { -0xff, 0xfa, 0xf0, 0xf0, 0xd9, 0xcd, 0xc0, 0xb1, 0x99, 0x93, 0x80, 0x82, 0x66}; - -/* Possible Max Reduction configs from least aggressive to most aggressive - * 0 1 2 3 4 5 6 7 8 9 10 11 12 - * 96.1 89.8 85.1 80.3 69.4 64.7 64.7 50.2 39.6 30.2 30.2 30.2 19.6 % - */ -static const unsigned char max_reduction_table[13] = { -0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32}; - -/* Possible ABM 2.2 Min Reduction configs from least aggressive to most aggressive - * 0 1 2 3 4 5 6 7 8 9 10 11 12 - * 100 100 100 100 100 100 100 100 100 92.2 83.1 75.3 75.3 % - */ -static const unsigned char min_reduction_table_v_2_2[13] = { -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xd4, 0xc0, 0xc0}; - -/* Possible ABM 2.2 Max Reduction configs from least aggressive to most aggressive - * 0 1 2 3 4 5 6 7 8 9 10 11 12 - * 96.1 89.8 74.9 69.4 64.7 52.2 48.6 39.6 30.2 25.1 19.6 12.5 12.5 % - */ -static const unsigned char max_reduction_table_v_2_2[13] = { -0xf5, 0xe5, 0xbf, 0xb1, 0xa5, 0x85, 0x7c, 0x65, 0x4d, 0x40, 0x32, 0x20, 0x20}; - -/* Predefined ABM configuration sets. We may have different configuration sets - * in order to satisfy different power/quality requirements. - */ -static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_level] = { -/* ABM Level 1, ABM Level 2, ABM Level 3, ABM Level 4 */ -{ 2, 5, 7, 8 }, /* Default - Medium aggressiveness */ -{ 2, 5, 8, 11 }, /* Alt #1 - Increased aggressiveness */ -{ 0, 2, 4, 8 }, /* Alt #2 - Minimal aggressiveness */ -{ 3, 6, 10, 12 }, /* Alt #3 - Super aggressiveness */ -}; - -struct abm_parameters { - unsigned char min_reduction; - unsigned char max_reduction; - unsigned char bright_pos_gain; - unsigned char dark_pos_gain; - unsigned char brightness_gain; - unsigned char contrast_factor; - unsigned char deviation_gain; - unsigned char min_knee; - unsigned char max_knee; - unsigned short blRampReduction; - unsigned short blRampStart; -}; - -static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = { -// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart - {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xf777, 0xcccc}, - {0xde, 0x85, 0x20, 0x00, 0xe0, 0x90, 0xa8, 0x40, 0xc8, 0xf777, 0xcccc}, - {0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xeeee, 0x9999}, - {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xe333, 0xb333}, -}; - -static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = { -// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart - {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, - {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, - {0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, - {0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, -}; - -static const struct abm_parameters abm_settings_config2[abm_defines_max_level] = { -// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart - {0xf0, 0xbf, 0x20, 0x00, 0x88, 0x99, 0xb3, 0x40, 0xe0, 0x0000, 0xcccc}, - {0xd8, 0x85, 0x20, 0x00, 0x70, 0x90, 0xa8, 0x40, 0xc8, 0x0700, 0xb333}, - {0xb8, 0x58, 0x20, 0x00, 0x64, 0x88, 0x78, 0x70, 0xa0, 0x7000, 0x9999}, - {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xc333, 0xb333}, -}; - -static const struct abm_parameters * const abm_settings[] = { - abm_settings_config0, - abm_settings_config1, - abm_settings_config2, -}; - -static const struct dm_bl_data_point custom_backlight_curve0[] = { - {2, 14}, {4, 16}, {6, 18}, {8, 21}, {10, 23}, {12, 26}, {14, 29}, {16, 32}, {18, 35}, - {20, 38}, {22, 41}, {24, 44}, {26, 48}, {28, 52}, {30, 55}, {32, 59}, {34, 62}, - {36, 67}, {38, 71}, {40, 75}, {42, 80}, {44, 84}, {46, 88}, {48, 93}, {50, 98}, - {52, 103}, {54, 108}, {56, 113}, {58, 118}, {60, 123}, {62, 129}, {64, 135}, {66, 140}, - {68, 146}, {70, 152}, {72, 158}, {74, 164}, {76, 171}, {78, 177}, {80, 183}, {82, 190}, - {84, 197}, {86, 204}, {88, 211}, {90, 218}, {92, 225}, {94, 232}, {96, 240}, {98, 247}}; - -struct custom_backlight_profile { - uint8_t ac_level_percentage; - uint8_t dc_level_percentage; - uint8_t min_input_signal; - uint8_t max_input_signal; - uint8_t num_data_points; - const struct dm_bl_data_point *data_points; -}; - -static const struct custom_backlight_profile custom_backlight_profiles[] = { - {100, 32, 12, 255, ARRAY_SIZE(custom_backlight_curve0), custom_backlight_curve0}, -}; - -#define NUM_AMBI_LEVEL 5 -#define NUM_AGGR_LEVEL 4 -#define NUM_POWER_FN_SEGS 8 -#define NUM_BL_CURVE_SEGS 16 -#define IRAM_SIZE 256 - -#define IRAM_RESERVE_AREA_START_V2 0xF0 // reserve 0xF0~0xF6 are write by DMCU only -#define IRAM_RESERVE_AREA_END_V2 0xF6 // reserve 0xF0~0xF6 are write by DMCU only - -#define IRAM_RESERVE_AREA_START_V2_2 0xF0 // reserve 0xF0~0xFF are write by DMCU only -#define IRAM_RESERVE_AREA_END_V2_2 0xFF // reserve 0xF0~0xFF are write by DMCU only - -#pragma pack(push, 1) -/* NOTE: iRAM is 256B in size */ -struct iram_table_v_2 { - /* flags */ - uint16_t min_abm_backlight; /* 0x00 U16 */ - - /* parameters for ABM2.0 algorithm */ - uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */ - uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */ - uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */ - uint8_t bright_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */ - uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x52 U2.6 */ - uint8_t dark_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x66 U2.6 */ - uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x7a U0.8 */ - uint8_t deviation_gain; /* 0x7f U0.8 */ - - /* parameters for crgb conversion */ - uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */ - uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */ - uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */ - - /* parameters for custom curve */ - /* thresholds for brightness --> backlight */ - uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */ - /* offsets for brightness --> backlight */ - uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */ - - /* For reading PSR State directly from IRAM */ - uint8_t psr_state; /* 0xf0 */ - uint8_t dmcu_mcp_interface_version; /* 0xf1 */ - uint8_t dmcu_abm_feature_version; /* 0xf2 */ - uint8_t dmcu_psr_feature_version; /* 0xf3 */ - uint16_t dmcu_version; /* 0xf4 */ - uint8_t dmcu_state; /* 0xf6 */ - - uint16_t blRampReduction; /* 0xf7 */ - uint16_t blRampStart; /* 0xf9 */ - uint8_t dummy5; /* 0xfb */ - uint8_t dummy6; /* 0xfc */ - uint8_t dummy7; /* 0xfd */ - uint8_t dummy8; /* 0xfe */ - uint8_t dummy9; /* 0xff */ -}; - -struct iram_table_v_2_2 { - /* flags */ - uint16_t flags; /* 0x00 U16 */ - - /* parameters for ABM2.2 algorithm */ - uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */ - uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */ - uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */ - uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */ - uint8_t hybrid_factor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */ - uint8_t contrast_factor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */ - uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a U0.8 */ - uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x5e U0.8 */ - uint8_t min_knee[NUM_AGGR_LEVEL]; /* 0x63 U0.8 */ - uint8_t max_knee[NUM_AGGR_LEVEL]; /* 0x67 U0.8 */ - uint16_t min_abm_backlight; /* 0x6b U16 */ - uint8_t pad[19]; /* 0x6d U0.8 */ - - /* parameters for crgb conversion */ - uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */ - uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */ - uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */ - - /* parameters for custom curve */ - /* thresholds for brightness --> backlight */ - uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */ - /* offsets for brightness --> backlight */ - uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */ - - /* For reading PSR State directly from IRAM */ - uint8_t psr_state; /* 0xf0 */ - uint8_t dmcu_mcp_interface_version; /* 0xf1 */ - uint8_t dmcu_abm_feature_version; /* 0xf2 */ - uint8_t dmcu_psr_feature_version; /* 0xf3 */ - uint16_t dmcu_version; /* 0xf4 */ - uint8_t dmcu_state; /* 0xf6 */ - - uint8_t dummy1; /* 0xf7 */ - uint8_t dummy2; /* 0xf8 */ - uint8_t dummy3; /* 0xf9 */ - uint8_t dummy4; /* 0xfa */ - uint8_t dummy5; /* 0xfb */ - uint8_t dummy6; /* 0xfc */ - uint8_t dummy7; /* 0xfd */ - uint8_t dummy8; /* 0xfe */ - uint8_t dummy9; /* 0xff */ -}; -#pragma pack(pop) - -static void fill_backlight_transform_table(struct dmcu_iram_parameters params, - struct iram_table_v_2 *table) -{ - unsigned int i; - unsigned int num_entries = NUM_BL_CURVE_SEGS; - unsigned int lut_index; - - table->backlight_thresholds[0] = 0; - ASSERT(params.backlight_lut_array[0] <= 0xFFFF); - table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0]; - table->backlight_thresholds[num_entries-1] = 0xFFFF; - ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF); - table->backlight_offsets[num_entries-1] = - (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1]; - - /* Setup all brightness levels between 0% and 100% exclusive - * Fills brightness-to-backlight transform table. Backlight custom curve - * describes transform from brightness to backlight. It will be defined - * as set of thresholds and set of offsets, together, implying - * extrapolation of custom curve into 16 uniformly spanned linear - * segments. Each threshold/offset represented by 16 bit entry in - * format U4.10. - */ - for (i = 1; i+1 < num_entries; i++) { - lut_index = (params.backlight_lut_array_size - 1) * i / (num_entries - 1); - - ASSERT(lut_index < params.backlight_lut_array_size); - - unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries); - unsigned int offset_val = params.backlight_lut_array[lut_index]; - - ASSERT(threshold_val <= 0xFFFF); - ASSERT(offset_val <= 0xFFFF); - - table->backlight_thresholds[i] = cpu_to_be16((uint16_t)threshold_val); - table->backlight_offsets[i] = cpu_to_be16((uint16_t)offset_val); - } -} - -static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters params, - struct iram_table_v_2_2 *table, bool big_endian) -{ - unsigned int i; - unsigned int num_entries = NUM_BL_CURVE_SEGS; - unsigned int lut_index; - - table->backlight_thresholds[0] = 0; - ASSERT(params.backlight_lut_array[0] <= 0xFFFF); - table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0]; - table->backlight_thresholds[num_entries-1] = 0xFFFF; - ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF); - table->backlight_offsets[num_entries-1] = - (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1]; - - /* Setup all brightness levels between 0% and 100% exclusive - * Fills brightness-to-backlight transform table. Backlight custom curve - * describes transform from brightness to backlight. It will be defined - * as set of thresholds and set of offsets, together, implying - * extrapolation of custom curve into 16 uniformly spanned linear - * segments. Each threshold/offset represented by 16 bit entry in - * format U4.10. - */ - for (i = 1; i+1 < num_entries; i++) { - lut_index = DIV_ROUNDUP((i * params.backlight_lut_array_size), num_entries); - ASSERT(lut_index < params.backlight_lut_array_size); - - unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries); - unsigned int offset_val = params.backlight_lut_array[lut_index]; - - ASSERT(threshold_val <= 0xFFFF); - ASSERT(offset_val <= 0xFFFF); - - table->backlight_thresholds[i] = (big_endian) ? - cpu_to_be16((uint16_t)threshold_val) : cpu_to_le16((uint16_t)threshold_val); - table->backlight_offsets[i] = (big_endian) ? - cpu_to_be16((uint16_t)offset_val) : cpu_to_le16((uint16_t)offset_val); - } -} - -static void fill_iram_v_2(struct iram_table_v_2 *ram_table, struct dmcu_iram_parameters params) -{ - unsigned int set = params.set; - - ram_table->min_abm_backlight = - cpu_to_be16(params.min_abm_backlight); - ram_table->deviation_gain = 0xb3; - - ram_table->blRampReduction = - cpu_to_be16(params.backlight_ramping_reduction); - ram_table->blRampStart = - cpu_to_be16(params.backlight_ramping_start); - - ram_table->min_reduction[0][0] = min_reduction_table[abm_config[set][0]]; - ram_table->min_reduction[1][0] = min_reduction_table[abm_config[set][0]]; - ram_table->min_reduction[2][0] = min_reduction_table[abm_config[set][0]]; - ram_table->min_reduction[3][0] = min_reduction_table[abm_config[set][0]]; - ram_table->min_reduction[4][0] = min_reduction_table[abm_config[set][0]]; - ram_table->max_reduction[0][0] = max_reduction_table[abm_config[set][0]]; - ram_table->max_reduction[1][0] = max_reduction_table[abm_config[set][0]]; - ram_table->max_reduction[2][0] = max_reduction_table[abm_config[set][0]]; - ram_table->max_reduction[3][0] = max_reduction_table[abm_config[set][0]]; - ram_table->max_reduction[4][0] = max_reduction_table[abm_config[set][0]]; - - ram_table->min_reduction[0][1] = min_reduction_table[abm_config[set][1]]; - ram_table->min_reduction[1][1] = min_reduction_table[abm_config[set][1]]; - ram_table->min_reduction[2][1] = min_reduction_table[abm_config[set][1]]; - ram_table->min_reduction[3][1] = min_reduction_table[abm_config[set][1]]; - ram_table->min_reduction[4][1] = min_reduction_table[abm_config[set][1]]; - ram_table->max_reduction[0][1] = max_reduction_table[abm_config[set][1]]; - ram_table->max_reduction[1][1] = max_reduction_table[abm_config[set][1]]; - ram_table->max_reduction[2][1] = max_reduction_table[abm_config[set][1]]; - ram_table->max_reduction[3][1] = max_reduction_table[abm_config[set][1]]; - ram_table->max_reduction[4][1] = max_reduction_table[abm_config[set][1]]; - - ram_table->min_reduction[0][2] = min_reduction_table[abm_config[set][2]]; - ram_table->min_reduction[1][2] = min_reduction_table[abm_config[set][2]]; - ram_table->min_reduction[2][2] = min_reduction_table[abm_config[set][2]]; - ram_table->min_reduction[3][2] = min_reduction_table[abm_config[set][2]]; - ram_table->min_reduction[4][2] = min_reduction_table[abm_config[set][2]]; - ram_table->max_reduction[0][2] = max_reduction_table[abm_config[set][2]]; - ram_table->max_reduction[1][2] = max_reduction_table[abm_config[set][2]]; - ram_table->max_reduction[2][2] = max_reduction_table[abm_config[set][2]]; - ram_table->max_reduction[3][2] = max_reduction_table[abm_config[set][2]]; - ram_table->max_reduction[4][2] = max_reduction_table[abm_config[set][2]]; - - ram_table->min_reduction[0][3] = min_reduction_table[abm_config[set][3]]; - ram_table->min_reduction[1][3] = min_reduction_table[abm_config[set][3]]; - ram_table->min_reduction[2][3] = min_reduction_table[abm_config[set][3]]; - ram_table->min_reduction[3][3] = min_reduction_table[abm_config[set][3]]; - ram_table->min_reduction[4][3] = min_reduction_table[abm_config[set][3]]; - ram_table->max_reduction[0][3] = max_reduction_table[abm_config[set][3]]; - ram_table->max_reduction[1][3] = max_reduction_table[abm_config[set][3]]; - ram_table->max_reduction[2][3] = max_reduction_table[abm_config[set][3]]; - ram_table->max_reduction[3][3] = max_reduction_table[abm_config[set][3]]; - ram_table->max_reduction[4][3] = max_reduction_table[abm_config[set][3]]; - - ram_table->bright_pos_gain[0][0] = 0x20; - ram_table->bright_pos_gain[0][1] = 0x20; - ram_table->bright_pos_gain[0][2] = 0x20; - ram_table->bright_pos_gain[0][3] = 0x20; - ram_table->bright_pos_gain[1][0] = 0x20; - ram_table->bright_pos_gain[1][1] = 0x20; - ram_table->bright_pos_gain[1][2] = 0x20; - ram_table->bright_pos_gain[1][3] = 0x20; - ram_table->bright_pos_gain[2][0] = 0x20; - ram_table->bright_pos_gain[2][1] = 0x20; - ram_table->bright_pos_gain[2][2] = 0x20; - ram_table->bright_pos_gain[2][3] = 0x20; - ram_table->bright_pos_gain[3][0] = 0x20; - ram_table->bright_pos_gain[3][1] = 0x20; - ram_table->bright_pos_gain[3][2] = 0x20; - ram_table->bright_pos_gain[3][3] = 0x20; - ram_table->bright_pos_gain[4][0] = 0x20; - ram_table->bright_pos_gain[4][1] = 0x20; - ram_table->bright_pos_gain[4][2] = 0x20; - ram_table->bright_pos_gain[4][3] = 0x20; - ram_table->bright_neg_gain[0][0] = 0x00; - ram_table->bright_neg_gain[0][1] = 0x00; - ram_table->bright_neg_gain[0][2] = 0x00; - ram_table->bright_neg_gain[0][3] = 0x00; - ram_table->bright_neg_gain[1][0] = 0x00; - ram_table->bright_neg_gain[1][1] = 0x00; - ram_table->bright_neg_gain[1][2] = 0x00; - ram_table->bright_neg_gain[1][3] = 0x00; - ram_table->bright_neg_gain[2][0] = 0x00; - ram_table->bright_neg_gain[2][1] = 0x00; - ram_table->bright_neg_gain[2][2] = 0x00; - ram_table->bright_neg_gain[2][3] = 0x00; - ram_table->bright_neg_gain[3][0] = 0x00; - ram_table->bright_neg_gain[3][1] = 0x00; - ram_table->bright_neg_gain[3][2] = 0x00; - ram_table->bright_neg_gain[3][3] = 0x00; - ram_table->bright_neg_gain[4][0] = 0x00; - ram_table->bright_neg_gain[4][1] = 0x00; - ram_table->bright_neg_gain[4][2] = 0x00; - ram_table->bright_neg_gain[4][3] = 0x00; - ram_table->dark_pos_gain[0][0] = 0x00; - ram_table->dark_pos_gain[0][1] = 0x00; - ram_table->dark_pos_gain[0][2] = 0x00; - ram_table->dark_pos_gain[0][3] = 0x00; - ram_table->dark_pos_gain[1][0] = 0x00; - ram_table->dark_pos_gain[1][1] = 0x00; - ram_table->dark_pos_gain[1][2] = 0x00; - ram_table->dark_pos_gain[1][3] = 0x00; - ram_table->dark_pos_gain[2][0] = 0x00; - ram_table->dark_pos_gain[2][1] = 0x00; - ram_table->dark_pos_gain[2][2] = 0x00; - ram_table->dark_pos_gain[2][3] = 0x00; - ram_table->dark_pos_gain[3][0] = 0x00; - ram_table->dark_pos_gain[3][1] = 0x00; - ram_table->dark_pos_gain[3][2] = 0x00; - ram_table->dark_pos_gain[3][3] = 0x00; - ram_table->dark_pos_gain[4][0] = 0x00; - ram_table->dark_pos_gain[4][1] = 0x00; - ram_table->dark_pos_gain[4][2] = 0x00; - ram_table->dark_pos_gain[4][3] = 0x00; - ram_table->dark_neg_gain[0][0] = 0x00; - ram_table->dark_neg_gain[0][1] = 0x00; - ram_table->dark_neg_gain[0][2] = 0x00; - ram_table->dark_neg_gain[0][3] = 0x00; - ram_table->dark_neg_gain[1][0] = 0x00; - ram_table->dark_neg_gain[1][1] = 0x00; - ram_table->dark_neg_gain[1][2] = 0x00; - ram_table->dark_neg_gain[1][3] = 0x00; - ram_table->dark_neg_gain[2][0] = 0x00; - ram_table->dark_neg_gain[2][1] = 0x00; - ram_table->dark_neg_gain[2][2] = 0x00; - ram_table->dark_neg_gain[2][3] = 0x00; - ram_table->dark_neg_gain[3][0] = 0x00; - ram_table->dark_neg_gain[3][1] = 0x00; - ram_table->dark_neg_gain[3][2] = 0x00; - ram_table->dark_neg_gain[3][3] = 0x00; - ram_table->dark_neg_gain[4][0] = 0x00; - ram_table->dark_neg_gain[4][1] = 0x00; - ram_table->dark_neg_gain[4][2] = 0x00; - ram_table->dark_neg_gain[4][3] = 0x00; - - ram_table->iir_curve[0] = 0x65; - ram_table->iir_curve[1] = 0x65; - ram_table->iir_curve[2] = 0x65; - ram_table->iir_curve[3] = 0x65; - ram_table->iir_curve[4] = 0x65; - - //Gamma 2.4 - ram_table->crgb_thresh[0] = cpu_to_be16(0x13b6); - ram_table->crgb_thresh[1] = cpu_to_be16(0x1648); - ram_table->crgb_thresh[2] = cpu_to_be16(0x18e3); - ram_table->crgb_thresh[3] = cpu_to_be16(0x1b41); - ram_table->crgb_thresh[4] = cpu_to_be16(0x1d46); - ram_table->crgb_thresh[5] = cpu_to_be16(0x1f21); - ram_table->crgb_thresh[6] = cpu_to_be16(0x2167); - ram_table->crgb_thresh[7] = cpu_to_be16(0x2384); - ram_table->crgb_offset[0] = cpu_to_be16(0x2999); - ram_table->crgb_offset[1] = cpu_to_be16(0x3999); - ram_table->crgb_offset[2] = cpu_to_be16(0x4666); - ram_table->crgb_offset[3] = cpu_to_be16(0x5999); - ram_table->crgb_offset[4] = cpu_to_be16(0x6333); - ram_table->crgb_offset[5] = cpu_to_be16(0x7800); - ram_table->crgb_offset[6] = cpu_to_be16(0x8c00); - ram_table->crgb_offset[7] = cpu_to_be16(0xa000); - ram_table->crgb_slope[0] = cpu_to_be16(0x3147); - ram_table->crgb_slope[1] = cpu_to_be16(0x2978); - ram_table->crgb_slope[2] = cpu_to_be16(0x23a2); - ram_table->crgb_slope[3] = cpu_to_be16(0x1f55); - ram_table->crgb_slope[4] = cpu_to_be16(0x1c63); - ram_table->crgb_slope[5] = cpu_to_be16(0x1a0f); - ram_table->crgb_slope[6] = cpu_to_be16(0x178d); - ram_table->crgb_slope[7] = cpu_to_be16(0x15ab); - - fill_backlight_transform_table( - params, ram_table); -} - -static void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params) -{ - unsigned int set = params.set; - - ram_table->flags = 0x0; - - ram_table->min_abm_backlight = - cpu_to_be16(params.min_abm_backlight); - - ram_table->deviation_gain[0] = 0xb3; - ram_table->deviation_gain[1] = 0xa8; - ram_table->deviation_gain[2] = 0x98; - ram_table->deviation_gain[3] = 0x68; - - ram_table->min_reduction[0][0] = min_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->min_reduction[1][0] = min_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->min_reduction[2][0] = min_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->min_reduction[3][0] = min_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->min_reduction[4][0] = min_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->max_reduction[0][0] = max_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->max_reduction[1][0] = max_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->max_reduction[2][0] = max_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->max_reduction[3][0] = max_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->max_reduction[4][0] = max_reduction_table_v_2_2[abm_config[set][0]]; - - ram_table->min_reduction[0][1] = min_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->min_reduction[1][1] = min_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->min_reduction[2][1] = min_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->min_reduction[3][1] = min_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->min_reduction[4][1] = min_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->max_reduction[0][1] = max_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->max_reduction[1][1] = max_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->max_reduction[2][1] = max_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->max_reduction[3][1] = max_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->max_reduction[4][1] = max_reduction_table_v_2_2[abm_config[set][1]]; - - ram_table->min_reduction[0][2] = min_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->min_reduction[1][2] = min_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->min_reduction[2][2] = min_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->min_reduction[3][2] = min_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->min_reduction[4][2] = min_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->max_reduction[0][2] = max_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->max_reduction[1][2] = max_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->max_reduction[2][2] = max_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->max_reduction[3][2] = max_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->max_reduction[4][2] = max_reduction_table_v_2_2[abm_config[set][2]]; - - ram_table->min_reduction[0][3] = min_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->min_reduction[1][3] = min_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->min_reduction[2][3] = min_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->min_reduction[3][3] = min_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->min_reduction[4][3] = min_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->max_reduction[0][3] = max_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->max_reduction[1][3] = max_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->max_reduction[2][3] = max_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->max_reduction[3][3] = max_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->max_reduction[4][3] = max_reduction_table_v_2_2[abm_config[set][3]]; - - ram_table->bright_pos_gain[0][0] = 0x20; - ram_table->bright_pos_gain[0][1] = 0x20; - ram_table->bright_pos_gain[0][2] = 0x20; - ram_table->bright_pos_gain[0][3] = 0x20; - ram_table->bright_pos_gain[1][0] = 0x20; - ram_table->bright_pos_gain[1][1] = 0x20; - ram_table->bright_pos_gain[1][2] = 0x20; - ram_table->bright_pos_gain[1][3] = 0x20; - ram_table->bright_pos_gain[2][0] = 0x20; - ram_table->bright_pos_gain[2][1] = 0x20; - ram_table->bright_pos_gain[2][2] = 0x20; - ram_table->bright_pos_gain[2][3] = 0x20; - ram_table->bright_pos_gain[3][0] = 0x20; - ram_table->bright_pos_gain[3][1] = 0x20; - ram_table->bright_pos_gain[3][2] = 0x20; - ram_table->bright_pos_gain[3][3] = 0x20; - ram_table->bright_pos_gain[4][0] = 0x20; - ram_table->bright_pos_gain[4][1] = 0x20; - ram_table->bright_pos_gain[4][2] = 0x20; - ram_table->bright_pos_gain[4][3] = 0x20; - - ram_table->dark_pos_gain[0][0] = 0x00; - ram_table->dark_pos_gain[0][1] = 0x00; - ram_table->dark_pos_gain[0][2] = 0x00; - ram_table->dark_pos_gain[0][3] = 0x00; - ram_table->dark_pos_gain[1][0] = 0x00; - ram_table->dark_pos_gain[1][1] = 0x00; - ram_table->dark_pos_gain[1][2] = 0x00; - ram_table->dark_pos_gain[1][3] = 0x00; - ram_table->dark_pos_gain[2][0] = 0x00; - ram_table->dark_pos_gain[2][1] = 0x00; - ram_table->dark_pos_gain[2][2] = 0x00; - ram_table->dark_pos_gain[2][3] = 0x00; - ram_table->dark_pos_gain[3][0] = 0x00; - ram_table->dark_pos_gain[3][1] = 0x00; - ram_table->dark_pos_gain[3][2] = 0x00; - ram_table->dark_pos_gain[3][3] = 0x00; - ram_table->dark_pos_gain[4][0] = 0x00; - ram_table->dark_pos_gain[4][1] = 0x00; - ram_table->dark_pos_gain[4][2] = 0x00; - ram_table->dark_pos_gain[4][3] = 0x00; - - ram_table->hybrid_factor[0] = 0xff; - ram_table->hybrid_factor[1] = 0xff; - ram_table->hybrid_factor[2] = 0xff; - ram_table->hybrid_factor[3] = 0xc0; - - ram_table->contrast_factor[0] = 0x99; - ram_table->contrast_factor[1] = 0x99; - ram_table->contrast_factor[2] = 0x90; - ram_table->contrast_factor[3] = 0x80; - - ram_table->iir_curve[0] = 0x65; - ram_table->iir_curve[1] = 0x65; - ram_table->iir_curve[2] = 0x65; - ram_table->iir_curve[3] = 0x65; - ram_table->iir_curve[4] = 0x65; - - //Gamma 2.2 - ram_table->crgb_thresh[0] = cpu_to_be16(0x127c); - ram_table->crgb_thresh[1] = cpu_to_be16(0x151b); - ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5); - ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56); - ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83); - ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72); - ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0); - ram_table->crgb_thresh[7] = cpu_to_be16(0x232b); - ram_table->crgb_offset[0] = cpu_to_be16(0x2999); - ram_table->crgb_offset[1] = cpu_to_be16(0x3999); - ram_table->crgb_offset[2] = cpu_to_be16(0x4666); - ram_table->crgb_offset[3] = cpu_to_be16(0x5999); - ram_table->crgb_offset[4] = cpu_to_be16(0x6333); - ram_table->crgb_offset[5] = cpu_to_be16(0x7800); - ram_table->crgb_offset[6] = cpu_to_be16(0x8c00); - ram_table->crgb_offset[7] = cpu_to_be16(0xa000); - ram_table->crgb_slope[0] = cpu_to_be16(0x3609); - ram_table->crgb_slope[1] = cpu_to_be16(0x2dfa); - ram_table->crgb_slope[2] = cpu_to_be16(0x27ea); - ram_table->crgb_slope[3] = cpu_to_be16(0x235d); - ram_table->crgb_slope[4] = cpu_to_be16(0x2042); - ram_table->crgb_slope[5] = cpu_to_be16(0x1dc3); - ram_table->crgb_slope[6] = cpu_to_be16(0x1b1a); - ram_table->crgb_slope[7] = cpu_to_be16(0x1910); - - fill_backlight_transform_table_v_2_2( - params, ram_table, true); -} - -static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params, bool big_endian) -{ - unsigned int i, j; - unsigned int set = params.set; - - ram_table->flags = 0x0; - ram_table->min_abm_backlight = (big_endian) ? - cpu_to_be16(params.min_abm_backlight) : - cpu_to_le16(params.min_abm_backlight); - - for (i = 0; i < NUM_AGGR_LEVEL; i++) { - ram_table->hybrid_factor[i] = abm_settings[set][i].brightness_gain; - ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor; - ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain; - ram_table->min_knee[i] = abm_settings[set][i].min_knee; - ram_table->max_knee[i] = abm_settings[set][i].max_knee; - - for (j = 0; j < NUM_AMBI_LEVEL; j++) { - ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction; - ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction; - ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain; - ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain; - } - } - - ram_table->iir_curve[0] = 0x65; - ram_table->iir_curve[1] = 0x65; - ram_table->iir_curve[2] = 0x65; - ram_table->iir_curve[3] = 0x65; - ram_table->iir_curve[4] = 0x65; - - //Gamma 2.2 - ram_table->crgb_thresh[0] = bswap16_based_on_endian(big_endian, 0x127c); - ram_table->crgb_thresh[1] = bswap16_based_on_endian(big_endian, 0x151b); - ram_table->crgb_thresh[2] = bswap16_based_on_endian(big_endian, 0x17d5); - ram_table->crgb_thresh[3] = bswap16_based_on_endian(big_endian, 0x1a56); - ram_table->crgb_thresh[4] = bswap16_based_on_endian(big_endian, 0x1c83); - ram_table->crgb_thresh[5] = bswap16_based_on_endian(big_endian, 0x1e72); - ram_table->crgb_thresh[6] = bswap16_based_on_endian(big_endian, 0x20f0); - ram_table->crgb_thresh[7] = bswap16_based_on_endian(big_endian, 0x232b); - ram_table->crgb_offset[0] = bswap16_based_on_endian(big_endian, 0x2999); - ram_table->crgb_offset[1] = bswap16_based_on_endian(big_endian, 0x3999); - ram_table->crgb_offset[2] = bswap16_based_on_endian(big_endian, 0x4666); - ram_table->crgb_offset[3] = bswap16_based_on_endian(big_endian, 0x5999); - ram_table->crgb_offset[4] = bswap16_based_on_endian(big_endian, 0x6333); - ram_table->crgb_offset[5] = bswap16_based_on_endian(big_endian, 0x7800); - ram_table->crgb_offset[6] = bswap16_based_on_endian(big_endian, 0x8c00); - ram_table->crgb_offset[7] = bswap16_based_on_endian(big_endian, 0xa000); - ram_table->crgb_slope[0] = bswap16_based_on_endian(big_endian, 0x3609); - ram_table->crgb_slope[1] = bswap16_based_on_endian(big_endian, 0x2dfa); - ram_table->crgb_slope[2] = bswap16_based_on_endian(big_endian, 0x27ea); - ram_table->crgb_slope[3] = bswap16_based_on_endian(big_endian, 0x235d); - ram_table->crgb_slope[4] = bswap16_based_on_endian(big_endian, 0x2042); - ram_table->crgb_slope[5] = bswap16_based_on_endian(big_endian, 0x1dc3); - ram_table->crgb_slope[6] = bswap16_based_on_endian(big_endian, 0x1b1a); - ram_table->crgb_slope[7] = bswap16_based_on_endian(big_endian, 0x1910); - - fill_backlight_transform_table_v_2_2( - params, ram_table, big_endian); -} - -bool dmub_init_abm_config(struct resource_pool *res_pool, - struct dmcu_iram_parameters params, - unsigned int inst) -{ - struct iram_table_v_2_2 ram_table; - struct abm_config_table config; - unsigned int set = params.set; - bool result = false; - uint32_t i, j = 0; - - if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) - return false; - - memset(&ram_table, 0, sizeof(ram_table)); - memset(&config, 0, sizeof(config)); - - fill_iram_v_2_3(&ram_table, params, false); - - // We must copy to structure that is aligned to 32-bit - for (i = 0; i < NUM_POWER_FN_SEGS; i++) { - config.crgb_thresh[i] = ram_table.crgb_thresh[i]; - config.crgb_offset[i] = ram_table.crgb_offset[i]; - config.crgb_slope[i] = ram_table.crgb_slope[i]; - } - - for (i = 0; i < NUM_BL_CURVE_SEGS; i++) { - config.backlight_thresholds[i] = ram_table.backlight_thresholds[i]; - config.backlight_offsets[i] = ram_table.backlight_offsets[i]; - } - - for (i = 0; i < NUM_AMBI_LEVEL; i++) - config.iir_curve[i] = ram_table.iir_curve[i]; - - for (i = 0; i < NUM_AMBI_LEVEL; i++) { - for (j = 0; j < NUM_AGGR_LEVEL; j++) { - config.min_reduction[i][j] = ram_table.min_reduction[i][j]; - config.max_reduction[i][j] = ram_table.max_reduction[i][j]; - config.bright_pos_gain[i][j] = ram_table.bright_pos_gain[i][j]; - config.dark_pos_gain[i][j] = ram_table.dark_pos_gain[i][j]; - } - } - - for (i = 0; i < NUM_AGGR_LEVEL; i++) { - config.hybrid_factor[i] = ram_table.hybrid_factor[i]; - config.contrast_factor[i] = ram_table.contrast_factor[i]; - config.deviation_gain[i] = ram_table.deviation_gain[i]; - config.min_knee[i] = ram_table.min_knee[i]; - config.max_knee[i] = ram_table.max_knee[i]; - } - - if (params.backlight_ramping_override) { - - ASSERT(params.backlight_ramping_reduction <= 0xFFFF); - ASSERT(params.backlight_ramping_start <= 0xFFFF); - for (i = 0; i < NUM_AGGR_LEVEL; i++) { - config.blRampReduction[i] = (uint16_t)params.backlight_ramping_reduction; - config.blRampStart[i] = (uint16_t)params.backlight_ramping_start; - } - } else { - for (i = 0; i < NUM_AGGR_LEVEL; i++) { - config.blRampReduction[i] = abm_settings[set][i].blRampReduction; - config.blRampStart[i] = abm_settings[set][i].blRampStart; - } - } - - config.min_abm_backlight = ram_table.min_abm_backlight; - - if (res_pool->multiple_abms[inst]) { - result = res_pool->multiple_abms[inst]->funcs->init_abm_config( - res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); - } else - result = res_pool->abm->funcs->init_abm_config( - res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0); - - return result; -} - -bool dmcu_load_iram(struct dmcu *dmcu, - struct dmcu_iram_parameters params) -{ - unsigned char ram_table[IRAM_SIZE]; - bool result = false; - - if (dmcu == NULL) - return false; - - if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu)) - return true; - - memset(&ram_table, 0, sizeof(ram_table)); - - if (dmcu->dmcu_version.abm_version == 0x24) { - fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true); - result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table), - IRAM_RESERVE_AREA_START_V2_2); - } else if (dmcu->dmcu_version.abm_version == 0x23) { - fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true); - - result = dmcu->funcs->load_iram( - dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2); - } else if (dmcu->dmcu_version.abm_version == 0x22) { - fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params); - - result = dmcu->funcs->load_iram( - dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2); - } else { - fill_iram_v_2((struct iram_table_v_2 *)ram_table, params); - - result = dmcu->funcs->load_iram( - dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2); - - if (result) - result = dmcu->funcs->load_iram( - dmcu, IRAM_RESERVE_AREA_END_V2 + 1, - (char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1, - sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1); - } - - return result; -} - -/* - * is_psr_su_specific_panel() - check if sink is AMD vendor-specific PSR-SU - * supported eDP device. - * - * @link: dc link pointer - * - * Return: true if AMDGPU vendor specific PSR-SU eDP panel - */ -bool is_psr_su_specific_panel(struct dc_link *link) -{ - bool isPSRSUSupported = false; - struct dpcd_caps *dpcd_caps = &link->dpcd_caps; - - if (dpcd_caps->edp_rev >= DP_EDP_14) { - if (dpcd_caps->psr_info.psr_version >= DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) - isPSRSUSupported = true; - /* - * Some panels will report PSR capabilities over additional DPCD bits. - * Such panels are approved despite reporting only PSR v3, as long as - * the additional bits are reported. - */ - if (dpcd_caps->sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) { - /* - * This is the temporary workaround to disable PSRSU when system turned on - * DSC function on the sepcific sink. - */ - if (dpcd_caps->psr_info.psr_version < DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) - isPSRSUSupported = false; - else if (dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && - ((dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x08) || - (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x07))) - isPSRSUSupported = false; - else if (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x03) - isPSRSUSupported = false; - else if (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x01) - isPSRSUSupported = false; - else if (dpcd_caps->psr_info.force_psrsu_cap == 0x1) - isPSRSUSupported = true; - } - } - - return isPSRSUSupported; -} - -/** - * mod_power_calc_psr_configs() - calculate/update generic psr configuration fields. - * @psr_config: [output], psr configuration structure to be updated - * @link: [input] dc link pointer - * @stream: [input] dc stream state pointer - * - * calculate and update the psr configuration fields that are not DM specific, i.e. such - * fields which are based on DPCD caps or timing information. To setup PSR in DMUB FW, - * this helper is assumed to be called before the call of the DC helper dc_link_setup_psr(). - * - * PSR config fields to be updated within the helper: - * - psr_rfb_setup_time - * - psr_sdp_transmit_line_num_deadline - * - line_time_in_us - * - su_y_granularity - * - su_granularity_required - * - psr_frame_capture_indication_req - * - psr_exit_link_training_required - * - * PSR config fields that are DM specific and NOT updated within the helper: - * - allow_smu_optimizations - * - allow_multi_disp_optimizations - */ -void mod_power_calc_psr_configs(struct psr_config *psr_config, - struct dc_link *link, - const struct dc_stream_state *stream) -{ - unsigned int num_vblank_lines = 0; - unsigned int vblank_time_in_us = 0; - unsigned int sdp_tx_deadline_in_us = 0; - unsigned int line_time_in_us = 0; - struct dpcd_caps *dpcd_caps = &link->dpcd_caps; - const int psr_setup_time_step_in_us = 55; /* refer to eDP spec DPCD 0x071h */ - - /* timing parameters */ - num_vblank_lines = stream->timing.v_total - - stream->timing.v_addressable - - stream->timing.v_border_top - - stream->timing.v_border_bottom; - - vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10); - - line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1; - - /** - * psr configuration fields - * - * as per eDP 1.5 pg. 377 of 459, DPCD 0x071h bits [3:1], psr setup time bits interpreted as below - * 000b <--> 330 us (default) - * 001b <--> 275 us - * 010b <--> 220 us - * 011b <--> 165 us - * 100b <--> 110 us - * 101b <--> 055 us - * 110b <--> 000 us - */ - psr_config->psr_rfb_setup_time = - (6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * psr_setup_time_step_in_us; - - if (psr_config->psr_rfb_setup_time > vblank_time_in_us) { - link->psr_settings.psr_frame_capture_indication_req = true; - link->psr_settings.psr_sdp_transmit_line_num_deadline = num_vblank_lines; - } else { - sdp_tx_deadline_in_us = vblank_time_in_us - psr_config->psr_rfb_setup_time; - - /* Set the last possible line SDP may be transmitted without violating the RFB setup time */ - link->psr_settings.psr_frame_capture_indication_req = false; - link->psr_settings.psr_sdp_transmit_line_num_deadline = sdp_tx_deadline_in_us / line_time_in_us; - } - - psr_config->psr_sdp_transmit_line_num_deadline = link->psr_settings.psr_sdp_transmit_line_num_deadline; - psr_config->line_time_in_us = line_time_in_us; - psr_config->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap; - psr_config->su_granularity_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED; - psr_config->psr_frame_capture_indication_req = link->psr_settings.psr_frame_capture_indication_req; - psr_config->psr_exit_link_training_required = - !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED; -} - -void init_replay_config(struct dc_link *link, struct replay_config *pr_config) -{ - link->replay_settings.config = *pr_config; -} - bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream) { return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal); } - -bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link, - struct dc_stream_state *stream, - struct psr_config *config) -{ - uint16_t pic_height; - uint16_t slice_height; - - config->dsc_slice_height = 0; - if (!(link->connector_signal & SIGNAL_TYPE_EDP) || - !dc->caps.edp_dsc_support || - link->panel_config.dsc.disable_dsc_edp || - !link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || - !stream->timing.dsc_cfg.num_slices_v) - return true; - - pic_height = stream->timing.v_addressable + - stream->timing.v_border_top + stream->timing.v_border_bottom; - - if (stream->timing.dsc_cfg.num_slices_v == 0) - return false; - - slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v; - config->dsc_slice_height = slice_height; - - if (slice_height) { - if (config->su_y_granularity && - (slice_height % config->su_y_granularity)) { - ASSERT(0); - return false; - } - } - - return true; -} - -void set_replay_frame_skip_number(struct dc_link *link, - enum replay_coasting_vtotal_type type, - uint32_t coasting_vtotal_refresh_rate_mhz, - uint32_t flicker_free_refresh_rate_mhz, - bool is_defer) -{ - uint32_t *frame_skip_number_array = NULL; - uint32_t frame_skip_number = 0; - - if (link == NULL) - return; - - if (false == link->replay_settings.config.frame_skip_supported) - return; - - if (flicker_free_refresh_rate_mhz == 0 || coasting_vtotal_refresh_rate_mhz == 0) - return; - - if (is_defer) - frame_skip_number_array = link->replay_settings.defer_frame_skip_number_table; - else - frame_skip_number_array = link->replay_settings.frame_skip_number_table; - - if (frame_skip_number_array == NULL) - return; - - frame_skip_number = coasting_vtotal_refresh_rate_mhz / flicker_free_refresh_rate_mhz; - - if (frame_skip_number >= 1) - frame_skip_number_array[type] = frame_skip_number - 1; - else - frame_skip_number_array[type] = 0; -} - -void set_replay_defer_update_coasting_vtotal(struct dc_link *link, - enum replay_coasting_vtotal_type type, - uint32_t vtotal) -{ - link->replay_settings.defer_update_coasting_vtotal_table[type] = vtotal; -} - -void update_replay_coasting_vtotal_from_defer(struct dc_link *link, - enum replay_coasting_vtotal_type type) -{ - link->replay_settings.coasting_vtotal_table[type] = - link->replay_settings.defer_update_coasting_vtotal_table[type]; - link->replay_settings.frame_skip_number_table[type] = - link->replay_settings.defer_frame_skip_number_table[type]; -} - -void set_replay_coasting_vtotal(struct dc_link *link, - enum replay_coasting_vtotal_type type, - uint32_t vtotal) -{ - link->replay_settings.coasting_vtotal_table[type] = vtotal; -} - -void set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link *link, uint16_t vtotal) -{ - link->replay_settings.low_rr_full_screen_video_pseudo_vtotal = vtotal; -} - -void calculate_replay_link_off_frame_count(struct dc_link *link, - uint16_t vtotal, uint16_t htotal) -{ - uint8_t max_link_off_frame_count = 0; - uint16_t max_deviation_line = 0, pixel_deviation_per_line = 0; - - if (!link || link->replay_settings.config.replay_version != DC_FREESYNC_REPLAY) - return; - - max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line; - pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line; - - if (htotal != 0 && vtotal != 0 && pixel_deviation_per_line != 0) - max_link_off_frame_count = htotal * max_deviation_line / (pixel_deviation_per_line * vtotal); - else - ASSERT(0); - - link->replay_settings.link_off_frame_count = max_link_off_frame_count; -} - -bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_backlight_caps *caps) -{ - unsigned int data_points_size; - uint64_t caps_size; - - if (config_no >= ARRAY_SIZE(custom_backlight_profiles)) - return false; - - data_points_size = custom_backlight_profiles[config_no].num_data_points - * sizeof(custom_backlight_profiles[config_no].data_points[0]); - - caps_size = sizeof(struct dm_acpi_atif_backlight_caps) - sizeof(caps->data_points) + data_points_size; - ASSERT(caps_size <= 0xFFFF); - caps->size = (uint16_t)caps_size; - caps->flags = 0; - caps->error_code = 0; - caps->ac_level_percentage = custom_backlight_profiles[config_no].ac_level_percentage; - caps->dc_level_percentage = custom_backlight_profiles[config_no].dc_level_percentage; - caps->min_input_signal = custom_backlight_profiles[config_no].min_input_signal; - caps->max_input_signal = custom_backlight_profiles[config_no].max_input_signal; - caps->num_data_points = custom_backlight_profiles[config_no].num_data_points; - memcpy(caps->data_points, custom_backlight_profiles[config_no].data_points, data_points_size); - return true; -} - -void reset_replay_dsync_error_count(struct dc_link *link) -{ - link->replay_settings.replay_desync_error_fail_count = 0; -} diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h index 87d31d9dce5a..600da3e33126 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h @@ -28,6 +28,7 @@ #include "dc/inc/hw/dmcu.h" #include "dc/inc/hw/abm.h" #include "dc/inc/core_types.h" +#include "mod_power.h" struct resource_pool; @@ -46,7 +47,99 @@ struct dmcu_iram_parameters { unsigned int min_abm_backlight; unsigned int set; }; +struct backlight_state { + /* HW uses u16.16 format for backlight PWM */ + unsigned int backlight_pwm; + /* DM may call power module to set backlight + * targeting percent brightness + */ + unsigned int backlight_millipercent; + /* DM may call power module to set backlight based on an explicit + * nits value. + */ + unsigned int backlight_millinit; + unsigned int frame_ramp; + bool smooth_brightness_enabled; + bool isHDR; +}; +struct power_entity { + struct dc_stream_state *stream; + struct psr_caps *caps; + struct mod_power_psr_context *psr_context; + /*PSR cached properties*/ + bool psr_enabled; + unsigned int psr_events; + unsigned int psr_power_opt; + unsigned int replay_events; +}; + +struct pwr_backlight_properties { + bool use_nits_based_brightness; + bool disable_fractional_pwm; + + unsigned int min_abm_backlight; + unsigned int num_backlight_levels; + + bool backlight_ramping_override; + unsigned int backlight_ramping_reduction; + unsigned int backlight_ramping_start; + + /* Backlight cached properties */ + unsigned int ac_backlight_percent; + unsigned int dc_backlight_percent; + + /* backlight LUT stored in HW u16.16 format*/ + unsigned int *backlight_lut; + unsigned int min_backlight_pwm; + unsigned int max_backlight_pwm; + unsigned int backlight_range; + + /* Describes the panel's min and max luminance in millinits measured + * on full white screen, in min and max backlight settings. + */ + unsigned int min_brightness_millinits; + unsigned int max_brightness_millinits; + unsigned int nits_range; + + bool backlight_caps_valid; + bool use_custom_backlight_caps; + unsigned int custom_backlight_caps_config_no; + bool use_linear_backlight_curve; +}; + +struct dmcu_varibright_cached_properties { + unsigned int varibright_config_setting; + unsigned int varibright_level; + unsigned int varibright_hw_level; + unsigned int def_varibright_level; + bool varibright_user_enable; + bool varibright_active; +}; + +struct core_power { + struct mod_power mod_public; + struct dc *dc; + struct power_entity *map; + struct dmcu_varibright_cached_properties varibright_prop; + struct pwr_backlight_properties bl_prop[MAX_NUM_EDP]; + struct backlight_state bl_state[MAX_NUM_EDP]; + unsigned int edp_num; + + bool psr_smu_optimizations_support; + bool multi_disp_optimizations_support; + + unsigned int num_entities; +}; + +union dmcu_abm_set_bl_params { + struct { + unsigned int gradual_change : 1; /* [0:0] */ + unsigned int reserved : 15; /* [15:1] */ + unsigned int frame_ramp : 16; /* [31:16] */ + } bits; + unsigned int u32All; +}; bool dmcu_load_iram(struct dmcu *dmcu, struct dmcu_iram_parameters params); bool dmub_init_abm_config(struct resource_pool *res_pool, @@ -86,4 +179,33 @@ bool fill_custom_backlight_caps(unsigned int config_no, void reset_replay_dsync_error_count(struct dc_link *link); void change_replay_to_psr(struct dc_link *link); void change_psr_to_replay(struct dc_link *link); +void initialize_backlight_caps(struct core_power *core_power, unsigned int inst); +unsigned int backlight_millipercent_to_pwm( + struct core_power *core_power, unsigned int millipercent, unsigned int inst); +unsigned int backlight_millipercent_to_millinit( + struct core_power *core_power, unsigned int millipercent, unsigned int inst); +void fill_backlight_level_params(struct core_power *core_power, + struct set_backlight_level_params *backlight_level_params, + int panel_inst, uint8_t aux_inst, unsigned int backlight_pwm, + enum backlight_control_type backlight_control_type, + unsigned int backlight_millinit, unsigned int transition_time_millisec, + bool is_hdr); +bool mod_power_hw_init_backlight(struct mod_power *mod_power); +void mod_power_update_backlight_on_mode_change( + struct core_power *core_power, + struct dc_link *link, + unsigned int panel_inst, + uint8_t aux_inst, + bool is_hdr); +unsigned int map_index_from_stream(struct core_power *core_power, + const struct dc_stream_state *stream); +bool mod_power_psr_notify_mode_change(struct mod_power *mod_power, + const struct dc_stream_state *stream, + struct dc_link *link, + unsigned int stream_index); +void mod_power_replay_notify_mode_change(struct mod_power *mod_power, + struct dc *dc, + struct dc_link *link, + const struct dc_stream_state *stream, + unsigned int stream_index); #endif /* MODULES_POWER_POWER_HELPERS_H_ */ diff --git a/drivers/gpu/drm/amd/display/modules/power/power_psr.c b/drivers/gpu/drm/amd/display/modules/power/power_psr.c new file mode 100644 index 000000000000..5ecb570c204e --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/power/power_psr.c @@ -0,0 +1,665 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "dc.h" +#include "mod_power.h" +#include "core_types.h" +#include "dmcu.h" +#include "abm.h" +#include "power_helpers.h" +#include "dce/dmub_psr.h" +#include "dal_asic_id.h" +#include "link_service.h" +#include + +#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ +#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */ +#include "dc/inc/hw/dmcu.h" +#include "dc/inc/hw/abm.h" +#include "dmub_cmd.h" + +#define MOD_POWER_TO_CORE(mod_power)\ + container_of(mod_power, struct core_power, mod_public) + +static unsigned int calc_psr_num_static_frames(unsigned int vsync_rate_hz) +{ + /* Initialize fail-safe to 2 static frames. */ + unsigned int num_frames_static = 2; + + /* Calculate number of frames such that at least 30 ms has passed. + * Round up to ensure the static period is not shorter than 30 ms. + */ + if (vsync_rate_hz != 0) + num_frames_static = DIV_ROUND_UP(30000 * vsync_rate_hz, 1000000); + + return num_frames_static; +} + +bool mod_power_psr_notify_mode_change(struct mod_power *mod_power, + const struct dc_stream_state *stream, + struct dc_link *link, + unsigned int stream_index) +{ + struct core_power *core_power = NULL; + struct dc *dc = NULL; + struct psr_config psr_config = {0}; + struct psr_context psr_context = {0}; + int active_psr_events = 0; + + if ((mod_power == NULL) || (stream == NULL) || (link == NULL)) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + dc = core_power->dc; + + // NO num_entities check here - already validated by caller + // stream_index is passed as validated parameter + active_psr_events = core_power->map[stream_index].psr_events; + + /* Calculate PSR configurations */ + mod_power_calc_psr_configs(&psr_config, link, stream); + + psr_config.psr_exit_link_training_required = + core_power->map[stream_index].caps->psr_exit_link_training_required; + if (dc->ctx->asic_id.chip_family >= AMDGPU_FAMILY_GC_11_0_1) + psr_config.allow_smu_optimizations = + core_power->psr_smu_optimizations_support && dc_is_embedded_signal(stream->signal); + else + psr_config.allow_smu_optimizations = + core_power->psr_smu_optimizations_support && + mod_power_only_edp(dc->current_state, stream); + + psr_config.allow_multi_disp_optimizations = core_power->multi_disp_optimizations_support; + + psr_config.rate_control_caps = core_power->map[stream_index].caps->rate_control_caps; + + if (active_psr_events & psr_event_os_request_force_ffu) + psr_config.os_request_force_ffu = true; + + /* + * DSC support: + * DSC slice height value must be 'mod' by su_y_granularity. + * According to Panel Vendor, there might be varied conditions to fulfill. + * Right now, DSC slice height value must be multiple of su_y_granularity. + * + * The value of DSC slice height is determined in DSC Driver but it does not + * propagated out here, so we need to calculate it as below 'slice_height'. + */ + psr_su_set_dsc_slice_height(dc, link, + (struct dc_stream_state *) stream, + &psr_config); + + dc_link_setup_psr(link, stream, &psr_config, &psr_context); + + return true; +} + +static void mod_power_psr_set_power_opt(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int active_psr_events, + bool psr_enable_request) +{ + (void)psr_enable_request; + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + unsigned int power_opt = 0; + + if (!stream) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + stream_index = map_index_from_stream(core_power, stream); + if (!core_power->map[stream_index].caps->psr_version) + return; + + link = dc_stream_get_link(stream); + + if (active_psr_events == 0) { + /* Static Screen */ + power_opt |= (psr_power_opt_smu_opt_static_screen | psr_power_opt_z10_static_screen | + psr_power_opt_ds_disable_allow); + } + + /* psr_power_opt_flag is a configuration parameter into the module that determines + * which optimizations to enable during psr + */ + power_opt &= core_power->map[stream_index].caps->psr_power_opt_flag; + if (core_power->map[stream_index].psr_power_opt != power_opt) { + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power set_power_opt: psr_power_opt=0x%04x, power_opt=0x%04x active_psr_events=0x%04x, psr_power_opt_flag=0x%04x", + core_power->map[stream_index].psr_power_opt, + power_opt, + active_psr_events, + core_power->map[stream_index].caps->psr_power_opt_flag); + dc_link_set_psr_allow_active(link, NULL, false, false, &power_opt); + core_power->map[stream_index].psr_power_opt = power_opt; + } +} + +static bool set_psr_enable(struct mod_power *mod_power, + struct dc_stream_state *stream, + bool psr_enable, + bool wait, + bool force_static) +{ + struct core_power *core_power = NULL; + enum dc_psr_state state = PSR_STATE0; + unsigned int retry_count; + const unsigned int max_retry = 1000; + struct dc_link *link = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) { + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: ERROR: stream=%p num_entities=%u", + stream, + core_power->num_entities); + return false; + } + + if (psr_enable) { + unsigned int vsync_rate_hz; + struct dc_static_screen_params params = {0}; + + vsync_rate_hz = (unsigned int)div_u64(div_u64(( + stream->timing.pix_clk_100hz * 100), + stream->timing.v_total), + stream->timing.h_total); + + params.triggers.cursor_update = true; + params.triggers.overlay_update = true; + params.triggers.surface_update = true; + params.num_frames = calc_psr_num_static_frames(vsync_rate_hz); + + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: CALCS: pix_clk_100hz=%u v_total=%u h_total=%u vsync_rate_hz=%u num_frames=%u", + stream->timing.pix_clk_100hz, + stream->timing.v_total, + stream->timing.h_total, + vsync_rate_hz, + params.num_frames); + + dc_stream_set_static_screen_params(core_power->dc, + &stream, 1, + ¶ms); + } + + link = dc_stream_get_link(stream); + + if (!dc_link_set_psr_allow_active(link, &psr_enable, false, force_static, NULL)) { + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: ERROR: stream=%p link=%p psr_enable=%d", + stream, + link, + psr_enable); + return false; + } + + if (wait == true) { + + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: BEGIN WAIT: psr_enable=%d", + (int)psr_enable); + + for (retry_count = 0; retry_count <= max_retry; retry_count++) { + dc_link_get_psr_state(link, &state); + if (psr_enable) { + if (state != PSR_STATE0 && + (!force_static || state == PSR_STATE3)) + break; + } else { + if (state == PSR_STATE0) + break; + } + udelay(500); + } + + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: END WAIT: psr_enable=%d", + (int)psr_enable); + + /* assert if max retry hit */ + if (retry_count >= max_retry) { + ASSERT(0); + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: ERROR: retry_count=%u: Unexpectedly long wait for PSR state change.", + retry_count); + } + } else { + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Firmware_PsrState, + "set psr enable: PSR state change initiated (wait=false): psr_enable=%d", + (int)psr_enable); + } + + return true; +} + +bool mod_power_get_psr_event(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int *active_psr_events) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + if (!core_power->map[stream_index].caps->psr_version) + return false; + + *active_psr_events = core_power->map[stream_index].psr_events; + + return true; +} + +bool mod_power_set_psr_event(struct mod_power *mod_power, + struct dc_stream_state *stream, bool set_event, + enum psr_event event, bool wait) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + unsigned int active_psr_events = 0; + bool psr_enable_request = false; + bool force_static = false; + + if (mod_power == NULL || stream == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + stream_index = map_index_from_stream(core_power, stream); + + if (core_power->num_entities == 0) { + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power set_psr_event: ERROR: stream=%p event=%d num_entities=%u", + stream, + (int)event, + core_power->num_entities); + return false; + } + + if (!core_power->map[stream_index].caps->psr_version) + return false; + + if (set_event) + core_power->map[stream_index].psr_events |= event; + else + core_power->map[stream_index].psr_events &= ~event; + + active_psr_events = core_power->map[stream_index].psr_events; + + // ignore other events when we're in forced psr enabled state + if (active_psr_events & psr_event_dynamic_display_switch && + event != psr_event_dynamic_display_switch) + return false; + + // ignore other events when we're in forced psr enabled state + if (active_psr_events & psr_event_os_override_hold && + event != psr_event_os_override_hold) + return false; + + // ignore other events when we're in forced psr enabled state + // dds events need to be processed while in dynamic_link_rate_control + if (active_psr_events & psr_event_dynamic_link_rate_control && + event != psr_event_dynamic_link_rate_control && + event != psr_event_dds_defer_stream_enable && + event != psr_event_dynamic_display_switch) + return false; + + if (active_psr_events & (psr_event_test_harness_disable_psr | psr_event_os_request_disable)) + psr_enable_request = false; + else if (active_psr_events & psr_event_pause) + psr_enable_request = false; + else if (active_psr_events & psr_event_test_harness_enable_psr) + psr_enable_request = true; + else if (active_psr_events & psr_event_dynamic_display_switch) { + psr_enable_request = true; + force_static = true; + } else if (active_psr_events & psr_event_dynamic_link_rate_control) { + psr_enable_request = true; + force_static = true; + } else if (active_psr_events & psr_event_edp_panel_off_disable_psr) + psr_enable_request = false; + else if (active_psr_events & (psr_event_hw_programming | + psr_event_defer_enable | + psr_event_dds_defer_stream_enable | + psr_event_vrr_transition | + psr_event_immediate_flip)) + psr_enable_request = false; + else if (active_psr_events & psr_event_big_screen_video) + psr_enable_request = true; + else if (active_psr_events & psr_event_full_screen) + psr_enable_request = false; + else if (active_psr_events & psr_event_mpo_video_selective_update) + psr_enable_request = true; + else if (active_psr_events & psr_event_vsync) + psr_enable_request = false; + else if (active_psr_events & psr_event_crc_window_active) + psr_enable_request = false; + else + psr_enable_request = true; + + DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE, + WPP_BIT_FLAG_Firmware_PsrState, + "mod_power set_psr_event: before: psr_enabled=%d -> request: set_event=%d event=0x%04x -> result: psr_events=0x%04x psr_enable_request=%d", + (int)core_power->map[stream_index].psr_enabled, + (int)set_event, + (unsigned int)event, + (unsigned int)core_power->map[stream_index].psr_events, + (int)psr_enable_request); + mod_power_psr_set_power_opt(mod_power, stream, active_psr_events, psr_enable_request); + + if (core_power->map[stream_index].psr_enabled != psr_enable_request || force_static) { + if (set_psr_enable(mod_power, stream, psr_enable_request, wait, force_static)) + core_power->map[stream_index].psr_enabled = psr_enable_request; + } + + return true; +} + +bool mod_power_get_psr_state(struct mod_power *mod_power, + const struct dc_stream_state *stream, + enum dc_psr_state *state) +{ + struct core_power *core_power = NULL; + const struct dc_link *link = NULL; + + if (!stream) + return false; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + link = dc_stream_get_link(stream); + return dc_link_get_psr_state(link, state); +} + +bool mod_power_get_psr_enabled_status(struct mod_power *mod_power, + const struct dc_stream_state *stream, + bool *psr_enabled) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + if (!core_power->map[stream_index].caps->psr_version) + return false; + + *psr_enabled = core_power->map[stream_index].psr_enabled; + + return true; +} + +void mod_power_psr_residency(struct mod_power *mod_power, + const struct dc_stream_state *stream, + unsigned int *residency, + const uint8_t mode) +{ + struct core_power *core_power = NULL; + const struct dc_link *link = NULL; + + if (!stream) + return; + + if (mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return; + + link = dc_stream_get_link(stream); + + if (link != NULL) + link->dc->link_srv->edp_get_psr_residency(link, residency, mode); +} +bool mod_power_psr_get_active_psr_events(struct mod_power *mod_power, + const struct dc_stream_state *stream, unsigned int *active_psr_events) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + + if (!stream) + return false; + + if (mod_power == NULL) + return false; + + if (active_psr_events == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + *active_psr_events = core_power->map[stream_index].psr_events; + return true; +} + +bool mod_power_psr_set_sink_vtotal_in_psr_active(struct mod_power *mod_power, + const struct dc_stream_state *stream, + uint16_t psr_vtotal_idle, + uint16_t psr_vtotal_su) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + const struct dc_link *link = NULL; + + if (!stream) + return false; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + if (!core_power->map[stream_index].caps->psr_version) + return false; + + link = dc_stream_get_link(stream); + + return link->dc->link_srv->edp_set_sink_vtotal_in_psr_active( + link, psr_vtotal_idle, psr_vtotal_su); +} +/* + * is_psr_su_specific_panel() - check if sink is AMD vendor-specific PSR-SU + * supported eDP device. + * + * @link: dc link pointer + * + * Return: true if AMDGPU vendor specific PSR-SU eDP panel + */ +bool is_psr_su_specific_panel(struct dc_link *link) +{ + bool isPSRSUSupported = false; + struct dpcd_caps *dpcd_caps = &link->dpcd_caps; + + if (dpcd_caps->edp_rev >= DP_EDP_14) { + if (dpcd_caps->psr_info.psr_version >= DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) + isPSRSUSupported = true; + /* + * Some panels will report PSR capabilities over additional DPCD bits. + * Such panels are approved despite reporting only PSR v3, as long as + * the additional bits are reported. + */ + if (dpcd_caps->sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) { + /* + * This is the temporary workaround to disable PSRSU when system turned on + * DSC function on the sepcific sink. + */ + if (dpcd_caps->psr_info.psr_version < DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) + isPSRSUSupported = false; + else if (dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && + ((dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x08) || + (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x07))) + isPSRSUSupported = false; + else if (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x03) + isPSRSUSupported = false; + else if (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x01) + isPSRSUSupported = false; + else if (dpcd_caps->psr_info.force_psrsu_cap == 0x1) + isPSRSUSupported = true; + } + } + + return isPSRSUSupported; +} + +/** + * mod_power_calc_psr_configs() - calculate/update generic psr configuration fields. + * @psr_config: [output], psr configuration structure to be updated + * @link: [input] dc link pointer + * @stream: [input] dc stream state pointer + * + * calculate and update the psr configuration fields that are not DM specific, i.e. such + * fields which are based on DPCD caps or timing information. To setup PSR in DMUB FW, + * this helper is assumed to be called before the call of the DC helper dc_link_setup_psr(). + * + * PSR config fields to be updated within the helper: + * - psr_rfb_setup_time + * - psr_sdp_transmit_line_num_deadline + * - line_time_in_us + * - su_y_granularity + * - su_granularity_required + * - psr_frame_capture_indication_req + * - psr_exit_link_training_required + * + * PSR config fields that are DM specific and NOT updated within the helper: + * - allow_smu_optimizations + * - allow_multi_disp_optimizations + */ +void mod_power_calc_psr_configs(struct psr_config *psr_config, + struct dc_link *link, + const struct dc_stream_state *stream) +{ + unsigned int num_vblank_lines = 0; + unsigned int vblank_time_in_us = 0; + unsigned int sdp_tx_deadline_in_us = 0; + unsigned int line_time_in_us = 0; + struct dpcd_caps *dpcd_caps = &link->dpcd_caps; + const int psr_setup_time_step_in_us = 55; /* refer to eDP spec DPCD 0x071h */ + + /* timing parameters */ + num_vblank_lines = stream->timing.v_total - + stream->timing.v_addressable - + stream->timing.v_border_top - + stream->timing.v_border_bottom; + + vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10); + + line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1; + + /** + * psr configuration fields + * + * as per eDP 1.5 pg. 377 of 459, DPCD 0x071h bits [3:1], psr setup time bits interpreted as below + * 000b <--> 330 us (default) + * 001b <--> 275 us + * 010b <--> 220 us + * 011b <--> 165 us + * 100b <--> 110 us + * 101b <--> 055 us + * 110b <--> 000 us + */ + psr_config->psr_rfb_setup_time = + (6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * psr_setup_time_step_in_us; + + if (psr_config->psr_rfb_setup_time > vblank_time_in_us) { + link->psr_settings.psr_frame_capture_indication_req = true; + link->psr_settings.psr_sdp_transmit_line_num_deadline = num_vblank_lines; + } else { + sdp_tx_deadline_in_us = vblank_time_in_us - psr_config->psr_rfb_setup_time; + + /* Set the last possible line SDP may be transmitted without violating the RFB setup time */ + link->psr_settings.psr_frame_capture_indication_req = false; + link->psr_settings.psr_sdp_transmit_line_num_deadline = sdp_tx_deadline_in_us / line_time_in_us; + } + + psr_config->psr_sdp_transmit_line_num_deadline = link->psr_settings.psr_sdp_transmit_line_num_deadline; + psr_config->line_time_in_us = line_time_in_us; + psr_config->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap; + psr_config->su_granularity_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED; + psr_config->psr_frame_capture_indication_req = link->psr_settings.psr_frame_capture_indication_req; + psr_config->psr_exit_link_training_required = + !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED; +} + +bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link, + struct dc_stream_state *stream, + struct psr_config *config) +{ + uint32_t pic_height; + uint32_t slice_height; + + config->dsc_slice_height = 0; + if (!(link->connector_signal & SIGNAL_TYPE_EDP) || + !dc->caps.edp_dsc_support || + link->panel_config.dsc.disable_dsc_edp || + !link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || + !stream->timing.dsc_cfg.num_slices_v) + return true; + + pic_height = stream->timing.v_addressable + + stream->timing.v_border_top + stream->timing.v_border_bottom; + + if (stream->timing.dsc_cfg.num_slices_v == 0) + return false; + + slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v; + config->dsc_slice_height = (uint16_t)slice_height; + + if (slice_height) { + if (config->su_y_granularity && + (slice_height % config->su_y_granularity)) { + ASSERT(0); + return false; + } + } + + return true; +} diff --git a/drivers/gpu/drm/amd/display/modules/power/power_replay.c b/drivers/gpu/drm/amd/display/modules/power/power_replay.c new file mode 100644 index 000000000000..983be9759e74 --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/power/power_replay.c @@ -0,0 +1,911 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "dc.h" +#include "mod_power.h" +#include "core_types.h" +#include "dmcu.h" +#include "abm.h" +#include "power_helpers.h" +#include "dce/dmub_psr.h" +#include "dal_asic_id.h" +#include "link_service.h" +#include + +#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ +#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */ +#include "power_helpers.h" +#include "dc/inc/hw/dmcu.h" +#include "dc/inc/hw/abm.h" +#include "dc.h" +#include "core_types.h" +#include "dmub_cmd.h" + +#define MOD_POWER_TO_CORE(mod_power)\ + container_of(mod_power, struct core_power, mod_public) + +#define LOW_REFRESH_RATE_DURATION_US_UPPER_BOUND 25000 + +static bool mod_power_set_replay_active(struct dc_stream_state *stream, + bool replay_active, + bool wait, + bool force_static) +{ + uint64_t state; + unsigned int retry_count; + const unsigned int max_retry = 1000; + struct dc_link *link = NULL; + + if (!stream) + return false; + + link = dc_stream_get_link(stream); + + if (!link) + return false; + + if (!dc_link_set_replay_allow_active(link, &replay_active, false, force_static, NULL)) + return false; + + if (wait == true) { + + for (retry_count = 0; retry_count <= max_retry; retry_count++) { + dc_link_get_replay_state(link, &state); + if (replay_active) { + if (state != REPLAY_STATE_0 && + (!force_static || state == REPLAY_STATE_3)) + break; + } else { + if (state == REPLAY_STATE_0) + break; + } + udelay(500); + } + + /* assert if max retry hit */ + if (retry_count >= max_retry) + ASSERT(0); + } else { + /* To-do: Add trace log */ + } + + return true; +} + +static unsigned int mod_power_replay_setup_power_opt(struct dc_link *link, + unsigned int active_replay_events, bool is_ultra_sleep_mode) +{ + unsigned int power_opt = 0; + + if (is_ultra_sleep_mode) { + /* Static Screen */ + power_opt |= (replay_power_opt_smu_opt_static_screen | replay_power_opt_z10_static_screen); + } else if (active_replay_events & replay_event_test_harness_ultra_sleep) { + power_opt |= replay_power_opt_z10_static_screen; + } + + /* replay_power_opt_flag is a configuration parameter into the module that determines + * which optimizations to enable during replay + */ + power_opt &= link->replay_settings.config.replay_power_opt_supported; + + return power_opt; +} + +static bool mod_power_replay_set_power_opt(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int active_replay_events, + bool is_ultra_sleep_mode) +{ + (void)mod_power; + struct dc_link *link = NULL; + unsigned int power_opt = 0; + + if (!stream) + return false; + + link = dc_stream_get_link(stream); + + if (!link || !link->replay_settings.replay_feature_enabled) + return false; + + power_opt = mod_power_replay_setup_power_opt(link, active_replay_events, is_ultra_sleep_mode); + + if (!dc_link_set_replay_allow_active(link, NULL, false, false, &power_opt)) + return false; + + return true; +} + +bool mod_power_get_replay_event(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int *active_replay_events) +{ + struct core_power *core_power = NULL; + unsigned int stream_index = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + *active_replay_events = core_power->map[stream_index].replay_events; + + return true; +} + +static bool mod_power_update_replay_active_status(unsigned int active_replay_events, + struct dc_link *link, uint32_t *coasting_vtotal, bool *is_full_screen_video, + bool *is_ultra_sleep_mode, uint16_t *frame_skip_number, bool *is_video_playback) +{ + if (!link || !coasting_vtotal || !is_full_screen_video || !is_video_playback) + return false; + + // Check coasting_vtotal_table has been updated. + if (!link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_STATIC] + || !link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM]) + return false; + + unsigned int replay_enable_option = + link->replay_settings.config.replay_enable_option; + + /* TODO: To support test harness and DDS event */ + + *coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM]; + ASSERT(link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM] <= 0xFFFF); + *frame_skip_number = (uint16_t)link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM]; + + link->replay_settings.config.replay_timing_sync_supported = false; + + *is_full_screen_video = false; + + *is_ultra_sleep_mode = false; + + *is_video_playback = false; + + /* DSAT test scenario */ + if (active_replay_events & replay_event_test_harness_mode) { + if (link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]) + *coasting_vtotal = + link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]; + if (link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]) { + ASSERT(link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS] <= 0xFFFF); + *frame_skip_number = + (uint16_t)link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]; + } + + /* During the ultra sleep mode testing, disable the timing sync in short vblank mode */ + if (active_replay_events & (replay_event_test_harness_enable_replay)) { + if ((active_replay_events & replay_event_test_harness_ultra_sleep) && + !link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode) + link->replay_settings.config.replay_timing_sync_supported = false; + return true; + } else + return false; + } else if (active_replay_events & (replay_event_test_harness_enable_replay)) { + if (link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]) + *coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]; + if (link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]) { + uint32_t frame_skip_val = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]; + + ASSERT(frame_skip_val <= 0xFFFF); + *frame_skip_number = (uint16_t)frame_skip_val; + } + + /* During the ultra sleep mode testing, disable the timing sync in short vblank mode */ + if ((active_replay_events & replay_event_test_harness_ultra_sleep) && + !link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode) { + link->replay_settings.config.replay_timing_sync_supported = false; + } + return true; + } else if (active_replay_events & + (replay_event_test_harness_disable_replay | replay_event_os_request_disable)) { + // set last set coasting vtotal + if (link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]) + *coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS]; + if (link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]) { + uint32_t frame_skip_val = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]; + + ASSERT(frame_skip_val <= 0xFFFF); + *frame_skip_number = (uint16_t)frame_skip_val; + } + return false; + } + + /* Inactive conditions */ + if (active_replay_events & (replay_event_edp_panel_off_disable_psr | + replay_event_hw_programming | + replay_event_vrr | + replay_event_immediate_flip | + replay_event_prepare_vtotal | + replay_event_vrr_transition | + replay_event_pause | + replay_event_disable_replay_while_DPMS | + replay_event_sleep_resume | + replay_event_disable_in_AC | + replay_event_disable_replay_while_detect_display | + replay_event_infopacket | + replay_event_crc_window_active)) + return false; + + // Full screen scenario + if (active_replay_events & replay_event_full_screen) { + if (!(replay_enable_option & pr_enable_option_full_screen)) + return false; + } + + /* Full screen video scenario */ + if (active_replay_events & replay_event_big_screen_video) { + + link->replay_settings.config.replay_timing_sync_supported = false; + + if (replay_enable_option & pr_enable_option_full_screen_video_coasting) { + unsigned int fsn_vid = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_FULL_SCREEN_VIDEO]; + + *coasting_vtotal = + link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_FULL_SCREEN_VIDEO]; + ASSERT(fsn_vid <= 0xFFFF); + *frame_skip_number = (uint16_t)fsn_vid; + } + + *is_video_playback = true; + + if ((replay_enable_option & pr_enable_option_full_screen_video) && + (replay_enable_option & pr_enable_option_full_screen_video_coasting)) { + *is_full_screen_video = true; + return true; + } else + return false; + } + + /* MPO video scenario + * Some of the cases may contain a full screen UI layer in MPO video scenario which is + * not the expected case to enable Replay. + */ + if ((active_replay_events & replay_event_mpo_video_selective_update) && + !(active_replay_events & replay_event_full_screen)) { + + link->replay_settings.config.replay_timing_sync_supported = false; + + if (replay_enable_option & pr_enable_option_mpo_video_coasting) { + *coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM]; + { + uint32_t frame_skip_val = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM]; + + ASSERT(frame_skip_val <= 0xFFFF); + *frame_skip_number = (uint16_t)frame_skip_val; + } + } + + *is_video_playback = true; + + if (replay_enable_option & pr_enable_option_mpo_video) + return true; + else + return false; + } + + /* Static screen scenario */ + if (!(active_replay_events & replay_event_vsync)) { + + if (replay_enable_option & pr_enable_option_static_screen_coasting) { + // Do not adjust eDP refresh rate if static screen + normal sleep mode + if ((!(link->replay_settings.config.replay_power_opt_supported & + replay_power_opt_z10_static_screen)) || + (active_replay_events & replay_event_cursor_updating)) { + // normal sleep mode + *coasting_vtotal = + link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM]; + { + uint32_t frame_skip_val = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM]; + + ASSERT(frame_skip_val <= 0xFFFF); + *frame_skip_number = (uint16_t)frame_skip_val; + } + } else { + // ultra sleep mode + *coasting_vtotal = + link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_STATIC]; + { + uint32_t frame_skip_val = + link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_STATIC]; + + ASSERT(frame_skip_val <= 0xFFFF); + *frame_skip_number = (uint16_t)frame_skip_val; + } + *is_ultra_sleep_mode = true; + } + } + + if (replay_enable_option & pr_enable_option_static_screen) { + if (!link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode) + link->replay_settings.config.replay_timing_sync_supported = false; + return true; + } else + return false; + } + + /* General UI scenario */ + if (active_replay_events & replay_event_general_ui) { + if (replay_enable_option & pr_enable_option_general_ui) + return true; + else + return false; + } + + return false; +} + +bool mod_power_replay_set_coasting_vtotal(struct mod_power *mod_power, + const struct dc_stream_state *stream, + uint32_t coasting_vtotal, + uint16_t frame_skip_number) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + + if (!stream) + return false; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return false; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + return link->dc->link_srv->edp_set_coasting_vtotal(link, coasting_vtotal, frame_skip_number); +} + +void mod_power_replay_set_timing_sync_supported(struct mod_power *mod_power, + const struct dc_stream_state *stream) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + union dmub_replay_cmd_set cmd_data = { 0 }; + + if (!stream || mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) + return; + + stream_index = map_index_from_stream(core_power, stream); + if (stream_index > core_power->num_entities) //invalid index + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + cmd_data.sync_data.timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported; + + link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Timing_Sync_Supported, + &cmd_data); +} + +void mod_power_replay_disabled_adaptive_sync_sdp(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool force_disabled) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + union dmub_replay_cmd_set cmd_data = { 0 }; + + if (!stream || mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) + return; + + stream_index = map_index_from_stream(core_power, stream); + if (stream_index > core_power->num_entities) //invalid index + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + cmd_data.disabled_adaptive_sync_sdp_data.force_disabled = force_disabled; + + link->dc->link_srv->edp_send_replay_cmd(link, Replay_Disabled_Adaptive_Sync_SDP, + &cmd_data); +} + +static void mod_power_replay_set_general_cmd(struct mod_power *mod_power, + const struct dc_stream_state *stream, + const enum dmub_cmd_replay_general_subtype general_cmd_type, + const uint32_t param1, const uint32_t param2) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + union dmub_replay_cmd_set cmd_data = { 0 }; + + if (!stream || mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) + return; + + stream_index = map_index_from_stream(core_power, stream); + if (stream_index > core_power->num_entities) //invalid index + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + cmd_data.set_general_cmd_data.subtype = general_cmd_type; + cmd_data.set_general_cmd_data.param1 = param1; + cmd_data.set_general_cmd_data.param2 = param2; + link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_General_Cmd, + &cmd_data); +} + +void mod_power_replay_disabled_desync_error_detection(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool force_disabled) +{ + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, + force_disabled, 0); +} + +static void mod_power_replay_set_pseudo_vtotal(struct mod_power *mod_power, + const struct dc_stream_state *stream, uint16_t vtotal) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + union dmub_replay_cmd_set cmd_data = { 0 }; + + if (!stream || mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + if (core_power->num_entities == 0) + return; + + stream_index = map_index_from_stream(core_power, stream); + if (stream_index > core_power->num_entities) //invalid index + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + cmd_data.pseudo_vtotal_data.vtotal = vtotal; + + if (link->replay_settings.last_pseudo_vtotal != vtotal) { + link->replay_settings.last_pseudo_vtotal = vtotal; + link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Pseudo_VTotal, &cmd_data); + } +} + +static void mod_power_update_error_status(struct mod_power *mod_power, + const struct dc_stream_state *stream) +{ + struct dc_link *link = NULL; + union replay_debug_flags *pDebug = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + + if (!link) + return; + + pDebug = (union replay_debug_flags *)&link->replay_settings.config.debug_flags; + + if (pDebug->bitfields.enable_visual_confirm_debug == 0) + return; + + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, + link->replay_settings.config.replay_error_status.raw, 0); +} + +void mod_power_set_low_rr_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool low_rr_supported) +{ + struct dc_link *link = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + + if (!link) + return; + + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, + low_rr_supported, 0); +} + +void mod_power_set_video_conferencing_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool video_conferencing_activate) +{ + struct dc_link *link = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, + video_conferencing_activate, 0); +} + +void mod_power_set_coasting_vtotal_without_frame_update(struct mod_power *mod_power, + const struct dc_stream_state *stream, uint32_t coasting_vtotal) +{ + struct dc_link *link = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_SET_COASTING_VTOTAL_WITHOUT_FRAME_UPDATE, + coasting_vtotal, 0); +} + +void mod_power_set_replay_continuously_resync(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool enable) +{ + struct dc_link *link = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC, + enable, 0); +} + +void mod_power_set_live_capture_with_cvt_activate(struct mod_power *mod_power, + const struct dc_stream_state *stream, bool live_capture_with_cvt_activate) +{ + struct dc_link *link = NULL; + + if (mod_power == NULL || stream == NULL) + return; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return; + + // Check if LIVE_CAPTURE_WITH_CVT bit is enabled in replay optimization config + if (!link->replay_settings.config.replay_optimization.bits.LIVE_CAPTURE_WITH_CVT) + return; + + if (link->replay_settings.config.live_capture_with_cvt_activated != live_capture_with_cvt_activate) { + link->replay_settings.config.live_capture_with_cvt_activated = live_capture_with_cvt_activate; + mod_power_replay_set_general_cmd(mod_power, stream, + REPLAY_GENERAL_CMD_LIVE_CAPTURE_WITH_CVT, + live_capture_with_cvt_activate, 0); + } +} + +bool mod_power_set_replay_event(struct mod_power *mod_power, + struct dc_stream_state *stream, bool set_event, + enum replay_event event, bool wait_for_disable) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int stream_index = 0; + unsigned int active_replay_events = 0; + bool replay_active_request = false; + bool force_static = false; + uint32_t coasting_vtotal = 0; + bool current_timing_sync_status = false; + bool is_full_screen_video = false; + bool is_ultra_sleep_mode = false; + unsigned int sink_duration_us = 0; + bool low_rr_active = false; + uint16_t frame_skip_number = 0; + bool is_video_playback = false; + + if (!stream) + return false; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + stream_index = map_index_from_stream(core_power, stream); + + if (set_event) + core_power->map[stream_index].replay_events |= event; + else + core_power->map[stream_index].replay_events &= ~event; + + link = dc_stream_get_link(stream); + if (!link || !link->replay_settings.replay_feature_enabled) + return false; + + if ((core_power->map[stream_index].replay_events & replay_event_disable_replay_while_switching_mux) != 0) + return false; + + if ((core_power->map[stream_index].replay_events & replay_event_os_override_hold) != 0) + return false; + + active_replay_events = core_power->map[stream_index].replay_events; + + current_timing_sync_status = + link->replay_settings.config.replay_timing_sync_supported; + + replay_active_request = mod_power_update_replay_active_status(active_replay_events, + link, &coasting_vtotal, &is_full_screen_video, &is_ultra_sleep_mode, &frame_skip_number, &is_video_playback); + + if (is_full_screen_video) + mod_power_replay_set_pseudo_vtotal(mod_power, stream, + link->replay_settings.low_rr_full_screen_video_pseudo_vtotal); + else + mod_power_replay_set_pseudo_vtotal(mod_power, stream, 0); + + //If timing_sync_status change, then re-enabled set timing_sync_supported value and re-enabled replay + if (current_timing_sync_status != link->replay_settings.config.replay_timing_sync_supported) + mod_power_replay_set_timing_sync_supported(mod_power, stream); + + if (link->replay_settings.config.low_rr_supported) { + sink_duration_us = + (unsigned int)(div_u64(((unsigned long long)(coasting_vtotal) + * 10000) * stream->timing.h_total, + stream->timing.pix_clk_100hz)); + low_rr_active = sink_duration_us < LOW_REFRESH_RATE_DURATION_US_UPPER_BOUND ? false : true; + if (low_rr_active != link->replay_settings.config.low_rr_activated) { + mod_power_set_low_rr_activate(mod_power, stream, low_rr_active); + link->replay_settings.config.low_rr_activated = low_rr_active; + } + } + + // The function return fail when + // 1. DMUB function is not support (for backward compatible). + // 2. active_replay_events or coasting_vtotal is not updated in the same time + if (!mod_power_replay_set_power_opt_and_coasting_vtotal(mod_power, + stream, active_replay_events, coasting_vtotal, is_ultra_sleep_mode, frame_skip_number)) { + if (!mod_power_replay_set_power_opt(mod_power, stream, active_replay_events, is_ultra_sleep_mode)) + return false; + + if (!mod_power_replay_set_coasting_vtotal(mod_power, stream, coasting_vtotal, frame_skip_number)) + return false; + } + + mod_power_set_live_capture_with_cvt_activate(mod_power, stream, is_video_playback); + + mod_power_update_error_status(mod_power, stream); + + // If Replay is going to be enable (No matter is disable -> enable or enable -> enable), we don't need to wait. + // If Replay is going to be disable + // if disable -> disable + // -> Replay DMUB state should be state 0. + // So no matter wait_for_disable is true or not, it should makes no difference. + // if enable -> disable -> We should wait if wait_for_disable is true. + if (replay_active_request) + wait_for_disable = false; + + if (!mod_power_set_replay_active(stream, replay_active_request, wait_for_disable, force_static)) + return false; + + return true; +} + +bool mod_power_get_replay_active_status(const struct dc_stream_state *stream, + bool *replay_active) +{ + const struct dc_link *link = NULL; + + if (!stream) + return false; + + link = dc_stream_get_link(stream); + *replay_active = link->replay_settings.replay_allow_active; + + return true; +} + +void mod_power_replay_residency(const struct dc_stream_state *stream, + unsigned int *residency, const bool is_start, const bool is_alpm) +{ + const struct dc_link *link = NULL; + enum pr_residency_mode mode; + + if (!stream) + return; + + link = dc_stream_get_link(stream); + + if (is_alpm) + mode = PR_RESIDENCY_MODE_ALPM; + else + mode = PR_RESIDENCY_MODE_PHY; + + if (link && link->dc && link->dc->link_srv) + link->dc->link_srv->edp_replay_residency(link, residency, is_start, mode); +} + +bool mod_power_replay_set_power_opt_and_coasting_vtotal(struct mod_power *mod_power, + const struct dc_stream_state *stream, unsigned int active_replay_events, uint32_t coasting_vtotal, + bool is_ultra_sleep_mode, uint16_t frame_skip_number) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + unsigned int power_opt = 0; + + if (!stream) + return false; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power->num_entities == 0) + return false; + + link = dc_stream_get_link(stream); + + if (!link || !link->replay_settings.replay_feature_enabled) + return false; + + power_opt = mod_power_replay_setup_power_opt(link, active_replay_events, is_ultra_sleep_mode); + + return link->dc->link_srv->edp_set_replay_power_opt_and_coasting_vtotal(link, &power_opt, coasting_vtotal, frame_skip_number); +} + +void mod_power_replay_notify_mode_change(struct mod_power *mod_power, + struct dc *dc, + struct dc_link *link, + const struct dc_stream_state *stream, + unsigned int stream_index) +{ + struct core_power *core_power = NULL; + int active_replay_events = 0; + + if (!mod_power || !dc || !link || !stream) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + active_replay_events = core_power->map[stream_index].replay_events; + + link->replay_settings.replay_smu_opt_enable = + (link->replay_settings.config.replay_smu_opt_supported && + mod_power_only_edp(dc->current_state, stream)); + + if (active_replay_events & replay_event_os_request_force_ffu) { + link->replay_settings.config.os_request_force_ffu = true; + } + + if (dc_is_embedded_signal(stream->signal)) + dc->link_srv->dp_setup_replay(link, stream); +} + +void init_replay_config(struct dc_link *link, struct replay_config *pr_config) +{ + link->replay_settings.config = *pr_config; +} + +void set_replay_frame_skip_number(struct dc_link *link, + enum replay_coasting_vtotal_type type, + uint32_t coasting_vtotal_refresh_rate_uhz, + uint32_t flicker_free_refresh_rate_uhz, + bool is_defer) +{ + uint32_t *frame_skip_number_array = NULL; + uint32_t frame_skip_number = 0; + + if (link == NULL) + return; + + if (link->replay_settings.config.frame_skip_supported == false) + return; + + if (flicker_free_refresh_rate_uhz == 0 || coasting_vtotal_refresh_rate_uhz == 0) + return; + + if (is_defer) + frame_skip_number_array = link->replay_settings.defer_frame_skip_number_table; + else + frame_skip_number_array = link->replay_settings.frame_skip_number_table; + + if (frame_skip_number_array == NULL) + return; + + frame_skip_number = (coasting_vtotal_refresh_rate_uhz + 500000) / flicker_free_refresh_rate_uhz; + + if (frame_skip_number >= 1) + frame_skip_number_array[type] = frame_skip_number - 1; + else + frame_skip_number_array[type] = 0; +} + +void set_replay_defer_update_coasting_vtotal(struct dc_link *link, + enum replay_coasting_vtotal_type type, + uint32_t vtotal) +{ + link->replay_settings.defer_update_coasting_vtotal_table[type] = vtotal; +} + +void update_replay_coasting_vtotal_from_defer(struct dc_link *link, + enum replay_coasting_vtotal_type type) +{ + link->replay_settings.coasting_vtotal_table[type] = + link->replay_settings.defer_update_coasting_vtotal_table[type]; + link->replay_settings.frame_skip_number_table[type] = + link->replay_settings.defer_frame_skip_number_table[type]; +} + +void set_replay_coasting_vtotal(struct dc_link *link, + enum replay_coasting_vtotal_type type, + uint32_t vtotal) +{ + link->replay_settings.coasting_vtotal_table[type] = vtotal; +} + +void set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link *link, uint16_t vtotal) +{ + link->replay_settings.low_rr_full_screen_video_pseudo_vtotal = vtotal; +} + +void calculate_replay_link_off_frame_count(struct dc_link *link, + uint16_t vtotal, uint16_t htotal) +{ + uint32_t max_link_off_frame_count = 0; + uint16_t max_deviation_line = 0, pixel_deviation_per_line = 0; + + if (!link || link->replay_settings.config.replay_version != DC_FREESYNC_REPLAY) + return; + + max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line; + pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line; + + if (htotal != 0 && vtotal != 0 && pixel_deviation_per_line != 0) + max_link_off_frame_count = htotal * max_deviation_line / (pixel_deviation_per_line * vtotal); + else + ASSERT(0); + + link->replay_settings.link_off_frame_count = max_link_off_frame_count; +} + +void reset_replay_dsync_error_count(struct dc_link *link) +{ + link->replay_settings.replay_desync_error_fail_count = 0; +} diff --git a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c index 179b505f7777..32617893ffb2 100644 --- a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c +++ b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c @@ -56,7 +56,7 @@ static void clear_entry_from_vmid_table(struct core_vmid *core_vmid, unsigned in static void evict_vmids(struct core_vmid *core_vmid) { - int i; + unsigned int i; int ord_int = dc_get_vmid_use_vector(core_vmid->dc); ASSERT(ord_int >= 0 && ord_int <= 0xFFFF); @@ -72,7 +72,7 @@ static void evict_vmids(struct core_vmid *core_vmid) // Return value of -1 indicates vmid table uninitialized or ptb dne in the table static int get_existing_vmid_for_ptb(struct core_vmid *core_vmid, uint64_t ptb) { - int i; + unsigned int i; for (i = 0; i < core_vmid->num_vmid; i++) { if (core_vmid->ptb_assigned_to_vmid[i] == ptb) @@ -85,7 +85,7 @@ static int get_existing_vmid_for_ptb(struct core_vmid *core_vmid, uint64_t ptb) // Expected to be called only when there's an available vmid static int get_next_available_vmid(struct core_vmid *core_vmid) { - int i; + unsigned int i; for (i = 1; i < core_vmid->num_vmid; i++) { if (core_vmid->ptb_assigned_to_vmid[i] == 0) diff --git a/drivers/gpu/drm/amd/include/amd_cper.h b/drivers/gpu/drm/amd/include/amd_cper.h index a252ee4c7874..baa0f30b9c4d 100644 --- a/drivers/gpu/drm/amd/include/amd_cper.h +++ b/drivers/gpu/drm/amd/include/amd_cper.h @@ -58,7 +58,7 @@ enum cper_error_severity { CPER_SEV_NON_FATAL_UNCORRECTED = 0, - CPER_SEV_FATAL = 1, + CPER_SEV_FATAL_UNCORRECTED = 1, CPER_SEV_NON_FATAL_CORRECTED = 2, CPER_SEV_NUM = 3, diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h new file mode 100644 index 000000000000..154b8da3bfa9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -0,0 +1,64 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMDGPU_PTL_H__ +#define __AMDGPU_PTL_H__ + +enum amdgpu_ptl_fmt { + AMDGPU_PTL_FMT_I8 = 0, + AMDGPU_PTL_FMT_F16 = 1, + AMDGPU_PTL_FMT_BF16 = 2, + AMDGPU_PTL_FMT_F32 = 3, + AMDGPU_PTL_FMT_F64 = 4, + AMDGPU_PTL_FMT_F8 = 5, + AMDGPU_PTL_FMT_VECTOR = 6, + AMDGPU_PTL_FMT_INVALID = 7, +}; + +enum amdgpu_ptl_disable_source { + AMDGPU_PTL_DISABLE_SYSFS = 0, + AMDGPU_PTL_DISABLE_PROFILER, + AMDGPU_PTL_DISABLE_MAX, +}; +struct amdgpu_ptl { + enum amdgpu_ptl_fmt fmt1; + enum amdgpu_ptl_fmt fmt2; + bool enabled; + bool hw_supported; + bool permanently_disabled; + /* PTL disable reference counting */ + atomic_t disable_ref; + struct mutex mutex; + DECLARE_BITMAP(disable_bitmap, AMDGPU_PTL_DISABLE_MAX); + bool ptl_sysfs_created; +}; + +int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, + u32 *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2); + +int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev); +void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev); + +extern const struct attribute_group amdgpu_ptl_attr_group; +#endif /* __AMDGPU_PTL_H__ */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h index f32649047374..904518791b62 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h @@ -15871,6 +15871,113 @@ #define mmDC_PERFMON28_PERFMON_LOW 0x08cf #define mmDC_PERFMON28_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL 0x08d4 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL 0x08d4 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define mmHDMI_TB_ENC_CONTROL 0x08df +#define mmHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define mmHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define mmHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define mmHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define mmHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define mmHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_0 0x08f2 +#define mmHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_1 0x08f3 +#define mmHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_0 0x08f4 +#define mmHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_1 0x08f5 +#define mmHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_0 0x08f6 +#define mmHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_1 0x08f7 +#define mmHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define mmHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define mmHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define mmHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_MEM_CTRL 0x08fe +#define mmHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_CNTL 0x0903 +#define mmHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define mmHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_MODE 0x0908 +#define mmHDMI_TB_ENC_MODE_BASE_IDX 3 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define mmHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // base address: 0x2646c #define mmAFMT6_AFMT_VBI_PACKET_CONTROL 0x091c #define mmAFMT6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 @@ -15934,6 +16041,28 @@ #define mmVPG6_VPG_MPEG_INFO1 0x093a #define mmVPG6_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define mmHDMI_LINK_ENC_CONTROL 0x095b +#define mmHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_LINK_ENC_CLK_CTRL 0x095c +#define mmHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define mmHDMI_FRL_ENC_CONFIG 0x0965 +#define mmHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define mmHDMI_FRL_ENC_CONFIG2 0x0966 +#define mmHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define mmHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define mmHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +// base address: 0x0 +#define mmHPO_TOP_CLOCK_CONTROL 0x0e43 +#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 // base address: 0x264f0 #define mmDME6_DME_CONTROL 0x093c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h index 4005c73c2c9f..92c3ba54effa 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h @@ -60370,6 +60370,496 @@ #define DC_PERFMON28_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON28_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO__SHIFT 0x8 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT_MASK 0x000000FFL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO_MASK 0x0000FF00L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + //AFMT6_AFMT_VBI_PACKET_CONTROL #define AFMT6_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 #define AFMT6_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 @@ -60736,10 +61226,120 @@ #define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L #define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_hdcp2_hdcp2_dispdec +//HDCP2_6_HDCP2_CONTROL +#define HDCP2_6_HDCP2_CONTROL__HDCP2_RESET__SHIFT 0x4 +#define HDCP2_6_HDCP2_CONTROL__HDCP2_TYPE__SHIFT 0x8 +#define HDCP2_6_HDCP2_CONTROL__HDCP2_EESS_WHEN_AVMUTE__SHIFT 0x10 +#define HDCP2_6_HDCP2_CONTROL__HDCP2_ESS_ENABLE__SHIFT 0x14 +#define HDCP2_6_HDCP2_CONTROL__HDCP2_ESS_TYPE__SHIFT 0x18 +#define HDCP2_6_HDCP2_CONTROL__HDCP2_RESET_MASK 0x00000010L +#define HDCP2_6_HDCP2_CONTROL__HDCP2_TYPE_MASK 0x00000300L +#define HDCP2_6_HDCP2_CONTROL__HDCP2_EESS_WHEN_AVMUTE_MASK 0x00010000L +#define HDCP2_6_HDCP2_CONTROL__HDCP2_ESS_ENABLE_MASK 0x00100000L +#define HDCP2_6_HDCP2_CONTROL__HDCP2_ESS_TYPE_MASK 0x01000000L +//HDCP2_6_HDCP2_ENABLE_DELAY +#define HDCP2_6_HDCP2_ENABLE_DELAY__HDCP2_ENABLE_DELAY__SHIFT 0x0 +#define HDCP2_6_HDCP2_ENABLE_DELAY__HDCP2_ENABLE_DELAY_MASK 0x000003FFL +//HDCP2_6_HDCP2_RIV0 +#define HDCP2_6_HDCP2_RIV0__HDCP2_RIV0__SHIFT 0x0 +#define HDCP2_6_HDCP2_RIV0__HDCP2_RIV0_MASK 0xFFFFFFFFL +//HDCP2_6_HDCP2_RIV1 +#define HDCP2_6_HDCP2_RIV1__HDCP2_RIV1__SHIFT 0x0 +#define HDCP2_6_HDCP2_RIV1__HDCP2_RIV1_MASK 0xFFFFFFFFL +//HDCP2_6_HDCP2_KS_XOR_LC128_0 +#define HDCP2_6_HDCP2_KS_XOR_LC128_0__HDCP2_KS_XOR_LC128_0__SHIFT 0x0 +#define HDCP2_6_HDCP2_KS_XOR_LC128_0__HDCP2_KS_XOR_LC128_0_MASK 0xFFFFFFFFL +//HDCP2_6_HDCP2_KS_XOR_LC128_1 +#define HDCP2_6_HDCP2_KS_XOR_LC128_1__HDCP2_KS_XOR_LC128_1__SHIFT 0x0 +#define HDCP2_6_HDCP2_KS_XOR_LC128_1__HDCP2_KS_XOR_LC128_1_MASK 0xFFFFFFFFL +//HDCP2_6_HDCP2_KS_XOR_LC128_2 +#define HDCP2_6_HDCP2_KS_XOR_LC128_2__HDCP2_KS_XOR_LC128_2__SHIFT 0x0 +#define HDCP2_6_HDCP2_KS_XOR_LC128_2__HDCP2_KS_XOR_LC128_2_MASK 0xFFFFFFFFL +//HDCP2_6_HDCP2_KS_XOR_LC128_3 +#define HDCP2_6_HDCP2_KS_XOR_LC128_3__HDCP2_KS_XOR_LC128_3__SHIFT 0x0 +#define HDCP2_6_HDCP2_KS_XOR_LC128_3__HDCP2_KS_XOR_LC128_3_MASK 0xFFFFFFFFL + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + // addressBlock: dce_dc_hpo_hpo_top_dispdec //HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 #define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L #define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0x003F0000L // addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec //DC_PERFMON29_PERFCOUNTER_CNTL diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h index b2962b5ce31e..47f09e233f47 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h @@ -14303,12 +14303,124 @@ #define mmDC_PERFMON25_PERFMON_HI_BASE_IDX 3 #define mmDC_PERFMON25_PERFMON_LOW 0x08cf #define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL 0x08d4 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define mmHDMI_TB_ENC_CONTROL 0x08df +#define mmHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define mmHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define mmHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define mmHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define mmHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define mmHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_0 0x08f2 +#define mmHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_1 0x08f3 +#define mmHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_0 0x08f4 +#define mmHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_1 0x08f5 +#define mmHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_0 0x08f6 +#define mmHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_1 0x08f7 +#define mmHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define mmHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define mmHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define mmHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_MEM_CTRL 0x08fe +#define mmHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_CNTL 0x0903 +#define mmHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define mmHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_MODE 0x0908 +#define mmHDMI_TB_ENC_MODE_BASE_IDX 3 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define mmHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + + // base address: 0x264f0 #define mmDME5_DME_CONTROL 0x093c #define mmDME5_DME_CONTROL_BASE_IDX 3 #define mmDME5_DME_MEMORY_CONTROL 0x093d #define mmDME5_DME_MEMORY_CONTROL_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define mmHDMI_LINK_ENC_CONTROL 0x095b +#define mmHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_LINK_ENC_CLK_CTRL 0x095c +#define mmHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define mmHDMI_FRL_ENC_CONFIG 0x0965 +#define mmHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define mmHDMI_FRL_ENC_CONFIG2 0x0966 +#define mmHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define mmHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define mmHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_hdcp2_hdcp2_dispdec // base address: 0x264f8 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h index 7f8f0a646422..e6e0d1bb9614 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h @@ -52453,10 +52453,1917 @@ #define DC_PERFMON25_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON25_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +//AFMT5_AFMT_ACP +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE__SHIFT 0x0 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_MASK 0x00000003L +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +//AFMT5_AFMT_VBI_PACKET_CONTROL +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT 0xd +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK 0x00002000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT5_AFMT_AUDIO_INFO0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT5_AFMT_AUDIO_INFO1 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT5_AFMT_60958_0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT5_AFMT_60958_1 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_CONTROL +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT5_AFMT_RAMP_CONTROL0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT5_AFMT_RAMP_CONTROL1 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT5_AFMT_RAMP_CONTROL2 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_RAMP_CONTROL3 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_60958_2 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_RESULT +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT5_AFMT_STATUS +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT5_AFMT_INFOFRAME_CONTROL0 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT5_AFMT_AUDIO_SRC_CONTROL +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT5_AFMT_AUDIO_DBG_DTO_CNTL +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L +//AFMT5_AFMT_MEM_PWR +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG5_VPG_GENERIC_PACKET_DATA +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GENERIC_STATUS +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG5_VPG_MEM_PWR +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG5_VPG_ISRC1_2_ACCESS_CTRL +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG5_VPG_ISRC1_2_DATA +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO1 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME5_DME_CONTROL +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DME5_DME_MEMORY_CONTROL +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + // addressBlock: dce_dc_hpo_hpo_top_dispdec //HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 #define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L #define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0x003F0000L + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO__SHIFT 0x8 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT_MASK 0x000000FFL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO_MASK 0x0000FF00L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +//AFMT5_AFMT_ACP +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE__SHIFT 0x0 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_MASK 0x00000003L +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +//AFMT5_AFMT_VBI_PACKET_CONTROL +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT 0xd +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK 0x00002000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT5_AFMT_AUDIO_INFO0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT5_AFMT_AUDIO_INFO1 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT5_AFMT_60958_0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT5_AFMT_60958_1 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_CONTROL +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT5_AFMT_RAMP_CONTROL0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT5_AFMT_RAMP_CONTROL1 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT5_AFMT_RAMP_CONTROL2 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_RAMP_CONTROL3 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_60958_2 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_RESULT +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT5_AFMT_STATUS +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT5_AFMT_INFOFRAME_CONTROL0 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT5_AFMT_AUDIO_SRC_CONTROL +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT5_AFMT_AUDIO_DBG_DTO_CNTL +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L +//AFMT5_AFMT_MEM_PWR +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG5_VPG_GENERIC_PACKET_DATA +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GENERIC_STATUS +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG5_VPG_MEM_PWR +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG5_VPG_ISRC1_2_ACCESS_CTRL +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG5_VPG_ISRC1_2_DATA +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO1 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME5_DME_CONTROL +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DME5_DME_MEMORY_CONTROL +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +//HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0x003F0000L + // addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec //DC_PERFMON26_PERFCOUNTER_CNTL diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h index a3373d1e1736..9b1132bbab07 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h @@ -6838,6 +6838,98 @@ #define mmDC_PERFMON15_PERFMON_LOW 0x08cf #define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL 0x08d4 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define mmHDMI_TB_ENC_CONTROL 0x08df +#define mmHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define mmHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define mmHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define mmHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define mmHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define mmHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_0 0x08f2 +#define mmHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_1 0x08f3 +#define mmHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_0 0x08f4 +#define mmHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_1 0x08f5 +#define mmHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_0 0x08f6 +#define mmHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_1 0x08f7 +#define mmHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define mmHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define mmHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define mmHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_MEM_CTRL 0x08fe +#define mmHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_CNTL 0x0903 +#define mmHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define mmHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_MODE 0x0908 +#define mmHDMI_TB_ENC_MODE_BASE_IDX 3 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define mmHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c @@ -6882,6 +6974,25 @@ #define mmDME2_DME_MEMORY_CONTROL 0x093d #define mmDME2_DME_MEMORY_CONTROL_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define mmHDMI_LINK_ENC_CONTROL 0x095b +#define mmHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_LINK_ENC_CLK_CTRL 0x095c +#define mmHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define mmHDMI_FRL_ENC_CONFIG 0x0965 +#define mmHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define mmHDMI_FRL_ENC_CONFIG2 0x0966 +#define mmHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define mmHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define mmHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hpo_top_dispdec // base address: 0x0 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h index 9549494b65b5..0326604ea9a7 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h @@ -26316,6 +26316,947 @@ #define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO__SHIFT 0x8 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT_MASK 0x000000FFL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO_MASK 0x0000FF00L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +//AFMT2_AFMT_ACP +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE__SHIFT 0x0 +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_MASK 0x00000003L +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +//AFMT2_AFMT_VBI_PACKET_CONTROL +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT 0xd +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK 0x00002000L +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT2_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT2_AFMT_AUDIO_INFO0 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT2_AFMT_AUDIO_INFO1 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT2_AFMT_60958_0 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT2_AFMT_60958_1 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT2_AFMT_AUDIO_CRC_CONTROL +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT2_AFMT_RAMP_CONTROL0 +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT2_AFMT_RAMP_CONTROL1 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT2_AFMT_RAMP_CONTROL2 +#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT2_AFMT_RAMP_CONTROL3 +#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT2_AFMT_60958_2 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT2_AFMT_AUDIO_CRC_RESULT +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT2_AFMT_STATUS +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT2_AFMT_AUDIO_PACKET_CONTROL +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT2_AFMT_INFOFRAME_CONTROL0 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT2_AFMT_AUDIO_SRC_CONTROL +#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT2_AFMT_AUDIO_DBG_DTO_CNTL +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L +//AFMT2_AFMT_MEM_PWR +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG2_VPG_GENERIC_PACKET_DATA +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GENERIC_STATUS +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG2_VPG_MEM_PWR +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG2_VPG_ISRC1_2_ACCESS_CTRL +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG2_VPG_ISRC1_2_DATA +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_MPEG_INFO0 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG2_VPG_MPEG_INFO1 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME2_DME_CONTROL +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DME2_DME_MEMORY_CONTROL +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + // addressBlock: dce_dc_hpo_hpo_top_dispdec //HPO_TOP_CLOCK_CONTROL diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h index 7fd906f10803..ad8c2dd480f2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h @@ -12907,9 +12907,41 @@ #define regDC_PERFMON22_PERFMON_LOW 0x0e6e #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c +#define regAFMT5_AFMT_ACP 0x091b +#define regAFMT5_AFMT_ACP_BASE_IDX 3 #define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c #define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d @@ -12981,6 +13013,83 @@ #define regVPG5_VPG_MPEG_INFO1 0x093a #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h index 07fbfafe6056..9c570d781c52 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h @@ -48391,6 +48391,124 @@ #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL @@ -48765,6 +48883,436 @@ #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_DEBUG_DATA +#define HDMI_TB_ENC_DEBUG_DATA__HDMI_DEBUG_DATA__SHIFT 0x0 +#define HDMI_TB_ENC_DEBUG_DATA__HDMI_DEBUG_DATA_MASK 0xFFFFFFFFL +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec //DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h index 20a6ee7adeef..3aeb01346c12 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h @@ -14560,6 +14560,96 @@ #define regDC_PERFMON22_PERFMON_LOW 0x08cf #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c @@ -14634,6 +14724,24 @@ #define regDME9_DME_MEMORY_CONTROL 0x093d #define regDME9_DME_MEMORY_CONTROL_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hpo_top_dispdec // base address: 0x2790c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h index d3d98d43287c..4fd16249a2db 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h @@ -59876,6 +59876,489 @@ #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL @@ -60252,6 +60735,67 @@ #define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L #define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + // addressBlock: dce_dc_hpo_hpo_top_dispdec //HPO_TOP_CLOCK_CONTROL diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h index 16a69d17bb1e..45ec5cb0f90c 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h @@ -12773,6 +12773,39 @@ #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c #define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c @@ -12845,6 +12878,84 @@ #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h index 6473362e39a8..6bc91ae44682 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h @@ -46664,6 +46664,126 @@ #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL #define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT 0xd @@ -47041,6 +47161,434 @@ #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec //DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL #define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h index a05bf8e4f58d..d289d8356adf 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h @@ -13503,6 +13503,39 @@ #define regDC_PERFMON22_PERFMON_LOW 0x0e6e #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c @@ -13578,6 +13611,84 @@ #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h index df84941bbe5b..dd98cd5582cf 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h @@ -50009,6 +50009,125 @@ #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL @@ -50386,6 +50505,433 @@ #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec //DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h index 78cb61d5800a..bc4524f9b462 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h @@ -12201,6 +12201,38 @@ #define regDP_STREAM_MAPPER_CONTROL3 0x0e59 #define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 +// addressBlock: dcn_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dcn_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + + +// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 // addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c @@ -12275,6 +12307,83 @@ #define regVPG5_VPG_MPEG_INFO1 0x093a #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dcn_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h index c20bf730dc55..a89fe19c4c84 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h @@ -43567,6 +43567,124 @@ #define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT 0x0 #define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK 0x00000007L +// addressBlock: dcn_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + +// addressBlock: dcn_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + // addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL @@ -43943,6 +44061,432 @@ #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L +// addressBlock: dcn_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL // addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec //DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h index a04b8c32c564..20deafe52a07 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h @@ -11814,7 +11814,6 @@ #define regDSCC0_DSCC_TEST_DEBUG_DATA0 0x303b #define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 - // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec // base address: 0x0 #define regDSCCIF0_DSCCIF_CONFIG0 0x3005 @@ -12173,6 +12172,19 @@ #define regHPO_TOP_HW_CONTROL 0x0e4a #define regHPO_TOP_HW_CONTROL_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + // addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec // base address: 0x27958 @@ -12185,6 +12197,39 @@ #define regDP_STREAM_MAPPER_CONTROL3 0x0e59 #define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c @@ -12259,6 +12304,83 @@ #define regVPG5_VPG_MPEG_INFO1 0x093a #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h index ce773fca621f..c22929134196 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h @@ -43576,6 +43576,125 @@ #define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT 0x0 #define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK 0x00000007L +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL @@ -43952,6 +44071,435 @@ #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec //DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h index d6a2839b4682..025e5490e6f1 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h @@ -5475,6 +5475,14 @@ #define regCHA_PERFCOUNTER3_HI_BASE_IDX 1 +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfddec +// base address: 0x34000 +#define regGC_CANE_PERFCOUNTER0_LO 0x36c0 +#define regGC_CANE_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGC_CANE_PERFCOUNTER0_HI 0x36c1 +#define regGC_CANE_PERFCOUNTER0_HI_BASE_IDX 1 + + // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfsdec // base address: 0x36000 #define regCPG_PERFCOUNTER1_SELECT 0x3800 @@ -5761,6 +5769,16 @@ #define regCHA_PERFCOUNTER3_SELECT1_BASE_IDX 1 +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfsdec +// base address: 0x36000 +#define regGC_CANE_PERFCOUNTER0_SELECT 0x3e80 +#define regGC_CANE_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGC_CANE_PERFCOUNTER0_SELECT1 0x3e81 +#define regGC_CANE_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGC_CANE_PERFCOUNTER0_MODE 0x3e82 +#define regGC_CANE_PERFCOUNTER0_MODE_BASE_IDX 1 + + // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk // base address: 0x3a014 #define regXVMIN_XVMIN_WR_DATA 0x4806 @@ -12080,6 +12098,22 @@ #define regGC_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmprdec +// base address: 0x353d0 +#define regGCUTCL2_FFBM_PERFCOUNTER_LO 0x34f4 +#define regGCUTCL2_FFBM_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER_HI 0x34f5 +#define regGCUTCL2_FFBM_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbprdec +// base address: 0x353e0 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_LO 0x34f8 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_HI 0x34f9 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_HI_BASE_IDX 1 + + // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbprdec // base address: 0x353f0 #define regGC_L2TLB_PERFCOUNTER_LO 0x34fc @@ -12176,6 +12210,82 @@ #define regGC_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmpldec +// base address: 0x37bb0 +#define regGCUTCL2_FFBM_PERFCOUNTER0_CFG 0x3eec +#define regGCUTCL2_FFBM_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER1_CFG 0x3eed +#define regGCUTCL2_FFBM_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER2_CFG 0x3eee +#define regGCUTCL2_FFBM_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER3_CFG 0x3eef +#define regGCUTCL2_FFBM_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER4_CFG 0x3ef0 +#define regGCUTCL2_FFBM_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER5_CFG 0x3ef1 +#define regGCUTCL2_FFBM_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER6_CFG 0x3ef2 +#define regGCUTCL2_FFBM_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER7_CFG 0x3ef3 +#define regGCUTCL2_FFBM_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER8_CFG 0x3ef4 +#define regGCUTCL2_FFBM_PERFCOUNTER8_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER9_CFG 0x3ef5 +#define regGCUTCL2_FFBM_PERFCOUNTER9_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER10_CFG 0x3ef6 +#define regGCUTCL2_FFBM_PERFCOUNTER10_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER11_CFG 0x3ef7 +#define regGCUTCL2_FFBM_PERFCOUNTER11_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER12_CFG 0x3ef8 +#define regGCUTCL2_FFBM_PERFCOUNTER12_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER13_CFG 0x3ef9 +#define regGCUTCL2_FFBM_PERFCOUNTER13_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER14_CFG 0x3efa +#define regGCUTCL2_FFBM_PERFCOUNTER14_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER15_CFG 0x3efb +#define regGCUTCL2_FFBM_PERFCOUNTER15_CFG_BASE_IDX 1 +#define regGCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL 0x3efc +#define regGCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbpldec +// base address: 0x37c00 +#define regGCUTCL2_NHTTLB_PERFCOUNTER0_CFG 0x3f00 +#define regGCUTCL2_NHTTLB_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER1_CFG 0x3f01 +#define regGCUTCL2_NHTTLB_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER2_CFG 0x3f02 +#define regGCUTCL2_NHTTLB_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER3_CFG 0x3f03 +#define regGCUTCL2_NHTTLB_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER4_CFG 0x3f04 +#define regGCUTCL2_NHTTLB_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER5_CFG 0x3f05 +#define regGCUTCL2_NHTTLB_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER6_CFG 0x3f06 +#define regGCUTCL2_NHTTLB_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER7_CFG 0x3f07 +#define regGCUTCL2_NHTTLB_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER8_CFG 0x3f08 +#define regGCUTCL2_NHTTLB_PERFCOUNTER8_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER9_CFG 0x3f09 +#define regGCUTCL2_NHTTLB_PERFCOUNTER9_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER10_CFG 0x3f0a +#define regGCUTCL2_NHTTLB_PERFCOUNTER10_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER11_CFG 0x3f0b +#define regGCUTCL2_NHTTLB_PERFCOUNTER11_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER12_CFG 0x3f0c +#define regGCUTCL2_NHTTLB_PERFCOUNTER12_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER13_CFG 0x3f0d +#define regGCUTCL2_NHTTLB_PERFCOUNTER13_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER14_CFG 0x3f0e +#define regGCUTCL2_NHTTLB_PERFCOUNTER14_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER15_CFG 0x3f0f +#define regGCUTCL2_NHTTLB_PERFCOUNTER15_CFG_BASE_IDX 1 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL 0x3f10 +#define regGCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpldec // base address: 0x37c50 #define regGC_L2TLB_PERFCOUNTER0_CFG 0x3f14 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h index f606c5cd03c5..1cf890de35cb 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h @@ -16951,6 +16951,15 @@ #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfddec +//GC_CANE_PERFCOUNTER0_LO +#define GC_CANE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GC_CANE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GC_CANE_PERFCOUNTER0_HI +#define GC_CANE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GC_CANE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfsdec //CPG_PERFCOUNTER1_SELECT #define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 @@ -18123,6 +18132,46 @@ #define CHA_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfsdec +//GC_CANE_PERFCOUNTER0_SELECT +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GC_CANE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GC_CANE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GC_CANE_PERFCOUNTER0_SELECT1 +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GC_CANE_PERFCOUNTER0_MODE +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE0__SHIFT 0x0 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE1__SHIFT 0x2 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE2__SHIFT 0x4 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE3__SHIFT 0x6 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE0__SHIFT 0x8 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE1__SHIFT 0xc +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE2__SHIFT 0x10 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE3__SHIFT 0x14 +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE0_MASK 0x00000003L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE1_MASK 0x0000000CL +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE2_MASK 0x00000030L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE3_MASK 0x000000C0L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE0_MASK 0x00000F00L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE1_MASK 0x0000F000L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE2_MASK 0x000F0000L +#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE3_MASK 0x00F00000L + + // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk //XVMIN_XVMIN_WR_DATA #define XVMIN_XVMIN_WR_DATA__XVMINDATA__SHIFT 0x0 @@ -43203,6 +43252,28 @@ #define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmprdec +//GCUTCL2_FFBM_PERFCOUNTER_LO +#define GCUTCL2_FFBM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCUTCL2_FFBM_PERFCOUNTER_HI +#define GCUTCL2_FFBM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCUTCL2_FFBM_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCUTCL2_FFBM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbprdec +//GCUTCL2_NHTTLB_PERFCOUNTER_LO +#define GCUTCL2_NHTTLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCUTCL2_NHTTLB_PERFCOUNTER_HI +#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbprdec //GC_L2TLB_PERFCOUNTER_LO #define GC_L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 @@ -43660,6 +43731,390 @@ #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmpldec +//GCUTCL2_FFBM_PERFCOUNTER0_CFG +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER1_CFG +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER2_CFG +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER3_CFG +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER4_CFG +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER5_CFG +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER6_CFG +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER7_CFG +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER8_CFG +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER9_CFG +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER10_CFG +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER11_CFG +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER12_CFG +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER13_CFG +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER14_CFG +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER15_CFG +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbpldec +//GCUTCL2_NHTTLB_PERFCOUNTER0_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER1_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER2_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER3_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER4_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER5_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER6_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER7_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER8_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER9_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER10_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER11_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER12_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER13_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER14_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER15_CFG +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpldec //GC_L2TLB_PERFCOUNTER0_CFG #define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h new file mode 100755 index 000000000000..f10e6168ad54 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h @@ -0,0 +1,149 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_12_1_1_OFFSET_HEADER +#define _gc_12_1_1_OFFSET_HEADER + + + +// addressBlock: aigc_grbma_grbma_grbmadec +// base address: 0x18000 +#define regGRBMA_GFX_INDEX 0x0011 +#define regGRBMA_GFX_INDEX_BASE_IDX 1 + + +// addressBlock: aigc_grbma_grbma_perfddec +// base address: 0x19200 +#define regGRBMA_PERFCOUNTER0_LO 0x0480 +#define regGRBMA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGRBMA_PERFCOUNTER0_HI 0x0481 +#define regGRBMA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGRBMA_PERFCOUNTER1_LO 0x0482 +#define regGRBMA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGRBMA_PERFCOUNTER1_HI 0x0483 +#define regGRBMA_PERFCOUNTER1_HI_BASE_IDX 1 + + +// addressBlock: aigc_grbma_grbma_perfsdec +// base address: 0x19300 +#define regGRBMA_PERFCOUNTER0_SELECT 0x04c0 +#define regGRBMA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGRBMA_PERFCOUNTER1_SELECT 0x04c1 +#define regGRBMA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regAID_PERFMON_CNTL 0x04c2 +#define regAID_PERFMON_CNTL_BASE_IDX 1 + + +// addressBlock: aigc_gl2x_gfx_se_perfsdec +// base address: 0x19300 +#define regGL2C_PERFCOUNTER0_SELECT 0x04e8 +#define regGL2C_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_SELECT1 0x04e9 +#define regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_SELECT 0x04ea +#define regGL2C_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_SELECT1 0x04eb +#define regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_SELECT 0x04ec +#define regGL2C_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_SELECT1 0x04ed +#define regGL2C_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_SELECT 0x04ee +#define regGL2C_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_SELECT1 0x04ef +#define regGL2C_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_SELECT 0x04f0 +#define regGL2A_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_SELECT1 0x04f1 +#define regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_SELECT 0x04f2 +#define regGL2A_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_SELECT1 0x04f3 +#define regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_SELECT 0x04f4 +#define regGL2A_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_SELECT1 0x04f5 +#define regGL2A_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_SELECT 0x04f6 +#define regGL2A_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_SELECT1 0x04f7 +#define regGL2A_PERFCOUNTER3_SELECT1_BASE_IDX 1 + + +// addressBlock: aigc_gl2x_gfx_se_perfddec +// base address: 0x19200 +#define regGL2C_PERFCOUNTER0_LO 0x04a0 +#define regGL2C_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER0_HI 0x04a1 +#define regGL2C_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_LO 0x04a2 +#define regGL2C_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER1_HI 0x04a3 +#define regGL2C_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_LO 0x04a4 +#define regGL2C_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER2_HI 0x04a5 +#define regGL2C_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_LO 0x04a6 +#define regGL2C_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL2C_PERFCOUNTER3_HI 0x04a7 +#define regGL2C_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_LO 0x04a8 +#define regGL2A_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER0_HI 0x04a9 +#define regGL2A_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_LO 0x04aa +#define regGL2A_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER1_HI 0x04ab +#define regGL2A_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_LO 0x04ac +#define regGL2A_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER2_HI 0x04ad +#define regGL2A_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_LO 0x04ae +#define regGL2A_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL2A_PERFCOUNTER3_HI 0x04af +#define regGL2A_PERFCOUNTER3_HI_BASE_IDX 1 + + +// addressBlock: aigc_gfx_gcea_se_gfx_se_perfsdec +// base address: 0x19320 +#define regGC_EA_SE_PERFCOUNTER0_SELECT 0x04c8 +#define regGC_EA_SE_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGC_EA_SE_PERFCOUNTER0_SELECT1 0x04c9 +#define regGC_EA_SE_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGC_EA_SE_PERFCOUNTER1_SELECT 0x04ca +#define regGC_EA_SE_PERFCOUNTER1_SELECT_BASE_IDX 1 + + +// addressBlock: aigc_gfx_gcea_se_gfx_se_perfddec +// base address: 0x19240 +#define regGC_EA_SE_PERFCOUNTER0_LO 0x0490 +#define regGC_EA_SE_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGC_EA_SE_PERFCOUNTER0_HI 0x0491 +#define regGC_EA_SE_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGC_EA_SE_PERFCOUNTER1_LO 0x0492 +#define regGC_EA_SE_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGC_EA_SE_PERFCOUNTER1_HI 0x0493 +#define regGC_EA_SE_PERFCOUNTER1_HI_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h new file mode 100755 index 000000000000..8d09c8150a53 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h @@ -0,0 +1,377 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_12_1_1_SH_MASK_HEADER +#define _gc_12_1_1_SH_MASK_HEADER + + +// addressBlock: aigc_grbma_grbma_grbmadec +//GRBMA_GFX_INDEX +#define GRBMA_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBMA_GFX_INDEX__SA_INDEX__SHIFT 0x8 +#define GRBMA_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBMA_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT 0x1d +#define GRBMA_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBMA_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBMA_GFX_INDEX__INSTANCE_INDEX_MASK 0x0000007FL +#define GRBMA_GFX_INDEX__SA_INDEX_MASK 0x00000300L +#define GRBMA_GFX_INDEX__SE_INDEX_MASK 0x000F0000L +#define GRBMA_GFX_INDEX__SA_BROADCAST_WRITES_MASK 0x20000000L +#define GRBMA_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBMA_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L + + +// addressBlock: aigc_grbma_grbma_perfddec +//GRBMA_PERFCOUNTER0_LO +#define GRBMA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBMA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBMA_PERFCOUNTER0_HI +#define GRBMA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBMA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBMA_PERFCOUNTER1_LO +#define GRBMA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBMA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBMA_PERFCOUNTER1_HI +#define GRBMA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBMA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aigc_grbma_grbma_perfsdec +//GRBMA_PERFCOUNTER0_SELECT +#define GRBMA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBMA_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBMA_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x7 +#define GRBMA_PERFCOUNTER0_SELECT__PMR_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBMA_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBMA_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xa +#define GRBMA_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBMA_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xc +#define GRBMA_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBMA_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBMA_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBMA_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBMA_PERFCOUNTER0_SELECT__XCAC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBMA_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBMA_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBMA_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBMA_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBMA_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBMA_PERFCOUNTER0_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBMA_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBMA_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBMA_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBMA_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBMA_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBMA_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBMA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBMA_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBMA_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000080L +#define GRBMA_PERFCOUNTER0_SELECT__PMR_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBMA_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBMA_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBMA_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBMA_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBMA_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBMA_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBMA_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBMA_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBMA_PERFCOUNTER0_SELECT__XCAC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBMA_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBMA_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBMA_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBMA_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBMA_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBMA_PERFCOUNTER0_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBMA_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBMA_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBMA_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBMA_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBMA_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBMA_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//GRBMA_PERFCOUNTER1_SELECT +#define GRBMA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBMA_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBMA_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x7 +#define GRBMA_PERFCOUNTER1_SELECT__PMR_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBMA_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBMA_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xa +#define GRBMA_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBMA_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xc +#define GRBMA_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBMA_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBMA_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBMA_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBMA_PERFCOUNTER1_SELECT__XCAC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBMA_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBMA_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBMA_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBMA_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBMA_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBMA_PERFCOUNTER1_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBMA_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBMA_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBMA_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBMA_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBMA_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBMA_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBMA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBMA_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBMA_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000080L +#define GRBMA_PERFCOUNTER1_SELECT__PMR_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBMA_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBMA_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBMA_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBMA_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBMA_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBMA_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBMA_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBMA_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBMA_PERFCOUNTER1_SELECT__XCAC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBMA_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBMA_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBMA_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBMA_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBMA_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBMA_PERFCOUNTER1_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBMA_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBMA_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBMA_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBMA_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBMA_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBMA_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//AID_PERFMON_CNTL +#define AID_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define AID_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define AID_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define AID_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define AID_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL +#define AID_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L +#define AID_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define AID_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L + + +// addressBlock: aigc_gl2x_gfx_se_perfsdec +//GL2C_PERFCOUNTER0_SELECT +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER0_SELECT1 +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2C_PERFCOUNTER1_SELECT +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER1_SELECT1 +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2C_PERFCOUNTER2_SELECT +#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER2_SELECT1 +#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2C_PERFCOUNTER3_SELECT +#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2C_PERFCOUNTER3_SELECT1 +#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2A_PERFCOUNTER0_SELECT +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER0_SELECT1 +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2A_PERFCOUNTER1_SELECT +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER1_SELECT1 +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2A_PERFCOUNTER2_SELECT +#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER2_SELECT1 +#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL2A_PERFCOUNTER3_SELECT +#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL2A_PERFCOUNTER3_SELECT1 +#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L + + +// addressBlock: aigc_gfx_gcea_se_gfx_se_perfsdec +//GC_EA_SE_PERFCOUNTER0_SELECT +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GC_EA_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GC_EA_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GC_EA_SE_PERFCOUNTER0_SELECT1 +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GC_EA_SE_PERFCOUNTER1_SELECT +#define GC_EA_SE_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c +#define GC_EA_SE_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GC_EA_SE_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L + + +// addressBlock: aigc_gfx_gcea_se_gfx_se_perfddec +//GC_EA_SE_PERFCOUNTER0_LO +#define GC_EA_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GC_EA_SE_PERFCOUNTER0_HI +#define GC_EA_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GC_EA_SE_PERFCOUNTER1_LO +#define GC_EA_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GC_EA_SE_PERFCOUNTER1_HI +#define GC_EA_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GC_EA_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h new file mode 100644 index 000000000000..0b42c1c9c848 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h @@ -0,0 +1,13149 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_6_3_2_OFFSET_HEADER +#define _nbio_6_3_2_OFFSET_HEADER + + + +// addressBlock: nbif0_nbif0_bif_bx_SYSDEC +// base address: 0x0 +#define regBIF_BX0_SYSHUB_INDEX_OVLP 0x0008 +#define regBIF_BX0_SYSHUB_INDEX_OVLP_BASE_IDX 0 +#define regBIF_BX0_SYSHUB_DATA_OVLP 0x0009 +#define regBIF_BX0_SYSHUB_DATA_OVLP_BASE_IDX 0 +#define regBIF_BX0_SYSHUB_INDEX_HI_OVLP 0x000a +#define regBIF_BX0_SYSHUB_INDEX_HI_OVLP_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX 0x000c +#define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA 0x000d +#define regBIF_BX0_PCIE_DATA_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2 0x000e +#define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA2 0x000f +#define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX_HI 0x0010 +#define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2_HI 0x0011 +#define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0 +#define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 +#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 +#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 +#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 +#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_0 0x0038 +#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_1 0x0039 +#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_2 0x003a +#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_3 0x003b +#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_4 0x003c +#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_5 0x003d +#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_6 0x003e +#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_7 0x003f +#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_8 0x0040 +#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_9 0x0041 +#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_10 0x0042 +#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_11 0x0043 +#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_12 0x0044 +#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_13 0x0045 +#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_14 0x0046 +#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_15 0x0047 +#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c +#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d +#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e +#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_Engine_INTR_CNTL 0x004f +#define regBIF_BX0_BIF_Engine_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_0 0x0080 +#define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_1 0x0081 +#define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_2 0x0082 +#define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_3 0x0083 +#define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_4 0x0084 +#define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_5 0x0085 +#define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_6 0x0086 +#define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_7 0x0087 +#define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_8 0x0088 +#define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_9 0x0089 +#define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_10 0x008a +#define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_11 0x008b +#define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_12 0x008c +#define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_13 0x008d +#define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_14 0x008e +#define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_15 0x008f +#define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_0 0x0090 +#define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_1 0x0091 +#define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_2 0x0092 +#define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_3 0x0093 +#define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_4 0x0094 +#define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_5 0x0095 +#define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_6 0x0096 +#define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_7 0x0097 +#define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_8 0x0098 +#define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_9 0x0099 +#define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_10 0x009a +#define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_11 0x009b +#define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_12 0x009c +#define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_13 0x009d +#define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_14 0x009e +#define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_15 0x009f +#define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0 +#define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1 +#define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2 +#define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3 +#define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4 +#define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5 +#define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6 +#define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7 +#define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8 +#define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9 +#define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa +#define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab +#define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1 + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0068 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0069 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x006b +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x006c +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x006d +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x006e +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x006f +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0070 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0071 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x0072 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x0074 +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x0075 +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x0076 +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x0077 +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0078 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0079 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x004b +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x004d +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x004e +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x004f +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0050 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0051 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0052 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0054 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x0055 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x0055 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x0055 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x0055 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x0056 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x0056 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x0056 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x0056 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x0057 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x0058 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x005a +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x005b +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x005b +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x005b +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x005c +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x005c +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x005c +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x005c +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x005d +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x005d +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x005d +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x005d +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x005e +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0060 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0061 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0062 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0063 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x0064 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3 0x0065 +#define regRCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_PF0_MM_INDEX 0x0000 +#define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_PF0_MM_DATA 0x0001 +#define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 +#define regBIF_BX_PF0_MM_INDEX_HI 0x0006 +#define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 +#define regBIF_BX_PF0_RSMU_INDEX 0x0000 +#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_DATA 0x0001 +#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002 +#define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1 + + +// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1 +// base address: 0x0 +#define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 +#define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BUS_CNTL 0x00e7 +#define regBIF_BX0_BUS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH0 0x00e8 +#define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH1 0x00e9 +#define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_EN 0x00ed +#define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 +#define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee +#define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_CNTL 0x00f0 +#define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL 0x00f1 +#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 +#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 +#define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 +#define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd +#define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FB_EN 0x0100 +#define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 +#define regBIF_BX0_BIF_INTR_CNTL 0x0101 +#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BACO_CNTL 0x010b +#define regBIF_BX0_BACO_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIME0 0x010c +#define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER1 0x010d +#define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER2 0x010e +#define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER3 0x010f +#define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER4 0x0110 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX 2 +#define regBIF_BX0_MEM_TYPE_CNTL 0x0111 +#define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2 +#define regBIF_BX0_VF_REGWR_EN 0x0124 +#define regBIF_BX0_VF_REGWR_EN_BASE_IDX 2 +#define regBIF_BX0_VF_DOORBELL_EN 0x0125 +#define regBIF_BX0_VF_DOORBELL_EN_BASE_IDX 2 +#define regBIF_BX0_VF_FB_EN 0x0126 +#define regBIF_BX0_VF_FB_EN_BASE_IDX 2 +#define regBIF_BX0_VF_REGWR_STATUS 0x0127 +#define regBIF_BX0_VF_REGWR_STATUS_BASE_IDX 2 +#define regBIF_BX0_VF_DOORBELL_STATUS 0x0128 +#define regBIF_BX0_VF_DOORBELL_STATUS_BASE_IDX 2 +#define regBIF_BX0_VF_FB_STATUS 0x0129 +#define regBIF_BX0_VF_FB_STATUS_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_CNTL 0x012f +#define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_BASE 0x0130 +#define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_RPTR 0x0131 +#define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR 0x0132 +#define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 +#define regBIF_BX0_MAILBOX_INDEX 0x0135 +#define regBIF_BX0_MAILBOX_INDEX_BASE_IDX 2 +#define regBIF_BX0_BACO_AZ_ENHANCE_CTRL 0x0141 +#define regBIF_BX0_BACO_AZ_ENHANCE_CTRL_BASE_IDX 2 +#define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142 +#define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2 +#define regBIF_BX0_BIF_PERSTB_PAD_CNTL 0x0145 +#define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_PX_EN_PAD_CNTL 0x0146 +#define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL 0x0147 +#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL 0x0148 +#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL 0x0149 +#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE 0x0165 +#define regBIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_RESET_EN 0x0088 +#define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c +#define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 +#define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 +#define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca +#define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1 +// base address: 0x0 +#define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 +#define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 +#define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP10 0x0002 +#define regRCC_STRAP0_RCC_BIF_STRAP10_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP11 0x0003 +#define regRCC_STRAP0_RCC_BIF_STRAP11_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP12 0x0004 +#define regRCC_STRAP0_RCC_BIF_STRAP12_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP13 0x0005 +#define regRCC_STRAP0_RCC_BIF_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP2 0x0006 +#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP3 0x0007 +#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP4 0x0008 +#define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP5 0x0009 +#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP6 0x000a +#define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP7 0x000b +#define regRCC_STRAP0_RCC_BIF_STRAP7_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP8 0x000c +#define regRCC_STRAP0_RCC_BIF_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP9 0x000d +#define regRCC_STRAP0_RCC_BIF_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x000e +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x000f +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0010 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x0011 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x0012 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x0013 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x0014 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP15 0x0015 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP15_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP16 0x0016 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP16_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP17 0x0017 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP17_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP18 0x0018 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP18_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x0019 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x001a +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x001b +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x001c +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x001d +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x001e +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x001f +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0020 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0021 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0022 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0023 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0024 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x0025 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x0026 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x0027 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x0028 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP19 0x0029 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP19_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x002a +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP22 0x002b +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP22_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP23 0x002c +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP23_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP24 0x002d +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP24_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x002e +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x002f +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0030 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0031 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0032 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0033 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP1 0x0034 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10 0x0035 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11 0x0036 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12 0x0037 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13 0x0038 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14 0x0039 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP15 0x003a +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP15_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP16 0x003b +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP16_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP17 0x003c +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP17_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP18 0x003d +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP18_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP19 0x003e +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP19_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x003f +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0040 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0041 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 0x0042 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 0x0043 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0044 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x0045 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x0046 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x0047 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x0048 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP8 0x0049 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP9 0x004a +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP9_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb +#define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_CONTROL 0x013e +#define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_PF0_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_gdc_GDCDEC +// base address: 0x0 +#define regGDC0_NGDC_SDP_PORT_CTRL 0x0180 +#define regGDC0_NGDC_SDP_PORT_CTRL_BASE_IDX 2 +#define regGDC0_SHUB_REGS_IF_CTL 0x0181 +#define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 2 +#define regGDC0_NGDC_MGCG_CTRL 0x0187 +#define regGDC0_NGDC_MGCG_CTRL_BASE_IDX 2 +#define regGDC0_S2A_MISC_CNTL 0x0188 +#define regGDC0_S2A_MISC_CNTL_BASE_IDX 2 +#define regGDC0_NGDC_MCA_SMN_CTRL0 0x018b +#define regGDC0_NGDC_MCA_SMN_CTRL0_BASE_IDX 2 +#define regGDC0_NGDC_EARLY_WAKEUP_CTRL 0x018c +#define regGDC0_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 2 +#define regGDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL 0x0198 +#define regGDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL_BASE_IDX 2 +#define regGDC0_GDC_DMA_SION_PCTRL 0x0199 +#define regGDC0_GDC_DMA_SION_PCTRL_BASE_IDX 2 +#define regGDC0_NGDC_MP4SDP_CNTL 0x019b +#define regGDC0_NGDC_MP4SDP_CNTL_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF0 0x01f3 +#define regGDC0_DOORBELL_VCN_TARGET_VF0_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF1 0x01f3 +#define regGDC0_DOORBELL_VCN_TARGET_VF1_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF2 0x01f4 +#define regGDC0_DOORBELL_VCN_TARGET_VF2_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF3 0x01f4 +#define regGDC0_DOORBELL_VCN_TARGET_VF3_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF4 0x01f5 +#define regGDC0_DOORBELL_VCN_TARGET_VF4_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF5 0x01f5 +#define regGDC0_DOORBELL_VCN_TARGET_VF5_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF6 0x01f6 +#define regGDC0_DOORBELL_VCN_TARGET_VF6_BASE_IDX 2 +#define regGDC0_DOORBELL_VCN_TARGET_VF7 0x01f6 +#define regGDC0_DOORBELL_VCN_TARGET_VF7_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_PF 0x01f7 +#define regGDC0_DOORBELL_ACCESS_EN_PF_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF0 0x01f7 +#define regGDC0_DOORBELL_ACCESS_EN_VF0_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF1 0x01f8 +#define regGDC0_DOORBELL_ACCESS_EN_VF1_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF2 0x01f8 +#define regGDC0_DOORBELL_ACCESS_EN_VF2_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF3 0x01f9 +#define regGDC0_DOORBELL_ACCESS_EN_VF3_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF4 0x01f9 +#define regGDC0_DOORBELL_ACCESS_EN_VF4_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF5 0x01fa +#define regGDC0_DOORBELL_ACCESS_EN_VF5_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF6 0x01fa +#define regGDC0_DOORBELL_ACCESS_EN_VF6_BASE_IDX 2 +#define regGDC0_DOORBELL_ACCESS_EN_VF7 0x01fb +#define regGDC0_DOORBELL_ACCESS_EN_VF7_BASE_IDX 2 +#define regGDC0_NGDC_CNDI_BUS_PORT_CTRL 0x01fc +#define regGDC0_NGDC_CNDI_BUS_PORT_CTRL_BASE_IDX 2 +#define regGDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL 0x01fd +#define regGDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC +// base address: 0x0 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL 0x01cb +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1 0x01cc +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL 0x01cd +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1 0x01ce +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL 0x01cf +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1 0x01d0 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL 0x01d1 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1 0x01d2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL 0x01d3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1 0x01d4 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL 0x01d5 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1 0x01d6 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL 0x01d7 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1 0x01d8 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL 0x01d9 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1 0x01da +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL 0x01db +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1 0x01dc +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL 0x01dd +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1 0x01de +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL 0x01df +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1 0x01e0 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL 0x01e1 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1 0x01e2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL 0x01e3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1 0x01e4 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL 0x01e5 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1 0x01e6 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL 0x01e7 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1 0x01e8 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL 0x01e9 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1 0x01ea +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1_BASE_IDX 2 +#define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG 0x01eb +#define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 2 +#define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS 0x01ec +#define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f +#define cfgVENDOR_CAP_LIST 0x0048 +#define cfgADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0664 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0668 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x066c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x06dc +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x06e0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x06e2 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_RTR_DATA2 0x0724 +#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0728 +#define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x072c +#define cfgPCIE_PWR_BUDGET_DATA 0x0730 +#define cfgPCIE_PWR_BUDGET_CAP 0x0734 +#define cfgPCIE_DPA_ENH_CAP_LIST 0x0738 +#define cfgPCIE_DPA_CAP 0x073c +#define cfgPCIE_DPA_LATENCY_INDICATOR 0x0740 +#define cfgPCIE_DPA_STATUS 0x0744 +#define cfgPCIE_DPA_CNTL 0x0746 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0748 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0749 +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x074a +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x074b +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x074c +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x074d +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x074e +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x074f +#define cfgPCIE_LTR_ENH_CAP_LIST 0x0768 +#define cfgPCIE_LTR_CAP 0x076c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x0776 +#define cfgPCIE_BAR_ENH_CAP_LIST 0x0778 +#define cfgPCIE_BAR1_CAP 0x077c +#define cfgPCIE_BAR1_CNTL 0x0780 +#define cfgPCIE_BAR2_CAP 0x0784 +#define cfgPCIE_BAR2_CNTL 0x0788 +#define cfgPCIE_BAR3_CAP 0x078c +#define cfgPCIE_BAR3_CNTL 0x0790 +#define cfgPCIE_BAR4_CAP 0x0794 +#define cfgPCIE_BAR4_CNTL 0x0798 +#define cfgPCIE_BAR5_CAP 0x079c +#define cfgPCIE_BAR5_CNTL 0x07a0 +#define cfgPCIE_BAR6_CAP 0x07a4 +#define cfgPCIE_BAR6_CNTL 0x07a8 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x07b2 +#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x07b4 +#define cfgPCIE_PAGE_REQ_CNTL 0x07b8 +#define cfgPCIE_PAGE_REQ_STATUS 0x07ba +#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x07bc +#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x07c0 +#define cfgPCIE_PASID_ENH_CAP_LIST 0x07c4 +#define cfgPCIE_PASID_CAP 0x07c8 +#define cfgPCIE_PASID_CNTL 0x07ca +#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x07cc +#define cfgPCIE_SRIOV_CAP 0x07d0 +#define cfgPCIE_SRIOV_CONTROL 0x07d4 +#define cfgPCIE_SRIOV_STATUS 0x07d6 +#define cfgPCIE_SRIOV_INITIAL_VFS 0x07d8 +#define cfgPCIE_SRIOV_TOTAL_VFS 0x07da +#define cfgPCIE_SRIOV_NUM_VFS 0x07dc +#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x07de +#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x07e0 +#define cfgPCIE_SRIOV_VF_STRIDE 0x07e2 +#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x07e6 +#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x07e8 +#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x07ec +#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x07f0 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x07f4 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x07f8 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x07fc +#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0800 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0804 +#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x0808 +#define cfgPCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x08e0 +#define cfgPCIE_VF_RESIZE_BAR1_CAP 0x08e4 +#define cfgPCIE_VF_RESIZE_BAR1_CNTL 0x08e8 +#define cfgPCIE_VF_RESIZE_BAR2_CAP 0x08ec +#define cfgPCIE_VF_RESIZE_BAR2_CNTL 0x08f0 +#define cfgPCIE_VF_RESIZE_BAR3_CAP 0x08f4 +#define cfgPCIE_VF_RESIZE_BAR3_CNTL 0x08f8 +#define cfgPCIE_VF_RESIZE_BAR4_CAP 0x08fc +#define cfgPCIE_VF_RESIZE_BAR4_CNTL 0x0900 +#define cfgPCIE_VF_RESIZE_BAR5_CAP 0x0904 +#define cfgPCIE_VF_RESIZE_BAR5_CNTL 0x0908 +#define cfgPCIE_VF_RESIZE_BAR6_CAP 0x090c +#define cfgPCIE_VF_RESIZE_BAR6_CNTL 0x0910 +#define cfgPCIE_DOE_ENH_CAP_LIST 0x0914 +#define cfgPCIE_DOE_CAP 0x0918 +#define cfgPCIE_DOE_CNTL 0x091c +#define cfgPCIE_DOE_STS 0x0920 +#define cfgPCIE_DOE_WMBOX 0x0924 +#define cfgPCIE_DOE_RMBOX 0x0928 +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x09ac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x09b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x09b4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x09b8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x09bc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x09c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x09c4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x09c8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x09cc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x09d4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x09dc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x09e0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0 0x0a04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x0a08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x0a0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x0a10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x0a14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0 0x0a1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1 0x0a20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2 0x0a24 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3 0x0a28 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4 0x0a2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5 0x0a30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6 0x0a34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7 0x0a38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8 0x0a3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0 0x0a4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1 0x0a50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2 0x0a54 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3 0x0a58 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4 0x0a5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5 0x0a60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6 0x0a64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7 0x0a68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8 0x0a6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0 0x0a7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1 0x0a80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2 0x0a84 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3 0x0a88 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4 0x0a8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5 0x0a90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6 0x0a94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7 0x0a98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8 0x0a9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0 0x0aac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1 0x0ab0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2 0x0ab4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3 0x0ab8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4 0x0abc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5 0x0ac0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6 0x0ac4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7 0x0ac8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8 0x0acc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0 0x0adc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1 0x0ae0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2 0x0ae4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3 0x0ae8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4 0x0aec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5 0x0af0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6 0x0af4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7 0x0af8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8 0x0afc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0 0x0b0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1 0x0b10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2 0x0b14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3 0x0b18 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4 0x0b1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5 0x0b20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6 0x0b24 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7 0x0b28 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8 0x0b2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0 0x0b3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1 0x0b40 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2 0x0b44 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3 0x0b48 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4 0x0b4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5 0x0b50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6 0x0b54 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7 0x0b58 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8 0x0b5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0 0x0b6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1 0x0b70 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2 0x0b74 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3 0x0b78 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4 0x0b7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5 0x0b80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6 0x0b84 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7 0x0b88 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8 0x0b8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0 0x0b9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1 0x0ba0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2 0x0ba4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3 0x0ba8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4 0x0bac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5 0x0bb0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6 0x0bb4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7 0x0bb8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8 0x0bbc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0 0x0bcc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1 0x0bd0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2 0x0bd4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3 0x0bd8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4 0x0bdc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5 0x0be0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6 0x0be4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7 0x0be8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8 0x0bec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0 0x0bfc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1 0x0c00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2 0x0c04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3 0x0c08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4 0x0c0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5 0x0c10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6 0x0c14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7 0x0c18 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8 0x0c1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0 0x0c2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1 0x0c30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2 0x0c34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3 0x0c38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4 0x0c3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5 0x0c40 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6 0x0c44 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7 0x0c48 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8 0x0c4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0 0x0c5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1 0x0c60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2 0x0c64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3 0x0c68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4 0x0c6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5 0x0c70 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6 0x0c74 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7 0x0c78 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8 0x0c7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0 0x0c8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1 0x0c90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2 0x0c94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3 0x0c98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4 0x0c9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5 0x0ca0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6 0x0ca4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7 0x0ca8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8 0x0cac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0 0x0cbc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1 0x0cc0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2 0x0cc4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3 0x0cc8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4 0x0ccc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5 0x0cd0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6 0x0cd4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7 0x0cd8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8 0x0cdc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0 0x0cec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1 0x0cf0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2 0x0cf4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3 0x0cf8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4 0x0cfc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5 0x0d00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6 0x0d04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7 0x0d08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8 0x0d0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0 0x0d1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1 0x0d20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2 0x0d24 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3 0x0d28 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4 0x0d2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5 0x0d30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6 0x0d34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7 0x0d38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8 0x0d3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0 0x0d4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1 0x0d50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2 0x0d54 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3 0x0d58 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4 0x0d5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5 0x0d60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6 0x0d64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7 0x0d68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8 0x0d6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0 0x0d7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1 0x0d80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2 0x0d84 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3 0x0d88 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4 0x0d8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5 0x0d90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6 0x0d94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7 0x0d98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8 0x0d9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0 0x0dac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1 0x0db0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2 0x0db4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3 0x0db8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4 0x0dbc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5 0x0dc0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6 0x0dc4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7 0x0dc8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8 0x0dcc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE 0x0ddc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE 0x0de0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE 0x0de4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE 0x0de8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS 0x0dec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS 0x0df0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS 0x0df4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS 0x0df8 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0114 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0118 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x011c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x011e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0120 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0122 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0126 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0128 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x012a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x012c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x012e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0132 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0134 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0136 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0138 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x013a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x01b8 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x01bc +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x01c0 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x01c4 +#define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x01c8 +#define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x01cc +#define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x01d0 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x01d8 +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x01d9 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x01da +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x01db +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x01dc +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x01dd +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x01de +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x01df +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x01e0 +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x01e1 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x01e2 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x01e3 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x01e4 +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x01e5 +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x01e6 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x01e7 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST 0x01f8 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x01fc +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x0200 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x0204 +#define cfgBIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1 0x0208 +#define cfgBIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2 0x020c +#define cfgBIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1 0x0210 +#define cfgBIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2 0x0214 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT 0x0218 +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT 0x0219 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT 0x021a +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT 0x021b +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT 0x021c +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT 0x021d +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT 0x021e +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT 0x021f +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT 0x0220 +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT 0x0221 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT 0x0222 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT 0x0223 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT 0x0224 +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT 0x0225 +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT 0x0226 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT 0x0227 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST 0x0238 +#define cfgBIF_CFG_DEV0_EPF0_AP_CAP 0x023c +#define cfgBIF_CFG_DEV0_EPF0_AP_CNTL 0x0240 +#define cfgBIF_CFG_DEV0_EPF0_AP_DATA1 0x0244 +#define cfgBIF_CFG_DEV0_EPF0_AP_DATA2 0x0248 +#define cfgBIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK 0x024c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x0256 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x0258 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x025a +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x025c +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x025e +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x0260 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x0262 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x0264 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x0266 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x0268 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x026a +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x026c +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x026e +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x0270 +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x0272 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x0274 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x0276 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x0278 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x027a +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x027c +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x027e +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x0282 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x0286 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x028a +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x028c +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x028e +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x0292 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x0296 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0404 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0408 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x040c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x0410 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x0412 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0414 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0418 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x041e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x0420 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0424 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x042a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x0430 +#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x0434 +#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x0438 +#define cfgBIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST 0x0e00 +#define cfgBIF_CFG_DEV0_EPF0_IDE_CAP 0x0e04 +#define cfgBIF_CFG_DEV0_EPF0_IDE_CNTL 0x0e08 +#define cfgBIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL 0x0e0c +#define cfgBIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS 0x0e10 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP 0x0e14 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL 0x0e18 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS 0x0e1c +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1 0x0e20 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2 0x0e24 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1 0x0e28 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2 0x0e2c +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3 0x0e30 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1 0x0e34 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2 0x0e38 +#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3 0x0e3c +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP 0x0e40 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL 0x0e44 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS 0x0e48 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1 0x0e4c +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2 0x0e50 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1 0x0e54 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2 0x0e58 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3 0x0e5c +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1 0x0e60 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2 0x0e64 +#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3 0x0e68 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP 0x0e6c +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL 0x0e70 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS 0x0e74 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1 0x0e78 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2 0x0e7c +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1 0x0e80 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2 0x0e84 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3 0x0e88 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1 0x0e8c +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2 0x0e90 +#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3 0x0e94 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP 0x0e98 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL 0x0e9c +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS 0x0ea0 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1 0x0ea4 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2 0x0ea8 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1 0x0eac +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2 0x0eb0 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3 0x0eb4 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1 0x0eb8 +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2 0x0ebc +#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3 0x0ec0 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP 0x0ec4 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL 0x0ec8 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS 0x0ecc +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1 0x0ed0 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2 0x0ed4 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1 0x0ed8 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2 0x0edc +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3 0x0ee0 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1 0x0ee4 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2 0x0ee8 +#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3 0x0eec +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP 0x0ef0 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL 0x0ef4 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS 0x0ef8 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1 0x0efc +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2 0x0f00 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1 0x0f04 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2 0x0f08 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3 0x0f0c +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1 0x0f10 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2 0x0f14 +#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3 0x0f18 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP 0x0f1c +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL 0x0f20 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS 0x0f24 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1 0x0f28 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2 0x0f2c +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1 0x0f30 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2 0x0f34 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3 0x0f38 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1 0x0f3c +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2 0x0f40 +#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3 0x0f44 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP 0x0f48 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL 0x0f4c +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS 0x0f50 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1 0x0f54 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2 0x0f58 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1 0x0f5c +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2 0x0f60 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3 0x0f64 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1 0x0f68 +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2 0x0f6c +#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3 0x0f70 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP 0x0f74 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL 0x0f78 +#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS 0x0f7c +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1 0x0f80 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2 0x0f84 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1 0x0f88 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2 0x0f8c +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3 0x0f90 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1 0x0f94 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2 0x0f98 +#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3 0x0f9c + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x10100000 +#define regBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000 +#define regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_ID 0x0000 +#define regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_COMMAND 0x0001 +#define regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_STATUS 0x0001 +#define regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_REVISION_ID 0x0002 +#define regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0002 +#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SUB_CLASS 0x0002 +#define regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_BASE_CLASS 0x0002 +#define regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_CACHE_LINE 0x0003 +#define regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LATENCY 0x0003 +#define regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_HEADER 0x0003 +#define regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_BIST 0x0003 +#define regBIF_CFG_DEV0_RC0_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0004 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2 0x0005 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0006 +#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x0007 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x0007 +#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0008 +#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0009 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x000a +#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x000b +#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x000c +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_CAP_PTR 0x000d +#define regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0x000e +#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x000f +#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x000f +#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x000f +#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0010 +#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0014 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PMI_CAP 0x0014 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0015 +#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0016 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP 0x0016 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP 0x0017 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0018 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0018 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CAP 0x0019 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL 0x001a +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS 0x001a +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP 0x001b +#define regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL 0x001c +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS 0x001c +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_ROOT_CNTL 0x001d +#define regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_ROOT_CAP 0x001d +#define regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_ROOT_STATUS 0x001e +#define regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x001f +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0020 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0020 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CAP2 0x0021 +#define regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0022 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS2 0x0022 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP2 0x0023 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0024 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0024 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x0028 +#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x0028 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x0029 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x002b +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0x002b +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x0030 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SSID_CAP 0x0031 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0040 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0041 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0042 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x0043 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x0044 +#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x0045 +#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x0046 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x0047 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x0047 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0048 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0048 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0049 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0049 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x004a +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x004a +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x004b +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x004b +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x004c +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x004c +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x004d +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x004d +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x004e +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x004e +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0x006e +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0x006f +#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0x0070 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0x0071 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0072 +#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0073 +#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0074 +#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0x0076 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0x0076 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0x0076 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0x0076 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0x0077 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0x0077 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0x0077 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0x0077 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0x0078 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0x0078 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0x0078 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0x0078 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0x0079 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0x0079 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0x0079 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0x0079 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST 0x007e +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT 0x007f +#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT 0x0080 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT 0x0081 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1 0x0082 +#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2 0x0083 +#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1 0x0084 +#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2 0x0085 +#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT 0x0086 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT 0x0086 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT 0x0086 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT 0x0086 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT 0x0087 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT 0x0087 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT 0x0087 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT 0x0087 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT 0x0088 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT 0x0088 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT 0x0088 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT 0x0088 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT 0x0089 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT 0x0089 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT 0x0089 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT 0x0089 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST 0x008e +#define regBIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_AP_CAP 0x008f +#define regBIF_CFG_DEV0_RC0_AP_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_AP_CNTL 0x0090 +#define regBIF_CFG_DEV0_RC0_AP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_AP_DATA1 0x0091 +#define regBIF_CFG_DEV0_RC0_AP_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_AP_DATA2 0x0092 +#define regBIF_CFG_DEV0_RC0_AP_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_AP_SEL_EN_MASK 0x0093 +#define regBIF_CFG_DEV0_RC0_AP_SEL_EN_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0x0094 +#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0x0095 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0x0095 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0x0096 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0x0096 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0x0097 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0x0097 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0x0098 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0x0098 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0x0099 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0x0099 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0x009a +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0x009a +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0x009b +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0x009b +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0x009c +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0x009c +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0x009d +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0x009d +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0x009e +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0x009e +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0x009f +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0x009f +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0x00a0 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0x00a0 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0x00a1 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0x00a1 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0x00a2 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0x00a2 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0x00a3 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0x00a3 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0x00a4 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0x00a4 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0x00a5 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0x00a5 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST 0x0100 +#define regBIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0101 +#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0102 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0103 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x0104 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x0104 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0105 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0106 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x0107 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x0108 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x0109 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x010a +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0x010c +#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0x010d +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0x010e +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST 0x0180 +#define regBIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0181 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0182 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0183 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x0184 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0185 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0186 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x0187 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x0188 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x0189 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x018a +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x018b +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x018c +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x018d +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x018e +#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG4 0x018f +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x018f +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG5 0x0190 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x0190 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG6 0x0191 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0191 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG7 0x0192 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0192 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG8 0x0193 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG9 0x0194 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG10 0x0195 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG11 0x0196 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG12 0x0197 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG13 0x0198 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0199 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x019a +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x019b +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x01b7 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x01b8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x01b8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST 0x01c7 +#define regBIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RTR_DATA1 0x01c8 +#define regBIF_CFG_DEV0_RC0_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_RTR_DATA2 0x01c9 +#define regBIF_CFG_DEV0_RC0_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST 0x0380 +#define regBIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_CAP 0x0381 +#define regBIF_CFG_DEV0_RC0_IDE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_CNTL 0x0382 +#define regBIF_CFG_DEV0_RC0_IDE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL 0x0383 +#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS 0x0384 +#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP 0x0385 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL 0x0386 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS 0x0387 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1 0x0388 +#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2 0x0389 +#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1 0x038a +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2 0x038b +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3 0x038c +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1 0x038d +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2 0x038e +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3 0x038f +#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP 0x0390 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL 0x0391 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS 0x0392 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1 0x0393 +#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2 0x0394 +#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1 0x0395 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2 0x0396 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3 0x0397 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1 0x0398 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2 0x0399 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3 0x039a +#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP 0x039b +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL 0x039c +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS 0x039d +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1 0x039e +#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2 0x039f +#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1 0x03a0 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2 0x03a1 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3 0x03a2 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1 0x03a3 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2 0x03a4 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3 0x03a5 +#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP 0x03a6 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL 0x03a7 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS 0x03a8 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1 0x03a9 +#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2 0x03aa +#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1 0x03ab +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2 0x03ac +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3 0x03ad +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1 0x03ae +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2 0x03af +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3 0x03b0 +#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP 0x03b1 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL 0x03b2 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS 0x03b3 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1 0x03b4 +#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2 0x03b5 +#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1 0x03b6 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2 0x03b7 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3 0x03b8 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1 0x03b9 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2 0x03ba +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3 0x03bb +#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP 0x03bc +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL 0x03bd +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS 0x03be +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1 0x03bf +#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2 0x03c0 +#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1 0x03c1 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2 0x03c2 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3 0x03c3 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1 0x03c4 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2 0x03c5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3 0x03c6 +#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP 0x03c7 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL 0x03c8 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS 0x03c9 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1 0x03ca +#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2 0x03cb +#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1 0x03cc +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2 0x03cd +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3 0x03ce +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1 0x03cf +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2 0x03d0 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3 0x03d1 +#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP 0x03d2 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL 0x03d3 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS 0x03d4 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1 0x03d5 +#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2 0x03d6 +#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1 0x03d7 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2 0x03d8 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3 0x03d9 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1 0x03da +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2 0x03db +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3 0x03dc +#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP 0x03dd +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL 0x03de +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS 0x03df +#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1 0x03e0 +#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2 0x03e1 +#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1 0x03e2 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2 0x03e3 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3 0x03e4 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1 0x03e5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2 0x03e6 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3 0x03e7 +#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x10012 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x10013 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x10014 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x10014 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x10015 +#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10199 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x1019a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x1019b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x101b7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x101b8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x101b8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x101ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x101cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x101cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x101cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x101ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x101cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x101d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x101d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x101d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x101da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x101db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x101de +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x101df +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x101e0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x101e1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x101e2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x101e3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x101e4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x101e5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x101e6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x101e7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x101e8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x101e9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x101ea +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x101ed +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x101ee +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x101ee +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x101ef +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x101f0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x101f1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x101f2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x101f2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x101f3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x101f4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x101f5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x101f5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x101f6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x101f6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x101f7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x101f7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x101f8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x101f8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x101f9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x101fa +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x101fb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x101fc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x101fd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x101fe +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x101ff +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x10200 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x10201 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x10202 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10238 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0x10239 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0x1023a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0x1023b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0x1023c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0x1023d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0x1023e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0x1023f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0x10240 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0x10241 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0x10242 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0x10243 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0x10244 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST 0x10245 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP 0x10246 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL 0x10247 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS 0x10248 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX 0x10249 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX 0x1024a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x1026b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x1026c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x1026d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x1026e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x1026f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x10270 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x10271 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x10272 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x10273 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x10275 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x10277 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x10278 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0 0x10281 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x10282 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x10283 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x10284 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x10285 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0 0x10287 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1 0x10288 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2 0x10289 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3 0x1028a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4 0x1028b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5 0x1028c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6 0x1028d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7 0x1028e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8 0x1028f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0 0x10293 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1 0x10294 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2 0x10295 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3 0x10296 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4 0x10297 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5 0x10298 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6 0x10299 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7 0x1029a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8 0x1029b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0 0x1029f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1 0x102a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2 0x102a1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3 0x102a2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4 0x102a3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5 0x102a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6 0x102a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7 0x102a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8 0x102a7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0 0x102ab +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1 0x102ac +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2 0x102ad +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3 0x102ae +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4 0x102af +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5 0x102b0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6 0x102b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7 0x102b2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8 0x102b3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0 0x102b7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1 0x102b8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2 0x102b9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3 0x102ba +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4 0x102bb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5 0x102bc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6 0x102bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7 0x102be +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8 0x102bf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0 0x102c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1 0x102c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2 0x102c5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3 0x102c6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4 0x102c7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5 0x102c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6 0x102c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7 0x102ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8 0x102cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0 0x102cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1 0x102d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2 0x102d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3 0x102d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4 0x102d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5 0x102d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6 0x102d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7 0x102d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8 0x102d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0 0x102db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1 0x102dc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2 0x102dd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3 0x102de +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4 0x102df +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5 0x102e0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6 0x102e1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7 0x102e2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8 0x102e3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0 0x102e7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1 0x102e8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2 0x102e9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3 0x102ea +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4 0x102eb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5 0x102ec +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6 0x102ed +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7 0x102ee +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8 0x102ef +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0 0x102f3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1 0x102f4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2 0x102f5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3 0x102f6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4 0x102f7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5 0x102f8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6 0x102f9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7 0x102fa +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8 0x102fb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0 0x102ff +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1 0x10300 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2 0x10301 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3 0x10302 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4 0x10303 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5 0x10304 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6 0x10305 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7 0x10306 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8 0x10307 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0 0x1030b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1 0x1030c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2 0x1030d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3 0x1030e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4 0x1030f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5 0x10310 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6 0x10311 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7 0x10312 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8 0x10313 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0 0x10317 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1 0x10318 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2 0x10319 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3 0x1031a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4 0x1031b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5 0x1031c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6 0x1031d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7 0x1031e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8 0x1031f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0 0x10323 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1 0x10324 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2 0x10325 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3 0x10326 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4 0x10327 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5 0x10328 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6 0x10329 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7 0x1032a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8 0x1032b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0 0x1032f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1 0x10330 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2 0x10331 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3 0x10332 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4 0x10333 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5 0x10334 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6 0x10335 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7 0x10336 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8 0x10337 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0 0x1033b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1 0x1033c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2 0x1033d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3 0x1033e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4 0x1033f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5 0x10340 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6 0x10341 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7 0x10342 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8 0x10343 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0 0x10347 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1 0x10348 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2 0x10349 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3 0x1034a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4 0x1034b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5 0x1034c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6 0x1034d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7 0x1034e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8 0x1034f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0 0x10353 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1 0x10354 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2 0x10355 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3 0x10356 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4 0x10357 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5 0x10358 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6 0x10359 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7 0x1035a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8 0x1035b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0 0x1035f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1 0x10360 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2 0x10361 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3 0x10362 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4 0x10363 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5 0x10364 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6 0x10365 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7 0x10366 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8 0x10367 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0 0x1036b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1 0x1036c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2 0x1036d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3 0x1036e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4 0x1036f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5 0x10370 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6 0x10371 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7 0x10372 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8 0x10373 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE 0x10377 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE 0x10378 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE 0x10379 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE 0x1037a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS 0x1037b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS 0x1037c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS 0x1037d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS 0x1037e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x10044 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x10045 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x10046 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x10047 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x10047 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x10048 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x10048 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x10049 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x10049 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x1004a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x1004a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x1004b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x1004b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x1004c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x1004c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x1004d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x1004d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x1004e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x1004e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x1006e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x1006f +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x10070 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x10071 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10072 +#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10073 +#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x10074 +#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x10076 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x10076 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x10076 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x10076 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x10077 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x10077 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x10077 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x10077 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x10078 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x10078 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x10078 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x10078 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x10079 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x10079 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x10079 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x10079 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST 0x1007e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT 0x1007f +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT 0x10080 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT 0x10081 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1 0x10082 +#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2 0x10083 +#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1 0x10084 +#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2 0x10085 +#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST 0x1008e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_AP_CAP 0x1008f +#define regBIF_CFG_DEV0_EPF0_0_AP_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_AP_CNTL 0x10090 +#define regBIF_CFG_DEV0_EPF0_0_AP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_AP_DATA1 0x10091 +#define regBIF_CFG_DEV0_EPF0_0_AP_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_AP_DATA2 0x10092 +#define regBIF_CFG_DEV0_EPF0_0_AP_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK 0x10093 +#define regBIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x10094 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x10095 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x10095 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x10096 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x10096 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x10097 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x10097 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x1009a +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x1009a +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x1009b +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x1009b +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x1009c +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x1009c +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x1009d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x1009d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x1009e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x1009e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x1009f +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x1009f +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x100a0 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x100a0 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x100a1 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x100a1 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x100a2 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x100a2 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x100a3 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x100a3 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x100a4 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x100a4 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x100a5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x100a5 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x10101 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x10102 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x10103 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x10104 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x10104 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x10105 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x10106 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x10107 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x10108 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x10109 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x1010a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST 0x10380 +#define regBIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_CAP 0x10381 +#define regBIF_CFG_DEV0_EPF0_0_IDE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_CNTL 0x10382 +#define regBIF_CFG_DEV0_EPF0_0_IDE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL 0x10383 +#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS 0x10384 +#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP 0x10385 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL 0x10386 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS 0x10387 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1 0x10388 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2 0x10389 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1 0x1038a +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2 0x1038b +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3 0x1038c +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1 0x1038d +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2 0x1038e +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3 0x1038f +#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP 0x10390 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL 0x10391 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS 0x10392 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1 0x10393 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2 0x10394 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1 0x10395 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2 0x10396 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3 0x10397 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1 0x10398 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2 0x10399 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3 0x1039a +#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP 0x1039b +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL 0x1039c +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS 0x1039d +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1 0x1039e +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2 0x1039f +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1 0x103a0 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2 0x103a1 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3 0x103a2 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1 0x103a3 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2 0x103a4 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3 0x103a5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP 0x103a6 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL 0x103a7 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS 0x103a8 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1 0x103a9 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2 0x103aa +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1 0x103ab +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2 0x103ac +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3 0x103ad +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1 0x103ae +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2 0x103af +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3 0x103b0 +#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP 0x103b1 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL 0x103b2 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS 0x103b3 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1 0x103b4 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2 0x103b5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1 0x103b6 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2 0x103b7 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3 0x103b8 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1 0x103b9 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2 0x103ba +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3 0x103bb +#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP 0x103bc +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL 0x103bd +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS 0x103be +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1 0x103bf +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2 0x103c0 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1 0x103c1 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2 0x103c2 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3 0x103c3 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1 0x103c4 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2 0x103c5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3 0x103c6 +#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP 0x103c7 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL 0x103c8 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS 0x103c9 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1 0x103ca +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2 0x103cb +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1 0x103cc +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2 0x103cd +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3 0x103ce +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1 0x103cf +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2 0x103d0 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3 0x103d1 +#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP 0x103d2 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL 0x103d3 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS 0x103d4 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1 0x103d5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2 0x103d6 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1 0x103d7 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2 0x103d8 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3 0x103d9 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1 0x103da +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2 0x103db +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3 0x103dc +#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP 0x103dd +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL 0x103de +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS 0x103df +#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1 0x103e0 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2 0x103e1 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1 0x103e2 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2 0x103e3 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3 0x103e4 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1 0x103e5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2 0x103e6 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3 0x103e7 +#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST 0x100b6 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3 0x100b7 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3 0x100b8 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3 0x100b9 +#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST 0x10180 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10181 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x10182 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x10183 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x10184 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x10185 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x10186 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x10187 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x10188 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x10189 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x1018a +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x1018b +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x1018f +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x10190 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x10191 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x10192 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8 0x10193 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9 0x10194 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10 0x10195 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11 0x10196 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12 0x10197 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13 0x10198 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST 0x101c7 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1 0x101c8 +#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2 0x101c9 +#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x101dc +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x101dd +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST 0x101eb +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL 0x101ec +#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX 0x8000 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_DATA 0x8001 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_DATA_BASE_IDX 5 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI 0x8006 +#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC:1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO 0x0410 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI 0x0411 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA 0x0412 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL 0x0413 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO 0x0414 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI 0x0415 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA 0x0416 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL 0x0417 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO 0x0418 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI 0x0419 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA 0x041a +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL 0x041b +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO 0x041c +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI 0x041d +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA 0x041e +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL 0x041f +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO 0x0420 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI 0x0421 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA 0x0422 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL 0x0423 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL_BASE_IDX 3 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x10141000 +#define regBIF_CFG_DEV0_EPF1_VENDOR_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_COMMAND 0x10401 +#define regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_STATUS 0x10401 +#define regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_REVISION_ID 0x10402 +#define regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x10402 +#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_SUB_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_CACHE_LINE 0x10403 +#define regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LATENCY 0x10403 +#define regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_HEADER 0x10403 +#define regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BIST 0x10403 +#define regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x10404 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x10405 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x10406 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x10407 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x10408 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x10409 +#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x1040a +#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x1040b +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x1040c +#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_CAP_PTR 0x1040d +#define regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x1040f +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x1040f +#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MIN_GRANT 0x1040f +#define regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x1040f +#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x10412 +#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x10413 +#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x10414 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP 0x10414 +#define regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x10415 +#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX 5 +#define regSBRN 0x10418 +#define regSBRN_BASE_IDX 5 +#define regFLADJ 0x10418 +#define regFLADJ_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x10419 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP 0x10419 +#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x1041a +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x1041b +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x1041b +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CAP 0x1041c +#define regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL 0x1041d +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS 0x1041d +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x10422 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x10423 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x10423 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CAP2 0x10424 +#define regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x10425 +#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x10425 +#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x10428 +#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x10428 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x10429 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x1042a +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MASK 0x1042b +#define regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x1042c +#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING 0x1042c +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x1042d +#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x10430 +#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x10430 +#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x10431 +#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_MSIX_PBA 0x10432 +#define regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x10441 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x10442 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x10443 +#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST 0x104b6 +#define regBIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP3 0x104b7 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL3 0x104b8 +#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS3 0x104b9 +#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST 0x10500 +#define regBIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST 0x10580 +#define regBIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10581 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x10582 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x10583 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x10584 +#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x10585 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x10586 +#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x10587 +#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x10588 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x10589 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x1058a +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x1058b +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4 0x1058f +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x1058f +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5 0x10590 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x10590 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6 0x10591 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x10591 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7 0x10592 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x10592 +#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8 0x10593 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9 0x10594 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10 0x10595 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11 0x10596 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12 0x10597 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13 0x10598 +#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x105b7 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x105b8 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x105b8 +#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST 0x105c7 +#define regBIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_RTR_DATA1 0x105c8 +#define regBIF_CFG_DEV0_EPF1_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_RTR_DATA2 0x105c9 +#define regBIF_CFG_DEV0_EPF1_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x105ca +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x105cb +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x105cc +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x105cd +#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x105ce +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x105cf +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x105d0 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x105d1 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x105d1 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x105d2 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x105d2 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x105d2 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x105d2 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x105d3 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x105d3 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x105d3 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x105d3 +#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x105dc +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x105dd +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x105dd +#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x105de +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x105df +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x105e0 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x105e1 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x105e2 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x105e3 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x105e4 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x105e5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x105e6 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x105e7 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x105e8 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x105e9 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x105ea +#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x105f1 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x105f2 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x105f2 +#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x105f3 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x105f4 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x105f5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x105f5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x105f6 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x105f6 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x105f7 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x105f7 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x105f8 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x105f8 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x105f9 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x105fa +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x105fb +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x105fc +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x105fd +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x105fe +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x105ff +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x10600 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x10601 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x10602 +#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10638 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x10639 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x1063a +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x1063b +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x1063c +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x1063d +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x1063e +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x1063f +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x10640 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x10641 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x10642 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x10643 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x10644 +#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_vf0_bifcfgdecp +// base address: 0x10141000 +#define regBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_COMMAND 0x10401 +#define regBIF_CFG_DEV0_EPF1_VF0_COMMAND_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_STATUS 0x10401 +#define regBIF_CFG_DEV0_EPF1_VF0_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_REVISION_ID 0x10402 +#define regBIF_CFG_DEV0_EPF1_VF0_REVISION_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE 0x10402 +#define regBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE 0x10403 +#define regBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LATENCY 0x10403 +#define regBIF_CFG_DEV0_EPF1_VF0_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_HEADER 0x10403 +#define regBIF_CFG_DEV0_EPF1_VF0_HEADER_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BIST 0x10403 +#define regBIF_CFG_DEV0_EPF1_VF0_BIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1 0x10404 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2 0x10405 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3 0x10406 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4 0x10407 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5 0x10408 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6 0x10409 +#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR 0x1040a +#define regBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID 0x1040b +#define regBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR 0x1040c +#define regBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_CAP_PTR 0x1040d +#define regBIF_CFG_DEV0_EPF1_VF0_CAP_PTR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE 0x1040f +#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN 0x1040f +#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT 0x1040f +#define regBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY 0x1040f +#define regBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST 0x10419 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP 0x10419 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP 0x1041a +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL 0x1041b +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS 0x1041b +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP 0x1041c +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL 0x1041d +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS 0x1041d +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2 0x10422 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2 0x10423 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2 0x10423 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2 0x10424 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2 0x10425 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2 0x10425 +#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST 0x10428 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL 0x10428 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO 0x10429 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI 0x1042a +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK 0x1042b +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64 0x1042c +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING 0x1042c +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64 0x1042d +#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST 0x10430 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL 0x10430 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE 0x10431 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA 0x10432 +#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x10441 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1 0x10442 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2 0x10443 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x104b6 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3 0x104b7 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3 0x104b8 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3 0x104b9 +#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST 0x10500 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST 0x10580 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10581 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS 0x10582 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK 0x10583 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY 0x10584 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS 0x10585 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK 0x10586 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL 0x10587 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0 0x10588 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1 0x10589 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2 0x1058a +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3 0x1058b +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4 0x1058f +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0 0x1058f +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5 0x10590 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1 0x10590 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6 0x10591 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2 0x10591 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7 0x10592 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3 0x10592 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8 0x10593 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9 0x10594 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10 0x10595 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11 0x10596 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12 0x10597 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13 0x10598 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST 0x105c7 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1 0x105c8 +#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2 0x105c9 +#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST 0x105dc +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP 0x105dd +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP_BASE_IDX 5 +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL 0x105dd +#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441 +#define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3 0xc464 +#define regRCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +// base address: 0x10134000 +#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL 0xd040 +#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE 0xd041 +#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 0xd042 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 0xd043 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 0xd044 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 0xd045 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 0xd046 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 0xd047 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL 0xd048 +#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL 0xd049 +#define regRCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL_BASE_IDX 5 +#define regRCC_PFC_AMDGFX_RCC_NFC 0xd04a +#define regRCC_PFC_AMDGFX_RCC_NFC_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_shadow_reg_shadowdec +// base address: 0x10130000 +#define regSHADOW_COMMAND 0xc001 +#define regSHADOW_COMMAND_BASE_IDX 5 +#define regSHADOW_BASE_ADDR_1 0xc004 +#define regSHADOW_BASE_ADDR_1_BASE_IDX 5 +#define regSHADOW_BASE_ADDR_2 0xc005 +#define regSHADOW_BASE_ADDR_2_BASE_IDX 5 +#define regSHADOW_SUB_BUS_NUMBER_LATENCY 0xc006 +#define regSHADOW_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 +#define regSHADOW_IO_BASE_LIMIT 0xc007 +#define regSHADOW_IO_BASE_LIMIT_BASE_IDX 5 +#define regSHADOW_MEM_BASE_LIMIT 0xc008 +#define regSHADOW_MEM_BASE_LIMIT_BASE_IDX 5 +#define regSHADOW_PREF_BASE_LIMIT 0xc009 +#define regSHADOW_PREF_BASE_LIMIT_BASE_IDX 5 +#define regSHADOW_PREF_BASE_UPPER 0xc00a +#define regSHADOW_PREF_BASE_UPPER_BASE_IDX 5 +#define regSHADOW_PREF_LIMIT_UPPER 0xc00b +#define regSHADOW_PREF_LIMIT_UPPER_BASE_IDX 5 +#define regSHADOW_IO_BASE_LIMIT_HI 0xc00c +#define regSHADOW_IO_BASE_LIMIT_HI_BASE_IDX 5 +#define regSHADOW_IRQ_BRIDGE_CNTL 0xc00f +#define regSHADOW_IRQ_BRIDGE_CNTL_BASE_IDX 5 +#define regSUC_INDEX 0xc038 +#define regSUC_INDEX_BASE_IDX 5 +#define regSUC_DATA 0xc039 +#define regSUC_DATA_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_swus_SUMDEC +// base address: 0x1013b000 +#define regSUM_INDEX 0xec38 +#define regSUM_INDEX_BASE_IDX 5 +#define regSUM_DATA 0xec39 +#define regSUM_DATA_BASE_IDX 5 +#define regSUM_INDEX_HI 0xec3b +#define regSUM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_strap_rcc_strap_internal +// base address: 0x10100000 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP15 0xc40f +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP15_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP16 0xc410 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP16_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP17 0xc411 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP17_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP18 0xc412 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP18_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP0 0xc480 +#define regRCC_DEV1_PORT_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP1 0xc481 +#define regRCC_DEV1_PORT_STRAP1_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP2 0xc482 +#define regRCC_DEV1_PORT_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP3 0xc483 +#define regRCC_DEV1_PORT_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP4 0xc484 +#define regRCC_DEV1_PORT_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP5 0xc485 +#define regRCC_DEV1_PORT_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP6 0xc486 +#define regRCC_DEV1_PORT_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP7 0xc487 +#define regRCC_DEV1_PORT_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP8 0xc488 +#define regRCC_DEV1_PORT_STRAP8_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP9 0xc489 +#define regRCC_DEV1_PORT_STRAP9_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP10 0xc48a +#define regRCC_DEV1_PORT_STRAP10_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP11 0xc48b +#define regRCC_DEV1_PORT_STRAP11_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP12 0xc48c +#define regRCC_DEV1_PORT_STRAP12_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP13 0xc48d +#define regRCC_DEV1_PORT_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP14 0xc48e +#define regRCC_DEV1_PORT_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP15 0xc48f +#define regRCC_DEV1_PORT_STRAP15_BASE_IDX 5 +#define regRCC_DEV1_PORT_STRAP16 0xc490 +#define regRCC_DEV1_PORT_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP0 0xc500 +#define regRCC_DEV2_PORT_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP1 0xc501 +#define regRCC_DEV2_PORT_STRAP1_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP2 0xc502 +#define regRCC_DEV2_PORT_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP3 0xc503 +#define regRCC_DEV2_PORT_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP4 0xc504 +#define regRCC_DEV2_PORT_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP5 0xc505 +#define regRCC_DEV2_PORT_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP6 0xc506 +#define regRCC_DEV2_PORT_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP7 0xc507 +#define regRCC_DEV2_PORT_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP8 0xc508 +#define regRCC_DEV2_PORT_STRAP8_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP9 0xc509 +#define regRCC_DEV2_PORT_STRAP9_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP10 0xc50a +#define regRCC_DEV2_PORT_STRAP10_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP11 0xc50b +#define regRCC_DEV2_PORT_STRAP11_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP12 0xc50c +#define regRCC_DEV2_PORT_STRAP12_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP13 0xc50d +#define regRCC_DEV2_PORT_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP14 0xc50e +#define regRCC_DEV2_PORT_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP15 0xc50f +#define regRCC_DEV2_PORT_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_PORT_STRAP16 0xc510 +#define regRCC_DEV2_PORT_STRAP16_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600 +#define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601 +#define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602 +#define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603 +#define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604 +#define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605 +#define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606 +#define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP7 0xc607 +#define regRCC_STRAP1_RCC_BIF_STRAP7_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP8 0xc608 +#define regRCC_STRAP1_RCC_BIF_STRAP8_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP9 0xc609 +#define regRCC_STRAP1_RCC_BIF_STRAP9_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP10 0xc60a +#define regRCC_STRAP1_RCC_BIF_STRAP10_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP11 0xc60b +#define regRCC_STRAP1_RCC_BIF_STRAP11_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP12 0xc60c +#define regRCC_STRAP1_RCC_BIF_STRAP12_BASE_IDX 5 +#define regRCC_STRAP1_RCC_BIF_STRAP13 0xc60d +#define regRCC_STRAP1_RCC_BIF_STRAP13_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP19 0xd013 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP19_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP22 0xd016 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP22_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP23 0xd017 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP23_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP24 0xd018 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP24_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP1 0xd081 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP1_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP8 0xd088 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP8_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP9 0xd089 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP9_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10 0xd08a +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11 0xd08b +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12 0xd08c +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13 0xd08d +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14 0xd08e +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP15 0xd08f +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP15_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP16 0xd090 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP16_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP17 0xd091 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP17_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP18 0xd092 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP18_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP19 0xd093 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP19_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 0xd097 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 0xd098 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP0 0xd100 +#define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP2 0xd102 +#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP3 0xd103 +#define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP4 0xd104 +#define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP5 0xd105 +#define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP6 0xd106 +#define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP7 0xd107 +#define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP9 0xd109 +#define regRCC_DEV0_EPF2_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP10 0xd10a +#define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP11 0xd10b +#define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP12 0xd10c +#define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP13 0xd10d +#define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP14 0xd10e +#define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP15 0xd10f +#define regRCC_DEV0_EPF2_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP16 0xd110 +#define regRCC_DEV0_EPF2_STRAP16_BASE_IDX 5 +#define regRCC_DEV0_EPF2_STRAP20 0xd114 +#define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP0 0xd180 +#define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP2 0xd182 +#define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP3 0xd183 +#define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP4 0xd184 +#define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP5 0xd185 +#define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP6 0xd186 +#define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP7 0xd187 +#define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP9 0xd189 +#define regRCC_DEV0_EPF3_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP10 0xd18a +#define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP11 0xd18b +#define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP12 0xd18c +#define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP13 0xd18d +#define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP14 0xd18e +#define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP15 0xd18f +#define regRCC_DEV0_EPF3_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP16 0xd190 +#define regRCC_DEV0_EPF3_STRAP16_BASE_IDX 5 +#define regRCC_DEV0_EPF3_STRAP20 0xd194 +#define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP0 0xd200 +#define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP2 0xd202 +#define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP3 0xd203 +#define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP4 0xd204 +#define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP5 0xd205 +#define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP6 0xd206 +#define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP7 0xd207 +#define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP9 0xd209 +#define regRCC_DEV0_EPF4_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP13 0xd20d +#define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP14 0xd20e +#define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP15 0xd20f +#define regRCC_DEV0_EPF4_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF4_STRAP16 0xd210 +#define regRCC_DEV0_EPF4_STRAP16_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP0 0xd280 +#define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP2 0xd282 +#define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP3 0xd283 +#define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP4 0xd284 +#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP5 0xd285 +#define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP6 0xd286 +#define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP7 0xd287 +#define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP9 0xd289 +#define regRCC_DEV0_EPF5_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP13 0xd28d +#define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP14 0xd28e +#define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP15 0xd28f +#define regRCC_DEV0_EPF5_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF5_STRAP16 0xd290 +#define regRCC_DEV0_EPF5_STRAP16_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP0 0xd300 +#define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP2 0xd302 +#define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP3 0xd303 +#define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP4 0xd304 +#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP5 0xd305 +#define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP6 0xd306 +#define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP7 0xd307 +#define regRCC_DEV0_EPF6_STRAP7_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP9 0xd309 +#define regRCC_DEV0_EPF6_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP13 0xd30d +#define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP14 0xd30e +#define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP15 0xd30f +#define regRCC_DEV0_EPF6_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF6_STRAP16 0xd310 +#define regRCC_DEV0_EPF6_STRAP16_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP0 0xd380 +#define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP2 0xd382 +#define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP3 0xd383 +#define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP4 0xd384 +#define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP5 0xd385 +#define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP6 0xd386 +#define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP9 0xd389 +#define regRCC_DEV0_EPF7_STRAP9_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP13 0xd38d +#define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP14 0xd38e +#define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP15 0xd38f +#define regRCC_DEV0_EPF7_STRAP15_BASE_IDX 5 +#define regRCC_DEV0_EPF7_STRAP16 0xd390 +#define regRCC_DEV0_EPF7_STRAP16_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP0 0xd400 +#define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP2 0xd402 +#define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP3 0xd403 +#define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP4 0xd404 +#define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP5 0xd405 +#define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP6 0xd406 +#define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP9 0xd409 +#define regRCC_DEV1_EPF0_STRAP9_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP13 0xd40d +#define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP14 0xd40e +#define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP15 0xd40f +#define regRCC_DEV1_EPF0_STRAP15_BASE_IDX 5 +#define regRCC_DEV1_EPF0_STRAP16 0xd410 +#define regRCC_DEV1_EPF0_STRAP16_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP0 0xd480 +#define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP1 0xd481 +#define regRCC_DEV1_EPF1_STRAP1_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP2 0xd482 +#define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP3 0xd483 +#define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP4 0xd484 +#define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP5 0xd485 +#define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP6 0xd486 +#define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP7 0xd487 +#define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP8 0xd488 +#define regRCC_DEV1_EPF1_STRAP8_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP9 0xd489 +#define regRCC_DEV1_EPF1_STRAP9_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP13 0xd48d +#define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP14 0xd48e +#define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP15 0xd48f +#define regRCC_DEV1_EPF1_STRAP15_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP16 0xd490 +#define regRCC_DEV1_EPF1_STRAP16_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP17 0xd491 +#define regRCC_DEV1_EPF1_STRAP17_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP18 0xd492 +#define regRCC_DEV1_EPF1_STRAP18_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP19 0xd493 +#define regRCC_DEV1_EPF1_STRAP19_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP20 0xd494 +#define regRCC_DEV1_EPF1_STRAP20_BASE_IDX 5 +#define regRCC_DEV1_EPF1_STRAP21 0xd495 +#define regRCC_DEV1_EPF1_STRAP21_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP0 0xd500 +#define regRCC_DEV1_EPF2_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP1 0xd501 +#define regRCC_DEV1_EPF2_STRAP1_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP2 0xd502 +#define regRCC_DEV1_EPF2_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP3 0xd503 +#define regRCC_DEV1_EPF2_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP4 0xd504 +#define regRCC_DEV1_EPF2_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP5 0xd505 +#define regRCC_DEV1_EPF2_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP6 0xd506 +#define regRCC_DEV1_EPF2_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP7 0xd507 +#define regRCC_DEV1_EPF2_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP8 0xd508 +#define regRCC_DEV1_EPF2_STRAP8_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP9 0xd509 +#define regRCC_DEV1_EPF2_STRAP9_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP13 0xd50d +#define regRCC_DEV1_EPF2_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP14 0xd50e +#define regRCC_DEV1_EPF2_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP15 0xd50f +#define regRCC_DEV1_EPF2_STRAP15_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP16 0xd510 +#define regRCC_DEV1_EPF2_STRAP16_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP17 0xd511 +#define regRCC_DEV1_EPF2_STRAP17_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP18 0xd512 +#define regRCC_DEV1_EPF2_STRAP18_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP19 0xd513 +#define regRCC_DEV1_EPF2_STRAP19_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP20 0xd514 +#define regRCC_DEV1_EPF2_STRAP20_BASE_IDX 5 +#define regRCC_DEV1_EPF2_STRAP21 0xd515 +#define regRCC_DEV1_EPF2_STRAP21_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP0 0xd580 +#define regRCC_DEV1_EPF3_STRAP0_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP2 0xd582 +#define regRCC_DEV1_EPF3_STRAP2_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP3 0xd583 +#define regRCC_DEV1_EPF3_STRAP3_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP4 0xd584 +#define regRCC_DEV1_EPF3_STRAP4_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP5 0xd585 +#define regRCC_DEV1_EPF3_STRAP5_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP6 0xd586 +#define regRCC_DEV1_EPF3_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP7 0xd587 +#define regRCC_DEV1_EPF3_STRAP7_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP13 0xd58d +#define regRCC_DEV1_EPF3_STRAP13_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP14 0xd58e +#define regRCC_DEV1_EPF3_STRAP14_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP15 0xd58f +#define regRCC_DEV1_EPF3_STRAP15_BASE_IDX 5 +#define regRCC_DEV1_EPF3_STRAP16 0xd590 +#define regRCC_DEV1_EPF3_STRAP16_BASE_IDX 5 +#define regRCC_DEV1_EPF4_STRAP6 0xd606 +#define regRCC_DEV1_EPF4_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF5_STRAP6 0xd686 +#define regRCC_DEV1_EPF5_STRAP6_BASE_IDX 5 +#define regRCC_DEV1_EPF6_STRAP6 0xd706 +#define regRCC_DEV1_EPF6_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP0 0xd800 +#define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP2 0xd802 +#define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP3 0xd803 +#define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP4 0xd804 +#define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP5 0xd805 +#define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP6 0xd806 +#define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP7 0xd807 +#define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP13 0xd80d +#define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP14 0xd80e +#define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP15 0xd80f +#define regRCC_DEV2_EPF0_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP16 0xd810 +#define regRCC_DEV2_EPF0_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP18 0xd812 +#define regRCC_DEV2_EPF0_STRAP18_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP25 0xd819 +#define regRCC_DEV2_EPF0_STRAP25_BASE_IDX 5 +#define regRCC_DEV2_EPF0_STRAP26 0xd81a +#define regRCC_DEV2_EPF0_STRAP26_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP0 0xd880 +#define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP2 0xd882 +#define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP3 0xd883 +#define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP4 0xd884 +#define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP5 0xd885 +#define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP6 0xd886 +#define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP7 0xd887 +#define regRCC_DEV2_EPF1_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP13 0xd88d +#define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP14 0xd88e +#define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP15 0xd88f +#define regRCC_DEV2_EPF1_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF1_STRAP16 0xd890 +#define regRCC_DEV2_EPF1_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP0 0xd900 +#define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP2 0xd902 +#define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP3 0xd903 +#define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP4 0xd904 +#define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP5 0xd905 +#define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP6 0xd906 +#define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP7 0xd907 +#define regRCC_DEV2_EPF2_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP13 0xd90d +#define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP14 0xd90e +#define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP15 0xd90f +#define regRCC_DEV2_EPF2_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF2_STRAP16 0xd910 +#define regRCC_DEV2_EPF2_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP0 0xd980 +#define regRCC_DEV2_EPF3_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP2 0xd982 +#define regRCC_DEV2_EPF3_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP3 0xd983 +#define regRCC_DEV2_EPF3_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP4 0xd984 +#define regRCC_DEV2_EPF3_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP5 0xd985 +#define regRCC_DEV2_EPF3_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP6 0xd986 +#define regRCC_DEV2_EPF3_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP7 0xd987 +#define regRCC_DEV2_EPF3_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP13 0xd98d +#define regRCC_DEV2_EPF3_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP14 0xd98e +#define regRCC_DEV2_EPF3_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP15 0xd98f +#define regRCC_DEV2_EPF3_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF3_STRAP16 0xd990 +#define regRCC_DEV2_EPF3_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP0 0xda00 +#define regRCC_DEV2_EPF4_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP2 0xda02 +#define regRCC_DEV2_EPF4_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP3 0xda03 +#define regRCC_DEV2_EPF4_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP4 0xda04 +#define regRCC_DEV2_EPF4_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP5 0xda05 +#define regRCC_DEV2_EPF4_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP6 0xda06 +#define regRCC_DEV2_EPF4_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP7 0xda07 +#define regRCC_DEV2_EPF4_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP13 0xda0d +#define regRCC_DEV2_EPF4_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP14 0xda0e +#define regRCC_DEV2_EPF4_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP15 0xda0f +#define regRCC_DEV2_EPF4_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF4_STRAP16 0xda10 +#define regRCC_DEV2_EPF4_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP0 0xda80 +#define regRCC_DEV2_EPF5_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP2 0xda82 +#define regRCC_DEV2_EPF5_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP3 0xda83 +#define regRCC_DEV2_EPF5_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP4 0xda84 +#define regRCC_DEV2_EPF5_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP5 0xda85 +#define regRCC_DEV2_EPF5_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP6 0xda86 +#define regRCC_DEV2_EPF5_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP7 0xda87 +#define regRCC_DEV2_EPF5_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP13 0xda8d +#define regRCC_DEV2_EPF5_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP14 0xda8e +#define regRCC_DEV2_EPF5_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP15 0xda8f +#define regRCC_DEV2_EPF5_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF5_STRAP16 0xda90 +#define regRCC_DEV2_EPF5_STRAP16_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP0 0xdb00 +#define regRCC_DEV2_EPF6_STRAP0_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP2 0xdb02 +#define regRCC_DEV2_EPF6_STRAP2_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP3 0xdb03 +#define regRCC_DEV2_EPF6_STRAP3_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP4 0xdb04 +#define regRCC_DEV2_EPF6_STRAP4_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP5 0xdb05 +#define regRCC_DEV2_EPF6_STRAP5_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP6 0xdb06 +#define regRCC_DEV2_EPF6_STRAP6_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP7 0xdb07 +#define regRCC_DEV2_EPF6_STRAP7_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP13 0xdb0d +#define regRCC_DEV2_EPF6_STRAP13_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP14 0xdb0e +#define regRCC_DEV2_EPF6_STRAP14_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP15 0xdb0f +#define regRCC_DEV2_EPF6_STRAP15_BASE_IDX 5 +#define regRCC_DEV2_EPF6_STRAP16 0xdb10 +#define regRCC_DEV2_EPF6_STRAP16_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_rst_bif_rst_regblk +// base address: 0x10100000 +#define regHARD_RST_CTRL 0xe000 +#define regHARD_RST_CTRL_BASE_IDX 5 +#define regSELF_SOFT_RST 0xe002 +#define regSELF_SOFT_RST_BASE_IDX 5 +#define regBIF_GFX_DRV_VPU_RST 0xe003 +#define regBIF_GFX_DRV_VPU_RST_BASE_IDX 5 +#define regBIF_RST_MISC_CTRL 0xe004 +#define regBIF_RST_MISC_CTRL_BASE_IDX 5 +#define regBIF_RST_MISC_CTRL2 0xe005 +#define regBIF_RST_MISC_CTRL2_BASE_IDX 5 +#define regBIF_RST_MISC_CTRL3 0xe006 +#define regBIF_RST_MISC_CTRL3_BASE_IDX 5 +#define regDEV0_PF0_FLR_RST_CTRL 0xe008 +#define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 5 +#define regDEV0_PF1_FLR_RST_CTRL 0xe009 +#define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 5 +#define regBIF_INST_RESET_INTR_STS 0xe010 +#define regBIF_INST_RESET_INTR_STS_BASE_IDX 5 +#define regBIF_PF_FLR_INTR_STS 0xe011 +#define regBIF_PF_FLR_INTR_STS_BASE_IDX 5 +#define regBIF_D3HOTD0_INTR_STS 0xe012 +#define regBIF_D3HOTD0_INTR_STS_BASE_IDX 5 +#define regBIF_POWER_INTR_STS 0xe014 +#define regBIF_POWER_INTR_STS_BASE_IDX 5 +#define regBIF_PF_DSTATE_INTR_STS 0xe015 +#define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 5 +#define regSELF_SOFT_RST_2 0xe016 +#define regSELF_SOFT_RST_2_BASE_IDX 5 +#define regSION_SDP_PORT_RST 0xe017 +#define regSION_SDP_PORT_RST_BASE_IDX 5 +#define regBIF_INST_RESET_INTR_MASK 0xe020 +#define regBIF_INST_RESET_INTR_MASK_BASE_IDX 5 +#define regBIF_PF_FLR_INTR_MASK 0xe021 +#define regBIF_PF_FLR_INTR_MASK_BASE_IDX 5 +#define regBIF_D3HOTD0_INTR_MASK 0xe022 +#define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 5 +#define regBIF_POWER_INTR_MASK 0xe024 +#define regBIF_POWER_INTR_MASK_BASE_IDX 5 +#define regBIF_PF_DSTATE_INTR_MASK 0xe025 +#define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF_FLR_INTR_MASK 0xe028 +#define regBIF_DEV0_PF0_VF_FLR_INTR_MASK_BASE_IDX 5 +#define regBIF_DEV0_PF1_VF_FLR_INTR_MASK 0xe029 +#define regBIF_DEV0_PF1_VF_FLR_INTR_MASK_BASE_IDX 5 +#define regBIF_PF_FLR_RST 0xe040 +#define regBIF_PF_FLR_RST_BASE_IDX 5 +#define regBIF_PF_FLR_PROTECT 0xe042 +#define regBIF_PF_FLR_PROTECT_BASE_IDX 5 +#define regBIF_PF_FLR_PROTECT3 0xe044 +#define regBIF_PF_FLR_PROTECT3_BASE_IDX 5 +#define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 +#define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 5 +#define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 +#define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 5 +#define regGFX_RST_CNTL_IND0 0xe05d +#define regGFX_RST_CNTL_IND0_BASE_IDX 5 +#define regGFX_RST_CNTL_SOFT_PF 0xe05e +#define regGFX_RST_CNTL_SOFT_PF_BASE_IDX 5 +#define regGFX_RST_CNTL_IND1 0xe05f +#define regGFX_RST_CNTL_IND1_BASE_IDX 5 +#define regGFX_RST_CNTL_IND2 0xe060 +#define regGFX_RST_CNTL_IND2_BASE_IDX 5 +#define regGFX_RST_CNTL_IND3 0xe061 +#define regGFX_RST_CNTL_IND3_BASE_IDX 5 +#define regGFX_RST_CNTL_IND4 0xe062 +#define regGFX_RST_CNTL_IND4_BASE_IDX 5 +#define regGFX_RST_CNTL_IND5 0xe063 +#define regGFX_RST_CNTL_IND5_BASE_IDX 5 +#define regGFX_RST_CNTL_IND6 0xe064 +#define regGFX_RST_CNTL_IND6_BASE_IDX 5 +#define regGFX_RST_CNTL_IND7 0xe065 +#define regGFX_RST_CNTL_IND7_BASE_IDX 5 +#define regGFX_RST_CNTL_IND8 0xe066 +#define regGFX_RST_CNTL_IND8_BASE_IDX 5 +#define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe07e +#define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5 +#define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe07f +#define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF_FLR_PROTECT 0xe086 +#define regBIF_DEV0_PF0_VF_FLR_PROTECT_BASE_IDX 5 +#define regBIF_DEV0_PF1_VF_FLR_PROTECT 0xe087 +#define regBIF_DEV0_PF1_VF_FLR_PROTECT_BASE_IDX 5 +#define regBIF_SRIOVEN_SET_INTR_STS 0xe088 +#define regBIF_SRIOVEN_SET_INTR_STS_BASE_IDX 5 +#define regBIF_SRIOVEN_CLR_INTR_STS 0xe089 +#define regBIF_SRIOVEN_CLR_INTR_STS_BASE_IDX 5 +#define regBIF_SRIOVEN_SET_INTR_MASK 0xe08a +#define regBIF_SRIOVEN_SET_INTR_MASK_BASE_IDX 5 +#define regBIF_SRIOVEN_CLR_INTR_MASK 0xe08b +#define regBIF_SRIOVEN_CLR_INTR_MASK_BASE_IDX 5 +#define regBIF_PORT0_DSTATE_VALUE 0xe230 +#define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 5 +#define regBIF_DEV0_PF0_RST_VF_FLR_IDLE 0xe2c4 +#define regBIF_DEV0_PF0_RST_VF_FLR_IDLE_BASE_IDX 5 +#define regBIF_DEV0_PF1_RST_VF_FLR_IDLE 0xe2c5 +#define regBIF_DEV0_PF1_RST_VF_FLR_IDLE_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF_FLR_INTR_STS 0xe2c8 +#define regBIF_DEV0_PF0_VF_FLR_INTR_STS_BASE_IDX 5 +#define regBIF_DEV0_PF1_VF_FLR_INTR_STS 0xe2c9 +#define regBIF_DEV0_PF1_VF_FLR_INTR_STS_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF_FLR_RST 0xe2cc +#define regBIF_DEV0_PF0_VF_FLR_RST_BASE_IDX 5 +#define regBIF_DEV0_PF1_VF_FLR_RST 0xe2cd +#define regBIF_DEV0_PF1_VF_FLR_RST_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_misc_bif_misc_regblk +// base address: 0x10100000 +#define regDOE_PRV_CTRL0_DEV0F0 0xc806 +#define regDOE_PRV_CTRL0_DEV0F0_BASE_IDX 5 +#define regDOE_PRV_CMD_DEV0F0 0xc807 +#define regDOE_PRV_CMD_DEV0F0_BASE_IDX 5 +#define regDOE_PRV_WDATA_DEV0F0 0xc808 +#define regDOE_PRV_WDATA_DEV0F0_BASE_IDX 5 +#define regDOE_PRV_STS_DEV0F0 0xc809 +#define regDOE_PRV_STS_DEV0F0_BASE_IDX 5 +#define regDOE_PRV_RDATA_DEV0F0 0xc80a +#define regDOE_PRV_RDATA_DEV0F0_BASE_IDX 5 +#define regNBIF_RC_INTR_CNTL 0xc81b +#define regNBIF_RC_INTR_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_TDISP_CNTL 0xc8c0 +#define regBIF_DEV0_PF0_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF1_TDISP_CNTL 0xc8c1 +#define regBIF_DEV0_PF1_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF0_TDISP_CNTL 0xc8d0 +#define regBIF_DEV0_PF0_VF0_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF1_TDISP_CNTL 0xc8d1 +#define regBIF_DEV0_PF0_VF1_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF2_TDISP_CNTL 0xc8d2 +#define regBIF_DEV0_PF0_VF2_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF3_TDISP_CNTL 0xc8d3 +#define regBIF_DEV0_PF0_VF3_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF4_TDISP_CNTL 0xc8d4 +#define regBIF_DEV0_PF0_VF4_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF5_TDISP_CNTL 0xc8d5 +#define regBIF_DEV0_PF0_VF5_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF6_TDISP_CNTL 0xc8d6 +#define regBIF_DEV0_PF0_VF6_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF0_VF7_TDISP_CNTL 0xc8d7 +#define regBIF_DEV0_PF0_VF7_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_PF1_VF0_TDISP_CNTL 0xc8d8 +#define regBIF_DEV0_PF1_VF0_TDISP_CNTL_BASE_IDX 5 +#define regBIF_TDISP_ERROR_DEV0_PF0_INST0 0xc9d0 +#define regBIF_TDISP_ERROR_DEV0_PF0_INST0_BASE_IDX 5 +#define regBIF_TDISP_ERROR_DEV0_PF1_INST0 0xc9d1 +#define regBIF_TDISP_ERROR_DEV0_PF1_INST0_BASE_IDX 5 +#define regBIF_TDISP_UNLOCKED_DEV0_PF0_INST0 0xc9d8 +#define regBIF_TDISP_UNLOCKED_DEV0_PF0_INST0_BASE_IDX 5 +#define regBIF_TDISP_UNLOCKED_DEV0_PF1_INST0 0xc9d9 +#define regBIF_TDISP_UNLOCKED_DEV0_PF1_INST0_BASE_IDX 5 +#define regBIF_TDISP_MISC_CNTL_DEV0 0xc9e0 +#define regBIF_TDISP_MISC_CNTL_DEV0_BASE_IDX 5 +#define regBIF_TDISP_MISC_CNTL 0xc9e4 +#define regBIF_TDISP_MISC_CNTL_BASE_IDX 5 +#define regBIF_RCC_IDE_TDISP_CNTL 0xc9e5 +#define regBIF_RCC_IDE_TDISP_CNTL_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31 0xca00 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31 0xca01 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31 0xca02 +#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31 0xca03 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31 0xca04 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31 0xca05 +#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31 0xca06 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31 0xca07 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31 0xca08 +#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31 0xca09 +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31 0xca0a +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31 0xca0b +#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31 0xca0c +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31 0xca0d +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31 0xca0e +#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31 0xca0f +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31 0xca10 +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31 0xca11 +#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31 0xca12 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31 0xca13 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31 0xca14 +#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31 0xca15 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31 0xca16 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31 0xca17 +#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31 0xca18 +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31 0xca19 +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31_BASE_IDX 5 +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31 0xca1a +#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31_BASE_IDX 5 +#define regBIF_SYSTEM_EN 0xca1b +#define regBIF_SYSTEM_EN_BASE_IDX 5 +#define regBIF_MASK_SYSTEM_EN 0xca1c +#define regBIF_MASK_SYSTEM_EN_BASE_IDX 5 +#define regGPUIOV_SCH0 0xcb40 +#define regGPUIOV_SCH0_BASE_IDX 5 +#define regGPUIOV_SCH1 0xcb41 +#define regGPUIOV_SCH1_BASE_IDX 5 +#define regGPUIOV_SCH2 0xcb42 +#define regGPUIOV_SCH2_BASE_IDX 5 +#define regGPUIOV_SCH3 0xcb43 +#define regGPUIOV_SCH3_BASE_IDX 5 +#define regGPUIOV_SCH4 0xcb44 +#define regGPUIOV_SCH4_BASE_IDX 5 +#define regGPUIOV_SCH5 0xcb45 +#define regGPUIOV_SCH5_BASE_IDX 5 +#define regGPUIOV_SCH6 0xcb46 +#define regGPUIOV_SCH6_BASE_IDX 5 +#define regGPUIOV_SCH7 0xcb47 +#define regGPUIOV_SCH7_BASE_IDX 5 +#define regGPUIOV_SCH8 0xcb48 +#define regGPUIOV_SCH8_BASE_IDX 5 +#define regGPUIOV_SCH9 0xcb49 +#define regGPUIOV_SCH9_BASE_IDX 5 +#define regGPUIOV_SCH10 0xcb4a +#define regGPUIOV_SCH10_BASE_IDX 5 +#define regGPUIOV_SCH11 0xcb4b +#define regGPUIOV_SCH11_BASE_IDX 5 +#define regGPUIOV_SCH12 0xcb4c +#define regGPUIOV_SCH12_BASE_IDX 5 +#define regGPUIOV_SCH13 0xcb4d +#define regGPUIOV_SCH13_BASE_IDX 5 +#define regGPUIOV_SCH14 0xcb4e +#define regGPUIOV_SCH14_BASE_IDX 5 +#define regGPUIOV_SCH15 0xcb4f +#define regGPUIOV_SCH15_BASE_IDX 5 +#define regGPUIOV_SCH16 0xcb50 +#define regGPUIOV_SCH16_BASE_IDX 5 +#define regGPUIOV_SCH17 0xcb51 +#define regGPUIOV_SCH17_BASE_IDX 5 +#define regGPUIOV_SCH18 0xcb52 +#define regGPUIOV_SCH18_BASE_IDX 5 +#define regGPUIOV_SCH19 0xcb53 +#define regGPUIOV_SCH19_BASE_IDX 5 +#define regGPUIOV_MMHUB_P2P_CNTL 0xcb54 +#define regGPUIOV_MMHUB_P2P_CNTL_BASE_IDX 5 +#define regBIF_AER_INTR_CTRL 0xcb55 +#define regBIF_AER_INTR_CTRL_BASE_IDX 5 +#define regBIF_AER_INTR_STS 0xcb56 +#define regBIF_AER_INTR_STS_BASE_IDX 5 +#define regBIF_PCIE_MSG_CTRL 0xcb57 +#define regBIF_PCIE_MSG_CTRL_BASE_IDX 5 +#define regBIF_PCIE_MSG_HEADER_DW0 0xcb58 +#define regBIF_PCIE_MSG_HEADER_DW0_BASE_IDX 5 +#define regBIF_PCIE_MSG_HEADER_DW1 0xcb59 +#define regBIF_PCIE_MSG_HEADER_DW1_BASE_IDX 5 +#define regBIF_PCIE_MSG_HEADER_DW2 0xcb5a +#define regBIF_PCIE_MSG_HEADER_DW2_BASE_IDX 5 +#define regBIF_PCIE_MSG_HEADER_DW3 0xcb5b +#define regBIF_PCIE_MSG_HEADER_DW3_BASE_IDX 5 +#define regBIF_PCIE_MSG_DATA_DW0 0xcb5c +#define regBIF_PCIE_MSG_DATA_DW0_BASE_IDX 5 +#define regBIF_PCIE_MSG_DATA_DW1 0xcb5d +#define regBIF_PCIE_MSG_DATA_DW1_BASE_IDX 5 +#define regBIF_PCIE_MSG_DATA_DW2 0xcb5e +#define regBIF_PCIE_MSG_DATA_DW2_BASE_IDX 5 +#define regBIF_PCIE_MSG_DATA_DW3 0xcb5f +#define regBIF_PCIE_MSG_DATA_DW3_BASE_IDX 5 +#define regBIFC_SEC_AER_SMN_CTRL0 0xcb60 +#define regBIFC_SEC_AER_SMN_CTRL0_BASE_IDX 5 +#define regBIFC_SEC_AER_SMN_CTRL1 0xcb61 +#define regBIFC_SEC_AER_SMN_CTRL1_BASE_IDX 5 +#define regBIFC_SEC_AER_SMN_CTRL2 0xcb62 +#define regBIFC_SEC_AER_SMN_CTRL2_BASE_IDX 5 +#define regBIF_PCIE_ERR_CTRL0 0xcb63 +#define regBIF_PCIE_ERR_CTRL0_BASE_IDX 5 +#define regBIF_PCIE_ERR_CTRL1 0xcb64 +#define regBIF_PCIE_ERR_CTRL1_BASE_IDX 5 +#define regBIF_PCIE_ERR_CTRL2 0xcb65 +#define regBIF_PCIE_ERR_CTRL2_BASE_IDX 5 +#define regBIF_AER_UNCORR_ERR_STATUS 0xcb66 +#define regBIF_AER_UNCORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_AER_UNCORR_ERR_MASK 0xcb67 +#define regBIF_AER_UNCORR_ERR_MASK_BASE_IDX 5 +#define regBIF_AER_UNCORR_ERR_SEVERITY 0xcb68 +#define regBIF_AER_UNCORR_ERR_SEVERITY_BASE_IDX 5 +#define regBIF_AER_CORR_ERR_STATUS 0xcb69 +#define regBIF_AER_CORR_ERR_STATUS_BASE_IDX 5 +#define regBIF_AER_CORR_ERR_MASK 0xcb6a +#define regBIF_AER_CORR_ERR_MASK_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_0 0xcb6b +#define regRCC_EP_STICKY_RESTORE_0_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_1 0xcb6c +#define regRCC_EP_STICKY_RESTORE_1_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_2 0xcb6d +#define regRCC_EP_STICKY_RESTORE_2_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_3 0xcb6e +#define regRCC_EP_STICKY_RESTORE_3_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_4 0xcb6f +#define regRCC_EP_STICKY_RESTORE_4_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_5 0xcb70 +#define regRCC_EP_STICKY_RESTORE_5_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_6 0xcb71 +#define regRCC_EP_STICKY_RESTORE_6_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_7 0xcb72 +#define regRCC_EP_STICKY_RESTORE_7_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_8 0xcb73 +#define regRCC_EP_STICKY_RESTORE_8_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_9 0xcb74 +#define regRCC_EP_STICKY_RESTORE_9_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_10 0xcb75 +#define regRCC_EP_STICKY_RESTORE_10_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_11 0xcb76 +#define regRCC_EP_STICKY_RESTORE_11_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_12 0xcb77 +#define regRCC_EP_STICKY_RESTORE_12_BASE_IDX 5 +#define regRCC_EP_STICKY_RESTORE_13 0xcb78 +#define regRCC_EP_STICKY_RESTORE_13_BASE_IDX 5 +#define regBIF_DEVICE3_STATUS 0xcb79 +#define regBIF_DEVICE3_STATUS_BASE_IDX 5 +#define regBIFC_SEC_MCTP_SMN_CTRL0 0xcb81 +#define regBIFC_SEC_MCTP_SMN_CTRL0_BASE_IDX 5 +#define regBIFC_SEC_MCTP_SMN_CTRL1 0xcb82 +#define regBIFC_SEC_MCTP_SMN_CTRL1_BASE_IDX 5 +#define regNBIF_MCTP_GENERIC_CNTL 0xcc08 +#define regNBIF_MCTP_GENERIC_CNTL_BASE_IDX 5 +#define regNBIF_MCTP_GENERIC_STATUS 0xcc09 +#define regNBIF_MCTP_GENERIC_STATUS_BASE_IDX 5 +#define regSDPVW_UPDATE_EN 0xcc22 +#define regSDPVW_UPDATE_EN_BASE_IDX 5 +#define regREGS_ROM_OFFSET_CTRL 0xcc23 +#define regREGS_ROM_OFFSET_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_POISON_DATA_DROP_CTRL 0xcc24 +#define regBIFL_SEC_RAS_POISON_DATA_DROP_CTRL_BASE_IDX 5 +#define regREGS_INDEX_DATA_PAIR_CTRL 0xcc25 +#define regREGS_INDEX_DATA_PAIR_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_RESPONSE_DROP_CTRL 0xcc26 +#define regBIFL_SEC_RAS_RESPONSE_DROP_CTRL_BASE_IDX 5 +#define regBIFC_SEC_MCA_SMN_CTRL0 0xcc44 +#define regBIFC_SEC_MCA_SMN_CTRL0_BASE_IDX 5 +#define regBIFC_SEC_MCA_SMN_CTRL1 0xcc45 +#define regBIFC_SEC_MCA_SMN_CTRL1_BASE_IDX 5 +#define regBIFL_SEC_RAS_POISON_DBUG_CTRL 0xcc46 +#define regBIFL_SEC_RAS_POISON_DBUG_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_PARITY_DBUG_CTRL 0xcc47 +#define regBIFL_SEC_RAS_PARITY_DBUG_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_NTB_DBUG_CTRL 0xcc48 +#define regBIFL_SEC_RAS_NTB_DBUG_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL 0xcc4a +#define regBIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_TIMEOUT_DBUG_CTRL 0xcc4c +#define regBIFL_SEC_RAS_TIMEOUT_DBUG_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL 0xcc5b +#define regBIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL 0xcc5c +#define regBIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL 0xcc5d +#define regBIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL 0xcc5e +#define regBIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL 0xcc5f +#define regBIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL 0xcc60 +#define regBIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL 0xcc61 +#define regBIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL 0xcc62 +#define regBIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL 0xcc63 +#define regBIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL 0xcc64 +#define regBIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL 0xcc65 +#define regBIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL 0xcc66 +#define regBIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL 0xcc67 +#define regBIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL 0xcc68 +#define regBIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL 0xcc69 +#define regBIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL 0xcc6a +#define regBIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL 0xcc6b +#define regBIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL 0xcc6c +#define regBIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL 0xcc6d +#define regBIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL 0xcc6e +#define regBIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL 0xcc6f +#define regBIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL 0xcc70 +#define regBIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL 0xcc71 +#define regBIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL 0xcc72 +#define regBIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL 0xcc73 +#define regBIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL 0xcc74 +#define regBIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL 0xcc75 +#define regBIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL 0xcc76 +#define regBIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL 0xcc77 +#define regBIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL 0xcc78 +#define regBIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL 0xcc79 +#define regBIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL 0xcc7a +#define regBIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL 0xcc7b +#define regBIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL 0xcc7c +#define regBIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL 0xcc7d +#define regBIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL 0xcc7e +#define regBIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL 0xcc7f +#define regBIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL 0xcc80 +#define regBIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL 0xcc81 +#define regBIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL_BASE_IDX 5 +#define regBIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL 0xcc82 +#define regBIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL_BASE_IDX 5 +#define regNBIF_STRAP_BIOS_CNTL 0xcc89 +#define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 5 +#define regSMN_MST_NORMAL_SECURITY 0xcdea +#define regSMN_MST_NORMAL_SECURITY_BASE_IDX 5 +#define regOVERRIDE_TYPE_FOR_CHAIN_CTRL 0xcdec +#define regOVERRIDE_TYPE_FOR_CHAIN_CTRL_BASE_IDX 5 +#define regPROCESSING_HINT_SUPPORT_CNTL 0xcded +#define regPROCESSING_HINT_SUPPORT_CNTL_BASE_IDX 5 +#define regDEV0_PF0_VF0_MMIO0_FENCE 0xce40 +#define regDEV0_PF0_VF0_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF1_MMIO0_FENCE 0xce41 +#define regDEV0_PF0_VF1_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF2_MMIO0_FENCE 0xce42 +#define regDEV0_PF0_VF2_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF3_MMIO0_FENCE 0xce43 +#define regDEV0_PF0_VF3_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF4_MMIO0_FENCE 0xce44 +#define regDEV0_PF0_VF4_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF5_MMIO0_FENCE 0xce45 +#define regDEV0_PF0_VF5_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF6_MMIO0_FENCE 0xce46 +#define regDEV0_PF0_VF6_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF7_MMIO0_FENCE 0xce47 +#define regDEV0_PF0_VF7_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_START 0xce48 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_END 0xce49 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_START 0xce4a +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_END 0xce4b +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_START 0xce4c +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_END 0xce4d +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_START 0xce4e +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_END 0xce4f +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_START 0xce50 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_END 0xce51 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_START 0xce52 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_END 0xce53 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_START 0xce54 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_END 0xce55 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_END_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_START 0xce56 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_START_BASE_IDX 5 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_END 0xce57 +#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_END_BASE_IDX 5 +#define regDEV0_PF1_VF0_MMIO0_FENCE 0xce58 +#define regDEV0_PF1_VF0_MMIO0_FENCE_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_START 0xce59 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_END 0xce5a +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_START 0xce5b +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_END 0xce5c +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_START 0xce5d +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_END 0xce5e +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_START 0xce5f +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_END 0xce60 +#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_WR 0xce61 +#define regDEV0_PF0_PF_MMIO0_FENCE_WR_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RD 0xce62 +#define regDEV0_PF0_PF_MMIO0_FENCE_RD_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_START 0xce63 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_END 0xce64 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_START 0xce65 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_END 0xce66 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_START 0xce67 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_END 0xce68 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_START 0xce69 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_END 0xce6a +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_START 0xce6b +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_END 0xce6c +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_START 0xce6d +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_END 0xce6e +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_START 0xce6f +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_END 0xce70 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_START 0xce71 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_END 0xce72 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_START 0xce73 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_END 0xce74 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_START 0xce75 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_END 0xce76 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_START 0xce77 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_END 0xce78 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_START 0xce79 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_END 0xce7a +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_START 0xce7b +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_END 0xce7c +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_START 0xce7d +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_END 0xce7e +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_START 0xce7f +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_END 0xce80 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_START 0xce81 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_END 0xce82 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_START 0xce83 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_END 0xce84 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_START 0xce85 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_END 0xce86 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_START 0xce87 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_END 0xce88 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_START 0xce89 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_END 0xce8a +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_START 0xce8b +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_END 0xce8c +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_START 0xce8d +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_END 0xce8e +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_START 0xce8f +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_END 0xce90 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_START 0xce91 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_END 0xce92 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_START 0xce93 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_END 0xce94 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_START 0xce95 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_END 0xce96 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_START 0xce97 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_END 0xce98 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_START 0xce99 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_END 0xce9a +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_START 0xce9b +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_END 0xce9c +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_START 0xce9d +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_END 0xce9e +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_START 0xce9f +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_END 0xcea0 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_END_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_START 0xcea1 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_START_BASE_IDX 5 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_END 0xcea2 +#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_END_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_WR 0xcea3 +#define regDEV0_PF1_PF_MMIO0_FENCE_WR_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RD 0xcea4 +#define regDEV0_PF1_PF_MMIO0_FENCE_RD_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_START 0xcea5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_START_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_END 0xcea6 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_END_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_START 0xcea7 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_START_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_END 0xcea8 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_END_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_START 0xcea9 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_START_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_END 0xceaa +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_END_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_START 0xceab +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_START_BASE_IDX 5 +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_END 0xceac +#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_END_BASE_IDX 5 +#define regMISC_SCRATCH 0xe800 +#define regMISC_SCRATCH_BASE_IDX 5 +#define regINTR_LINE_POLARITY 0xe801 +#define regINTR_LINE_POLARITY_BASE_IDX 5 +#define regINTR_LINE_ENABLE 0xe802 +#define regINTR_LINE_ENABLE_BASE_IDX 5 +#define regOUTSTANDING_VC_ALLOC 0xe803 +#define regOUTSTANDING_VC_ALLOC_BASE_IDX 5 +#define regBIFC_MISC_CTRL0 0xe804 +#define regBIFC_MISC_CTRL0_BASE_IDX 5 +#define regBIFC_MISC_CTRL1 0xe805 +#define regBIFC_MISC_CTRL1_BASE_IDX 5 +#define regBIFC_BME_ERR_LOG_LB 0xe806 +#define regBIFC_BME_ERR_LOG_LB_BASE_IDX 5 +#define regBIFC_LC_TIMER_CTRL 0xe807 +#define regBIFC_LC_TIMER_CTRL_BASE_IDX 5 +#define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 +#define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 5 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 5 +#define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a +#define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 5 +#define regBIFC_MISC_CTRL2 0xe822 +#define regBIFC_MISC_CTRL2_BASE_IDX 5 +#define regBME_DUMMY_CNTL_0 0xe825 +#define regBME_DUMMY_CNTL_0_BASE_IDX 5 +#define regBIFC_THT_CNTL 0xe827 +#define regBIFC_THT_CNTL_BASE_IDX 5 +#define regBIFC_HSTARB_CNTL 0xe828 +#define regBIFC_HSTARB_CNTL_BASE_IDX 5 +#define regBIFC_GSI_CNTL 0xe829 +#define regBIFC_GSI_CNTL_BASE_IDX 5 +#define regBIFC_PCIEFUNC_CNTL 0xe82a +#define regBIFC_PCIEFUNC_CNTL_BASE_IDX 5 +#define regBIFC_PASID_CHECK_DIS 0xe82b +#define regBIFC_PASID_CHECK_DIS_BASE_IDX 5 +#define regBIFC_SDP_CNTL_0 0xe82c +#define regBIFC_SDP_CNTL_0_BASE_IDX 5 +#define regBIFC_SDP_CNTL_1 0xe82d +#define regBIFC_SDP_CNTL_1_BASE_IDX 5 +#define regBIFC_PASID_STS 0xe82e +#define regBIFC_PASID_STS_BASE_IDX 5 +#define regBIFC_ATHUB_ACT_CNTL 0xe82f +#define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 5 +#define regBIFC_PERF_CNTL_0 0xe830 +#define regBIFC_PERF_CNTL_0_BASE_IDX 5 +#define regBIF_MISC_BIFC_PERF_CNTL_1 0xe831 +#define regBIF_MISC_BIFC_PERF_CNTL_1_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 5 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 5 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 5 +#define regNBIF_REGIF_ERRSET_CTRL 0xe836 +#define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 5 +#define regBIFC_SDP_CNTL_2 0xe837 +#define regBIFC_SDP_CNTL_2_BASE_IDX 5 +#define regNBIF_PGMST_CTRL 0xe838 +#define regNBIF_PGMST_CTRL_BASE_IDX 5 +#define regNBIF_PGSLV_CTRL 0xe839 +#define regNBIF_PGSLV_CTRL_BASE_IDX 5 +#define regNBIF_PG_MISC_CTRL 0xe83a +#define regNBIF_PG_MISC_CTRL_BASE_IDX 5 +#define regSMN_MST_EP_CNTL3 0xe83c +#define regSMN_MST_EP_CNTL3_BASE_IDX 5 +#define regSMN_MST_EP_CNTL4 0xe83d +#define regSMN_MST_EP_CNTL4_BASE_IDX 5 +#define regSMN_MST_CNTL1 0xe83e +#define regSMN_MST_CNTL1_BASE_IDX 5 +#define regSMN_MST_EP_CNTL5 0xe83f +#define regSMN_MST_EP_CNTL5_BASE_IDX 5 +#define regBIF_SELFRING_BUFFER_VID 0xe840 +#define regBIF_SELFRING_BUFFER_VID_BASE_IDX 5 +#define regBIF_SELFRING_VECTOR_CNTL 0xe841 +#define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 5 +#define regHDP_ERR_STATUS_EXT 0xe842 +#define regHDP_ERR_STATUS_EXT_BASE_IDX 5 +#define regNBIF_STRAP_WRITE_CTRL 0xe845 +#define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 5 +#define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 +#define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 5 +#define regNBIF_PENDING_MISC_CNTL 0xe847 +#define regNBIF_PENDING_MISC_CNTL_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT 0xe848 +#define regBIF_GMI_WRR_WEIGHT_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT2 0xe849 +#define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT3 0xe84a +#define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 5 +#define regBIF_GMI_WRR_WEIGHT4 0xe84b +#define regBIF_GMI_WRR_WEIGHT4_BASE_IDX 5 +#define regNBIF_PWRBRK_REQUEST 0xe84c +#define regNBIF_PWRBRK_REQUEST_BASE_IDX 5 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 5 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 5 +#define regBIF_DMA_MP4_ERR_LOG 0xe870 +#define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 5 +#define regBIF_PASID_ERR_LOG 0xe871 +#define regBIF_PASID_ERR_LOG_BASE_IDX 5 +#define regBIF_PASID_ERR_CLR 0xe872 +#define regBIF_PASID_ERR_CLR_BASE_IDX 5 +#define regNBIF_VWIRE_CTRL 0xe880 +#define regNBIF_VWIRE_CTRL_BASE_IDX 5 +#define regNBIF_MGCG_CTRL_LCLK 0xe887 +#define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 5 +#define regNBIF_DS_CTRL_LCLK 0xe888 +#define regNBIF_DS_CTRL_LCLK_BASE_IDX 5 +#define regSMN_MST_CNTL0 0xe889 +#define regSMN_MST_CNTL0_BASE_IDX 5 +#define regSMN_MST_EP_CNTL1 0xe88a +#define regSMN_MST_EP_CNTL1_BASE_IDX 5 +#define regSMN_MST_EP_CNTL2 0xe88b +#define regSMN_MST_EP_CNTL2_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 5 +#define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f +#define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 5 +#define regNBIO_LCLK_DEEPSLEEP_MASK 0xe890 +#define regNBIO_LCLK_DEEPSLEEP_MASK_BASE_IDX 5 +#define regNBIF_DS_CTRL_USBCLK 0xe891 +#define regNBIF_DS_CTRL_USBCLK_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_MISC3 0xe897 +#define regNBIF_SHUB_TODET_CLIENT_MISC3_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CTRL 0xe898 +#define regNBIF_SHUB_TODET_CTRL_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899 +#define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a +#define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 5 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c +#define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d +#define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 5 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 5 +#define regDMA_SDP_PORT_DEBUG 0xe8a0 +#define regDMA_SDP_PORT_DEBUG_BASE_IDX 5 +#define regSDP_PORT_MONITOR_CONTROL 0xe8a2 +#define regSDP_PORT_MONITOR_CONTROL_BASE_IDX 5 +#define regSDP_PORT_MONITOR_ADDRESS0 0xe8a3 +#define regSDP_PORT_MONITOR_ADDRESS0_BASE_IDX 5 +#define regSDP_PORT_MONITOR_ADDRESS1 0xe8a4 +#define regSDP_PORT_MONITOR_ADDRESS1_BASE_IDX 5 +#define regSDP_PORT_MONITOR_UNITID 0xe8a5 +#define regSDP_PORT_MONITOR_UNITID_BASE_IDX 5 +#define regSDP_PORT_MONITOR_INFO0 0xe8a6 +#define regSDP_PORT_MONITOR_INFO0_BASE_IDX 5 +#define regSDP_PORT_MONITOR_INFO1 0xe8a7 +#define regSDP_PORT_MONITOR_INFO1_BASE_IDX 5 +#define regSDP_PORT_MONITOR_INFO2 0xe8a8 +#define regSDP_PORT_MONITOR_INFO2_BASE_IDX 5 +#define regSDP_PORT_MONITOR_INFO3 0xe8a9 +#define regSDP_PORT_MONITOR_INFO3_BASE_IDX 5 +#define regSDP_PORT_MONITOR_INFO4 0xe8aa +#define regSDP_PORT_MONITOR_INFO4_BASE_IDX 5 +#define regBIFC_BME_ERR_LOG_HB 0xe8ab +#define regBIFC_BME_ERR_LOG_HB_BASE_IDX 5 +#define regBIFC_GFX_INT_MONITOR_MASK 0xe8ad +#define regBIFC_GFX_INT_MONITOR_MASK_BASE_IDX 5 +#define regBIFC_GFX_INT_MONITOR_STS 0xe8ae +#define regBIFC_GFX_INT_MONITOR_STS_BASE_IDX 5 +#define regBIFC_GFX_INT_MONITOR_CTRL 0xe8af +#define regBIFC_GFX_INT_MONITOR_CTRL_BASE_IDX 5 +#define regNBIF_FLUSH_CTRL 0xe8b1 +#define regNBIF_FLUSH_CTRL_BASE_IDX 5 +#define regNBIF_GUI_FLUSH_CNTL 0xe8b3 +#define regNBIF_GUI_FLUSH_CNTL_BASE_IDX 5 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC 0xe8c4 +#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC 0xe8c5 +#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 +#define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 +#define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 5 +#define regBIFC_GSI_SDP_REQ_POOLCRED_ALLOC 0xe8c7 +#define regBIFC_GSI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_GSI_SDP_DAT_POOLCRED_ALLOC 0xe8c8 +#define regBIFC_GSI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5 +#define regBIFC_MCA_SMN_CTRL0 0xe8cb +#define regBIFC_MCA_SMN_CTRL0_BASE_IDX 5 +#define regBIFC_MCTP_SMN_CTRL0 0xe8ce +#define regBIFC_MCTP_SMN_CTRL0_BASE_IDX 5 +#define regNBIF_REGIF_DEBUG_COUNTER_CTRL 0xe8cf +#define regNBIF_REGIF_DEBUG_COUNTER_CTRL_BASE_IDX 5 +#define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 +#define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 5 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 5 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 5 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 +#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_PERF_COM_COUNT_ENABLE 0xe8f4 +#define regBIF_MISC_NBIF_PERF_COM_COUNT_ENABLE_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_FSM 0xe8f5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_FSM_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_COUNTER 0xe8f6 +#define regBIF_MISC_NBIF_SDP_PERF_COUNTER_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT 0xe8f7 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT 0xe8f8 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT 0xe8f9 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT 0xe8fa +#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT 0xe8fb +#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT 0xe8fc +#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT 0xe8fd +#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT 0xe8fe +#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT_BASE_IDX 5 +#define regBIF_MISC_NBIF_BX_PERF_CNT_FSM 0xe8ff +#define regBIF_MISC_NBIF_BX_PERF_CNT_FSM_BASE_IDX 5 +#define regNBIF_TDISP_ENTER_ERR_CNTL 0xe905 +#define regNBIF_TDISP_ENTER_ERR_CNTL_BASE_IDX 5 +#define regBIF_UNITID_ERR_LOG 0xe906 +#define regBIF_UNITID_ERR_LOG_BASE_IDX 5 +#define regNBIF_COM_COUNT_VALUE 0xe908 +#define regNBIF_COM_COUNT_VALUE_BASE_IDX 5 +#define regNBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL 0xe909 +#define regNBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL_BASE_IDX 5 +#define regNBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL 0xe90a +#define regNBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL_BASE_IDX 5 +#define regBIF_AER_CNTL 0xe92c +#define regBIF_AER_CNTL_BASE_IDX 5 +#define regNBIF_IDE_INFO_CNTL 0xe92d +#define regNBIF_IDE_INFO_CNTL_BASE_IDX 5 +#define regBIFC_EXP_MISC_CTRL0 0xe9c0 +#define regBIFC_EXP_MISC_CTRL0_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_PF 0xea80 +#define regSECOND_HDP_MEM_FLUSH_CNTL_PF_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF0 0xea81 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF0_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF1 0xea82 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF1_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF2 0xea83 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF2_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF3 0xea84 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF3_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF4 0xea85 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF4_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF5 0xea86 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF5_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF6 0xea87 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF6_BASE_IDX 5 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF7 0xea88 +#define regSECOND_HDP_MEM_FLUSH_CNTL_VF7_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_PF 0xea89 +#define regSECOND_HDP_REG_FLUSH_CNTL_PF_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF0 0xea8a +#define regSECOND_HDP_REG_FLUSH_CNTL_VF0_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF1 0xea8b +#define regSECOND_HDP_REG_FLUSH_CNTL_VF1_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF2 0xea8c +#define regSECOND_HDP_REG_FLUSH_CNTL_VF2_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF3 0xea8d +#define regSECOND_HDP_REG_FLUSH_CNTL_VF3_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF4 0xea8e +#define regSECOND_HDP_REG_FLUSH_CNTL_VF4_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF5 0xea8f +#define regSECOND_HDP_REG_FLUSH_CNTL_VF5_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF6 0xea90 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF6_BASE_IDX 5 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF7 0xea91 +#define regSECOND_HDP_REG_FLUSH_CNTL_VF7_BASE_IDX 5 +#define regGPU_HDP_FLUSH_GFX_FW 0xf4c0 +#define regGPU_HDP_FLUSH_GFX_FW_BASE_IDX 5 +#define regNBIF_RRMT_CNTL 0xf500 +#define regNBIF_RRMT_CNTL_BASE_IDX 5 +#define regRRMT_NBIF_MISC_REG1 0xf501 +#define regRRMT_NBIF_MISC_REG1_BASE_IDX 5 +#define regRRMT_LUT_INDEX 0xf502 +#define regRRMT_LUT_INDEX_BASE_IDX 5 +#define regRRMT_LUT_DATA 0xf503 +#define regRRMT_LUT_DATA_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf0_bif_misc_pfvf_regblk +// base address: 0x10100000 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0 0xf600 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1 0xf601 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2 0xf602 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3 0xf603 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0 0xf604 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1 0xf605 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2 0xf606 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3 0xf607 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0 0xf608 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1 0xf609 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2 0xf60a +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3 0xf60b +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0 0xf60c +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1 0xf60d +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2 0xf60e +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3 0xf60f +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0 0xf610 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1 0xf611 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2 0xf612 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3 0xf613 +#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf1_bif_misc_pfvf_regblk +// base address: 0x10100000 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0 0xf619 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1 0xf61a +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2 0xf61b +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3 0xf61c +#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0 0xf61d +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1 0xf61e +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2 0xf61f +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3 0xf620 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0 0xf621 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1 0xf622 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2 0xf623 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3 0xf624 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0 0xf625 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1 0xf626 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2 0xf627 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3 0xf628 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0 0xf629 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1 0xf62a +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2 0xf62b +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2_BASE_IDX 5 +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3 0xf62c +#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_trap_bif_trap_regblk +// base address: 0x10100000 +#define regNBIF_TRAP_NP_STATUS 0x4000 +#define regNBIF_TRAP_NP_STATUS_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST0 0x4001 +#define regNBIF_TRAP_NP_REQUEST0_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST1 0x4002 +#define regNBIF_TRAP_NP_REQUEST1_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST2 0x4003 +#define regNBIF_TRAP_NP_REQUEST2_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST3 0x4004 +#define regNBIF_TRAP_NP_REQUEST3_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST4 0x4005 +#define regNBIF_TRAP_NP_REQUEST4_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST5 0x4006 +#define regNBIF_TRAP_NP_REQUEST5_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST6 0x4007 +#define regNBIF_TRAP_NP_REQUEST6_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB0 0x4008 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB0_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB1 0x4009 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB1_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB2 0x400a +#define regNBIF_TRAP_NP_REQUEST_DATASTRB2_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB3 0x400b +#define regNBIF_TRAP_NP_REQUEST_DATASTRB3_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB4 0x400c +#define regNBIF_TRAP_NP_REQUEST_DATASTRB4_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB5 0x400d +#define regNBIF_TRAP_NP_REQUEST_DATASTRB5_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB6 0x400e +#define regNBIF_TRAP_NP_REQUEST_DATASTRB6_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATASTRB7 0x400f +#define regNBIF_TRAP_NP_REQUEST_DATASTRB7_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA0 0x4010 +#define regNBIF_TRAP_NP_REQUEST_DATA0_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA1 0x4011 +#define regNBIF_TRAP_NP_REQUEST_DATA1_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA2 0x4012 +#define regNBIF_TRAP_NP_REQUEST_DATA2_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA3 0x4013 +#define regNBIF_TRAP_NP_REQUEST_DATA3_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA4 0x4014 +#define regNBIF_TRAP_NP_REQUEST_DATA4_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA5 0x4015 +#define regNBIF_TRAP_NP_REQUEST_DATA5_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA6 0x4016 +#define regNBIF_TRAP_NP_REQUEST_DATA6_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA7 0x4017 +#define regNBIF_TRAP_NP_REQUEST_DATA7_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA8 0x4018 +#define regNBIF_TRAP_NP_REQUEST_DATA8_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA9 0x4019 +#define regNBIF_TRAP_NP_REQUEST_DATA9_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA10 0x401a +#define regNBIF_TRAP_NP_REQUEST_DATA10_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA11 0x401b +#define regNBIF_TRAP_NP_REQUEST_DATA11_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA12 0x401c +#define regNBIF_TRAP_NP_REQUEST_DATA12_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA13 0x401d +#define regNBIF_TRAP_NP_REQUEST_DATA13_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA14 0x401e +#define regNBIF_TRAP_NP_REQUEST_DATA14_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA15 0x401f +#define regNBIF_TRAP_NP_REQUEST_DATA15_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA16 0x4020 +#define regNBIF_TRAP_NP_REQUEST_DATA16_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA17 0x4021 +#define regNBIF_TRAP_NP_REQUEST_DATA17_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA18 0x4022 +#define regNBIF_TRAP_NP_REQUEST_DATA18_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA19 0x4023 +#define regNBIF_TRAP_NP_REQUEST_DATA19_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA20 0x4024 +#define regNBIF_TRAP_NP_REQUEST_DATA20_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA21 0x4025 +#define regNBIF_TRAP_NP_REQUEST_DATA21_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA22 0x4026 +#define regNBIF_TRAP_NP_REQUEST_DATA22_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA23 0x4027 +#define regNBIF_TRAP_NP_REQUEST_DATA23_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA24 0x4028 +#define regNBIF_TRAP_NP_REQUEST_DATA24_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA25 0x4029 +#define regNBIF_TRAP_NP_REQUEST_DATA25_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA26 0x402a +#define regNBIF_TRAP_NP_REQUEST_DATA26_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA27 0x402b +#define regNBIF_TRAP_NP_REQUEST_DATA27_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA28 0x402c +#define regNBIF_TRAP_NP_REQUEST_DATA28_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA29 0x402d +#define regNBIF_TRAP_NP_REQUEST_DATA29_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA30 0x402e +#define regNBIF_TRAP_NP_REQUEST_DATA30_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA31 0x402f +#define regNBIF_TRAP_NP_REQUEST_DATA31_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA32 0x4030 +#define regNBIF_TRAP_NP_REQUEST_DATA32_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA33 0x4031 +#define regNBIF_TRAP_NP_REQUEST_DATA33_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA34 0x4032 +#define regNBIF_TRAP_NP_REQUEST_DATA34_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA35 0x4033 +#define regNBIF_TRAP_NP_REQUEST_DATA35_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA36 0x4034 +#define regNBIF_TRAP_NP_REQUEST_DATA36_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA37 0x4035 +#define regNBIF_TRAP_NP_REQUEST_DATA37_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA38 0x4036 +#define regNBIF_TRAP_NP_REQUEST_DATA38_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA39 0x4037 +#define regNBIF_TRAP_NP_REQUEST_DATA39_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA40 0x4038 +#define regNBIF_TRAP_NP_REQUEST_DATA40_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA41 0x4039 +#define regNBIF_TRAP_NP_REQUEST_DATA41_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA42 0x403a +#define regNBIF_TRAP_NP_REQUEST_DATA42_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA43 0x403b +#define regNBIF_TRAP_NP_REQUEST_DATA43_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA44 0x403c +#define regNBIF_TRAP_NP_REQUEST_DATA44_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA45 0x403d +#define regNBIF_TRAP_NP_REQUEST_DATA45_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA46 0x403e +#define regNBIF_TRAP_NP_REQUEST_DATA46_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA47 0x403f +#define regNBIF_TRAP_NP_REQUEST_DATA47_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA48 0x4040 +#define regNBIF_TRAP_NP_REQUEST_DATA48_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA49 0x4041 +#define regNBIF_TRAP_NP_REQUEST_DATA49_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA50 0x4042 +#define regNBIF_TRAP_NP_REQUEST_DATA50_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA51 0x4043 +#define regNBIF_TRAP_NP_REQUEST_DATA51_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA52 0x4044 +#define regNBIF_TRAP_NP_REQUEST_DATA52_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA53 0x4045 +#define regNBIF_TRAP_NP_REQUEST_DATA53_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA54 0x4046 +#define regNBIF_TRAP_NP_REQUEST_DATA54_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA55 0x4047 +#define regNBIF_TRAP_NP_REQUEST_DATA55_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA56 0x4048 +#define regNBIF_TRAP_NP_REQUEST_DATA56_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA57 0x4049 +#define regNBIF_TRAP_NP_REQUEST_DATA57_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA58 0x404a +#define regNBIF_TRAP_NP_REQUEST_DATA58_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA59 0x404b +#define regNBIF_TRAP_NP_REQUEST_DATA59_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA60 0x404c +#define regNBIF_TRAP_NP_REQUEST_DATA60_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA61 0x404d +#define regNBIF_TRAP_NP_REQUEST_DATA61_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA62 0x404e +#define regNBIF_TRAP_NP_REQUEST_DATA62_BASE_IDX 5 +#define regNBIF_TRAP_NP_REQUEST_DATA63 0x404f +#define regNBIF_TRAP_NP_REQUEST_DATA63_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_CONTROL 0x4050 +#define regNBIF_TRAP_NP_RESPONSE_CONTROL_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE0 0x4051 +#define regNBIF_TRAP_NP_RESPONSE0_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE1 0x4052 +#define regNBIF_TRAP_NP_RESPONSE1_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE2 0x4053 +#define regNBIF_TRAP_NP_RESPONSE2_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE3 0x4054 +#define regNBIF_TRAP_NP_RESPONSE3_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE4 0x4055 +#define regNBIF_TRAP_NP_RESPONSE4_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE5 0x4056 +#define regNBIF_TRAP_NP_RESPONSE5_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA0 0x4057 +#define regNBIF_TRAP_NP_RESPONSE_DATA0_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA1 0x4058 +#define regNBIF_TRAP_NP_RESPONSE_DATA1_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA2 0x4059 +#define regNBIF_TRAP_NP_RESPONSE_DATA2_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA3 0x405a +#define regNBIF_TRAP_NP_RESPONSE_DATA3_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA4 0x405b +#define regNBIF_TRAP_NP_RESPONSE_DATA4_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA5 0x405c +#define regNBIF_TRAP_NP_RESPONSE_DATA5_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA6 0x405d +#define regNBIF_TRAP_NP_RESPONSE_DATA6_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA7 0x405e +#define regNBIF_TRAP_NP_RESPONSE_DATA7_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA8 0x405f +#define regNBIF_TRAP_NP_RESPONSE_DATA8_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA9 0x4060 +#define regNBIF_TRAP_NP_RESPONSE_DATA9_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA10 0x4061 +#define regNBIF_TRAP_NP_RESPONSE_DATA10_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA11 0x4062 +#define regNBIF_TRAP_NP_RESPONSE_DATA11_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA12 0x4063 +#define regNBIF_TRAP_NP_RESPONSE_DATA12_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA13 0x4064 +#define regNBIF_TRAP_NP_RESPONSE_DATA13_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA14 0x4065 +#define regNBIF_TRAP_NP_RESPONSE_DATA14_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA15 0x4066 +#define regNBIF_TRAP_NP_RESPONSE_DATA15_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA16 0x4067 +#define regNBIF_TRAP_NP_RESPONSE_DATA16_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA17 0x4068 +#define regNBIF_TRAP_NP_RESPONSE_DATA17_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA18 0x4069 +#define regNBIF_TRAP_NP_RESPONSE_DATA18_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA19 0x406a +#define regNBIF_TRAP_NP_RESPONSE_DATA19_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA20 0x406b +#define regNBIF_TRAP_NP_RESPONSE_DATA20_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA21 0x406c +#define regNBIF_TRAP_NP_RESPONSE_DATA21_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA22 0x406d +#define regNBIF_TRAP_NP_RESPONSE_DATA22_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA23 0x406e +#define regNBIF_TRAP_NP_RESPONSE_DATA23_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA24 0x406f +#define regNBIF_TRAP_NP_RESPONSE_DATA24_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA25 0x4070 +#define regNBIF_TRAP_NP_RESPONSE_DATA25_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA26 0x4071 +#define regNBIF_TRAP_NP_RESPONSE_DATA26_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA27 0x4072 +#define regNBIF_TRAP_NP_RESPONSE_DATA27_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA28 0x4073 +#define regNBIF_TRAP_NP_RESPONSE_DATA28_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA29 0x4074 +#define regNBIF_TRAP_NP_RESPONSE_DATA29_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA30 0x4075 +#define regNBIF_TRAP_NP_RESPONSE_DATA30_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA31 0x4076 +#define regNBIF_TRAP_NP_RESPONSE_DATA31_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA32 0x4077 +#define regNBIF_TRAP_NP_RESPONSE_DATA32_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA33 0x4078 +#define regNBIF_TRAP_NP_RESPONSE_DATA33_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA34 0x4079 +#define regNBIF_TRAP_NP_RESPONSE_DATA34_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA35 0x407a +#define regNBIF_TRAP_NP_RESPONSE_DATA35_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA36 0x407b +#define regNBIF_TRAP_NP_RESPONSE_DATA36_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA37 0x407c +#define regNBIF_TRAP_NP_RESPONSE_DATA37_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA38 0x407d +#define regNBIF_TRAP_NP_RESPONSE_DATA38_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA39 0x407e +#define regNBIF_TRAP_NP_RESPONSE_DATA39_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA40 0x407f +#define regNBIF_TRAP_NP_RESPONSE_DATA40_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA41 0x4080 +#define regNBIF_TRAP_NP_RESPONSE_DATA41_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA42 0x4081 +#define regNBIF_TRAP_NP_RESPONSE_DATA42_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA43 0x4082 +#define regNBIF_TRAP_NP_RESPONSE_DATA43_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA44 0x4083 +#define regNBIF_TRAP_NP_RESPONSE_DATA44_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA45 0x4084 +#define regNBIF_TRAP_NP_RESPONSE_DATA45_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA46 0x4085 +#define regNBIF_TRAP_NP_RESPONSE_DATA46_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA47 0x4086 +#define regNBIF_TRAP_NP_RESPONSE_DATA47_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA48 0x4087 +#define regNBIF_TRAP_NP_RESPONSE_DATA48_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA49 0x4088 +#define regNBIF_TRAP_NP_RESPONSE_DATA49_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA50 0x4089 +#define regNBIF_TRAP_NP_RESPONSE_DATA50_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA51 0x408a +#define regNBIF_TRAP_NP_RESPONSE_DATA51_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA52 0x408b +#define regNBIF_TRAP_NP_RESPONSE_DATA52_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA53 0x408c +#define regNBIF_TRAP_NP_RESPONSE_DATA53_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA54 0x408d +#define regNBIF_TRAP_NP_RESPONSE_DATA54_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA55 0x408e +#define regNBIF_TRAP_NP_RESPONSE_DATA55_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA56 0x408f +#define regNBIF_TRAP_NP_RESPONSE_DATA56_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA57 0x4090 +#define regNBIF_TRAP_NP_RESPONSE_DATA57_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA58 0x4091 +#define regNBIF_TRAP_NP_RESPONSE_DATA58_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA59 0x4092 +#define regNBIF_TRAP_NP_RESPONSE_DATA59_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA60 0x4093 +#define regNBIF_TRAP_NP_RESPONSE_DATA60_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA61 0x4094 +#define regNBIF_TRAP_NP_RESPONSE_DATA61_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA62 0x4095 +#define regNBIF_TRAP_NP_RESPONSE_DATA62_BASE_IDX 5 +#define regNBIF_TRAP_NP_RESPONSE_DATA63 0x4096 +#define regNBIF_TRAP_NP_RESPONSE_DATA63_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_CONTROL0 0x4097 +#define regNBIF_TRAP_NP_0_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_ADDRESS_LO 0x4098 +#define regNBIF_TRAP_NP_0_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_ADDRESS_HI 0x4099 +#define regNBIF_TRAP_NP_0_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_COMMAND 0x409a +#define regNBIF_TRAP_NP_0_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_ADDRESS_LO_MASK 0x409b +#define regNBIF_TRAP_NP_0_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_ADDRESS_HI_MASK 0x409c +#define regNBIF_TRAP_NP_0_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_0_COMMAND_MASK 0x409d +#define regNBIF_TRAP_NP_0_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_CONTROL0 0x409e +#define regNBIF_TRAP_NP_1_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_ADDRESS_LO 0x409f +#define regNBIF_TRAP_NP_1_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_ADDRESS_HI 0x40a0 +#define regNBIF_TRAP_NP_1_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_COMMAND 0x40a1 +#define regNBIF_TRAP_NP_1_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_ADDRESS_LO_MASK 0x40a2 +#define regNBIF_TRAP_NP_1_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_ADDRESS_HI_MASK 0x40a3 +#define regNBIF_TRAP_NP_1_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_1_COMMAND_MASK 0x40a4 +#define regNBIF_TRAP_NP_1_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_CONTROL0 0x40a5 +#define regNBIF_TRAP_NP_2_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_ADDRESS_LO 0x40a6 +#define regNBIF_TRAP_NP_2_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_ADDRESS_HI 0x40a7 +#define regNBIF_TRAP_NP_2_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_COMMAND 0x40a8 +#define regNBIF_TRAP_NP_2_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_ADDRESS_LO_MASK 0x40a9 +#define regNBIF_TRAP_NP_2_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_ADDRESS_HI_MASK 0x40aa +#define regNBIF_TRAP_NP_2_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_2_COMMAND_MASK 0x40ab +#define regNBIF_TRAP_NP_2_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_CONTROL0 0x40ac +#define regNBIF_TRAP_NP_3_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_ADDRESS_LO 0x40ad +#define regNBIF_TRAP_NP_3_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_ADDRESS_HI 0x40ae +#define regNBIF_TRAP_NP_3_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_COMMAND 0x40af +#define regNBIF_TRAP_NP_3_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_ADDRESS_LO_MASK 0x40b0 +#define regNBIF_TRAP_NP_3_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_ADDRESS_HI_MASK 0x40b1 +#define regNBIF_TRAP_NP_3_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_3_COMMAND_MASK 0x40b2 +#define regNBIF_TRAP_NP_3_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_CONTROL0 0x40b3 +#define regNBIF_TRAP_NP_4_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_ADDRESS_LO 0x40b4 +#define regNBIF_TRAP_NP_4_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_ADDRESS_HI 0x40b5 +#define regNBIF_TRAP_NP_4_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_COMMAND 0x40b6 +#define regNBIF_TRAP_NP_4_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_ADDRESS_LO_MASK 0x40b7 +#define regNBIF_TRAP_NP_4_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_ADDRESS_HI_MASK 0x40b8 +#define regNBIF_TRAP_NP_4_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_4_COMMAND_MASK 0x40b9 +#define regNBIF_TRAP_NP_4_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_CONTROL0 0x40ba +#define regNBIF_TRAP_NP_5_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_ADDRESS_LO 0x40bb +#define regNBIF_TRAP_NP_5_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_ADDRESS_HI 0x40bc +#define regNBIF_TRAP_NP_5_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_COMMAND 0x40bd +#define regNBIF_TRAP_NP_5_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_ADDRESS_LO_MASK 0x40be +#define regNBIF_TRAP_NP_5_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_ADDRESS_HI_MASK 0x40bf +#define regNBIF_TRAP_NP_5_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_5_COMMAND_MASK 0x40c0 +#define regNBIF_TRAP_NP_5_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_CONTROL0 0x40c1 +#define regNBIF_TRAP_NP_6_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_ADDRESS_LO 0x40c2 +#define regNBIF_TRAP_NP_6_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_ADDRESS_HI 0x40c3 +#define regNBIF_TRAP_NP_6_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_COMMAND 0x40c4 +#define regNBIF_TRAP_NP_6_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_ADDRESS_LO_MASK 0x40c5 +#define regNBIF_TRAP_NP_6_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_ADDRESS_HI_MASK 0x40c6 +#define regNBIF_TRAP_NP_6_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_6_COMMAND_MASK 0x40c7 +#define regNBIF_TRAP_NP_6_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_CONTROL0 0x40c8 +#define regNBIF_TRAP_NP_7_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_ADDRESS_LO 0x40c9 +#define regNBIF_TRAP_NP_7_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_ADDRESS_HI 0x40ca +#define regNBIF_TRAP_NP_7_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_COMMAND 0x40cb +#define regNBIF_TRAP_NP_7_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_ADDRESS_LO_MASK 0x40cc +#define regNBIF_TRAP_NP_7_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_ADDRESS_HI_MASK 0x40cd +#define regNBIF_TRAP_NP_7_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_7_COMMAND_MASK 0x40ce +#define regNBIF_TRAP_NP_7_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_CONTROL0 0x40cf +#define regNBIF_TRAP_NP_8_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_ADDRESS_LO 0x40d0 +#define regNBIF_TRAP_NP_8_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_ADDRESS_HI 0x40d1 +#define regNBIF_TRAP_NP_8_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_COMMAND 0x40d2 +#define regNBIF_TRAP_NP_8_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_ADDRESS_LO_MASK 0x40d3 +#define regNBIF_TRAP_NP_8_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_ADDRESS_HI_MASK 0x40d4 +#define regNBIF_TRAP_NP_8_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_8_COMMAND_MASK 0x40d5 +#define regNBIF_TRAP_NP_8_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_CONTROL0 0x40d6 +#define regNBIF_TRAP_NP_9_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_ADDRESS_LO 0x40d7 +#define regNBIF_TRAP_NP_9_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_ADDRESS_HI 0x40d8 +#define regNBIF_TRAP_NP_9_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_COMMAND 0x40d9 +#define regNBIF_TRAP_NP_9_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_ADDRESS_LO_MASK 0x40da +#define regNBIF_TRAP_NP_9_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_ADDRESS_HI_MASK 0x40db +#define regNBIF_TRAP_NP_9_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_9_COMMAND_MASK 0x40dc +#define regNBIF_TRAP_NP_9_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_CONTROL0 0x40dd +#define regNBIF_TRAP_NP_10_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_ADDRESS_LO 0x40de +#define regNBIF_TRAP_NP_10_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_ADDRESS_HI 0x40df +#define regNBIF_TRAP_NP_10_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_COMMAND 0x40e0 +#define regNBIF_TRAP_NP_10_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_ADDRESS_LO_MASK 0x40e1 +#define regNBIF_TRAP_NP_10_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_ADDRESS_HI_MASK 0x40e2 +#define regNBIF_TRAP_NP_10_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_10_COMMAND_MASK 0x40e3 +#define regNBIF_TRAP_NP_10_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_CONTROL0 0x40e4 +#define regNBIF_TRAP_NP_11_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_ADDRESS_LO 0x40e5 +#define regNBIF_TRAP_NP_11_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_ADDRESS_HI 0x40e6 +#define regNBIF_TRAP_NP_11_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_COMMAND 0x40e7 +#define regNBIF_TRAP_NP_11_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_ADDRESS_LO_MASK 0x40e8 +#define regNBIF_TRAP_NP_11_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_ADDRESS_HI_MASK 0x40e9 +#define regNBIF_TRAP_NP_11_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_11_COMMAND_MASK 0x40ea +#define regNBIF_TRAP_NP_11_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_CONTROL0 0x40eb +#define regNBIF_TRAP_NP_12_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_ADDRESS_LO 0x40ec +#define regNBIF_TRAP_NP_12_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_ADDRESS_HI 0x40ed +#define regNBIF_TRAP_NP_12_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_COMMAND 0x40ee +#define regNBIF_TRAP_NP_12_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_ADDRESS_LO_MASK 0x40ef +#define regNBIF_TRAP_NP_12_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_ADDRESS_HI_MASK 0x40f0 +#define regNBIF_TRAP_NP_12_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_12_COMMAND_MASK 0x40f1 +#define regNBIF_TRAP_NP_12_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_CONTROL0 0x40f2 +#define regNBIF_TRAP_NP_13_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_ADDRESS_LO 0x40f3 +#define regNBIF_TRAP_NP_13_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_ADDRESS_HI 0x40f4 +#define regNBIF_TRAP_NP_13_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_COMMAND 0x40f5 +#define regNBIF_TRAP_NP_13_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_ADDRESS_LO_MASK 0x40f6 +#define regNBIF_TRAP_NP_13_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_ADDRESS_HI_MASK 0x40f7 +#define regNBIF_TRAP_NP_13_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_13_COMMAND_MASK 0x40f8 +#define regNBIF_TRAP_NP_13_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_CONTROL0 0x40f9 +#define regNBIF_TRAP_NP_14_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_ADDRESS_LO 0x40fa +#define regNBIF_TRAP_NP_14_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_ADDRESS_HI 0x40fb +#define regNBIF_TRAP_NP_14_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_COMMAND 0x40fc +#define regNBIF_TRAP_NP_14_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_ADDRESS_LO_MASK 0x40fd +#define regNBIF_TRAP_NP_14_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_ADDRESS_HI_MASK 0x40fe +#define regNBIF_TRAP_NP_14_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_14_COMMAND_MASK 0x40ff +#define regNBIF_TRAP_NP_14_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_CONTROL0 0x4100 +#define regNBIF_TRAP_NP_15_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_ADDRESS_LO 0x4101 +#define regNBIF_TRAP_NP_15_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_ADDRESS_HI 0x4102 +#define regNBIF_TRAP_NP_15_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_COMMAND 0x4103 +#define regNBIF_TRAP_NP_15_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_ADDRESS_LO_MASK 0x4104 +#define regNBIF_TRAP_NP_15_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_ADDRESS_HI_MASK 0x4105 +#define regNBIF_TRAP_NP_15_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_15_COMMAND_MASK 0x4106 +#define regNBIF_TRAP_NP_15_COMMAND_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_CONTROL0 0x4107 +#define regNBIF_TRAP_NP_S2_CONTROL0_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_ADDRESS_LO 0x4108 +#define regNBIF_TRAP_NP_S2_ADDRESS_LO_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_ADDRESS_HI 0x4109 +#define regNBIF_TRAP_NP_S2_ADDRESS_HI_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_COMMAND 0x410a +#define regNBIF_TRAP_NP_S2_COMMAND_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_ADDRESS_LO_MASK 0x410b +#define regNBIF_TRAP_NP_S2_ADDRESS_LO_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_ADDRESS_HI_MASK 0x410c +#define regNBIF_TRAP_NP_S2_ADDRESS_HI_MASK_BASE_IDX 5 +#define regNBIF_TRAP_NP_S2_COMMAND_MASK 0x410d +#define regNBIF_TRAP_NP_S2_COMMAND_MASK_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_ras_bif_ras_regblk +// base address: 0x10100000 +#define regBIFL_RAS_CENTRAL_CNTL 0xe400 +#define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX 5 +#define regBIFL_RAS_CENTRAL_STATUS 0xe404 +#define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF0_CTRL 0xe408 +#define regBIFL_RAS_LEAF0_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF1_CTRL 0xe409 +#define regBIFL_RAS_LEAF1_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF2_CTRL 0xe40a +#define regBIFL_RAS_LEAF2_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF3_CTRL 0xe40b +#define regBIFL_RAS_LEAF3_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF4_CTRL 0xe40c +#define regBIFL_RAS_LEAF4_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF5_CTRL 0xe40d +#define regBIFL_RAS_LEAF5_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF6_CTRL 0xe40e +#define regBIFL_RAS_LEAF6_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF7_CTRL 0xe40f +#define regBIFL_RAS_LEAF7_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF8_CTRL 0xe410 +#define regBIFL_RAS_LEAF8_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF9_CTRL 0xe411 +#define regBIFL_RAS_LEAF9_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF10_CTRL 0xe412 +#define regBIFL_RAS_LEAF10_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF11_CTRL 0xe413 +#define regBIFL_RAS_LEAF11_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF12_CTRL 0xe414 +#define regBIFL_RAS_LEAF12_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF13_CTRL 0xe415 +#define regBIFL_RAS_LEAF13_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF14_CTRL 0xe416 +#define regBIFL_RAS_LEAF14_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF15_CTRL 0xe417 +#define regBIFL_RAS_LEAF15_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF16_CTRL 0xe418 +#define regBIFL_RAS_LEAF16_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF17_CTRL 0xe419 +#define regBIFL_RAS_LEAF17_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF18_CTRL 0xe41a +#define regBIFL_RAS_LEAF18_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF19_CTRL 0xe41b +#define regBIFL_RAS_LEAF19_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF2_MISC_CTRL 0xe42e +#define regBIFL_RAS_LEAF2_MISC_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF2_MISC_CTRL2 0xe42f +#define regBIFL_RAS_LEAF2_MISC_CTRL2_BASE_IDX 5 +#define regBIFL_RAS_LEAF_NTB_CTRL 0xe430 +#define regBIFL_RAS_LEAF_NTB_CTRL_BASE_IDX 5 +#define regBIFL_RAS_LEAF0_STATUS 0xe431 +#define regBIFL_RAS_LEAF0_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF1_STATUS 0xe432 +#define regBIFL_RAS_LEAF1_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF2_STATUS 0xe433 +#define regBIFL_RAS_LEAF2_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF3_STATUS 0xe434 +#define regBIFL_RAS_LEAF3_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF4_STATUS 0xe435 +#define regBIFL_RAS_LEAF4_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF5_STATUS 0xe436 +#define regBIFL_RAS_LEAF5_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF6_STATUS 0xe437 +#define regBIFL_RAS_LEAF6_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF7_STATUS 0xe438 +#define regBIFL_RAS_LEAF7_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF8_STATUS 0xe439 +#define regBIFL_RAS_LEAF8_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF9_STATUS 0xe43a +#define regBIFL_RAS_LEAF9_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF10_STATUS 0xe43b +#define regBIFL_RAS_LEAF10_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF11_STATUS 0xe43c +#define regBIFL_RAS_LEAF11_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF12_STATUS 0xe43d +#define regBIFL_RAS_LEAF12_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF13_STATUS 0xe43e +#define regBIFL_RAS_LEAF13_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF14_STATUS 0xe43f +#define regBIFL_RAS_LEAF14_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF15_STATUS 0xe440 +#define regBIFL_RAS_LEAF15_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF16_STATUS 0xe441 +#define regBIFL_RAS_LEAF16_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF17_STATUS 0xe442 +#define regBIFL_RAS_LEAF17_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF18_STATUS 0xe443 +#define regBIFL_RAS_LEAF18_STATUS_BASE_IDX 5 +#define regBIFL_RAS_LEAF19_STATUS 0xe444 +#define regBIFL_RAS_LEAF19_STATUS_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP 0xe450 +#define regBIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP 0xe451 +#define regBIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP 0xe452 +#define regBIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP 0xe453 +#define regBIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP 0xe458 +#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP 0xe459 +#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP 0xe45a +#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP 0xe45b +#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP 0xe460 +#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP 0xe461 +#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP 0xe462 +#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP_BASE_IDX 5 +#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP 0xe463 +#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP_BASE_IDX 5 +#define regBIFL_IOHUB_RAS_IH_CNTL 0xe7fe +#define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX 5 +#define regBIFL_RAS_VWR_FROM_IOHUB 0xe7ff +#define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d88 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d89 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d8b +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d8c +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d8d +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d8e +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d8f +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d90 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d91 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d92 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d94 +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d95 +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d96 +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d97 +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d98 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 5 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d99 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d6b +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d6d +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d6e +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d6f +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d70 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d71 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d72 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d74 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d75 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d75 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d75 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d75 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d76 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d76 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d76 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d76 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d77 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d78 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d7a +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d7b +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d7b +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d7b +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d7c +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d7c +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d7c +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d7c +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d7d +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d7d +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d7d +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d7d +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d7e +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d80 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d81 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d82 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d83 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d84 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 +#define regRCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3 0x8d85 +#define regRCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 +#define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac +#define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1 +#define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 +#define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea +#define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 5 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_SYSDEC +// base address: 0x10120000 +#define regBIF_BX1_SYSHUB_INDEX_OVLP 0x8008 +#define regBIF_BX1_SYSHUB_INDEX_OVLP_BASE_IDX 5 +#define regBIF_BX1_SYSHUB_DATA_OVLP 0x8009 +#define regBIF_BX1_SYSHUB_DATA_OVLP_BASE_IDX 5 +#define regBIF_BX1_SYSHUB_INDEX_HI_OVLP 0x800a +#define regBIF_BX1_SYSHUB_INDEX_HI_OVLP_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX 0x800c +#define regBIF_BX1_PCIE_INDEX_BASE_IDX 5 +#define regBIF_BX1_PCIE_DATA 0x800d +#define regBIF_BX1_PCIE_DATA_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX2 0x800e +#define regBIF_BX1_PCIE_INDEX2_BASE_IDX 5 +#define regBIF_BX1_PCIE_DATA2 0x800f +#define regBIF_BX1_PCIE_DATA2_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX_HI 0x8010 +#define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 5 +#define regBIF_BX1_PCIE_INDEX2_HI 0x8011 +#define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 +#define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 +#define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_2 0x804a +#define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_3 0x804b +#define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_0 0x804c +#define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_1 0x804d +#define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_2 0x804e +#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_3 0x804f +#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_4 0x8050 +#define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_5 0x8051 +#define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_6 0x8052 +#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_7 0x8053 +#define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_8 0x8054 +#define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_9 0x8055 +#define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_10 0x8056 +#define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_11 0x8057 +#define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_12 0x8058 +#define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_13 0x8059 +#define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_14 0x805a +#define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_BIOS_SCRATCH_15 0x805b +#define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 5 +#define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 +#define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 +#define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 +#define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_Engine_INTR_CNTL 0x8063 +#define regBIF_BX1_BIF_Engine_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 5 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_0 0x8094 +#define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_1 0x8095 +#define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_2 0x8096 +#define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_3 0x8097 +#define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_4 0x8098 +#define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_5 0x8099 +#define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_6 0x809a +#define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_7 0x809b +#define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_8 0x809c +#define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_9 0x809d +#define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_10 0x809e +#define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_11 0x809f +#define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0 +#define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1 +#define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2 +#define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3 +#define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_0 0x80a4 +#define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_1 0x80a5 +#define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_2 0x80a6 +#define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_3 0x80a7 +#define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_4 0x80a8 +#define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_5 0x80a9 +#define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_6 0x80aa +#define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_7 0x80ab +#define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_8 0x80ac +#define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_9 0x80ad +#define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_10 0x80ae +#define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_11 0x80af +#define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_12 0x80b0 +#define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_13 0x80b1 +#define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_14 0x80b2 +#define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_FW_SCRATCH_15 0x80b3 +#define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4 +#define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5 +#define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6 +#define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7 +#define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8 +#define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9 +#define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba +#define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb +#define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc +#define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd +#define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_14 0x80be +#define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 5 +#define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf +#define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_PF1_MM_INDEX 0x8000 +#define regBIF_BX_PF1_MM_INDEX_BASE_IDX 5 +#define regBIF_BX_PF1_MM_DATA 0x8001 +#define regBIF_BX_PF1_MM_DATA_BASE_IDX 5 +#define regBIF_BX_PF1_MM_INDEX_HI 0x8006 +#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1 +// base address: 0x10120000 +#define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 +#define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 5 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 5 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 5 +#define regBIF_BX1_BUS_CNTL 0x8e07 +#define regBIF_BX1_BUS_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_SCRATCH0 0x8e08 +#define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 5 +#define regBIF_BX1_BIF_SCRATCH1 0x8e09 +#define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 5 +#define regBIF_BX1_BX_RESET_EN 0x8e0d +#define regBIF_BX1_BX_RESET_EN_BASE_IDX 5 +#define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e +#define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 5 +#define regBIF_BX1_BX_RESET_CNTL 0x8e10 +#define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 5 +#define regBIF_BX1_INTERRUPT_CNTL 0x8e11 +#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 5 +#define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 +#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 5 +#define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 +#define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 5 +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 5 +#define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d +#define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_FB_EN 0x8e20 +#define regBIF_BX1_BIF_FB_EN_BASE_IDX 5 +#define regBIF_BX1_BIF_INTR_CNTL 0x8e21 +#define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 5 +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 5 +#define regBIF_BX1_BACO_CNTL 0x8e2b +#define regBIF_BX1_BACO_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_BACO_EXIT_TIME0 0x8e2c +#define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX 5 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER1 0x8e2d +#define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX 5 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER2 0x8e2e +#define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX 5 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER3 0x8e2f +#define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX 5 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER4 0x8e30 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX 5 +#define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 +#define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 5 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 5 +#define regBIF_BX1_VF_REGWR_EN 0x8e44 +#define regBIF_BX1_VF_REGWR_EN_BASE_IDX 5 +#define regBIF_BX1_VF_DOORBELL_EN 0x8e45 +#define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 5 +#define regBIF_BX1_VF_FB_EN 0x8e46 +#define regBIF_BX1_VF_FB_EN_BASE_IDX 5 +#define regBIF_BX1_VF_REGWR_STATUS 0x8e47 +#define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 5 +#define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 +#define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 5 +#define regBIF_BX1_VF_FB_STATUS 0x8e49 +#define regBIF_BX1_VF_FB_STATUS_BASE_IDX 5 +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_CNTL 0x8e4f +#define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_BASE 0x8e50 +#define regBIF_BX1_BIF_RB_BASE_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_RPTR 0x8e51 +#define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_WPTR 0x8e52 +#define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 5 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 5 +#define regBIF_BX1_MAILBOX_INDEX 0x8e55 +#define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 5 +#define regBIF_BX1_BACO_AZ_ENHANCE_CTRL 0x8e61 +#define regBIF_BX1_BACO_AZ_ENHANCE_CTRL_BASE_IDX 5 +#define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62 +#define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 5 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e65 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e66 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e67 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e68 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e69 +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 5 +#define regBIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE 0x8e85 +#define regBIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 5 +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 5 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 5 +#define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 5 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 5 +#define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 5 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 5 +#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP_BASE_IDX 5 +#define regBIF_BX_PF1_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_PF1_PARTITION_MEM_CAP_BASE_IDX 5 +#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS_BASE_IDX 5 +#define regBIF_BX_PF1_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_PF1_PARTITION_MEM_STATUS_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1:1 +// base address: 0x10120000 +#define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20 +#define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21 +#define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP10 0x8d22 +#define regRCC_STRAP2_RCC_BIF_STRAP10_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP11 0x8d23 +#define regRCC_STRAP2_RCC_BIF_STRAP11_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP12 0x8d24 +#define regRCC_STRAP2_RCC_BIF_STRAP12_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP13 0x8d25 +#define regRCC_STRAP2_RCC_BIF_STRAP13_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d26 +#define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d27 +#define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d28 +#define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d29 +#define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d2a +#define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP7 0x8d2b +#define regRCC_STRAP2_RCC_BIF_STRAP7_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP8 0x8d2c +#define regRCC_STRAP2_RCC_BIF_STRAP8_BASE_IDX 5 +#define regRCC_STRAP2_RCC_BIF_STRAP9 0x8d2d +#define regRCC_STRAP2_RCC_BIF_STRAP9_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d2e +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d2f +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d30 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d31 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d32 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d33 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d34 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP15 0x8d35 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP15_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP16 0x8d36 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP16_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP17 0x8d37 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP17_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP18 0x8d38 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP18_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d39 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d3a +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d3b +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d3c +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d3d +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d3e +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d3f +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d40 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d41 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d42 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d43 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d44 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d45 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d46 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d47 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d48 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP19 0x8d49 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP19_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d4a +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP22 0x8d4b +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP22_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP23 0x8d4c +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP23_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP24 0x8d4d +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP24_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d4e +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d4f +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d50 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d51 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d52 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d53 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP1 0x8d54 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP1_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10 0x8d55 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11 0x8d56 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12 0x8d57 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13 0x8d58 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14 0x8d59 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP15 0x8d5a +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP15_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP16 0x8d5b +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP16_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP17 0x8d5c +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP17_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP18 0x8d5d +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP18_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP19 0x8d5e +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP19_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d5f +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d60 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d61 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 0x8d62 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 0x8d63 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d64 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d65 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d66 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d67 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d68 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP8 0x8d69 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP8_BASE_IDX 5 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP9 0x8d6a +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP9_BASE_IDX 5 + + +// addressBlock: nbif0_hpdma0_hpdma_private_hpdma_private_regblk +// base address: 0x10100000 +#define regNBIF_SDP_PERF_COUNTER_2 0x100a +#define regNBIF_SDP_PERF_COUNTER_2_BASE_IDX 5 +#define regNBIF_SHUB_TODET_CLIENT_STATUS3 0x10d1 +#define regNBIF_SHUB_TODET_CLIENT_STATUS3_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0 0x10d5 +#define regBIF_AER_ERR_LOG_DEV0_F0_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf0 0x10d6 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf0_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf1 0x10d7 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf1_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf2 0x10d8 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf2_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf3 0x10d9 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf3_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf4 0x10da +#define regBIF_AER_ERR_LOG_DEV0_F0_vf4_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf5 0x10db +#define regBIF_AER_ERR_LOG_DEV0_F0_vf5_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf6 0x10dc +#define regBIF_AER_ERR_LOG_DEV0_F0_vf6_BASE_IDX 5 +#define regBIF_AER_ERR_LOG_DEV0_F0_vf7 0x10dd +#define regBIF_AER_ERR_LOG_DEV0_F0_vf7_BASE_IDX 5 + + +// addressBlock: nbif0_hphost0_hphost_private_hphost_private_regblk +// base address: 0x10106000 +#define regNBIF_AON_SVA_DISABLE_SAD 0x189a +#define regNBIF_AON_SVA_DISABLE_SAD_BASE_IDX 5 + + +// addressBlock: nbif0_nbif0_gdc_dma_sion_SIONDEC +// base address: 0x1400000 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7400 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7401 +#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7402 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7403 +#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7404 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7405 +#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7406 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7407 +#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0 0x4f7408 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1 0x4f7409 +#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0 0x4f740a +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1 0x4f740b +#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f740c +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f740d +#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f740e +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f740f +#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7410 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7411 +#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7412 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7413 +#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7414 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7415 +#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7416 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7417 +#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7418 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7419 +#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 0x4f741a +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 0x4f741b +#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0 0x4f741c +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1 0x4f741d +#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0 0x4f741e +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1 0x4f741f +#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7420 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7421 +#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7422 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7423 +#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7424 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7425 +#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7426 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7427 +#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 0x4f7428 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 0x4f7429 +#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 0x4f742a +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 0x4f742b +#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 0x4f742c +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 0x4f742d +#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 0x4f742e +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 0x4f742f +#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0 0x4f7430 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1 0x4f7431 +#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0 0x4f7432 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1 0x4f7433 +#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 0x4f7434 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 0x4f7435 +#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 0x4f7436 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 0x4f7437 +#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 0x4f7438 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 0x4f7439 +#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 0x4f743a +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 0x4f743b +#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_DMA_SION_CNTL_REG0 0x4f743c +#define regGDC_DMA_SION_CNTL_REG0_BASE_IDX 3 +#define regGDC_DMA_SION_CNTL_REG1 0x4f743d +#define regGDC_DMA_SION_CNTL_REG1_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_hst_sion_SIONDEC +// base address: 0x1400000 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 0x4f7600 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 0x4f7601 +#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 0x4f7602 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 0x4f7603 +#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 0x4f7604 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 0x4f7605 +#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 0x4f7606 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 0x4f7607 +#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0 0x4f7608 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1 0x4f7609 +#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0 0x4f760a +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1 0x4f760b +#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 0x4f760c +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 0x4f760d +#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 0x4f760e +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 0x4f760f +#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 0x4f7610 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 0x4f7611 +#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 0x4f7612 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 0x4f7613 +#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 0x4f7614 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 0x4f7615 +#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 0x4f7616 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 0x4f7617 +#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 0x4f7618 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 0x4f7619 +#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 0x4f761a +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 0x4f761b +#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0 0x4f761c +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1 0x4f761d +#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0 0x4f761e +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1 0x4f761f +#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 0x4f7620 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 0x4f7621 +#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 0x4f7622 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 0x4f7623 +#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 0x4f7624 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 0x4f7625 +#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 0x4f7626 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 0x4f7627 +#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 3 +#define regGDC_HST_SION_CNTL_REG0 0x4f7628 +#define regGDC_HST_SION_CNTL_REG0_BASE_IDX 3 +#define regGDC_HST_SION_CNTL_REG1 0x4f7629 +#define regGDC_HST_SION_CNTL_REG1_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_GDCDEC +// base address: 0x1400000 +#define regGDC1_NGDC_SDP_PORT_CTRL 0x4f0aa0 +#define regGDC1_NGDC_SDP_PORT_CTRL_BASE_IDX 3 +#define regGDC1_SHUB_REGS_IF_CTL 0x4f0aa1 +#define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 3 +#define regGDC1_NGDC_MGCG_CTRL 0x4f0aa7 +#define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 3 +#define regGDC1_S2A_MISC_CNTL 0x4f0aa8 +#define regGDC1_S2A_MISC_CNTL_BASE_IDX 3 +#define regGDC1_NGDC_MCA_SMN_CTRL0 0x4f0aab +#define regGDC1_NGDC_MCA_SMN_CTRL0_BASE_IDX 3 +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x4f0aac +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 3 +#define regGDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL 0x4f0ab8 +#define regGDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL_BASE_IDX 3 +#define regGDC1_GDC_DMA_SION_PCTRL 0x4f0ab9 +#define regGDC1_GDC_DMA_SION_PCTRL_BASE_IDX 3 +#define regGDC1_NGDC_MP4SDP_CNTL 0x4f0abb +#define regGDC1_NGDC_MP4SDP_CNTL_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF0 0x4f0b13 +#define regGDC1_DOORBELL_VCN_TARGET_VF0_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF1 0x4f0b13 +#define regGDC1_DOORBELL_VCN_TARGET_VF1_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF2 0x4f0b14 +#define regGDC1_DOORBELL_VCN_TARGET_VF2_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF3 0x4f0b14 +#define regGDC1_DOORBELL_VCN_TARGET_VF3_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF4 0x4f0b15 +#define regGDC1_DOORBELL_VCN_TARGET_VF4_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF5 0x4f0b15 +#define regGDC1_DOORBELL_VCN_TARGET_VF5_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF6 0x4f0b16 +#define regGDC1_DOORBELL_VCN_TARGET_VF6_BASE_IDX 3 +#define regGDC1_DOORBELL_VCN_TARGET_VF7 0x4f0b16 +#define regGDC1_DOORBELL_VCN_TARGET_VF7_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_PF 0x4f0b17 +#define regGDC1_DOORBELL_ACCESS_EN_PF_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF0 0x4f0b17 +#define regGDC1_DOORBELL_ACCESS_EN_VF0_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF1 0x4f0b18 +#define regGDC1_DOORBELL_ACCESS_EN_VF1_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF2 0x4f0b18 +#define regGDC1_DOORBELL_ACCESS_EN_VF2_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF3 0x4f0b19 +#define regGDC1_DOORBELL_ACCESS_EN_VF3_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF4 0x4f0b19 +#define regGDC1_DOORBELL_ACCESS_EN_VF4_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF5 0x4f0b1a +#define regGDC1_DOORBELL_ACCESS_EN_VF5_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF6 0x4f0b1a +#define regGDC1_DOORBELL_ACCESS_EN_VF6_BASE_IDX 3 +#define regGDC1_DOORBELL_ACCESS_EN_VF7 0x4f0b1b +#define regGDC1_DOORBELL_ACCESS_EN_VF7_BASE_IDX 3 +#define regGDC1_NGDC_CNDI_BUS_PORT_CTRL 0x4f0b1c +#define regGDC1_NGDC_CNDI_BUS_PORT_CTRL_BASE_IDX 3 +#define regGDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL 0x4f0b1d +#define regGDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_ras_gdc_ras_regblk +// base address: 0x1400000 +#define regGDCSOC_ERR_RSP_CNTL 0x4f5c00 +#define regGDCSOC_ERR_RSP_CNTL_BASE_IDX 3 +#define regGDCSOC_RAS_CENTRAL_STATUS 0x4f5c10 +#define regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF0_CTRL 0x4f5c20 +#define regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF1_CTRL 0x4f5c21 +#define regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF2_CTRL 0x4f5c22 +#define regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF3_CTRL 0x4f5c23 +#define regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF4_CTRL 0x4f5c24 +#define regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF5_CTRL 0x4f5c25 +#define regGDCSOC_RAS_LEAF5_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF6_CTRL 0x4f5c26 +#define regGDCSOC_RAS_LEAF6_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF7_CTRL 0x4f5c27 +#define regGDCSOC_RAS_LEAF7_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF8_CTRL 0x4f5c28 +#define regGDCSOC_RAS_LEAF8_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF9_CTRL 0x4f5c29 +#define regGDCSOC_RAS_LEAF9_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF10_CTRL 0x4f5c2a +#define regGDCSOC_RAS_LEAF10_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF11_CTRL 0x4f5c2b +#define regGDCSOC_RAS_LEAF11_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF12_CTRL 0x4f5c2c +#define regGDCSOC_RAS_LEAF12_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF13_CTRL 0x4f5c2d +#define regGDCSOC_RAS_LEAF13_CTRL_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF0_STATUS 0x4f5c30 +#define regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF1_STATUS 0x4f5c31 +#define regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF2_STATUS 0x4f5c32 +#define regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF3_STATUS 0x4f5c33 +#define regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF4_STATUS 0x4f5c34 +#define regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF5_STATUS 0x4f5c35 +#define regGDCSOC_RAS_LEAF5_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF6_STATUS 0x4f5c36 +#define regGDCSOC_RAS_LEAF6_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF7_STATUS 0x4f5c37 +#define regGDCSOC_RAS_LEAF7_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF8_STATUS 0x4f5c38 +#define regGDCSOC_RAS_LEAF8_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF9_STATUS 0x4f5c39 +#define regGDCSOC_RAS_LEAF9_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF10_STATUS 0x4f5c3a +#define regGDCSOC_RAS_LEAF10_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF11_STATUS 0x4f5c3b +#define regGDCSOC_RAS_LEAF11_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF12_STATUS 0x4f5c3c +#define regGDCSOC_RAS_LEAF12_STATUS_BASE_IDX 3 +#define regGDCSOC_RAS_LEAF13_STATUS 0x4f5c3d +#define regGDCSOC_RAS_LEAF13_STATUS_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_sec_GDCSEC_DEC +// base address: 0x1400000 +#define regGDC_SEC_MCA_SMN_CTRL0 0x4f7001 +#define regGDC_SEC_MCA_SMN_CTRL0_BASE_IDX 3 +#define regGDC_SEC_MCA_SMN_CTRL1 0x4f7002 +#define regGDC_SEC_MCA_SMN_CTRL1_BASE_IDX 3 +#define regXCD_DOORBELL_FENCE 0x4f7003 +#define regXCD_DOORBELL_FENCE_BASE_IDX 3 +#define regSHUB_PWRBRK_DEGLITCH 0x4f7004 +#define regSHUB_PWRBRK_DEGLITCH_BASE_IDX 3 +#define regSHUB_DIE_CTRL 0x4f7005 +#define regSHUB_DIE_CTRL_BASE_IDX 3 +#define regGDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL 0x4f700a +#define regGDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL_BASE_IDX 3 +#define regXCD_DOORBELL_FENCE_1 0x4f700b +#define regXCD_DOORBELL_FENCE_1_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_0 0x4f700c +#define regNGDC_CNDI_DOORBELL_REQUSER_0_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_1 0x4f700d +#define regNGDC_CNDI_DOORBELL_REQUSER_1_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_2 0x4f700e +#define regNGDC_CNDI_DOORBELL_REQUSER_2_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_3 0x4f700f +#define regNGDC_CNDI_DOORBELL_REQUSER_3_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_4 0x4f7010 +#define regNGDC_CNDI_DOORBELL_REQUSER_4_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQUSER_5 0x4f7011 +#define regNGDC_CNDI_DOORBELL_REQUSER_5_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0 0x4f7012 +#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0_BASE_IDX 3 +#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1 0x4f7013 +#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_rst_GDCRST_DEC +// base address: 0x1400000 +#define regSHUB_PF_FLR_RST 0x4f7800 +#define regSHUB_PF_FLR_RST_BASE_IDX 3 +#define regSHUB_GFX_DRV_VPU_RST 0x4f7801 +#define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 3 +#define regSHUB_LINK_RESET 0x4f7802 +#define regSHUB_LINK_RESET_BASE_IDX 3 +#define regSHUB_HST_NIC400_SW_CTRL_RESET 0x4f7803 +#define regSHUB_HST_NIC400_SW_CTRL_RESET_BASE_IDX 3 +#define regSHUB_DEV0_PF0_VF_FLR_RST 0x4f7808 +#define regSHUB_DEV0_PF0_VF_FLR_RST_BASE_IDX 3 +#define regSHUB_DEV0_PF1_VF_FLR_RST 0x4f7809 +#define regSHUB_DEV0_PF1_VF_FLR_RST_BASE_IDX 3 +#define regSHUB_HARD_RST_CTRL 0x4f7810 +#define regSHUB_HARD_RST_CTRL_BASE_IDX 3 +#define regSHUB_SOFT_RST_CTRL 0x4f7811 +#define regSHUB_SOFT_RST_CTRL_BASE_IDX 3 +#define regSHUB_SDP_PORT_RST 0x4f7812 +#define regSHUB_SDP_PORT_RST_BASE_IDX 3 +#define regSHUB_RST_MISC_TRL 0x4f7813 +#define regSHUB_RST_MISC_TRL_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC +// base address: 0x1400000 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL 0x4f0aeb +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1 0x4f0aec +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL 0x4f0aed +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1 0x4f0aee +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL 0x4f0aef +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1 0x4f0af0 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL 0x4f0af1 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1 0x4f0af2 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL 0x4f0af3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1 0x4f0af4 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL 0x4f0af5 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1 0x4f0af6 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL 0x4f0af7 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1 0x4f0af8 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL 0x4f0af9 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1 0x4f0afa +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL 0x4f0afb +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1 0x4f0afc +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL 0x4f0afd +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1 0x4f0afe +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL 0x4f0aff +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1 0x4f0b00 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL 0x4f0b01 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1 0x4f0b02 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL 0x4f0b03 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1 0x4f0b04 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL 0x4f0b05 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1 0x4f0b06 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL 0x4f0b07 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1 0x4f0b08 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL 0x4f0b09 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1 0x4f0b0a +#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1_BASE_IDX 3 +#define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG 0x4f0b0b +#define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 3 +#define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS 0x4f0b0c +#define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_misc_GDCMISC_DEC +// base address: 0x1400000 +#define regGDC_DMA_SION_CRED_RST 0x4f3401 +#define regGDC_DMA_SION_CRED_RST_BASE_IDX 3 +#define regGDC_HST_SION_PER_SDP_PORT_RST 0x4f3402 +#define regGDC_HST_SION_PER_SDP_PORT_RST_BASE_IDX 3 +#define regGDC_HST_SION_PER_SDP_CNTL_REG1 0x4f3403 +#define regGDC_HST_SION_PER_SDP_CNTL_REG1_BASE_IDX 3 +#define regGDC_HST_AXI_STALL_FOR_FLUSH 0x4f3404 +#define regGDC_HST_AXI_STALL_FOR_FLUSH_BASE_IDX 3 +#define regSYSHUB_SDP_DEBUG_COUNTER_CTRL 0x4f3405 +#define regSYSHUB_SDP_DEBUG_COUNTER_CTRL_BASE_IDX 3 +#define regNBIF_PWRBRK_IN_PAD_CNTL 0x4f3801 +#define regNBIF_PWRBRK_IN_PAD_CNTL_BASE_IDX 3 +#define regNBIF_PWRBRK_OUT_PAD_CNTL 0x4f3802 +#define regNBIF_PWRBRK_OUT_PAD_CNTL_BASE_IDX 3 +#define regSHUB_OOB_CRUSH_DUMP_CTRL 0x4f3803 +#define regSHUB_OOB_CRUSH_DUMP_CTRL_BASE_IDX 3 +#define regSHUB_MP_ERREVENT_MASK_CTRL 0x4f3804 +#define regSHUB_MP_ERREVENT_MASK_CTRL_BASE_IDX 3 +#define regSHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL 0x4f3805 +#define regSHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL_BASE_IDX 3 +#define regSHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL 0x4f3806 +#define regSHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_sec_misc_GDCSEC_MISC_DEC +// base address: 0x1400000 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI 0x4f2883 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI 0x4f2884 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI 0x4f2885 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI 0x4f2886 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI 0x4f2887 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI 0x4f2888 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI 0x4f2889 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI 0x4f288a +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI 0x4f288b +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI 0x4f288c +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI 0x4f288d +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI 0x4f288e +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI 0x4f288f +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI 0x4f2890 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI 0x4f2891 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP 0x4f2898 +#define regGDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP 0x4f2899 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP 0x4f289a +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI 0x4f28a7 +#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI 0x4f28a8 +#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI 0x4f28a9 +#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_POISON_DBUG_CTRL 0x4f2c00 +#define regGDCSOC_SEC_RAS_POISON_DBUG_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_PARITY_DBUG_CTRL 0x4f2c01 +#define regGDCSOC_SEC_RAS_PARITY_DBUG_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL 0x4f2c02 +#define regGDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL 0x4f2c03 +#define regGDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL 0x4f2c04 +#define regGDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_RESPONSE_DROP_CTRL 0x4f2c05 +#define regGDCSOC_SEC_RAS_RESPONSE_DROP_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL 0x4f2c06 +#define regGDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL 0x4f2c07 +#define regGDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL 0x4f2c08 +#define regGDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL 0x4f2c09 +#define regGDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL 0x4f2c0a +#define regGDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL 0x4f2c0b +#define regGDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL 0x4f2c0c +#define regGDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL 0x4f2c0d +#define regGDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL 0x4f2c0e +#define regGDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL 0x4f2c0f +#define regGDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL 0x4f2c10 +#define regGDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL 0x4f2c11 +#define regGDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL 0x4f2c12 +#define regGDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL 0x4f2c13 +#define regGDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL 0x4f2c14 +#define regGDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL 0x4f2c15 +#define regGDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL 0x4f2c16 +#define regGDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL 0x4f2c17 +#define regGDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL 0x4f2c18 +#define regGDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL 0x4f2c19 +#define regGDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL 0x4f2c1a +#define regGDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL 0x4f2c1b +#define regGDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL 0x4f2c1c +#define regGDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL 0x4f2c1d +#define regGDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL 0x4f2c1e +#define regGDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL 0x4f2c1f +#define regGDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL 0x4f2c20 +#define regGDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL_BASE_IDX 3 +#define regGDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL 0x4f2c21 +#define regGDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_gdc_a2s_GDCA2S_DEC +// base address: 0x1400000 +#define regA2S_CNTL_SW0 0x4f0c40 +#define regA2S_CNTL_SW0_BASE_IDX 3 +#define regA2S_CNTL_SW1 0x4f0c41 +#define regA2S_CNTL_SW1_BASE_IDX 3 +#define regA2S_CNTL_SW2 0x4f0c42 +#define regA2S_CNTL_SW2_BASE_IDX 3 +#define regA2S_CNTL_SW3 0x4f0c43 +#define regA2S_CNTL_SW3_BASE_IDX 3 +#define regA2S_CNTL_SW4 0x4f0c44 +#define regA2S_CNTL_SW4_BASE_IDX 3 +#define regA2S_CNTL_SW5 0x4f0c45 +#define regA2S_CNTL_SW5_BASE_IDX 3 +#define regA2S_CNTL_2_SW0 0x4f0c50 +#define regA2S_CNTL_2_SW0_BASE_IDX 3 +#define regA2S_CNTL_2_SW1 0x4f0c51 +#define regA2S_CNTL_2_SW1_BASE_IDX 3 +#define regA2S_CNTL_2_SW2 0x4f0c52 +#define regA2S_CNTL_2_SW2_BASE_IDX 3 +#define regA2S_CNTL_2_SW3 0x4f0c53 +#define regA2S_CNTL_2_SW3_BASE_IDX 3 +#define regA2S_CNTL_2_SW4 0x4f0c54 +#define regA2S_CNTL_2_SW4_BASE_IDX 3 +#define regA2S_CNTL_2_SW5 0x4f0c55 +#define regA2S_CNTL_2_SW5_BASE_IDX 3 +#define regA2S_WRSIZEFULL_SUPPORT_DISABLE 0x4f0c5c +#define regA2S_WRSIZEFULL_SUPPORT_DISABLE_BASE_IDX 3 +#define regROUTING_TABLE_CNTL 0x4f0c60 +#define regROUTING_TABLE_CNTL_BASE_IDX 3 +#define regROUTING_TABLE_DATA0 0x4f0c61 +#define regROUTING_TABLE_DATA0_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC0 0x4f0c68 +#define regA2S_ARB_CONTROL_FOR_VC0_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC1 0x4f0c69 +#define regA2S_ARB_CONTROL_FOR_VC1_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC2 0x4f0c6a +#define regA2S_ARB_CONTROL_FOR_VC2_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC3 0x4f0c6b +#define regA2S_ARB_CONTROL_FOR_VC3_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC4 0x4f0c6c +#define regA2S_ARB_CONTROL_FOR_VC4_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC5 0x4f0c6d +#define regA2S_ARB_CONTROL_FOR_VC5_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC6 0x4f0c6e +#define regA2S_ARB_CONTROL_FOR_VC6_BASE_IDX 3 +#define regA2S_ARB_CONTROL_FOR_VC7 0x4f0c6f +#define regA2S_ARB_CONTROL_FOR_VC7_BASE_IDX 3 +#define regA2S_RW_ARB_CNTL 0x4f0c70 +#define regA2S_RW_ARB_CNTL_BASE_IDX 3 +#define regA2S_REQ_RSP_TAG_CNTL 0x4f0c71 +#define regA2S_REQ_RSP_TAG_CNTL_BASE_IDX 3 +#define regA2S_MISC_CNTL 0x4f0c72 +#define regA2S_MISC_CNTL_BASE_IDX 3 +#define regA2S_TAG_ALLOC_0 0x4f0c74 +#define regA2S_TAG_ALLOC_0_BASE_IDX 3 +#define regA2S_TAG_ALLOC_1 0x4f0c75 +#define regA2S_TAG_ALLOC_1_BASE_IDX 3 +#define regA2S_TAG_ALLOC_2 0x4f0c76 +#define regA2S_TAG_ALLOC_2_BASE_IDX 3 +#define regA2S_TAG_ALLOC_3 0x4f0c77 +#define regA2S_TAG_ALLOC_3_BASE_IDX 3 +#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_0 0x4f0c78 +#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_0_BASE_IDX 3 +#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_1 0x4f0c79 +#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_1_BASE_IDX 3 +#define regGDC_SDP_PORT_CTRL 0x4f0c7c +#define regGDC_SDP_PORT_CTRL_BASE_IDX 3 +#define regGDC_A2S_SDP_REQ_POOLCRED_ALLOC 0x4f0c7d +#define regGDC_A2S_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 3 +#define regGDC_A2S_SDP_DAT_POOLCRED_ALLOC 0x4f0c7e +#define regGDC_A2S_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 3 +#define regSHUB_PERF_COMMON_COUNTER 0x4f0c80 +#define regSHUB_PERF_COMMON_COUNTER_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_FSM 0x4f0c81 +#define regSHUB_A2S_PERF_CNT_FSM_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_RSP_UNITID 0x4f0c83 +#define regSHUB_A2S_PERF_CNT_RSP_UNITID_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_0_CTRL 0x4f0c84 +#define regSHUB_A2S_PERF_CNT_0_CTRL_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_1_CTRL 0x4f0c85 +#define regSHUB_A2S_PERF_CNT_1_CTRL_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_2_CTRL 0x4f0c86 +#define regSHUB_A2S_PERF_CNT_2_CTRL_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_3_CTRL 0x4f0c87 +#define regSHUB_A2S_PERF_CNT_3_CTRL_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_0_VALUE_L32BIT 0x4f0c88 +#define regSHUB_A2S_PERF_CNT_0_VALUE_L32BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_0_VALUE_H16BIT 0x4f0c89 +#define regSHUB_A2S_PERF_CNT_0_VALUE_H16BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_1_VALUE_L32BIT 0x4f0c8a +#define regSHUB_A2S_PERF_CNT_1_VALUE_L32BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_1_VALUE_H16BIT 0x4f0c8b +#define regSHUB_A2S_PERF_CNT_1_VALUE_H16BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_2_VALUE_L32BIT 0x4f0c8c +#define regSHUB_A2S_PERF_CNT_2_VALUE_L32BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_2_VALUE_H16BIT 0x4f0c8d +#define regSHUB_A2S_PERF_CNT_2_VALUE_H16BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_3_VALUE_L32BIT 0x4f0c8e +#define regSHUB_A2S_PERF_CNT_3_VALUE_L32BIT_BASE_IDX 3 +#define regSHUB_A2S_PERF_CNT_3_VALUE_H16BIT 0x4f0c8f +#define regSHUB_A2S_PERF_CNT_3_VALUE_H16BIT_BASE_IDX 3 +#define regSHUB_TO_ALL_PERF_COUNTER 0x4f0c90 +#define regSHUB_TO_ALL_PERF_COUNTER_BASE_IDX 3 +#define regGDC_PERF_COUNTER_RESET 0x4f0c91 +#define regGDC_PERF_COUNTER_RESET_BASE_IDX 3 +#define regSHUB_COM_COUNT_VALUE 0x4f0c92 +#define regSHUB_COM_COUNT_VALUE_BASE_IDX 3 +#define regA2S_QUEUE_FIFO_ARB_CNTL 0x4f0c93 +#define regA2S_QUEUE_FIFO_ARB_CNTL_BASE_IDX 3 +#define regWR_A2S_RSP_WRR_CNTL 0x4f0c94 +#define regWR_A2S_RSP_WRR_CNTL_BASE_IDX 3 +#define regRD_A2S_RSP_WRR_CNTL 0x4f0c95 +#define regRD_A2S_RSP_WRR_CNTL_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdirect +// base address: 0x1400000 +#define regSYSHUB_DS_CTRL_SOCCLK 0x4f3c00 +#define regSYSHUB_DS_CTRL_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_CTRL2_SOCCLK 0x4f3c01 +#define regSYSHUB_DS_CTRL2_SOCCLK_BASE_IDX 3 +#define regSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x4f3c02 +#define regSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_BASE_IDX 3 +#define regSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x4f3c03 +#define regSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_BASE_IDX 3 +#define regSYSHUB_MGCG_CTRL_SOCCLK 0x4f3c08 +#define regSYSHUB_MGCG_CTRL_SOCCLK_BASE_IDX 3 +#define regSYSHUB_SCRATCH_SOCCLK 0x4f3c0a +#define regSYSHUB_SCRATCH_SOCCLK_BASE_IDX 3 +#define regSYSHUB_HANG_CNTL_SOCCLK 0x4f3c0c +#define regSYSHUB_HANG_CNTL_SOCCLK_BASE_IDX 3 +#define regSYSHUB_SELECT_SOCCLK 0x4f3c0d +#define regSYSHUB_SELECT_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_AW_READY_SOCCLK 0x4f3c11 +#define regSYSHUB_DS_AW_READY_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_AR_READY_SOCCLK 0x4f3c12 +#define regSYSHUB_DS_AR_READY_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_W_READY_SOCCLK 0x4f3c13 +#define regSYSHUB_DS_W_READY_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_R_READY_SOCCLK 0x4f3c14 +#define regSYSHUB_DS_R_READY_SOCCLK_BASE_IDX 3 +#define regSYSHUB_DS_B_READY_SOCCLK 0x4f3c15 +#define regSYSHUB_DS_B_READY_SOCCLK_BASE_IDX 3 +#define regSYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK 0x4f3c16 +#define regSYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK_BASE_IDX 3 +#define regDMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x4f3e00 +#define regDMA_CLK0_SW0_SYSHUB_QOS_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x4f3e01 +#define regDMA_CLK0_SW1_SYSHUB_QOS_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW0_CL0_CNTL 0x4f3e40 +#define regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW0_CL1_CNTL 0x4f3e41 +#define regDMA_CLK0_SW0_CL1_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW1_CL0_CNTL 0x4f3e60 +#define regDMA_CLK0_SW1_CL0_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW1_CL1_CNTL 0x4f3e61 +#define regDMA_CLK0_SW1_CL1_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW2_CL0_CNTL 0x4f3e80 +#define regDMA_CLK0_SW2_CL0_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW3_CL0_CNTL 0x4f3ea0 +#define regDMA_CLK0_SW3_CL0_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW4_CL0_CNTL 0x4f3ec0 +#define regDMA_CLK0_SW4_CL0_CNTL_BASE_IDX 3 +#define regDMA_CLK0_SW5_CL0_CNTL 0x4f3ee0 +#define regDMA_CLK0_SW5_CL0_CNTL_BASE_IDX 3 +#define regNIC400_0_AMIB_0_FN_MOD_BM_ISS 0x4f7c02 +#define regNIC400_0_AMIB_0_FN_MOD_BM_ISS_BASE_IDX 3 +#define regNIC400_0_AMIB_0_FN_MOD 0x4f7c42 +#define regNIC400_0_AMIB_0_FN_MOD_BASE_IDX 3 +#define regNIC400_0_ASIB_0_FN_MOD 0x4f8842 +#define regNIC400_0_ASIB_0_FN_MOD_BASE_IDX 3 +#define regNIC400_0_ASIB_0_QOS_CNTL 0x4f8843 +#define regNIC400_0_ASIB_0_QOS_CNTL_BASE_IDX 3 +#define regNIC400_0_ASIB_0_MAX_OT 0x4f8844 +#define regNIC400_0_ASIB_0_MAX_OT_BASE_IDX 3 +#define regNIC400_0_ASIB_0_MAX_COMB_OT 0x4f8845 +#define regNIC400_0_ASIB_0_MAX_COMB_OT_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AW_P 0x4f8846 +#define regNIC400_0_ASIB_0_AW_P_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AW_B 0x4f8847 +#define regNIC400_0_ASIB_0_AW_B_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AW_R 0x4f8848 +#define regNIC400_0_ASIB_0_AW_R_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AR_P 0x4f8849 +#define regNIC400_0_ASIB_0_AR_P_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AR_B 0x4f884a +#define regNIC400_0_ASIB_0_AR_B_BASE_IDX 3 +#define regNIC400_0_ASIB_0_AR_R 0x4f884b +#define regNIC400_0_ASIB_0_AR_R_BASE_IDX 3 +#define regNIC400_0_ASIB_0_TARGET_FC 0x4f884c +#define regNIC400_0_ASIB_0_TARGET_FC_BASE_IDX 3 +#define regNIC400_0_ASIB_0_KI_FC 0x4f884d +#define regNIC400_0_ASIB_0_KI_FC_BASE_IDX 3 +#define regNIC400_0_ASIB_0_QOS_RANGE 0x4f884e +#define regNIC400_0_ASIB_0_QOS_RANGE_BASE_IDX 3 +#define regNIC400_0_ASIB_1_FN_MOD 0x4f8c42 +#define regNIC400_0_ASIB_1_FN_MOD_BASE_IDX 3 +#define regNIC400_0_ASIB_1_QOS_CNTL 0x4f8c43 +#define regNIC400_0_ASIB_1_QOS_CNTL_BASE_IDX 3 +#define regNIC400_0_ASIB_1_MAX_OT 0x4f8c44 +#define regNIC400_0_ASIB_1_MAX_OT_BASE_IDX 3 +#define regNIC400_0_ASIB_1_MAX_COMB_OT 0x4f8c45 +#define regNIC400_0_ASIB_1_MAX_COMB_OT_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AW_P 0x4f8c46 +#define regNIC400_0_ASIB_1_AW_P_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AW_B 0x4f8c47 +#define regNIC400_0_ASIB_1_AW_B_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AW_R 0x4f8c48 +#define regNIC400_0_ASIB_1_AW_R_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AR_P 0x4f8c49 +#define regNIC400_0_ASIB_1_AR_P_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AR_B 0x4f8c4a +#define regNIC400_0_ASIB_1_AR_B_BASE_IDX 3 +#define regNIC400_0_ASIB_1_AR_R 0x4f8c4b +#define regNIC400_0_ASIB_1_AR_R_BASE_IDX 3 +#define regNIC400_0_ASIB_1_TARGET_FC 0x4f8c4c +#define regNIC400_0_ASIB_1_TARGET_FC_BASE_IDX 3 +#define regNIC400_0_ASIB_1_KI_FC 0x4f8c4d +#define regNIC400_0_ASIB_1_KI_FC_BASE_IDX 3 +#define regNIC400_0_ASIB_1_QOS_RANGE 0x4f8c4e +#define regNIC400_0_ASIB_1_QOS_RANGE_BASE_IDX 3 +#define regNIC400_0_IB_0_FN_MOD 0x4fb842 +#define regNIC400_0_IB_0_FN_MOD_BASE_IDX 3 +#define regNIC400_1_AMIB_0_FN_MOD_BM_ISS 0x4fbc02 +#define regNIC400_1_AMIB_0_FN_MOD_BM_ISS_BASE_IDX 3 +#define regNIC400_1_AMIB_0_FN_MOD 0x4fbc42 +#define regNIC400_1_AMIB_0_FN_MOD_BASE_IDX 3 +#define regNIC400_1_ASIB_0_FN_MOD 0x4fc842 +#define regNIC400_1_ASIB_0_FN_MOD_BASE_IDX 3 +#define regNIC400_1_ASIB_0_QOS_CNTL 0x4fc843 +#define regNIC400_1_ASIB_0_QOS_CNTL_BASE_IDX 3 +#define regNIC400_1_ASIB_0_MAX_OT 0x4fc844 +#define regNIC400_1_ASIB_0_MAX_OT_BASE_IDX 3 +#define regNIC400_1_ASIB_0_MAX_COMB_OT 0x4fc845 +#define regNIC400_1_ASIB_0_MAX_COMB_OT_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AW_P 0x4fc846 +#define regNIC400_1_ASIB_0_AW_P_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AW_B 0x4fc847 +#define regNIC400_1_ASIB_0_AW_B_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AW_R 0x4fc848 +#define regNIC400_1_ASIB_0_AW_R_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AR_P 0x4fc849 +#define regNIC400_1_ASIB_0_AR_P_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AR_B 0x4fc84a +#define regNIC400_1_ASIB_0_AR_B_BASE_IDX 3 +#define regNIC400_1_ASIB_0_AR_R 0x4fc84b +#define regNIC400_1_ASIB_0_AR_R_BASE_IDX 3 +#define regNIC400_1_ASIB_0_TARGET_FC 0x4fc84c +#define regNIC400_1_ASIB_0_TARGET_FC_BASE_IDX 3 +#define regNIC400_1_ASIB_0_KI_FC 0x4fc84d +#define regNIC400_1_ASIB_0_KI_FC_BASE_IDX 3 +#define regNIC400_1_ASIB_0_QOS_RANGE 0x4fc84e +#define regNIC400_1_ASIB_0_QOS_RANGE_BASE_IDX 3 +#define regNIC400_1_ASIB_1_FN_MOD 0x4fcc42 +#define regNIC400_1_ASIB_1_FN_MOD_BASE_IDX 3 +#define regNIC400_1_ASIB_1_QOS_CNTL 0x4fcc43 +#define regNIC400_1_ASIB_1_QOS_CNTL_BASE_IDX 3 +#define regNIC400_1_ASIB_1_MAX_OT 0x4fcc44 +#define regNIC400_1_ASIB_1_MAX_OT_BASE_IDX 3 +#define regNIC400_1_ASIB_1_MAX_COMB_OT 0x4fcc45 +#define regNIC400_1_ASIB_1_MAX_COMB_OT_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AW_P 0x4fcc46 +#define regNIC400_1_ASIB_1_AW_P_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AW_B 0x4fcc47 +#define regNIC400_1_ASIB_1_AW_B_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AW_R 0x4fcc48 +#define regNIC400_1_ASIB_1_AW_R_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AR_P 0x4fcc49 +#define regNIC400_1_ASIB_1_AR_P_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AR_B 0x4fcc4a +#define regNIC400_1_ASIB_1_AR_B_BASE_IDX 3 +#define regNIC400_1_ASIB_1_AR_R 0x4fcc4b +#define regNIC400_1_ASIB_1_AR_R_BASE_IDX 3 +#define regNIC400_1_ASIB_1_TARGET_FC 0x4fcc4c +#define regNIC400_1_ASIB_1_TARGET_FC_BASE_IDX 3 +#define regNIC400_1_ASIB_1_KI_FC 0x4fcc4d +#define regNIC400_1_ASIB_1_KI_FC_BASE_IDX 3 +#define regNIC400_1_ASIB_1_QOS_RANGE 0x4fcc4e +#define regNIC400_1_ASIB_1_QOS_RANGE_BASE_IDX 3 +#define regNIC400_1_IB_0_FN_MOD 0x4ff842 +#define regNIC400_1_IB_0_FN_MOD_BASE_IDX 3 + + +// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdec +// base address: 0x0 +#define regSYSHUB_INDEX 0x0008 +#define regSYSHUB_INDEX_BASE_IDX 0 +#define regSYSHUB_DATA 0x0009 +#define regSYSHUB_DATA_BASE_IDX 0 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_RC_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_RC_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_RC_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_RC_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_RC_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_RC_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_RC_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_RC_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_RC_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_RC_HEADER 0x000e +#define cfgBIF_CFG_DEV0_RC_BIST 0x000f +#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_2 0x0014 +#define cfgSUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgIO_BASE_LIMIT 0x001c +#define cfgSECONDARY_STATUS 0x001e +#define cfgMEM_BASE_LIMIT 0x0020 +#define cfgPREF_BASE_LIMIT 0x0024 +#define cfgPREF_BASE_UPPER 0x0028 +#define cfgPREF_LIMIT_UPPER 0x002c +#define cfgIO_BASE_LIMIT_HI 0x0030 +#define cfgBIF_CFG_DEV0_RC_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR 0x0038 +#define cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN 0x003d +#define cfgIRQ_BRIDGE_CNTL 0x003e +#define cfgEXT_BRIDGE_CNTL 0x0040 +#define cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_RC_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST 0x0058 +#define cfgBIF_CFG_DEV0_RC_PCIE_CAP 0x005a +#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP 0x005c +#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL 0x0060 +#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS 0x0062 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP 0x0064 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL 0x0068 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS 0x006a +#define cfgSLOT_CAP 0x006c +#define cfgSLOT_CNTL 0x0070 +#define cfgSLOT_STATUS 0x0072 +#define cfgROOT_CNTL 0x0074 +#define cfgROOT_CAP 0x0076 +#define cfgROOT_STATUS 0x0078 +#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP2 0x007c +#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2 0x0080 +#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2 0x0082 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP2 0x0084 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL2 0x0088 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS2 0x008a +#define cfgSLOT_CAP2 0x008c +#define cfgSLOT_CNTL2 0x0090 +#define cfgSLOT_STATUS2 0x0092 +#define cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgSSID_CAP_LIST 0x00c0 +#define cfgSSID_CAP 0x00c4 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 0x0114 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS 0x0118 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL 0x011c +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL 0x011e +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL 0x0120 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL 0x0122 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL 0x0126 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL 0x0128 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL 0x012a +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL 0x012c +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL 0x012e +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL 0x0132 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL 0x0134 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL 0x0136 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL 0x0138 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL 0x013a +#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST 0x01b8 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT 0x01bc +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT 0x01c0 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT 0x01c4 +#define cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x01c8 +#define cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 0x01cc +#define cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 0x01d0 +#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT 0x01d8 +#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT 0x01d9 +#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT 0x01da +#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT 0x01db +#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT 0x01dc +#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT 0x01dd +#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT 0x01de +#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT 0x01df +#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT 0x01e0 +#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT 0x01e1 +#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT 0x01e2 +#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT 0x01e3 +#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT 0x01e4 +#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT 0x01e5 +#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT 0x01e6 +#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT 0x01e7 +#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST 0x01f8 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP_32GT 0x01fc +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_32GT 0x0200 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_32GT 0x0204 +#define cfgBIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1 0x0208 +#define cfgBIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2 0x020c +#define cfgBIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1 0x0210 +#define cfgBIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2 0x0214 +#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT 0x0218 +#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT 0x0219 +#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT 0x021a +#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT 0x021b +#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT 0x021c +#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT 0x021d +#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT 0x021e +#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT 0x021f +#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT 0x0220 +#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT 0x0221 +#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT 0x0222 +#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT 0x0223 +#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT 0x0224 +#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT 0x0225 +#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT 0x0226 +#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT 0x0227 +#define cfgBIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST 0x0238 +#define cfgBIF_CFG_DEV0_RC_AP_CAP 0x023c +#define cfgBIF_CFG_DEV0_RC_AP_CNTL 0x0240 +#define cfgBIF_CFG_DEV0_RC_AP_DATA1 0x0244 +#define cfgBIF_CFG_DEV0_RC_AP_DATA2 0x0248 +#define cfgBIF_CFG_DEV0_RC_AP_SEL_EN_MASK 0x024c +#define cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP 0x0254 +#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS 0x0256 +#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL 0x0258 +#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS 0x025a +#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL 0x025c +#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS 0x025e +#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL 0x0260 +#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS 0x0262 +#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL 0x0264 +#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS 0x0266 +#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL 0x0268 +#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS 0x026a +#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL 0x026c +#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS 0x026e +#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL 0x0270 +#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS 0x0272 +#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL 0x0274 +#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS 0x0276 +#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL 0x0278 +#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS 0x027a +#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL 0x027c +#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS 0x027e +#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS 0x0282 +#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS 0x0286 +#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS 0x028a +#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL 0x028c +#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS 0x028e +#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS 0x0292 +#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS 0x0296 +#define cfgBIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST 0x0404 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 0x0408 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 0x040c +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL 0x0410 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS 0x0412 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP 0x0414 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL 0x0418 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS 0x041e +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP 0x0420 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL 0x0424 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS 0x042a +#define cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST 0x0430 +#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP 0x0434 +#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS 0x0438 +#define cfgBIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3 0x062c +#define cfgPCIE_ROOT_ERR_CMD 0x0630 +#define cfgPCIE_ROOT_ERR_STATUS 0x0634 +#define cfgPCIE_ERR_SRC_ID 0x0638 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0664 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 0x0668 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 0x066c +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST 0x06dc +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP 0x06e0 +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL 0x06e2 +#define cfgBIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_RC_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_RC_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST 0x0e00 +#define cfgBIF_CFG_DEV0_RC_IDE_CAP 0x0e04 +#define cfgBIF_CFG_DEV0_RC_IDE_CNTL 0x0e08 +#define cfgBIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL 0x0e0c +#define cfgBIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS 0x0e10 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP 0x0e14 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL 0x0e18 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS 0x0e1c +#define cfgBIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1 0x0e20 +#define cfgBIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2 0x0e24 +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1 0x0e28 +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2 0x0e2c +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3 0x0e30 +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1 0x0e34 +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2 0x0e38 +#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3 0x0e3c +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP 0x0e40 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL 0x0e44 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS 0x0e48 +#define cfgBIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1 0x0e4c +#define cfgBIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2 0x0e50 +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1 0x0e54 +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2 0x0e58 +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3 0x0e5c +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1 0x0e60 +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2 0x0e64 +#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3 0x0e68 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP 0x0e6c +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL 0x0e70 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS 0x0e74 +#define cfgBIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1 0x0e78 +#define cfgBIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2 0x0e7c +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1 0x0e80 +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2 0x0e84 +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3 0x0e88 +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1 0x0e8c +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2 0x0e90 +#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3 0x0e94 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP 0x0e98 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL 0x0e9c +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS 0x0ea0 +#define cfgBIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1 0x0ea4 +#define cfgBIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2 0x0ea8 +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1 0x0eac +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2 0x0eb0 +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3 0x0eb4 +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1 0x0eb8 +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2 0x0ebc +#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3 0x0ec0 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP 0x0ec4 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL 0x0ec8 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS 0x0ecc +#define cfgBIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1 0x0ed0 +#define cfgBIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2 0x0ed4 +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1 0x0ed8 +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2 0x0edc +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3 0x0ee0 +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1 0x0ee4 +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2 0x0ee8 +#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3 0x0eec +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP 0x0ef0 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL 0x0ef4 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS 0x0ef8 +#define cfgBIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1 0x0efc +#define cfgBIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2 0x0f00 +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1 0x0f04 +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2 0x0f08 +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3 0x0f0c +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1 0x0f10 +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2 0x0f14 +#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3 0x0f18 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP 0x0f1c +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL 0x0f20 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS 0x0f24 +#define cfgBIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1 0x0f28 +#define cfgBIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2 0x0f2c +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1 0x0f30 +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2 0x0f34 +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3 0x0f38 +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1 0x0f3c +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2 0x0f40 +#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3 0x0f44 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP 0x0f48 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL 0x0f4c +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS 0x0f50 +#define cfgBIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1 0x0f54 +#define cfgBIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2 0x0f58 +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1 0x0f5c +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2 0x0f60 +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3 0x0f64 +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1 0x0f68 +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2 0x0f6c +#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3 0x0f70 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP 0x0f74 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL 0x0f78 +#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS 0x0f7c +#define cfgBIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1 0x0f80 +#define cfgBIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2 0x0f84 +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1 0x0f88 +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2 0x0f8c +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3 0x0f90 +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1 0x0f94 +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2 0x0f98 +#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3 0x0f9c + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF2_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF2_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF2_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF3_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF3_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF3_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF4_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF4_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF4_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF5_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF5_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF5_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF6_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF6_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF6_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF7_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF7_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF7_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x0776 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST 0x07ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP 0x07b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL 0x07b2 + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_vf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF1_VF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF1_VF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF1_VF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF1_VF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF1_VF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF1_VF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF1_VF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST 0x02d8 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3 0x02dc +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3 0x02e0 +#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3 0x02e4 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST 0x0600 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0604 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS 0x0608 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK 0x060c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY 0x0610 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS 0x0614 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK 0x0618 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL 0x061c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0 0x0620 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1 0x0624 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2 0x0628 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3 0x062c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4 0x063c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0 0x063c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5 0x0640 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1 0x0640 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6 0x0644 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2 0x0644 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7 0x0648 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3 0x0648 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8 0x064c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9 0x0650 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10 0x0654 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11 0x0658 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12 0x065c +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13 0x0660 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST 0x071c +#define cfgBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1 0x0720 +#define cfgBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2 0x0724 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST 0x0770 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP 0x0774 +#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL 0x0776 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h new file mode 100644 index 000000000000..9f8f8b3eba02 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h @@ -0,0 +1,49475 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_6_3_2_SH_MASK_HEADER +#define _nbio_6_3_2_SH_MASK_HEADER + + +// addressBlock: nbif0_nbif0_bif_bx_SYSDEC +//BIF_BX0_SYSHUB_INDEX_OVLP +#define BIF_BX0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 +#define BIF_BX0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL +//BIF_BX0_SYSHUB_DATA_OVLP +#define BIF_BX0_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 +#define BIF_BX0_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL +//BIF_BX0_SYSHUB_INDEX_HI_OVLP +#define BIF_BX0_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI__SHIFT 0x0 +#define BIF_BX0_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI_MASK 0x0000FFFFL +//BIF_BX0_PCIE_INDEX +#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_DATA +#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_INDEX2 +#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_DATA2 +#define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_INDEX_HI +#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x0000FFFFL +//BIF_BX0_PCIE_INDEX2_HI +#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x0000FFFFL +//BIF_BX0_SBIOS_SCRATCH_0 +#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_1 +#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_2 +#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_3 +#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_0 +#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_1 +#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_2 +#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_3 +#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_4 +#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_5 +#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_6 +#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_7 +#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_8 +#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_9 +#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_10 +#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_11 +#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_12 +#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_13 +#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_14 +#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_15 +#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_RLC_INTR_CNTL +//BIF_BX0_BIF_VCE_INTR_CNTL +//BIF_BX0_BIF_UVD_INTR_CNTL +//BIF_BX0_BIF_Engine_INTR_CNTL +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE__SHIFT 0x0 +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_INST_SEL__SHIFT 0x1b +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE_MASK 0x00000001L +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION_MASK 0x00000008L +#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_INST_SEL_MASK 0xF8000000L +//BIF_BX0_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_CNTL +#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_0 +#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_1 +#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_2 +#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_3 +#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_4 +#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_5 +#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_6 +#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_7 +#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_8 +#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_9 +#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_10 +#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_11 +#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_12 +#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_13 +#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_14 +#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_15 +#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_0 +#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_1 +#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_2 +#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_3 +#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_4 +#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_5 +#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_6 +#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_7 +#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_8 +#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_9 +#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_10 +#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_11 +#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_12 +#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_13 +#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_14 +#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_15 +#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_4 +#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_5 +#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_6 +#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_7 +#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_8 +#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_9 +#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_10 +#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_11 +#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_12 +#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_13 +#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_14 +#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_15 +#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_0_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_0_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_0_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_0_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3 +#define RCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF0_MM_INDEX +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF0_MM_DATA +#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MM_INDEX_HI +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_INDEX +#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_DATA +#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_INDEX_HI +#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI_MASK 0x0000FFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1 +//BIF_BX0_CC_BIF_BX_STRAP0 +#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//BIF_BX0_CC_BIF_BX_PINSTRAP0 +//BIF_BX0_BIF_MM_INDACCESS_CNTL +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX0_BUS_CNTL +#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX0_BIF_SCRATCH0 +#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_SCRATCH1 +#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX0_BX_RESET_EN +#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX0_MM_CFGREGS_CNTL +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX0_BX_RESET_CNTL +#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX0_INTERRUPT_CNTL +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//BIF_BX0_INTERRUPT_CNTL2 +#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX0_CLKREQB_PAD_CNTL +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX0_BIF_FEATURES_CONTROL_MISC +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//BIF_BX0_HDP_ATOMIC_CONTROL_MISC +#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_BX0_BIF_DOORBELL_CNTL +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL__SHIFT 0x5 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL_MASK 0x00000020L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX0_BIF_DOORBELL_INT_CNTL +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_BX0_BIF_FB_EN +#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX0_BIF_INTR_CNTL +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_BX0_BIF_MST_TRANS_PENDING_VF +#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX0_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX0_BACO_CNTL +#define BIF_BX0_BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BIF_BX0_BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10 +#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BIF_BX0_BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BIF_BX0_BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L +#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BX0_BIF_BACO_EXIT_TIME0 +#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER1 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BX0_BIF_BACO_EXIT_TIMER2 +#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER3 +#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER4 +#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_MEM_TYPE_CNTL +#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//BIF_BX0_NBIF_GFX_ADDR_LUT_0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_1 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_2 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_3 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_4 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_5 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_6 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_7 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_8 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_9 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_10 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_11 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_12 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_13 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_14 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_15 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_VF_REGWR_EN +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19 +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L +#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L +//BIF_BX0_VF_DOORBELL_EN +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19 +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L +#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L +//BIF_BX0_VF_FB_EN +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19 +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L +#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L +//BIF_BX0_VF_REGWR_STATUS +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19 +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L +#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L +//BIF_BX0_VF_DOORBELL_STATUS +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19 +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L +#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L +//BIF_BX0_VF_FB_STATUS +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19 +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L +#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L +//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX0_BIF_RB_CNTL +#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT 0x19 +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK 0x02000000L +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX0_BIF_RB_BASE +#define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_RB_RPTR +#define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX0_BIF_RB_WPTR +#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX0_BIF_RB_WPTR_ADDR_HI +#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX0_BIF_RB_WPTR_ADDR_LO +#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX0_MAILBOX_INDEX +#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX0_BACO_AZ_ENHANCE_CTRL +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET__SHIFT 0x2 +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE__SHIFT 0x10 +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO__SHIFT 0x11 +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO__SHIFT 0x1f +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET_MASK 0x00003FFCL +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE_MASK 0x00010000L +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO_MASK 0x00020000L +#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO_MASK 0x80000000L +//BIF_BX0_BIF_MP1_INTR_CTRL +#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L +//BIF_BX0_BIF_PERSTB_PAD_CNTL +#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX0_BIF_PX_EN_PAD_CNTL +#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL +//BIF_BX0_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX0_BIF_CLKREQB_PAD_CNTL +#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL +//BIF_BX0_BIF_PWRBRK_PAD_CNTL +#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL +//BIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE +#define BIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE__SHIFT 0x0 +#define BIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE_MASK 0x0000000FL + + +// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1 +//RCC_DEV0_0_RCC_ERR_INT_CNTL +#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_BACO_CNTL_MISC +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_DEV0_0_RCC_RESET_EN +#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_DEV0_0_RCC_VDM_SUPPORT +#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_DEV0_0_RCC_GPUIOV_REGION +#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_DEV0_0_RCC_GPU_HOSTVM_EN +#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_DEV0_0_RCC_PEER_REG_RANGE0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_PEER_REG_RANGE1 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_BUS_CNTL +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_0_RCC_CONFIG_CNTL +#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_DEV0_0_RCC_CONFIG_F0_BASE +#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_DEV0_0_RCC_CONFIG_APER_SIZE +#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE +#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_DEV0_0_RCC_XDMA_LO +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_XDMA_HI +#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_0_RCC_BUSNUM_CNTL1 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_DEV0_0_RCC_BUSNUM_LIST0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_DEV0_0_RCC_BUSNUM_LIST1 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_DEV0_0_RCC_BUSNUM_CNTL2 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM +#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_HOST_BUSNUM +#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_0_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_0_RCC_CMN_LINK_CNTL +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG__SHIFT 0x10 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG_MASK 0x00FF0000L +//RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_0_RCC_MH_ARB_CNTL +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x0000FFFEL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFDEC2 +//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_PBA +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L + + +// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1 +//RCC_STRAP0_RCC_BIF_STRAP0 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE__SHIFT 0x17 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK 0x00400000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE_MASK 0x00800000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP1 +#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT__SHIFT 0x4 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT_MASK 0x00000010L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP10 +//RCC_STRAP0_RCC_BIF_STRAP11 +//RCC_STRAP0_RCC_BIF_STRAP12 +//RCC_STRAP0_RCC_BIF_STRAP13 +#define RCC_STRAP0_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER_MASK 0x00000FFFL +//RCC_STRAP0_RCC_BIF_STRAP2 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWDS_SPT__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ARI_EN_UP__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWDS_SPT_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ARI_EN_UP_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP3 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_BIF_STRAP4 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_BIF_STRAP5 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP6 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN_MASK 0x00007C00L +#define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK 0xFFFF8000L +//RCC_STRAP0_RCC_BIF_STRAP7 +#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_GEN6_DIS__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_GEN6_DIS_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6_MASK 0x04000000L +//RCC_STRAP0_RCC_BIF_STRAP8 +//RCC_STRAP0_RCC_BIF_STRAP9 +//RCC_STRAP0_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0_MASK 0x03000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0_MASK 0x0C000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0_MASK 0x38000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0_MASK 0x00000E00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0_MASK 0x00002000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP0_RCC_DEV0_PORT_STRAP16 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP0_RCC_DEV0_PORT_STRAP17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0_MASK 0x0000E000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0_MASK 0x02000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0_MASK 0x0000000FL +//RCC_STRAP0_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0_MASK 0x000FF000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP19 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP22 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x0001F000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x003E0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0x07C00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0xF8000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP23 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP24 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0_MASK 0x10000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP1 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP10 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP11 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP12 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP13 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK 0x00FFF000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK 0x01000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP16 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK 0x00FFF000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP17 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK 0x01FFE000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1_MASK 0x000FF000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP19 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1__SHIFT 0xa +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1_MASK 0x00000400L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1_MASK 0x08000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP7 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1_MASK 0xC0000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP9 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1_MASK 0x10000000L + + +// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF0_BIF_BME_STATUS +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF0_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF0_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF0_BIF_TRANS_PENDING +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_CONTROL +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF0_MAILBOX_INT_CNTL +#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF0_BIF_VMHV_MAILBOX +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_PF0_PARTITION_COMPUTE_CAP +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_PF0_PARTITION_MEM_CAP +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_PF0_PARTITION_COMPUTE_STATUS +#define BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_PF0_PARTITION_MEM_STATUS +#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFPFVFDEC1 +//RCC_DEV0_EPF0_RCC_ERR_LOG +#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_gdc_GDCDEC +//GDC0_NGDC_SDP_PORT_CTRL +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT 0x10 +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT 0x1f +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L +#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK 0x80000000L +//GDC0_SHUB_REGS_IF_CTL +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT 0x1 +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK 0x00000002L +//GDC0_NGDC_MGCG_CTRL +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS__SHIFT 0xe +#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT 0xf +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS_MASK 0x00004000L +#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK 0x00008000L +//GDC0_S2A_MISC_CNTL +#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L +//GDC0_NGDC_MCA_SMN_CTRL0 +#define GDC0_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT 0x0 +#define GDC0_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK 0x00000001L +//GDC0_NGDC_EARLY_WAKEUP_CTRL +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS__SHIFT 0x0 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL__SHIFT 0x1 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN__SHIFT 0x2 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA__SHIFT 0x3 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5 +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS_MASK 0x00000001L +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL_MASK 0x00000002L +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN_MASK 0x00000004L +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA_MASK 0x00000008L +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L +#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L +//GDC0_GDC_DMA_SION_PCTRL +#define GDC0_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS__SHIFT 0x0 +#define GDC0_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS__SHIFT 0x3 +#define GDC0_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS__SHIFT 0x6 +#define GDC0_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS_MASK 0x00000001L +#define GDC0_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS_MASK 0x00000008L +#define GDC0_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS_MASK 0x00000040L +//GDC0_NGDC_MP4SDP_CNTL +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN__SHIFT 0x0 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL__SHIFT 0x1 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN__SHIFT 0x4 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL__SHIFT 0x5 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN__SHIFT 0x8 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL__SHIFT 0x9 +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN_MASK 0x00000001L +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL_MASK 0x00000006L +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN_MASK 0x00000010L +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL_MASK 0x00000060L +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN_MASK 0x00000100L +#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL_MASK 0x00000600L +//GDC0_DOORBELL_VCN_TARGET_VF0 +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF1 +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF2 +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF3 +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF4 +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF5 +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF6 +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6_MASK 0xF000L +//GDC0_DOORBELL_VCN_TARGET_VF7 +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7__SHIFT 0x0 +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7__SHIFT 0x4 +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7__SHIFT 0x8 +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7__SHIFT 0xc +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7_MASK 0x000FL +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7_MASK 0x00F0L +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7_MASK 0x0F00L +#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7_MASK 0xF000L +//GDC0_DOORBELL_ACCESS_EN_PF +#define GDC0_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF_MASK 0x00FFL +//GDC0_DOORBELL_ACCESS_EN_VF0 +#define GDC0_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF1 +#define GDC0_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF2 +#define GDC0_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF3 +#define GDC0_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF4 +#define GDC0_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF5 +#define GDC0_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF6 +#define GDC0_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6_MASK 0xFF00L +//GDC0_DOORBELL_ACCESS_EN_VF7 +#define GDC0_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7__SHIFT 0x0 +#define GDC0_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7__SHIFT 0x8 +#define GDC0_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7_MASK 0x00FFL +#define GDC0_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7_MASK 0xFF00L +//GDC0_NGDC_CNDI_BUS_PORT_CTRL +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS__SHIFT 0x0 +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK__SHIFT 0xc +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS__SHIFT 0xd +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK__SHIFT 0x19 +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE__SHIFT 0x1a +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK__SHIFT 0x1b +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS_MASK 0x00000FFFL +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK_MASK 0x00001000L +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS_MASK 0x01FFE000L +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK_MASK 0x02000000L +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE_MASK 0x04000000L +#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK_MASK 0x08000000L +//GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT 0x0 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT 0x4 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT 0x8 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT 0xc +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x10 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x11 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x12 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x13 +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK 0x0000000FL +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK 0x000000F0L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK 0x00000F00L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK 0x0000F000L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00010000L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00020000L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00040000L +#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00080000L + + +// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC +//GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN__SHIFT 0x1b +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK 0x0000003EL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN_MASK 0x08000000L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG +#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0 +#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE__SHIFT 0x1 +#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L +#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE_MASK 0x00000002L +//GDC_S2A0_NBIF_GFX_DOORBELL_STATUS +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN__SHIFT 0x10 +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST__SHIFT 0x18 +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN_MASK 0x00010000L +#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST_MASK 0x01000000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_COMMAND +#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_STATUS +#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_LATENCY +#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_HEADER +#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_BIST +#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//VENDOR_CAP_LIST +#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//ADAPTER_ID_W +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PMI_CAP +#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//PCIE_PWR_BUDGET_ENH_CAP_LIST +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PWR_BUDGET_DATA_SELECT +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE__SHIFT 0x10 +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0x000000FFL +#define PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE_MASK 0x00010000L +//PCIE_PWR_BUDGET_DATA +#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//PCIE_PWR_BUDGET_CAP +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT__SHIFT 0x1 +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +#define PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT_MASK 0x02L +//PCIE_DPA_ENH_CAP_LIST +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_DPA_CAP +#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//PCIE_DPA_LATENCY_INDICATOR +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//PCIE_DPA_STATUS +#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//PCIE_DPA_CNTL +#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//PCIE_LTR_ENH_CAP_LIST +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_LTR_CAP +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//PCIE_BAR_ENH_CAP_LIST +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_BAR1_CAP +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR1_CNTL +#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_BAR2_CAP +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR2_CNTL +#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_BAR3_CAP +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR3_CNTL +#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_BAR4_CAP +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR4_CNTL +#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_BAR5_CAP +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR5_CNTL +#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_BAR6_CAP +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_BAR6_CNTL +#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//PCIE_PAGE_REQ_ENH_CAP_LIST +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PAGE_REQ_CNTL +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//PCIE_PAGE_REQ_STATUS +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//PCIE_PASID_ENH_CAP_LIST +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PASID_CAP +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED__SHIFT 0x3 +#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED_MASK 0x0008L +#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//PCIE_PASID_CNTL +#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE__SHIFT 0x3 +#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +#define PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE_MASK 0x0008L +//PCIE_SRIOV_ENH_CAP_LIST +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_SRIOV_CAP +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x3 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000008L +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//PCIE_SRIOV_CONTROL +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x6 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE_MASK 0x0040L +//PCIE_SRIOV_STATUS +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//PCIE_SRIOV_INITIAL_VFS +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//PCIE_SRIOV_TOTAL_VFS +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//PCIE_SRIOV_NUM_VFS +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//PCIE_SRIOV_FUNC_DEP_LINK +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//PCIE_SRIOV_FIRST_VF_OFFSET +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//PCIE_SRIOV_VF_STRIDE +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//PCIE_SRIOV_VF_DEVICE_ID +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_1 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_2 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_3 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_4 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_5 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_VF_RESIZE_BAR1_CAP +#define PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR1_CNTL +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_VF_RESIZE_BAR2_CAP +#define PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR2_CNTL +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_VF_RESIZE_BAR3_CAP +#define PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR3_CNTL +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_VF_RESIZE_BAR4_CAP +#define PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR4_CNTL +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_VF_RESIZE_BAR5_CAP +#define PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR5_CNTL +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_VF_RESIZE_BAR6_CAP +#define PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//PCIE_VF_RESIZE_BAR6_CNTL +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//PCIE_DOE_ENH_CAP_LIST +#define PCIE_DOE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DOE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DOE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DOE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_DOE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_DOE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_DOE_CAP +#define PCIE_DOE_CAP__INTR_SUPPORT__SHIFT 0x0 +#define PCIE_DOE_CAP__DOE_INTR_MSG_NUM__SHIFT 0x1 +#define PCIE_DOE_CAP__DOE_ATT_SUPPORT__SHIFT 0xc +#define PCIE_DOE_CAP__DOE_ASYNC_SUPPORT__SHIFT 0xd +#define PCIE_DOE_CAP__INTR_SUPPORT_MASK 0x00000001L +#define PCIE_DOE_CAP__DOE_INTR_MSG_NUM_MASK 0x00000FFEL +#define PCIE_DOE_CAP__DOE_ATT_SUPPORT_MASK 0x00001000L +#define PCIE_DOE_CAP__DOE_ASYNC_SUPPORT_MASK 0x00002000L +//PCIE_DOE_CNTL +#define PCIE_DOE_CNTL__DOE_ABORT__SHIFT 0x0 +#define PCIE_DOE_CNTL__DOE_INTR_EN__SHIFT 0x1 +#define PCIE_DOE_CNTL__DOE_ATT_NOT_NEED__SHIFT 0x2 +#define PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN__SHIFT 0x3 +#define PCIE_DOE_CNTL__DOE_GO__SHIFT 0x1f +#define PCIE_DOE_CNTL__DOE_ABORT_MASK 0x00000001L +#define PCIE_DOE_CNTL__DOE_INTR_EN_MASK 0x00000002L +#define PCIE_DOE_CNTL__DOE_ATT_NOT_NEED_MASK 0x00000004L +#define PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN_MASK 0x00000008L +#define PCIE_DOE_CNTL__DOE_GO_MASK 0x80000000L +//PCIE_DOE_STS +#define PCIE_DOE_STS__DOE_BUSY__SHIFT 0x0 +#define PCIE_DOE_STS__DOE_INTR_STS__SHIFT 0x1 +#define PCIE_DOE_STS__DOE_ERR__SHIFT 0x2 +#define PCIE_DOE_STS__DOE_ASYNC_MSG_STS__SHIFT 0x3 +#define PCIE_DOE_STS__DOE_AT_ATTENTION__SHIFT 0x4 +#define PCIE_DOE_STS__DOE_OBJ_RDY__SHIFT 0x1f +#define PCIE_DOE_STS__DOE_BUSY_MASK 0x00000001L +#define PCIE_DOE_STS__DOE_INTR_STS_MASK 0x00000002L +#define PCIE_DOE_STS__DOE_ERR_MASK 0x00000004L +#define PCIE_DOE_STS__DOE_ASYNC_MSG_STS_MASK 0x00000008L +#define PCIE_DOE_STS__DOE_AT_ATTENTION_MASK 0x00000010L +#define PCIE_DOE_STS__DOE_OBJ_RDY_MASK 0x80000000L +//PCIE_DOE_WMBOX +#define PCIE_DOE_WMBOX__DOE_WMBOX__SHIFT 0x0 +#define PCIE_DOE_WMBOX__DOE_WMBOX_MASK 0xFFFFFFFFL +//PCIE_DOE_RMBOX +#define PCIE_DOE_RMBOX__DOE_RMBOX__SHIFT 0x0 +#define PCIE_DOE_RMBOX__DOE_RMBOX_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID_MASK 0xFF00L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp +//BIF_CFG_DEV0_EPF0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_AP_CAP +#define BIF_CFG_DEV0_EPF0_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_AP_CNTL +#define BIF_CFG_DEV0_EPF0_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_AP_DATA1 +#define BIF_CFG_DEV0_EPF0_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_EPF0_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_AP_DATA2 +#define BIF_CFG_DEV0_EPF0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_CAP +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK 0x00001F00L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK 0x0000E000L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_IDE_CNTL +#define BIF_CFG_DEV0_EPF0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK 0x00000004L +//BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC0_VENDOR_ID +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_DEVICE_ID +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_COMMAND +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC0_STATUS +#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_REVISION_ID +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PROG_INTERFACE +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_SUB_CLASS +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_BASE_CLASS +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_CACHE_LINE +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_LATENCY +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC0_HEADER +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC0_BIST +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC0_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_BASE_ADDR_2 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC0_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_CAP_PTR +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_RC0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_RC0_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L +//BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC0_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PMI_CAP +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_CAP +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_RC0_LINK_CAP +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_RC0_LINK_STATUS +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC0_SLOT_CNTL +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//BIF_CFG_DEV0_RC0_SLOT_STATUS +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC0_ROOT_CNTL +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV0_RC0_ROOT_CAP +#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV0_RC0_ROOT_STATUS +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC0_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_LINK_CAP2 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC0_LINK_STATUS2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//BIF_CFG_DEV0_RC0_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_SSID_CAP +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_LINK_CAP_16GT +#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_LINK_CAP_32GT +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_RC0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_RC0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_AP_CAP +#define BIF_CFG_DEV0_RC0_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_RC0_AP_CNTL +#define BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_RC0_AP_DATA1 +#define BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_AP_DATA2 +#define BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK 0x00000180L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_RTR_DATA1 +#define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_RC0_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_RTR_DATA2 +#define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_CAP +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK 0x00001F00L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK 0x0000E000L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK 0x02000000L +//BIF_CFG_DEV0_RC0_IDE_CNTL +#define BIF_CFG_DEV0_RC0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK 0x00000004L +//BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_COMMAND +#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_0_STATUS +#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_LATENCY +#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_HEADER +#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_0_BIST +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PMI_CAP +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE_MASK 0x00010000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT_MASK 0x02L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE_MASK 0x0008L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__INTR_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_INTR_MSG_NUM__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ATT_SUPPORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ASYNC_SUPPORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__INTR_SUPPORT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_INTR_MSG_NUM_MASK 0x00000FFEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ATT_SUPPORT_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ASYNC_SUPPORT_MASK 0x00002000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ABORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ATT_NOT_NEED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_GO__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ABORT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ATT_NOT_NEED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_GO_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_BUSY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_INTR_STS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ASYNC_MSG_STS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_AT_ATTENTION__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_OBJ_RDY__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_BUSY_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_INTR_STS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ERR_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ASYNC_MSG_STS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_AT_ATTENTION_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_OBJ_RDY_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX__DOE_WMBOX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX__DOE_WMBOX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX__DOE_RMBOX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX__DOE_RMBOX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp +//BIF_CFG_DEV0_EPF0_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_AP_CAP +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_0_AP_CNTL +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_EPF0_0_AP_DATA1 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_AP_DATA2 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_CAP +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK 0x00001F00L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK 0x0000E000L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_0_IDE_CNTL +#define BIF_CFG_DEV0_EPF0_0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK 0x00000004L +//BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_HEADER +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_BIST +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_HEADER +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_BIST +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_COMMAND +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_HEADER +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_BIST +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF2_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_COMMAND +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_HEADER +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_BIST +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF3_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_COMMAND +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_HEADER +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_BIST +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF4_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_COMMAND +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_HEADER +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_BIST +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF5_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_COMMAND +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_HEADER +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_BIST +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF6_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_COMMAND +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_HEADER +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_BIST +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF7_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1 +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2 +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK 0x0200L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF0_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF0_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF0_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF1_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF1_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF1_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF2_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF2_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF2_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF3_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF3_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF3_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF4_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF4_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF4_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF5_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF5_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF5_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF6_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF6_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF6_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF7_0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1:1 +//BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC:1 +//BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF7_1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF7_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_COMMAND +#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_STATUS +#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_REVISION_ID +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_LATENCY +#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_HEADER +#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_BIST +#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_CAP_PTR +#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PMI_CAP +#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//SBRN +#define SBRN__SBRN__SHIFT 0x0 +#define SBRN__SBRN_MASK 0xFFL +//FLADJ +#define FLADJ__FLADJ__SHIFT 0x0 +#define FLADJ__NFC__SHIFT 0x6 +#define FLADJ__FLADJ_MASK 0x3FL +#define FLADJ__NFC_MASK 0x40L +//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_LINK_CAP +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MASK +#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_RTR_DATA1 +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_RTR_DATA2 +#define BIF_CFG_DEV0_EPF1_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE_MASK 0x00010000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT_MASK 0x02L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE_MASK 0x0008L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_vf0_bifcfgdecp +//BIF_CFG_DEV0_EPF1_VF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_VF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_COMMAND +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_VF0_STATUS +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_REVISION_ID +#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_VF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_VF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_LATENCY +#define BIF_CFG_DEV0_EPF1_VF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_HEADER +#define BIF_CFG_DEV0_EPF1_VF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_VF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_VF0_BIST +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_VF0_CAP_PTR +#define BIF_CFG_DEV0_EPF1_VF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_VF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__TEE_IO_SUPPORT_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_VF0_LINK_CAP +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__SRIS_CLOCKING__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__SRIS_CLOCKING_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__FLIT_MODE_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_MASK +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK 0x00000380L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__L0P_ENABLE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__L0P_ENABLE_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK 0x00000070L +//BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1 +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2 +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: nbif0_nbif0_rcc_dev0_RCCPORTDEC +//RCC_DEV0_1_RCC_VDM_SUPPORT +#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_1_RCC_BUS_CNTL +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_1_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_1_RCC_CMN_LINK_CNTL +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG__SHIFT 0x10 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG_MASK 0x00FF0000L +//RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_1_RCC_MH_ARB_CNTL +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x0000FFFEL +//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_RCCPORTDEC +//RCC_EP_DEV0_1_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_1_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3 +#define RCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_RCCPORTDEC +//RCC_DWN_DEV0_1_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_RCCPORTDEC +//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_1_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_SENT_FLAG__SHIFT 0x9 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_SENT_FLAG_MASK 0x00000200L +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L +//RCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL__BURST_EN__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL__BURST_EN_MASK 0x00000007L +//RCC_PFC_AMDGFX_RCC_NFC +#define RCC_PFC_AMDGFX_RCC_NFC__NFC_PFV__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_NFC__NFC_PFV_MASK 0x00000001L + + +// addressBlock: nbif0_nbif0_rcc_shadow_reg_shadowdec +//SHADOW_COMMAND +#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0 +#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1 +#define SHADOW_COMMAND__IOEN_UP_MASK 0x0001L +#define SHADOW_COMMAND__MEMEN_UP_MASK 0x0002L +//SHADOW_BASE_ADDR_1 +#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0 +#define SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xFFFFFFFFL +//SHADOW_BASE_ADDR_2 +#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0 +#define SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xFFFFFFFFL +//SHADOW_SUB_BUS_NUMBER_LATENCY +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8 +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10 +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK 0x0000FF00L +#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK 0x00FF0000L +//SHADOW_IO_BASE_LIMIT +#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4 +#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc +#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK 0x00F0L +#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK 0xF000L +//SHADOW_MEM_BASE_LIMIT +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4 +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14 +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK 0x0000FFF0L +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK 0xFFF00000L +//SHADOW_PREF_BASE_LIMIT +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14 +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK 0x0000FFF0L +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK 0xFFF00000L +//SHADOW_PREF_BASE_UPPER +#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0 +#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK 0xFFFFFFFFL +//SHADOW_PREF_LIMIT_UPPER +#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0 +#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK 0xFFFFFFFFL +//SHADOW_IO_BASE_LIMIT_HI +#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0 +#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10 +#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK 0x0000FFFFL +#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK 0xFFFF0000L +//SHADOW_IRQ_BRIDGE_CNTL +#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2 +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3 +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4 +#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6 +#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK 0x0004L +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK 0x0008L +#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK 0x0010L +#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK 0x0040L +//SUC_INDEX +#define SUC_INDEX__SUC_INDEX__SHIFT 0x0 +#define SUC_INDEX__SUC_INDEX_MASK 0xFFFFFFFFL +//SUC_DATA +#define SUC_DATA__SUC_DATA__SHIFT 0x0 +#define SUC_DATA__SUC_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_swus_SUMDEC +//SUM_INDEX +#define SUM_INDEX__SUM_INDEX__SHIFT 0x0 +#define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL +//SUM_DATA +#define SUM_DATA__SUM_DATA__SHIFT 0x0 +#define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL +//SUM_INDEX_HI +#define SUM_INDEX_HI__SUM_INDEX_HI__SHIFT 0x0 +#define SUM_INDEX_HI__SUM_INDEX_HI_MASK 0x0000FFFFL + + +// addressBlock: nbif0_nbif0_rcc_strap_rcc_strap_internal +//RCC_STRAP1_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0_MASK 0x03000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0_MASK 0x0C000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0_MASK 0x38000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0_MASK 0x00000E00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0_MASK 0x00002000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP1_RCC_DEV0_PORT_STRAP16 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP1_RCC_DEV0_PORT_STRAP17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0_MASK 0x0000E000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0_MASK 0x02000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0_MASK 0x0000000FL +//RCC_DEV1_PORT_STRAP0 +//RCC_DEV1_PORT_STRAP1 +//RCC_DEV1_PORT_STRAP2 +//RCC_DEV1_PORT_STRAP3 +//RCC_DEV1_PORT_STRAP4 +//RCC_DEV1_PORT_STRAP5 +//RCC_DEV1_PORT_STRAP6 +//RCC_DEV1_PORT_STRAP7 +//RCC_DEV1_PORT_STRAP8 +//RCC_DEV1_PORT_STRAP9 +//RCC_DEV1_PORT_STRAP10 +//RCC_DEV1_PORT_STRAP11 +//RCC_DEV1_PORT_STRAP12 +//RCC_DEV1_PORT_STRAP13 +//RCC_DEV1_PORT_STRAP14 +//RCC_DEV1_PORT_STRAP15 +//RCC_DEV1_PORT_STRAP16 +//RCC_DEV2_PORT_STRAP0 +//RCC_DEV2_PORT_STRAP1 +//RCC_DEV2_PORT_STRAP2 +//RCC_DEV2_PORT_STRAP3 +//RCC_DEV2_PORT_STRAP4 +//RCC_DEV2_PORT_STRAP5 +//RCC_DEV2_PORT_STRAP6 +//RCC_DEV2_PORT_STRAP7 +//RCC_DEV2_PORT_STRAP8 +//RCC_DEV2_PORT_STRAP9 +//RCC_DEV2_PORT_STRAP10 +//RCC_DEV2_PORT_STRAP11 +//RCC_DEV2_PORT_STRAP12 +//RCC_DEV2_PORT_STRAP13 +//RCC_DEV2_PORT_STRAP14 +//RCC_DEV2_PORT_STRAP15 +//RCC_DEV2_PORT_STRAP16 +//RCC_STRAP1_RCC_BIF_STRAP0 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE__SHIFT 0x17 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK 0x00400000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE_MASK 0x00800000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP1 +#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT__SHIFT 0x4 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT_MASK 0x00000010L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP2 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWDS_SPT__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ARI_EN_UP__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWDS_SPT_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ARI_EN_UP_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP3 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_BIF_STRAP4 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_BIF_STRAP5 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP6 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN_MASK 0x00007C00L +#define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK 0xFFFF8000L +//RCC_STRAP1_RCC_BIF_STRAP7 +#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_GEN6_DIS__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_GEN6_DIS_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6_MASK 0x04000000L +//RCC_STRAP1_RCC_BIF_STRAP8 +//RCC_STRAP1_RCC_BIF_STRAP9 +//RCC_STRAP1_RCC_BIF_STRAP10 +//RCC_STRAP1_RCC_BIF_STRAP11 +//RCC_STRAP1_RCC_BIF_STRAP12 +//RCC_STRAP1_RCC_BIF_STRAP13 +#define RCC_STRAP1_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER_MASK 0x00000FFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0_MASK 0x10000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0_MASK 0x000FF000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP19 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP22 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x0001F000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x003E0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0x07C00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0xF8000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP23 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP24 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP1 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1__SHIFT 0xa +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1_MASK 0x00000400L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1_MASK 0x08000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP7 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1_MASK 0xC0000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP9 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1_MASK 0x10000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP10 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP11 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP12 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP13 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK 0x00FFF000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK 0x01000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP16 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK 0x00FFF000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP17 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK 0x01FFE000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1_MASK 0x000FF000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP19 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP24 +//RCC_DEV0_EPF2_STRAP0 +//RCC_DEV0_EPF2_STRAP2 +//RCC_DEV0_EPF2_STRAP3 +//RCC_DEV0_EPF2_STRAP4 +//RCC_DEV0_EPF2_STRAP5 +//RCC_DEV0_EPF2_STRAP6 +//RCC_DEV0_EPF2_STRAP7 +//RCC_DEV0_EPF2_STRAP9 +//RCC_DEV0_EPF2_STRAP10 +//RCC_DEV0_EPF2_STRAP11 +//RCC_DEV0_EPF2_STRAP12 +//RCC_DEV0_EPF2_STRAP13 +//RCC_DEV0_EPF2_STRAP14 +//RCC_DEV0_EPF2_STRAP15 +//RCC_DEV0_EPF2_STRAP16 +//RCC_DEV0_EPF2_STRAP20 +//RCC_DEV0_EPF3_STRAP0 +//RCC_DEV0_EPF3_STRAP2 +//RCC_DEV0_EPF3_STRAP3 +//RCC_DEV0_EPF3_STRAP4 +//RCC_DEV0_EPF3_STRAP5 +//RCC_DEV0_EPF3_STRAP6 +//RCC_DEV0_EPF3_STRAP7 +//RCC_DEV0_EPF3_STRAP9 +//RCC_DEV0_EPF3_STRAP10 +//RCC_DEV0_EPF3_STRAP11 +//RCC_DEV0_EPF3_STRAP12 +//RCC_DEV0_EPF3_STRAP13 +//RCC_DEV0_EPF3_STRAP14 +//RCC_DEV0_EPF3_STRAP15 +//RCC_DEV0_EPF3_STRAP16 +//RCC_DEV0_EPF3_STRAP20 +//RCC_DEV0_EPF4_STRAP0 +//RCC_DEV0_EPF4_STRAP2 +//RCC_DEV0_EPF4_STRAP3 +//RCC_DEV0_EPF4_STRAP4 +//RCC_DEV0_EPF4_STRAP5 +//RCC_DEV0_EPF4_STRAP6 +//RCC_DEV0_EPF4_STRAP7 +//RCC_DEV0_EPF4_STRAP9 +//RCC_DEV0_EPF4_STRAP13 +//RCC_DEV0_EPF4_STRAP14 +//RCC_DEV0_EPF4_STRAP15 +//RCC_DEV0_EPF4_STRAP16 +//RCC_DEV0_EPF5_STRAP0 +//RCC_DEV0_EPF5_STRAP2 +//RCC_DEV0_EPF5_STRAP3 +//RCC_DEV0_EPF5_STRAP4 +//RCC_DEV0_EPF5_STRAP5 +//RCC_DEV0_EPF5_STRAP6 +//RCC_DEV0_EPF5_STRAP7 +//RCC_DEV0_EPF5_STRAP9 +//RCC_DEV0_EPF5_STRAP13 +//RCC_DEV0_EPF5_STRAP14 +//RCC_DEV0_EPF5_STRAP15 +//RCC_DEV0_EPF5_STRAP16 +//RCC_DEV0_EPF6_STRAP0 +//RCC_DEV0_EPF6_STRAP2 +//RCC_DEV0_EPF6_STRAP3 +//RCC_DEV0_EPF6_STRAP4 +//RCC_DEV0_EPF6_STRAP5 +//RCC_DEV0_EPF6_STRAP6 +//RCC_DEV0_EPF6_STRAP7 +//RCC_DEV0_EPF6_STRAP9 +//RCC_DEV0_EPF6_STRAP13 +//RCC_DEV0_EPF6_STRAP14 +//RCC_DEV0_EPF6_STRAP15 +//RCC_DEV0_EPF6_STRAP16 +//RCC_DEV0_EPF7_STRAP0 +//RCC_DEV0_EPF7_STRAP2 +//RCC_DEV0_EPF7_STRAP3 +//RCC_DEV0_EPF7_STRAP4 +//RCC_DEV0_EPF7_STRAP5 +//RCC_DEV0_EPF7_STRAP6 +//RCC_DEV0_EPF7_STRAP9 +//RCC_DEV0_EPF7_STRAP13 +//RCC_DEV0_EPF7_STRAP14 +//RCC_DEV0_EPF7_STRAP15 +//RCC_DEV0_EPF7_STRAP16 +//RCC_DEV1_EPF0_STRAP0 +//RCC_DEV1_EPF0_STRAP2 +//RCC_DEV1_EPF0_STRAP3 +//RCC_DEV1_EPF0_STRAP4 +//RCC_DEV1_EPF0_STRAP5 +//RCC_DEV1_EPF0_STRAP6 +//RCC_DEV1_EPF0_STRAP9 +//RCC_DEV1_EPF0_STRAP13 +//RCC_DEV1_EPF0_STRAP14 +//RCC_DEV1_EPF0_STRAP15 +//RCC_DEV1_EPF0_STRAP16 +//RCC_DEV1_EPF1_STRAP0 +//RCC_DEV1_EPF1_STRAP1 +//RCC_DEV1_EPF1_STRAP2 +//RCC_DEV1_EPF1_STRAP3 +//RCC_DEV1_EPF1_STRAP4 +//RCC_DEV1_EPF1_STRAP5 +//RCC_DEV1_EPF1_STRAP6 +//RCC_DEV1_EPF1_STRAP7 +//RCC_DEV1_EPF1_STRAP8 +//RCC_DEV1_EPF1_STRAP9 +//RCC_DEV1_EPF1_STRAP13 +//RCC_DEV1_EPF1_STRAP14 +//RCC_DEV1_EPF1_STRAP15 +//RCC_DEV1_EPF1_STRAP16 +//RCC_DEV1_EPF1_STRAP17 +//RCC_DEV1_EPF1_STRAP18 +//RCC_DEV1_EPF1_STRAP19 +//RCC_DEV1_EPF1_STRAP20 +//RCC_DEV1_EPF1_STRAP21 +//RCC_DEV1_EPF2_STRAP0 +//RCC_DEV1_EPF2_STRAP1 +//RCC_DEV1_EPF2_STRAP2 +//RCC_DEV1_EPF2_STRAP3 +//RCC_DEV1_EPF2_STRAP4 +//RCC_DEV1_EPF2_STRAP5 +//RCC_DEV1_EPF2_STRAP6 +//RCC_DEV1_EPF2_STRAP7 +//RCC_DEV1_EPF2_STRAP8 +//RCC_DEV1_EPF2_STRAP9 +//RCC_DEV1_EPF2_STRAP13 +//RCC_DEV1_EPF2_STRAP14 +//RCC_DEV1_EPF2_STRAP15 +//RCC_DEV1_EPF2_STRAP16 +//RCC_DEV1_EPF2_STRAP17 +//RCC_DEV1_EPF2_STRAP18 +//RCC_DEV1_EPF2_STRAP19 +//RCC_DEV1_EPF2_STRAP20 +//RCC_DEV1_EPF2_STRAP21 +//RCC_DEV1_EPF3_STRAP0 +//RCC_DEV1_EPF3_STRAP2 +//RCC_DEV1_EPF3_STRAP3 +//RCC_DEV1_EPF3_STRAP4 +//RCC_DEV1_EPF3_STRAP5 +//RCC_DEV1_EPF3_STRAP6 +//RCC_DEV1_EPF3_STRAP7 +//RCC_DEV1_EPF3_STRAP13 +//RCC_DEV1_EPF3_STRAP14 +//RCC_DEV1_EPF3_STRAP15 +//RCC_DEV1_EPF3_STRAP16 +//RCC_DEV1_EPF4_STRAP6 +//RCC_DEV1_EPF5_STRAP6 +//RCC_DEV1_EPF6_STRAP6 +//RCC_DEV2_EPF0_STRAP0 +//RCC_DEV2_EPF0_STRAP2 +//RCC_DEV2_EPF0_STRAP3 +//RCC_DEV2_EPF0_STRAP4 +//RCC_DEV2_EPF0_STRAP5 +//RCC_DEV2_EPF0_STRAP6 +//RCC_DEV2_EPF0_STRAP7 +//RCC_DEV2_EPF0_STRAP13 +//RCC_DEV2_EPF0_STRAP14 +//RCC_DEV2_EPF0_STRAP15 +//RCC_DEV2_EPF0_STRAP16 +//RCC_DEV2_EPF0_STRAP18 +//RCC_DEV2_EPF0_STRAP25 +//RCC_DEV2_EPF0_STRAP26 +//RCC_DEV2_EPF1_STRAP0 +//RCC_DEV2_EPF1_STRAP2 +//RCC_DEV2_EPF1_STRAP3 +//RCC_DEV2_EPF1_STRAP4 +//RCC_DEV2_EPF1_STRAP5 +//RCC_DEV2_EPF1_STRAP6 +//RCC_DEV2_EPF1_STRAP7 +//RCC_DEV2_EPF1_STRAP13 +//RCC_DEV2_EPF1_STRAP14 +//RCC_DEV2_EPF1_STRAP15 +//RCC_DEV2_EPF1_STRAP16 +//RCC_DEV2_EPF2_STRAP0 +//RCC_DEV2_EPF2_STRAP2 +//RCC_DEV2_EPF2_STRAP3 +//RCC_DEV2_EPF2_STRAP4 +//RCC_DEV2_EPF2_STRAP5 +//RCC_DEV2_EPF2_STRAP6 +//RCC_DEV2_EPF2_STRAP7 +//RCC_DEV2_EPF2_STRAP13 +//RCC_DEV2_EPF2_STRAP14 +//RCC_DEV2_EPF2_STRAP15 +//RCC_DEV2_EPF2_STRAP16 +//RCC_DEV2_EPF3_STRAP0 +//RCC_DEV2_EPF3_STRAP2 +//RCC_DEV2_EPF3_STRAP3 +//RCC_DEV2_EPF3_STRAP4 +//RCC_DEV2_EPF3_STRAP5 +//RCC_DEV2_EPF3_STRAP6 +//RCC_DEV2_EPF3_STRAP7 +//RCC_DEV2_EPF3_STRAP13 +//RCC_DEV2_EPF3_STRAP14 +//RCC_DEV2_EPF3_STRAP15 +//RCC_DEV2_EPF3_STRAP16 +//RCC_DEV2_EPF4_STRAP0 +//RCC_DEV2_EPF4_STRAP2 +//RCC_DEV2_EPF4_STRAP3 +//RCC_DEV2_EPF4_STRAP4 +//RCC_DEV2_EPF4_STRAP5 +//RCC_DEV2_EPF4_STRAP6 +//RCC_DEV2_EPF4_STRAP7 +//RCC_DEV2_EPF4_STRAP13 +//RCC_DEV2_EPF4_STRAP14 +//RCC_DEV2_EPF4_STRAP15 +//RCC_DEV2_EPF4_STRAP16 +//RCC_DEV2_EPF5_STRAP0 +//RCC_DEV2_EPF5_STRAP2 +//RCC_DEV2_EPF5_STRAP3 +//RCC_DEV2_EPF5_STRAP4 +//RCC_DEV2_EPF5_STRAP5 +//RCC_DEV2_EPF5_STRAP6 +//RCC_DEV2_EPF5_STRAP7 +//RCC_DEV2_EPF5_STRAP13 +//RCC_DEV2_EPF5_STRAP14 +//RCC_DEV2_EPF5_STRAP15 +//RCC_DEV2_EPF5_STRAP16 +//RCC_DEV2_EPF6_STRAP0 +//RCC_DEV2_EPF6_STRAP2 +//RCC_DEV2_EPF6_STRAP3 +//RCC_DEV2_EPF6_STRAP4 +//RCC_DEV2_EPF6_STRAP5 +//RCC_DEV2_EPF6_STRAP6 +//RCC_DEV2_EPF6_STRAP7 +//RCC_DEV2_EPF6_STRAP13 +//RCC_DEV2_EPF6_STRAP14 +//RCC_DEV2_EPF6_STRAP15 +//RCC_DEV2_EPF6_STRAP16 + + +// addressBlock: nbif0_nbif0_bif_rst_bif_rst_regblk +//HARD_RST_CTRL +#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 +#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 +#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 +#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 +#define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x9 +#define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0xa +#define HARD_RST_CTRL__STRAP_RST_EN__SHIFT 0x17 +#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c +#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d +#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e +#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f +#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L +#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L +#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L +#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L +#define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000200L +#define HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000400L +#define HARD_RST_CTRL__STRAP_RST_EN_MASK 0x00800000L +#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L +#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L +#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L +#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L +//SELF_SOFT_RST +#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST__PCIE_NBIF_HST_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST__SST_HST_SDP_PORT_RST__SHIFT 0x19 +#define SELF_SOFT_RST__NBIF_PCIE_DMA_SDP_PORT_RST__SHIFT 0x1a +#define SELF_SOFT_RST__SST_DMA_SDP_PORT_RST__SHIFT 0x1b +#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c +#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d +#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e +#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f +#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST__PCIE_NBIF_HST_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST__SST_HST_SDP_PORT_RST_MASK 0x02000000L +#define SELF_SOFT_RST__NBIF_PCIE_DMA_SDP_PORT_RST_MASK 0x04000000L +#define SELF_SOFT_RST__SST_DMA_SDP_PORT_RST_MASK 0x08000000L +#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L +#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L +#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L +#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L +//BIF_GFX_DRV_VPU_RST +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L +//BIF_RST_MISC_CTRL +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 +#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 +#define BIF_RST_MISC_CTRL__HARD_RST_CTRL_SWUS_SHADOW_PRV_RST_EN__SHIFT 0x1a +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L +#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L +#define BIF_RST_MISC_CTRL__HARD_RST_CTRL_SWUS_SHADOW_PRV_RST_EN_MASK 0x04000000L +//BIF_RST_MISC_CTRL2 +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT__SHIFT 0x0 +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT__SHIFT 0x1 +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT__SHIFT 0x2 +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT__SHIFT 0xf +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS__SHIFT 0x1e +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT_MASK 0x00000001L +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT_MASK 0x00000002L +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT_MASK 0x00000004L +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_MASK 0x00008000L +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS_MASK 0x40000000L +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L +//BIF_RST_MISC_CTRL3 +#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd +#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L +//DEV0_PF0_FLR_RST_CTRL +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_EN__SHIFT 0x5 +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_STICKY_EN__SHIFT 0x6 +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_PRV_EN__SHIFT 0x7 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_EN__SHIFT 0xd +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN__SHIFT 0xe +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_PRV_EN__SHIFT 0xf +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_EN_MASK 0x00000020L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_STICKY_EN_MASK 0x00000040L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_PRV_EN_MASK 0x00000080L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_EN_MASK 0x00002000L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN_MASK 0x00004000L +#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_PRV_EN_MASK 0x00008000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L +//DEV0_PF1_FLR_RST_CTRL +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_EN__SHIFT 0x5 +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_STICKY_EN__SHIFT 0x6 +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_PRV_EN__SHIFT 0x7 +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_EN__SHIFT 0xd +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN__SHIFT 0xe +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_PRV_EN__SHIFT 0xf +#define DEV0_PF1_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_EN_MASK 0x00000020L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_STICKY_EN_MASK 0x00000040L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_PRV_EN_MASK 0x00000080L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_EN_MASK 0x00002000L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN_MASK 0x00004000L +#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_PRV_EN_MASK 0x00008000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//BIF_INST_RESET_INTR_STS +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L +//BIF_PF_FLR_INTR_STS +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L +//BIF_D3HOTD0_INTR_STS +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L +//BIF_POWER_INTR_STS +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L +//BIF_PF_DSTATE_INTR_STS +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L +//SELF_SOFT_RST_2 +#define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST_2__STRAP_RST__SHIFT 0x19 +#define SELF_SOFT_RST_2__SWUS_SHADOW_PRV_RST__SHIFT 0x1a +#define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST_2__EP3_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST_2__EP3_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST_2__STRAP_RST_MASK 0x02000000L +#define SELF_SOFT_RST_2__SWUS_SHADOW_PRV_RST_MASK 0x04000000L +//SION_SDP_PORT_RST +#define SION_SDP_PORT_RST__SYSHUB_NBIFSION_SDP_PORT_RST__SHIFT 0x0 +#define SION_SDP_PORT_RST__NBIFSION_SYSHUB_SDP_PORT_RST__SHIFT 0x1 +#define SION_SDP_PORT_RST__BIF_NBIFSION_SDP_PORT_RST__SHIFT 0x2 +#define SION_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4 +#define SION_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST__SHIFT 0x5 +#define SION_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT 0x6 +#define SION_SDP_PORT_RST__NBIFSOIN_ATHUB_SDP_PORT_RST__SHIFT 0x7 +#define SION_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8 +#define SION_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9 +#define SION_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0xc +#define SION_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18 +#define SION_SDP_PORT_RST__SYSHUB_NBIFSION_SDP_PORT_RST_MASK 0x00000001L +#define SION_SDP_PORT_RST__NBIFSION_SYSHUB_SDP_PORT_RST_MASK 0x00000002L +#define SION_SDP_PORT_RST__BIF_NBIFSION_SDP_PORT_RST_MASK 0x00000004L +#define SION_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L +#define SION_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST_MASK 0x00000020L +#define SION_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK 0x00000040L +#define SION_SDP_PORT_RST__NBIFSOIN_ATHUB_SDP_PORT_RST_MASK 0x00000080L +#define SION_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L +#define SION_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L +#define SION_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00001000L +#define SION_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L +//BIF_INST_RESET_INTR_MASK +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L +//BIF_PF_FLR_INTR_MASK +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L +//BIF_D3HOTD0_INTR_MASK +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L +//BIF_POWER_INTR_MASK +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L +//BIF_PF_DSTATE_INTR_MASK +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L +//BIF_DEV0_PF0_VF_FLR_INTR_MASK +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF0_FLR_INTR_MASK__SHIFT 0x0 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF1_FLR_INTR_MASK__SHIFT 0x1 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF2_FLR_INTR_MASK__SHIFT 0x2 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF3_FLR_INTR_MASK__SHIFT 0x3 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF4_FLR_INTR_MASK__SHIFT 0x4 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF5_FLR_INTR_MASK__SHIFT 0x5 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF6_FLR_INTR_MASK__SHIFT 0x6 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF7_FLR_INTR_MASK__SHIFT 0x7 +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF0_FLR_INTR_MASK_MASK 0x00000001L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF1_FLR_INTR_MASK_MASK 0x00000002L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF2_FLR_INTR_MASK_MASK 0x00000004L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF3_FLR_INTR_MASK_MASK 0x00000008L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF4_FLR_INTR_MASK_MASK 0x00000010L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF5_FLR_INTR_MASK_MASK 0x00000020L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF6_FLR_INTR_MASK_MASK 0x00000040L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF7_FLR_INTR_MASK_MASK 0x00000080L +#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_SOFTPF_FLR_INTR_MASK_MASK 0x80000000L +//BIF_DEV0_PF1_VF_FLR_INTR_MASK +#define BIF_DEV0_PF1_VF_FLR_INTR_MASK__DEV0_PF1_VF0_FLR_INTR_MASK__SHIFT 0x0 +#define BIF_DEV0_PF1_VF_FLR_INTR_MASK__DEV0_PF1_VF0_FLR_INTR_MASK_MASK 0x00000001L +//BIF_PF_FLR_RST +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +//BIF_PF_FLR_PROTECT +#define BIF_PF_FLR_PROTECT__DEV0_PF0_FLR_PROTECT__SHIFT 0x0 +#define BIF_PF_FLR_PROTECT__DEV0_PF1_FLR_PROTECT__SHIFT 0x1 +#define BIF_PF_FLR_PROTECT__DEV0_PF2_FLR_PROTECT__SHIFT 0x2 +#define BIF_PF_FLR_PROTECT__DEV0_PF3_FLR_PROTECT__SHIFT 0x3 +#define BIF_PF_FLR_PROTECT__DEV0_PF4_FLR_PROTECT__SHIFT 0x4 +#define BIF_PF_FLR_PROTECT__DEV0_PF5_FLR_PROTECT__SHIFT 0x5 +#define BIF_PF_FLR_PROTECT__DEV0_PF6_FLR_PROTECT__SHIFT 0x6 +#define BIF_PF_FLR_PROTECT__DEV0_PF7_FLR_PROTECT__SHIFT 0x7 +#define BIF_PF_FLR_PROTECT__DEV0_PF0_TRANS_IDLE__SHIFT 0x10 +#define BIF_PF_FLR_PROTECT__DEV0_PF1_TRANS_IDLE__SHIFT 0x11 +#define BIF_PF_FLR_PROTECT__DEV0_PF2_TRANS_IDLE__SHIFT 0x12 +#define BIF_PF_FLR_PROTECT__DEV0_PF3_TRANS_IDLE__SHIFT 0x13 +#define BIF_PF_FLR_PROTECT__DEV0_PF4_TRANS_IDLE__SHIFT 0x14 +#define BIF_PF_FLR_PROTECT__DEV0_PF5_TRANS_IDLE__SHIFT 0x15 +#define BIF_PF_FLR_PROTECT__DEV0_PF6_TRANS_IDLE__SHIFT 0x16 +#define BIF_PF_FLR_PROTECT__DEV0_PF7_TRANS_IDLE__SHIFT 0x17 +#define BIF_PF_FLR_PROTECT__DEV0_PF0_FLR_PROTECT_MASK 0x00000001L +#define BIF_PF_FLR_PROTECT__DEV0_PF1_FLR_PROTECT_MASK 0x00000002L +#define BIF_PF_FLR_PROTECT__DEV0_PF2_FLR_PROTECT_MASK 0x00000004L +#define BIF_PF_FLR_PROTECT__DEV0_PF3_FLR_PROTECT_MASK 0x00000008L +#define BIF_PF_FLR_PROTECT__DEV0_PF4_FLR_PROTECT_MASK 0x00000010L +#define BIF_PF_FLR_PROTECT__DEV0_PF5_FLR_PROTECT_MASK 0x00000020L +#define BIF_PF_FLR_PROTECT__DEV0_PF6_FLR_PROTECT_MASK 0x00000040L +#define BIF_PF_FLR_PROTECT__DEV0_PF7_FLR_PROTECT_MASK 0x00000080L +#define BIF_PF_FLR_PROTECT__DEV0_PF0_TRANS_IDLE_MASK 0x00010000L +#define BIF_PF_FLR_PROTECT__DEV0_PF1_TRANS_IDLE_MASK 0x00020000L +#define BIF_PF_FLR_PROTECT__DEV0_PF2_TRANS_IDLE_MASK 0x00040000L +#define BIF_PF_FLR_PROTECT__DEV0_PF3_TRANS_IDLE_MASK 0x00080000L +#define BIF_PF_FLR_PROTECT__DEV0_PF4_TRANS_IDLE_MASK 0x00100000L +#define BIF_PF_FLR_PROTECT__DEV0_PF5_TRANS_IDLE_MASK 0x00200000L +#define BIF_PF_FLR_PROTECT__DEV0_PF6_TRANS_IDLE_MASK 0x00400000L +#define BIF_PF_FLR_PROTECT__DEV0_PF7_TRANS_IDLE_MASK 0x00800000L +//BIF_PF_FLR_PROTECT3 +#define BIF_PF_FLR_PROTECT3__DEV0_PF0_VF_FLR_CTRL__SHIFT 0x0 +#define BIF_PF_FLR_PROTECT3__DEV0_PF1_VF_FLR_CTRL__SHIFT 0x1 +#define BIF_PF_FLR_PROTECT3__DEV0_PF0_VF_FLR_CTRL_MASK 0x00000001L +#define BIF_PF_FLR_PROTECT3__DEV0_PF1_VF_FLR_CTRL_MASK 0x00000002L +//BIF_DEV0_PF0_DSTATE_VALUE +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF1_DSTATE_VALUE +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L +//GFX_RST_CNTL_IND0 +#define GFX_RST_CNTL_IND0__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND0__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND0__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND0__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_SOFT_PF +#define GFX_RST_CNTL_SOFT_PF__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_SOFT_PF__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_SOFT_PF__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_SOFT_PF__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND1 +#define GFX_RST_CNTL_IND1__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND1__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND1__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND1__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND2 +#define GFX_RST_CNTL_IND2__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND2__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND2__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND2__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND3 +#define GFX_RST_CNTL_IND3__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND3__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND3__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND3__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND4 +#define GFX_RST_CNTL_IND4__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND4__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND4__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND4__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND5 +#define GFX_RST_CNTL_IND5__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND5__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND5__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND5__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND6 +#define GFX_RST_CNTL_IND6__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND6__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND6__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND6__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND7 +#define GFX_RST_CNTL_IND7__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND7__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND7__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND7__SCRATCH_REG_MASK 0xFFFFFFFEL +//GFX_RST_CNTL_IND8 +#define GFX_RST_CNTL_IND8__GFX_RST_FINISH_INDICATION__SHIFT 0x0 +#define GFX_RST_CNTL_IND8__SCRATCH_REG__SHIFT 0x1 +#define GFX_RST_CNTL_IND8__GFX_RST_FINISH_INDICATION_MASK 0x00000001L +#define GFX_RST_CNTL_IND8__SCRATCH_REG_MASK 0xFFFFFFFEL +//DEV0_PF0_D3HOTD0_RST_CTRL +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF1_D3HOTD0_RST_CTRL +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//BIF_DEV0_PF0_VF_FLR_PROTECT +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF0_FLR_PROTECT__SHIFT 0x0 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF1_FLR_PROTECT__SHIFT 0x1 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF2_FLR_PROTECT__SHIFT 0x2 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF3_FLR_PROTECT__SHIFT 0x3 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF4_FLR_PROTECT__SHIFT 0x4 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF5_FLR_PROTECT__SHIFT 0x5 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF6_FLR_PROTECT__SHIFT 0x6 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF7_FLR_PROTECT__SHIFT 0x7 +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_SOFTPF_FLR_PROTECT__SHIFT 0x1f +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF0_FLR_PROTECT_MASK 0x00000001L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF1_FLR_PROTECT_MASK 0x00000002L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF2_FLR_PROTECT_MASK 0x00000004L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF3_FLR_PROTECT_MASK 0x00000008L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF4_FLR_PROTECT_MASK 0x00000010L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF5_FLR_PROTECT_MASK 0x00000020L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF6_FLR_PROTECT_MASK 0x00000040L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF7_FLR_PROTECT_MASK 0x00000080L +#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_SOFTPF_FLR_PROTECT_MASK 0x80000000L +//BIF_DEV0_PF1_VF_FLR_PROTECT +#define BIF_DEV0_PF1_VF_FLR_PROTECT__DEV0_PF1_VF0_FLR_PROTECT__SHIFT 0x0 +#define BIF_DEV0_PF1_VF_FLR_PROTECT__DEV0_PF1_VF0_FLR_PROTECT_MASK 0x00000001L +//BIF_SRIOVEN_SET_INTR_STS +#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF0_SRIOVEN_SET_INTR_STS__SHIFT 0x0 +#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF1_SRIOVEN_SET_INTR_STS__SHIFT 0x1 +#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF0_SRIOVEN_SET_INTR_STS_MASK 0x00000001L +#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF1_SRIOVEN_SET_INTR_STS_MASK 0x00000002L +//BIF_SRIOVEN_CLR_INTR_STS +#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF0_SRIOVEN_CLR_INTR_STS__SHIFT 0x0 +#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF1_SRIOVEN_CLR_INTR_STS__SHIFT 0x1 +#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF0_SRIOVEN_CLR_INTR_STS_MASK 0x00000001L +#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF1_SRIOVEN_CLR_INTR_STS_MASK 0x00000002L +//BIF_SRIOVEN_SET_INTR_MASK +#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF0_SRIOVEN_SET_INTR_MASK__SHIFT 0x0 +#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF1_SRIOVEN_SET_INTR_MASK__SHIFT 0x1 +#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF0_SRIOVEN_SET_INTR_MASK_MASK 0x00000001L +#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF1_SRIOVEN_SET_INTR_MASK_MASK 0x00000002L +//BIF_SRIOVEN_CLR_INTR_MASK +#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF0_SRIOVEN_CLR_INTR_MASK__SHIFT 0x0 +#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF1_SRIOVEN_CLR_INTR_MASK__SHIFT 0x1 +#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF0_SRIOVEN_CLR_INTR_MASK_MASK 0x00000001L +#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF1_SRIOVEN_CLR_INTR_MASK_MASK 0x00000002L +//BIF_PORT0_DSTATE_VALUE +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF0_RST_VF_FLR_IDLE +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF0_TRANS_IDLE__SHIFT 0x0 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF1_TRANS_IDLE__SHIFT 0x1 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF2_TRANS_IDLE__SHIFT 0x2 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF3_TRANS_IDLE__SHIFT 0x3 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF4_TRANS_IDLE__SHIFT 0x4 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF5_TRANS_IDLE__SHIFT 0x5 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF6_TRANS_IDLE__SHIFT 0x6 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF7_TRANS_IDLE__SHIFT 0x7 +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF0_TRANS_IDLE_MASK 0x00000001L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF1_TRANS_IDLE_MASK 0x00000002L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF2_TRANS_IDLE_MASK 0x00000004L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF3_TRANS_IDLE_MASK 0x00000008L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF4_TRANS_IDLE_MASK 0x00000010L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF5_TRANS_IDLE_MASK 0x00000020L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF6_TRANS_IDLE_MASK 0x00000040L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF7_TRANS_IDLE_MASK 0x00000080L +#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__SOFTPF_TRANS_IDLE_MASK 0x80000000L +//BIF_DEV0_PF1_RST_VF_FLR_IDLE +#define BIF_DEV0_PF1_RST_VF_FLR_IDLE__DEV0_PF1_VF0_TRANS_IDLE__SHIFT 0x0 +#define BIF_DEV0_PF1_RST_VF_FLR_IDLE__DEV0_PF1_VF0_TRANS_IDLE_MASK 0x00000001L +//BIF_DEV0_PF0_VF_FLR_INTR_STS +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF0_FLR_INTR_STS__SHIFT 0x0 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF1_FLR_INTR_STS__SHIFT 0x1 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF2_FLR_INTR_STS__SHIFT 0x2 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF3_FLR_INTR_STS__SHIFT 0x3 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF4_FLR_INTR_STS__SHIFT 0x4 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF5_FLR_INTR_STS__SHIFT 0x5 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF6_FLR_INTR_STS__SHIFT 0x6 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF7_FLR_INTR_STS__SHIFT 0x7 +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF0_FLR_INTR_STS_MASK 0x00000001L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF1_FLR_INTR_STS_MASK 0x00000002L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF2_FLR_INTR_STS_MASK 0x00000004L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF3_FLR_INTR_STS_MASK 0x00000008L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF4_FLR_INTR_STS_MASK 0x00000010L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF5_FLR_INTR_STS_MASK 0x00000020L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF6_FLR_INTR_STS_MASK 0x00000040L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF7_FLR_INTR_STS_MASK 0x00000080L +#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_SOFTPF_FLR_INTR_STS_MASK 0x80000000L +//BIF_DEV0_PF1_VF_FLR_INTR_STS +#define BIF_DEV0_PF1_VF_FLR_INTR_STS__DEV0_PF1_VF0_FLR_INTR_STS__SHIFT 0x0 +#define BIF_DEV0_PF1_VF_FLR_INTR_STS__DEV0_PF1_VF0_FLR_INTR_STS_MASK 0x00000001L +//BIF_DEV0_PF0_VF_FLR_RST +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST__SHIFT 0x0 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST__SHIFT 0x1 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST__SHIFT 0x2 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST__SHIFT 0x3 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST__SHIFT 0x6 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST__SHIFT 0x1f +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST_MASK 0x00000001L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST_MASK 0x00000002L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST_MASK 0x00000004L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST_MASK 0x00000008L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST_MASK 0x00000040L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST_MASK 0x80000000L +//BIF_DEV0_PF1_VF_FLR_RST +#define BIF_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST__SHIFT 0x0 +#define BIF_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST_MASK 0x00000001L + + +// addressBlock: nbif0_nbif0_bif_misc_bif_misc_regblk +//DOE_PRV_CTRL0_DEV0F0 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_INT_MSG_NUMBER_DEV0F0__SHIFT 0x0 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WRITE_THRESHOLD_DEV0F0__SHIFT 0xb +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_READ_THRESHOLD_DEV0F0__SHIFT 0x10 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WOT_INTM_DEV0F0__SHIFT 0x15 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ROT_INTM_DEV0F0__SHIFT 0x16 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ABT_INTM_DEV0F0__SHIFT 0x17 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_GO_INTM_DEV0F0__SHIFT 0x18 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_PSN_INTM_DEV0F0__SHIFT 0x19 +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_RUDF_INTM_DEV0F0__SHIFT 0x1a +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_INT_MSG_NUMBER_DEV0F0_MASK 0x000007FFL +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WRITE_THRESHOLD_DEV0F0_MASK 0x0000F800L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_READ_THRESHOLD_DEV0F0_MASK 0x001F0000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WOT_INTM_DEV0F0_MASK 0x00200000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ROT_INTM_DEV0F0_MASK 0x00400000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ABT_INTM_DEV0F0_MASK 0x00800000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_GO_INTM_DEV0F0_MASK 0x01000000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_PSN_INTM_DEV0F0_MASK 0x02000000L +#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_RUDF_INTM_DEV0F0_MASK 0x04000000L +//DOE_PRV_CMD_DEV0F0 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_ABORT_DEV0F0__SHIFT 0x0 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ERR_SET_DEV0F0__SHIFT 0x1 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DATA_REMAIN_DEV0F0__SHIFT 0x2 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DOE_RST_DEV0F0__SHIFT 0x8 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_NORSP_DEV0F0__SHIFT 0x9 +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ASYNC_MSG_STS_DEV0F0__SHIFT 0xa +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_ABORT_DEV0F0_MASK 0x00000001L +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ERR_SET_DEV0F0_MASK 0x00000002L +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DATA_REMAIN_DEV0F0_MASK 0x000000FCL +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DOE_RST_DEV0F0_MASK 0x00000100L +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_NORSP_DEV0F0_MASK 0x00000200L +#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ASYNC_MSG_STS_DEV0F0_MASK 0x00000400L +//DOE_PRV_WDATA_DEV0F0 +#define DOE_PRV_WDATA_DEV0F0__DOE_PRV_DATA_PUSH_DEV0F0__SHIFT 0x0 +#define DOE_PRV_WDATA_DEV0F0__DOE_PRV_DATA_PUSH_DEV0F0_MASK 0xFFFFFFFFL +//DOE_PRV_STS_DEV0F0 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_WRITE_OVER_THRESHOLD_DEV0F0__SHIFT 0x0 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_READ_UNDER_THRESHOLD_DEV0F0__SHIFT 0x1 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_ABORT_DET_DEV0F0__SHIFT 0x2 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_GO_DET_DEV0F0__SHIFT 0x3 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_PSN_DET_DEV0F0__SHIFT 0x4 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_UNDERFLOW_DET_DEV0F0__SHIFT 0x5 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_OCCUP_WMBOX_DEV0F0__SHIFT 0x6 +#define DOE_PRV_STS_DEV0F0__DOE_PRV_VACA_RMBOX_DEV0F0__SHIFT 0xc +#define DOE_PRV_STS_DEV0F0__DOE_PRV_WRITE_OVER_THRESHOLD_DEV0F0_MASK 0x00000001L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_READ_UNDER_THRESHOLD_DEV0F0_MASK 0x00000002L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_ABORT_DET_DEV0F0_MASK 0x00000004L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_GO_DET_DEV0F0_MASK 0x00000008L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_PSN_DET_DEV0F0_MASK 0x00000010L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_UNDERFLOW_DET_DEV0F0_MASK 0x00000020L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_OCCUP_WMBOX_DEV0F0_MASK 0x00000FC0L +#define DOE_PRV_STS_DEV0F0__DOE_PRV_VACA_RMBOX_DEV0F0_MASK 0x0003F000L +//DOE_PRV_RDATA_DEV0F0 +#define DOE_PRV_RDATA_DEV0F0__DOE_PRV_RDATA_WMBOX_DEV0F0__SHIFT 0x0 +#define DOE_PRV_RDATA_DEV0F0__DOE_PRV_RDATA_WMBOX_DEV0F0_MASK 0xFFFFFFFFL +//NBIF_RC_INTR_CNTL +#define NBIF_RC_INTR_CNTL__RC_ERR_INTR_TRIG_DEV0__SHIFT 0x0 +#define NBIF_RC_INTR_CNTL__RC_ERR_INTR_TRIG_DEV0_MASK 0x00000001L +//BIF_DEV0_PF0_TDISP_CNTL +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF1_TDISP_CNTL +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF0_TDISP_CNTL +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF1_TDISP_CNTL +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF2_TDISP_CNTL +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF3_TDISP_CNTL +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF4_TDISP_CNTL +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF5_TDISP_CNTL +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF6_TDISP_CNTL +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF0_VF7_TDISP_CNTL +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_INTERFACE_ERROR_MASK 0x00000100L +//BIF_DEV0_PF1_VF0_TDISP_CNTL +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_TDISP_STATE__SHIFT 0x0 +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_LOCK_INTERFACE_REQUEST__SHIFT 0x4 +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_START_INTERFACE_REQUEST__SHIFT 0x5 +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_STOP_INTERFACE_REQUEST__SHIFT 0x7 +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_INTERFACE_ERROR__SHIFT 0x8 +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_TDISP_STATE_MASK 0x00000007L +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_LOCK_INTERFACE_REQUEST_MASK 0x00000010L +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_START_INTERFACE_REQUEST_MASK 0x00000020L +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_STOP_INTERFACE_REQUEST_MASK 0x00000080L +#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_INTERFACE_ERROR_MASK 0x00000100L +//BIF_TDISP_ERROR_DEV0_PF0_INST0 +#define BIF_TDISP_ERROR_DEV0_PF0_INST0__BIF_TDISP_ERROR_DEV0_PF0_INST0__SHIFT 0x0 +#define BIF_TDISP_ERROR_DEV0_PF0_INST0__BIF_TDISP_ERROR_DEV0_PF0_INST0_MASK 0xFFFFFFFFL +//BIF_TDISP_ERROR_DEV0_PF1_INST0 +#define BIF_TDISP_ERROR_DEV0_PF1_INST0__BIF_TDISP_ERROR_DEV0_PF1_INST0__SHIFT 0x0 +#define BIF_TDISP_ERROR_DEV0_PF1_INST0__BIF_TDISP_ERROR_DEV0_PF1_INST0_MASK 0xFFFFFFFFL +//BIF_TDISP_UNLOCKED_DEV0_PF0_INST0 +#define BIF_TDISP_UNLOCKED_DEV0_PF0_INST0__BIF_TDISP_UNLOCKED_DEV0_PF0_INST0__SHIFT 0x0 +#define BIF_TDISP_UNLOCKED_DEV0_PF0_INST0__BIF_TDISP_UNLOCKED_DEV0_PF0_INST0_MASK 0xFFFFFFFFL +//BIF_TDISP_UNLOCKED_DEV0_PF1_INST0 +#define BIF_TDISP_UNLOCKED_DEV0_PF1_INST0__BIF_TDISP_UNLOCKED_DEV0_PF1_INST0__SHIFT 0x0 +#define BIF_TDISP_UNLOCKED_DEV0_PF1_INST0__BIF_TDISP_UNLOCKED_DEV0_PF1_INST0_MASK 0xFFFFFFFFL +//BIF_TDISP_MISC_CNTL_DEV0 +#define BIF_TDISP_MISC_CNTL_DEV0__BIF_RC_CONFIG_MONITOR_EN_DEV0__SHIFT 0x0 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF0__SHIFT 0x5 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF0__SHIFT 0x6 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF0__SHIFT 0x7 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF0__SHIFT 0x8 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF1__SHIFT 0x9 +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF1__SHIFT 0xa +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF1__SHIFT 0xb +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF1__SHIFT 0xc +#define BIF_TDISP_MISC_CNTL_DEV0__BIF_RC_CONFIG_MONITOR_EN_DEV0_MASK 0x00000001L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF0_MASK 0x00000020L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF0_MASK 0x00000040L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF0_MASK 0x00000080L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF0_MASK 0x00000100L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF1_MASK 0x00000200L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF1_MASK 0x00000400L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF1_MASK 0x00000800L +#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF1_MASK 0x00001000L +//BIF_TDISP_MISC_CNTL +#define BIF_TDISP_MISC_CNTL__BIF_MSI_MSIX_IDE_TBIT_OVERRIDE__SHIFT 0x0 +#define BIF_TDISP_MISC_CNTL__REMOTE_TDISP_STATE_VECTOR_CLR__SHIFT 0x1 +#define BIF_TDISP_MISC_CNTL__NBIF_GMI_TDISP_REMOTE_TX_EN__SHIFT 0x3 +#define BIF_TDISP_MISC_CNTL__BIF_TRUSTED_IO_ERR_Intr_0_MASK__SHIFT 0x4 +#define BIF_TDISP_MISC_CNTL__DSPT_CFG_RST_TRIG_TO_UNLOCK_MASK__SHIFT 0xa +#define BIF_TDISP_MISC_CNTL__EP_CFG_RST_TRIG_TO_UNLOCK_MASK__SHIFT 0xb +#define BIF_TDISP_MISC_CNTL__TDISP_ERR_AER_DIS__SHIFT 0xc +#define BIF_TDISP_MISC_CNTL__TDISP_ERR_PRGR_AER_EN__SHIFT 0xd +#define BIF_TDISP_MISC_CNTL__BIF_TBIT_FOR_RUN_BIH_MEM__SHIFT 0xe +#define BIF_TDISP_MISC_CNTL__BIF_XT1_FOR_RUN_BIH_MEM__SHIFT 0xf +#define BIF_TDISP_MISC_CNTL__BIF_MSI_MSIX_IDE_TBIT_OVERRIDE_MASK 0x00000001L +#define BIF_TDISP_MISC_CNTL__REMOTE_TDISP_STATE_VECTOR_CLR_MASK 0x00000002L +#define BIF_TDISP_MISC_CNTL__NBIF_GMI_TDISP_REMOTE_TX_EN_MASK 0x00000008L +#define BIF_TDISP_MISC_CNTL__BIF_TRUSTED_IO_ERR_Intr_0_MASK_MASK 0x00000010L +#define BIF_TDISP_MISC_CNTL__DSPT_CFG_RST_TRIG_TO_UNLOCK_MASK_MASK 0x00000400L +#define BIF_TDISP_MISC_CNTL__EP_CFG_RST_TRIG_TO_UNLOCK_MASK_MASK 0x00000800L +#define BIF_TDISP_MISC_CNTL__TDISP_ERR_AER_DIS_MASK 0x00001000L +#define BIF_TDISP_MISC_CNTL__TDISP_ERR_PRGR_AER_EN_MASK 0x00002000L +#define BIF_TDISP_MISC_CNTL__BIF_TBIT_FOR_RUN_BIH_MEM_MASK 0x00004000L +#define BIF_TDISP_MISC_CNTL__BIF_XT1_FOR_RUN_BIH_MEM_MASK 0x00008000L +//BIF_RCC_IDE_TDISP_CNTL +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_CHECK_EN__SHIFT 0x0 +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_FOR_UNLOCK_CHECK_EN__SHIFT 0x1 +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_CHECK_EN__SHIFT 0x2 +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_CHECK_EN_MASK 0x00000001L +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_FOR_UNLOCK_CHECK_EN_MASK 0x00000002L +#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_CHECK_EN_MASK 0x00000004L +//BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT 0x0 +#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK 0xFFFFFFFFL +//BIF_SYSTEM_EN +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0__SHIFT 0x0 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF0__SHIFT 0x1 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF1__SHIFT 0x2 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF2__SHIFT 0x3 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF3__SHIFT 0x4 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF4__SHIFT 0x5 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF5__SHIFT 0x6 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF6__SHIFT 0x7 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF7__SHIFT 0x8 +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_MASK 0x00000001L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF0_MASK 0x00000002L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF1_MASK 0x00000004L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF2_MASK 0x00000008L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF3_MASK 0x00000010L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF4_MASK 0x00000020L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF5_MASK 0x00000040L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF6_MASK 0x00000080L +#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF7_MASK 0x00000100L +//BIF_MASK_SYSTEM_EN +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0__SHIFT 0x0 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF0__SHIFT 0x1 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF1__SHIFT 0x2 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF2__SHIFT 0x3 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF3__SHIFT 0x4 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF4__SHIFT 0x5 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF5__SHIFT 0x6 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF6__SHIFT 0x7 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF7__SHIFT 0x8 +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_MASK 0x00000001L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF0_MASK 0x00000002L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF1_MASK 0x00000004L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF2_MASK 0x00000008L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF3_MASK 0x00000010L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF4_MASK 0x00000020L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF5_MASK 0x00000040L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF6_MASK 0x00000080L +#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF7_MASK 0x00000100L +//GPUIOV_SCH0 +#define GPUIOV_SCH0__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH0__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH1 +#define GPUIOV_SCH1__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH1__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH2 +#define GPUIOV_SCH2__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH2__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH3 +#define GPUIOV_SCH3__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH3__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH4 +#define GPUIOV_SCH4__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH4__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH5 +#define GPUIOV_SCH5__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH5__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH6 +#define GPUIOV_SCH6__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH6__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH7 +#define GPUIOV_SCH7__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH7__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH8 +#define GPUIOV_SCH8__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH8__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH9 +#define GPUIOV_SCH9__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH9__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH10 +#define GPUIOV_SCH10__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH10__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH11 +#define GPUIOV_SCH11__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH11__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH12 +#define GPUIOV_SCH12__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH12__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH13 +#define GPUIOV_SCH13__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH13__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH14 +#define GPUIOV_SCH14__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH14__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH15 +#define GPUIOV_SCH15__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH15__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH16 +#define GPUIOV_SCH16__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH16__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH17 +#define GPUIOV_SCH17__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH17__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH18 +#define GPUIOV_SCH18__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH18__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_SCH19 +#define GPUIOV_SCH19__REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_SCH19__REMAP_ADDR_MASK 0x001FFFFFL +//GPUIOV_MMHUB_P2P_CNTL +#define GPUIOV_MMHUB_P2P_CNTL__GPUIOV_MMHUB_P2P_ENABLE_REMAP_ADDR__SHIFT 0x0 +#define GPUIOV_MMHUB_P2P_CNTL__GPUIOV_MMHUB_P2P_ENABLE_REMAP_ADDR_MASK 0x000FFFFFL +//BIF_AER_INTR_CTRL +#define BIF_AER_INTR_CTRL__BIF_AER_INTR_MASK__SHIFT 0x0 +#define BIF_AER_INTR_CTRL__BIF_AER_SMN_POSTED__SHIFT 0x1 +#define BIF_AER_INTR_CTRL__BIF_AER_SMN_WDATA_SEL__SHIFT 0x2 +#define BIF_AER_INTR_CTRL__BIF_AER_INTR_MASK_MASK 0x00000001L +#define BIF_AER_INTR_CTRL__BIF_AER_SMN_POSTED_MASK 0x00000002L +#define BIF_AER_INTR_CTRL__BIF_AER_SMN_WDATA_SEL_MASK 0x00000004L +//BIF_AER_INTR_STS +#define BIF_AER_INTR_STS__BIF_AER_INTR_STS__SHIFT 0x0 +#define BIF_AER_INTR_STS__BIF_AER_INTR_STS_MASK 0x00000001L +//BIF_PCIE_MSG_CTRL +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VALID__SHIFT 0x0 +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_PORTID__SHIFT 0x1 +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VF_VALID__SHIFT 0x3 +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VFID__SHIFT 0x4 +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VALID_MASK 0x00000001L +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_PORTID_MASK 0x00000006L +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VF_VALID_MASK 0x00000008L +#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VFID_MASK 0x00003FF0L +//BIF_PCIE_MSG_HEADER_DW0 +#define BIF_PCIE_MSG_HEADER_DW0__BIF_PCIE_MSG_HEADER_DW0__SHIFT 0x0 +#define BIF_PCIE_MSG_HEADER_DW0__BIF_PCIE_MSG_HEADER_DW0_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_HEADER_DW1 +#define BIF_PCIE_MSG_HEADER_DW1__BIF_PCIE_MSG_HEADER_DW1__SHIFT 0x0 +#define BIF_PCIE_MSG_HEADER_DW1__BIF_PCIE_MSG_HEADER_DW1_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_HEADER_DW2 +#define BIF_PCIE_MSG_HEADER_DW2__BIF_PCIE_MSG_HEADER_DW2__SHIFT 0x0 +#define BIF_PCIE_MSG_HEADER_DW2__BIF_PCIE_MSG_HEADER_DW2_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_HEADER_DW3 +#define BIF_PCIE_MSG_HEADER_DW3__BIF_PCIE_MSG_HEADER_DW3__SHIFT 0x0 +#define BIF_PCIE_MSG_HEADER_DW3__BIF_PCIE_MSG_HEADER_DW3_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_DATA_DW0 +#define BIF_PCIE_MSG_DATA_DW0__BIF_PCIE_MSG_DATA_DW0__SHIFT 0x0 +#define BIF_PCIE_MSG_DATA_DW0__BIF_PCIE_MSG_DATA_DW0_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_DATA_DW1 +#define BIF_PCIE_MSG_DATA_DW1__BIF_PCIE_MSG_DATA_DW1__SHIFT 0x0 +#define BIF_PCIE_MSG_DATA_DW1__BIF_PCIE_MSG_DATA_DW1_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_DATA_DW2 +#define BIF_PCIE_MSG_DATA_DW2__BIF_PCIE_MSG_DATA_DW2__SHIFT 0x0 +#define BIF_PCIE_MSG_DATA_DW2__BIF_PCIE_MSG_DATA_DW2_MASK 0xFFFFFFFFL +//BIF_PCIE_MSG_DATA_DW3 +#define BIF_PCIE_MSG_DATA_DW3__BIF_PCIE_MSG_DATA_DW3__SHIFT 0x0 +#define BIF_PCIE_MSG_DATA_DW3__BIF_PCIE_MSG_DATA_DW3_MASK 0xFFFFFFFFL +//BIFC_SEC_AER_SMN_CTRL0 +#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_ADDR__SHIFT 0x0 +#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_APER_ID__SHIFT 0x14 +#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_ADDR_MASK 0x000FFFFFL +#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_APER_ID_MASK 0xFFF00000L +//BIFC_SEC_AER_SMN_CTRL1 +#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_INT_REQ_MCM_ADDR__SHIFT 0x0 +#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_SMN_SEC_SEL__SHIFT 0x10 +#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_INT_REQ_MCM_ADDR_MASK 0x0000FFFFL +#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_SMN_SEC_SEL_MASK 0x000F0000L +//BIFC_SEC_AER_SMN_CTRL2 +#define BIFC_SEC_AER_SMN_CTRL2__BIF_AER_INT_REQ_WDATA__SHIFT 0x0 +#define BIFC_SEC_AER_SMN_CTRL2__BIF_AER_INT_REQ_WDATA_MASK 0xFFFFFFFFL +//BIF_PCIE_ERR_CTRL0 +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF_NUM__SHIFT 0x0 +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF__SHIFT 0x7 +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_PF_NUM__SHIFT 0x8 +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF_NUM_MASK 0x0000007FL +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF_MASK 0x00000080L +#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_PF_NUM_MASK 0x00000700L +//BIF_PCIE_ERR_CTRL1 +#define BIF_PCIE_ERR_CTRL1__BIF_CORR_ERR_EN__SHIFT 0x0 +#define BIF_PCIE_ERR_CTRL1__BIF_NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_PCIE_ERR_CTRL1__BIF_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_PCIE_ERR_CTRL1__BIF_USR_REPORT_EN__SHIFT 0x3 +#define BIF_PCIE_ERR_CTRL1__BIF_SERR_EN__SHIFT 0x4 +#define BIF_PCIE_ERR_CTRL1__BIF_MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_PCIE_ERR_CTRL1__BIF_SIGNALED_SYSTEM_ERROR__SHIFT 0x9 +#define BIF_PCIE_ERR_CTRL1__BIF_PARITY_ERROR_DETECTED__SHIFT 0xa +#define BIF_PCIE_ERR_CTRL1__BIF_PCIE_DEVICE_STATUS__SHIFT 0x10 +#define BIF_PCIE_ERR_CTRL1__BIF_CORR_ERR_EN_MASK 0x00000001L +#define BIF_PCIE_ERR_CTRL1__BIF_NON_FATAL_ERR_EN_MASK 0x00000002L +#define BIF_PCIE_ERR_CTRL1__BIF_FATAL_ERR_EN_MASK 0x00000004L +#define BIF_PCIE_ERR_CTRL1__BIF_USR_REPORT_EN_MASK 0x00000008L +#define BIF_PCIE_ERR_CTRL1__BIF_SERR_EN_MASK 0x00000010L +#define BIF_PCIE_ERR_CTRL1__BIF_MASTER_DATA_PARITY_ERROR_MASK 0x00000100L +#define BIF_PCIE_ERR_CTRL1__BIF_SIGNALED_SYSTEM_ERROR_MASK 0x00000200L +#define BIF_PCIE_ERR_CTRL1__BIF_PARITY_ERROR_DETECTED_MASK 0x00000400L +#define BIF_PCIE_ERR_CTRL1__BIF_PCIE_DEVICE_STATUS_MASK 0xFFFF0000L +//BIF_PCIE_ERR_CTRL2 +#define BIF_PCIE_ERR_CTRL2__BIF_AER_FEP__SHIFT 0x0 +#define BIF_PCIE_ERR_CTRL2__BIF_AER_TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_PCIE_ERR_CTRL2__BIF_AER_LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_PCIE_ERR_CTRL2__BIF_AER_FEP_MASK 0x0000001FL +#define BIF_PCIE_ERR_CTRL2__BIF_AER_TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_PCIE_ERR_CTRL2__BIF_AER_LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_AER_UNCORR_ERR_STATUS +#define BIF_AER_UNCORR_ERR_STATUS__BIF_AER_UNCORR_ERR_STATUS__SHIFT 0x0 +#define BIF_AER_UNCORR_ERR_STATUS__BIF_AER_UNCORR_ERR_STATUS_MASK 0xFFFFFFFFL +//BIF_AER_UNCORR_ERR_MASK +#define BIF_AER_UNCORR_ERR_MASK__BIF_AER_UNCORR_ERR_MASK__SHIFT 0x0 +#define BIF_AER_UNCORR_ERR_MASK__BIF_AER_UNCORR_ERR_MASK_MASK 0xFFFFFFFFL +//BIF_AER_UNCORR_ERR_SEVERITY +#define BIF_AER_UNCORR_ERR_SEVERITY__BIF_AER_UNCORR_ERR_SEVERITY__SHIFT 0x0 +#define BIF_AER_UNCORR_ERR_SEVERITY__BIF_AER_UNCORR_ERR_SEVERITY_MASK 0xFFFFFFFFL +//BIF_AER_CORR_ERR_STATUS +#define BIF_AER_CORR_ERR_STATUS__BIF_AER_CORR_ERR_STATUS__SHIFT 0x0 +#define BIF_AER_CORR_ERR_STATUS__BIF_AER_CORR_ERR_STATUS_MASK 0xFFFFFFFFL +//BIF_AER_CORR_ERR_MASK +#define BIF_AER_CORR_ERR_MASK__BIF_AER_CORR_ERR_MASK__SHIFT 0x0 +#define BIF_AER_CORR_ERR_MASK__BIF_AER_CORR_ERR_MASK_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_0 +#define RCC_EP_STICKY_RESTORE_0__RESTORE_PCIE_TLP_HDR_0__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_0__RESTORE_PCIE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_1 +#define RCC_EP_STICKY_RESTORE_1__RESTORE_PCIE_TLP_HDR_1__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_1__RESTORE_PCIE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_2 +#define RCC_EP_STICKY_RESTORE_2__RESTORE_PCIE_TLP_HDR_2__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_2__RESTORE_PCIE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_3 +#define RCC_EP_STICKY_RESTORE_3__RESTORE_PCIE_TLP_HDR_3__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_3__RESTORE_PCIE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_4 +#define RCC_EP_STICKY_RESTORE_4__RESTORE_PCIE_TLP_HDR_4__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_4__RESTORE_PCIE_TLP_HDR_4_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_5 +#define RCC_EP_STICKY_RESTORE_5__RESTORE_PCIE_TLP_HDR_5__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_5__RESTORE_PCIE_TLP_HDR_5_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_6 +#define RCC_EP_STICKY_RESTORE_6__RESTORE_PCIE_TLP_HDR_6__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_6__RESTORE_PCIE_TLP_HDR_6_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_7 +#define RCC_EP_STICKY_RESTORE_7__RESTORE_PCIE_TLP_HDR_7__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_7__RESTORE_PCIE_TLP_HDR_7_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_8 +#define RCC_EP_STICKY_RESTORE_8__RESTORE_PCIE_TLP_HDR_8__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_8__RESTORE_PCIE_TLP_HDR_8_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_9 +#define RCC_EP_STICKY_RESTORE_9__RESTORE_PCIE_TLP_HDR_9__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_9__RESTORE_PCIE_TLP_HDR_9_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_10 +#define RCC_EP_STICKY_RESTORE_10__RESTORE_PCIE_TLP_HDR_10__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_10__RESTORE_PCIE_TLP_HDR_10_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_11 +#define RCC_EP_STICKY_RESTORE_11__RESTORE_PCIE_TLP_HDR_11__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_11__RESTORE_PCIE_TLP_HDR_11_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_12 +#define RCC_EP_STICKY_RESTORE_12__RESTORE_PCIE_TLP_HDR_12__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_12__RESTORE_PCIE_TLP_HDR_12_MASK 0xFFFFFFFFL +//RCC_EP_STICKY_RESTORE_13 +#define RCC_EP_STICKY_RESTORE_13__RESTORE_PCIE_TLP_HDR_13__SHIFT 0x0 +#define RCC_EP_STICKY_RESTORE_13__RESTORE_PCIE_TLP_HDR_13_MASK 0xFFFFFFFFL +//BIF_DEVICE3_STATUS +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_INITIAL_LINK_WIDTH__SHIFT 0x0 +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_SEGMENT_CAPTURED__SHIFT 0x3 +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_REMOTE_L0P_SUPPORTED__SHIFT 0x4 +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_INITIAL_LINK_WIDTH_MASK 0x00000007L +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_SEGMENT_CAPTURED_MASK 0x00000008L +#define BIF_DEVICE3_STATUS__BIF_DEVICE3_REMOTE_L0P_SUPPORTED_MASK 0x00000010L +//BIFC_SEC_MCTP_SMN_CTRL0 +#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_ADDR__SHIFT 0x0 +#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_APER_ID__SHIFT 0x14 +#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_ADDR_MASK 0x000FFFFFL +#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_APER_ID_MASK 0xFFF00000L +//BIFC_SEC_MCTP_SMN_CTRL1 +#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_INT_REQ_MCM_ADDR__SHIFT 0x0 +#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_SMN_SEC_SEL__SHIFT 0x10 +#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_INT_REQ_MCM_ADDR_MASK 0x0000FFFFL +#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_SMN_SEC_SEL_MASK 0x000F0000L +//NBIF_MCTP_GENERIC_CNTL +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_SUPPORT__SHIFT 0x0 +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_ROUTING_CODE_CHECK__SHIFT 0x1 +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_RBID_CPLID_CNTL__SHIFT 0x2 +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_SUPPORT_MASK 0x00000001L +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_ROUTING_CODE_CHECK_MASK 0x00000002L +#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_RBID_CPLID_CNTL_MASK 0x00000004L +//NBIF_MCTP_GENERIC_STATUS +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_ERR_FLAG__SHIFT 0x0 +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_EMPTY_STATUS__SHIFT 0x1 +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_FULL_STATUS__SHIFT 0x2 +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_ERR_FLAG_MASK 0x00000001L +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_EMPTY_STATUS_MASK 0x00000002L +#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_FULL_STATUS_MASK 0x00000004L +//SDPVW_UPDATE_EN +#define SDPVW_UPDATE_EN__SDPVW_UPDATE_EN__SHIFT 0x0 +#define SDPVW_UPDATE_EN__SWUS_SECBUSRST_SET_EN__SHIFT 0x1 +#define SDPVW_UPDATE_EN__SDPVW_UPDATE_EN_MASK 0x01L +#define SDPVW_UPDATE_EN__SWUS_SECBUSRST_SET_EN_MASK 0x02L +//REGS_ROM_OFFSET_CTRL +#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT 0x0 +#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK 0x7FL +//BIFL_SEC_RAS_POISON_DATA_DROP_CTRL +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF0_POISON_DATA_DROP_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF1_POISON_DATA_DROP_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF2_POISON_DATA_DROP_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF3_POISON_DATA_DROP_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF4_POISON_DATA_DROP_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF5_POISON_DATA_DROP_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF6_POISON_DATA_DROP_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF7_POISON_DATA_DROP_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF8_POISON_DATA_DROP_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF9_POISON_DATA_DROP_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF10_POISON_DATA_DROP_EN__SHIFT 0xa +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF11_POISON_DATA_DROP_EN__SHIFT 0xb +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF12_POISON_DATA_DROP_EN__SHIFT 0xc +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF13_POISON_DATA_DROP_EN__SHIFT 0xd +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF14_POISON_DATA_DROP_EN__SHIFT 0xe +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF15_POISON_DATA_DROP_EN__SHIFT 0xf +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF16_POISON_DATA_DROP_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF17_POISON_DATA_DROP_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF18_POISON_DATA_DROP_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF19_POISON_DATA_DROP_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF0_POISON_DATA_DROP_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF1_POISON_DATA_DROP_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF2_POISON_DATA_DROP_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF3_POISON_DATA_DROP_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF4_POISON_DATA_DROP_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF5_POISON_DATA_DROP_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF6_POISON_DATA_DROP_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF7_POISON_DATA_DROP_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF8_POISON_DATA_DROP_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF9_POISON_DATA_DROP_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF10_POISON_DATA_DROP_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF11_POISON_DATA_DROP_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF12_POISON_DATA_DROP_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF13_POISON_DATA_DROP_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF14_POISON_DATA_DROP_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF15_POISON_DATA_DROP_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF16_POISON_DATA_DROP_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF17_POISON_DATA_DROP_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF18_POISON_DATA_DROP_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF19_POISON_DATA_DROP_EN_MASK 0x00080000L +//REGS_INDEX_DATA_PAIR_CTRL +#define REGS_INDEX_DATA_PAIR_CTRL__MM_DATA_DIS__SHIFT 0x0 +#define REGS_INDEX_DATA_PAIR_CTRL__SYSHUB_DATA_DIS__SHIFT 0x1 +#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA_DIS__SHIFT 0x2 +#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA2_DIS__SHIFT 0x3 +#define REGS_INDEX_DATA_PAIR_CTRL__MM_DATA_DIS_MASK 0x00000001L +#define REGS_INDEX_DATA_PAIR_CTRL__SYSHUB_DATA_DIS_MASK 0x00000002L +#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA_DIS_MASK 0x00000004L +#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA2_DIS_MASK 0x00000008L +//BIFL_SEC_RAS_RESPONSE_DROP_CTRL +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF0_RESPONSE_DROP_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF1_RESPONSE_DROP_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF2_RESPONSE_DROP_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF3_RESPONSE_DROP_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF4_RESPONSE_DROP_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF5_RESPONSE_DROP_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF6_RESPONSE_DROP_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF7_RESPONSE_DROP_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF8_RESPONSE_DROP_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF9_RESPONSE_DROP_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF10_RESPONSE_DROP_EN__SHIFT 0xa +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF11_RESPONSE_DROP_EN__SHIFT 0xb +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF12_RESPONSE_DROP_EN__SHIFT 0xc +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF13_RESPONSE_DROP_EN__SHIFT 0xd +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF14_RESPONSE_DROP_EN__SHIFT 0xe +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF15_RESPONSE_DROP_EN__SHIFT 0xf +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF16_RESPONSE_DROP_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF17_RESPONSE_DROP_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF18_RESPONSE_DROP_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF19_RESPONSE_DROP_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF0_RESPONSE_DROP_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF1_RESPONSE_DROP_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF2_RESPONSE_DROP_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF3_RESPONSE_DROP_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF4_RESPONSE_DROP_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF5_RESPONSE_DROP_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF6_RESPONSE_DROP_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF7_RESPONSE_DROP_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF8_RESPONSE_DROP_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF9_RESPONSE_DROP_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF10_RESPONSE_DROP_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF11_RESPONSE_DROP_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF12_RESPONSE_DROP_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF13_RESPONSE_DROP_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF14_RESPONSE_DROP_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF15_RESPONSE_DROP_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF16_RESPONSE_DROP_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF17_RESPONSE_DROP_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF18_RESPONSE_DROP_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF19_RESPONSE_DROP_EN_MASK 0x00080000L +//BIFC_SEC_MCA_SMN_CTRL0 +#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR__SHIFT 0x0 +#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID__SHIFT 0x14 +#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR_MASK 0x000FFFFFL +#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID_MASK 0xFFF00000L +//BIFC_SEC_MCA_SMN_CTRL1 +#define BIFC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR__SHIFT 0x0 +#define BIFC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_SEL__SHIFT 0x10 +#define BIFC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR_MASK 0x0000FFFFL +#define BIFC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_SEL_MASK 0x000F0000L +//BIFL_SEC_RAS_POISON_DBUG_CTRL +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN__SHIFT 0xa +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN__SHIFT 0xb +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN__SHIFT 0xc +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN__SHIFT 0xd +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_POISON_DBUG_EN__SHIFT 0xe +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_POISON_DBUG_EN__SHIFT 0xf +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_POISON_DBUG_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_POISON_DBUG_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_POISON_DBUG_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_POISON_DBUG_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_POISON_DBUG_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_POISON_DBUG_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_POISON_DBUG_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_POISON_DBUG_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_POISON_DBUG_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_POISON_DBUG_EN_MASK 0x00080000L +//BIFL_SEC_RAS_PARITY_DBUG_CTRL +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN__SHIFT 0xa +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN__SHIFT 0xb +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN__SHIFT 0xc +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN__SHIFT 0xd +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_PARITY_DBUG_EN__SHIFT 0xe +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_PARITY_DBUG_EN__SHIFT 0xf +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_PARITY_DBUG_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_PARITY_DBUG_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_PARITY_DBUG_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_PARITY_DBUG_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_PARITY_DBUG_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_PARITY_DBUG_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_PARITY_DBUG_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_PARITY_DBUG_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_PARITY_DBUG_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_PARITY_DBUG_EN_MASK 0x00080000L +//BIFL_SEC_RAS_NTB_DBUG_CTRL +#define BIFL_SEC_RAS_NTB_DBUG_CTRL__BIFL_SEC_RAS_LEAF_NTB_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_NTB_DBUG_CTRL__BIFL_SEC_RAS_LEAF_NTB_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000001L +//BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xa +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xb +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xc +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xd +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xe +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xf +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00080000L +//BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x1 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x2 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x3 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x4 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x5 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x6 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x7 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x8 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x9 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xa +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xb +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xc +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xd +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xe +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xf +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x10 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x11 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x12 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x13 +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000001L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000002L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000004L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000008L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000010L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000020L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000040L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000080L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000100L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000200L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000400L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000800L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN_MASK 0x00001000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN_MASK 0x00002000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_TIMEOUT_DBUG_EN_MASK 0x00004000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_TIMEOUT_DBUG_EN_MASK 0x00008000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_TIMEOUT_DBUG_EN_MASK 0x00010000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_TIMEOUT_DBUG_EN_MASK 0x00020000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_TIMEOUT_DBUG_EN_MASK 0x00040000L +#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_TIMEOUT_DBUG_EN_MASK 0x00080000L +//BIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RUSER_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL +#define BIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RRESP_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RRESP_POISON_EN_MASK 0x000000FFL +//BIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL +#define BIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RUSER_POISON_EN__SHIFT 0x0 +#define BIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RUSER_POISON_EN_MASK 0x000000FFL +//NBIF_STRAP_BIOS_CNTL +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT 0x0 +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT 0x1 +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK 0x00000001L +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK 0x00000002L +//SMN_MST_NORMAL_SECURITY +#define SMN_MST_NORMAL_SECURITY__SMN_MST_NORMAL_RECURITY_SEL__SHIFT 0x0 +#define SMN_MST_NORMAL_SECURITY__SMN_MST_NORMAL_RECURITY_SEL_MASK 0x0000000FL +//OVERRIDE_TYPE_FOR_CHAIN_CTRL +#define OVERRIDE_TYPE_FOR_CHAIN_CTRL__OVERRIDE_TYPE_FOR_CHAIN__SHIFT 0x0 +#define OVERRIDE_TYPE_FOR_CHAIN_CTRL__OVERRIDE_TYPE_FOR_CHAIN_MASK 0x00000001L +//PROCESSING_HINT_SUPPORT_CNTL +#define PROCESSING_HINT_SUPPORT_CNTL__PH_MASK_EN__SHIFT 0x0 +#define PROCESSING_HINT_SUPPORT_CNTL__PH_MASK_EN_MASK 0x00000001L +//DEV0_PF0_VF0_MMIO0_FENCE +#define DEV0_PF0_VF0_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF0_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF0_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF0_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF1_MMIO0_FENCE +#define DEV0_PF0_VF1_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF1_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF1_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF1_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF2_MMIO0_FENCE +#define DEV0_PF0_VF2_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF2_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF2_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF2_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF3_MMIO0_FENCE +#define DEV0_PF0_VF3_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF3_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF3_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF3_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF4_MMIO0_FENCE +#define DEV0_PF0_VF4_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF4_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF4_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF4_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF5_MMIO0_FENCE +#define DEV0_PF0_VF5_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF5_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF5_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF5_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF6_MMIO0_FENCE +#define DEV0_PF0_VF6_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF6_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF6_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF6_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF7_MMIO0_FENCE +#define DEV0_PF0_VF7_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF0_VF7_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF0_VF7_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF0_VF7_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF0_VF_MMIO0_FENCE_RANGE0_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE0_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE1_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE1_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE2_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE2_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE3_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE3_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE4_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE4_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE5_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE5_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE6_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE6_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE7_START +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_VF_MMIO0_FENCE_RANGE7_END +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF0_MMIO0_FENCE +#define DEV0_PF1_VF0_MMIO0_FENCE__WR_ENABLE__SHIFT 0x0 +#define DEV0_PF1_VF0_MMIO0_FENCE__RD_ENABLE__SHIFT 0x10 +#define DEV0_PF1_VF0_MMIO0_FENCE__WR_ENABLE_MASK 0x0000FFFFL +#define DEV0_PF1_VF0_MMIO0_FENCE__RD_ENABLE_MASK 0xFFFF0000L +//DEV0_PF1_VF_MMIO0_FENCE_RANGE0_START +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE0_END +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE1_START +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE1_END +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE2_START +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE2_END +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE3_START +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_VF_MMIO0_FENCE_RANGE3_END +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_WR +#define DEV0_PF0_PF_MMIO0_FENCE_WR__ENABLE__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_WR__ENABLE_MASK 0xFFFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RD +#define DEV0_PF0_PF_MMIO0_FENCE_RD__ENABLE__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RD__ENABLE_MASK 0xFFFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE0_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE0_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE1_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE1_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE2_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE2_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE3_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE3_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE4_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE4_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE5_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE5_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE6_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE6_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE7_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE7_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE8_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE8_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE9_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE9_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE10_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE10_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE11_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE11_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE12_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE12_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE13_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE13_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE14_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE14_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE15_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE15_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE16_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE16_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE17_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE17_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE18_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE18_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE19_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE19_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE20_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE20_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE21_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE21_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE22_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE22_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE23_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE23_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE24_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE24_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE25_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE25_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE26_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE26_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE27_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE27_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE28_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE28_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE29_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE29_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE30_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE30_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE31_START +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF0_PF_MMIO0_FENCE_RANGE31_END +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_WR +#define DEV0_PF1_PF_MMIO0_FENCE_WR__ENABLE__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_WR__ENABLE_MASK 0xFFFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RD +#define DEV0_PF1_PF_MMIO0_FENCE_RD__ENABLE__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RD__ENABLE_MASK 0xFFFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE0_START +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE0_END +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE1_START +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE1_END +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE2_START +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE2_END +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE3_START +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK 0x3FFFFFFFL +//DEV0_PF1_PF_MMIO0_FENCE_RANGE3_END +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT 0x0 +#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK 0x3FFFFFFFL +//MISC_SCRATCH +#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 +#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL +//INTR_LINE_POLARITY +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL +//INTR_LINE_ENABLE +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL +//OUTSTANDING_VC_ALLOC +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L +//BIFC_MISC_CTRL0 +#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 +#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 +#define BIFC_MISC_CTRL0__REG_ACTIVE_VLINK_L0_EN__SHIFT 0x3 +#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT 0x4 +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT 0x9 +#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0xb +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0xc +#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT 0xd +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT 0xe +#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT 0xf +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12 +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13 +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14 +#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT 0x15 +#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT 0x16 +#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT 0x17 +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 +#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT 0x19 +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c +#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL__SHIFT 0x1d +#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT 0x1e +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f +#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L +#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L +#define BIFC_MISC_CTRL0__REG_ACTIVE_VLINK_L0_EN_MASK 0x00000008L +#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK 0x000000F0L +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK 0x00000200L +#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x00000800L +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x00001000L +#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK 0x00002000L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK 0x00004000L +#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK 0x00008000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L +#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK 0x00200000L +#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK 0x00400000L +#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK 0x00800000L +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L +#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK 0x02000000L +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L +#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL_MASK 0x20000000L +#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK 0x40000000L +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L +//BIFC_MISC_CTRL1 +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x7 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14 +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT 0x15 +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT 0x16 +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT 0x17 +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18 +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19 +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x1e +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x00000080L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK 0x00200000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK 0x00400000L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK 0x00800000L +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0xC0000000L +//BIFC_BME_ERR_LOG_LB +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +//BIFC_LC_TIMER_CTRL +#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT 0x0 +#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT 0x10 +#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK 0x0000FFFFL +#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK 0xFFFF0000L +//BIFC_RCCBIH_BME_ERR_LOG0 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK 0xC0000000L +//BIFC_DMA_ATTR_CNTL2_DEV0 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F0__SHIFT 0x1 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT 0x4 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F1__SHIFT 0x5 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F2__SHIFT 0x9 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT 0xc +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F3__SHIFT 0xd +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT 0x10 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F4__SHIFT 0x11 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT 0x14 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F5__SHIFT 0x15 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT 0x18 +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F6__SHIFT 0x19 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F7__SHIFT 0x1d +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK 0x00000001L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F0_MASK 0x00000002L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK 0x00000010L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F1_MASK 0x00000020L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK 0x00000100L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F2_MASK 0x00000200L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK 0x00001000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F3_MASK 0x00002000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK 0x00010000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F4_MASK 0x00020000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK 0x00100000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F5_MASK 0x00200000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK 0x01000000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F6_MASK 0x02000000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK 0x10000000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F7_MASK 0x20000000L +//BIFC_MISC_CTRL2 +#define BIFC_MISC_CTRL2__DIH_INTR_STFETCH_BLOCK_IN_LINKDOWN__SHIFT 0x0 +#define BIFC_MISC_CTRL2__SLOW_GMI_UPS_RSP_CRED_REL_EN__SHIFT 0x1 +#define BIFC_MISC_CTRL2__DMA_RSP_ECRC_REPORT__SHIFT 0x2 +#define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN__SHIFT 0x10 +#define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN__SHIFT 0x11 +#define BIFC_MISC_CTRL2__PH_SUPPORT__SHIFT 0x12 +#define BIFC_MISC_CTRL2__GMI_FAIL_REQ_RTS_MASK__SHIFT 0x16 +#define BIFC_MISC_CTRL2__NBIF_AERRPT_BACKPERSURE_EN__SHIFT 0x17 +#define BIFC_MISC_CTRL2__DIH_INTR_STFETCH_BLOCK_IN_LINKDOWN_MASK 0x00000001L +#define BIFC_MISC_CTRL2__SLOW_GMI_UPS_RSP_CRED_REL_EN_MASK 0x00000002L +#define BIFC_MISC_CTRL2__DMA_RSP_ECRC_REPORT_MASK 0x00000004L +#define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN_MASK 0x00010000L +#define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN_MASK 0x00020000L +#define BIFC_MISC_CTRL2__PH_SUPPORT_MASK 0x003C0000L +#define BIFC_MISC_CTRL2__GMI_FAIL_REQ_RTS_MASK_MASK 0x00400000L +#define BIFC_MISC_CTRL2__NBIF_AERRPT_BACKPERSURE_EN_MASK 0x00800000L +//BME_DUMMY_CNTL_0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L +//BIFC_THT_CNTL +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 +#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x10 +#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS__SHIFT 0x18 +#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x19 +#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS__SHIFT 0x1a +#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x1b +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L +#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x00010000L +#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS_MASK 0x01000000L +#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS_MASK 0x02000000L +#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS_MASK 0x04000000L +#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS_MASK 0x08000000L +//BIFC_HSTARB_CNTL +#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 +#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT 0x8 +#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L +#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK 0x00000100L +//BIFC_GSI_CNTL +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x6 +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x7 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x8 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x9 +#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0xa +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xb +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xd +#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT 0xf +#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT 0x10 +#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT 0x11 +#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT 0x12 +#define BIFC_GSI_CNTL__NBIF_UR_HPHIT_TRANS_DIS_EN__SHIFT 0x16 +#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT 0x1b +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT 0x1c +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT 0x1d +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT 0x1e +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT 0x1f +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000003CL +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000040L +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000080L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000100L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000200L +#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000400L +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00001800L +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00006000L +#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK 0x00008000L +#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK 0x00010000L +#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK 0x00020000L +#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK 0x00040000L +#define BIFC_GSI_CNTL__NBIF_UR_HPHIT_TRANS_DIS_EN_MASK 0x00400000L +#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK 0x08000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK 0x10000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK 0x20000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK 0x40000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK 0x80000000L +//BIFC_PCIEFUNC_CNTL +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 +#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL +#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L +//BIFC_PASID_CHECK_DIS +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT 0x0 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT 0x1 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK 0x00000001L +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK 0x00000002L +//BIFC_SDP_CNTL_0 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8 +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10 +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L +//BIFC_SDP_CNTL_1 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1 +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4 +#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT 0x5 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7 +#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT 0x8 +#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x9 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L +#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK 0x00000020L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L +#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK 0x00000100L +#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00000200L +//BIFC_PASID_STS +#define BIFC_PASID_STS__PASID_STS__SHIFT 0x0 +#define BIFC_PASID_STS__PASID_STS_MASK 0x0000000FL +//BIFC_ATHUB_ACT_CNTL +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT 0x0 +#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT 0x3 +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT 0x8 +#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0x9 +#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0xa +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT 0xb +#define BIFC_ATHUB_ACT_CNTL__ERREVENT_MODE1RST_FLUSH_LOG_AER_EN__SHIFT 0xc +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK 0x00000007L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK 0x00000038L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK 0x00000100L +#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000200L +#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000400L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK 0x00000800L +#define BIFC_ATHUB_ACT_CNTL__ERREVENT_MODE1RST_FLUSH_LOG_AER_EN_MASK 0x00001000L +//BIFC_PERF_CNTL_0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x007F0000L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x7F000000L +//BIF_MISC_BIFC_PERF_CNTL_1 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x4 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x5 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x8 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x10 +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000010L +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000020L +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x0000FF00L +#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x03FF0000L +//BIFC_PERF_CNT_MMIO_RD_L32BIT +#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_MMIO_WR_L32BIT +#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT +#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT +#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL +//NBIF_REGIF_ERRSET_CTRL +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//BIFC_SDP_CNTL_2 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT 0x10 +#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT 0x18 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK 0x00000F00L +#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L +#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK 0x0F000000L +//NBIF_PGMST_CTRL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8 +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//NBIF_PGSLV_CTRL +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +//NBIF_PG_MISC_CTRL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT 0xd +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT 0x10 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT 0x1e +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK 0x00002000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK 0x00010000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK 0x40000000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//SMN_MST_EP_CNTL3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_EP_CNTL4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_CNTL1 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L +//SMN_MST_EP_CNTL5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L +//BIF_SELFRING_BUFFER_VID +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 +#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT 0x8 +#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT 0x10 +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL +#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK 0x0000FF00L +#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK 0x00FF0000L +//BIF_SELFRING_VECTOR_CNTL +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1 +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L +//HDP_ERR_STATUS_EXT +#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_WR_EXT__SHIFT 0x0 +#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_RD_EXT__SHIFT 0x1 +#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_WR_EXT_MASK 0x00000001L +#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_RD_EXT_MASK 0x00000002L +//NBIF_STRAP_WRITE_CTRL +#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0 +#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK 0x00000001L +//NBIF_INTX_DSTATE_MISC_CNTL +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x0 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x1 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x2 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x3 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x4 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT 0x5 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT 0x6 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x7 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00000001L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00000002L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00000004L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00000008L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00000010L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK 0x00000020L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK 0x00000040L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000080L +//NBIF_PENDING_MISC_CNTL +#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT 0x0 +#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT 0x1 +#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK 0x00000001L +#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK 0x00000002L +//BIF_GMI_WRR_WEIGHT +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT 0x1d +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT 0x1e +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT 0x1f +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK 0x20000000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK 0x40000000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK 0x80000000L +//BIF_GMI_WRR_WEIGHT2 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT 0x18 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK 0xFF000000L +//BIF_GMI_WRR_WEIGHT3 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT 0x18 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK 0xFF000000L +//BIF_GMI_WRR_WEIGHT4 +#define BIF_GMI_WRR_WEIGHT4__GMI_REQ_ENTRY8_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT4__GMI_REQ_ENTRY8_WEIGHT_MASK 0x000000FFL +//NBIF_PWRBRK_REQUEST +#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT 0x0 +#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK 0x00000001L +//BIF_ATOMIC_ERR_LOG_DEV0_F0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L +//BIF_ATOMIC_ERR_LOG_DEV0_F1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK 0x00080000L +//BIF_DMA_MP4_ERR_LOG +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x0 +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x1 +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x10 +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x11 +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK 0x00000001L +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00000002L +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK 0x00010000L +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00020000L +//BIF_PASID_ERR_LOG +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT 0x0 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT 0x1 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK 0x00000001L +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK 0x00000002L +//BIF_PASID_ERR_CLR +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT 0x0 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT 0x1 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK 0x00000001L +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK 0x00000002L +//NBIF_VWIRE_CTRL +#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT 0x0 +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 +#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT 0x10 +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a +#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK 0x00000001L +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L +#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK 0x00010000L +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L +//NBIF_MGCG_CTRL_LCLK +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT 0xc +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DBG_DIS_LCLK__SHIFT 0xe +#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK__SHIFT 0xf +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DBG_DIS_LCLK_MASK 0x00004000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK_MASK 0x00008000L +//NBIF_DS_CTRL_LCLK +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 +#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L +#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L +//SMN_MST_CNTL0 +#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c +#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L +//SMN_MST_EP_CNTL1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_EP_CNTL2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L +//NBIF_SDP_VWR_VCHG_DIS_CTRL +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_TRIG +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L +//NBIO_LCLK_DEEPSLEEP_MASK +#define NBIO_LCLK_DEEPSLEEP_MASK__LCLK_DS_MASK__SHIFT 0x0 +#define NBIO_LCLK_DEEPSLEEP_MASK__LCLK_DS_MASK_MASK 0xFFFFFFFFL +//NBIF_DS_CTRL_USBCLK +#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DS_EN__SHIFT 0x0 +#define NBIF_DS_CTRL_USBCLK__USB_USBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DS_EN_MASK 0x00000001L +#define NBIF_DS_CTRL_USBCLK__USB_USBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L +//NBIF_SHUB_TODET_CLIENT_MISC3 +#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SLVERR_EN3__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SYNCFLOOD_EN3__SHIFT 0xa +#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SLVERR_EN3_MASK 0x000003FFL +#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SYNCFLOOD_EN3_MASK 0x000FFC00L +//NBIF_SHUB_TODET_CTRL +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT 0x1 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT 0x8 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT 0x10 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK 0x00000001L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK 0x00000002L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK 0x00000700L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK 0xFFFF0000L +//NBIF_SHUB_TODET_CLIENT_CTRL +#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_STATUS +#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_SYNCFLOOD_CTRL +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_CTRL2 +#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_STATUS2 +#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_SYNCFLOOD_CTRL2 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT 0x0 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK 0xFFFFFFFFL +//DMA_SDP_PORT_DEBUG +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_REQ_CREDIT_RDY_FOR_VC__SHIFT 0x0 +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_DAT_CREDIT_RDY_FOR_VC__SHIFT 0x8 +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_RDRSP_CREDIT_VLD_FOR_VC__SHIFT 0x10 +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_WRRSP_CREDIT_VLD_FOR_VC__SHIFT 0x18 +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_REQ_CREDIT_RDY_FOR_VC_MASK 0x000000FFL +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_DAT_CREDIT_RDY_FOR_VC_MASK 0x0000FF00L +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_RDRSP_CREDIT_VLD_FOR_VC_MASK 0x00FF0000L +#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_WRRSP_CREDIT_VLD_FOR_VC_MASK 0xFF000000L +//SDP_PORT_MONITOR_CONTROL +#define SDP_PORT_MONITOR_CONTROL__DMA_SDP_PORT_MONITOR_EN__SHIFT 0x0 +#define SDP_PORT_MONITOR_CONTROL__HST_SDP_PORT_MONITOR_EN__SHIFT 0x1 +#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_ADDRESS_EN__SHIFT 0x2 +#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_UNITID_EN__SHIFT 0x3 +#define SDP_PORT_MONITOR_CONTROL__DMA_SDP_PORT_MONITOR_EN_MASK 0x00000001L +#define SDP_PORT_MONITOR_CONTROL__HST_SDP_PORT_MONITOR_EN_MASK 0x00000002L +#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_ADDRESS_EN_MASK 0x00000004L +#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_UNITID_EN_MASK 0x00000008L +//SDP_PORT_MONITOR_ADDRESS0 +#define SDP_PORT_MONITOR_ADDRESS0__SDP_PORT_MONITOR_ADDRESS0__SHIFT 0x0 +#define SDP_PORT_MONITOR_ADDRESS0__SDP_PORT_MONITOR_ADDRESS0_MASK 0xFFFFFFFFL +//SDP_PORT_MONITOR_ADDRESS1 +#define SDP_PORT_MONITOR_ADDRESS1__SDP_PORT_MONITOR_ADDRESS1__SHIFT 0x0 +#define SDP_PORT_MONITOR_ADDRESS1__SDP_PORT_MONITOR_ADDRESS1_MASK 0xFFFFFFFFL +//SDP_PORT_MONITOR_UNITID +#define SDP_PORT_MONITOR_UNITID__SDP_PORT_MONITOR_UNITID__SHIFT 0x0 +#define SDP_PORT_MONITOR_UNITID__SDP_PORT_MONITOR_UNITID_MASK 0x000007FFL +//SDP_PORT_MONITOR_INFO0 +#define SDP_PORT_MONITOR_INFO0__SDP_PORT_MONITOR_INFO_ADDRESS0__SHIFT 0x0 +#define SDP_PORT_MONITOR_INFO0__SDP_PORT_MONITOR_INFO_ADDRESS0_MASK 0xFFFFFFFFL +//SDP_PORT_MONITOR_INFO1 +#define SDP_PORT_MONITOR_INFO1__SDP_PORT_MONITOR_INFO_ADDRESS1__SHIFT 0x0 +#define SDP_PORT_MONITOR_INFO1__SDP_PORT_MONITOR_INFO_ADDRESS1_MASK 0xFFFFFFFFL +//SDP_PORT_MONITOR_INFO2 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_BLOCKLEVEL__SHIFT 0x0 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CHAIN__SHIFT 0x2 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CMD__SHIFT 0x3 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_IO__SHIFT 0x9 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_PASSPW__SHIFT 0xa +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_RSPPASSPW__SHIFT 0xb +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_SECLEVEL__SHIFT 0xc +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_STREAMID__SHIFT 0x10 +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_BLOCKLEVEL_MASK 0x00000003L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CHAIN_MASK 0x00000004L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CMD_MASK 0x000001F8L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_IO_MASK 0x00000200L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_PASSPW_MASK 0x00000400L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_RSPPASSPW_MASK 0x00000800L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_SECLEVEL_MASK 0x0000F000L +#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_STREAMID_MASK 0xFFFF0000L +//SDP_PORT_MONITOR_INFO3 +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_TAG__SHIFT 0x0 +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_UNITID__SHIFT 0xc +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_VC__SHIFT 0x17 +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_LEN__SHIFT 0x1a +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_TAG_MASK 0x00000FFFL +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_UNITID_MASK 0x007FF000L +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_VC_MASK 0x03800000L +#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_LEN_MASK 0xFC000000L +//SDP_PORT_MONITOR_INFO4 +#define SDP_PORT_MONITOR_INFO4__SDP_PORT_MONITOR_INFO_ATTR__SHIFT 0x0 +#define SDP_PORT_MONITOR_INFO4__SDP_PORT_MONITOR_INFO_ATTR_MASK 0x000000FFL +//BIFC_BME_ERR_LOG_HB +//BIFC_GFX_INT_MONITOR_MASK +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_CTRL_MASK__SHIFT 0x0 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_ADDR_MASK__SHIFT 0x1 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_UPADDR_MASK__SHIFT 0x2 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_DATA_MASK__SHIFT 0x3 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_EDATA_MASK__SHIFT 0x4 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_ADDR_MASK__SHIFT 0x5 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_UPADDR_MASK__SHIFT 0x6 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_DATA_MASK__SHIFT 0x7 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_VEC_MASK__SHIFT 0x8 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_PEND_MASK__SHIFT 0x9 +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_CTRL_MASK__SHIFT 0xa +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_CTRL_MASK_MASK 0x00000001L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_ADDR_MASK_MASK 0x00000002L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_UPADDR_MASK_MASK 0x00000004L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_DATA_MASK_MASK 0x00000008L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_EDATA_MASK_MASK 0x00000010L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_ADDR_MASK_MASK 0x00000020L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_UPADDR_MASK_MASK 0x00000040L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_DATA_MASK_MASK 0x00000080L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_VEC_MASK_MASK 0x00000100L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_PEND_MASK_MASK 0x00000200L +#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_CTRL_MASK_MASK 0x00000400L +//BIFC_GFX_INT_MONITOR_STS +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_CTRL_STS__SHIFT 0x0 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_ADDR_STS__SHIFT 0x1 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_UPADDR_STS__SHIFT 0x2 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_DATA_STS__SHIFT 0x3 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_EDATA_STS__SHIFT 0x4 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_ADDR_STS__SHIFT 0x5 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_UPADDR_STS__SHIFT 0x6 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_DATA_STS__SHIFT 0x7 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_VEC_STS__SHIFT 0x8 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_PEND_STS__SHIFT 0x9 +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_CTRL_STS__SHIFT 0xa +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_CTRL_STS_MASK 0x00000001L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_ADDR_STS_MASK 0x00000002L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_UPADDR_STS_MASK 0x00000004L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_DATA_STS_MASK 0x00000008L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_EDATA_STS_MASK 0x00000010L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_ADDR_STS_MASK 0x00000020L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_UPADDR_STS_MASK 0x00000040L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_DATA_STS_MASK 0x00000080L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_VEC_STS_MASK 0x00000100L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_PEND_STS_MASK 0x00000200L +#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_CTRL_STS_MASK 0x00000400L +//BIFC_GFX_INT_MONITOR_CTRL +#define BIFC_GFX_INT_MONITOR_CTRL__GFX_INT_MONITOR_VEC_SEL__SHIFT 0x0 +#define BIFC_GFX_INT_MONITOR_CTRL__GFX_INT_MONITOR_VEC_SEL_MASK 0x0000000FL +//NBIF_FLUSH_CTRL +#define NBIF_FLUSH_CTRL__GMI_FLUSH_OT_ENABLE__SHIFT 0x0 +#define NBIF_FLUSH_CTRL__GSI_FLUSH_OT_ENABLE__SHIFT 0x1 +#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_EN__SHIFT 0x3 +#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_SEL__SHIFT 0x4 +#define NBIF_FLUSH_CTRL__NBIF_GRP1_RW_OT_SWITCH__SHIFT 0x6 +#define NBIF_FLUSH_CTRL__GMI_FLUSH_OT_ENABLE_MASK 0x00000001L +#define NBIF_FLUSH_CTRL__GSI_FLUSH_OT_ENABLE_MASK 0x00000002L +#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_EN_MASK 0x00000008L +#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_SEL_MASK 0x00000030L +#define NBIF_FLUSH_CTRL__NBIF_GRP1_RW_OT_SWITCH_MASK 0x00000040L +//NBIF_GUI_FLUSH_CNTL +#define NBIF_GUI_FLUSH_CNTL__NBIF_GUI_FLUSH_REQ_MERGE__SHIFT 0x0 +#define NBIF_GUI_FLUSH_CNTL__NBIF_GUI_FLUSH_REQ_MERGE_MASK 0x00000001L +//BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +//BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +//BIFC_GMI_SDP_REQ_POOLCRED_ALLOC +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SDP_DAT_POOLCRED_ALLOC +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//DISCON_HYSTERESIS_HEAD_CTRL +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x0 +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK 0x0000000FL +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L +//BIFC_GSI_SDP_REQ_POOLCRED_ALLOC +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GSI_SDP_DAT_POOLCRED_ALLOC +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_MCA_SMN_CTRL0 +#define BIFC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT 0x0 +#define BIFC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK 0x00000001L +//BIFC_MCTP_SMN_CTRL0 +#define BIFC_MCTP_SMN_CTRL0__MCTP_SMN_POSTED__SHIFT 0x0 +#define BIFC_MCTP_SMN_CTRL0__MCTP_SMN_POSTED_MASK 0x00000001L +//NBIF_REGIF_DEBUG_COUNTER_CTRL +//BIFC_EARLY_WAKEUP_CNTL +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//BIFC_PERF_CNT_MMIO_RD_H16BIT +#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_MMIO_WR_H16BIT +#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT +#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT +#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE__SHIFT 0x0 +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS__SHIFT 0x3 +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL__SHIFT 0x4 +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__PERF_CNT_TRIG_MONI_SEL__SHIFT 0x5 +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE_MASK 0x00000001L +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS_MASK 0x00000008L +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL_MASK 0x00000010L +#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__PERF_CNT_TRIG_MONI_SEL_MASK 0x00000060L +//BIF_MISC_NBIF_SDP_PERF_CNT_FSM +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_SHADOW_TGL_DELAY_COUNT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT 0x4 +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT 0x8 +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PRE_FLD_GLOBAL_SHADOW_WR__SHIFT 0x9 +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT_DONE__SHIFT 0xa +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT0_RESET__SHIFT 0xb +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT1_RESET__SHIFT 0xc +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT2_RESET__SHIFT 0xd +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT3_RESET__SHIFT 0xe +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_REQ_UNIT_ID__SHIFT 0xf +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_SHADOW_TGL_DELAY_COUNT_MASK 0x0000000FL +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK 0x000000F0L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK 0x00000100L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PRE_FLD_GLOBAL_SHADOW_WR_MASK 0x00000200L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT_DONE_MASK 0x00000400L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT0_RESET_MASK 0x00000800L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT1_RESET_MASK 0x00001000L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT2_RESET_MASK 0x00002000L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT3_RESET_MASK 0x00004000L +#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_REQ_UNIT_ID_MASK 0x03FF8000L +//BIF_MISC_NBIF_SDP_PERF_COUNTER +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_EN__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_EN__SHIFT 0x1 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_EN__SHIFT 0x2 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_EN__SHIFT 0x3 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_SEL__SHIFT 0x4 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_SEL__SHIFT 0xb +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_SEL__SHIFT 0x12 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_SEL__SHIFT 0x19 +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_EN_MASK 0x00000001L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_EN_MASK 0x00000002L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_EN_MASK 0x00000004L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_EN_MASK 0x00000008L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_SEL_MASK 0x000007F0L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_SEL_MASK 0x0003F800L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_SEL_MASK 0x01FC0000L +#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_SEL_MASK 0xFE000000L +//BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT__SDP_PERF_CNT_0_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT__SDP_PERF_CNT_0_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT__SDP_PERF_CNT_1_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT__SDP_PERF_CNT_1_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT__SDP_PERF_CNT_2_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT__SDP_PERF_CNT_2_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT__SDP_PERF_CNT_3_VALUE_L32BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT__SDP_PERF_CNT_3_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT__SDP_PERF_CNT_0_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT__SDP_PERF_CNT_0_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT__SDP_PERF_CNT_1_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT__SDP_PERF_CNT_1_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT__SDP_PERF_CNT_2_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT__SDP_PERF_CNT_2_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT +#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT__SDP_PERF_CNT_3_VALUE_H16BIT__SHIFT 0x0 +#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT__SDP_PERF_CNT_3_VALUE_H16BIT_MASK 0x0000FFFFL +//BIF_MISC_NBIF_BX_PERF_CNT_FSM +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_SHADOW_TGL_DELAY_COUNT__SHIFT 0x0 +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT 0x4 +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT 0x8 +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PRE_FLD_GLOBAL_SHADOW_WR__SHIFT 0x9 +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE__SHIFT 0xa +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_SHADOW_TGL_DELAY_COUNT_MASK 0x0000000FL +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK 0x000000F0L +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK 0x00000100L +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PRE_FLD_GLOBAL_SHADOW_WR_MASK 0x00000200L +#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE_MASK 0x00000400L +//NBIF_TDISP_ENTER_ERR_CNTL +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_POISONEDTLP_EN__SHIFT 0x0 +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_UR_EN__SHIFT 0x1 +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_CA_EN__SHIFT 0x2 +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_TO_EN__SHIFT 0x3 +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_POISONEDTLP_EN_MASK 0x00000001L +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_UR_EN_MASK 0x00000002L +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_CA_EN_MASK 0x00000004L +#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_TO_EN_MASK 0x00000008L +//BIF_UNITID_ERR_LOG +#define BIF_UNITID_ERR_LOG__UR_UNITID_athub__SHIFT 0x0 +#define BIF_UNITID_ERR_LOG__CLEAR_UR_UNITID_athub__SHIFT 0x10 +#define BIF_UNITID_ERR_LOG__UR_UNITID_athub_MASK 0x00000001L +#define BIF_UNITID_ERR_LOG__CLEAR_UR_UNITID_athub_MASK 0x00010000L +//NBIF_COM_COUNT_VALUE +#define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE__SHIFT 0x0 +#define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE_MASK 0xFFFFFFFFL +//NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT0_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x0 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT1_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x1 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT2_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x2 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT3_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x3 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT4_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x4 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT5_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x5 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT6_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x6 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT7_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x7 +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT0_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000001L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT1_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000002L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT2_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000004L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT3_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000008L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT4_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000010L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT5_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000020L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT6_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000040L +#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT7_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000080L +//NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x0 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x1 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x2 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x3 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x4 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT5_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x5 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT6_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x6 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT7_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x7 +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000001L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000002L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000004L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000008L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000010L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT5_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000020L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT6_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000040L +#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT7_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000080L +//BIF_AER_CNTL +#define BIF_AER_CNTL__BIF_AER_VF_NUM__SHIFT 0x0 +#define BIF_AER_CNTL__BIF_AER_PF_NUM__SHIFT 0x8 +#define BIF_AER_CNTL__BIF_AER_ERR_PTR__SHIFT 0xb +#define BIF_AER_CNTL__BIF_AER_HeaderStoreOffset__SHIFT 0x10 +#define BIF_AER_CNTL__BIF_AER_ERR_MSG_TYPE__SHIFT 0x18 +#define BIF_AER_CNTL__BIF_AER_DEVERR__SHIFT 0x1a +#define BIF_AER_CNTL__BIF_AER_POSTED__SHIFT 0x1b +#define BIF_AER_CNTL__BIF_AER_TOTAL_OF_PF__SHIFT 0x1c +#define BIF_AER_CNTL__BIF_AER_VF_HIT__SHIFT 0x1f +#define BIF_AER_CNTL__BIF_AER_VF_NUM_MASK 0x000000FFL +#define BIF_AER_CNTL__BIF_AER_PF_NUM_MASK 0x00000700L +#define BIF_AER_CNTL__BIF_AER_ERR_PTR_MASK 0x0000F800L +#define BIF_AER_CNTL__BIF_AER_HeaderStoreOffset_MASK 0x00FF0000L +#define BIF_AER_CNTL__BIF_AER_ERR_MSG_TYPE_MASK 0x03000000L +#define BIF_AER_CNTL__BIF_AER_DEVERR_MASK 0x04000000L +#define BIF_AER_CNTL__BIF_AER_POSTED_MASK 0x08000000L +#define BIF_AER_CNTL__BIF_AER_TOTAL_OF_PF_MASK 0x70000000L +#define BIF_AER_CNTL__BIF_AER_VF_HIT_MASK 0x80000000L +//NBIF_IDE_INFO_CNTL +#define NBIF_IDE_INFO_CNTL__NBIF_PRGR_MSG_IDE_INFO_FROM_DATA_EN__SHIFT 0x0 +#define NBIF_IDE_INFO_CNTL__NBIF_PRGR_MSG_IDE_INFO_FROM_DATA_EN_MASK 0x00000001L +//BIFC_EXP_MISC_CTRL0 +#define BIFC_EXP_MISC_CTRL0__VC0_DMA_IOCFG_DIS__SHIFT 0x0 +#define BIFC_EXP_MISC_CTRL0__VC1_DMA_IOCFG_DIS__SHIFT 0x1 +#define BIFC_EXP_MISC_CTRL0__VC2_DMA_IOCFG_DIS__SHIFT 0x2 +#define BIFC_EXP_MISC_CTRL0__VC3_DMA_IOCFG_DIS__SHIFT 0x3 +#define BIFC_EXP_MISC_CTRL0__VC4_DMA_IOCFG_DIS__SHIFT 0x4 +#define BIFC_EXP_MISC_CTRL0__VC5_DMA_IOCFG_DIS__SHIFT 0x5 +#define BIFC_EXP_MISC_CTRL0__VC6_DMA_IOCFG_DIS__SHIFT 0x6 +#define BIFC_EXP_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x7 +#define BIFC_EXP_MISC_CTRL0__VC0_DMA_IOCFG_DIS_MASK 0x00000001L +#define BIFC_EXP_MISC_CTRL0__VC1_DMA_IOCFG_DIS_MASK 0x00000002L +#define BIFC_EXP_MISC_CTRL0__VC2_DMA_IOCFG_DIS_MASK 0x00000004L +#define BIFC_EXP_MISC_CTRL0__VC3_DMA_IOCFG_DIS_MASK 0x00000008L +#define BIFC_EXP_MISC_CTRL0__VC4_DMA_IOCFG_DIS_MASK 0x00000010L +#define BIFC_EXP_MISC_CTRL0__VC5_DMA_IOCFG_DIS_MASK 0x00000020L +#define BIFC_EXP_MISC_CTRL0__VC6_DMA_IOCFG_DIS_MASK 0x00000040L +#define BIFC_EXP_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK 0x00000080L +//SECOND_HDP_MEM_FLUSH_CNTL_PF +#define SECOND_HDP_MEM_FLUSH_CNTL_PF__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_PF__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF0 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF0__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF0__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF1 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF1__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF1__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF2__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF2__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF3 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF3__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF3__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF4 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF4__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF4__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF5 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF5__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF5__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF6 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF6__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF6__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_MEM_FLUSH_CNTL_VF7 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF7__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_MEM_FLUSH_CNTL_VF7__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_PF +#define SECOND_HDP_REG_FLUSH_CNTL_PF__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_PF__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF0 +#define SECOND_HDP_REG_FLUSH_CNTL_VF0__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF0__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF1 +#define SECOND_HDP_REG_FLUSH_CNTL_VF1__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF1__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF2__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF2__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF3 +#define SECOND_HDP_REG_FLUSH_CNTL_VF3__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF3__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF4 +#define SECOND_HDP_REG_FLUSH_CNTL_VF4__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF4__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF5 +#define SECOND_HDP_REG_FLUSH_CNTL_VF5__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF5__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF6 +#define SECOND_HDP_REG_FLUSH_CNTL_VF6__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF6__ADDRESS_MASK 0x0007FFFCL +//SECOND_HDP_REG_FLUSH_CNTL_VF7 +#define SECOND_HDP_REG_FLUSH_CNTL_VF7__ADDRESS__SHIFT 0x2 +#define SECOND_HDP_REG_FLUSH_CNTL_VF7__ADDRESS_MASK 0x0007FFFCL +//GPU_HDP_FLUSH_GFX_FW +#define GPU_HDP_FLUSH_GFX_FW__CLEAR_ALL_VF_FLUSH_DONE__SHIFT 0x0 +#define GPU_HDP_FLUSH_GFX_FW__CLEAR_ALL_VF_FLUSH_DONE_MASK 0x00000001L +//NBIF_RRMT_CNTL +#define NBIF_RRMT_CNTL__PARTITION_MODE__SHIFT 0x0 +#define NBIF_RRMT_CNTL__AID_DIE_ID__SHIFT 0x4 +#define NBIF_RRMT_CNTL__RRMT_ENABLE__SHIFT 0x8 +#define NBIF_RRMT_CNTL__RRMT_Invalid_Address_H__SHIFT 0x10 +#define NBIF_RRMT_CNTL__PARTITION_MODE_MASK 0x00000007L +#define NBIF_RRMT_CNTL__AID_DIE_ID_MASK 0x00000030L +#define NBIF_RRMT_CNTL__RRMT_ENABLE_MASK 0x00000100L +#define NBIF_RRMT_CNTL__RRMT_Invalid_Address_H_MASK 0xFFFF0000L +//RRMT_NBIF_MISC_REG1 +#define RRMT_NBIF_MISC_REG1__RRMT_Invalid_Address_L__SHIFT 0x0 +#define RRMT_NBIF_MISC_REG1__RRMT_Invalid_Address_L_MASK 0xFFFFFFFFL +//RRMT_LUT_INDEX +#define RRMT_LUT_INDEX__RRMT_LUT_INDEX__SHIFT 0x0 +#define RRMT_LUT_INDEX__RRMT_LUT_INDEX_MASK 0x000003FFL +//RRMT_LUT_DATA +#define RRMT_LUT_DATA__RRMT_LUT_DATA__SHIFT 0x0 +#define RRMT_LUT_DATA__RRMT_LUT_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf0_bif_misc_pfvf_regblk +//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf1_bif_misc_pfvf_regblk +//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95_MASK 0x80000000L +//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96__SHIFT 0x0 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97__SHIFT 0x1 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98__SHIFT 0x2 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99__SHIFT 0x3 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100__SHIFT 0x4 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101__SHIFT 0x5 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102__SHIFT 0x6 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103__SHIFT 0x7 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104__SHIFT 0x8 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105__SHIFT 0x9 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106__SHIFT 0xa +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107__SHIFT 0xb +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108__SHIFT 0xc +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109__SHIFT 0xd +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110__SHIFT 0xe +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111__SHIFT 0xf +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112__SHIFT 0x10 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113__SHIFT 0x11 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114__SHIFT 0x12 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115__SHIFT 0x13 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116__SHIFT 0x14 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117__SHIFT 0x15 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118__SHIFT 0x16 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119__SHIFT 0x17 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120__SHIFT 0x18 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121__SHIFT 0x19 +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122__SHIFT 0x1a +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123__SHIFT 0x1b +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124__SHIFT 0x1c +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125__SHIFT 0x1d +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126__SHIFT 0x1e +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127__SHIFT 0x1f +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96_MASK 0x00000001L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97_MASK 0x00000002L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98_MASK 0x00000004L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99_MASK 0x00000008L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100_MASK 0x00000010L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101_MASK 0x00000020L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102_MASK 0x00000040L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103_MASK 0x00000080L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104_MASK 0x00000100L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105_MASK 0x00000200L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106_MASK 0x00000400L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107_MASK 0x00000800L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108_MASK 0x00001000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109_MASK 0x00002000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110_MASK 0x00004000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111_MASK 0x00008000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112_MASK 0x00010000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113_MASK 0x00020000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114_MASK 0x00040000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115_MASK 0x00080000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116_MASK 0x00100000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117_MASK 0x00200000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118_MASK 0x00400000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119_MASK 0x00800000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120_MASK 0x01000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121_MASK 0x02000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122_MASK 0x04000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123_MASK 0x08000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124_MASK 0x10000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125_MASK 0x20000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126_MASK 0x40000000L +#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127_MASK 0x80000000L + + +// addressBlock: nbif0_nbif0_bif_trap_bif_trap_regblk +//NBIF_TRAP_NP_STATUS +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapReqValid__SHIFT 0x0 +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapNumber__SHIFT 0x8 +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Vld__SHIFT 0xc +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Number__SHIFT 0x10 +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapReqValid_MASK 0x00000001L +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapNumber_MASK 0x00000F00L +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Vld_MASK 0x00001000L +#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Number_MASK 0x01FF0000L +//NBIF_TRAP_NP_REQUEST0 +#define NBIF_TRAP_NP_REQUEST0__NBIF_TRAP_NP_TrapReqAddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_REQUEST0__NBIF_TRAP_NP_TrapReqAddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_REQUEST1 +#define NBIF_TRAP_NP_REQUEST1__NBIF_TRAP_NP_TrapReqAddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST1__NBIF_TRAP_NP_TrapReqAddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST2 +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqCmd__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqAttr__SHIFT 0x8 +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqLen__SHIFT 0x10 +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqCmd_MASK 0x0000003FL +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqAttr_MASK 0x0000FF00L +#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqLen_MASK 0x003F0000L +//NBIF_TRAP_NP_REQUEST3 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqVC__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqBlockLevel__SHIFT 0x4 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqChain__SHIFT 0x6 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqIO__SHIFT 0x7 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqPassPW__SHIFT 0x8 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqRspPassPW__SHIFT 0x9 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqUnitID__SHIFT 0x10 +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqVC_MASK 0x00000007L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqBlockLevel_MASK 0x00000030L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqChain_MASK 0x00000040L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqIO_MASK 0x00000080L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqPassPW_MASK 0x00000100L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqRspPassPW_MASK 0x00000200L +#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqUnitID_MASK 0x07FF0000L +//NBIF_TRAP_NP_REQUEST4 +#define NBIF_TRAP_NP_REQUEST4__NBIF_TRAP_NP_TrapReqSecLevel__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST4__NBIF_TRAP_NP_TrapReqSecLevel_MASK 0x0000000FL +//NBIF_TRAP_NP_REQUEST5 +#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataVC__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataErr__SHIFT 0x4 +#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataVC_MASK 0x00000007L +#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataErr_MASK 0x000000F0L +//NBIF_TRAP_NP_REQUEST6 +#define NBIF_TRAP_NP_REQUEST6__NBIF_TRAP_NP_TrapReqDataParity__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST6__NBIF_TRAP_NP_TrapReqDataParity_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB0__NBIF_TRAP_NP_TrapReqDataBytEn0__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB0__NBIF_TRAP_NP_TrapReqDataBytEn0_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB1 +#define NBIF_TRAP_NP_REQUEST_DATASTRB1__NBIF_TRAP_NP_TrapReqDataBytEn1__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB1__NBIF_TRAP_NP_TrapReqDataBytEn1_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB2 +#define NBIF_TRAP_NP_REQUEST_DATASTRB2__NBIF_TRAP_NP_TrapReqDataBytEn2__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB2__NBIF_TRAP_NP_TrapReqDataBytEn2_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB3 +#define NBIF_TRAP_NP_REQUEST_DATASTRB3__NBIF_TRAP_NP_TrapReqDataBytEn3__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB3__NBIF_TRAP_NP_TrapReqDataBytEn3_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB4 +#define NBIF_TRAP_NP_REQUEST_DATASTRB4__NBIF_TRAP_NP_TrapReqDataBytEn4__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB4__NBIF_TRAP_NP_TrapReqDataBytEn4_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB5 +#define NBIF_TRAP_NP_REQUEST_DATASTRB5__NBIF_TRAP_NP_TrapReqDataBytEn5__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB5__NBIF_TRAP_NP_TrapReqDataBytEn5_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB6 +#define NBIF_TRAP_NP_REQUEST_DATASTRB6__NBIF_TRAP_NP_TrapReqDataBytEn6__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB6__NBIF_TRAP_NP_TrapReqDataBytEn6_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATASTRB7 +#define NBIF_TRAP_NP_REQUEST_DATASTRB7__NBIF_TRAP_NP_TrapReqDataBytEn7__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATASTRB7__NBIF_TRAP_NP_TrapReqDataBytEn7_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA0 +#define NBIF_TRAP_NP_REQUEST_DATA0__NBIF_TRAP_NP_TrapReqData0__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA0__NBIF_TRAP_NP_TrapReqData0_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA1 +#define NBIF_TRAP_NP_REQUEST_DATA1__NBIF_TRAP_NP_TrapReqData1__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA1__NBIF_TRAP_NP_TrapReqData1_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA2 +#define NBIF_TRAP_NP_REQUEST_DATA2__NBIF_TRAP_NP_TrapReqData2__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA2__NBIF_TRAP_NP_TrapReqData2_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA3 +#define NBIF_TRAP_NP_REQUEST_DATA3__NBIF_TRAP_NP_TrapReqData3__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA3__NBIF_TRAP_NP_TrapReqData3_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA4 +#define NBIF_TRAP_NP_REQUEST_DATA4__NBIF_TRAP_NP_TrapReqData4__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA4__NBIF_TRAP_NP_TrapReqData4_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA5 +#define NBIF_TRAP_NP_REQUEST_DATA5__NBIF_TRAP_NP_TrapReqData5__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA5__NBIF_TRAP_NP_TrapReqData5_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA6 +#define NBIF_TRAP_NP_REQUEST_DATA6__NBIF_TRAP_NP_TrapReqData6__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA6__NBIF_TRAP_NP_TrapReqData6_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA7 +#define NBIF_TRAP_NP_REQUEST_DATA7__NBIF_TRAP_NP_TrapReqData7__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA7__NBIF_TRAP_NP_TrapReqData7_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA8 +#define NBIF_TRAP_NP_REQUEST_DATA8__NBIF_TRAP_NP_TrapReqData8__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA8__NBIF_TRAP_NP_TrapReqData8_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA9 +#define NBIF_TRAP_NP_REQUEST_DATA9__NBIF_TRAP_NP_TrapReqData9__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA9__NBIF_TRAP_NP_TrapReqData9_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA10 +#define NBIF_TRAP_NP_REQUEST_DATA10__NBIF_TRAP_NP_TrapReqData10__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA10__NBIF_TRAP_NP_TrapReqData10_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA11 +#define NBIF_TRAP_NP_REQUEST_DATA11__NBIF_TRAP_NP_TrapReqData11__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA11__NBIF_TRAP_NP_TrapReqData11_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA12 +#define NBIF_TRAP_NP_REQUEST_DATA12__NBIF_TRAP_NP_TrapReqData12__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA12__NBIF_TRAP_NP_TrapReqData12_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA13 +#define NBIF_TRAP_NP_REQUEST_DATA13__NBIF_TRAP_NP_TrapReqData13__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA13__NBIF_TRAP_NP_TrapReqData13_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA14 +#define NBIF_TRAP_NP_REQUEST_DATA14__NBIF_TRAP_NP_TrapReqData14__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA14__NBIF_TRAP_NP_TrapReqData14_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA15 +#define NBIF_TRAP_NP_REQUEST_DATA15__NBIF_TRAP_NP_TrapReqData15__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA15__NBIF_TRAP_NP_TrapReqData15_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA16 +#define NBIF_TRAP_NP_REQUEST_DATA16__NBIF_TRAP_NP_TrapReqData16__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA16__NBIF_TRAP_NP_TrapReqData16_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA17 +#define NBIF_TRAP_NP_REQUEST_DATA17__NBIF_TRAP_NP_TrapReqData17__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA17__NBIF_TRAP_NP_TrapReqData17_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA18 +#define NBIF_TRAP_NP_REQUEST_DATA18__NBIF_TRAP_NP_TrapReqData18__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA18__NBIF_TRAP_NP_TrapReqData18_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA19 +#define NBIF_TRAP_NP_REQUEST_DATA19__NBIF_TRAP_NP_TrapReqData19__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA19__NBIF_TRAP_NP_TrapReqData19_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA20 +#define NBIF_TRAP_NP_REQUEST_DATA20__NBIF_TRAP_NP_TrapReqData20__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA20__NBIF_TRAP_NP_TrapReqData20_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA21 +#define NBIF_TRAP_NP_REQUEST_DATA21__NBIF_TRAP_NP_TrapReqData21__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA21__NBIF_TRAP_NP_TrapReqData21_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA22 +#define NBIF_TRAP_NP_REQUEST_DATA22__NBIF_TRAP_NP_TrapReqData22__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA22__NBIF_TRAP_NP_TrapReqData22_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA23 +#define NBIF_TRAP_NP_REQUEST_DATA23__NBIF_TRAP_NP_TrapReqData23__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA23__NBIF_TRAP_NP_TrapReqData23_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA24 +#define NBIF_TRAP_NP_REQUEST_DATA24__NBIF_TRAP_NP_TrapReqData24__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA24__NBIF_TRAP_NP_TrapReqData24_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA25 +#define NBIF_TRAP_NP_REQUEST_DATA25__NBIF_TRAP_NP_TrapReqData25__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA25__NBIF_TRAP_NP_TrapReqData25_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA26 +#define NBIF_TRAP_NP_REQUEST_DATA26__NBIF_TRAP_NP_TrapReqData26__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA26__NBIF_TRAP_NP_TrapReqData26_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA27 +#define NBIF_TRAP_NP_REQUEST_DATA27__NBIF_TRAP_NP_TrapReqData27__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA27__NBIF_TRAP_NP_TrapReqData27_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA28 +#define NBIF_TRAP_NP_REQUEST_DATA28__NBIF_TRAP_NP_TrapReqData28__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA28__NBIF_TRAP_NP_TrapReqData28_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA29 +#define NBIF_TRAP_NP_REQUEST_DATA29__NBIF_TRAP_NP_TrapReqData29__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA29__NBIF_TRAP_NP_TrapReqData29_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA30 +#define NBIF_TRAP_NP_REQUEST_DATA30__NBIF_TRAP_NP_TrapReqData30__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA30__NBIF_TRAP_NP_TrapReqData30_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA31 +#define NBIF_TRAP_NP_REQUEST_DATA31__NBIF_TRAP_NP_TrapReqData31__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA31__NBIF_TRAP_NP_TrapReqData31_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA32 +#define NBIF_TRAP_NP_REQUEST_DATA32__NBIF_TRAP_NP_TrapReqData32__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA32__NBIF_TRAP_NP_TrapReqData32_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA33 +#define NBIF_TRAP_NP_REQUEST_DATA33__NBIF_TRAP_NP_TrapReqData33__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA33__NBIF_TRAP_NP_TrapReqData33_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA34 +#define NBIF_TRAP_NP_REQUEST_DATA34__NBIF_TRAP_NP_TrapReqData34__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA34__NBIF_TRAP_NP_TrapReqData34_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA35 +#define NBIF_TRAP_NP_REQUEST_DATA35__NBIF_TRAP_NP_TrapReqData35__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA35__NBIF_TRAP_NP_TrapReqData35_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA36 +#define NBIF_TRAP_NP_REQUEST_DATA36__NBIF_TRAP_NP_TrapReqData36__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA36__NBIF_TRAP_NP_TrapReqData36_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA37 +#define NBIF_TRAP_NP_REQUEST_DATA37__NBIF_TRAP_NP_TrapReqData37__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA37__NBIF_TRAP_NP_TrapReqData37_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA38 +#define NBIF_TRAP_NP_REQUEST_DATA38__NBIF_TRAP_NP_TrapReqData38__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA38__NBIF_TRAP_NP_TrapReqData38_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA39 +#define NBIF_TRAP_NP_REQUEST_DATA39__NBIF_TRAP_NP_TrapReqData39__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA39__NBIF_TRAP_NP_TrapReqData39_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA40 +#define NBIF_TRAP_NP_REQUEST_DATA40__NBIF_TRAP_NP_TrapReqData40__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA40__NBIF_TRAP_NP_TrapReqData40_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA41 +#define NBIF_TRAP_NP_REQUEST_DATA41__NBIF_TRAP_NP_TrapReqData41__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA41__NBIF_TRAP_NP_TrapReqData41_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA42 +#define NBIF_TRAP_NP_REQUEST_DATA42__NBIF_TRAP_NP_TrapReqData42__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA42__NBIF_TRAP_NP_TrapReqData42_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA43 +#define NBIF_TRAP_NP_REQUEST_DATA43__NBIF_TRAP_NP_TrapReqData43__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA43__NBIF_TRAP_NP_TrapReqData43_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA44 +#define NBIF_TRAP_NP_REQUEST_DATA44__NBIF_TRAP_NP_TrapReqData44__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA44__NBIF_TRAP_NP_TrapReqData44_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA45 +#define NBIF_TRAP_NP_REQUEST_DATA45__NBIF_TRAP_NP_TrapReqData45__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA45__NBIF_TRAP_NP_TrapReqData45_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA46 +#define NBIF_TRAP_NP_REQUEST_DATA46__NBIF_TRAP_NP_TrapReqData46__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA46__NBIF_TRAP_NP_TrapReqData46_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA47 +#define NBIF_TRAP_NP_REQUEST_DATA47__NBIF_TRAP_NP_TrapReqData47__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA47__NBIF_TRAP_NP_TrapReqData47_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA48 +#define NBIF_TRAP_NP_REQUEST_DATA48__NBIF_TRAP_NP_TrapReqData48__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA48__NBIF_TRAP_NP_TrapReqData48_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA49 +#define NBIF_TRAP_NP_REQUEST_DATA49__NBIF_TRAP_NP_TrapReqData49__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA49__NBIF_TRAP_NP_TrapReqData49_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA50 +#define NBIF_TRAP_NP_REQUEST_DATA50__NBIF_TRAP_NP_TrapReqData50__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA50__NBIF_TRAP_NP_TrapReqData50_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA51 +#define NBIF_TRAP_NP_REQUEST_DATA51__NBIF_TRAP_NP_TrapReqData51__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA51__NBIF_TRAP_NP_TrapReqData51_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA52 +#define NBIF_TRAP_NP_REQUEST_DATA52__NBIF_TRAP_NP_TrapReqData52__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA52__NBIF_TRAP_NP_TrapReqData52_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA53 +#define NBIF_TRAP_NP_REQUEST_DATA53__NBIF_TRAP_NP_TrapReqData53__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA53__NBIF_TRAP_NP_TrapReqData53_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA54 +#define NBIF_TRAP_NP_REQUEST_DATA54__NBIF_TRAP_NP_TrapReqData54__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA54__NBIF_TRAP_NP_TrapReqData54_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA55 +#define NBIF_TRAP_NP_REQUEST_DATA55__NBIF_TRAP_NP_TrapReqData55__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA55__NBIF_TRAP_NP_TrapReqData55_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA56 +#define NBIF_TRAP_NP_REQUEST_DATA56__NBIF_TRAP_NP_TrapReqData56__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA56__NBIF_TRAP_NP_TrapReqData56_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA57 +#define NBIF_TRAP_NP_REQUEST_DATA57__NBIF_TRAP_NP_TrapReqData57__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA57__NBIF_TRAP_NP_TrapReqData57_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA58 +#define NBIF_TRAP_NP_REQUEST_DATA58__NBIF_TRAP_NP_TrapReqData58__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA58__NBIF_TRAP_NP_TrapReqData58_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA59 +#define NBIF_TRAP_NP_REQUEST_DATA59__NBIF_TRAP_NP_TrapReqData59__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA59__NBIF_TRAP_NP_TrapReqData59_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA60 +#define NBIF_TRAP_NP_REQUEST_DATA60__NBIF_TRAP_NP_TrapReqData60__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA60__NBIF_TRAP_NP_TrapReqData60_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA61 +#define NBIF_TRAP_NP_REQUEST_DATA61__NBIF_TRAP_NP_TrapReqData61__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA61__NBIF_TRAP_NP_TrapReqData61_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA62 +#define NBIF_TRAP_NP_REQUEST_DATA62__NBIF_TRAP_NP_TrapReqData62__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA62__NBIF_TRAP_NP_TrapReqData62_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_REQUEST_DATA63 +#define NBIF_TRAP_NP_REQUEST_DATA63__NBIF_TRAP_NP_TrapReqData63__SHIFT 0x0 +#define NBIF_TRAP_NP_REQUEST_DATA63__NBIF_TRAP_NP_TrapReqData63_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_CONTROL +#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspTrigger__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspReqPassthru__SHIFT 0x1 +#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspTrigger_MASK 0x00000001L +#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspReqPassthru_MASK 0x00000002L +//NBIF_TRAP_NP_RESPONSE0 +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspPassPW__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspStatus__SHIFT 0x4 +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspDataStatus__SHIFT 0x10 +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspPassPW_MASK 0x00000001L +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspStatus_MASK 0x000000F0L +#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspDataStatus_MASK 0x00FF0000L +//NBIF_TRAP_NP_RESPONSE1 +#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspCplid__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspSrcdata__SHIFT 0x10 +#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspCplid_MASK 0x0000FFFFL +#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspSrcdata_MASK 0x003F0000L +//NBIF_TRAP_NP_RESPONSE2 +#define NBIF_TRAP_NP_RESPONSE2__NBIF_TRAP_NP_TrapRspUser0__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE2__NBIF_TRAP_NP_TrapRspUser0_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE3 +#define NBIF_TRAP_NP_RESPONSE3__NBIF_TRAP_NP_TrapRspUser1__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE3__NBIF_TRAP_NP_TrapRspUser1_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE4 +#define NBIF_TRAP_NP_RESPONSE4__NBIF_TRAP_NP_TrapRspUser2__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE4__NBIF_TRAP_NP_TrapRspUser2_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE5 +#define NBIF_TRAP_NP_RESPONSE5__NBIF_TRAP_NP_TrapRspUser3__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE5__NBIF_TRAP_NP_TrapRspUser3_MASK 0x00000007L +//NBIF_TRAP_NP_RESPONSE_DATA0 +#define NBIF_TRAP_NP_RESPONSE_DATA0__NBIF_TRAP_NP_TrapRdRspData0__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA0__NBIF_TRAP_NP_TrapRdRspData0_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA1 +#define NBIF_TRAP_NP_RESPONSE_DATA1__NBIF_TRAP_NP_TrapRdRspData1__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA1__NBIF_TRAP_NP_TrapRdRspData1_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA2 +#define NBIF_TRAP_NP_RESPONSE_DATA2__NBIF_TRAP_NP_TrapRdRspData2__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA2__NBIF_TRAP_NP_TrapRdRspData2_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA3 +#define NBIF_TRAP_NP_RESPONSE_DATA3__NBIF_TRAP_NP_TrapRdRspData3__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA3__NBIF_TRAP_NP_TrapRdRspData3_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA4 +#define NBIF_TRAP_NP_RESPONSE_DATA4__NBIF_TRAP_NP_TrapRdRspData4__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA4__NBIF_TRAP_NP_TrapRdRspData4_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA5 +#define NBIF_TRAP_NP_RESPONSE_DATA5__NBIF_TRAP_NP_TrapRdRspData5__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA5__NBIF_TRAP_NP_TrapRdRspData5_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA6 +#define NBIF_TRAP_NP_RESPONSE_DATA6__NBIF_TRAP_NP_TrapRdRspData6__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA6__NBIF_TRAP_NP_TrapRdRspData6_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA7 +#define NBIF_TRAP_NP_RESPONSE_DATA7__NBIF_TRAP_NP_TrapRdRspData7__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA7__NBIF_TRAP_NP_TrapRdRspData7_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA8 +#define NBIF_TRAP_NP_RESPONSE_DATA8__NBIF_TRAP_NP_TrapRdRspData8__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA8__NBIF_TRAP_NP_TrapRdRspData8_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA9 +#define NBIF_TRAP_NP_RESPONSE_DATA9__NBIF_TRAP_NP_TrapRdRspData9__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA9__NBIF_TRAP_NP_TrapRdRspData9_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA10 +#define NBIF_TRAP_NP_RESPONSE_DATA10__NBIF_TRAP_NP_TrapRdRspData10__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA10__NBIF_TRAP_NP_TrapRdRspData10_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA11 +#define NBIF_TRAP_NP_RESPONSE_DATA11__NBIF_TRAP_NP_TrapRdRspData11__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA11__NBIF_TRAP_NP_TrapRdRspData11_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA12 +#define NBIF_TRAP_NP_RESPONSE_DATA12__NBIF_TRAP_NP_TrapRdRspData12__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA12__NBIF_TRAP_NP_TrapRdRspData12_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA13 +#define NBIF_TRAP_NP_RESPONSE_DATA13__NBIF_TRAP_NP_TrapRdRspData13__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA13__NBIF_TRAP_NP_TrapRdRspData13_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA14 +#define NBIF_TRAP_NP_RESPONSE_DATA14__NBIF_TRAP_NP_TrapRdRspData14__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA14__NBIF_TRAP_NP_TrapRdRspData14_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA15 +#define NBIF_TRAP_NP_RESPONSE_DATA15__NBIF_TRAP_NP_TrapRdRspData15__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA15__NBIF_TRAP_NP_TrapRdRspData15_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA16 +#define NBIF_TRAP_NP_RESPONSE_DATA16__NBIF_TRAP_NP_TrapRdRspData16__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA16__NBIF_TRAP_NP_TrapRdRspData16_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA17 +#define NBIF_TRAP_NP_RESPONSE_DATA17__NBIF_TRAP_NP_TrapRdRspData17__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA17__NBIF_TRAP_NP_TrapRdRspData17_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA18 +#define NBIF_TRAP_NP_RESPONSE_DATA18__NBIF_TRAP_NP_TrapRdRspData18__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA18__NBIF_TRAP_NP_TrapRdRspData18_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA19 +#define NBIF_TRAP_NP_RESPONSE_DATA19__NBIF_TRAP_NP_TrapRdRspData19__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA19__NBIF_TRAP_NP_TrapRdRspData19_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA20 +#define NBIF_TRAP_NP_RESPONSE_DATA20__NBIF_TRAP_NP_TrapRdRspData20__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA20__NBIF_TRAP_NP_TrapRdRspData20_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA21 +#define NBIF_TRAP_NP_RESPONSE_DATA21__NBIF_TRAP_NP_TrapRdRspData21__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA21__NBIF_TRAP_NP_TrapRdRspData21_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA22 +#define NBIF_TRAP_NP_RESPONSE_DATA22__NBIF_TRAP_NP_TrapRdRspData22__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA22__NBIF_TRAP_NP_TrapRdRspData22_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA23 +#define NBIF_TRAP_NP_RESPONSE_DATA23__NBIF_TRAP_NP_TrapRdRspData23__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA23__NBIF_TRAP_NP_TrapRdRspData23_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA24 +#define NBIF_TRAP_NP_RESPONSE_DATA24__NBIF_TRAP_NP_TrapRdRspData24__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA24__NBIF_TRAP_NP_TrapRdRspData24_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA25 +#define NBIF_TRAP_NP_RESPONSE_DATA25__NBIF_TRAP_NP_TrapRdRspData25__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA25__NBIF_TRAP_NP_TrapRdRspData25_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA26 +#define NBIF_TRAP_NP_RESPONSE_DATA26__NBIF_TRAP_NP_TrapRdRspData26__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA26__NBIF_TRAP_NP_TrapRdRspData26_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA27 +#define NBIF_TRAP_NP_RESPONSE_DATA27__NBIF_TRAP_NP_TrapRdRspData27__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA27__NBIF_TRAP_NP_TrapRdRspData27_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA28 +#define NBIF_TRAP_NP_RESPONSE_DATA28__NBIF_TRAP_NP_TrapRdRspData28__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA28__NBIF_TRAP_NP_TrapRdRspData28_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA29 +#define NBIF_TRAP_NP_RESPONSE_DATA29__NBIF_TRAP_NP_TrapRdRspData29__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA29__NBIF_TRAP_NP_TrapRdRspData29_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA30 +#define NBIF_TRAP_NP_RESPONSE_DATA30__NBIF_TRAP_NP_TrapRdRspData30__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA30__NBIF_TRAP_NP_TrapRdRspData30_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA31 +#define NBIF_TRAP_NP_RESPONSE_DATA31__NBIF_TRAP_NP_TrapRdRspData31__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA31__NBIF_TRAP_NP_TrapRdRspData31_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA32 +#define NBIF_TRAP_NP_RESPONSE_DATA32__NBIF_TRAP_NP_TrapRdRspData32__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA32__NBIF_TRAP_NP_TrapRdRspData32_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA33 +#define NBIF_TRAP_NP_RESPONSE_DATA33__NBIF_TRAP_NP_TrapRdRspData33__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA33__NBIF_TRAP_NP_TrapRdRspData33_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA34 +#define NBIF_TRAP_NP_RESPONSE_DATA34__NBIF_TRAP_NP_TrapRdRspData34__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA34__NBIF_TRAP_NP_TrapRdRspData34_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA35 +#define NBIF_TRAP_NP_RESPONSE_DATA35__NBIF_TRAP_NP_TrapRdRspData35__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA35__NBIF_TRAP_NP_TrapRdRspData35_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA36 +#define NBIF_TRAP_NP_RESPONSE_DATA36__NBIF_TRAP_NP_TrapRdRspData36__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA36__NBIF_TRAP_NP_TrapRdRspData36_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA37 +#define NBIF_TRAP_NP_RESPONSE_DATA37__NBIF_TRAP_NP_TrapRdRspData37__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA37__NBIF_TRAP_NP_TrapRdRspData37_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA38 +#define NBIF_TRAP_NP_RESPONSE_DATA38__NBIF_TRAP_NP_TrapRdRspData38__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA38__NBIF_TRAP_NP_TrapRdRspData38_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA39 +#define NBIF_TRAP_NP_RESPONSE_DATA39__NBIF_TRAP_NP_TrapRdRspData39__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA39__NBIF_TRAP_NP_TrapRdRspData39_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA40 +#define NBIF_TRAP_NP_RESPONSE_DATA40__NBIF_TRAP_NP_TrapRdRspData40__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA40__NBIF_TRAP_NP_TrapRdRspData40_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA41 +#define NBIF_TRAP_NP_RESPONSE_DATA41__NBIF_TRAP_NP_TrapRdRspData41__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA41__NBIF_TRAP_NP_TrapRdRspData41_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA42 +#define NBIF_TRAP_NP_RESPONSE_DATA42__NBIF_TRAP_NP_TrapRdRspData42__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA42__NBIF_TRAP_NP_TrapRdRspData42_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA43 +#define NBIF_TRAP_NP_RESPONSE_DATA43__NBIF_TRAP_NP_TrapRdRspData43__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA43__NBIF_TRAP_NP_TrapRdRspData43_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA44 +#define NBIF_TRAP_NP_RESPONSE_DATA44__NBIF_TRAP_NP_TrapRdRspData44__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA44__NBIF_TRAP_NP_TrapRdRspData44_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA45 +#define NBIF_TRAP_NP_RESPONSE_DATA45__NBIF_TRAP_NP_TrapRdRspData45__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA45__NBIF_TRAP_NP_TrapRdRspData45_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA46 +#define NBIF_TRAP_NP_RESPONSE_DATA46__NBIF_TRAP_NP_TrapRdRspData46__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA46__NBIF_TRAP_NP_TrapRdRspData46_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA47 +#define NBIF_TRAP_NP_RESPONSE_DATA47__NBIF_TRAP_NP_TrapRdRspData47__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA47__NBIF_TRAP_NP_TrapRdRspData47_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA48 +#define NBIF_TRAP_NP_RESPONSE_DATA48__NBIF_TRAP_NP_TrapRdRspData48__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA48__NBIF_TRAP_NP_TrapRdRspData48_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA49 +#define NBIF_TRAP_NP_RESPONSE_DATA49__NBIF_TRAP_NP_TrapRdRspData49__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA49__NBIF_TRAP_NP_TrapRdRspData49_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA50 +#define NBIF_TRAP_NP_RESPONSE_DATA50__NBIF_TRAP_NP_TrapRdRspData50__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA50__NBIF_TRAP_NP_TrapRdRspData50_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA51 +#define NBIF_TRAP_NP_RESPONSE_DATA51__NBIF_TRAP_NP_TrapRdRspData51__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA51__NBIF_TRAP_NP_TrapRdRspData51_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA52 +#define NBIF_TRAP_NP_RESPONSE_DATA52__NBIF_TRAP_NP_TrapRdRspData52__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA52__NBIF_TRAP_NP_TrapRdRspData52_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA53 +#define NBIF_TRAP_NP_RESPONSE_DATA53__NBIF_TRAP_NP_TrapRdRspData53__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA53__NBIF_TRAP_NP_TrapRdRspData53_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA54 +#define NBIF_TRAP_NP_RESPONSE_DATA54__NBIF_TRAP_NP_TrapRdRspData54__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA54__NBIF_TRAP_NP_TrapRdRspData54_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA55 +#define NBIF_TRAP_NP_RESPONSE_DATA55__NBIF_TRAP_NP_TrapRdRspData55__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA55__NBIF_TRAP_NP_TrapRdRspData55_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA56 +#define NBIF_TRAP_NP_RESPONSE_DATA56__NBIF_TRAP_NP_TrapRdRspData56__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA56__NBIF_TRAP_NP_TrapRdRspData56_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA57 +#define NBIF_TRAP_NP_RESPONSE_DATA57__NBIF_TRAP_NP_TrapRdRspData57__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA57__NBIF_TRAP_NP_TrapRdRspData57_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA58 +#define NBIF_TRAP_NP_RESPONSE_DATA58__NBIF_TRAP_NP_TrapRdRspData58__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA58__NBIF_TRAP_NP_TrapRdRspData58_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA59 +#define NBIF_TRAP_NP_RESPONSE_DATA59__NBIF_TRAP_NP_TrapRdRspData59__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA59__NBIF_TRAP_NP_TrapRdRspData59_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA60 +#define NBIF_TRAP_NP_RESPONSE_DATA60__NBIF_TRAP_NP_TrapRdRspData60__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA60__NBIF_TRAP_NP_TrapRdRspData60_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA61 +#define NBIF_TRAP_NP_RESPONSE_DATA61__NBIF_TRAP_NP_TrapRdRspData61__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA61__NBIF_TRAP_NP_TrapRdRspData61_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA62 +#define NBIF_TRAP_NP_RESPONSE_DATA62__NBIF_TRAP_NP_TrapRdRspData62__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA62__NBIF_TRAP_NP_TrapRdRspData62_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_RESPONSE_DATA63 +#define NBIF_TRAP_NP_RESPONSE_DATA63__NBIF_TRAP_NP_TrapRdRspData63__SHIFT 0x0 +#define NBIF_TRAP_NP_RESPONSE_DATA63__NBIF_TRAP_NP_TrapRdRspData63_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_0_CONTROL0 +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0En__SHIFT 0x0 +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0En_MASK 0x00000001L +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_0_ADDRESS_LO +#define NBIF_TRAP_NP_0_ADDRESS_LO__NBIF_TRAP_NP_Trap0AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_0_ADDRESS_LO__NBIF_TRAP_NP_Trap0AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_0_ADDRESS_HI +#define NBIF_TRAP_NP_0_ADDRESS_HI__NBIF_TRAP_NP_Trap0AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_0_ADDRESS_HI__NBIF_TRAP_NP_Trap0AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_0_COMMAND +#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_0_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_0_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap0AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_0_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap0AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_0_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_0_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap0AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_0_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap0AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_0_COMMAND_MASK +#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_1_CONTROL0 +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1En__SHIFT 0x0 +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1En_MASK 0x00000001L +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_1_ADDRESS_LO +#define NBIF_TRAP_NP_1_ADDRESS_LO__NBIF_TRAP_NP_Trap1AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_1_ADDRESS_LO__NBIF_TRAP_NP_Trap1AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_1_ADDRESS_HI +#define NBIF_TRAP_NP_1_ADDRESS_HI__NBIF_TRAP_NP_Trap1AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_1_ADDRESS_HI__NBIF_TRAP_NP_Trap1AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_1_COMMAND +#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_1_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_1_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap1AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_1_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap1AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_1_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_1_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap1AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_1_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap1AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_1_COMMAND_MASK +#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_2_CONTROL0 +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2En__SHIFT 0x0 +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2En_MASK 0x00000001L +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_2_ADDRESS_LO +#define NBIF_TRAP_NP_2_ADDRESS_LO__NBIF_TRAP_NP_Trap2AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_2_ADDRESS_LO__NBIF_TRAP_NP_Trap2AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_2_ADDRESS_HI +#define NBIF_TRAP_NP_2_ADDRESS_HI__NBIF_TRAP_NP_Trap2AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_2_ADDRESS_HI__NBIF_TRAP_NP_Trap2AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_2_COMMAND +#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_2_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_2_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap2AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_2_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap2AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_2_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_2_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap2AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_2_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap2AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_2_COMMAND_MASK +#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_3_CONTROL0 +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3En__SHIFT 0x0 +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3En_MASK 0x00000001L +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_3_ADDRESS_LO +#define NBIF_TRAP_NP_3_ADDRESS_LO__NBIF_TRAP_NP_Trap3AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_3_ADDRESS_LO__NBIF_TRAP_NP_Trap3AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_3_ADDRESS_HI +#define NBIF_TRAP_NP_3_ADDRESS_HI__NBIF_TRAP_NP_Trap3AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_3_ADDRESS_HI__NBIF_TRAP_NP_Trap3AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_3_COMMAND +#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_3_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_3_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap3AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_3_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap3AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_3_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_3_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap3AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_3_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap3AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_3_COMMAND_MASK +#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_4_CONTROL0 +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4En__SHIFT 0x0 +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4En_MASK 0x00000001L +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_4_ADDRESS_LO +#define NBIF_TRAP_NP_4_ADDRESS_LO__NBIF_TRAP_NP_Trap4AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_4_ADDRESS_LO__NBIF_TRAP_NP_Trap4AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_4_ADDRESS_HI +#define NBIF_TRAP_NP_4_ADDRESS_HI__NBIF_TRAP_NP_Trap4AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_4_ADDRESS_HI__NBIF_TRAP_NP_Trap4AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_4_COMMAND +#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_4_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_4_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap4AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_4_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap4AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_4_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_4_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap4AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_4_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap4AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_4_COMMAND_MASK +#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_5_CONTROL0 +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5En__SHIFT 0x0 +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5En_MASK 0x00000001L +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_5_ADDRESS_LO +#define NBIF_TRAP_NP_5_ADDRESS_LO__NBIF_TRAP_NP_Trap5AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_5_ADDRESS_LO__NBIF_TRAP_NP_Trap5AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_5_ADDRESS_HI +#define NBIF_TRAP_NP_5_ADDRESS_HI__NBIF_TRAP_NP_Trap5AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_5_ADDRESS_HI__NBIF_TRAP_NP_Trap5AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_5_COMMAND +#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_5_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_5_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap5AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_5_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap5AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_5_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_5_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap5AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_5_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap5AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_5_COMMAND_MASK +#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_6_CONTROL0 +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6En__SHIFT 0x0 +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6En_MASK 0x00000001L +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_6_ADDRESS_LO +#define NBIF_TRAP_NP_6_ADDRESS_LO__NBIF_TRAP_NP_Trap6AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_6_ADDRESS_LO__NBIF_TRAP_NP_Trap6AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_6_ADDRESS_HI +#define NBIF_TRAP_NP_6_ADDRESS_HI__NBIF_TRAP_NP_Trap6AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_6_ADDRESS_HI__NBIF_TRAP_NP_Trap6AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_6_COMMAND +#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_6_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_6_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap6AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_6_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap6AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_6_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_6_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap6AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_6_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap6AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_6_COMMAND_MASK +#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_7_CONTROL0 +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7En__SHIFT 0x0 +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7En_MASK 0x00000001L +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_7_ADDRESS_LO +#define NBIF_TRAP_NP_7_ADDRESS_LO__NBIF_TRAP_NP_Trap7AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_7_ADDRESS_LO__NBIF_TRAP_NP_Trap7AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_7_ADDRESS_HI +#define NBIF_TRAP_NP_7_ADDRESS_HI__NBIF_TRAP_NP_Trap7AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_7_ADDRESS_HI__NBIF_TRAP_NP_Trap7AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_7_COMMAND +#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_7_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_7_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap7AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_7_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap7AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_7_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_7_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap7AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_7_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap7AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_7_COMMAND_MASK +#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_8_CONTROL0 +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8En__SHIFT 0x0 +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8En_MASK 0x00000001L +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_8_ADDRESS_LO +#define NBIF_TRAP_NP_8_ADDRESS_LO__NBIF_TRAP_NP_Trap8AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_8_ADDRESS_LO__NBIF_TRAP_NP_Trap8AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_8_ADDRESS_HI +#define NBIF_TRAP_NP_8_ADDRESS_HI__NBIF_TRAP_NP_Trap8AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_8_ADDRESS_HI__NBIF_TRAP_NP_Trap8AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_8_COMMAND +#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_8_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_8_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap8AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_8_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap8AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_8_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_8_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap8AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_8_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap8AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_8_COMMAND_MASK +#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_9_CONTROL0 +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9En__SHIFT 0x0 +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9En_MASK 0x00000001L +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_9_ADDRESS_LO +#define NBIF_TRAP_NP_9_ADDRESS_LO__NBIF_TRAP_NP_Trap9AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_9_ADDRESS_LO__NBIF_TRAP_NP_Trap9AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_9_ADDRESS_HI +#define NBIF_TRAP_NP_9_ADDRESS_HI__NBIF_TRAP_NP_Trap9AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_9_ADDRESS_HI__NBIF_TRAP_NP_Trap9AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_9_COMMAND +#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_9_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_9_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap9AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_9_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap9AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_9_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_9_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap9AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_9_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap9AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_9_COMMAND_MASK +#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_10_CONTROL0 +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10En__SHIFT 0x0 +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10En_MASK 0x00000001L +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_10_ADDRESS_LO +#define NBIF_TRAP_NP_10_ADDRESS_LO__NBIF_TRAP_NP_Trap10AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_10_ADDRESS_LO__NBIF_TRAP_NP_Trap10AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_10_ADDRESS_HI +#define NBIF_TRAP_NP_10_ADDRESS_HI__NBIF_TRAP_NP_Trap10AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_10_ADDRESS_HI__NBIF_TRAP_NP_Trap10AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_10_COMMAND +#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_10_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_10_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap10AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_10_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap10AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_10_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_10_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap10AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_10_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap10AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_10_COMMAND_MASK +#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_11_CONTROL0 +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11En__SHIFT 0x0 +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11En_MASK 0x00000001L +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_11_ADDRESS_LO +#define NBIF_TRAP_NP_11_ADDRESS_LO__NBIF_TRAP_NP_Trap11AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_11_ADDRESS_LO__NBIF_TRAP_NP_Trap11AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_11_ADDRESS_HI +#define NBIF_TRAP_NP_11_ADDRESS_HI__NBIF_TRAP_NP_Trap11AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_11_ADDRESS_HI__NBIF_TRAP_NP_Trap11AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_11_COMMAND +#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_11_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_11_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap11AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_11_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap11AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_11_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_11_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap11AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_11_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap11AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_11_COMMAND_MASK +#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_12_CONTROL0 +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12En__SHIFT 0x0 +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12En_MASK 0x00000001L +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_12_ADDRESS_LO +#define NBIF_TRAP_NP_12_ADDRESS_LO__NBIF_TRAP_NP_Trap12AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_12_ADDRESS_LO__NBIF_TRAP_NP_Trap12AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_12_ADDRESS_HI +#define NBIF_TRAP_NP_12_ADDRESS_HI__NBIF_TRAP_NP_Trap12AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_12_ADDRESS_HI__NBIF_TRAP_NP_Trap12AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_12_COMMAND +#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_12_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_12_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap12AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_12_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap12AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_12_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_12_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap12AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_12_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap12AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_12_COMMAND_MASK +#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_13_CONTROL0 +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13En__SHIFT 0x0 +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13En_MASK 0x00000001L +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_13_ADDRESS_LO +#define NBIF_TRAP_NP_13_ADDRESS_LO__NBIF_TRAP_NP_Trap13AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_13_ADDRESS_LO__NBIF_TRAP_NP_Trap13AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_13_ADDRESS_HI +#define NBIF_TRAP_NP_13_ADDRESS_HI__NBIF_TRAP_NP_Trap13AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_13_ADDRESS_HI__NBIF_TRAP_NP_Trap13AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_13_COMMAND +#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_13_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_13_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap13AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_13_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap13AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_13_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_13_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap13AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_13_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap13AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_13_COMMAND_MASK +#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_14_CONTROL0 +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14En__SHIFT 0x0 +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14En_MASK 0x00000001L +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_14_ADDRESS_LO +#define NBIF_TRAP_NP_14_ADDRESS_LO__NBIF_TRAP_NP_Trap14AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_14_ADDRESS_LO__NBIF_TRAP_NP_Trap14AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_14_ADDRESS_HI +#define NBIF_TRAP_NP_14_ADDRESS_HI__NBIF_TRAP_NP_Trap14AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_14_ADDRESS_HI__NBIF_TRAP_NP_Trap14AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_14_COMMAND +#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_14_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_14_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap14AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_14_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap14AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_14_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_14_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap14AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_14_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap14AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_14_COMMAND_MASK +#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_15_CONTROL0 +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15En__SHIFT 0x0 +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15SMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15CrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15En_MASK 0x00000001L +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15SMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15CrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2En_MASK 0x80000000L +//NBIF_TRAP_NP_15_ADDRESS_LO +#define NBIF_TRAP_NP_15_ADDRESS_LO__NBIF_TRAP_NP_Trap15AddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_15_ADDRESS_LO__NBIF_TRAP_NP_Trap15AddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_15_ADDRESS_HI +#define NBIF_TRAP_NP_15_ADDRESS_HI__NBIF_TRAP_NP_Trap15AddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_15_ADDRESS_HI__NBIF_TRAP_NP_Trap15AddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_15_COMMAND +#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_15_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_15_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap15AddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_15_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap15AddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_15_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_15_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap15AddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_15_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap15AddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_15_COMMAND_MASK +#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd1Mask_MASK 0x00003F00L +//NBIF_TRAP_NP_S2_CONTROL0 +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapEn__SHIFT 0x0 +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapSMUIntr__SHIFT 0x3 +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Offset__SHIFT 0x4 +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Ptr__SHIFT 0xe +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapCrossTrigger__SHIFT 0x18 +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2En__SHIFT 0x1f +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapEn_MASK 0x00000001L +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapSMUIntr_MASK 0x00000008L +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Offset_MASK 0x00003FF0L +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Ptr_MASK 0x00FFC000L +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapCrossTrigger_MASK 0x0F000000L +#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2En_MASK 0x80000000L +//NBIF_TRAP_NP_S2_ADDRESS_LO +#define NBIF_TRAP_NP_S2_ADDRESS_LO__NBIF_TRAP_NP_S2_TrapAddrLo__SHIFT 0x2 +#define NBIF_TRAP_NP_S2_ADDRESS_LO__NBIF_TRAP_NP_S2_TrapAddrLo_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_S2_ADDRESS_HI +#define NBIF_TRAP_NP_S2_ADDRESS_HI__NBIF_TRAP_NP_S2_TrapAddrHi__SHIFT 0x0 +#define NBIF_TRAP_NP_S2_ADDRESS_HI__NBIF_TRAP_NP_S2_TrapAddrHi_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_S2_COMMAND +#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd0__SHIFT 0x0 +#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd1__SHIFT 0x8 +#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd0_MASK 0x0000003FL +#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd1_MASK 0x00003F00L +//NBIF_TRAP_NP_S2_ADDRESS_LO_MASK +#define NBIF_TRAP_NP_S2_ADDRESS_LO_MASK__NBIF_TRAP_NP_S2_TrapAddrLoMask__SHIFT 0x2 +#define NBIF_TRAP_NP_S2_ADDRESS_LO_MASK__NBIF_TRAP_NP_S2_TrapAddrLoMask_MASK 0xFFFFFFFCL +//NBIF_TRAP_NP_S2_ADDRESS_HI_MASK +#define NBIF_TRAP_NP_S2_ADDRESS_HI_MASK__NBIF_TRAP_NP_S2_TrapAddrHiMask__SHIFT 0x0 +#define NBIF_TRAP_NP_S2_ADDRESS_HI_MASK__NBIF_TRAP_NP_S2_TrapAddrHiMask_MASK 0xFFFFFFFFL +//NBIF_TRAP_NP_S2_COMMAND_MASK +#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd0Mask__SHIFT 0x0 +#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd1Mask__SHIFT 0x8 +#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd0Mask_MASK 0x0000003FL +#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd1Mask_MASK 0x00003F00L + + +// addressBlock: nbif0_nbif0_bif_ras_bif_ras_regblk +//BIFL_RAS_CENTRAL_CNTL +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS__SHIFT 0x1b +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS__SHIFT 0x1c +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT 0x1d +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT 0x1e +#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT 0x1f +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS_MASK 0x08000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS_MASK 0x10000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK 0x20000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK 0x40000000L +#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK 0x80000000L +//BIFL_RAS_CENTRAL_STATUS +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT 0x0 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT 0x1 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT 0x2 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT 0x3 +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT 0x1d +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT 0x1e +#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT 0x1f +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK 0x00000001L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK 0x00000002L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK 0x00000004L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK 0x00000008L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK 0x20000000L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK 0x40000000L +#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK 0x80000000L +//BIFL_RAS_LEAF0_CTRL +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF0_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF0_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF0_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF0_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF1_CTRL +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF1_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF1_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF1_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF1_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF2_CTRL +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF2_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF2_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF2_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF2_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF3_CTRL +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF3_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF3_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF3_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF3_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF4_CTRL +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF4_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF4_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF4_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF4_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF4_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF4_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF5_CTRL +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF5_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF5_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF5_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF5_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF5_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF5_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF5_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF5_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF6_CTRL +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF6_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF6_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF6_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF6_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF6_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF6_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF6_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF6_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF6_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF6_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF7_CTRL +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF7_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF7_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF7_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF7_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF7_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF7_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF7_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF7_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF7_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF7_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF8_CTRL +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF8_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF8_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF8_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF8_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF8_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF8_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF8_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF8_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF8_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF8_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF9_CTRL +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF9_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF9_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF9_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF9_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF9_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF9_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF9_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF9_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF9_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF9_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF10_CTRL +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF10_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF10_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF10_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF10_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF10_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF10_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF10_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF10_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF10_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF10_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF11_CTRL +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF11_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF11_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF11_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF11_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF11_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF11_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF11_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF11_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF11_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF11_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF12_CTRL +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF12_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF12_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF12_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF12_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF12_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF12_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF12_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF12_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF12_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF12_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF13_CTRL +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF13_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF13_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF13_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF13_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF13_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF13_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF13_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF13_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF13_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF13_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF14_CTRL +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF14_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF14_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF14_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF14_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF14_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF14_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF14_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF14_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF14_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF14_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF15_CTRL +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF15_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF15_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF15_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF15_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF15_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF15_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF15_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF15_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF15_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF15_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF16_CTRL +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF16_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF16_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF16_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF16_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF16_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF16_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF16_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF16_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF16_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF16_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF17_CTRL +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF17_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF17_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF17_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF17_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF17_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF17_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF17_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF17_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF17_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF17_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF18_CTRL +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF18_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF18_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF18_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF18_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF18_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF18_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF18_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF18_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF18_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF18_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF19_CTRL +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF19_CTRL__POISON_STALL_EN__SHIFT 0x2 +#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 +#define BIFL_RAS_LEAF19_CTRL__PARITY_STALL_EN__SHIFT 0x4 +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 +#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa +#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define BIFL_RAS_LEAF19_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define BIFL_RAS_LEAF19_CTRL__UCP_EN__SHIFT 0x15 +#define BIFL_RAS_LEAF19_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF19_CTRL__POISON_STALL_EN_MASK 0x00000004L +#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L +#define BIFL_RAS_LEAF19_CTRL__PARITY_STALL_EN_MASK 0x00000010L +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L +#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L +#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define BIFL_RAS_LEAF19_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define BIFL_RAS_LEAF19_CTRL__UCP_EN_MASK 0x00200000L +#define BIFL_RAS_LEAF19_CTRL__POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//BIFL_RAS_LEAF2_MISC_CTRL +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN__SHIFT 0x0 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN__SHIFT 0x1 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT 0x8 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT 0x9 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ__SHIFT 0xb +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK__SHIFT 0xc +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP__SHIFT 0xd +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN__SHIFT 0x10 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN__SHIFT 0x11 +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN_MASK 0x00000001L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN_MASK 0x00000002L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK 0x00000100L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK 0x00000200L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ_MASK 0x00000800L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK_MASK 0x00001000L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP_MASK 0x00002000L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN_MASK 0x00010000L +#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN_MASK 0x00020000L +//BIFL_RAS_LEAF2_MISC_CTRL2 +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID__SHIFT 0x0 +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG__SHIFT 0xb +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET__SHIFT 0x15 +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_MASK 0x000007FFL +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_MASK 0x001FF800L +#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET_MASK 0x7FE00000L +//BIFL_RAS_LEAF_NTB_CTRL +#define BIFL_RAS_LEAF_NTB_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x0 +#define BIFL_RAS_LEAF_NTB_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00000001L +//BIFL_RAS_LEAF0_STATUS +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF1_STATUS +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF2_STATUS +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF3_STATUS +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF4_STATUS +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF5_STATUS +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF5_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF5_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF5_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF5_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF6_STATUS +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF6_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF6_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF6_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF6_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF7_STATUS +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF7_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF7_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF7_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF7_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF8_STATUS +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF8_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF8_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF8_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF8_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF9_STATUS +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF9_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF9_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF9_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF9_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF10_STATUS +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF10_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF10_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF10_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF10_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF11_STATUS +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF11_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF11_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF11_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF11_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF12_STATUS +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF12_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF12_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF12_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF12_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF13_STATUS +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF13_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF13_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF13_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF13_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF14_STATUS +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF14_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF14_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF14_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF14_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF15_STATUS +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF15_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF15_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF15_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF15_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF16_STATUS +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF16_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF16_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF16_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF16_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF17_STATUS +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF17_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF17_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF17_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF17_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF18_STATUS +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF18_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF18_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF18_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF18_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_RAS_LEAF19_STATUS +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_RECV__SHIFT 0x0 +#define BIFL_RAS_LEAF19_STATUS__POISON_ERR_DET__SHIFT 0x1 +#define BIFL_RAS_LEAF19_STATUS__PARITY_ERR_DET__SHIFT 0x2 +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa +#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_RECV_MASK 0x00000001L +#define BIFL_RAS_LEAF19_STATUS__POISON_ERR_DET_MASK 0x00000002L +#define BIFL_RAS_LEAF19_STATUS__PARITY_ERR_DET_MASK 0x00000004L +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP +#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_CNT__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_CNT__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_CNT_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_CNT_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT_MASK 0x000000F0L +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT 0x8 +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT 0xc +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT_MASK 0x00000F00L +#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT_MASK 0x0000F000L +//BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_LOG__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_LOG__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_LOG_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_LOG_MASK 0x000000F0L +//BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG_MASK 0x000000F0L +//BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP +#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG__SHIFT 0x0 +#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG__SHIFT 0x4 +#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG_MASK 0x0000000FL +#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG_MASK 0x000000F0L +//BIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP +//BIFL_IOHUB_RAS_IH_CNTL +#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT 0x0 +#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK 0x00000001L +//BIFL_RAS_VWR_FROM_IOHUB +#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT 0x0 +#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK 0x00000001L + + +// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_2_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_2_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_2_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT 0x5 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK 0x00000020L +//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_2_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK 0x00000010L +//RCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3 +#define RCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK 0x00000004L + + +// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1 +//RCC_DEV0_1_RCC_ERR_INT_CNTL +#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_BACO_CNTL_MISC +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_DEV0_1_RCC_RESET_EN +#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_DEV0_2_RCC_VDM_SUPPORT +#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_DEV0_1_RCC_GPUIOV_REGION +#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_DEV0_1_RCC_GPU_HOSTVM_EN +#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_DEV0_1_RCC_PEER_REG_RANGE0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_1_RCC_PEER_REG_RANGE1 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_2_RCC_BUS_CNTL +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_1_RCC_CONFIG_CNTL +#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_DEV0_1_RCC_CONFIG_F0_BASE +#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_DEV0_1_RCC_CONFIG_APER_SIZE +#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE +#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_DEV0_1_RCC_XDMA_LO +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_XDMA_HI +#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_1_RCC_BUSNUM_CNTL1 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_DEV0_1_RCC_BUSNUM_LIST0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_DEV0_1_RCC_BUSNUM_LIST1 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_DEV0_1_RCC_BUSNUM_CNTL2 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM +#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_HOST_BUSNUM +#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_2_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_2_RCC_CMN_LINK_CNTL +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG__SHIFT 0x10 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG_MASK 0x00FF0000L +//RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_2_RCC_MH_ARB_CNTL +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x0000FFFEL + + +// addressBlock: nbif0_nbif0_bif_bx_SYSDEC +//BIF_BX1_SYSHUB_INDEX_OVLP +#define BIF_BX1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 +#define BIF_BX1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL +//BIF_BX1_SYSHUB_DATA_OVLP +#define BIF_BX1_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 +#define BIF_BX1_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL +//BIF_BX1_SYSHUB_INDEX_HI_OVLP +#define BIF_BX1_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI__SHIFT 0x0 +#define BIF_BX1_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI_MASK 0x0000FFFFL +//BIF_BX1_PCIE_INDEX +#define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_DATA +#define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_INDEX2 +#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_DATA2 +#define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_INDEX_HI +#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x0000FFFFL +//BIF_BX1_PCIE_INDEX2_HI +#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x0000FFFFL +//BIF_BX1_SBIOS_SCRATCH_0 +#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_1 +#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_2 +#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_3 +#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_0 +#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_1 +#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_2 +#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_3 +#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_4 +#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_5 +#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_6 +#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_7 +#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_8 +#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_9 +#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_10 +#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_11 +#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_12 +#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_13 +#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_14 +#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_15 +#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_RLC_INTR_CNTL +//BIF_BX1_BIF_VCE_INTR_CNTL +//BIF_BX1_BIF_UVD_INTR_CNTL +//BIF_BX1_BIF_Engine_INTR_CNTL +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE__SHIFT 0x0 +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED__SHIFT 0x1 +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR__SHIFT 0x2 +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION__SHIFT 0x3 +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_INST_SEL__SHIFT 0x1b +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE_MASK 0x00000001L +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED_MASK 0x00000002L +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR_MASK 0x00000004L +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION_MASK 0x00000008L +#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_INST_SEL_MASK 0xF8000000L +//BIF_BX1_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_CNTL +#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_0 +#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_1 +#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_2 +#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_3 +#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_4 +#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_5 +#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_6 +#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_7 +#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_8 +#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_9 +#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_10 +#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_11 +#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_12 +#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_13 +#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_14 +#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_15 +#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_0 +#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_1 +#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_2 +#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_3 +#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_4 +#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_5 +#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_6 +#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_7 +#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_8 +#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_9 +#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_10 +#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_11 +#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_12 +#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_13 +#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_14 +#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_15 +#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_4 +#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_5 +#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_6 +#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_7 +#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_8 +#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_9 +#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_10 +#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_11 +#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_12 +#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_13 +#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_14 +#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_15 +#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF1_MM_INDEX +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF1_MM_DATA +#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MM_INDEX_HI +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1 +//BIF_BX1_CC_BIF_BX_STRAP0 +#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//BIF_BX1_CC_BIF_BX_PINSTRAP0 +//BIF_BX1_BIF_MM_INDACCESS_CNTL +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX1_BUS_CNTL +#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX1_BIF_SCRATCH0 +#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_SCRATCH1 +#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX1_BX_RESET_EN +#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX1_MM_CFGREGS_CNTL +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX1_BX_RESET_CNTL +#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX1_INTERRUPT_CNTL +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//BIF_BX1_INTERRUPT_CNTL2 +#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX1_CLKREQB_PAD_CNTL +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX1_BIF_FEATURES_CONTROL_MISC +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//BIF_BX1_HDP_ATOMIC_CONTROL_MISC +#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_BX1_BIF_DOORBELL_CNTL +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL__SHIFT 0x5 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL_MASK 0x00000020L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX1_BIF_DOORBELL_INT_CNTL +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_BX1_BIF_FB_EN +#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX1_BIF_INTR_CNTL +#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_BX1_BIF_MST_TRANS_PENDING_VF +#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX1_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX1_BACO_CNTL +#define BIF_BX1_BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BIF_BX1_BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10 +#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BIF_BX1_BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BIF_BX1_BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L +#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BX1_BIF_BACO_EXIT_TIME0 +#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER1 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BX1_BIF_BACO_EXIT_TIMER2 +#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER3 +#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER4 +#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_MEM_TYPE_CNTL +#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//BIF_BX1_NBIF_GFX_ADDR_LUT_0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_1 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_2 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_3 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_4 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_5 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_6 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_7 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_8 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_9 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_10 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_11 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_12 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_13 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_14 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_15 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_VF_REGWR_EN +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L +//BIF_BX1_VF_DOORBELL_EN +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L +//BIF_BX1_VF_FB_EN +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L +//BIF_BX1_VF_REGWR_STATUS +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_VF_DOORBELL_STATUS +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_VF_FB_STATUS +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX1_BIF_RB_CNTL +#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT 0x19 +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK 0x02000000L +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX1_BIF_RB_BASE +#define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_RB_RPTR +#define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX1_BIF_RB_WPTR +#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX1_BIF_RB_WPTR_ADDR_HI +#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX1_BIF_RB_WPTR_ADDR_LO +#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX1_MAILBOX_INDEX +#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX1_BACO_AZ_ENHANCE_CTRL +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET__SHIFT 0x2 +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE__SHIFT 0x10 +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO__SHIFT 0x11 +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO__SHIFT 0x1f +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET_MASK 0x00003FFCL +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE_MASK 0x00010000L +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO_MASK 0x00020000L +#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO_MASK 0x80000000L +//BIF_BX1_BIF_MP1_INTR_CTRL +#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L +//BIF_BX1_BIF_PERSTB_PAD_CNTL +#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX1_BIF_PX_EN_PAD_CNTL +#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL +//BIF_BX1_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX1_BIF_CLKREQB_PAD_CNTL +#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL +//BIF_BX1_BIF_PWRBRK_PAD_CNTL +#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL +//BIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE +#define BIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE__SHIFT 0x0 +#define BIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE_MASK 0x0000000FL + + +// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF1_BIF_BME_STATUS +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF1_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF1_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF1_BIF_TRANS_PENDING +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_CONTROL +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF1_MAILBOX_INT_CNTL +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF1_BIF_VMHV_MAILBOX +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_PF1_PARTITION_COMPUTE_CAP +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_PF1_PARTITION_MEM_CAP +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_PF1_PARTITION_COMPUTE_STATUS +#define BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_PF1_PARTITION_MEM_STATUS +#define BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK 0x0000000FL +#define BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1:1 +//RCC_STRAP2_RCC_BIF_STRAP0 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE__SHIFT 0x17 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK 0x00400000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE_MASK 0x00800000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP1 +#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT__SHIFT 0x4 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT_MASK 0x00000010L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP10 +//RCC_STRAP2_RCC_BIF_STRAP11 +//RCC_STRAP2_RCC_BIF_STRAP12 +//RCC_STRAP2_RCC_BIF_STRAP13 +#define RCC_STRAP2_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER_MASK 0x00000FFFL +//RCC_STRAP2_RCC_BIF_STRAP2 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWDS_SPT__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ARI_EN_UP__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWDS_SPT_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ARI_EN_UP_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP3 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_BIF_STRAP4 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_BIF_STRAP5 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP6 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN_MASK 0x00007C00L +#define RCC_STRAP2_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK 0xFFFF8000L +//RCC_STRAP2_RCC_BIF_STRAP7 +#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_GEN6_DIS__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_GEN6_DIS_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6_MASK 0x04000000L +//RCC_STRAP2_RCC_BIF_STRAP8 +//RCC_STRAP2_RCC_BIF_STRAP9 +//RCC_STRAP2_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0_MASK 0x03000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0_MASK 0x0C000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0_MASK 0x38000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0_MASK 0x00000E00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0_MASK 0x00002000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP2_RCC_DEV0_PORT_STRAP16 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0_MASK 0xFFFFFFFFL +//RCC_STRAP2_RCC_DEV0_PORT_STRAP17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0_MASK 0x0000E000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0_MASK 0x02000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0_MASK 0x0000000FL +//RCC_STRAP2_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0_MASK 0x000FF000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP19 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP22 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x0001F000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x003E0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0x07C00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK 0xF8000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP23 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP24 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0_MASK 0xFFFFFFFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0_MASK 0x10000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP1 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP10 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP11 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP12 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP13 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK 0x00FFF000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK 0x01000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP16 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK 0x00FFF000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP17 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK 0x01FFE000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1_MASK 0x000FF000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP19 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1__SHIFT 0xa +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1_MASK 0x00000400L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1_MASK 0x08000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP7 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1_MASK 0xC0000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP9 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1_MASK 0x10000000L + + +// addressBlock: nbif0_hpdma0_hpdma_private_hpdma_private_regblk +//NBIF_SDP_PERF_COUNTER_2 +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_0_SEL__SHIFT 0x0 +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_1_SEL__SHIFT 0x8 +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_2_SEL__SHIFT 0x10 +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_3_SEL__SHIFT 0x18 +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_0_SEL_MASK 0x000000FFL +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_1_SEL_MASK 0x0000FF00L +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_2_SEL_MASK 0x00FF0000L +#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_3_SEL_MASK 0xFF000000L +//NBIF_SHUB_TODET_CLIENT_STATUS3 +#define NBIF_SHUB_TODET_CLIENT_STATUS3__NBIF_SHUB_TODET_CLIENT_STATUS3__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS3__NBIF_SHUB_TODET_CLIENT_STATUS3_MASK 0x000003FFL +//BIF_AER_ERR_LOG_DEV0_F0 +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_DEV0_F0__SHIFT 0x5 +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_CLR_DEV0_F0__SHIFT 0x15 +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_DEV0_F0_MASK 0x00000020L +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00100000L +#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_CLR_DEV0_F0_MASK 0x00200000L +//BIF_AER_ERR_LOG_DEV0_F0_vf0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_OPCODE_DEV0_F0_vf0__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_LENGTH_DEV0_F0_vf0__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_NR_DEV0_F0_vf0__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__DMA_ON_BME_LOW_DEV0_F0_vf0__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf0__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf0__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf0__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf0__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_OPCODE_DEV0_F0_vf0_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_LENGTH_DEV0_F0_vf0_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_NR_DEV0_F0_vf0_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__DMA_ON_BME_LOW_DEV0_F0_vf0_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf0_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf0_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf0_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf0_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_OPCODE_DEV0_F0_vf1__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_LENGTH_DEV0_F0_vf1__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_NR_DEV0_F0_vf1__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__DMA_ON_BME_LOW_DEV0_F0_vf1__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf1__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf1__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf1__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf1__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_OPCODE_DEV0_F0_vf1_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_LENGTH_DEV0_F0_vf1_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_NR_DEV0_F0_vf1_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__DMA_ON_BME_LOW_DEV0_F0_vf1_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf1_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf1_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf1_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf1_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_OPCODE_DEV0_F0_vf2__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_LENGTH_DEV0_F0_vf2__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_NR_DEV0_F0_vf2__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__DMA_ON_BME_LOW_DEV0_F0_vf2__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf2__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf2__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf2__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf2__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_OPCODE_DEV0_F0_vf2_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_LENGTH_DEV0_F0_vf2_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_NR_DEV0_F0_vf2_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__DMA_ON_BME_LOW_DEV0_F0_vf2_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf2_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf2_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf2_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf2_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_OPCODE_DEV0_F0_vf3__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_LENGTH_DEV0_F0_vf3__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_NR_DEV0_F0_vf3__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__DMA_ON_BME_LOW_DEV0_F0_vf3__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf3__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf3__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf3__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf3__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_OPCODE_DEV0_F0_vf3_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_LENGTH_DEV0_F0_vf3_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_NR_DEV0_F0_vf3_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__DMA_ON_BME_LOW_DEV0_F0_vf3_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf3_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf3_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf3_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf3_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_OPCODE_DEV0_F0_vf4__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_LENGTH_DEV0_F0_vf4__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_NR_DEV0_F0_vf4__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__DMA_ON_BME_LOW_DEV0_F0_vf4__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf4__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf4__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf4__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf4__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_OPCODE_DEV0_F0_vf4_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_LENGTH_DEV0_F0_vf4_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_NR_DEV0_F0_vf4_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__DMA_ON_BME_LOW_DEV0_F0_vf4_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf4_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf4_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf4_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf4_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf5 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_OPCODE_DEV0_F0_vf5__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_LENGTH_DEV0_F0_vf5__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_NR_DEV0_F0_vf5__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__DMA_ON_BME_LOW_DEV0_F0_vf5__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf5__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf5__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf5__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf5__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_OPCODE_DEV0_F0_vf5_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_LENGTH_DEV0_F0_vf5_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_NR_DEV0_F0_vf5_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__DMA_ON_BME_LOW_DEV0_F0_vf5_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf5_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf5_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf5_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf5_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf6 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_OPCODE_DEV0_F0_vf6__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_LENGTH_DEV0_F0_vf6__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_NR_DEV0_F0_vf6__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__DMA_ON_BME_LOW_DEV0_F0_vf6__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf6__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf6__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf6__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf6__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_OPCODE_DEV0_F0_vf6_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_LENGTH_DEV0_F0_vf6_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_NR_DEV0_F0_vf6_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__DMA_ON_BME_LOW_DEV0_F0_vf6_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf6_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf6_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf6_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf6_MASK 0x00100000L +//BIF_AER_ERR_LOG_DEV0_F0_vf7 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_OPCODE_DEV0_F0_vf7__SHIFT 0x0 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7__SHIFT 0x1 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_LENGTH_DEV0_F0_vf7__SHIFT 0x2 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_NR_DEV0_F0_vf7__SHIFT 0x3 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__DMA_ON_BME_LOW_DEV0_F0_vf7__SHIFT 0x4 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf7__SHIFT 0x10 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7__SHIFT 0x11 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf7__SHIFT 0x12 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf7__SHIFT 0x13 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf7__SHIFT 0x14 +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_OPCODE_DEV0_F0_vf7_MASK 0x00000001L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7_MASK 0x00000002L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_LENGTH_DEV0_F0_vf7_MASK 0x00000004L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_NR_DEV0_F0_vf7_MASK 0x00000008L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__DMA_ON_BME_LOW_DEV0_F0_vf7_MASK 0x00000010L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf7_MASK 0x00010000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7_MASK 0x00020000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf7_MASK 0x00040000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf7_MASK 0x00080000L +#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf7_MASK 0x00100000L + + +// addressBlock: nbif0_hphost0_hphost_private_hphost_private_regblk +//NBIF_AON_SVA_DISABLE_SAD +#define NBIF_AON_SVA_DISABLE_SAD__NBIF_AON_SVA_DISABLE__SHIFT 0x0 +#define NBIF_AON_SVA_DISABLE_SAD__NBIF_AON_SVA_DISABLE_MASK 0x00000001L + + +// addressBlock: nbif0_nbif0_gdc_dma_sion_SIONDEC +//GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_BurstTarget_REG0 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_BurstTarget_REG1 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_TimeSlot_REG0 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_Req_TimeSlot_REG1 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_BurstTarget_REG0 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_BurstTarget_REG1 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_TimeSlot_REG0 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_Req_TimeSlot_REG1 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_BurstTarget_REG0 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_BurstTarget_REG1 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_TimeSlot_REG0 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_Req_TimeSlot_REG1 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_DMA_SION_CNTL_REG0 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L +#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L +//GDC_DMA_SION_CNTL_REG1 +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS__SHIFT 0x8 +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL +#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS_MASK 0x0000FF00L + + +// addressBlock: nbif0_nbif0_gdc_hst_sion_SIONDEC +//GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_BurstTarget_REG0 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_BurstTarget_REG1 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_TimeSlot_REG0 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_Req_TimeSlot_REG1 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_BurstTarget_REG0 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_BurstTarget_REG1 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_TimeSlot_REG0 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_Req_TimeSlot_REG1 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL +//GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL +//GDC_HST_SION_CNTL_REG0 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L +#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L +//GDC_HST_SION_CNTL_REG1 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS__SHIFT 0x8 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVE_ACTIVE__SHIFT 0x10 +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS_MASK 0x0000FF00L +#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVE_ACTIVE_MASK 0xFFFF0000L + + +// addressBlock: nbif0_nbif0_gdc_GDCDEC +//GDC1_NGDC_SDP_PORT_CTRL +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT 0x10 +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT 0x1f +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L +#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK 0x80000000L +//GDC1_SHUB_REGS_IF_CTL +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT 0x1 +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK 0x00000002L +//GDC1_NGDC_MGCG_CTRL +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS__SHIFT 0xe +#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT 0xf +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS_MASK 0x00004000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK 0x00008000L +//GDC1_S2A_MISC_CNTL +#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L +//GDC1_NGDC_MCA_SMN_CTRL0 +#define GDC1_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT 0x0 +#define GDC1_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK 0x00000001L +//GDC1_NGDC_EARLY_WAKEUP_CTRL +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS__SHIFT 0x0 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL__SHIFT 0x1 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN__SHIFT 0x2 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA__SHIFT 0x3 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5 +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS_MASK 0x00000001L +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL_MASK 0x00000002L +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN_MASK 0x00000004L +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA_MASK 0x00000008L +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L +#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L +//GDC1_GDC_DMA_SION_PCTRL +#define GDC1_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS__SHIFT 0x0 +#define GDC1_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS__SHIFT 0x3 +#define GDC1_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS__SHIFT 0x6 +#define GDC1_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS_MASK 0x00000001L +#define GDC1_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS_MASK 0x00000008L +#define GDC1_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS_MASK 0x00000040L +//GDC1_NGDC_MP4SDP_CNTL +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN__SHIFT 0x0 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL__SHIFT 0x1 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN__SHIFT 0x4 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL__SHIFT 0x5 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN__SHIFT 0x8 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL__SHIFT 0x9 +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN_MASK 0x00000001L +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL_MASK 0x00000006L +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN_MASK 0x00000010L +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL_MASK 0x00000060L +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN_MASK 0x00000100L +#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL_MASK 0x00000600L +//GDC1_DOORBELL_VCN_TARGET_VF0 +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF1 +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF2 +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF3 +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF4 +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF5 +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF6 +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6_MASK 0xF000L +//GDC1_DOORBELL_VCN_TARGET_VF7 +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7__SHIFT 0x0 +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7__SHIFT 0x4 +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7__SHIFT 0x8 +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7__SHIFT 0xc +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7_MASK 0x000FL +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7_MASK 0x00F0L +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7_MASK 0x0F00L +#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7_MASK 0xF000L +//GDC1_DOORBELL_ACCESS_EN_PF +#define GDC1_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF_MASK 0x00FFL +//GDC1_DOORBELL_ACCESS_EN_VF0 +#define GDC1_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF1 +#define GDC1_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF2 +#define GDC1_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF3 +#define GDC1_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF4 +#define GDC1_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF5 +#define GDC1_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF6 +#define GDC1_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6_MASK 0xFF00L +//GDC1_DOORBELL_ACCESS_EN_VF7 +#define GDC1_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7__SHIFT 0x0 +#define GDC1_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7__SHIFT 0x8 +#define GDC1_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7_MASK 0x00FFL +#define GDC1_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7_MASK 0xFF00L +//GDC1_NGDC_CNDI_BUS_PORT_CTRL +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK__SHIFT 0xc +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS__SHIFT 0xd +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK__SHIFT 0x19 +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE__SHIFT 0x1a +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK__SHIFT 0x1b +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS_MASK 0x00000FFFL +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK_MASK 0x00001000L +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS_MASK 0x01FFE000L +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK_MASK 0x02000000L +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE_MASK 0x04000000L +#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK_MASK 0x08000000L +//GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT 0x0 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT 0x4 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT 0x8 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT 0xc +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x10 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x11 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x12 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x13 +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK 0x0000000FL +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK 0x000000F0L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK 0x00000F00L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK 0x0000F000L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00010000L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00020000L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00040000L +#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00080000L + + +// addressBlock: nbif0_nbif0_gdc_ras_gdc_ras_regblk +//GDCSOC_ERR_RSP_CNTL +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS__SHIFT 0x0 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL__SHIFT 0x1 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN__SHIFT 0x2 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA__SHIFT 0x3 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5 +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS_MASK 0x00000001L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL_MASK 0x00000002L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN_MASK 0x00000004L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA_MASK 0x00000008L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L +#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L +//GDCSOC_RAS_CENTRAL_STATUS +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT 0x0 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT 0x1 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT 0x2 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT 0x3 +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK 0x00000001L +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK 0x00000002L +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK 0x00000004L +#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK 0x00000008L +//GDCSOC_RAS_LEAF0_CTRL +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF1_CTRL +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF2_CTRL +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF3_CTRL +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF4_CTRL +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF5_CTRL +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF6_CTRL +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF7_CTRL +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF8_CTRL +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF9_CTRL +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF10_CTRL +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF11_CTRL +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF12_CTRL +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF13_CTRL +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_STALL_EN__SHIFT 0x2 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_STALL_EN__SHIFT 0x4 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT 0x11 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT 0x12 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT 0x13 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT 0x14 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_UCP_EN__SHIFT 0x15 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT 0x16 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT 0x17 +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_STALL_EN_MASK 0x00000004L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_STALL_EN_MASK 0x00000010L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_LOG_MCA_MASK 0x00020000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_LOG_MCA_MASK 0x00040000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK 0x00080000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK 0x00100000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_UCP_EN_MASK 0x00200000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_PROPAGATION_LOG_MCA_MASK 0x00400000L +#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK 0x00800000L +//GDCSOC_RAS_LEAF0_STATUS +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF1_STATUS +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF2_STATUS +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF3_STATUS +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF4_STATUS +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF5_STATUS +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF6_STATUS +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF7_STATUS +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF8_STATUS +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF9_STATUS +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF10_STATUS +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF11_STATUS +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF12_STATUS +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L +//GDCSOC_RAS_LEAF13_STATUS +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_RECV__SHIFT 0x0 +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_POISON_ERR_DET__SHIFT 0x1 +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_PARITY_ERR_DET__SHIFT 0x2 +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_RECV_MASK 0x00000001L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_POISON_ERR_DET_MASK 0x00000002L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_PARITY_ERR_DET_MASK 0x00000004L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L +#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L + + +// addressBlock: nbif0_nbif0_gdc_sec_GDCSEC_DEC +//GDC_SEC_MCA_SMN_CTRL0 +#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR__SHIFT 0x0 +#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID__SHIFT 0x14 +#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR_MASK 0x000FFFFFL +#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID_MASK 0xFFF00000L +//GDC_SEC_MCA_SMN_CTRL1 +#define GDC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR__SHIFT 0x0 +#define GDC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_FLAG__SHIFT 0x10 +#define GDC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR_MASK 0x0000FFFFL +#define GDC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_FLAG_MASK 0x000F0000L +//XCD_DOORBELL_FENCE +#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0 +#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_INTR_ENABLE__SHIFT 0x1 +#define XCD_DOORBELL_FENCE__RMOTE_SDMA_SENT__SHIFT 0x8 +#define XCD_DOORBELL_FENCE__SDMA_0_SENT__SHIFT 0x9 +#define XCD_DOORBELL_FENCE__SDMA_1_SENT__SHIFT 0xa +#define XCD_DOORBELL_FENCE__SDMA_2_SENT__SHIFT 0xb +#define XCD_DOORBELL_FENCE__SDMA_3_SENT__SHIFT 0xc +#define XCD_DOORBELL_FENCE__SDMA_4_SENT__SHIFT 0xd +#define XCD_DOORBELL_FENCE__SDMA_5_SENT__SHIFT 0xe +#define XCD_DOORBELL_FENCE__SDMA_6_SENT__SHIFT 0xf +#define XCD_DOORBELL_FENCE__SDMA_7_SENT__SHIFT 0x10 +#define XCD_DOORBELL_FENCE__RMOTE_CP_SENT__SHIFT 0x11 +#define XCD_DOORBELL_FENCE__CP_0_SENT__SHIFT 0x12 +#define XCD_DOORBELL_FENCE__CP_1_SENT__SHIFT 0x13 +#define XCD_DOORBELL_FENCE__CP_2_SENT__SHIFT 0x14 +#define XCD_DOORBELL_FENCE__CP_3_SENT__SHIFT 0x15 +#define XCD_DOORBELL_FENCE__CP_4_SENT__SHIFT 0x16 +#define XCD_DOORBELL_FENCE__CP_5_SENT__SHIFT 0x17 +#define XCD_DOORBELL_FENCE__CP_6_SENT__SHIFT 0x18 +#define XCD_DOORBELL_FENCE__CP_7_SENT__SHIFT 0x19 +#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_SENT__SHIFT 0x1a +#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING__SHIFT 0x1b +#define XCD_DOORBELL_FENCE__SHUB_SLV_MODE__SHIFT 0x1c +#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L +#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_INTR_ENABLE_MASK 0x00000002L +#define XCD_DOORBELL_FENCE__RMOTE_SDMA_SENT_MASK 0x00000100L +#define XCD_DOORBELL_FENCE__SDMA_0_SENT_MASK 0x00000200L +#define XCD_DOORBELL_FENCE__SDMA_1_SENT_MASK 0x00000400L +#define XCD_DOORBELL_FENCE__SDMA_2_SENT_MASK 0x00000800L +#define XCD_DOORBELL_FENCE__SDMA_3_SENT_MASK 0x00001000L +#define XCD_DOORBELL_FENCE__SDMA_4_SENT_MASK 0x00002000L +#define XCD_DOORBELL_FENCE__SDMA_5_SENT_MASK 0x00004000L +#define XCD_DOORBELL_FENCE__SDMA_6_SENT_MASK 0x00008000L +#define XCD_DOORBELL_FENCE__SDMA_7_SENT_MASK 0x00010000L +#define XCD_DOORBELL_FENCE__RMOTE_CP_SENT_MASK 0x00020000L +#define XCD_DOORBELL_FENCE__CP_0_SENT_MASK 0x00040000L +#define XCD_DOORBELL_FENCE__CP_1_SENT_MASK 0x00080000L +#define XCD_DOORBELL_FENCE__CP_2_SENT_MASK 0x00100000L +#define XCD_DOORBELL_FENCE__CP_3_SENT_MASK 0x00200000L +#define XCD_DOORBELL_FENCE__CP_4_SENT_MASK 0x00400000L +#define XCD_DOORBELL_FENCE__CP_5_SENT_MASK 0x00800000L +#define XCD_DOORBELL_FENCE__CP_6_SENT_MASK 0x01000000L +#define XCD_DOORBELL_FENCE__CP_7_SENT_MASK 0x02000000L +#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_SENT_MASK 0x04000000L +#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING_MASK 0x08000000L +#define XCD_DOORBELL_FENCE__SHUB_SLV_MODE_MASK 0x10000000L +//SHUB_PWRBRK_DEGLITCH +#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x0 +#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x8 +#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_CYCLE_MASK 0x000000FFL +#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_BYPASS_MASK 0x00000100L +//SHUB_DIE_CTRL +#define SHUB_DIE_CTRL__SHUB_MST_DIE__SHIFT 0x0 +#define SHUB_DIE_CTRL__SHUB_MST_DIE_MASK 0x00000001L +//GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL +#define GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL__GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL__SHIFT 0x0 +#define GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL__GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL_MASK 0x00000007L +//XCD_DOORBELL_FENCE_1 +#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_FENCE__SHIFT 0x0 +#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_FENCE__SHIFT 0x1 +#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_FENCE__SHIFT 0x2 +#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_FENCE__SHIFT 0x3 +#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_FENCE__SHIFT 0x4 +#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_FENCE__SHIFT 0x5 +#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_FENCE__SHIFT 0x6 +#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_FENCE__SHIFT 0x7 +#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE__SHIFT 0x8 +#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_DISABLE__SHIFT 0x9 +#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_DISABLE__SHIFT 0xa +#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_DISABLE__SHIFT 0xb +#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_DISABLE__SHIFT 0xc +#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_DISABLE__SHIFT 0xd +#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_DISABLE__SHIFT 0xe +#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_DISABLE__SHIFT 0xf +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_0_REG__SHIFT 0x10 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_1_REG__SHIFT 0x11 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_2_REG__SHIFT 0x12 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_3_REG__SHIFT 0x13 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_4_REG__SHIFT 0x14 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_5_REG__SHIFT 0x15 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_6_REG__SHIFT 0x16 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_7_REG__SHIFT 0x17 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_0_REG__SHIFT 0x18 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_1_REG__SHIFT 0x19 +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_2_REG__SHIFT 0x1a +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_3_REG__SHIFT 0x1b +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_4_REG__SHIFT 0x1c +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_5_REG__SHIFT 0x1d +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_6_REG__SHIFT 0x1e +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_7_REG__SHIFT 0x1f +#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_FENCE_MASK 0x00000001L +#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_FENCE_MASK 0x00000002L +#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_FENCE_MASK 0x00000004L +#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_FENCE_MASK 0x00000008L +#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_FENCE_MASK 0x00000010L +#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_FENCE_MASK 0x00000020L +#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_FENCE_MASK 0x00000040L +#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_FENCE_MASK 0x00000080L +#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE_MASK 0x00000100L +#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_DISABLE_MASK 0x00000200L +#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_DISABLE_MASK 0x00000400L +#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_DISABLE_MASK 0x00000800L +#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_DISABLE_MASK 0x00001000L +#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_DISABLE_MASK 0x00002000L +#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_DISABLE_MASK 0x00004000L +#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_DISABLE_MASK 0x00008000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_0_REG_MASK 0x00010000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_1_REG_MASK 0x00020000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_2_REG_MASK 0x00040000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_3_REG_MASK 0x00080000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_4_REG_MASK 0x00100000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_5_REG_MASK 0x00200000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_6_REG_MASK 0x00400000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_7_REG_MASK 0x00800000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_0_REG_MASK 0x01000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_1_REG_MASK 0x02000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_2_REG_MASK 0x04000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_3_REG_MASK 0x08000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_4_REG_MASK 0x10000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_5_REG_MASK 0x20000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_6_REG_MASK 0x40000000L +#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_7_REG_MASK 0x80000000L +//NGDC_CNDI_DOORBELL_REQUSER_0 +#define NGDC_CNDI_DOORBELL_REQUSER_0__NGDC_CNDI_IH_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_0__NGDC_CNDI_IH_ReqUser_MASK 0x0000003FL +//NGDC_CNDI_DOORBELL_REQUSER_1 +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN0_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN1_ReqUser__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN2_ReqUser__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN3_ReqUser__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN0_ReqUser_MASK 0x0000003FL +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN1_ReqUser_MASK 0x00003F00L +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN2_ReqUser_MASK 0x003F0000L +#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN3_ReqUser_MASK 0x3F000000L +//NGDC_CNDI_DOORBELL_REQUSER_2 +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD0_SDMA_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD1_SDMA_ReqUser__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD2_SDMA_ReqUser__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD3_SDMA_ReqUser__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD0_SDMA_ReqUser_MASK 0x0000003FL +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD1_SDMA_ReqUser_MASK 0x00003F00L +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD2_SDMA_ReqUser_MASK 0x003F0000L +#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD3_SDMA_ReqUser_MASK 0x3F000000L +//NGDC_CNDI_DOORBELL_REQUSER_3 +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD4_SDMA_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD5_SDMA_ReqUser__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD6_SDMA_ReqUser__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD7_SDMA_ReqUser__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD4_SDMA_ReqUser_MASK 0x0000003FL +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD5_SDMA_ReqUser_MASK 0x00003F00L +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD6_SDMA_ReqUser_MASK 0x003F0000L +#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD7_SDMA_ReqUser_MASK 0x3F000000L +//NGDC_CNDI_DOORBELL_REQUSER_4 +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD0_CP_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD1_CP_ReqUser__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD2_CP_ReqUser__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD3_CP_ReqUser__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD0_CP_ReqUser_MASK 0x0000003FL +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD1_CP_ReqUser_MASK 0x00003F00L +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD2_CP_ReqUser_MASK 0x003F0000L +#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD3_CP_ReqUser_MASK 0x3F000000L +//NGDC_CNDI_DOORBELL_REQUSER_5 +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD4_CP_ReqUser__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD5_CP_ReqUser__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD6_CP_ReqUser__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD7_CP_ReqUser__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD4_CP_ReqUser_MASK 0x0000003FL +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD5_CP_ReqUser_MASK 0x00003F00L +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD6_CP_ReqUser_MASK 0x003F0000L +#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD7_CP_ReqUser_MASK 0x3F000000L +//NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_IH_REQADDR_32_33BIT__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN0_REQADDR_32_33BIT__SHIFT 0x2 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN1_REQADDR_32_33BIT__SHIFT 0x4 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN2_REQADDR_32_33BIT__SHIFT 0x6 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN3_REQADDR_32_33BIT__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD0_SDMA_REQADDR_32_33BIT__SHIFT 0xa +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD1_SDMA_REQADDR_32_33BIT__SHIFT 0xc +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD2_SDMA_REQADDR_32_33BIT__SHIFT 0xe +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD3_SDMA_REQADDR_32_33BIT__SHIFT 0x10 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD4_SDMA_REQADDR_32_33BIT__SHIFT 0x12 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD5_SDMA_REQADDR_32_33BIT__SHIFT 0x14 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD6_SDMA_REQADDR_32_33BIT__SHIFT 0x16 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD7_SDMA_REQADDR_32_33BIT__SHIFT 0x18 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_IH_REQADDR_32_33BIT_MASK 0x00000003L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN0_REQADDR_32_33BIT_MASK 0x0000000CL +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN1_REQADDR_32_33BIT_MASK 0x00000030L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN2_REQADDR_32_33BIT_MASK 0x000000C0L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN3_REQADDR_32_33BIT_MASK 0x00000300L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD0_SDMA_REQADDR_32_33BIT_MASK 0x00000C00L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD1_SDMA_REQADDR_32_33BIT_MASK 0x00003000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD2_SDMA_REQADDR_32_33BIT_MASK 0x0000C000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD3_SDMA_REQADDR_32_33BIT_MASK 0x00030000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD4_SDMA_REQADDR_32_33BIT_MASK 0x000C0000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD5_SDMA_REQADDR_32_33BIT_MASK 0x00300000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD6_SDMA_REQADDR_32_33BIT_MASK 0x00C00000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD7_SDMA_REQADDR_32_33BIT_MASK 0x03000000L +//NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD0_CP_REQADDR_32_33BIT__SHIFT 0x0 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD1_CP_REQADDR_32_33BIT__SHIFT 0x2 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD2_CP_REQADDR_32_33BIT__SHIFT 0x4 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD3_CP_REQADDR_32_33BIT__SHIFT 0x6 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD4_CP_REQADDR_32_33BIT__SHIFT 0x8 +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD5_CP_REQADDR_32_33BIT__SHIFT 0xa +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD6_CP_REQADDR_32_33BIT__SHIFT 0xc +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD7_CP_REQADDR_32_33BIT__SHIFT 0xe +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD0_CP_REQADDR_32_33BIT_MASK 0x00000003L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD1_CP_REQADDR_32_33BIT_MASK 0x0000000CL +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD2_CP_REQADDR_32_33BIT_MASK 0x00000030L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD3_CP_REQADDR_32_33BIT_MASK 0x000000C0L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD4_CP_REQADDR_32_33BIT_MASK 0x00000300L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD5_CP_REQADDR_32_33BIT_MASK 0x00000C00L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD6_CP_REQADDR_32_33BIT_MASK 0x00003000L +#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD7_CP_REQADDR_32_33BIT_MASK 0x0000C000L + + +// addressBlock: nbif0_nbif0_gdc_rst_GDCRST_DEC +//SHUB_PF_FLR_RST +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +//SHUB_GFX_DRV_VPU_RST +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L +//SHUB_LINK_RESET +#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0 +#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1 +#define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT 0x2 +#define SHUB_LINK_RESET__LINK_P3_RESET__SHIFT 0x3 +#define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L +#define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L +#define SHUB_LINK_RESET__LINK_P2_RESET_MASK 0x00000004L +#define SHUB_LINK_RESET__LINK_P3_RESET_MASK 0x00000008L +//SHUB_HST_NIC400_SW_CTRL_RESET +#define SHUB_HST_NIC400_SW_CTRL_RESET__HST_NIC400_SW_CTRL_RESET__SHIFT 0x0 +#define SHUB_HST_NIC400_SW_CTRL_RESET__HST_NIC400_SW_CTRL_RESET_MASK 0x00000001L +//SHUB_DEV0_PF0_VF_FLR_RST +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST__SHIFT 0x0 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST__SHIFT 0x1 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST__SHIFT 0x2 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST__SHIFT 0x3 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST__SHIFT 0x4 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST__SHIFT 0x5 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST__SHIFT 0x6 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST__SHIFT 0x7 +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST__SHIFT 0x1f +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST_MASK 0x00000001L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST_MASK 0x00000002L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST_MASK 0x00000004L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST_MASK 0x00000008L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST_MASK 0x00000010L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST_MASK 0x00000020L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST_MASK 0x00000040L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST_MASK 0x00000080L +#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST_MASK 0x80000000L +//SHUB_DEV0_PF1_VF_FLR_RST +#define SHUB_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST__SHIFT 0x0 +#define SHUB_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST_MASK 0x00000001L +//SHUB_HARD_RST_CTRL +#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 +#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L +//SHUB_SOFT_RST_CTRL +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L +//SHUB_SDP_PORT_RST +#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST__SHIFT 0x0 +#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT 0x1 +#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0x2 +#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT 0x3 +#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4 +#define SHUB_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST__SHIFT 0x5 +#define SHUB_SDP_PORT_RST__MP4_SDP_SDP_PORT_RST__SHIFT 0x6 +#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT 0x7 +#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8 +#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9 +#define SHUB_SDP_PORT_RST__DACCFE_NBIF_DMA_SDP_PORT_RST__SHIFT 0xa +#define SHUB_SDP_PORT_RST__DACCBE_NBIF_DMA_SDP_PORT_RST__SHIFT 0xb +#define SHUB_SDP_PORT_RST__DACCFE_HST_SDP_PORT_RST__SHIFT 0xc +#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT 0xd +#define SHUB_SDP_PORT_RST__HST_ATHUB_HST_SION_SDP_PORT_RST__SHIFT 0xe +#define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18 +#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST_MASK 0x00000001L +#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK 0x00000002L +#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00000004L +#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK 0x00000008L +#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L +#define SHUB_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST_MASK 0x00000020L +#define SHUB_SDP_PORT_RST__MP4_SDP_SDP_PORT_RST_MASK 0x00000040L +#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK 0x00000080L +#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L +#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L +#define SHUB_SDP_PORT_RST__DACCFE_NBIF_DMA_SDP_PORT_RST_MASK 0x00000400L +#define SHUB_SDP_PORT_RST__DACCBE_NBIF_DMA_SDP_PORT_RST_MASK 0x00000800L +#define SHUB_SDP_PORT_RST__DACCFE_HST_SDP_PORT_RST_MASK 0x00001000L +#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK 0x00002000L +#define SHUB_SDP_PORT_RST__HST_ATHUB_HST_SION_SDP_PORT_RST_MASK 0x00004000L +#define SHUB_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L +//SHUB_RST_MISC_TRL + + +// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC +//GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT 0x11 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN__SHIFT 0x1b +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT 0x1c +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK 0x0000003EL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK 0x0001FF80L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK 0x01FE0000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN_MASK 0x08000000L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK 0xF0000000L +//GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID__SHIFT 0x2 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID__SHIFT 0x4 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA__SHIFT 0x6 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE__SHIFT 0x7 +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE_MASK 0x00000003L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID_MASK 0x0000000CL +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID_MASK 0x00000030L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA_MASK 0x00000040L +#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L +//GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG +#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0 +#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE__SHIFT 0x1 +#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L +#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE_MASK 0x00000002L +//GDC_S2A1_NBIF_GFX_DOORBELL_STATUS +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN__SHIFT 0x10 +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST__SHIFT 0x18 +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN_MASK 0x00010000L +#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST_MASK 0x01000000L + + +// addressBlock: nbif0_nbif0_gdc_misc_GDCMISC_DEC +//GDC_DMA_SION_CRED_RST +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_CRED_RST__SHIFT 0x0 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_TX_DS_MSK__SHIFT 0x1 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_RX_DS_MSK__SHIFT 0x2 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_CRED_RST__SHIFT 0x4 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_TX_DS_MSK__SHIFT 0x5 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_RX_DS_MSK__SHIFT 0x6 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_CRED_RST__SHIFT 0x8 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_TX_DS_MSK__SHIFT 0x9 +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_RX_DS_MSK__SHIFT 0xa +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_CRED_RST_MASK 0x00000001L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_TX_DS_MSK_MASK 0x00000002L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_RX_DS_MSK_MASK 0x00000004L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_CRED_RST_MASK 0x00000010L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_TX_DS_MSK_MASK 0x00000020L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_RX_DS_MSK_MASK 0x00000040L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_CRED_RST_MASK 0x00000100L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_TX_DS_MSK_MASK 0x00000200L +#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_RX_DS_MSK_MASK 0x00000400L +//GDC_HST_SION_PER_SDP_PORT_RST +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_CRED_RST__SHIFT 0x0 +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_PORT_RST__SHIFT 0x1 +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_DISCON_DIS__SHIFT 0x2 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_TX_DS_MSK__SHIFT 0x3 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_RX_DS_MSK__SHIFT 0x4 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_CRED_RST__SHIFT 0x5 +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_PORT_RST__SHIFT 0x6 +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_DISCON_DIS__SHIFT 0x7 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_TX_DS_MSK__SHIFT 0x8 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_RX_DS_MSK__SHIFT 0x9 +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_CRED_RST_MASK 0x00000001L +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_PORT_RST_MASK 0x00000002L +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_DISCON_DIS_MASK 0x00000004L +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_TX_DS_MSK_MASK 0x00000008L +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_RX_DS_MSK_MASK 0x00000010L +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_CRED_RST_MASK 0x00000020L +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_PORT_RST_MASK 0x00000040L +#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_DISCON_DIS_MASK 0x00000080L +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_TX_DS_MSK_MASK 0x00000100L +#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_RX_DS_MSK_MASK 0x00000200L +//GDC_HST_SION_PER_SDP_CNTL_REG1 +//GDC_HST_AXI_STALL_FOR_FLUSH +#define GDC_HST_AXI_STALL_FOR_FLUSH__SHUB_HST_AXI_STALL_FOR_FLUSH_GFX__SHIFT 0x0 +#define GDC_HST_AXI_STALL_FOR_FLUSH__SHUB_HST_AXI_STALL_FOR_FLUSH_GFX_MASK 0x00000001L +//SYSHUB_SDP_DEBUG_COUNTER_CTRL +#define SYSHUB_SDP_DEBUG_COUNTER_CTRL__SHUB_SDP_DEBUG_COUNTER_EN__SHIFT 0x0 +#define SYSHUB_SDP_DEBUG_COUNTER_CTRL__SHUB_SDP_DEBUG_COUNTER_EN_MASK 0x00000001L +//NBIF_PWRBRK_IN_PAD_CNTL +#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL_BIT0__SHIFT 0x0 +#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL__SHIFT 0x1 +#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL_BIT0_MASK 0x00000001L +#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL_MASK 0x000000FEL +//NBIF_PWRBRK_OUT_PAD_CNTL +#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL_BIT0__SHIFT 0x0 +#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL__SHIFT 0x1 +#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL_BIT0_MASK 0x00000001L +#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL_MASK 0x000000FEL +//SHUB_OOB_CRUSH_DUMP_CTRL +#define SHUB_OOB_CRUSH_DUMP_CTRL__REGS_SHUB_OOB_TRIGGER__SHIFT 0x0 +#define SHUB_OOB_CRUSH_DUMP_CTRL__REGS_SHUB_OOB_TRIGGER_MASK 0x00000001L +//SHUB_MP_ERREVENT_MASK_CTRL +#define SHUB_MP_ERREVENT_MASK_CTRL__SHUB_MP_ERREVENT_MASK_EN__SHIFT 0x0 +#define SHUB_MP_ERREVENT_MASK_CTRL__MCA_FATAL_OUT_PROP_EN__SHIFT 0x1 +#define SHUB_MP_ERREVENT_MASK_CTRL__SHUB_MP_ERREVENT_MASK_EN_MASK 0x00000001L +#define SHUB_MP_ERREVENT_MASK_CTRL__MCA_FATAL_OUT_PROP_EN_MASK 0x00000002L +//SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT0_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x0 +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT1_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x1 +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT2_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x2 +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT3_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x3 +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT4_RAS_V1_GEN_ERREVENT_EN__SHIFT 0x4 +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT0_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000001L +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT1_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000002L +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT2_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000004L +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT3_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000008L +#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT4_RAS_V1_GEN_ERREVENT_EN_MASK 0x00000010L +//SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x0 +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x1 +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x2 +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x3 +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT 0x4 +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000001L +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000002L +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000004L +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000008L +#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN_MASK 0x00000010L + + +// addressBlock: nbif0_nbif0_gdc_sec_misc_GDCSEC_MISC_DEC +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI +//GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP +#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ__SHIFT 0xc +#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ_MASK 0x00000F00L +#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ_MASK 0x0000F000L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT 0xc +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT_MASK 0x00000F00L +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT_MASK 0x0000F000L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP +//GDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ_CNT__SHIFT 0x8 +#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ_CNT_MASK 0x00000F00L +//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI +//GDCSOC_SEC_RAS_POISON_DBUG_CTRL +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_PARITY_DBUG_CTRL +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_POISON_DATA_DROP_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_POISON_DATA_DROP_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_POISON_DATA_DROP_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_POISON_DATA_DROP_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_POISON_DATA_DROP_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_POISON_DATA_DROP_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_POISON_DATA_DROP_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_POISON_DATA_DROP_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_POISON_DATA_DROP_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_POISON_DATA_DROP_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_POISON_DATA_DROP_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_POISON_DATA_DROP_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_POISON_DATA_DROP_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_POISON_DATA_DROP_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_POISON_DATA_DROP_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_POISON_DATA_DROP_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_POISON_DATA_DROP_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_POISON_DATA_DROP_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_POISON_DATA_DROP_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_POISON_DATA_DROP_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_POISON_DATA_DROP_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_POISON_DATA_DROP_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_POISON_DATA_DROP_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_POISON_DATA_DROP_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_POISON_DATA_DROP_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_POISON_DATA_DROP_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_POISON_DATA_DROP_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_POISON_DATA_DROP_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_RESPONSE_DROP_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_RESPONSE_DROP_EN__SHIFT 0x1 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_RESPONSE_DROP_EN__SHIFT 0x2 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_RESPONSE_DROP_EN__SHIFT 0x3 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_RESPONSE_DROP_EN__SHIFT 0x4 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_RESPONSE_DROP_EN__SHIFT 0x5 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_RESPONSE_DROP_EN__SHIFT 0x6 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_RESPONSE_DROP_EN__SHIFT 0x7 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_RESPONSE_DROP_EN__SHIFT 0x8 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_RESPONSE_DROP_EN__SHIFT 0x9 +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_RESPONSE_DROP_EN__SHIFT 0xa +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_RESPONSE_DROP_EN__SHIFT 0xb +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_RESPONSE_DROP_EN__SHIFT 0xc +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_RESPONSE_DROP_EN__SHIFT 0xd +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_RESPONSE_DROP_EN_MASK 0x00000001L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_RESPONSE_DROP_EN_MASK 0x00000002L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_RESPONSE_DROP_EN_MASK 0x00000004L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_RESPONSE_DROP_EN_MASK 0x00000008L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_RESPONSE_DROP_EN_MASK 0x00000010L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_RESPONSE_DROP_EN_MASK 0x00000020L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_RESPONSE_DROP_EN_MASK 0x00000040L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_RESPONSE_DROP_EN_MASK 0x00000080L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_RESPONSE_DROP_EN_MASK 0x00000100L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_RESPONSE_DROP_EN_MASK 0x00000200L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_RESPONSE_DROP_EN_MASK 0x00000400L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_RESPONSE_DROP_EN_MASK 0x00000800L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_RESPONSE_DROP_EN_MASK 0x00001000L +#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_RESPONSE_DROP_EN_MASK 0x00002000L +//GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_EN_MASK 0x000000FFL +//GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL +#define GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_EN__SHIFT 0x0 +#define GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_EN_MASK 0x000000FFL + + +// addressBlock: nbif0_nbif0_gdc_a2s_GDCA2S_DEC +//A2S_CNTL_SW0 +#define A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW0__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_SW1 +#define A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW1__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_SW2 +#define A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW2__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_SW3 +#define A2S_CNTL_SW3__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW3__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW3__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW3__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW3__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW3__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW3__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW3__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW3__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW3__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW3__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW3__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW3__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW3__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW3__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW3__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_SW4 +#define A2S_CNTL_SW4__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW4__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW4__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW4__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW4__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW4__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW4__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW4__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW4__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW4__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW4__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW4__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW4__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW4__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW4__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW4__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_SW5 +#define A2S_CNTL_SW5__STATIC_VC_ENABLE__SHIFT 0x0 +#define A2S_CNTL_SW5__STATIC_VC_VALUE__SHIFT 0x1 +#define A2S_CNTL_SW5__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define A2S_CNTL_SW5__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define A2S_CNTL_SW5__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define A2S_CNTL_SW5__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define A2S_CNTL_SW5__WRR_RD_WEIGHT__SHIFT 0x10 +#define A2S_CNTL_SW5__WRR_WR_WEIGHT__SHIFT 0x18 +#define A2S_CNTL_SW5__STATIC_VC_ENABLE_MASK 0x00000001L +#define A2S_CNTL_SW5__STATIC_VC_VALUE_MASK 0x0000000EL +#define A2S_CNTL_SW5__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define A2S_CNTL_SW5__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define A2S_CNTL_SW5__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define A2S_CNTL_SW5__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define A2S_CNTL_SW5__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define A2S_CNTL_SW5__WRR_WR_WEIGHT_MASK 0xFF000000L +//A2S_CNTL_2_SW0 +#define A2S_CNTL_2_SW0__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW0__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_CNTL_2_SW1 +#define A2S_CNTL_2_SW1__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW1__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_CNTL_2_SW2 +#define A2S_CNTL_2_SW2__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW2__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_CNTL_2_SW3 +#define A2S_CNTL_2_SW3__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW3__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_CNTL_2_SW4 +#define A2S_CNTL_2_SW4__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW4__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_CNTL_2_SW5 +#define A2S_CNTL_2_SW5__SDP_LARGE_WR_CHAIN_DIS__SHIFT 0x0 +#define A2S_CNTL_2_SW5__SDP_LARGE_WR_CHAIN_DIS_MASK 0x00000001L +//A2S_WRSIZEFULL_SUPPORT_DISABLE +#define A2S_WRSIZEFULL_SUPPORT_DISABLE__SHUB_A2S_WRSIZEFULL_SUPPORT_DISABLE__SHIFT 0x0 +#define A2S_WRSIZEFULL_SUPPORT_DISABLE__SHUB_A2S_WRSIZEFULL_SUPPORT_DISABLE_MASK 0x00000001L +//ROUTING_TABLE_CNTL +#define ROUTING_TABLE_CNTL__TABLE_INDEX__SHIFT 0x0 +#define ROUTING_TABLE_CNTL__TABLE_INDEX_MASK 0x0000FFFFL +//ROUTING_TABLE_DATA0 +#define ROUTING_TABLE_DATA0__TABLE_DATA0__SHIFT 0x0 +#define ROUTING_TABLE_DATA0__TABLE_DATA0_MASK 0xFFFFFFFFL +//A2S_ARB_CONTROL_FOR_VC0 +#define A2S_ARB_CONTROL_FOR_VC0__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC0__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC0__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC0__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC0__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC0__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC1 +#define A2S_ARB_CONTROL_FOR_VC1__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC1__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC1__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC1__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC1__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC1__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC2 +#define A2S_ARB_CONTROL_FOR_VC2__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC2__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC2__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC2__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC2__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC2__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC3 +#define A2S_ARB_CONTROL_FOR_VC3__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC3__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC3__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC3__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC3__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC3__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC4 +#define A2S_ARB_CONTROL_FOR_VC4__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC4__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC4__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC4__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC4__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC4__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC5 +#define A2S_ARB_CONTROL_FOR_VC5__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC5__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC5__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC5__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC5__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC5__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC6 +#define A2S_ARB_CONTROL_FOR_VC6__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC6__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC6__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC6__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC6__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC6__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_ARB_CONTROL_FOR_VC7 +#define A2S_ARB_CONTROL_FOR_VC7__VC_RD_WEIGHT__SHIFT 0x0 +#define A2S_ARB_CONTROL_FOR_VC7__VC_WR_WEIGHT__SHIFT 0x8 +#define A2S_ARB_CONTROL_FOR_VC7__VC_RW_WEIGHT__SHIFT 0x10 +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_MODE_RW__SHIFT 0x18 +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_SIZE_MODE_RW__SHIFT 0x19 +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_COUNTER_MODE_RW__SHIFT 0x1a +#define A2S_ARB_CONTROL_FOR_VC7__VC_RD_WEIGHT_MASK 0x000000FFL +#define A2S_ARB_CONTROL_FOR_VC7__VC_WR_WEIGHT_MASK 0x0000FF00L +#define A2S_ARB_CONTROL_FOR_VC7__VC_RW_WEIGHT_MASK 0x00FF0000L +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_MODE_RW_MASK 0x01000000L +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_SIZE_MODE_RW_MASK 0x02000000L +#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_COUNTER_MODE_RW_MASK 0x04000000L +//A2S_RW_ARB_CNTL +#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_RD__SHIFT 0x0 +#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_WR__SHIFT 0x8 +#define A2S_RW_ARB_CNTL__A2S_LRG_MODE_RW__SHIFT 0x10 +#define A2S_RW_ARB_CNTL__A2S_LRG_SIZE_MODE_RW__SHIFT 0x11 +#define A2S_RW_ARB_CNTL__A2S_LRG_COUNTER_MODE_RW__SHIFT 0x12 +#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_RD_MASK 0x000000FFL +#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_WR_MASK 0x0000FF00L +#define A2S_RW_ARB_CNTL__A2S_LRG_MODE_RW_MASK 0x00010000L +#define A2S_RW_ARB_CNTL__A2S_LRG_SIZE_MODE_RW_MASK 0x00020000L +#define A2S_RW_ARB_CNTL__A2S_LRG_COUNTER_MODE_RW_MASK 0x00040000L +//A2S_REQ_RSP_TAG_CNTL +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_MODE__SHIFT 0x0 +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_SIZE_MODE__SHIFT 0x1 +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_COUNTER_MODE__SHIFT 0x2 +#define A2S_REQ_RSP_TAG_CNTL__RD_A2S_RSP_ARBMODE__SHIFT 0x3 +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_MODE__SHIFT 0x10 +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_SIZE_MODE__SHIFT 0x11 +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_COUNTER_MODE__SHIFT 0x12 +#define A2S_REQ_RSP_TAG_CNTL__WR_A2S_RSP_ARBMODE__SHIFT 0x13 +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_MODE_MASK 0x00000001L +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_SIZE_MODE_MASK 0x00000002L +#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_COUNTER_MODE_MASK 0x00000004L +#define A2S_REQ_RSP_TAG_CNTL__RD_A2S_RSP_ARBMODE_MASK 0x00000008L +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_MODE_MASK 0x00010000L +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_SIZE_MODE_MASK 0x00020000L +#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_COUNTER_MODE_MASK 0x00040000L +#define A2S_REQ_RSP_TAG_CNTL__WR_A2S_RSP_ARBMODE_MASK 0x00080000L +//A2S_MISC_CNTL +#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 +#define A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6 +#define A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L +#define A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L +//A2S_TAG_ALLOC_0 +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0 +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8 +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10 +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L +#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L +//A2S_TAG_ALLOC_1 +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0 +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10 +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18 +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L +#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L +//A2S_TAG_ALLOC_2 +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_WR__SHIFT 0x0 +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_RD__SHIFT 0x8 +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_WR__SHIFT 0x10 +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_RD__SHIFT 0x18 +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_WR_MASK 0x000000FFL +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_RD_MASK 0x0000FF00L +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_WR_MASK 0x00FF0000L +#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_RD_MASK 0xFF000000L +//A2S_TAG_ALLOC_3 +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_WR__SHIFT 0x0 +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_RD__SHIFT 0x8 +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_WR__SHIFT 0x10 +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_RD__SHIFT 0x18 +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_WR_MASK 0x000000FFL +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_RD_MASK 0x0000FF00L +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_WR_MASK 0x00FF0000L +#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_RD_MASK 0xFF000000L +//SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC0_CHAIN__SHIFT 0x0 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC1_CHAIN__SHIFT 0x8 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC2_CHAIN__SHIFT 0x10 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC3_CHAIN__SHIFT 0x18 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC0_CHAIN_MASK 0x000000FFL +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC1_CHAIN_MASK 0x0000FF00L +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC2_CHAIN_MASK 0x00FF0000L +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC3_CHAIN_MASK 0xFF000000L +//SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC4_CHAIN__SHIFT 0x0 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC5_CHAIN__SHIFT 0x8 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC6_CHAIN__SHIFT 0x10 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC7_CHAIN__SHIFT 0x18 +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC4_CHAIN_MASK 0x000000FFL +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC5_CHAIN_MASK 0x0000FF00L +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC6_CHAIN_MASK 0x00FF0000L +#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC7_CHAIN_MASK 0xFF000000L +//GDC_SDP_PORT_CTRL +#define GDC_SDP_PORT_CTRL__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x0 +#define GDC_SDP_PORT_CTRL__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00000001L +//GDC_A2S_SDP_REQ_POOLCRED_ALLOC +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//GDC_A2S_SDP_DAT_POOLCRED_ALLOC +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//SHUB_PERF_COMMON_COUNTER +#define SHUB_PERF_COMMON_COUNTER__SHUB_COM_COUNT_ENBALE__SHIFT 0x0 +#define SHUB_PERF_COMMON_COUNTER__SHUB_COM_COUNT_ENBALE_MASK 0x00000001L +//SHUB_A2S_PERF_CNT_FSM +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_SHADOW_TGL_DELAY_COUNT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT 0x4 +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT 0x8 +#define SHUB_A2S_PERF_CNT_FSM__A2S_PRE_FLD_GLOBAL_SHADOW_WR__SHIFT 0x9 +#define SHUB_A2S_PERF_CNT_FSM__A2S_PERF_CNT_DONE__SHIFT 0xa +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_SHADOW_TGL_DELAY_COUNT_MASK 0x0000000FL +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK 0x000000F0L +#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK 0x00000100L +#define SHUB_A2S_PERF_CNT_FSM__A2S_PRE_FLD_GLOBAL_SHADOW_WR_MASK 0x00000200L +#define SHUB_A2S_PERF_CNT_FSM__A2S_PERF_CNT_DONE_MASK 0x00000400L +//SHUB_A2S_PERF_CNT_RSP_UNITID +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID_EN__SHIFT 0xf +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID__SHIFT 0x10 +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID_EN__SHIFT 0x1f +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID_MASK 0x000007FFL +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID_EN_MASK 0x00008000L +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID_MASK 0x07FF0000L +#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID_EN_MASK 0x80000000L +//SHUB_A2S_PERF_CNT_0_CTRL +#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_SEL__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_EN__SHIFT 0x1f +#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_SEL_MASK 0x7FFFFFFFL +#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_EN_MASK 0x80000000L +//SHUB_A2S_PERF_CNT_1_CTRL +#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_SEL__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_EN__SHIFT 0x1f +#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_SEL_MASK 0x7FFFFFFFL +#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_EN_MASK 0x80000000L +//SHUB_A2S_PERF_CNT_2_CTRL +#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_SEL__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_EN__SHIFT 0x1f +#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_SEL_MASK 0x7FFFFFFFL +#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_EN_MASK 0x80000000L +//SHUB_A2S_PERF_CNT_3_CTRL +#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_SEL__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_EN__SHIFT 0x1f +#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_SEL_MASK 0x7FFFFFFFL +#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_EN_MASK 0x80000000L +//SHUB_A2S_PERF_CNT_0_VALUE_L32BIT +#define SHUB_A2S_PERF_CNT_0_VALUE_L32BIT__A2S_PERF_CNT_0_VALUE_L32BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_0_VALUE_L32BIT__A2S_PERF_CNT_0_VALUE_L32BIT_MASK 0xFFFFFFFFL +//SHUB_A2S_PERF_CNT_0_VALUE_H16BIT +#define SHUB_A2S_PERF_CNT_0_VALUE_H16BIT__A2S_PERF_CNT_0_VALUE_H16BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_0_VALUE_H16BIT__A2S_PERF_CNT_0_VALUE_H16BIT_MASK 0xFFFFL +//SHUB_A2S_PERF_CNT_1_VALUE_L32BIT +#define SHUB_A2S_PERF_CNT_1_VALUE_L32BIT__A2S_PERF_CNT_1_VALUE_L32BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_1_VALUE_L32BIT__A2S_PERF_CNT_1_VALUE_L32BIT_MASK 0xFFFFFFFFL +//SHUB_A2S_PERF_CNT_1_VALUE_H16BIT +#define SHUB_A2S_PERF_CNT_1_VALUE_H16BIT__A2S_PERF_CNT_1_VALUE_H16BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_1_VALUE_H16BIT__A2S_PERF_CNT_1_VALUE_H16BIT_MASK 0xFFFFL +//SHUB_A2S_PERF_CNT_2_VALUE_L32BIT +#define SHUB_A2S_PERF_CNT_2_VALUE_L32BIT__A2S_PERF_CNT_2_VALUE_L32BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_2_VALUE_L32BIT__A2S_PERF_CNT_2_VALUE_L32BIT_MASK 0xFFFFFFFFL +//SHUB_A2S_PERF_CNT_2_VALUE_H16BIT +#define SHUB_A2S_PERF_CNT_2_VALUE_H16BIT__A2S_PERF_CNT_2_VALUE_H16BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_2_VALUE_H16BIT__A2S_PERF_CNT_2_VALUE_H16BIT_MASK 0xFFFFL +//SHUB_A2S_PERF_CNT_3_VALUE_L32BIT +#define SHUB_A2S_PERF_CNT_3_VALUE_L32BIT__A2S_PERF_CNT_3_VALUE_L32BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_3_VALUE_L32BIT__A2S_PERF_CNT_3_VALUE_L32BIT_MASK 0xFFFFFFFFL +//SHUB_A2S_PERF_CNT_3_VALUE_H16BIT +#define SHUB_A2S_PERF_CNT_3_VALUE_H16BIT__A2S_PERF_CNT_3_VALUE_H16BIT__SHIFT 0x0 +#define SHUB_A2S_PERF_CNT_3_VALUE_H16BIT__A2S_PERF_CNT_3_VALUE_H16BIT_MASK 0xFFFFL +//SHUB_TO_ALL_PERF_COUNTER +#define SHUB_TO_ALL_PERF_COUNTER__START_COUNT_NOPULS__SHIFT 0x0 +#define SHUB_TO_ALL_PERF_COUNTER__LEGACY_OUT_REALTIME_SEL__SHIFT 0x1 +#define SHUB_TO_ALL_PERF_COUNTER__PERF_CNT_TRIG_MONI_SEL__SHIFT 0x2 +#define SHUB_TO_ALL_PERF_COUNTER__START_COUNT_NOPULS_MASK 0x00000001L +#define SHUB_TO_ALL_PERF_COUNTER__LEGACY_OUT_REALTIME_SEL_MASK 0x00000002L +#define SHUB_TO_ALL_PERF_COUNTER__PERF_CNT_TRIG_MONI_SEL_MASK 0x0000000CL +//GDC_PERF_COUNTER_RESET +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT0_RESET__SHIFT 0x0 +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT1_RESET__SHIFT 0x1 +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT2_RESET__SHIFT 0x2 +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT3_RESET__SHIFT 0x3 +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT0_RESET_MASK 0x00000001L +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT1_RESET_MASK 0x00000002L +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT2_RESET_MASK 0x00000004L +#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT3_RESET_MASK 0x00000008L +//SHUB_COM_COUNT_VALUE +#define SHUB_COM_COUNT_VALUE__SHUB_COM_COUNT_VALUE__SHIFT 0x0 +#define SHUB_COM_COUNT_VALUE__SHUB_COM_COUNT_VALUE_MASK 0xFFFFFFFFL +//A2S_QUEUE_FIFO_ARB_CNTL +#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0x0 +#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT 0xa +#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x14 +#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT 0x15 +#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000003FFL +#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK 0x000FFC00L +#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00100000L +#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK 0x00200000L +//WR_A2S_RSP_WRR_CNTL +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE0__SHIFT 0x0 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE1__SHIFT 0x4 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE2__SHIFT 0x8 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE3__SHIFT 0xc +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE4__SHIFT 0x10 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE5__SHIFT 0x14 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE6__SHIFT 0x18 +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE7__SHIFT 0x1c +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE0_MASK 0x0000000FL +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE1_MASK 0x000000F0L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE2_MASK 0x00000F00L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE3_MASK 0x0000F000L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE4_MASK 0x000F0000L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE5_MASK 0x00F00000L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE6_MASK 0x0F000000L +#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE7_MASK 0xF0000000L +//RD_A2S_RSP_WRR_CNTL +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE0__SHIFT 0x0 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE1__SHIFT 0x4 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE2__SHIFT 0x8 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE3__SHIFT 0xc +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE4__SHIFT 0x10 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE5__SHIFT 0x14 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE6__SHIFT 0x18 +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE7__SHIFT 0x1c +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE0_MASK 0x0000000FL +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE1_MASK 0x000000F0L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE2_MASK 0x00000F00L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE3_MASK 0x0000F000L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE4_MASK 0x000F0000L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE5_MASK 0x00F00000L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE6_MASK 0x0F000000L +#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE7_MASK 0xF0000000L + + +// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdirect +//SYSHUB_DS_CTRL_SOCCLK +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c +#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L +#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L +#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L +//SYSHUB_DS_CTRL2_SOCCLK +#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 +#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL +//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0x10 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x11 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x12 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_bypass_en__SHIFT 0x13 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_bypass_en__SHIFT 0x14 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_bypass_en__SHIFT 0x15 +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_DYNAMIC_BYPASS_EN_socclk__SHIFT 0x1f +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00010000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK 0x00020000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK 0x00040000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_bypass_en_MASK 0x00080000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_bypass_en_MASK 0x00100000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_bypass_en_MASK 0x00200000L +#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_DYNAMIC_BYPASS_EN_socclk_MASK 0x80000000L +//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0x10 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x11 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x12 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_imm_en__SHIFT 0x13 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_imm_en__SHIFT 0x14 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_imm_en__SHIFT 0x15 +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00010000L +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK 0x00020000L +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK 0x00040000L +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_imm_en_MASK 0x00080000L +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_imm_en_MASK 0x00100000L +#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_imm_en_MASK 0x00200000L +//SYSHUB_MGCG_CTRL_SOCCLK +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0 +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1 +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2 +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REG_DIS_SOCCLK__SHIFT 0xc +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DBG_DIS_SOCCLK__SHIFT 0xe +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REG_DIS_SOCCLK_MASK 0x00001000L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L +#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DBG_DIS_SOCCLK_MASK 0x00004000L +//SYSHUB_SCRATCH_SOCCLK +#define SYSHUB_SCRATCH_SOCCLK__SCRATCH_SOCCLK__SHIFT 0x0 +#define SYSHUB_SCRATCH_SOCCLK__SCRATCH_SOCCLK_MASK 0xFFFFFFFFL +//SYSHUB_HANG_CNTL_SOCCLK +//SYSHUB_SELECT_SOCCLK +#define SYSHUB_SELECT_SOCCLK__SELECT_USB0__SHIFT 0x0 +#define SYSHUB_SELECT_SOCCLK__SELECT_USB0_MASK 0x00000001L +//SYSHUB_DS_AW_READY_SOCCLK +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL0_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL1_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL2_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL3_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL4_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL5_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL6_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL7_SOCCLK_AW_READY_DIS_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL0_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL1_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL2_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL3_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL4_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL5_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL6_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL7_SOCCLK_AW_READY_DIS_ENABLE_MASK 0x00000080L +//SYSHUB_DS_AR_READY_SOCCLK +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL0_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL1_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL2_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL3_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL4_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL5_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL6_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL7_SOCCLK_AR_READY_DIS_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL0_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL1_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL2_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL3_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL4_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL5_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL6_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL7_SOCCLK_AR_READY_DIS_ENABLE_MASK 0x00000080L +//SYSHUB_DS_W_READY_SOCCLK +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL0_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL1_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL2_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL3_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL4_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL5_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL6_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL7_SOCCLK_W_READY_DIS_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL0_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL1_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL2_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL3_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL4_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL5_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL6_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL7_SOCCLK_W_READY_DIS_ENABLE_MASK 0x00000080L +//SYSHUB_DS_R_READY_SOCCLK +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL0_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL1_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL2_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL3_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL4_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL5_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL6_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL7_SOCCLK_R_READY_DIS_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL0_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL1_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL2_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL3_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL4_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL5_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL6_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL7_SOCCLK_R_READY_DIS_ENABLE_MASK 0x00000080L +//SYSHUB_DS_B_READY_SOCCLK +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL0_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x0 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL1_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x1 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL2_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x2 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL3_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x3 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL4_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x4 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL5_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x5 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL6_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x6 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL7_SOCCLK_B_READY_DIS_ENABLE__SHIFT 0x7 +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL0_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000001L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL1_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000002L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL2_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000004L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL3_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000008L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL4_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000010L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL5_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000020L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL6_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000040L +#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL7_SOCCLK_B_READY_DIS_ENABLE_MASK 0x00000080L +//SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK +#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__HST_SOCCLK_AXI_DEBUG_COUNTER_EN__SHIFT 0x0 +#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__DMA_SOCCLK_AXI_DEBUG_COUNTER_EN__SHIFT 0x1 +#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__HST_SOCCLK_AXI_DEBUG_COUNTER_EN_MASK 0x00000001L +#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__DMA_SOCCLK_AXI_DEBUG_COUNTER_EN_MASK 0x00000002L +//DMA_CLK0_SW0_SYSHUB_QOS_CNTL +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//DMA_CLK0_SW1_SYSHUB_QOS_CNTL +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL +#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L +//DMA_CLK0_SW0_CL0_CNTL +#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW0_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW0_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//DMA_CLK0_SW0_CL1_CNTL +#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW0_CL1_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW0_CL1_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//DMA_CLK0_SW1_CL0_CNTL +#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW1_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW1_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//DMA_CLK0_SW1_CL1_CNTL +#define DMA_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW1_CL1_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW1_CL1_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//DMA_CLK0_SW2_CL0_CNTL +#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW2_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW2_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +//DMA_CLK0_SW3_CL0_CNTL +#define DMA_CLK0_SW3_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW3_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW3_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW3_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW3_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW3_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +//DMA_CLK0_SW4_CL0_CNTL +#define DMA_CLK0_SW4_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW4_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW4_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW4_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW4_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW4_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +//DMA_CLK0_SW5_CL0_CNTL +#define DMA_CLK0_SW5_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW5_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW5_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT 0x2 +#define DMA_CLK0_SW5_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW5_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW5_CL0_CNTL__DEBUG_RS_RESET_EN_MASK 0x00000004L +//NIC400_0_AMIB_0_FN_MOD_BM_ISS +#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 +#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 +#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L +#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L +//NIC400_0_AMIB_0_FN_MOD +#define NIC400_0_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_0_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_0_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_0_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_0_ASIB_0_FN_MOD +#define NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_0_ASIB_0_QOS_CNTL +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_0_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_0_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_0_ASIB_0_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_0_ASIB_0_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_0_ASIB_0_MAX_OT +#define NIC400_0_ASIB_0_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_0_ASIB_0_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_0_ASIB_0_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_0_ASIB_0_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_0_ASIB_0_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_0_ASIB_0_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_0_ASIB_0_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_0_ASIB_0_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_0_ASIB_0_MAX_COMB_OT +#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_0_ASIB_0_AW_P +#define NIC400_0_ASIB_0_AW_P__aw_p__SHIFT 0x18 +#define NIC400_0_ASIB_0_AW_P__aw_p_MASK 0xFF000000L +//NIC400_0_ASIB_0_AW_B +#define NIC400_0_ASIB_0_AW_B__aw_b__SHIFT 0x0 +#define NIC400_0_ASIB_0_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_0_ASIB_0_AW_R +#define NIC400_0_ASIB_0_AW_R__aw_r__SHIFT 0x14 +#define NIC400_0_ASIB_0_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_0_ASIB_0_AR_P +#define NIC400_0_ASIB_0_AR_P__ar_p__SHIFT 0x18 +#define NIC400_0_ASIB_0_AR_P__ar_p_MASK 0xFF000000L +//NIC400_0_ASIB_0_AR_B +#define NIC400_0_ASIB_0_AR_B__ar_b__SHIFT 0x0 +#define NIC400_0_ASIB_0_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_0_ASIB_0_AR_R +#define NIC400_0_ASIB_0_AR_R__ar_r__SHIFT 0x14 +#define NIC400_0_ASIB_0_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_0_ASIB_0_TARGET_FC +#define NIC400_0_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_0_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_0_ASIB_0_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_0_ASIB_0_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_0_ASIB_0_KI_FC +#define NIC400_0_ASIB_0_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_0_ASIB_0_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_0_ASIB_0_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_0_ASIB_0_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_0_ASIB_0_QOS_RANGE +#define NIC400_0_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_0_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_0_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_0_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_0_ASIB_0_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_0_ASIB_0_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_0_ASIB_0_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_0_ASIB_0_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_0_ASIB_1_FN_MOD +#define NIC400_0_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_0_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_0_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_0_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_0_ASIB_1_QOS_CNTL +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_0_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_0_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_0_ASIB_1_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_0_ASIB_1_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_0_ASIB_1_MAX_OT +#define NIC400_0_ASIB_1_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_0_ASIB_1_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_0_ASIB_1_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_0_ASIB_1_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_0_ASIB_1_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_0_ASIB_1_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_0_ASIB_1_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_0_ASIB_1_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_0_ASIB_1_MAX_COMB_OT +#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_0_ASIB_1_AW_P +#define NIC400_0_ASIB_1_AW_P__aw_p__SHIFT 0x18 +#define NIC400_0_ASIB_1_AW_P__aw_p_MASK 0xFF000000L +//NIC400_0_ASIB_1_AW_B +#define NIC400_0_ASIB_1_AW_B__aw_b__SHIFT 0x0 +#define NIC400_0_ASIB_1_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_0_ASIB_1_AW_R +#define NIC400_0_ASIB_1_AW_R__aw_r__SHIFT 0x14 +#define NIC400_0_ASIB_1_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_0_ASIB_1_AR_P +#define NIC400_0_ASIB_1_AR_P__ar_p__SHIFT 0x18 +#define NIC400_0_ASIB_1_AR_P__ar_p_MASK 0xFF000000L +//NIC400_0_ASIB_1_AR_B +#define NIC400_0_ASIB_1_AR_B__ar_b__SHIFT 0x0 +#define NIC400_0_ASIB_1_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_0_ASIB_1_AR_R +#define NIC400_0_ASIB_1_AR_R__ar_r__SHIFT 0x14 +#define NIC400_0_ASIB_1_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_0_ASIB_1_TARGET_FC +#define NIC400_0_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_0_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_0_ASIB_1_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_0_ASIB_1_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_0_ASIB_1_KI_FC +#define NIC400_0_ASIB_1_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_0_ASIB_1_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_0_ASIB_1_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_0_ASIB_1_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_0_ASIB_1_QOS_RANGE +#define NIC400_0_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_0_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_0_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_0_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_0_ASIB_1_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_0_ASIB_1_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_0_ASIB_1_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_0_ASIB_1_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_0_IB_0_FN_MOD +#define NIC400_0_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_0_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_0_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_0_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_1_AMIB_0_FN_MOD_BM_ISS +#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 +#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 +#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L +#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L +//NIC400_1_AMIB_0_FN_MOD +#define NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_1_ASIB_0_FN_MOD +#define NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_1_ASIB_0_QOS_CNTL +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_1_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_1_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_1_ASIB_0_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_1_ASIB_0_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_1_ASIB_0_MAX_OT +#define NIC400_1_ASIB_0_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_1_ASIB_0_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_1_ASIB_0_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_1_ASIB_0_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_1_ASIB_0_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_1_ASIB_0_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_1_ASIB_0_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_1_ASIB_0_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_1_ASIB_0_MAX_COMB_OT +#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_1_ASIB_0_AW_P +#define NIC400_1_ASIB_0_AW_P__aw_p__SHIFT 0x18 +#define NIC400_1_ASIB_0_AW_P__aw_p_MASK 0xFF000000L +//NIC400_1_ASIB_0_AW_B +#define NIC400_1_ASIB_0_AW_B__aw_b__SHIFT 0x0 +#define NIC400_1_ASIB_0_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_1_ASIB_0_AW_R +#define NIC400_1_ASIB_0_AW_R__aw_r__SHIFT 0x14 +#define NIC400_1_ASIB_0_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_1_ASIB_0_AR_P +#define NIC400_1_ASIB_0_AR_P__ar_p__SHIFT 0x18 +#define NIC400_1_ASIB_0_AR_P__ar_p_MASK 0xFF000000L +//NIC400_1_ASIB_0_AR_B +#define NIC400_1_ASIB_0_AR_B__ar_b__SHIFT 0x0 +#define NIC400_1_ASIB_0_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_1_ASIB_0_AR_R +#define NIC400_1_ASIB_0_AR_R__ar_r__SHIFT 0x14 +#define NIC400_1_ASIB_0_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_1_ASIB_0_TARGET_FC +#define NIC400_1_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_1_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_1_ASIB_0_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_1_ASIB_0_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_1_ASIB_0_KI_FC +#define NIC400_1_ASIB_0_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_1_ASIB_0_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_1_ASIB_0_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_1_ASIB_0_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_1_ASIB_0_QOS_RANGE +#define NIC400_1_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_1_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_1_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_1_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_1_ASIB_0_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_1_ASIB_0_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_1_ASIB_0_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_1_ASIB_0_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_1_ASIB_1_FN_MOD +#define NIC400_1_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_1_ASIB_1_QOS_CNTL +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_1_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_1_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_1_ASIB_1_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_1_ASIB_1_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_1_ASIB_1_MAX_OT +#define NIC400_1_ASIB_1_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_1_ASIB_1_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_1_ASIB_1_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_1_ASIB_1_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_1_ASIB_1_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_1_ASIB_1_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_1_ASIB_1_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_1_ASIB_1_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_1_ASIB_1_MAX_COMB_OT +#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_1_ASIB_1_AW_P +#define NIC400_1_ASIB_1_AW_P__aw_p__SHIFT 0x18 +#define NIC400_1_ASIB_1_AW_P__aw_p_MASK 0xFF000000L +//NIC400_1_ASIB_1_AW_B +#define NIC400_1_ASIB_1_AW_B__aw_b__SHIFT 0x0 +#define NIC400_1_ASIB_1_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_1_ASIB_1_AW_R +#define NIC400_1_ASIB_1_AW_R__aw_r__SHIFT 0x14 +#define NIC400_1_ASIB_1_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_1_ASIB_1_AR_P +#define NIC400_1_ASIB_1_AR_P__ar_p__SHIFT 0x18 +#define NIC400_1_ASIB_1_AR_P__ar_p_MASK 0xFF000000L +//NIC400_1_ASIB_1_AR_B +#define NIC400_1_ASIB_1_AR_B__ar_b__SHIFT 0x0 +#define NIC400_1_ASIB_1_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_1_ASIB_1_AR_R +#define NIC400_1_ASIB_1_AR_R__ar_r__SHIFT 0x14 +#define NIC400_1_ASIB_1_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_1_ASIB_1_TARGET_FC +#define NIC400_1_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_1_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_1_ASIB_1_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_1_ASIB_1_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_1_ASIB_1_KI_FC +#define NIC400_1_ASIB_1_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_1_ASIB_1_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_1_ASIB_1_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_1_ASIB_1_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_1_ASIB_1_QOS_RANGE +#define NIC400_1_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_1_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_1_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_1_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_1_ASIB_1_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_1_ASIB_1_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_1_ASIB_1_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_1_ASIB_1_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_1_IB_0_FN_MOD +#define NIC400_1_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L + + +// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdec +//SYSHUB_INDEX +#define SYSHUB_INDEX__INDEX__SHIFT 0x0 +#define SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL +//SYSHUB_DATA +#define SYSHUB_DATA__DATA__SHIFT 0x0 +#define SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC_VENDOR_ID +#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_DEVICE_ID +#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_COMMAND +#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC_STATUS +#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC_REVISION_ID +#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC_PROG_INTERFACE +#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC_SUB_CLASS +#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC_BASE_CLASS +#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC_CACHE_LINE +#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC_LATENCY +#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC_HEADER +#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC_BIST +#define BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_BASE_ADDR_2 +#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//SUB_BUS_NUMBER_LATENCY +#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//IO_BASE_LIMIT +#define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//SECONDARY_STATUS +#define SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//MEM_BASE_LIMIT +#define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//PREF_BASE_LIMIT +#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//PREF_BASE_UPPER +#define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//PREF_LIMIT_UPPER +#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//IO_BASE_LIMIT_HI +#define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_CAP_PTR +#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_RC_ROM_BASE_ADDR +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_RC_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//IRQ_BRIDGE_CNTL +#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 +#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb +#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L +#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L +//EXT_BRIDGE_CNTL +#define EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PMI_CAP +#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PCIE_CAP +#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +#define BIF_CFG_DEV0_RC_PCIE_CAP__FLIT_MODE_SUPPORT_MASK 0x8000L +//BIF_CFG_DEV0_RC_DEVICE_CAP +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__RX_MPS_FIXED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT 0x1d +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__RX_MPS_FIXED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK 0x20000000L +//BIF_CFG_DEV0_RC_DEVICE_CNTL +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC_DEVICE_STATUS +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_RC_LINK_CAP +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_LINK_CNTL +#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_RC_LINK_STATUS +#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//SLOT_CAP +#define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//SLOT_CNTL +#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//SLOT_STATUS +#define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//ROOT_CNTL +#define ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//ROOT_CAP +#define ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//ROOT_STATUS +#define ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_LINK_CAP2 +#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC_LINK_CNTL2 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC_LINK_STATUS2 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__FLIT_MODE_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//SLOT_CAP2 +#define SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//SLOT_CNTL2 +#define SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//SLOT_STATUS2 +#define SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//SSID_CAP_LIST +#define SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//SSID_CAP +#define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_LINK_CAP_16GT +#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_LINK_CNTL_16GT +#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_LINK_STATUS_16GT +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_LINK_CAP_32GT +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_RC_LINK_CNTL_32GT +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_RC_LINK_STATUS_32GT +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK 0x0000FFF8L +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK 0x00FFFFFFL +#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK 0x03000000L +//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_AP_CAP +#define BIF_CFG_DEV0_RC_AP_CAP__COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_AP_CAP__SEL_EN_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_AP_CAP__COUNT_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_AP_CAP__SEL_EN_SUPPORTED_MASK 0x00000100L +//BIF_CFG_DEV0_RC_AP_CNTL +#define BIF_CFG_DEV0_RC_AP_CNTL__INX_SEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_AP_CNTL__NEGO_GLOBAL_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_AP_CNTL__INX_SEL_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_AP_CNTL__NEGO_GLOBAL_EN_MASK 0x00000100L +//BIF_CFG_DEV0_RC_AP_DATA1 +#define BIF_CFG_DEV0_RC_AP_DATA1__USAGE_INFOR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_AP_DATA1__DETAILS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_AP_DATA1__VENDORID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_AP_DATA1__USAGE_INFOR_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_AP_DATA1__DETAILS_MASK 0x0000FFE0L +#define BIF_CFG_DEV0_RC_AP_DATA1__VENDORID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_AP_DATA2 +#define BIF_CFG_DEV0_RC_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_AP_DATA2__MODIFIED_TS_INFOR2_MASK 0x00FFFFFFL +//BIF_CFG_DEV0_RC_AP_SEL_EN_MASK +#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__PCIE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__OTHERS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__PCIE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__OTHERS_MASK 0xFFFFFFFEL +//BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK 0x40000000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT 0x1b +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT 0x1c +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT 0x1d +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT 0x1e +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK 0x08000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK 0x10000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK 0x20000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK 0x40000000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1b +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT 0x1c +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT 0x1d +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT 0x1e +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK 0x08000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK 0x10000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK 0x20000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK 0x40000000L +//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK 0x0003E000L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK 0x00F80000L +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//PCIE_ROOT_ERR_CMD +#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//PCIE_ROOT_ERR_STATUS +#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT 0x7 +#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK 0x00000180L +#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//PCIE_ERR_SRC_ID +#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG4 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG4__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG4__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG5 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG5__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG5__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG6 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG6__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG6__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG7 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG7__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG7__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG8 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG8__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG8__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG9 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG9__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG9__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG10 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG10__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG10__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG11 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG11__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG11__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG12 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG12__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG12__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG13 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG13__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG13__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_RTR_DATA1 +#define BIF_CFG_DEV0_RC_RTR_DATA1__RESET_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTR_DATA1__DLUP_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC_RTR_DATA1__RTR_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_RTR_DATA1__RESET_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC_RTR_DATA1__DLUP_TIME_MASK 0x00FFF000L +#define BIF_CFG_DEV0_RC_RTR_DATA1__RTR_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC_RTR_DATA2 +#define BIF_CFG_DEV0_RC_RTR_DATA2__FLR_TIME__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTR_DATA2__D3HOTD0_TIME__SHIFT 0xc +#define BIF_CFG_DEV0_RC_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL +#define BIF_CFG_DEV0_RC_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +//BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_CAP +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK 0x00001F00L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK 0x0000E000L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK 0x02000000L +//BIF_CFG_DEV0_RC_IDE_CNTL +#define BIF_CFG_DEV0_RC_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK 0x00000004L +//BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK 0x0000000FL +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK 0x0000000CL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK 0x00000030L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK 0x00003C00L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK 0x0007C000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK 0x00380000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK 0x80000000L +//BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK 0x00FFFF00L +//BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK 0x00FFFF00L +#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK 0x000FFF00L +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_offset.h new file mode 100644 index 000000000000..d815f560dacc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_offset.h @@ -0,0 +1,1041 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _vpe_2_0_0_OFFSET_HEADER +#define _vpe_2_0_0_OFFSET_HEADER + + + +// addressBlock: vpe_vpec_vpecdec +// base address: 0x46000 +#define regVPEC_DEC_START 0x0000 +#define regVPEC_DEC_START_BASE_IDX 0 +#define regVPEC_UCODE_ADDR 0x0001 +#define regVPEC_UCODE_ADDR_BASE_IDX 0 +#define regVPEC_UCODE_DATA 0x0002 +#define regVPEC_UCODE_DATA_BASE_IDX 0 +#define regVPEC_F32_CNTL 0x0003 +#define regVPEC_F32_CNTL_BASE_IDX 0 +#define regVPEC_MMHUB_CNTL 0x0004 +#define regVPEC_MMHUB_CNTL_BASE_IDX 0 +#define regVPEC_MMHUB_TRUSTLVL 0x0005 +#define regVPEC_MMHUB_TRUSTLVL_BASE_IDX 0 +#define regVPEC_VPEP_CTRL 0x0010 +#define regVPEC_VPEP_CTRL_BASE_IDX 0 +#define regVPEC_CLK_CTRL 0x0011 +#define regVPEC_CLK_CTRL_BASE_IDX 0 +#define regVPEC_COLLABORATE_CNTL 0x0012 +#define regVPEC_COLLABORATE_CNTL_BASE_IDX 0 +#define regVPEC_COLLABORATE_CFG 0x0013 +#define regVPEC_COLLABORATE_CFG_BASE_IDX 0 +#define regVPEC_POWER_CNTL 0x0014 +#define regVPEC_POWER_CNTL_BASE_IDX 0 +#define regVPEC_ZPR_CNTL 0x0015 +#define regVPEC_ZPR_CNTL_BASE_IDX 0 +#define regVPEC_CNTL 0x0016 +#define regVPEC_CNTL_BASE_IDX 0 +#define regVPEC_CNTL_DCC 0x0017 +#define regVPEC_CNTL_DCC_BASE_IDX 0 +#define regVPEC_CE_OP_MULTI_64B_BURST 0x0018 +#define regVPEC_CE_OP_MULTI_64B_BURST_BASE_IDX 0 +#define regVPEC_CNTL1 0x0019 +#define regVPEC_CNTL1_BASE_IDX 0 +#define regVPEC_CNTL2 0x001a +#define regVPEC_CNTL2_BASE_IDX 0 +#define regVPEC_GB_ADDR_CONFIG 0x001b +#define regVPEC_GB_ADDR_CONFIG_BASE_IDX 0 +#define regVPEC_GB_ADDR_CONFIG_READ 0x001c +#define regVPEC_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regVPEC_GB_ADDR_CONFIG_META 0x001d +#define regVPEC_GB_ADDR_CONFIG_META_BASE_IDX 0 +#define regVPEC_PROCESS_QUANTUM0 0x001e +#define regVPEC_PROCESS_QUANTUM0_BASE_IDX 0 +#define regVPEC_PROCESS_QUANTUM1 0x001f +#define regVPEC_PROCESS_QUANTUM1_BASE_IDX 0 +#define regVPEC_CONTEXT_SWITCH_THRESHOLD 0x0020 +#define regVPEC_CONTEXT_SWITCH_THRESHOLD_BASE_IDX 0 +#define regVPEC_GLOBAL_QUANTUM 0x0021 +#define regVPEC_GLOBAL_QUANTUM_BASE_IDX 0 +#define regVPEC_WATCHDOG_CNTL 0x0025 +#define regVPEC_WATCHDOG_CNTL_BASE_IDX 0 +#define regVPEC_ATOMIC_CNTL 0x0026 +#define regVPEC_ATOMIC_CNTL_BASE_IDX 0 +#define regVPEC_UCODE_VERSION 0x0027 +#define regVPEC_UCODE_VERSION_BASE_IDX 0 +#define regVPEC_MEMREQ_BURST_CNTL 0x0028 +#define regVPEC_MEMREQ_BURST_CNTL_BASE_IDX 0 +#define regVPEC_TIMESTAMP_CNTL 0x0029 +#define regVPEC_TIMESTAMP_CNTL_BASE_IDX 0 +#define regVPEC_GLOBAL_TIMESTAMP_LO 0x002a +#define regVPEC_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regVPEC_GLOBAL_TIMESTAMP_HI 0x002b +#define regVPEC_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regVPEC_FREEZE 0x002c +#define regVPEC_FREEZE_BASE_IDX 0 +#define regVPEC_CE_CTRL 0x002d +#define regVPEC_CE_CTRL_BASE_IDX 0 +#define regVPEC_RELAX_ORDERING_LUT 0x002e +#define regVPEC_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regVPEC_CREDIT_CNTL 0x002f +#define regVPEC_CREDIT_CNTL_BASE_IDX 0 +#define regVPEC_SCRATCH_RAM_DATA 0x0030 +#define regVPEC_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regVPEC_SCRATCH_RAM_ADDR 0x0031 +#define regVPEC_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regVPEC_QUEUE_RESET_REQ 0x0032 +#define regVPEC_QUEUE_RESET_REQ_BASE_IDX 0 +#define regVPEC_MAILBOX0 0x0040 +#define regVPEC_MAILBOX0_BASE_IDX 0 +#define regVPEC_MAILBOX1 0x0041 +#define regVPEC_MAILBOX1_BASE_IDX 0 +#define regVPEC_MAILBOX2 0x0042 +#define regVPEC_MAILBOX2_BASE_IDX 0 +#define regVPEC_MAILBOX3 0x0043 +#define regVPEC_MAILBOX3_BASE_IDX 0 +#define regVPEC_MAILBOX4 0x0044 +#define regVPEC_MAILBOX4_BASE_IDX 0 +#define regVPEC_MAILBOX5 0x0045 +#define regVPEC_MAILBOX5_BASE_IDX 0 +#define regVPEC_MAILBOX6 0x0046 +#define regVPEC_MAILBOX6_BASE_IDX 0 +#define regVPEC_MAILBOX7 0x0047 +#define regVPEC_MAILBOX7_BASE_IDX 0 +#define regVPEC_MAILBOX8 0x0048 +#define regVPEC_MAILBOX8_BASE_IDX 0 +#define regVPEC_MAILBOX9 0x0049 +#define regVPEC_MAILBOX9_BASE_IDX 0 +#define regVPEC_MAILBOX10 0x004a +#define regVPEC_MAILBOX10_BASE_IDX 0 +#define regVPEC_MAILBOX11 0x004b +#define regVPEC_MAILBOX11_BASE_IDX 0 +#define regVPEC_MAILBOX12 0x004c +#define regVPEC_MAILBOX12_BASE_IDX 0 +#define regVPEC_MAILBOX13 0x004d +#define regVPEC_MAILBOX13_BASE_IDX 0 +#define regVPEC_MAILBOX14 0x004e +#define regVPEC_MAILBOX14_BASE_IDX 0 +#define regVPEC_MAILBOX15 0x004f +#define regVPEC_MAILBOX15_BASE_IDX 0 +#define regVPEC_PUB_DUMMY0 0x0050 +#define regVPEC_PUB_DUMMY0_BASE_IDX 0 +#define regVPEC_PUB_DUMMY1 0x0051 +#define regVPEC_PUB_DUMMY1_BASE_IDX 0 +#define regVPEC_PUB_DUMMY2 0x0052 +#define regVPEC_PUB_DUMMY2_BASE_IDX 0 +#define regVPEC_PUB_DUMMY3 0x0053 +#define regVPEC_PUB_DUMMY3_BASE_IDX 0 +#define regVPEC_PUB_DUMMY4 0x0054 +#define regVPEC_PUB_DUMMY4_BASE_IDX 0 +#define regVPEC_PUB_DUMMY5 0x0055 +#define regVPEC_PUB_DUMMY5_BASE_IDX 0 +#define regVPEC_PUB_DUMMY6 0x0056 +#define regVPEC_PUB_DUMMY6_BASE_IDX 0 +#define regVPEC_PUB_DUMMY7 0x0057 +#define regVPEC_PUB_DUMMY7_BASE_IDX 0 +#define regVPEC_PUB_DUMMY8 0x0058 +#define regVPEC_PUB_DUMMY8_BASE_IDX 0 +#define regVPEC_PUB_DUMMY9 0x0059 +#define regVPEC_PUB_DUMMY9_BASE_IDX 0 +#define regVPEC_PUB_DUMMY10 0x005a +#define regVPEC_PUB_DUMMY10_BASE_IDX 0 +#define regVPEC_PUB_DUMMY11 0x005b +#define regVPEC_PUB_DUMMY11_BASE_IDX 0 +#define regVPEC_UCODE1_CHECKSUM 0x005c +#define regVPEC_UCODE1_CHECKSUM_BASE_IDX 0 +#define regVPEC_VERSION 0x005d +#define regVPEC_VERSION_BASE_IDX 0 +#define regVPEC_UCODE_CHECKSUM 0x005e +#define regVPEC_UCODE_CHECKSUM_BASE_IDX 0 +#define regVPEC_RB_RPTR_FETCH 0x005f +#define regVPEC_RB_RPTR_FETCH_BASE_IDX 0 +#define regVPEC_RB_RPTR_FETCH_HI 0x0060 +#define regVPEC_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regVPEC_IB_OFFSET_FETCH 0x0061 +#define regVPEC_IB_OFFSET_FETCH_BASE_IDX 0 +#define regVPEC_CMDIB_OFFSET_FETCH 0x0062 +#define regVPEC_CMDIB_OFFSET_FETCH_BASE_IDX 0 +#define regVPEC_3DLUTIB_OFFSET_FETCH 0x0063 +#define regVPEC_3DLUTIB_OFFSET_FETCH_BASE_IDX 0 +#define regVPEC_ATOMIC_PREOP_LO 0x0064 +#define regVPEC_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regVPEC_ATOMIC_PREOP_HI 0x0065 +#define regVPEC_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regVPEC_CE_BUSY 0x0066 +#define regVPEC_CE_BUSY_BASE_IDX 0 +#define regVPEC_F32_COUNTER 0x0067 +#define regVPEC_F32_COUNTER_BASE_IDX 0 +#define regVPEC_HOLE_ADDR_LO 0x0068 +#define regVPEC_HOLE_ADDR_LO_BASE_IDX 0 +#define regVPEC_HOLE_ADDR_HI 0x0069 +#define regVPEC_HOLE_ADDR_HI_BASE_IDX 0 +#define regVPEC_ERROR_LOG 0x006a +#define regVPEC_ERROR_LOG_BASE_IDX 0 +#define regVPEC_INT_STATUS 0x006b +#define regVPEC_INT_STATUS_BASE_IDX 0 +#define regVPEC_STATUS 0x006c +#define regVPEC_STATUS_BASE_IDX 0 +#define regVPEC_STATUS1 0x006d +#define regVPEC_STATUS1_BASE_IDX 0 +#define regVPEC_STATUS2 0x006e +#define regVPEC_STATUS2_BASE_IDX 0 +#define regVPEC_STATUS3 0x006f +#define regVPEC_STATUS3_BASE_IDX 0 +#define regVPEC_STATUS4 0x0070 +#define regVPEC_STATUS4_BASE_IDX 0 +#define regVPEC_STATUS5 0x0071 +#define regVPEC_STATUS5_BASE_IDX 0 +#define regVPEC_STATUS6 0x0072 +#define regVPEC_STATUS6_BASE_IDX 0 +#define regVPEC_STATUS7 0x0073 +#define regVPEC_STATUS7_BASE_IDX 0 +#define regVPEC_STATUS8 0x0074 +#define regVPEC_STATUS8_BASE_IDX 0 +#define regVPEC_STATUS9 0x0075 +#define regVPEC_STATUS9_BASE_IDX 0 +#define regVPEC_STATUS10 0x0076 +#define regVPEC_STATUS10_BASE_IDX 0 +#define regVPEC_STATUS_DCC 0x0077 +#define regVPEC_STATUS_DCC_BASE_IDX 0 +#define regVPEC_STATUS11 0x0078 +#define regVPEC_STATUS11_BASE_IDX 0 +#define regVPEC_INST 0x0079 +#define regVPEC_INST_BASE_IDX 0 +#define regVPEC_QUEUE_STATUS0 0x007a +#define regVPEC_QUEUE_STATUS0_BASE_IDX 0 +#define regVPEC_QUEUE_HANG_STATUS 0x007b +#define regVPEC_QUEUE_HANG_STATUS_BASE_IDX 0 +#define regVPEC_DPM_IDLE_TIME 0x007c +#define regVPEC_DPM_IDLE_TIME_BASE_IDX 0 +#define regVPEC_DPM_BUSY_TIME 0x007d +#define regVPEC_DPM_BUSY_TIME_BASE_IDX 0 +#define regVPEC_DPM_IDLE_START_LO 0x007e +#define regVPEC_DPM_IDLE_START_LO_BASE_IDX 0 +#define regVPEC_DPM_IDLE_START_HI 0x007f +#define regVPEC_DPM_IDLE_START_HI_BASE_IDX 0 +#define regVPEC_DPM_BUSY_START_LO 0x0080 +#define regVPEC_DPM_BUSY_START_LO_BASE_IDX 0 +#define regVPEC_DPM_BUSY_START_HI 0x0081 +#define regVPEC_DPM_BUSY_START_HI_BASE_IDX 0 +#define regVPEC_DPM_LAST_REQ_TIMESTAMP 0x0082 +#define regVPEC_DPM_LAST_REQ_TIMESTAMP_BASE_IDX 0 +#define regVPEC_DPM_NEW_JOB_DUMMY3 0x0083 +#define regVPEC_DPM_NEW_JOB_DUMMY3_BASE_IDX 0 +#define regVPEC_DPM_STATE 0x0084 +#define regVPEC_DPM_STATE_BASE_IDX 0 +#define regVPEC_DPM0_FREQ 0x0085 +#define regVPEC_DPM0_FREQ_BASE_IDX 0 +#define regVPEC_DPM1_FREQ 0x0086 +#define regVPEC_DPM1_FREQ_BASE_IDX 0 +#define regVPEC_DPM2_FREQ 0x0087 +#define regVPEC_DPM2_FREQ_BASE_IDX 0 +#define regVPEC_DPM3_FREQ 0x0088 +#define regVPEC_DPM3_FREQ_BASE_IDX 0 +#define regVPEC_DPM_THRESHOLD_SKIP 0x0089 +#define regVPEC_DPM_THRESHOLD_SKIP_BASE_IDX 0 +#define regVPEC_DPM_THRESHOLD_BUSY_OVERFLOW 0x008a +#define regVPEC_DPM_THRESHOLD_BUSY_OVERFLOW_BASE_IDX 0 +#define regVPEC_DPM_CALC_BUSY_IN_POSTPROCESS 0x008b +#define regVPEC_DPM_CALC_BUSY_IN_POSTPROCESS_BASE_IDX 0 +#define regVPEC_DPM_IN_CHECKIDLE_LOOP 0x008c +#define regVPEC_DPM_IN_CHECKIDLE_LOOP_BASE_IDX 0 +#define regVPEC_DPM_THRESHOLD_IDLE_OVERFLOW 0x008d +#define regVPEC_DPM_THRESHOLD_IDLE_OVERFLOW_BASE_IDX 0 +#define regVPEC_DPM_BUSY_CLAMP_COUNT 0x008e +#define regVPEC_DPM_BUSY_CLAMP_COUNT_BASE_IDX 0 +#define regVPEC_DPM_IDLE_CLAMP_COUNT 0x008f +#define regVPEC_DPM_IDLE_CLAMP_COUNT_BASE_IDX 0 +#define regVPEC_PG_CNTL 0x00b8 +#define regVPEC_PG_CNTL_BASE_IDX 0 +#define regVPEC_PG_STATUS 0x00b9 +#define regVPEC_PG_STATUS_BASE_IDX 0 +#define regVPEC_CLOCK_GATING_STATUS 0x00ba +#define regVPEC_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_CNTL 0x00c0 +#define regVPEC_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_SCHEDULE_CNTL 0x00c1 +#define regVPEC_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_BASE 0x00c2 +#define regVPEC_QUEUE0_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_BASE_HI 0x00c3 +#define regVPEC_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR 0x00c4 +#define regVPEC_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR_HI 0x00c5 +#define regVPEC_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_WPTR 0x00c6 +#define regVPEC_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_WPTR_HI 0x00c7 +#define regVPEC_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_HI 0x00c8 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_LO 0x00c9 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_AQL_CNTL 0x00ca +#define regVPEC_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_MINOR_PTR_UPDATE 0x00cb +#define regVPEC_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE0_CD_INFO 0x00cc +#define regVPEC_QUEUE0_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_PREEMPT 0x00cd +#define regVPEC_QUEUE0_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE0_SKIP_CNTL 0x00ce +#define regVPEC_QUEUE0_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_DOORBELL 0x00cf +#define regVPEC_QUEUE0_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE0_DOORBELL_OFFSET 0x00d0 +#define regVPEC_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY0 0x00d1 +#define regVPEC_QUEUE0_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY1 0x00d2 +#define regVPEC_QUEUE0_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY2 0x00d3 +#define regVPEC_QUEUE0_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY3 0x00d4 +#define regVPEC_QUEUE0_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY4 0x00d5 +#define regVPEC_QUEUE0_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_CNTL 0x00ec +#define regVPEC_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_RPTR 0x00ed +#define regVPEC_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_OFFSET 0x00ee +#define regVPEC_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_BASE_LO 0x00ef +#define regVPEC_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_BASE_HI 0x00f0 +#define regVPEC_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_SIZE 0x00f1 +#define regVPEC_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_CNTL 0x00f2 +#define regVPEC_QUEUE0_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_RPTR 0x00f3 +#define regVPEC_QUEUE0_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_OFFSET 0x00f4 +#define regVPEC_QUEUE0_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_BASE_LO 0x00f5 +#define regVPEC_QUEUE0_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_BASE_HI 0x00f6 +#define regVPEC_QUEUE0_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_SIZE 0x00f7 +#define regVPEC_QUEUE0_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_CNTL 0x00f8 +#define regVPEC_QUEUE0_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_RPTR 0x00f9 +#define regVPEC_QUEUE0_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_OFFSET 0x00fa +#define regVPEC_QUEUE0_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_BASE_LO 0x00fb +#define regVPEC_QUEUE0_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_BASE_HI 0x00fc +#define regVPEC_QUEUE0_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_SIZE 0x00fd +#define regVPEC_QUEUE0_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE0_CSA_ADDR_LO 0x00fe +#define regVPEC_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_CSA_ADDR_HI 0x00ff +#define regVPEC_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_CONTEXT_STATUS 0x0100 +#define regVPEC_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE0_DOORBELL_LOG 0x0101 +#define regVPEC_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_SUB_REMAIN 0x0102 +#define regVPEC_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE0_PREEMPT 0x0103 +#define regVPEC_QUEUE0_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE0_LOG0BUFFER_CFG 0x0104 +#define regVPEC_QUEUE0_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE0_LOG1BUFFER_CFG 0x0105 +#define regVPEC_QUEUE0_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_CNTL 0x0118 +#define regVPEC_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_SCHEDULE_CNTL 0x0119 +#define regVPEC_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_BASE 0x011a +#define regVPEC_QUEUE1_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_BASE_HI 0x011b +#define regVPEC_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR 0x011c +#define regVPEC_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR_HI 0x011d +#define regVPEC_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_WPTR 0x011e +#define regVPEC_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_WPTR_HI 0x011f +#define regVPEC_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_HI 0x0120 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_LO 0x0121 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_AQL_CNTL 0x0122 +#define regVPEC_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_MINOR_PTR_UPDATE 0x0123 +#define regVPEC_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE1_CD_INFO 0x0124 +#define regVPEC_QUEUE1_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_PREEMPT 0x0125 +#define regVPEC_QUEUE1_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE1_SKIP_CNTL 0x0126 +#define regVPEC_QUEUE1_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_DOORBELL 0x0127 +#define regVPEC_QUEUE1_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE1_DOORBELL_OFFSET 0x0128 +#define regVPEC_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY0 0x0129 +#define regVPEC_QUEUE1_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY1 0x012a +#define regVPEC_QUEUE1_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY2 0x012b +#define regVPEC_QUEUE1_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY3 0x012c +#define regVPEC_QUEUE1_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY4 0x012d +#define regVPEC_QUEUE1_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_CNTL 0x0144 +#define regVPEC_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_RPTR 0x0145 +#define regVPEC_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_OFFSET 0x0146 +#define regVPEC_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_BASE_LO 0x0147 +#define regVPEC_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_BASE_HI 0x0148 +#define regVPEC_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_SIZE 0x0149 +#define regVPEC_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_CNTL 0x014a +#define regVPEC_QUEUE1_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_RPTR 0x014b +#define regVPEC_QUEUE1_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_OFFSET 0x014c +#define regVPEC_QUEUE1_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_BASE_LO 0x014d +#define regVPEC_QUEUE1_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_BASE_HI 0x014e +#define regVPEC_QUEUE1_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_SIZE 0x014f +#define regVPEC_QUEUE1_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_CNTL 0x0150 +#define regVPEC_QUEUE1_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_RPTR 0x0151 +#define regVPEC_QUEUE1_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_OFFSET 0x0152 +#define regVPEC_QUEUE1_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_BASE_LO 0x0153 +#define regVPEC_QUEUE1_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_BASE_HI 0x0154 +#define regVPEC_QUEUE1_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_SIZE 0x0155 +#define regVPEC_QUEUE1_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE1_CSA_ADDR_LO 0x0156 +#define regVPEC_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_CSA_ADDR_HI 0x0157 +#define regVPEC_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_CONTEXT_STATUS 0x0158 +#define regVPEC_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE1_DOORBELL_LOG 0x0159 +#define regVPEC_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_SUB_REMAIN 0x015a +#define regVPEC_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE1_PREEMPT 0x015b +#define regVPEC_QUEUE1_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE1_LOG0BUFFER_CFG 0x015c +#define regVPEC_QUEUE1_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE1_LOG1BUFFER_CFG 0x015d +#define regVPEC_QUEUE1_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_CNTL 0x0170 +#define regVPEC_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_SCHEDULE_CNTL 0x0171 +#define regVPEC_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_BASE 0x0172 +#define regVPEC_QUEUE2_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_BASE_HI 0x0173 +#define regVPEC_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR 0x0174 +#define regVPEC_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR_HI 0x0175 +#define regVPEC_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_WPTR 0x0176 +#define regVPEC_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_WPTR_HI 0x0177 +#define regVPEC_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_HI 0x0178 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_LO 0x0179 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_AQL_CNTL 0x017a +#define regVPEC_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_MINOR_PTR_UPDATE 0x017b +#define regVPEC_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE2_CD_INFO 0x017c +#define regVPEC_QUEUE2_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_PREEMPT 0x017d +#define regVPEC_QUEUE2_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE2_SKIP_CNTL 0x017e +#define regVPEC_QUEUE2_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_DOORBELL 0x017f +#define regVPEC_QUEUE2_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE2_DOORBELL_OFFSET 0x0180 +#define regVPEC_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY0 0x0181 +#define regVPEC_QUEUE2_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY1 0x0182 +#define regVPEC_QUEUE2_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY2 0x0183 +#define regVPEC_QUEUE2_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY3 0x0184 +#define regVPEC_QUEUE2_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY4 0x0185 +#define regVPEC_QUEUE2_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_CNTL 0x019c +#define regVPEC_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_RPTR 0x019d +#define regVPEC_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_OFFSET 0x019e +#define regVPEC_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_BASE_LO 0x019f +#define regVPEC_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_BASE_HI 0x01a0 +#define regVPEC_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_SIZE 0x01a1 +#define regVPEC_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_CNTL 0x01a2 +#define regVPEC_QUEUE2_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_RPTR 0x01a3 +#define regVPEC_QUEUE2_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_OFFSET 0x01a4 +#define regVPEC_QUEUE2_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_BASE_LO 0x01a5 +#define regVPEC_QUEUE2_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_BASE_HI 0x01a6 +#define regVPEC_QUEUE2_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_SIZE 0x01a7 +#define regVPEC_QUEUE2_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_CNTL 0x01a8 +#define regVPEC_QUEUE2_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_RPTR 0x01a9 +#define regVPEC_QUEUE2_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_OFFSET 0x01aa +#define regVPEC_QUEUE2_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_BASE_LO 0x01ab +#define regVPEC_QUEUE2_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_BASE_HI 0x01ac +#define regVPEC_QUEUE2_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_SIZE 0x01ad +#define regVPEC_QUEUE2_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE2_CSA_ADDR_LO 0x01ae +#define regVPEC_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_CSA_ADDR_HI 0x01af +#define regVPEC_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_CONTEXT_STATUS 0x01b0 +#define regVPEC_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE2_DOORBELL_LOG 0x01b1 +#define regVPEC_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_SUB_REMAIN 0x01b2 +#define regVPEC_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE2_PREEMPT 0x01b3 +#define regVPEC_QUEUE2_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE2_LOG0BUFFER_CFG 0x01b4 +#define regVPEC_QUEUE2_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE2_LOG1BUFFER_CFG 0x01b5 +#define regVPEC_QUEUE2_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_CNTL 0x01c8 +#define regVPEC_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_SCHEDULE_CNTL 0x01c9 +#define regVPEC_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_BASE 0x01ca +#define regVPEC_QUEUE3_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_BASE_HI 0x01cb +#define regVPEC_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR 0x01cc +#define regVPEC_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR_HI 0x01cd +#define regVPEC_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_WPTR 0x01ce +#define regVPEC_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_WPTR_HI 0x01cf +#define regVPEC_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_HI 0x01d0 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_LO 0x01d1 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_AQL_CNTL 0x01d2 +#define regVPEC_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_MINOR_PTR_UPDATE 0x01d3 +#define regVPEC_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE3_CD_INFO 0x01d4 +#define regVPEC_QUEUE3_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_PREEMPT 0x01d5 +#define regVPEC_QUEUE3_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE3_SKIP_CNTL 0x01d6 +#define regVPEC_QUEUE3_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_DOORBELL 0x01d7 +#define regVPEC_QUEUE3_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE3_DOORBELL_OFFSET 0x01d8 +#define regVPEC_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY0 0x01d9 +#define regVPEC_QUEUE3_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY1 0x01da +#define regVPEC_QUEUE3_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY2 0x01db +#define regVPEC_QUEUE3_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY3 0x01dc +#define regVPEC_QUEUE3_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY4 0x01dd +#define regVPEC_QUEUE3_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_CNTL 0x01f4 +#define regVPEC_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_RPTR 0x01f5 +#define regVPEC_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_OFFSET 0x01f6 +#define regVPEC_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_BASE_LO 0x01f7 +#define regVPEC_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_BASE_HI 0x01f8 +#define regVPEC_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_SIZE 0x01f9 +#define regVPEC_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_CNTL 0x01fa +#define regVPEC_QUEUE3_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_RPTR 0x01fb +#define regVPEC_QUEUE3_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_OFFSET 0x01fc +#define regVPEC_QUEUE3_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_BASE_LO 0x01fd +#define regVPEC_QUEUE3_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_BASE_HI 0x01fe +#define regVPEC_QUEUE3_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_SIZE 0x01ff +#define regVPEC_QUEUE3_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_CNTL 0x0200 +#define regVPEC_QUEUE3_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_RPTR 0x0201 +#define regVPEC_QUEUE3_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_OFFSET 0x0202 +#define regVPEC_QUEUE3_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_BASE_LO 0x0203 +#define regVPEC_QUEUE3_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_BASE_HI 0x0204 +#define regVPEC_QUEUE3_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_SIZE 0x0205 +#define regVPEC_QUEUE3_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE3_CSA_ADDR_LO 0x0206 +#define regVPEC_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_CSA_ADDR_HI 0x0207 +#define regVPEC_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_CONTEXT_STATUS 0x0208 +#define regVPEC_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE3_DOORBELL_LOG 0x0209 +#define regVPEC_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_SUB_REMAIN 0x020a +#define regVPEC_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE3_PREEMPT 0x020b +#define regVPEC_QUEUE3_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE3_LOG0BUFFER_CFG 0x020c +#define regVPEC_QUEUE3_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE3_LOG1BUFFER_CFG 0x020d +#define regVPEC_QUEUE3_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_CNTL 0x0220 +#define regVPEC_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_SCHEDULE_CNTL 0x0221 +#define regVPEC_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_BASE 0x0222 +#define regVPEC_QUEUE4_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_BASE_HI 0x0223 +#define regVPEC_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR 0x0224 +#define regVPEC_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR_HI 0x0225 +#define regVPEC_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_WPTR 0x0226 +#define regVPEC_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_WPTR_HI 0x0227 +#define regVPEC_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_HI 0x0228 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_LO 0x0229 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_AQL_CNTL 0x022a +#define regVPEC_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_MINOR_PTR_UPDATE 0x022b +#define regVPEC_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE4_CD_INFO 0x022c +#define regVPEC_QUEUE4_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_PREEMPT 0x022d +#define regVPEC_QUEUE4_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE4_SKIP_CNTL 0x022e +#define regVPEC_QUEUE4_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_DOORBELL 0x022f +#define regVPEC_QUEUE4_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE4_DOORBELL_OFFSET 0x0230 +#define regVPEC_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY0 0x0231 +#define regVPEC_QUEUE4_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY1 0x0232 +#define regVPEC_QUEUE4_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY2 0x0233 +#define regVPEC_QUEUE4_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY3 0x0234 +#define regVPEC_QUEUE4_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY4 0x0235 +#define regVPEC_QUEUE4_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_CNTL 0x024c +#define regVPEC_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_RPTR 0x024d +#define regVPEC_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_OFFSET 0x024e +#define regVPEC_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_BASE_LO 0x024f +#define regVPEC_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_BASE_HI 0x0250 +#define regVPEC_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_SIZE 0x0251 +#define regVPEC_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_CNTL 0x0252 +#define regVPEC_QUEUE4_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_RPTR 0x0253 +#define regVPEC_QUEUE4_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_OFFSET 0x0254 +#define regVPEC_QUEUE4_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_BASE_LO 0x0255 +#define regVPEC_QUEUE4_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_BASE_HI 0x0256 +#define regVPEC_QUEUE4_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_SIZE 0x0257 +#define regVPEC_QUEUE4_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_CNTL 0x0258 +#define regVPEC_QUEUE4_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_RPTR 0x0259 +#define regVPEC_QUEUE4_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_OFFSET 0x025a +#define regVPEC_QUEUE4_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_BASE_LO 0x025b +#define regVPEC_QUEUE4_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_BASE_HI 0x025c +#define regVPEC_QUEUE4_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_SIZE 0x025d +#define regVPEC_QUEUE4_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE4_CSA_ADDR_LO 0x025e +#define regVPEC_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_CSA_ADDR_HI 0x025f +#define regVPEC_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_CONTEXT_STATUS 0x0260 +#define regVPEC_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE4_DOORBELL_LOG 0x0261 +#define regVPEC_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_SUB_REMAIN 0x0262 +#define regVPEC_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE4_PREEMPT 0x0263 +#define regVPEC_QUEUE4_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE4_LOG0BUFFER_CFG 0x0264 +#define regVPEC_QUEUE4_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE4_LOG1BUFFER_CFG 0x0265 +#define regVPEC_QUEUE4_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_CNTL 0x0278 +#define regVPEC_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_SCHEDULE_CNTL 0x0279 +#define regVPEC_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_BASE 0x027a +#define regVPEC_QUEUE5_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_BASE_HI 0x027b +#define regVPEC_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR 0x027c +#define regVPEC_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR_HI 0x027d +#define regVPEC_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_WPTR 0x027e +#define regVPEC_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_WPTR_HI 0x027f +#define regVPEC_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_HI 0x0280 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_LO 0x0281 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_AQL_CNTL 0x0282 +#define regVPEC_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_MINOR_PTR_UPDATE 0x0283 +#define regVPEC_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE5_CD_INFO 0x0284 +#define regVPEC_QUEUE5_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_PREEMPT 0x0285 +#define regVPEC_QUEUE5_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE5_SKIP_CNTL 0x0286 +#define regVPEC_QUEUE5_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_DOORBELL 0x0287 +#define regVPEC_QUEUE5_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE5_DOORBELL_OFFSET 0x0288 +#define regVPEC_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY0 0x0289 +#define regVPEC_QUEUE5_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY1 0x028a +#define regVPEC_QUEUE5_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY2 0x028b +#define regVPEC_QUEUE5_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY3 0x028c +#define regVPEC_QUEUE5_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY4 0x028d +#define regVPEC_QUEUE5_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_CNTL 0x02a4 +#define regVPEC_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_RPTR 0x02a5 +#define regVPEC_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_OFFSET 0x02a6 +#define regVPEC_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_BASE_LO 0x02a7 +#define regVPEC_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_BASE_HI 0x02a8 +#define regVPEC_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_SIZE 0x02a9 +#define regVPEC_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_CNTL 0x02aa +#define regVPEC_QUEUE5_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_RPTR 0x02ab +#define regVPEC_QUEUE5_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_OFFSET 0x02ac +#define regVPEC_QUEUE5_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_BASE_LO 0x02ad +#define regVPEC_QUEUE5_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_BASE_HI 0x02ae +#define regVPEC_QUEUE5_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_SIZE 0x02af +#define regVPEC_QUEUE5_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_CNTL 0x02b0 +#define regVPEC_QUEUE5_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_RPTR 0x02b1 +#define regVPEC_QUEUE5_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_OFFSET 0x02b2 +#define regVPEC_QUEUE5_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_BASE_LO 0x02b3 +#define regVPEC_QUEUE5_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_BASE_HI 0x02b4 +#define regVPEC_QUEUE5_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_SIZE 0x02b5 +#define regVPEC_QUEUE5_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE5_CSA_ADDR_LO 0x02b6 +#define regVPEC_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_CSA_ADDR_HI 0x02b7 +#define regVPEC_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_CONTEXT_STATUS 0x02b8 +#define regVPEC_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE5_DOORBELL_LOG 0x02b9 +#define regVPEC_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_SUB_REMAIN 0x02ba +#define regVPEC_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE5_PREEMPT 0x02bb +#define regVPEC_QUEUE5_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE5_LOG0BUFFER_CFG 0x02bc +#define regVPEC_QUEUE5_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE5_LOG1BUFFER_CFG 0x02bd +#define regVPEC_QUEUE5_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_CNTL 0x02d0 +#define regVPEC_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_SCHEDULE_CNTL 0x02d1 +#define regVPEC_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_BASE 0x02d2 +#define regVPEC_QUEUE6_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_BASE_HI 0x02d3 +#define regVPEC_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR 0x02d4 +#define regVPEC_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR_HI 0x02d5 +#define regVPEC_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_WPTR 0x02d6 +#define regVPEC_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_WPTR_HI 0x02d7 +#define regVPEC_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_HI 0x02d8 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_LO 0x02d9 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_AQL_CNTL 0x02da +#define regVPEC_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_MINOR_PTR_UPDATE 0x02db +#define regVPEC_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE6_CD_INFO 0x02dc +#define regVPEC_QUEUE6_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_PREEMPT 0x02dd +#define regVPEC_QUEUE6_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE6_SKIP_CNTL 0x02de +#define regVPEC_QUEUE6_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_DOORBELL 0x02df +#define regVPEC_QUEUE6_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE6_DOORBELL_OFFSET 0x02e0 +#define regVPEC_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY0 0x02e1 +#define regVPEC_QUEUE6_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY1 0x02e2 +#define regVPEC_QUEUE6_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY2 0x02e3 +#define regVPEC_QUEUE6_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY3 0x02e4 +#define regVPEC_QUEUE6_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY4 0x02e5 +#define regVPEC_QUEUE6_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_CNTL 0x02fc +#define regVPEC_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_RPTR 0x02fd +#define regVPEC_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_OFFSET 0x02fe +#define regVPEC_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_BASE_LO 0x02ff +#define regVPEC_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_BASE_HI 0x0300 +#define regVPEC_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_SIZE 0x0301 +#define regVPEC_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_CNTL 0x0302 +#define regVPEC_QUEUE6_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_RPTR 0x0303 +#define regVPEC_QUEUE6_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_OFFSET 0x0304 +#define regVPEC_QUEUE6_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_BASE_LO 0x0305 +#define regVPEC_QUEUE6_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_BASE_HI 0x0306 +#define regVPEC_QUEUE6_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_SIZE 0x0307 +#define regVPEC_QUEUE6_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_CNTL 0x0308 +#define regVPEC_QUEUE6_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_RPTR 0x0309 +#define regVPEC_QUEUE6_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_OFFSET 0x030a +#define regVPEC_QUEUE6_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_BASE_LO 0x030b +#define regVPEC_QUEUE6_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_BASE_HI 0x030c +#define regVPEC_QUEUE6_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_SIZE 0x030d +#define regVPEC_QUEUE6_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE6_CSA_ADDR_LO 0x030e +#define regVPEC_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_CSA_ADDR_HI 0x030f +#define regVPEC_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_CONTEXT_STATUS 0x0310 +#define regVPEC_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE6_DOORBELL_LOG 0x0311 +#define regVPEC_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_SUB_REMAIN 0x0312 +#define regVPEC_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE6_PREEMPT 0x0313 +#define regVPEC_QUEUE6_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE6_LOG0BUFFER_CFG 0x0314 +#define regVPEC_QUEUE6_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE6_LOG1BUFFER_CFG 0x0315 +#define regVPEC_QUEUE6_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_CNTL 0x0328 +#define regVPEC_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_SCHEDULE_CNTL 0x0329 +#define regVPEC_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_BASE 0x032a +#define regVPEC_QUEUE7_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_BASE_HI 0x032b +#define regVPEC_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR 0x032c +#define regVPEC_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR_HI 0x032d +#define regVPEC_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_WPTR 0x032e +#define regVPEC_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_WPTR_HI 0x032f +#define regVPEC_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_HI 0x0330 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_LO 0x0331 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_AQL_CNTL 0x0332 +#define regVPEC_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_MINOR_PTR_UPDATE 0x0333 +#define regVPEC_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE7_CD_INFO 0x0334 +#define regVPEC_QUEUE7_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_PREEMPT 0x0335 +#define regVPEC_QUEUE7_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE7_SKIP_CNTL 0x0336 +#define regVPEC_QUEUE7_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_DOORBELL 0x0337 +#define regVPEC_QUEUE7_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE7_DOORBELL_OFFSET 0x0338 +#define regVPEC_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY0 0x0339 +#define regVPEC_QUEUE7_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY1 0x033a +#define regVPEC_QUEUE7_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY2 0x033b +#define regVPEC_QUEUE7_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY3 0x033c +#define regVPEC_QUEUE7_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY4 0x033d +#define regVPEC_QUEUE7_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_CNTL 0x0354 +#define regVPEC_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_RPTR 0x0355 +#define regVPEC_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_OFFSET 0x0356 +#define regVPEC_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_BASE_LO 0x0357 +#define regVPEC_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_BASE_HI 0x0358 +#define regVPEC_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_SIZE 0x0359 +#define regVPEC_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_CNTL 0x035a +#define regVPEC_QUEUE7_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_RPTR 0x035b +#define regVPEC_QUEUE7_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_OFFSET 0x035c +#define regVPEC_QUEUE7_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_BASE_LO 0x035d +#define regVPEC_QUEUE7_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_BASE_HI 0x035e +#define regVPEC_QUEUE7_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_SIZE 0x035f +#define regVPEC_QUEUE7_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_CNTL 0x0360 +#define regVPEC_QUEUE7_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_RPTR 0x0361 +#define regVPEC_QUEUE7_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_OFFSET 0x0362 +#define regVPEC_QUEUE7_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_BASE_LO 0x0363 +#define regVPEC_QUEUE7_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_BASE_HI 0x0364 +#define regVPEC_QUEUE7_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_SIZE 0x0365 +#define regVPEC_QUEUE7_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE7_CSA_ADDR_LO 0x0366 +#define regVPEC_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_CSA_ADDR_HI 0x0367 +#define regVPEC_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_CONTEXT_STATUS 0x0368 +#define regVPEC_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE7_DOORBELL_LOG 0x0369 +#define regVPEC_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_SUB_REMAIN 0x036a +#define regVPEC_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE7_PREEMPT 0x036b +#define regVPEC_QUEUE7_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE7_LOG0BUFFER_CFG 0x036c +#define regVPEC_QUEUE7_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE7_LOG1BUFFER_CFG 0x036d +#define regVPEC_QUEUE7_LOG1BUFFER_CFG_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_sh_mask.h new file mode 100644 index 000000000000..7e0e56d14e67 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_sh_mask.h @@ -0,0 +1,3162 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _vpe_2_0_0_SH_MASK_HEADER +#define _vpe_2_0_0_SH_MASK_HEADER + + +// addressBlock: vpe_vpec_vpecdec +//VPEC_DEC_START +#define VPEC_DEC_START__START__SHIFT 0x0 +#define VPEC_DEC_START__START_MASK 0xFFFFFFFFL +//VPEC_UCODE_ADDR +#define VPEC_UCODE_ADDR__VALUE__SHIFT 0x0 +#define VPEC_UCODE_ADDR__THID__SHIFT 0xf +#define VPEC_UCODE_ADDR__VALUE_MASK 0x00001FFFL +#define VPEC_UCODE_ADDR__THID_MASK 0x00008000L +//VPEC_UCODE_DATA +#define VPEC_UCODE_DATA__VALUE__SHIFT 0x0 +#define VPEC_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//VPEC_F32_CNTL +#define VPEC_F32_CNTL__HALT__SHIFT 0x0 +#define VPEC_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8 +#define VPEC_F32_CNTL__TH0_RESET__SHIFT 0x9 +#define VPEC_F32_CNTL__TH0_ENABLE__SHIFT 0xa +#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc +#define VPEC_F32_CNTL__TH1_RESET__SHIFT 0xd +#define VPEC_F32_CNTL__TH1_ENABLE__SHIFT 0xe +#define VPEC_F32_CNTL__TH0_PRIORITY__SHIFT 0x10 +#define VPEC_F32_CNTL__TH1_PRIORITY__SHIFT 0x18 +#define VPEC_F32_CNTL__HALT_MASK 0x00000001L +#define VPEC_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL +#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L +#define VPEC_F32_CNTL__TH0_RESET_MASK 0x00000200L +#define VPEC_F32_CNTL__TH0_ENABLE_MASK 0x00000400L +#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L +#define VPEC_F32_CNTL__TH1_RESET_MASK 0x00002000L +#define VPEC_F32_CNTL__TH1_ENABLE_MASK 0x00004000L +#define VPEC_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L +#define VPEC_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L +//VPEC_MMHUB_CNTL +#define VPEC_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define VPEC_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//VPEC_MMHUB_TRUSTLVL +#define VPEC_MMHUB_TRUSTLVL__SECLVL0__SHIFT 0x0 +#define VPEC_MMHUB_TRUSTLVL__SECLVL1__SHIFT 0x4 +#define VPEC_MMHUB_TRUSTLVL__SECLVL2__SHIFT 0x8 +#define VPEC_MMHUB_TRUSTLVL__SECLVL3__SHIFT 0xc +#define VPEC_MMHUB_TRUSTLVL__SECLVL4__SHIFT 0x10 +#define VPEC_MMHUB_TRUSTLVL__SECLVL5__SHIFT 0x14 +#define VPEC_MMHUB_TRUSTLVL__SECLVL6__SHIFT 0x18 +#define VPEC_MMHUB_TRUSTLVL__SECLVL7__SHIFT 0x1c +#define VPEC_MMHUB_TRUSTLVL__SECLVL0_MASK 0x0000000FL +#define VPEC_MMHUB_TRUSTLVL__SECLVL1_MASK 0x000000F0L +#define VPEC_MMHUB_TRUSTLVL__SECLVL2_MASK 0x00000F00L +#define VPEC_MMHUB_TRUSTLVL__SECLVL3_MASK 0x0000F000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL4_MASK 0x000F0000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL5_MASK 0x00F00000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL6_MASK 0x0F000000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL7_MASK 0xF0000000L +//VPEC_VPEP_CTRL +#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN__SHIFT 0x0 +#define VPEC_VPEP_CTRL__VPEP_SW_RESETB__SHIFT 0x1 +#define VPEC_VPEP_CTRL__RESERVED__SHIFT 0x2 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P0__SHIFT 0x16 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P1__SHIFT 0x17 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P2__SHIFT 0x18 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P0__SHIFT 0x19 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P1__SHIFT 0x1a +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P2__SHIFT 0x1b +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_3DLUT__SHIFT 0x1c +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEC_VPEP_REG_FGCLKEN__SHIFT 0x1d +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK__SHIFT 0x1e +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK__SHIFT 0x1f +#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN_MASK 0x00000001L +#define VPEC_VPEP_CTRL__VPEP_SW_RESETB_MASK 0x00000002L +#define VPEC_VPEP_CTRL__RESERVED_MASK 0x003FFFFCL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P0_MASK 0x00400000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P1_MASK 0x00800000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P2_MASK 0x01000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P0_MASK 0x02000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P1_MASK 0x04000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P2_MASK 0x08000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_3DLUT_MASK 0x10000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEC_VPEP_REG_FGCLKEN_MASK 0x20000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK_MASK 0x40000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK_MASK 0x80000000L +//VPEC_CLK_CTRL +#define VPEC_CLK_CTRL__VPECLK_EN__SHIFT 0x1 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK__SHIFT 0x8 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK__SHIFT 0x9 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE2_CLK__SHIFT 0xa +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE3_CLK__SHIFT 0xb +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE4_CLK__SHIFT 0xc +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE5_CLK__SHIFT 0xd +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK__SHIFT 0x10 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE1_CLK__SHIFT 0x11 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE2_CLK__SHIFT 0x12 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE3_CLK__SHIFT 0x13 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE4_CLK__SHIFT 0x14 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE5_CLK__SHIFT 0x15 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE6_CLK__SHIFT 0x16 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE7_CLK__SHIFT 0x17 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE8_CLK__SHIFT 0x18 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE9_CLK__SHIFT 0x19 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK__SHIFT 0x1b +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK__SHIFT 0x1c +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK__SHIFT 0x1d +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK__SHIFT 0x1e +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK__SHIFT 0x1f +#define VPEC_CLK_CTRL__VPECLK_EN_MASK 0x00000002L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK_MASK 0x00000100L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK_MASK 0x00000200L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE2_CLK_MASK 0x00000400L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE3_CLK_MASK 0x00000800L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE4_CLK_MASK 0x00001000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE5_CLK_MASK 0x00002000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK_MASK 0x00010000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE1_CLK_MASK 0x00020000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE2_CLK_MASK 0x00040000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE3_CLK_MASK 0x00080000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE4_CLK_MASK 0x00100000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE5_CLK_MASK 0x00200000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE6_CLK_MASK 0x00400000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE7_CLK_MASK 0x00800000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE8_CLK_MASK 0x01000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE9_CLK_MASK 0x02000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK_MASK 0x08000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK_MASK 0x10000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK_MASK 0x20000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK_MASK 0x40000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK_MASK 0x80000000L +//VPEC_COLLABORATE_CNTL +#define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN__SHIFT 0x0 +#define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN_MASK 0x00000001L +//VPEC_COLLABORATE_CFG +#define VPEC_COLLABORATE_CFG__MASTER_ID__SHIFT 0x0 +#define VPEC_COLLABORATE_CFG__MASTER_EN__SHIFT 0x3 +#define VPEC_COLLABORATE_CFG__SLAVE0_ID__SHIFT 0x4 +#define VPEC_COLLABORATE_CFG__SLAVE0_EN__SHIFT 0x7 +#define VPEC_COLLABORATE_CFG__MASTER_ID_MASK 0x00000007L +#define VPEC_COLLABORATE_CFG__MASTER_EN_MASK 0x00000008L +#define VPEC_COLLABORATE_CFG__SLAVE0_ID_MASK 0x00000070L +#define VPEC_COLLABORATE_CFG__SLAVE0_EN_MASK 0x00000080L +//VPEC_POWER_CNTL +#define VPEC_POWER_CNTL__LS_ENABLE__SHIFT 0x0 +#define VPEC_POWER_CNTL__UCODE_SRAM_DS_EN__SHIFT 0x1 +#define VPEC_POWER_CNTL__FISO__SHIFT 0x2 +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_WAKEUP_TIME__SHIFT 0xf +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_CLK_FORCE__SHIFT 0x12 +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_DELAY__SHIFT 0x14 +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE__SHIFT 0x17 +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_DELAY__SHIFT 0x18 +#define VPEC_POWER_CNTL__LS_ENABLE_MASK 0x00000001L +#define VPEC_POWER_CNTL__UCODE_SRAM_DS_EN_MASK 0x00000002L +#define VPEC_POWER_CNTL__FISO_MASK 0x00000004L +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_UP_RECOVER_DELAY_MASK 0x00007F00L +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_WAKEUP_TIME_MASK 0x00038000L +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_CLK_FORCE_MASK 0x00040000L +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_DELAY_MASK 0x00700000L +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_MASK 0x00800000L +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_DELAY_MASK 0x03000000L +//VPEC_ZPR_CNTL +#define VPEC_ZPR_CNTL__CLK_UNGATE_DELAY__SHIFT 0x0 +#define VPEC_ZPR_CNTL__RESERVED__SHIFT 0x8 +#define VPEC_ZPR_CNTL__CLK_UNGATE_DELAY_MASK 0x000000FFL +#define VPEC_ZPR_CNTL__RESERVED_MASK 0xFFFFFF00L +//VPEC_CNTL +#define VPEC_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define VPEC_CNTL__RESERVED_2_2__SHIFT 0x2 +#define VPEC_CNTL__DATA_SWAP__SHIFT 0x3 +#define VPEC_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x5 +#define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x6 +#define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 +#define VPEC_CNTL__UMSCH_INT_ENABLE__SHIFT 0xa +#define VPEC_CNTL__RESERVED_13_11__SHIFT 0xb +#define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xe +#define VPEC_CNTL__NACK_PRT_INT_ENABLE__SHIFT 0xf +#define VPEC_CNTL__RESERVED_16_16__SHIFT 0x10 +#define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define VPEC_CNTL__RESERVED_19_19__SHIFT 0x13 +#define VPEC_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define VPEC_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define VPEC_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define VPEC_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f +#define VPEC_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define VPEC_CNTL__RESERVED_2_2_MASK 0x00000004L +#define VPEC_CNTL__DATA_SWAP_MASK 0x00000018L +#define VPEC_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000020L +#define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000040L +#define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L +#define VPEC_CNTL__UMSCH_INT_ENABLE_MASK 0x00000400L +#define VPEC_CNTL__RESERVED_13_11_MASK 0x00003800L +#define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00004000L +#define VPEC_CNTL__NACK_PRT_INT_ENABLE_MASK 0x00008000L +#define VPEC_CNTL__RESERVED_16_16_MASK 0x00010000L +#define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define VPEC_CNTL__RESERVED_19_19_MASK 0x00080000L +#define VPEC_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define VPEC_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define VPEC_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +#define VPEC_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L +//VPEC_CNTL_DCC +#define VPEC_CNTL_DCC__WDCC_COMP_MODE__SHIFT 0x0 +#define VPEC_CNTL_DCC__RESERVED_3_2__SHIFT 0x2 +#define VPEC_CNTL_DCC__WDCC_MICRO_TILE_MODE__SHIFT 0x4 +#define VPEC_CNTL_DCC__RESERVED_7_6__SHIFT 0x6 +#define VPEC_CNTL_DCC__WDCC_DATA_FORMAT__SHIFT 0x8 +#define VPEC_CNTL_DCC__RESERVED_15_13__SHIFT 0xd +#define VPEC_CNTL_DCC__WDCC_NUM_FORMAT_EN__SHIFT 0x10 +#define VPEC_CNTL_DCC__RESERVED_19_17__SHIFT 0x11 +#define VPEC_CNTL_DCC__WDCC_NUM_TYPE__SHIFT 0x14 +#define VPEC_CNTL_DCC__RESERVED_23_23__SHIFT 0x17 +#define VPEC_CNTL_DCC__WDCC_MAX_UNCOMP_SIZE__SHIFT 0x18 +#define VPEC_CNTL_DCC__WDCC_MAX_COMP_SIZE__SHIFT 0x19 +#define VPEC_CNTL_DCC__RESERVED_30_27__SHIFT 0x1b +#define VPEC_CNTL_DCC__RDCC_COMP_MODE__SHIFT 0x1f +#define VPEC_CNTL_DCC__WDCC_COMP_MODE_MASK 0x00000003L +#define VPEC_CNTL_DCC__RESERVED_3_2_MASK 0x0000000CL +#define VPEC_CNTL_DCC__WDCC_MICRO_TILE_MODE_MASK 0x00000030L +#define VPEC_CNTL_DCC__RESERVED_7_6_MASK 0x000000C0L +#define VPEC_CNTL_DCC__WDCC_DATA_FORMAT_MASK 0x00001F00L +#define VPEC_CNTL_DCC__RESERVED_15_13_MASK 0x0000E000L +#define VPEC_CNTL_DCC__WDCC_NUM_FORMAT_EN_MASK 0x00010000L +#define VPEC_CNTL_DCC__RESERVED_19_17_MASK 0x000E0000L +#define VPEC_CNTL_DCC__WDCC_NUM_TYPE_MASK 0x00700000L +#define VPEC_CNTL_DCC__RESERVED_23_23_MASK 0x00800000L +#define VPEC_CNTL_DCC__WDCC_MAX_UNCOMP_SIZE_MASK 0x01000000L +#define VPEC_CNTL_DCC__WDCC_MAX_COMP_SIZE_MASK 0x06000000L +#define VPEC_CNTL_DCC__RESERVED_30_27_MASK 0x78000000L +#define VPEC_CNTL_DCC__RDCC_COMP_MODE_MASK 0x80000000L +//VPEC_CE_OP_MULTI_64B_BURST +#define VPEC_CE_OP_MULTI_64B_BURST__EN__SHIFT 0x0 +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_3_1__SHIFT 0x1 +#define VPEC_CE_OP_MULTI_64B_BURST__LAZY_TIMER_DLY__SHIFT 0x4 +#define VPEC_CE_OP_MULTI_64B_BURST__NUM_64B_BURST_ALLOWED__SHIFT 0xa +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_31_12__SHIFT 0xc +#define VPEC_CE_OP_MULTI_64B_BURST__EN_MASK 0x00000001L +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_3_1_MASK 0x0000000EL +#define VPEC_CE_OP_MULTI_64B_BURST__LAZY_TIMER_DLY_MASK 0x000003F0L +#define VPEC_CE_OP_MULTI_64B_BURST__NUM_64B_BURST_ALLOWED_MASK 0x00000C00L +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_31_12_MASK 0xFFFFF000L +//VPEC_CNTL1 +#define VPEC_CNTL1__RESERVED_3_1__SHIFT 0x1 +#define VPEC_CNTL1__SRBM_POLL_RETRYING__SHIFT 0x5 +#define VPEC_CNTL1__RESERVED_23_10__SHIFT 0xa +#define VPEC_CNTL1__CG_STATUS_OUTPUT__SHIFT 0x18 +#define VPEC_CNTL1__SW_FREEZE_ENABLE__SHIFT 0x19 +#define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE__SHIFT 0x1a +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_RETURN_ERROR_ENABLE__SHIFT 0x1b +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_REPORT_ERROR_ENABLE__SHIFT 0x1c +#define VPEC_CNTL1__RESERVED__SHIFT 0x1d +#define VPEC_CNTL1__RESERVED_3_1_MASK 0x0000000EL +#define VPEC_CNTL1__SRBM_POLL_RETRYING_MASK 0x00000020L +#define VPEC_CNTL1__RESERVED_23_10_MASK 0x00FFFC00L +#define VPEC_CNTL1__CG_STATUS_OUTPUT_MASK 0x01000000L +#define VPEC_CNTL1__SW_FREEZE_ENABLE_MASK 0x02000000L +#define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE_MASK 0x04000000L +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_RETURN_ERROR_ENABLE_MASK 0x08000000L +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_REPORT_ERROR_ENABLE_MASK 0x10000000L +#define VPEC_CNTL1__RESERVED_MASK 0xE0000000L +//VPEC_CNTL2 +#define VPEC_CNTL2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define VPEC_CNTL2__F32_SEND_POSTCODE_EN__SHIFT 0x4 +#define VPEC_CNTL2__UCODE_BUF_DS_EN__SHIFT 0x6 +#define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT 0x7 +#define VPEC_CNTL2__LUTIB_FIFO_WATERMARK__SHIFT 0x8 +#define VPEC_CNTL2__CMDIB_FIFO_WATERMARK__SHIFT 0xa +#define VPEC_CNTL2__RESERVED_14_12__SHIFT 0xc +#define VPEC_CNTL2__IMPROVE_CE_IP_ARBITER__SHIFT 0xf +#define VPEC_CNTL2__RB_FIFO_WATERMARK__SHIFT 0x10 +#define VPEC_CNTL2__IB_FIFO_WATERMARK__SHIFT 0x12 +#define VPEC_CNTL2__RESERVED_22_20__SHIFT 0x14 +#define VPEC_CNTL2__CH_RD_WATERMARK__SHIFT 0x17 +#define VPEC_CNTL2__CH_WR_WATERMARK__SHIFT 0x19 +#define VPEC_CNTL2__CH_WR_WATERMARK_LSB__SHIFT 0x1e +#define VPEC_CNTL2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +#define VPEC_CNTL2__F32_SEND_POSTCODE_EN_MASK 0x00000010L +#define VPEC_CNTL2__UCODE_BUF_DS_EN_MASK 0x00000040L +#define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK 0x00000080L +#define VPEC_CNTL2__LUTIB_FIFO_WATERMARK_MASK 0x00000300L +#define VPEC_CNTL2__CMDIB_FIFO_WATERMARK_MASK 0x00000C00L +#define VPEC_CNTL2__RESERVED_14_12_MASK 0x00007000L +#define VPEC_CNTL2__IMPROVE_CE_IP_ARBITER_MASK 0x00008000L +#define VPEC_CNTL2__RB_FIFO_WATERMARK_MASK 0x00030000L +#define VPEC_CNTL2__IB_FIFO_WATERMARK_MASK 0x000C0000L +#define VPEC_CNTL2__RESERVED_22_20_MASK 0x00700000L +#define VPEC_CNTL2__CH_RD_WATERMARK_MASK 0x01800000L +#define VPEC_CNTL2__CH_WR_WATERMARK_MASK 0x3E000000L +#define VPEC_CNTL2__CH_WR_WATERMARK_LSB_MASK 0x40000000L +//VPEC_GB_ADDR_CONFIG +#define VPEC_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define VPEC_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 +#define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define VPEC_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define VPEC_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L +#define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +//VPEC_GB_ADDR_CONFIG_READ +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L +#define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +#define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +//VPEC_GB_ADDR_CONFIG_META +#define VPEC_GB_ADDR_CONFIG_META__NUM_PIPES__SHIFT 0x0 +#define VPEC_GB_ADDR_CONFIG_META__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define VPEC_GB_ADDR_CONFIG_META__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define VPEC_GB_ADDR_CONFIG_META__NUM_PKRS__SHIFT 0x8 +#define VPEC_GB_ADDR_CONFIG_META__NUM_SHADER_ENGINES__SHIFT 0x13 +#define VPEC_GB_ADDR_CONFIG_META__NUM_RB_PER_SE__SHIFT 0x1a +#define VPEC_GB_ADDR_CONFIG_META__NUM_PIPES_MASK 0x00000007L +#define VPEC_GB_ADDR_CONFIG_META__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define VPEC_GB_ADDR_CONFIG_META__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define VPEC_GB_ADDR_CONFIG_META__NUM_PKRS_MASK 0x00000700L +#define VPEC_GB_ADDR_CONFIG_META__NUM_SHADER_ENGINES_MASK 0x00180000L +#define VPEC_GB_ADDR_CONFIG_META__NUM_RB_PER_SE_MASK 0x0C000000L +//VPEC_PROCESS_QUANTUM0 +#define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 +#define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 +#define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 +#define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 +#define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL +#define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L +#define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L +#define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L +//VPEC_PROCESS_QUANTUM1 +#define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 +#define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 +#define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 +#define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 +#define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL +#define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L +#define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L +#define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L +//VPEC_CONTEXT_SWITCH_THRESHOLD +#define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD__SHIFT 0x0 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD__SHIFT 0x2 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD__SHIFT 0x4 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD__SHIFT 0x6 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD_MASK 0x00000003L +#define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD_MASK 0x0000000CL +#define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD_MASK 0x00000030L +#define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD_MASK 0x000000C0L +//VPEC_GLOBAL_QUANTUM +#define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 +#define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 +#define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL +#define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L +//VPEC_WATCHDOG_CNTL +#define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 +#define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 +#define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL +#define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L +//VPEC_ATOMIC_CNTL +#define VPEC_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define VPEC_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//VPEC_UCODE_VERSION +#define VPEC_UCODE_VERSION__T0_UCODE_VERSION__SHIFT 0x0 +#define VPEC_UCODE_VERSION__T1_UCODE_VERSION__SHIFT 0x10 +#define VPEC_UCODE_VERSION__T0_UCODE_VERSION_MASK 0x0000FFFFL +#define VPEC_UCODE_VERSION__T1_UCODE_VERSION_MASK 0xFFFF0000L +//VPEC_MEMREQ_BURST_CNTL +#define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST__SHIFT 0x0 +#define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST__SHIFT 0x2 +#define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST__SHIFT 0x4 +#define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST__SHIFT 0x6 +#define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE__SHIFT 0x8 +#define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST_MASK 0x00000003L +#define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST_MASK 0x0000000CL +#define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST_MASK 0x00000030L +#define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST_MASK 0x000000C0L +#define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE_MASK 0x00000700L +//VPEC_TIMESTAMP_CNTL +#define VPEC_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 +#define VPEC_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L +//VPEC_GLOBAL_TIMESTAMP_LO +#define VPEC_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 +#define VPEC_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL +//VPEC_GLOBAL_TIMESTAMP_HI +#define VPEC_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 +#define VPEC_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL +//VPEC_FREEZE +#define VPEC_FREEZE__PREEMPT__SHIFT 0x0 +#define VPEC_FREEZE__FREEZE__SHIFT 0x4 +#define VPEC_FREEZE__FROZEN__SHIFT 0x5 +#define VPEC_FREEZE__F32_FREEZE__SHIFT 0x6 +#define VPEC_FREEZE__PREEMPT_MASK 0x00000001L +#define VPEC_FREEZE__FREEZE_MASK 0x00000010L +#define VPEC_FREEZE__FROZEN_MASK 0x00000020L +#define VPEC_FREEZE__F32_FREEZE_MASK 0x00000040L +//VPEC_CE_CTRL +#define VPEC_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define VPEC_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define VPEC_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define VPEC_CE_CTRL__RESERVED__SHIFT 0x8 +#define VPEC_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define VPEC_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define VPEC_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define VPEC_CE_CTRL__RESERVED_MASK 0xFFFFFF00L +//VPEC_RELAX_ORDERING_LUT +#define VPEC_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define VPEC_RELAX_ORDERING_LUT__VPE__SHIFT 0x1 +#define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2__SHIFT 0x2 +#define VPEC_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define VPEC_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define VPEC_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define VPEC_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define VPEC_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define VPEC_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define VPEC_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11__SHIFT 0xb +#define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12__SHIFT 0xc +#define VPEC_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define VPEC_RELAX_ORDERING_LUT__NATIVE_FENCE__SHIFT 0xe +#define VPEC_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xf +#define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define VPEC_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29__SHIFT 0x1d +#define VPEC_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define VPEC_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define VPEC_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define VPEC_RELAX_ORDERING_LUT__VPE_MASK 0x00000002L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2_MASK 0x00000004L +#define VPEC_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define VPEC_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define VPEC_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define VPEC_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define VPEC_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define VPEC_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define VPEC_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11_MASK 0x00000800L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12_MASK 0x00001000L +#define VPEC_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define VPEC_RELAX_ORDERING_LUT__NATIVE_FENCE_MASK 0x00004000L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FF8000L +#define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define VPEC_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29_MASK 0x20000000L +#define VPEC_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define VPEC_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//VPEC_CREDIT_CNTL +#define VPEC_CREDIT_CNTL__DRM_CREDIT__SHIFT 0x0 +#define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define VPEC_CREDIT_CNTL__DRM_CREDIT_MASK 0x0000007FL +#define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//VPEC_SCRATCH_RAM_DATA +#define VPEC_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define VPEC_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//VPEC_SCRATCH_RAM_ADDR +#define VPEC_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define VPEC_SCRATCH_RAM_ADDR__ADDR_MASK 0x000000FFL +//VPEC_QUEUE_RESET_REQ +#define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 +#define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 +#define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 +#define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 +#define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 +#define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 +#define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 +#define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 +#define VPEC_QUEUE_RESET_REQ__RESERVED__SHIFT 0x8 +#define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L +#define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L +#define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L +#define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L +#define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L +#define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L +#define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L +#define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L +#define VPEC_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFF00L +//VPEC_MAILBOX0 +#define VPEC_MAILBOX0__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX0__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX1 +#define VPEC_MAILBOX1__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX1__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX2 +#define VPEC_MAILBOX2__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX2__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX3 +#define VPEC_MAILBOX3__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX3__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX4 +#define VPEC_MAILBOX4__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX4__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX5 +#define VPEC_MAILBOX5__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX5__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX6 +#define VPEC_MAILBOX6__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX6__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX7 +#define VPEC_MAILBOX7__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX7__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX8 +#define VPEC_MAILBOX8__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX8__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX9 +#define VPEC_MAILBOX9__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX9__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX10 +#define VPEC_MAILBOX10__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX10__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX11 +#define VPEC_MAILBOX11__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX11__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX12 +#define VPEC_MAILBOX12__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX12__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX13 +#define VPEC_MAILBOX13__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX13__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX14 +#define VPEC_MAILBOX14__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX14__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX15 +#define VPEC_MAILBOX15__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX15__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY0 +#define VPEC_PUB_DUMMY0__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY0__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY1 +#define VPEC_PUB_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY2 +#define VPEC_PUB_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY3 +#define VPEC_PUB_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY4 +#define VPEC_PUB_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY5 +#define VPEC_PUB_DUMMY5__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY5__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY6 +#define VPEC_PUB_DUMMY6__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY6__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY7 +#define VPEC_PUB_DUMMY7__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY7__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY8 +#define VPEC_PUB_DUMMY8__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY8__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY9 +#define VPEC_PUB_DUMMY9__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY9__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY10 +#define VPEC_PUB_DUMMY10__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY10__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY11 +#define VPEC_PUB_DUMMY11__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY11__VALUE_MASK 0xFFFFFFFFL +//VPEC_UCODE1_CHECKSUM +#define VPEC_UCODE1_CHECKSUM__DATA__SHIFT 0x0 +#define VPEC_UCODE1_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//VPEC_VERSION +#define VPEC_VERSION__MINVER__SHIFT 0x0 +#define VPEC_VERSION__MAJVER__SHIFT 0x8 +#define VPEC_VERSION__REV__SHIFT 0x10 +#define VPEC_VERSION__MINVER_MASK 0x0000007FL +#define VPEC_VERSION__MAJVER_MASK 0x00007F00L +#define VPEC_VERSION__REV_MASK 0x003F0000L +//VPEC_UCODE_CHECKSUM +#define VPEC_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define VPEC_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//VPEC_RB_RPTR_FETCH +#define VPEC_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//VPEC_RB_RPTR_FETCH_HI +#define VPEC_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define VPEC_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_IB_OFFSET_FETCH +#define VPEC_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//VPEC_CMDIB_OFFSET_FETCH +#define VPEC_CMDIB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_CMDIB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//VPEC_3DLUTIB_OFFSET_FETCH +#define VPEC_3DLUTIB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_3DLUTIB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//VPEC_ATOMIC_PREOP_LO +#define VPEC_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define VPEC_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//VPEC_ATOMIC_PREOP_HI +#define VPEC_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define VPEC_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//VPEC_CE_BUSY +#define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY__SHIFT 0x0 +#define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY__SHIFT 0x1 +#define VPEC_CE_BUSY__CE_IP_PIPE2_BUSY__SHIFT 0x2 +#define VPEC_CE_BUSY__CE_IP_PIPE3_BUSY__SHIFT 0x3 +#define VPEC_CE_BUSY__CE_IP_PIPE4_BUSY__SHIFT 0x4 +#define VPEC_CE_BUSY__CE_IP_PIPE5_BUSY__SHIFT 0x5 +#define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY__SHIFT 0x10 +#define VPEC_CE_BUSY__CE_OP_PIPE1_BUSY__SHIFT 0x11 +#define VPEC_CE_BUSY__CE_OP_PIPE2_BUSY__SHIFT 0x12 +#define VPEC_CE_BUSY__CE_OP_PIPE3_BUSY__SHIFT 0x13 +#define VPEC_CE_BUSY__CE_OP_PIPE4_BUSY__SHIFT 0x14 +#define VPEC_CE_BUSY__CE_OP_PIPE5_BUSY__SHIFT 0x15 +#define VPEC_CE_BUSY__CE_OP_PIPE6_BUSY__SHIFT 0x16 +#define VPEC_CE_BUSY__CE_OP_PIPE7_BUSY__SHIFT 0x17 +#define VPEC_CE_BUSY__CE_OP_PIPE8_BUSY__SHIFT 0x18 +#define VPEC_CE_BUSY__CE_OP_PIPE9_BUSY__SHIFT 0x19 +#define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY_MASK 0x00000001L +#define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY_MASK 0x00000002L +#define VPEC_CE_BUSY__CE_IP_PIPE2_BUSY_MASK 0x00000004L +#define VPEC_CE_BUSY__CE_IP_PIPE3_BUSY_MASK 0x00000008L +#define VPEC_CE_BUSY__CE_IP_PIPE4_BUSY_MASK 0x00000010L +#define VPEC_CE_BUSY__CE_IP_PIPE5_BUSY_MASK 0x00000020L +#define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY_MASK 0x00010000L +#define VPEC_CE_BUSY__CE_OP_PIPE1_BUSY_MASK 0x00020000L +#define VPEC_CE_BUSY__CE_OP_PIPE2_BUSY_MASK 0x00040000L +#define VPEC_CE_BUSY__CE_OP_PIPE3_BUSY_MASK 0x00080000L +#define VPEC_CE_BUSY__CE_OP_PIPE4_BUSY_MASK 0x00100000L +#define VPEC_CE_BUSY__CE_OP_PIPE5_BUSY_MASK 0x00200000L +#define VPEC_CE_BUSY__CE_OP_PIPE6_BUSY_MASK 0x00400000L +#define VPEC_CE_BUSY__CE_OP_PIPE7_BUSY_MASK 0x00800000L +#define VPEC_CE_BUSY__CE_OP_PIPE8_BUSY_MASK 0x01000000L +#define VPEC_CE_BUSY__CE_OP_PIPE9_BUSY_MASK 0x02000000L +//VPEC_F32_COUNTER +#define VPEC_F32_COUNTER__VALUE__SHIFT 0x0 +#define VPEC_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//VPEC_HOLE_ADDR_LO +#define VPEC_HOLE_ADDR_LO__VALUE__SHIFT 0x0 +#define VPEC_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL +//VPEC_HOLE_ADDR_HI +#define VPEC_HOLE_ADDR_HI__VALUE__SHIFT 0x0 +#define VPEC_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL +//VPEC_ERROR_LOG +#define VPEC_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define VPEC_ERROR_LOG__STATUS__SHIFT 0x10 +#define VPEC_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define VPEC_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//VPEC_INT_STATUS +#define VPEC_INT_STATUS__DATA__SHIFT 0x0 +#define VPEC_INT_STATUS__DATA_MASK 0xFFFFFFFFL +//VPEC_STATUS +#define VPEC_STATUS__IDLE__SHIFT 0x0 +#define VPEC_STATUS__REG_IDLE__SHIFT 0x1 +#define VPEC_STATUS__RB_EMPTY__SHIFT 0x2 +#define VPEC_STATUS__RB_FULL__SHIFT 0x3 +#define VPEC_STATUS__RB_CMD_IDLE__SHIFT 0x4 +#define VPEC_STATUS__RB_CMD_FULL__SHIFT 0x5 +#define VPEC_STATUS__IB_CMD_IDLE__SHIFT 0x6 +#define VPEC_STATUS__IB_CMD_FULL__SHIFT 0x7 +#define VPEC_STATUS__BLOCK_IDLE__SHIFT 0x8 +#define VPEC_STATUS__INSIDE_VPEP_CONFIG__SHIFT 0x9 +#define VPEC_STATUS__EX_IDLE__SHIFT 0xa +#define VPEC_STATUS__INSIDE_VPEP_3DLUT_CONFIG__SHIFT 0xb +#define VPEC_STATUS__PACKET_READY__SHIFT 0xc +#define VPEC_STATUS__MC_WR_IDLE__SHIFT 0xd +#define VPEC_STATUS__SRBM_IDLE__SHIFT 0xe +#define VPEC_STATUS__CONTEXT_EMPTY__SHIFT 0xf +#define VPEC_STATUS__INSIDE_IB__SHIFT 0x10 +#define VPEC_STATUS__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define VPEC_STATUS__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define VPEC_STATUS__MC_RD_IDLE__SHIFT 0x13 +#define VPEC_STATUS__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define VPEC_STATUS__MC_RD_RET_STALL__SHIFT 0x15 +#define VPEC_STATUS__LUTIB_CMD_IDLE__SHIFT 0x16 +#define VPEC_STATUS__LUTIB_CMD_FULL__SHIFT 0x17 +#define VPEC_STATUS__CMDIB_MC_RREQ_IDLE__SHIFT 0x18 +#define VPEC_STATUS__PREV_CMD_IDLE__SHIFT 0x19 +#define VPEC_STATUS__CMDIB_CMD_IDLE__SHIFT 0x1a +#define VPEC_STATUS__CMDIB_CMD_FULL__SHIFT 0x1b +#define VPEC_STATUS__RESERVED_29_28__SHIFT 0x1c +#define VPEC_STATUS__INT_IDLE__SHIFT 0x1e +#define VPEC_STATUS__INT_REQ_STALL__SHIFT 0x1f +#define VPEC_STATUS__IDLE_MASK 0x00000001L +#define VPEC_STATUS__REG_IDLE_MASK 0x00000002L +#define VPEC_STATUS__RB_EMPTY_MASK 0x00000004L +#define VPEC_STATUS__RB_FULL_MASK 0x00000008L +#define VPEC_STATUS__RB_CMD_IDLE_MASK 0x00000010L +#define VPEC_STATUS__RB_CMD_FULL_MASK 0x00000020L +#define VPEC_STATUS__IB_CMD_IDLE_MASK 0x00000040L +#define VPEC_STATUS__IB_CMD_FULL_MASK 0x00000080L +#define VPEC_STATUS__BLOCK_IDLE_MASK 0x00000100L +#define VPEC_STATUS__INSIDE_VPEP_CONFIG_MASK 0x00000200L +#define VPEC_STATUS__EX_IDLE_MASK 0x00000400L +#define VPEC_STATUS__INSIDE_VPEP_3DLUT_CONFIG_MASK 0x00000800L +#define VPEC_STATUS__PACKET_READY_MASK 0x00001000L +#define VPEC_STATUS__MC_WR_IDLE_MASK 0x00002000L +#define VPEC_STATUS__SRBM_IDLE_MASK 0x00004000L +#define VPEC_STATUS__CONTEXT_EMPTY_MASK 0x00008000L +#define VPEC_STATUS__INSIDE_IB_MASK 0x00010000L +#define VPEC_STATUS__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define VPEC_STATUS__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define VPEC_STATUS__MC_RD_IDLE_MASK 0x00080000L +#define VPEC_STATUS__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define VPEC_STATUS__MC_RD_RET_STALL_MASK 0x00200000L +#define VPEC_STATUS__LUTIB_CMD_IDLE_MASK 0x00400000L +#define VPEC_STATUS__LUTIB_CMD_FULL_MASK 0x00800000L +#define VPEC_STATUS__CMDIB_MC_RREQ_IDLE_MASK 0x01000000L +#define VPEC_STATUS__PREV_CMD_IDLE_MASK 0x02000000L +#define VPEC_STATUS__CMDIB_CMD_IDLE_MASK 0x04000000L +#define VPEC_STATUS__CMDIB_CMD_FULL_MASK 0x08000000L +#define VPEC_STATUS__RESERVED_29_28_MASK 0x30000000L +#define VPEC_STATUS__INT_IDLE_MASK 0x40000000L +#define VPEC_STATUS__INT_REQ_STALL_MASK 0x80000000L +//VPEC_STATUS1 +#define VPEC_STATUS1__EX_START__SHIFT 0x0 +#define VPEC_STATUS1__VPEC_IDLE__SHIFT 0x1 +#define VPEC_STATUS1__RESERVED_31_2__SHIFT 0x2 +#define VPEC_STATUS1__EX_START_MASK 0x00000001L +#define VPEC_STATUS1__VPEC_IDLE_MASK 0x00000002L +#define VPEC_STATUS1__RESERVED_31_2_MASK 0xFFFFFFFCL +//VPEC_STATUS2 +#define VPEC_STATUS2__ID__SHIFT 0x0 +#define VPEC_STATUS2__TH0F32_INSTR_PTR__SHIFT 0x2 +#define VPEC_STATUS2__CMD_OP__SHIFT 0x10 +#define VPEC_STATUS2__ID_MASK 0x00000003L +#define VPEC_STATUS2__TH0F32_INSTR_PTR_MASK 0x0000FFFCL +#define VPEC_STATUS2__CMD_OP_MASK 0xFFFF0000L +//VPEC_STATUS3 +#define VPEC_STATUS3__RESERVED_15_0__SHIFT 0x0 +#define VPEC_STATUS3__RESERVED_19_16__SHIFT 0x10 +#define VPEC_STATUS3__EXCEPTION_IDLE__SHIFT 0x14 +#define VPEC_STATUS3__RESERVED_21_21__SHIFT 0x15 +#define VPEC_STATUS3__RESERVED_22_22__SHIFT 0x16 +#define VPEC_STATUS3__RESERVED_23_23__SHIFT 0x17 +#define VPEC_STATUS3__RESERVED_24_24__SHIFT 0x18 +#define VPEC_STATUS3__RESERVED_25_25__SHIFT 0x19 +#define VPEC_STATUS3__INT_QUEUE_ID__SHIFT 0x1a +#define VPEC_STATUS3__RESERVED_31_30__SHIFT 0x1e +#define VPEC_STATUS3__RESERVED_15_0_MASK 0x0000FFFFL +#define VPEC_STATUS3__RESERVED_19_16_MASK 0x000F0000L +#define VPEC_STATUS3__EXCEPTION_IDLE_MASK 0x00100000L +#define VPEC_STATUS3__RESERVED_21_21_MASK 0x00200000L +#define VPEC_STATUS3__RESERVED_22_22_MASK 0x00400000L +#define VPEC_STATUS3__RESERVED_23_23_MASK 0x00800000L +#define VPEC_STATUS3__RESERVED_24_24_MASK 0x01000000L +#define VPEC_STATUS3__RESERVED_25_25_MASK 0x02000000L +#define VPEC_STATUS3__INT_QUEUE_ID_MASK 0x3C000000L +#define VPEC_STATUS3__RESERVED_31_30_MASK 0xC0000000L +//VPEC_STATUS4 +#define VPEC_STATUS4__IDLE__SHIFT 0x0 +#define VPEC_STATUS4__IH_OUTSTANDING__SHIFT 0x2 +#define VPEC_STATUS4__RESERVED_3_3__SHIFT 0x3 +#define VPEC_STATUS4__CH_RD_OUTSTANDING__SHIFT 0x4 +#define VPEC_STATUS4__CH_WR_OUTSTANDING__SHIFT 0x5 +#define VPEC_STATUS4__RESERVED_6_6__SHIFT 0x6 +#define VPEC_STATUS4__RESERVED_7_7__SHIFT 0x7 +#define VPEC_STATUS4__RESERVED_8_8__SHIFT 0x8 +#define VPEC_STATUS4__RESERVED_9_9__SHIFT 0x9 +#define VPEC_STATUS4__REG_POLLING__SHIFT 0xa +#define VPEC_STATUS4__MEM_POLLING__SHIFT 0xb +#define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING__SHIFT 0xc +#define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING__SHIFT 0xd +#define VPEC_STATUS4__RESERVED_15_14__SHIFT 0xe +#define VPEC_STATUS4__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define VPEC_STATUS4__RESERVED_27_20__SHIFT 0x14 +#define VPEC_STATUS4__IDLE_MASK 0x00000001L +#define VPEC_STATUS4__IH_OUTSTANDING_MASK 0x00000004L +#define VPEC_STATUS4__RESERVED_3_3_MASK 0x00000008L +#define VPEC_STATUS4__CH_RD_OUTSTANDING_MASK 0x00000010L +#define VPEC_STATUS4__CH_WR_OUTSTANDING_MASK 0x00000020L +#define VPEC_STATUS4__RESERVED_6_6_MASK 0x00000040L +#define VPEC_STATUS4__RESERVED_7_7_MASK 0x00000080L +#define VPEC_STATUS4__RESERVED_8_8_MASK 0x00000100L +#define VPEC_STATUS4__RESERVED_9_9_MASK 0x00000200L +#define VPEC_STATUS4__REG_POLLING_MASK 0x00000400L +#define VPEC_STATUS4__MEM_POLLING_MASK 0x00000800L +#define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING_MASK 0x00001000L +#define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING_MASK 0x00002000L +#define VPEC_STATUS4__RESERVED_15_14_MASK 0x0000C000L +#define VPEC_STATUS4__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define VPEC_STATUS4__RESERVED_27_20_MASK 0x0FF00000L +//VPEC_STATUS5 +#define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 +#define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 +#define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 +#define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 +#define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 +#define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 +#define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 +#define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 +#define VPEC_STATUS5__RESERVED_27_16__SHIFT 0x10 +#define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L +#define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L +#define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L +#define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L +#define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L +#define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L +#define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L +#define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L +#define VPEC_STATUS5__RESERVED_27_16_MASK 0x000F0000L +//VPEC_STATUS6 +#define VPEC_STATUS6__ID__SHIFT 0x0 +#define VPEC_STATUS6__TH1F32_INSTR_PTR__SHIFT 0x2 +#define VPEC_STATUS6__TH1_EXCEPTION__SHIFT 0x10 +#define VPEC_STATUS6__ID_MASK 0x00000003L +#define VPEC_STATUS6__TH1F32_INSTR_PTR_MASK 0x0000FFFCL +#define VPEC_STATUS6__TH1_EXCEPTION_MASK 0xFFFF0000L +//VPEC_STATUS7 +#define VPEC_STATUS7__TH0_DBG_STATUS__SHIFT 0x0 +#define VPEC_STATUS7__TH0_DBG_STATUS_MASK 0xFFFFFFFFL +//VPEC_STATUS8 +#define VPEC_STATUS8__CE_IP0_WREQ_IDLE__SHIFT 0x0 +#define VPEC_STATUS8__CE_IP0_WR_IDLE__SHIFT 0x1 +#define VPEC_STATUS8__CE_IP0_SPLIT_RD_IDLE__SHIFT 0x2 +#define VPEC_STATUS8__CE_IP0_SPLIT_WR_IDLE__SHIFT 0x3 +#define VPEC_STATUS8__CE_IP0_RREQ_IDLE__SHIFT 0x4 +#define VPEC_STATUS8__CE_IP0_OUT_IDLE__SHIFT 0x5 +#define VPEC_STATUS8__CE_IP0_IN_IDLE__SHIFT 0x6 +#define VPEC_STATUS8__CE_IP0_DST_IDLE__SHIFT 0x7 +#define VPEC_STATUS8__CE_IP0_CMD_IDLE__SHIFT 0x8 +#define VPEC_STATUS8__CE_IP1_WREQ_IDLE__SHIFT 0x9 +#define VPEC_STATUS8__CE_IP1_WR_IDLE__SHIFT 0xa +#define VPEC_STATUS8__CE_IP1_SPLIT_RD_IDLE__SHIFT 0xb +#define VPEC_STATUS8__CE_IP1_SPLIT_WR_IDLE__SHIFT 0xc +#define VPEC_STATUS8__CE_IP1_RREQ_IDLE__SHIFT 0xd +#define VPEC_STATUS8__CE_IP1_OUT_IDLE__SHIFT 0xe +#define VPEC_STATUS8__CE_IP1_IN_IDLE__SHIFT 0xf +#define VPEC_STATUS8__CE_IP1_DST_IDLE__SHIFT 0x10 +#define VPEC_STATUS8__CE_IP1_CMD_IDLE__SHIFT 0x11 +#define VPEC_STATUS8__CE_IP0_AFIFO_FULL__SHIFT 0x12 +#define VPEC_STATUS8__CE_IP0_CMD_INFO_FULL__SHIFT 0x13 +#define VPEC_STATUS8__CE_IP0_CMD_INFO1_FULL__SHIFT 0x14 +#define VPEC_STATUS8__CE_IP1_AFIFO_FULL__SHIFT 0x15 +#define VPEC_STATUS8__CE_IP1_CMD_INFO_FULL__SHIFT 0x16 +#define VPEC_STATUS8__CE_IP1_CMD_INFO1_FULL__SHIFT 0x17 +#define VPEC_STATUS8__CE_IP0_WR_STALL__SHIFT 0x18 +#define VPEC_STATUS8__CE_IP1_WR_STALL__SHIFT 0x19 +#define VPEC_STATUS8__CE_IP0_RD_STALL__SHIFT 0x1a +#define VPEC_STATUS8__CE_IP1_RD_STALL__SHIFT 0x1b +#define VPEC_STATUS8__RESERVED_31_28__SHIFT 0x1c +#define VPEC_STATUS8__CE_IP0_WREQ_IDLE_MASK 0x00000001L +#define VPEC_STATUS8__CE_IP0_WR_IDLE_MASK 0x00000002L +#define VPEC_STATUS8__CE_IP0_SPLIT_RD_IDLE_MASK 0x00000004L +#define VPEC_STATUS8__CE_IP0_SPLIT_WR_IDLE_MASK 0x00000008L +#define VPEC_STATUS8__CE_IP0_RREQ_IDLE_MASK 0x00000010L +#define VPEC_STATUS8__CE_IP0_OUT_IDLE_MASK 0x00000020L +#define VPEC_STATUS8__CE_IP0_IN_IDLE_MASK 0x00000040L +#define VPEC_STATUS8__CE_IP0_DST_IDLE_MASK 0x00000080L +#define VPEC_STATUS8__CE_IP0_CMD_IDLE_MASK 0x00000100L +#define VPEC_STATUS8__CE_IP1_WREQ_IDLE_MASK 0x00000200L +#define VPEC_STATUS8__CE_IP1_WR_IDLE_MASK 0x00000400L +#define VPEC_STATUS8__CE_IP1_SPLIT_RD_IDLE_MASK 0x00000800L +#define VPEC_STATUS8__CE_IP1_SPLIT_WR_IDLE_MASK 0x00001000L +#define VPEC_STATUS8__CE_IP1_RREQ_IDLE_MASK 0x00002000L +#define VPEC_STATUS8__CE_IP1_OUT_IDLE_MASK 0x00004000L +#define VPEC_STATUS8__CE_IP1_IN_IDLE_MASK 0x00008000L +#define VPEC_STATUS8__CE_IP1_DST_IDLE_MASK 0x00010000L +#define VPEC_STATUS8__CE_IP1_CMD_IDLE_MASK 0x00020000L +#define VPEC_STATUS8__CE_IP0_AFIFO_FULL_MASK 0x00040000L +#define VPEC_STATUS8__CE_IP0_CMD_INFO_FULL_MASK 0x00080000L +#define VPEC_STATUS8__CE_IP0_CMD_INFO1_FULL_MASK 0x00100000L +#define VPEC_STATUS8__CE_IP1_AFIFO_FULL_MASK 0x00200000L +#define VPEC_STATUS8__CE_IP1_CMD_INFO_FULL_MASK 0x00400000L +#define VPEC_STATUS8__CE_IP1_CMD_INFO1_FULL_MASK 0x00800000L +#define VPEC_STATUS8__CE_IP0_WR_STALL_MASK 0x01000000L +#define VPEC_STATUS8__CE_IP1_WR_STALL_MASK 0x02000000L +#define VPEC_STATUS8__CE_IP0_RD_STALL_MASK 0x04000000L +#define VPEC_STATUS8__CE_IP1_RD_STALL_MASK 0x08000000L +#define VPEC_STATUS8__RESERVED_31_28_MASK 0xF0000000L +//VPEC_STATUS9 +#define VPEC_STATUS9__CE_IP2_WREQ_IDLE__SHIFT 0x0 +#define VPEC_STATUS9__CE_IP2_WR_IDLE__SHIFT 0x1 +#define VPEC_STATUS9__CE_IP2_SPLIT_RD_IDLE__SHIFT 0x2 +#define VPEC_STATUS9__CE_IP2_SPLIT_WR_IDLE__SHIFT 0x3 +#define VPEC_STATUS9__CE_IP2_RREQ_IDLE__SHIFT 0x4 +#define VPEC_STATUS9__CE_IP2_OUT_IDLE__SHIFT 0x5 +#define VPEC_STATUS9__CE_IP2_IN_IDLE__SHIFT 0x6 +#define VPEC_STATUS9__CE_IP2_DST_IDLE__SHIFT 0x7 +#define VPEC_STATUS9__CE_IP2_CMD_IDLE__SHIFT 0x8 +#define VPEC_STATUS9__CE_IP3_WREQ_IDLE__SHIFT 0x9 +#define VPEC_STATUS9__CE_IP3_WR_IDLE__SHIFT 0xa +#define VPEC_STATUS9__CE_IP3_SPLIT_RD_IDLE__SHIFT 0xb +#define VPEC_STATUS9__CE_IP3_SPLIT_WR_IDLE__SHIFT 0xc +#define VPEC_STATUS9__CE_IP3_RREQ_IDLE__SHIFT 0xd +#define VPEC_STATUS9__CE_IP3_OUT_IDLE__SHIFT 0xe +#define VPEC_STATUS9__CE_IP3_IN_IDLE__SHIFT 0xf +#define VPEC_STATUS9__CE_IP3_DST_IDLE__SHIFT 0x10 +#define VPEC_STATUS9__CE_IP3_CMD_IDLE__SHIFT 0x11 +#define VPEC_STATUS9__CE_IP2_AFIFO_FULL__SHIFT 0x12 +#define VPEC_STATUS9__CE_IP2_CMD_INFO_FULL__SHIFT 0x13 +#define VPEC_STATUS9__CE_IP2_CMD_INFO1_FULL__SHIFT 0x14 +#define VPEC_STATUS9__CE_IP3_AFIFO_FULL__SHIFT 0x15 +#define VPEC_STATUS9__CE_IP3_CMD_INFO_FULL__SHIFT 0x16 +#define VPEC_STATUS9__CE_IP3_CMD_INFO1_FULL__SHIFT 0x17 +#define VPEC_STATUS9__CE_IP2_WR_STALL__SHIFT 0x18 +#define VPEC_STATUS9__CE_IP3_WR_STALL__SHIFT 0x19 +#define VPEC_STATUS9__CE_IP2_RD_STALL__SHIFT 0x1a +#define VPEC_STATUS9__CE_IP3_RD_STALL__SHIFT 0x1b +#define VPEC_STATUS9__RESERVED_31_28__SHIFT 0x1c +#define VPEC_STATUS9__CE_IP2_WREQ_IDLE_MASK 0x00000001L +#define VPEC_STATUS9__CE_IP2_WR_IDLE_MASK 0x00000002L +#define VPEC_STATUS9__CE_IP2_SPLIT_RD_IDLE_MASK 0x00000004L +#define VPEC_STATUS9__CE_IP2_SPLIT_WR_IDLE_MASK 0x00000008L +#define VPEC_STATUS9__CE_IP2_RREQ_IDLE_MASK 0x00000010L +#define VPEC_STATUS9__CE_IP2_OUT_IDLE_MASK 0x00000020L +#define VPEC_STATUS9__CE_IP2_IN_IDLE_MASK 0x00000040L +#define VPEC_STATUS9__CE_IP2_DST_IDLE_MASK 0x00000080L +#define VPEC_STATUS9__CE_IP2_CMD_IDLE_MASK 0x00000100L +#define VPEC_STATUS9__CE_IP3_WREQ_IDLE_MASK 0x00000200L +#define VPEC_STATUS9__CE_IP3_WR_IDLE_MASK 0x00000400L +#define VPEC_STATUS9__CE_IP3_SPLIT_RD_IDLE_MASK 0x00000800L +#define VPEC_STATUS9__CE_IP3_SPLIT_WR_IDLE_MASK 0x00001000L +#define VPEC_STATUS9__CE_IP3_RREQ_IDLE_MASK 0x00002000L +#define VPEC_STATUS9__CE_IP3_OUT_IDLE_MASK 0x00004000L +#define VPEC_STATUS9__CE_IP3_IN_IDLE_MASK 0x00008000L +#define VPEC_STATUS9__CE_IP3_DST_IDLE_MASK 0x00010000L +#define VPEC_STATUS9__CE_IP3_CMD_IDLE_MASK 0x00020000L +#define VPEC_STATUS9__CE_IP2_AFIFO_FULL_MASK 0x00040000L +#define VPEC_STATUS9__CE_IP2_CMD_INFO_FULL_MASK 0x00080000L +#define VPEC_STATUS9__CE_IP2_CMD_INFO1_FULL_MASK 0x00100000L +#define VPEC_STATUS9__CE_IP3_AFIFO_FULL_MASK 0x00200000L +#define VPEC_STATUS9__CE_IP3_CMD_INFO_FULL_MASK 0x00400000L +#define VPEC_STATUS9__CE_IP3_CMD_INFO1_FULL_MASK 0x00800000L +#define VPEC_STATUS9__CE_IP2_WR_STALL_MASK 0x01000000L +#define VPEC_STATUS9__CE_IP3_WR_STALL_MASK 0x02000000L +#define VPEC_STATUS9__CE_IP2_RD_STALL_MASK 0x04000000L +#define VPEC_STATUS9__CE_IP3_RD_STALL_MASK 0x08000000L +#define VPEC_STATUS9__RESERVED_31_28_MASK 0xF0000000L +//VPEC_STATUS10 +#define VPEC_STATUS10__CE_OP0_WR_IDLE__SHIFT 0x0 +#define VPEC_STATUS10__CE_OP0_CMD_IDLE__SHIFT 0x1 +#define VPEC_STATUS10__CE_OP1_WR_IDLE__SHIFT 0x2 +#define VPEC_STATUS10__CE_OP1_CMD_IDLE__SHIFT 0x3 +#define VPEC_STATUS10__CE_OP2_WR_IDLE__SHIFT 0x4 +#define VPEC_STATUS10__CE_OP2_CMD_IDLE__SHIFT 0x5 +#define VPEC_STATUS10__CE_OP3_WR_IDLE__SHIFT 0x6 +#define VPEC_STATUS10__CE_OP3_CMD_IDLE__SHIFT 0x7 +#define VPEC_STATUS10__CE_OP4_WR_IDLE__SHIFT 0x8 +#define VPEC_STATUS10__CE_OP4_CMD_IDLE__SHIFT 0x9 +#define VPEC_STATUS10__CE_OP5_WR_IDLE__SHIFT 0xa +#define VPEC_STATUS10__CE_OP5_CMD_IDLE__SHIFT 0xb +#define VPEC_STATUS10__CE_OP6_WR_IDLE__SHIFT 0xc +#define VPEC_STATUS10__CE_OP6_CMD_IDLE__SHIFT 0xd +#define VPEC_STATUS10__CE_OP7_WR_IDLE__SHIFT 0xe +#define VPEC_STATUS10__CE_OP7_CMD_IDLE__SHIFT 0xf +#define VPEC_STATUS10__CE_OP8_WR_IDLE__SHIFT 0x10 +#define VPEC_STATUS10__CE_OP8_CMD_IDLE__SHIFT 0x11 +#define VPEC_STATUS10__CE_OP9_WR_IDLE__SHIFT 0x12 +#define VPEC_STATUS10__CE_OP9_CMD_IDLE__SHIFT 0x13 +#define VPEC_STATUS10__RESERVED_31_28__SHIFT 0x1c +#define VPEC_STATUS10__CE_OP0_WR_IDLE_MASK 0x00000001L +#define VPEC_STATUS10__CE_OP0_CMD_IDLE_MASK 0x00000002L +#define VPEC_STATUS10__CE_OP1_WR_IDLE_MASK 0x00000004L +#define VPEC_STATUS10__CE_OP1_CMD_IDLE_MASK 0x00000008L +#define VPEC_STATUS10__CE_OP2_WR_IDLE_MASK 0x00000010L +#define VPEC_STATUS10__CE_OP2_CMD_IDLE_MASK 0x00000020L +#define VPEC_STATUS10__CE_OP3_WR_IDLE_MASK 0x00000040L +#define VPEC_STATUS10__CE_OP3_CMD_IDLE_MASK 0x00000080L +#define VPEC_STATUS10__CE_OP4_WR_IDLE_MASK 0x00000100L +#define VPEC_STATUS10__CE_OP4_CMD_IDLE_MASK 0x00000200L +#define VPEC_STATUS10__CE_OP5_WR_IDLE_MASK 0x00000400L +#define VPEC_STATUS10__CE_OP5_CMD_IDLE_MASK 0x00000800L +#define VPEC_STATUS10__CE_OP6_WR_IDLE_MASK 0x00001000L +#define VPEC_STATUS10__CE_OP6_CMD_IDLE_MASK 0x00002000L +#define VPEC_STATUS10__CE_OP7_WR_IDLE_MASK 0x00004000L +#define VPEC_STATUS10__CE_OP7_CMD_IDLE_MASK 0x00008000L +#define VPEC_STATUS10__CE_OP8_WR_IDLE_MASK 0x00010000L +#define VPEC_STATUS10__CE_OP8_CMD_IDLE_MASK 0x00020000L +#define VPEC_STATUS10__CE_OP9_WR_IDLE_MASK 0x00040000L +#define VPEC_STATUS10__CE_OP9_CMD_IDLE_MASK 0x00080000L +#define VPEC_STATUS10__RESERVED_31_28_MASK 0xF0000000L +//VPEC_STATUS_DCC +#define VPEC_STATUS_DCC__CE_IP0_MRQ_IDLE__SHIFT 0x0 +#define VPEC_STATUS_DCC__CE_IP0_DCCP_IDLE__SHIFT 0x1 +#define VPEC_STATUS_DCC__CE_IP0_DCC_RET_IDLE__SHIFT 0x2 +#define VPEC_STATUS_DCC__CE_IP1_MRQ_IDLE__SHIFT 0x3 +#define VPEC_STATUS_DCC__CE_IP1_DCCP_IDLE__SHIFT 0x4 +#define VPEC_STATUS_DCC__CE_IP1_DCC_RET_IDLE__SHIFT 0x5 +#define VPEC_STATUS_DCC__CE_IP2_MRQ_IDLE__SHIFT 0x6 +#define VPEC_STATUS_DCC__CE_IP2_DCCP_IDLE__SHIFT 0x7 +#define VPEC_STATUS_DCC__CE_IP2_DCC_RET_IDLE__SHIFT 0x8 +#define VPEC_STATUS_DCC__CE_IP3_MRQ_IDLE__SHIFT 0x9 +#define VPEC_STATUS_DCC__CE_IP3_DCCP_IDLE__SHIFT 0xa +#define VPEC_STATUS_DCC__CE_IP3_DCC_RET_IDLE__SHIFT 0xb +#define VPEC_STATUS_DCC__CE_IP4_MRQ_IDLE__SHIFT 0xc +#define VPEC_STATUS_DCC__CE_IP4_DCCP_IDLE__SHIFT 0xd +#define VPEC_STATUS_DCC__CE_IP4_DCC_RET_IDLE__SHIFT 0xe +#define VPEC_STATUS_DCC__CE_IP5_MRQ_IDLE__SHIFT 0xf +#define VPEC_STATUS_DCC__CE_IP5_DCCP_IDLE__SHIFT 0x10 +#define VPEC_STATUS_DCC__CE_IP5_DCC_RET_IDLE__SHIFT 0x11 +#define VPEC_STATUS_DCC__RESERVED_31_18__SHIFT 0x12 +#define VPEC_STATUS_DCC__CE_IP0_MRQ_IDLE_MASK 0x00000001L +#define VPEC_STATUS_DCC__CE_IP0_DCCP_IDLE_MASK 0x00000002L +#define VPEC_STATUS_DCC__CE_IP0_DCC_RET_IDLE_MASK 0x00000004L +#define VPEC_STATUS_DCC__CE_IP1_MRQ_IDLE_MASK 0x00000008L +#define VPEC_STATUS_DCC__CE_IP1_DCCP_IDLE_MASK 0x00000010L +#define VPEC_STATUS_DCC__CE_IP1_DCC_RET_IDLE_MASK 0x00000020L +#define VPEC_STATUS_DCC__CE_IP2_MRQ_IDLE_MASK 0x00000040L +#define VPEC_STATUS_DCC__CE_IP2_DCCP_IDLE_MASK 0x00000080L +#define VPEC_STATUS_DCC__CE_IP2_DCC_RET_IDLE_MASK 0x00000100L +#define VPEC_STATUS_DCC__CE_IP3_MRQ_IDLE_MASK 0x00000200L +#define VPEC_STATUS_DCC__CE_IP3_DCCP_IDLE_MASK 0x00000400L +#define VPEC_STATUS_DCC__CE_IP3_DCC_RET_IDLE_MASK 0x00000800L +#define VPEC_STATUS_DCC__CE_IP4_MRQ_IDLE_MASK 0x00001000L +#define VPEC_STATUS_DCC__CE_IP4_DCCP_IDLE_MASK 0x00002000L +#define VPEC_STATUS_DCC__CE_IP4_DCC_RET_IDLE_MASK 0x00004000L +#define VPEC_STATUS_DCC__CE_IP5_MRQ_IDLE_MASK 0x00008000L +#define VPEC_STATUS_DCC__CE_IP5_DCCP_IDLE_MASK 0x00010000L +#define VPEC_STATUS_DCC__CE_IP5_DCC_RET_IDLE_MASK 0x00020000L +#define VPEC_STATUS_DCC__RESERVED_31_18_MASK 0xFFFC0000L +//VPEC_STATUS11 +#define VPEC_STATUS11__CE_IP4_WREQ_IDLE__SHIFT 0x0 +#define VPEC_STATUS11__CE_IP4_WR_IDLE__SHIFT 0x1 +#define VPEC_STATUS11__CE_IP4_SPLIT_RD_IDLE__SHIFT 0x2 +#define VPEC_STATUS11__CE_IP4_SPLIT_WR_IDLE__SHIFT 0x3 +#define VPEC_STATUS11__CE_IP4_RREQ_IDLE__SHIFT 0x4 +#define VPEC_STATUS11__CE_IP4_OUT_IDLE__SHIFT 0x5 +#define VPEC_STATUS11__CE_IP4_IN_IDLE__SHIFT 0x6 +#define VPEC_STATUS11__CE_IP4_DST_IDLE__SHIFT 0x7 +#define VPEC_STATUS11__CE_IP4_CMD_IDLE__SHIFT 0x8 +#define VPEC_STATUS11__CE_IP5_WREQ_IDLE__SHIFT 0x9 +#define VPEC_STATUS11__CE_IP5_WR_IDLE__SHIFT 0xa +#define VPEC_STATUS11__CE_IP5_SPLIT_RD_IDLE__SHIFT 0xb +#define VPEC_STATUS11__CE_IP5_SPLIT_WR_IDLE__SHIFT 0xc +#define VPEC_STATUS11__CE_IP5_RREQ_IDLE__SHIFT 0xd +#define VPEC_STATUS11__CE_IP5_OUT_IDLE__SHIFT 0xe +#define VPEC_STATUS11__CE_IP5_IN_IDLE__SHIFT 0xf +#define VPEC_STATUS11__CE_IP5_DST_IDLE__SHIFT 0x10 +#define VPEC_STATUS11__CE_IP5_CMD_IDLE__SHIFT 0x11 +#define VPEC_STATUS11__CE_IP4_AFIFO_FULL__SHIFT 0x12 +#define VPEC_STATUS11__CE_IP4_CMD_INFO_FULL__SHIFT 0x13 +#define VPEC_STATUS11__CE_IP4_CMD_INFO1_FULL__SHIFT 0x14 +#define VPEC_STATUS11__CE_IP5_AFIFO_FULL__SHIFT 0x15 +#define VPEC_STATUS11__CE_IP5_CMD_INFO_FULL__SHIFT 0x16 +#define VPEC_STATUS11__CE_IP5_CMD_INFO1_FULL__SHIFT 0x17 +#define VPEC_STATUS11__CE_IP4_WR_STALL__SHIFT 0x18 +#define VPEC_STATUS11__CE_IP5_WR_STALL__SHIFT 0x19 +#define VPEC_STATUS11__CE_IP4_RD_STALL__SHIFT 0x1a +#define VPEC_STATUS11__CE_IP5_RD_STALL__SHIFT 0x1b +#define VPEC_STATUS11__RESERVED_31_28__SHIFT 0x1c +#define VPEC_STATUS11__CE_IP4_WREQ_IDLE_MASK 0x00000001L +#define VPEC_STATUS11__CE_IP4_WR_IDLE_MASK 0x00000002L +#define VPEC_STATUS11__CE_IP4_SPLIT_RD_IDLE_MASK 0x00000004L +#define VPEC_STATUS11__CE_IP4_SPLIT_WR_IDLE_MASK 0x00000008L +#define VPEC_STATUS11__CE_IP4_RREQ_IDLE_MASK 0x00000010L +#define VPEC_STATUS11__CE_IP4_OUT_IDLE_MASK 0x00000020L +#define VPEC_STATUS11__CE_IP4_IN_IDLE_MASK 0x00000040L +#define VPEC_STATUS11__CE_IP4_DST_IDLE_MASK 0x00000080L +#define VPEC_STATUS11__CE_IP4_CMD_IDLE_MASK 0x00000100L +#define VPEC_STATUS11__CE_IP5_WREQ_IDLE_MASK 0x00000200L +#define VPEC_STATUS11__CE_IP5_WR_IDLE_MASK 0x00000400L +#define VPEC_STATUS11__CE_IP5_SPLIT_RD_IDLE_MASK 0x00000800L +#define VPEC_STATUS11__CE_IP5_SPLIT_WR_IDLE_MASK 0x00001000L +#define VPEC_STATUS11__CE_IP5_RREQ_IDLE_MASK 0x00002000L +#define VPEC_STATUS11__CE_IP5_OUT_IDLE_MASK 0x00004000L +#define VPEC_STATUS11__CE_IP5_IN_IDLE_MASK 0x00008000L +#define VPEC_STATUS11__CE_IP5_DST_IDLE_MASK 0x00010000L +#define VPEC_STATUS11__CE_IP5_CMD_IDLE_MASK 0x00020000L +#define VPEC_STATUS11__CE_IP4_AFIFO_FULL_MASK 0x00040000L +#define VPEC_STATUS11__CE_IP4_CMD_INFO_FULL_MASK 0x00080000L +#define VPEC_STATUS11__CE_IP4_CMD_INFO1_FULL_MASK 0x00100000L +#define VPEC_STATUS11__CE_IP5_AFIFO_FULL_MASK 0x00200000L +#define VPEC_STATUS11__CE_IP5_CMD_INFO_FULL_MASK 0x00400000L +#define VPEC_STATUS11__CE_IP5_CMD_INFO1_FULL_MASK 0x00800000L +#define VPEC_STATUS11__CE_IP4_WR_STALL_MASK 0x01000000L +#define VPEC_STATUS11__CE_IP5_WR_STALL_MASK 0x02000000L +#define VPEC_STATUS11__CE_IP4_RD_STALL_MASK 0x04000000L +#define VPEC_STATUS11__CE_IP5_RD_STALL_MASK 0x08000000L +#define VPEC_STATUS11__RESERVED_31_28_MASK 0xF0000000L +//VPEC_INST +#define VPEC_INST__ID__SHIFT 0x0 +#define VPEC_INST__RESERVED__SHIFT 0x3 +#define VPEC_INST__ID_MASK 0x00000007L +#define VPEC_INST__RESERVED_MASK 0xFFFFFFF8L +//VPEC_QUEUE_STATUS0 +#define VPEC_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 +#define VPEC_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 +#define VPEC_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 +#define VPEC_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc +#define VPEC_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 +#define VPEC_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 +#define VPEC_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 +#define VPEC_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c +#define VPEC_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL +#define VPEC_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L +#define VPEC_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L +#define VPEC_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L +#define VPEC_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L +#define VPEC_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L +#define VPEC_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L +#define VPEC_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L +//VPEC_QUEUE_HANG_STATUS +#define VPEC_QUEUE_HANG_STATUS__F30T0_HANG__SHIFT 0x0 +#define VPEC_QUEUE_HANG_STATUS__CE_HANG__SHIFT 0x1 +#define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH__SHIFT 0x2 +#define VPEC_QUEUE_HANG_STATUS__INVALID_PKT_FIELD__SHIFT 0x3 +#define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR__SHIFT 0x4 +#define VPEC_QUEUE_HANG_STATUS__F32_ACCESS_OFF_VPDPP1__SHIFT 0x5 +#define VPEC_QUEUE_HANG_STATUS__RSMU_ACCESS_OFF_VPDPP1__SHIFT 0x6 +#define VPEC_QUEUE_HANG_STATUS__EOH_MISMATCH__SHIFT 0x7 +#define VPEC_QUEUE_HANG_STATUS__F30T0_HANG_MASK 0x00000001L +#define VPEC_QUEUE_HANG_STATUS__CE_HANG_MASK 0x00000002L +#define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH_MASK 0x00000004L +#define VPEC_QUEUE_HANG_STATUS__INVALID_PKT_FIELD_MASK 0x00000008L +#define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR_MASK 0x00000010L +#define VPEC_QUEUE_HANG_STATUS__F32_ACCESS_OFF_VPDPP1_MASK 0x00000020L +#define VPEC_QUEUE_HANG_STATUS__RSMU_ACCESS_OFF_VPDPP1_MASK 0x00000040L +#define VPEC_QUEUE_HANG_STATUS__EOH_MISMATCH_MASK 0x00000080L +//VPEC_DPM_IDLE_TIME +#define VPEC_DPM_IDLE_TIME__VALUE__SHIFT 0x0 +#define VPEC_DPM_IDLE_TIME__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_BUSY_TIME +#define VPEC_DPM_BUSY_TIME__VALUE__SHIFT 0x0 +#define VPEC_DPM_BUSY_TIME__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_IDLE_START_LO +#define VPEC_DPM_IDLE_START_LO__VALUE__SHIFT 0x0 +#define VPEC_DPM_IDLE_START_LO__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_IDLE_START_HI +#define VPEC_DPM_IDLE_START_HI__VALUE__SHIFT 0x0 +#define VPEC_DPM_IDLE_START_HI__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_BUSY_START_LO +#define VPEC_DPM_BUSY_START_LO__VALUE__SHIFT 0x0 +#define VPEC_DPM_BUSY_START_LO__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_BUSY_START_HI +#define VPEC_DPM_BUSY_START_HI__VALUE__SHIFT 0x0 +#define VPEC_DPM_BUSY_START_HI__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_LAST_REQ_TIMESTAMP +#define VPEC_DPM_LAST_REQ_TIMESTAMP__VALUE__SHIFT 0x0 +#define VPEC_DPM_LAST_REQ_TIMESTAMP__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_NEW_JOB_DUMMY3 +#define VPEC_DPM_NEW_JOB_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_DPM_NEW_JOB_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_STATE +#define VPEC_DPM_STATE__VALUE__SHIFT 0x0 +#define VPEC_DPM_STATE__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM0_FREQ +#define VPEC_DPM0_FREQ__VALUE__SHIFT 0x0 +#define VPEC_DPM0_FREQ__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM1_FREQ +#define VPEC_DPM1_FREQ__VALUE__SHIFT 0x0 +#define VPEC_DPM1_FREQ__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM2_FREQ +#define VPEC_DPM2_FREQ__VALUE__SHIFT 0x0 +#define VPEC_DPM2_FREQ__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM3_FREQ +#define VPEC_DPM3_FREQ__VALUE__SHIFT 0x0 +#define VPEC_DPM3_FREQ__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_THRESHOLD_SKIP +#define VPEC_DPM_THRESHOLD_SKIP__VALUE__SHIFT 0x0 +#define VPEC_DPM_THRESHOLD_SKIP__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_THRESHOLD_BUSY_OVERFLOW +#define VPEC_DPM_THRESHOLD_BUSY_OVERFLOW__VALUE__SHIFT 0x0 +#define VPEC_DPM_THRESHOLD_BUSY_OVERFLOW__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_CALC_BUSY_IN_POSTPROCESS +#define VPEC_DPM_CALC_BUSY_IN_POSTPROCESS__VALUE__SHIFT 0x0 +#define VPEC_DPM_CALC_BUSY_IN_POSTPROCESS__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_IN_CHECKIDLE_LOOP +#define VPEC_DPM_IN_CHECKIDLE_LOOP__VALUE__SHIFT 0x0 +#define VPEC_DPM_IN_CHECKIDLE_LOOP__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_THRESHOLD_IDLE_OVERFLOW +#define VPEC_DPM_THRESHOLD_IDLE_OVERFLOW__VALUE__SHIFT 0x0 +#define VPEC_DPM_THRESHOLD_IDLE_OVERFLOW__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_BUSY_CLAMP_COUNT +#define VPEC_DPM_BUSY_CLAMP_COUNT__VALUE__SHIFT 0x0 +#define VPEC_DPM_BUSY_CLAMP_COUNT__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_IDLE_CLAMP_COUNT +#define VPEC_DPM_IDLE_CLAMP_COUNT__VALUE__SHIFT 0x0 +#define VPEC_DPM_IDLE_CLAMP_COUNT__VALUE_MASK 0xFFFFFFFFL +//VPEC_PG_CNTL +#define VPEC_PG_CNTL__PG_EN__SHIFT 0x0 +#define VPEC_PG_CNTL__PG_HYSTERESIS__SHIFT 0x1 +#define VPEC_PG_CNTL__PG1_EN__SHIFT 0x8 +#define VPEC_PG_CNTL__PG1_HYSTERESIS__SHIFT 0x9 +#define VPEC_PG_CNTL__ZSTATES_ENABLE__SHIFT 0x10 +#define VPEC_PG_CNTL__ZSTATES_HYSTERESIS__SHIFT 0x11 +#define VPEC_PG_CNTL__FENCE_HYSTERESIS__SHIFT 0x18 +#define VPEC_PG_CNTL__CHECK_RSMU_UPON_POWER_UP__SHIFT 0x1c +#define VPEC_PG_CNTL__PG_EN_MASK 0x00000001L +#define VPEC_PG_CNTL__PG_HYSTERESIS_MASK 0x0000003EL +#define VPEC_PG_CNTL__PG1_EN_MASK 0x00000100L +#define VPEC_PG_CNTL__PG1_HYSTERESIS_MASK 0x00003E00L +#define VPEC_PG_CNTL__ZSTATES_ENABLE_MASK 0x00010000L +#define VPEC_PG_CNTL__ZSTATES_HYSTERESIS_MASK 0x003E0000L +#define VPEC_PG_CNTL__FENCE_HYSTERESIS_MASK 0x0F000000L +#define VPEC_PG_CNTL__CHECK_RSMU_UPON_POWER_UP_MASK 0x10000000L +//VPEC_PG_STATUS +#define VPEC_PG_STATUS__PG_STATUS__SHIFT 0x0 +#define VPEC_PG_STATUS__PG1_STATUS__SHIFT 0x2 +#define VPEC_PG_STATUS__PG_STATUS_MASK 0x00000003L +#define VPEC_PG_STATUS__PG1_STATUS_MASK 0x0000000CL +//VPEC_CLOCK_GATING_STATUS +#define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT 0x0 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS__SHIFT 0x2 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS__SHIFT 0x3 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE2_CLK_GATE_STATUS__SHIFT 0x4 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE3_CLK_GATE_STATUS__SHIFT 0x5 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS__SHIFT 0x6 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE1_CLK_GATE_STATUS__SHIFT 0x7 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE2_CLK_GATE_STATUS__SHIFT 0x8 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE3_CLK_GATE_STATUS__SHIFT 0x9 +#define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT 0xa +#define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT 0xb +#define VPEC_CLOCK_GATING_STATUS__USRAM_CLK_GATE_STATUS__SHIFT 0xc +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE4_CLK_GATE_STATUS__SHIFT 0xd +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE5_CLK_GATE_STATUS__SHIFT 0xe +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE6_CLK_GATE_STATUS__SHIFT 0xf +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE7_CLK_GATE_STATUS__SHIFT 0x10 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE4_CLK_GATE_STATUS__SHIFT 0x11 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE5_CLK_GATE_STATUS__SHIFT 0x12 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE8_CLK_GATE_STATUS__SHIFT 0x13 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE9_CLK_GATE_STATUS__SHIFT 0x14 +#define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS_MASK 0x00000004L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS_MASK 0x00000008L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE2_CLK_GATE_STATUS_MASK 0x00000010L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE3_CLK_GATE_STATUS_MASK 0x00000020L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS_MASK 0x00000040L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE1_CLK_GATE_STATUS_MASK 0x00000080L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE2_CLK_GATE_STATUS_MASK 0x00000100L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE3_CLK_GATE_STATUS_MASK 0x00000200L +#define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000400L +#define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000800L +#define VPEC_CLOCK_GATING_STATUS__USRAM_CLK_GATE_STATUS_MASK 0x00001000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE4_CLK_GATE_STATUS_MASK 0x00002000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE5_CLK_GATE_STATUS_MASK 0x00004000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE6_CLK_GATE_STATUS_MASK 0x00008000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE7_CLK_GATE_STATUS_MASK 0x00010000L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE4_CLK_GATE_STATUS_MASK 0x00020000L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE5_CLK_GATE_STATUS_MASK 0x00040000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE8_CLK_GATE_STATUS_MASK 0x00080000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE9_CLK_GATE_STATUS_MASK 0x00100000L +//VPEC_QUEUE0_RB_CNTL +#define VPEC_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE0_SCHEDULE_CNTL +#define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE0_RB_BASE +#define VPEC_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_BASE_HI +#define VPEC_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE0_RB_RPTR +#define VPEC_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_RPTR_HI +#define VPEC_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_WPTR +#define VPEC_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_WPTR_HI +#define VPEC_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_RPTR_ADDR_HI +#define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_RPTR_ADDR_LO +#define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE0_RB_AQL_CNTL +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE0_MINOR_PTR_UPDATE +#define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE0_CD_INFO +#define VPEC_QUEUE0_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE0_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_PREEMPT +#define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE0_SKIP_CNTL +#define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE0_DOORBELL +#define VPEC_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE0_DOORBELL_OFFSET +#define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE0_DUMMY0 +#define VPEC_QUEUE0_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY1 +#define VPEC_QUEUE0_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY2 +#define VPEC_QUEUE0_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY3 +#define VPEC_QUEUE0_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY4 +#define VPEC_QUEUE0_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_IB_CNTL +#define VPEC_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE0_IB_RPTR +#define VPEC_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_IB_OFFSET +#define VPEC_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_IB_BASE_LO +#define VPEC_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE0_IB_BASE_HI +#define VPEC_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_IB_SIZE +#define VPEC_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE0_CMDIB_CNTL +#define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE0_CMDIB_RPTR +#define VPEC_QUEUE0_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_CMDIB_OFFSET +#define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_CMDIB_BASE_LO +#define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE0_CMDIB_BASE_HI +#define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_CMDIB_SIZE +#define VPEC_QUEUE0_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE0_3DLUTIB_CNTL +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE0_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE0_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE0_3DLUTIB_RPTR +#define VPEC_QUEUE0_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_3DLUTIB_OFFSET +#define VPEC_QUEUE0_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_3DLUTIB_BASE_LO +#define VPEC_QUEUE0_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE0_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE0_3DLUTIB_BASE_HI +#define VPEC_QUEUE0_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_3DLUTIB_SIZE +#define VPEC_QUEUE0_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE0_CSA_ADDR_LO +#define VPEC_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_CSA_ADDR_HI +#define VPEC_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_CONTEXT_STATUS +#define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE0_DOORBELL_LOG +#define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE0_IB_SUB_REMAIN +#define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE0_PREEMPT +#define VPEC_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE0_LOG0BUFFER_CFG +#define VPEC_QUEUE0_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE0_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE0_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE0_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE0_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE0_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE0_LOG1BUFFER_CFG +#define VPEC_QUEUE0_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE0_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE0_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE0_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE0_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE1_RB_CNTL +#define VPEC_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE1_SCHEDULE_CNTL +#define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE1_RB_BASE +#define VPEC_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_BASE_HI +#define VPEC_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE1_RB_RPTR +#define VPEC_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_RPTR_HI +#define VPEC_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_WPTR +#define VPEC_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_WPTR_HI +#define VPEC_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_RPTR_ADDR_HI +#define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_RPTR_ADDR_LO +#define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE1_RB_AQL_CNTL +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE1_MINOR_PTR_UPDATE +#define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE1_CD_INFO +#define VPEC_QUEUE1_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE1_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_PREEMPT +#define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE1_SKIP_CNTL +#define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE1_DOORBELL +#define VPEC_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE1_DOORBELL_OFFSET +#define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE1_DUMMY0 +#define VPEC_QUEUE1_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY1 +#define VPEC_QUEUE1_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY2 +#define VPEC_QUEUE1_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY3 +#define VPEC_QUEUE1_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY4 +#define VPEC_QUEUE1_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_IB_CNTL +#define VPEC_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE1_IB_RPTR +#define VPEC_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_IB_OFFSET +#define VPEC_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_IB_BASE_LO +#define VPEC_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE1_IB_BASE_HI +#define VPEC_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_IB_SIZE +#define VPEC_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE1_CMDIB_CNTL +#define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE1_CMDIB_RPTR +#define VPEC_QUEUE1_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_CMDIB_OFFSET +#define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_CMDIB_BASE_LO +#define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE1_CMDIB_BASE_HI +#define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_CMDIB_SIZE +#define VPEC_QUEUE1_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE1_3DLUTIB_CNTL +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE1_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE1_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE1_3DLUTIB_RPTR +#define VPEC_QUEUE1_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_3DLUTIB_OFFSET +#define VPEC_QUEUE1_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_3DLUTIB_BASE_LO +#define VPEC_QUEUE1_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE1_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE1_3DLUTIB_BASE_HI +#define VPEC_QUEUE1_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_3DLUTIB_SIZE +#define VPEC_QUEUE1_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE1_CSA_ADDR_LO +#define VPEC_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_CSA_ADDR_HI +#define VPEC_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_CONTEXT_STATUS +#define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE1_DOORBELL_LOG +#define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE1_IB_SUB_REMAIN +#define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE1_PREEMPT +#define VPEC_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE1_LOG0BUFFER_CFG +#define VPEC_QUEUE1_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE1_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE1_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE1_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE1_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE1_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE1_LOG1BUFFER_CFG +#define VPEC_QUEUE1_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE1_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE1_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE1_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE1_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE2_RB_CNTL +#define VPEC_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE2_SCHEDULE_CNTL +#define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE2_RB_BASE +#define VPEC_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_BASE_HI +#define VPEC_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE2_RB_RPTR +#define VPEC_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_RPTR_HI +#define VPEC_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_WPTR +#define VPEC_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_WPTR_HI +#define VPEC_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_RPTR_ADDR_HI +#define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_RPTR_ADDR_LO +#define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE2_RB_AQL_CNTL +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE2_MINOR_PTR_UPDATE +#define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE2_CD_INFO +#define VPEC_QUEUE2_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE2_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_PREEMPT +#define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE2_SKIP_CNTL +#define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE2_DOORBELL +#define VPEC_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE2_DOORBELL_OFFSET +#define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE2_DUMMY0 +#define VPEC_QUEUE2_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY1 +#define VPEC_QUEUE2_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY2 +#define VPEC_QUEUE2_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY3 +#define VPEC_QUEUE2_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY4 +#define VPEC_QUEUE2_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_IB_CNTL +#define VPEC_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE2_IB_RPTR +#define VPEC_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_IB_OFFSET +#define VPEC_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_IB_BASE_LO +#define VPEC_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE2_IB_BASE_HI +#define VPEC_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_IB_SIZE +#define VPEC_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE2_CMDIB_CNTL +#define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE2_CMDIB_RPTR +#define VPEC_QUEUE2_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_CMDIB_OFFSET +#define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_CMDIB_BASE_LO +#define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE2_CMDIB_BASE_HI +#define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_CMDIB_SIZE +#define VPEC_QUEUE2_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE2_3DLUTIB_CNTL +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE2_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE2_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE2_3DLUTIB_RPTR +#define VPEC_QUEUE2_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_3DLUTIB_OFFSET +#define VPEC_QUEUE2_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_3DLUTIB_BASE_LO +#define VPEC_QUEUE2_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE2_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE2_3DLUTIB_BASE_HI +#define VPEC_QUEUE2_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_3DLUTIB_SIZE +#define VPEC_QUEUE2_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE2_CSA_ADDR_LO +#define VPEC_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_CSA_ADDR_HI +#define VPEC_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_CONTEXT_STATUS +#define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE2_DOORBELL_LOG +#define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE2_IB_SUB_REMAIN +#define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE2_PREEMPT +#define VPEC_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE2_LOG0BUFFER_CFG +#define VPEC_QUEUE2_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE2_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE2_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE2_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE2_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE2_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE2_LOG1BUFFER_CFG +#define VPEC_QUEUE2_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE2_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE2_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE2_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE2_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE3_RB_CNTL +#define VPEC_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE3_SCHEDULE_CNTL +#define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE3_RB_BASE +#define VPEC_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_BASE_HI +#define VPEC_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE3_RB_RPTR +#define VPEC_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_RPTR_HI +#define VPEC_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_WPTR +#define VPEC_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_WPTR_HI +#define VPEC_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_RPTR_ADDR_HI +#define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_RPTR_ADDR_LO +#define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE3_RB_AQL_CNTL +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE3_MINOR_PTR_UPDATE +#define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE3_CD_INFO +#define VPEC_QUEUE3_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE3_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_PREEMPT +#define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE3_SKIP_CNTL +#define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE3_DOORBELL +#define VPEC_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE3_DOORBELL_OFFSET +#define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE3_DUMMY0 +#define VPEC_QUEUE3_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY1 +#define VPEC_QUEUE3_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY2 +#define VPEC_QUEUE3_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY3 +#define VPEC_QUEUE3_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY4 +#define VPEC_QUEUE3_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_IB_CNTL +#define VPEC_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE3_IB_RPTR +#define VPEC_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_IB_OFFSET +#define VPEC_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_IB_BASE_LO +#define VPEC_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE3_IB_BASE_HI +#define VPEC_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_IB_SIZE +#define VPEC_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE3_CMDIB_CNTL +#define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE3_CMDIB_RPTR +#define VPEC_QUEUE3_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_CMDIB_OFFSET +#define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_CMDIB_BASE_LO +#define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE3_CMDIB_BASE_HI +#define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_CMDIB_SIZE +#define VPEC_QUEUE3_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE3_3DLUTIB_CNTL +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE3_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE3_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE3_3DLUTIB_RPTR +#define VPEC_QUEUE3_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_3DLUTIB_OFFSET +#define VPEC_QUEUE3_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_3DLUTIB_BASE_LO +#define VPEC_QUEUE3_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE3_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE3_3DLUTIB_BASE_HI +#define VPEC_QUEUE3_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_3DLUTIB_SIZE +#define VPEC_QUEUE3_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE3_CSA_ADDR_LO +#define VPEC_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_CSA_ADDR_HI +#define VPEC_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_CONTEXT_STATUS +#define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE3_DOORBELL_LOG +#define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE3_IB_SUB_REMAIN +#define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE3_PREEMPT +#define VPEC_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE3_LOG0BUFFER_CFG +#define VPEC_QUEUE3_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE3_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE3_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE3_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE3_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE3_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE3_LOG1BUFFER_CFG +#define VPEC_QUEUE3_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE3_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE3_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE3_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE3_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE4_RB_CNTL +#define VPEC_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE4_SCHEDULE_CNTL +#define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE4_RB_BASE +#define VPEC_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_BASE_HI +#define VPEC_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE4_RB_RPTR +#define VPEC_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_RPTR_HI +#define VPEC_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_WPTR +#define VPEC_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_WPTR_HI +#define VPEC_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_RPTR_ADDR_HI +#define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_RPTR_ADDR_LO +#define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE4_RB_AQL_CNTL +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE4_MINOR_PTR_UPDATE +#define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE4_CD_INFO +#define VPEC_QUEUE4_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE4_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_PREEMPT +#define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE4_SKIP_CNTL +#define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE4_DOORBELL +#define VPEC_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE4_DOORBELL_OFFSET +#define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE4_DUMMY0 +#define VPEC_QUEUE4_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY1 +#define VPEC_QUEUE4_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY2 +#define VPEC_QUEUE4_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY3 +#define VPEC_QUEUE4_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY4 +#define VPEC_QUEUE4_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_IB_CNTL +#define VPEC_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE4_IB_RPTR +#define VPEC_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_IB_OFFSET +#define VPEC_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_IB_BASE_LO +#define VPEC_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE4_IB_BASE_HI +#define VPEC_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_IB_SIZE +#define VPEC_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE4_CMDIB_CNTL +#define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE4_CMDIB_RPTR +#define VPEC_QUEUE4_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_CMDIB_OFFSET +#define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_CMDIB_BASE_LO +#define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE4_CMDIB_BASE_HI +#define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_CMDIB_SIZE +#define VPEC_QUEUE4_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE4_3DLUTIB_CNTL +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE4_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE4_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE4_3DLUTIB_RPTR +#define VPEC_QUEUE4_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_3DLUTIB_OFFSET +#define VPEC_QUEUE4_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_3DLUTIB_BASE_LO +#define VPEC_QUEUE4_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE4_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE4_3DLUTIB_BASE_HI +#define VPEC_QUEUE4_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_3DLUTIB_SIZE +#define VPEC_QUEUE4_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE4_CSA_ADDR_LO +#define VPEC_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_CSA_ADDR_HI +#define VPEC_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_CONTEXT_STATUS +#define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE4_DOORBELL_LOG +#define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE4_IB_SUB_REMAIN +#define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE4_PREEMPT +#define VPEC_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE4_LOG0BUFFER_CFG +#define VPEC_QUEUE4_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE4_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE4_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE4_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE4_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE4_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE4_LOG1BUFFER_CFG +#define VPEC_QUEUE4_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE4_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE4_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE4_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE4_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE5_RB_CNTL +#define VPEC_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE5_SCHEDULE_CNTL +#define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE5_RB_BASE +#define VPEC_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_BASE_HI +#define VPEC_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE5_RB_RPTR +#define VPEC_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_RPTR_HI +#define VPEC_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_WPTR +#define VPEC_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_WPTR_HI +#define VPEC_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_RPTR_ADDR_HI +#define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_RPTR_ADDR_LO +#define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE5_RB_AQL_CNTL +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE5_MINOR_PTR_UPDATE +#define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE5_CD_INFO +#define VPEC_QUEUE5_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE5_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_PREEMPT +#define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE5_SKIP_CNTL +#define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE5_DOORBELL +#define VPEC_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE5_DOORBELL_OFFSET +#define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE5_DUMMY0 +#define VPEC_QUEUE5_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY1 +#define VPEC_QUEUE5_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY2 +#define VPEC_QUEUE5_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY3 +#define VPEC_QUEUE5_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY4 +#define VPEC_QUEUE5_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_IB_CNTL +#define VPEC_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE5_IB_RPTR +#define VPEC_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_IB_OFFSET +#define VPEC_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_IB_BASE_LO +#define VPEC_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE5_IB_BASE_HI +#define VPEC_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_IB_SIZE +#define VPEC_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE5_CMDIB_CNTL +#define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE5_CMDIB_RPTR +#define VPEC_QUEUE5_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_CMDIB_OFFSET +#define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_CMDIB_BASE_LO +#define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE5_CMDIB_BASE_HI +#define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_CMDIB_SIZE +#define VPEC_QUEUE5_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE5_3DLUTIB_CNTL +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE5_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE5_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE5_3DLUTIB_RPTR +#define VPEC_QUEUE5_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_3DLUTIB_OFFSET +#define VPEC_QUEUE5_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_3DLUTIB_BASE_LO +#define VPEC_QUEUE5_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE5_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE5_3DLUTIB_BASE_HI +#define VPEC_QUEUE5_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_3DLUTIB_SIZE +#define VPEC_QUEUE5_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE5_CSA_ADDR_LO +#define VPEC_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_CSA_ADDR_HI +#define VPEC_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_CONTEXT_STATUS +#define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE5_DOORBELL_LOG +#define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE5_IB_SUB_REMAIN +#define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE5_PREEMPT +#define VPEC_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE5_LOG0BUFFER_CFG +#define VPEC_QUEUE5_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE5_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE5_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE5_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE5_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE5_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE5_LOG1BUFFER_CFG +#define VPEC_QUEUE5_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE5_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE5_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE5_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE5_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE6_RB_CNTL +#define VPEC_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE6_SCHEDULE_CNTL +#define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE6_RB_BASE +#define VPEC_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_BASE_HI +#define VPEC_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE6_RB_RPTR +#define VPEC_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_RPTR_HI +#define VPEC_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_WPTR +#define VPEC_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_WPTR_HI +#define VPEC_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_RPTR_ADDR_HI +#define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_RPTR_ADDR_LO +#define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE6_RB_AQL_CNTL +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE6_MINOR_PTR_UPDATE +#define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE6_CD_INFO +#define VPEC_QUEUE6_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE6_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_PREEMPT +#define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE6_SKIP_CNTL +#define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE6_DOORBELL +#define VPEC_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE6_DOORBELL_OFFSET +#define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE6_DUMMY0 +#define VPEC_QUEUE6_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY1 +#define VPEC_QUEUE6_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY2 +#define VPEC_QUEUE6_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY3 +#define VPEC_QUEUE6_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY4 +#define VPEC_QUEUE6_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_IB_CNTL +#define VPEC_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE6_IB_RPTR +#define VPEC_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_IB_OFFSET +#define VPEC_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_IB_BASE_LO +#define VPEC_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE6_IB_BASE_HI +#define VPEC_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_IB_SIZE +#define VPEC_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE6_CMDIB_CNTL +#define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE6_CMDIB_RPTR +#define VPEC_QUEUE6_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_CMDIB_OFFSET +#define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_CMDIB_BASE_LO +#define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE6_CMDIB_BASE_HI +#define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_CMDIB_SIZE +#define VPEC_QUEUE6_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE6_3DLUTIB_CNTL +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE6_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE6_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE6_3DLUTIB_RPTR +#define VPEC_QUEUE6_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_3DLUTIB_OFFSET +#define VPEC_QUEUE6_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_3DLUTIB_BASE_LO +#define VPEC_QUEUE6_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE6_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE6_3DLUTIB_BASE_HI +#define VPEC_QUEUE6_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_3DLUTIB_SIZE +#define VPEC_QUEUE6_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE6_CSA_ADDR_LO +#define VPEC_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_CSA_ADDR_HI +#define VPEC_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_CONTEXT_STATUS +#define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE6_DOORBELL_LOG +#define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE6_IB_SUB_REMAIN +#define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE6_PREEMPT +#define VPEC_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE6_LOG0BUFFER_CFG +#define VPEC_QUEUE6_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE6_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE6_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE6_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE6_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE6_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE6_LOG1BUFFER_CFG +#define VPEC_QUEUE6_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE6_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE6_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE6_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE6_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE7_RB_CNTL +#define VPEC_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE7_SCHEDULE_CNTL +#define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE7_RB_BASE +#define VPEC_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_BASE_HI +#define VPEC_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE7_RB_RPTR +#define VPEC_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_RPTR_HI +#define VPEC_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_WPTR +#define VPEC_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_WPTR_HI +#define VPEC_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_RPTR_ADDR_HI +#define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_RPTR_ADDR_LO +#define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE7_RB_AQL_CNTL +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE7_MINOR_PTR_UPDATE +#define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE7_CD_INFO +#define VPEC_QUEUE7_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE7_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_PREEMPT +#define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE7_SKIP_CNTL +#define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE7_DOORBELL +#define VPEC_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE7_DOORBELL_OFFSET +#define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE7_DUMMY0 +#define VPEC_QUEUE7_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY1 +#define VPEC_QUEUE7_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY2 +#define VPEC_QUEUE7_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY3 +#define VPEC_QUEUE7_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY4 +#define VPEC_QUEUE7_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_IB_CNTL +#define VPEC_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE7_IB_RPTR +#define VPEC_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_IB_OFFSET +#define VPEC_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_IB_BASE_LO +#define VPEC_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE7_IB_BASE_HI +#define VPEC_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_IB_SIZE +#define VPEC_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE7_CMDIB_CNTL +#define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE7_CMDIB_RPTR +#define VPEC_QUEUE7_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_CMDIB_OFFSET +#define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_CMDIB_BASE_LO +#define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE7_CMDIB_BASE_HI +#define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_CMDIB_SIZE +#define VPEC_QUEUE7_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE7_3DLUTIB_CNTL +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE7_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE7_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE7_3DLUTIB_RPTR +#define VPEC_QUEUE7_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_3DLUTIB_OFFSET +#define VPEC_QUEUE7_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_3DLUTIB_BASE_LO +#define VPEC_QUEUE7_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE7_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE7_3DLUTIB_BASE_HI +#define VPEC_QUEUE7_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_3DLUTIB_SIZE +#define VPEC_QUEUE7_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE7_CSA_ADDR_LO +#define VPEC_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_CSA_ADDR_HI +#define VPEC_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_CONTEXT_STATUS +#define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE7_DOORBELL_LOG +#define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE7_IB_SUB_REMAIN +#define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE7_PREEMPT +#define VPEC_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE7_LOG0BUFFER_CFG +#define VPEC_QUEUE7_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE7_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE7_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE7_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE7_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE7_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE7_LOG1BUFFER_CFG +#define VPEC_QUEUE7_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE7_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE7_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE7_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE7_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L + +#endif diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 9aba8596faa7..44e225e097d0 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -33,6 +33,7 @@ #include #include "amdgpu_irq.h" #include "amdgpu_gfx.h" +#include "amdgpu_ptl.h" struct pci_dev; struct amdgpu_device; @@ -333,6 +334,11 @@ struct kfd2kgd_calls { uint32_t inst, unsigned int utimeout); uint32_t (*hqd_sdma_get_doorbell)(struct amdgpu_device *adev, int engine, int queue); + uint32_t (*ptl_ctrl)(struct amdgpu_device *adev, + uint32_t cmd, + uint32_t *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 736304e73ca4..bb11f8bb7bd4 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -2034,15 +2034,13 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) *states = ATTR_STATE_UNSUPPORTED; } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) { - if (gc_ver == IP_VERSION(9, 4, 2) || - amdgpu_is_multi_aid(adev)) + if (amdgpu_is_multi_aid(adev)) *states = ATTR_STATE_UNSUPPORTED; } switch (gc_ver) { case IP_VERSION(9, 4, 1): - case IP_VERSION(9, 4, 2): - /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ + /* Arcturus does not support standalone mclk/socclk/fclk level setting */ if (DEVICE_ATTR_IS(pp_dpm_mclk) || DEVICE_ATTR_IS(pp_dpm_socclk) || DEVICE_ATTR_IS(pp_dpm_fclk)) { @@ -2050,6 +2048,19 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd dev_attr->store = NULL; } break; + case IP_VERSION(9, 4, 2): + if (DEVICE_ATTR_IS(pp_dpm_mclk) || + DEVICE_ATTR_IS(pp_dpm_socclk)) { + /* Aldebaran mclk/socclk DPM only supports voltage control, + * not allow to set dpm level directly */ + dev_attr->attr.mode &= ~S_IWUGO; + dev_attr->store = NULL; + } else if (DEVICE_ATTR_IS(pp_dpm_fclk) || + DEVICE_ATTR_IS(pp_dpm_pcie)) { + /* Aldebaran does not support fclk/pcie dpm */ + *states = ATTR_STATE_UNSUPPORTED; + } + break; default: break; } @@ -2505,12 +2516,12 @@ static ssize_t amdgpu_set_pm_policy_attr(struct device *dev, .dev_attr = __ATTR(_name, 0644, amdgpu_get_pm_policy_attr, \ amdgpu_set_pm_policy_attr), \ .id = PP_PM_POLICY_##_id, \ - }; + } #define AMDGPU_PM_POLICY_ATTR_VAR(_name) pm_policy_attr_##_name.dev_attr.attr -AMDGPU_PM_POLICY_ATTR(soc_pstate, SOC_PSTATE) -AMDGPU_PM_POLICY_ATTR(xgmi_plpd, XGMI_PLPD) +AMDGPU_PM_POLICY_ATTR(soc_pstate, SOC_PSTATE); +AMDGPU_PM_POLICY_ATTR(xgmi_plpd, XGMI_PLPD); static struct attribute *pm_policy_attrs[] = { &AMDGPU_PM_POLICY_ATTR_VAR(soc_pstate), diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c index 731355bdb9bc..3650e7beeb67 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c @@ -1333,12 +1333,13 @@ static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr) dev_id = adev->pdev->device; - if ((dpm_table->mclk_table.count >= 2) - && ((dev_id == 0x67B0) || (dev_id == 0x67B1))) { - smu_data->smc_state_table.MemoryLevel[1].MinVddci = - smu_data->smc_state_table.MemoryLevel[0].MinVddci; - smu_data->smc_state_table.MemoryLevel[1].MinMvdd = - smu_data->smc_state_table.MemoryLevel[0].MinMvdd; + if ((dpm_table->mclk_table.count >= 2) && + ((dev_id == 0x67B0) || (dev_id == 0x67B1)) && + (adev->pdev->revision == 0)) { + smu_data->smc_state_table.MemoryLevel[1].MinVddc = + smu_data->smc_state_table.MemoryLevel[0].MinVddc; + smu_data->smc_state_table.MemoryLevel[1].MinVddcPhases = + smu_data->smc_state_table.MemoryLevel[0].MinVddcPhases; } smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 7f386ff0c872..9d8b1227388f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -425,6 +425,7 @@ static int aldebaran_set_default_dpm_table(struct smu_context *smu) dpm_table->dpm_levels[0].enabled = true; dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; dpm_table->dpm_levels[1].enabled = true; + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index cd0a23f432ff..b12388134489 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -783,6 +783,10 @@ int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table, if (ret) return ret; + if (!memchr_inv(smu_table->metrics_table, 0xff, + min(16, table_size))) + return -EHWPOISON; + smu_table->metrics_time = jiffies; } @@ -1129,6 +1133,7 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; dpm_table->clk_type = SMU_GFXCLK; + dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { /* In the case of gfxclk, only fine-grained dpm is honored. * Get min/max values from FW. @@ -2070,9 +2075,9 @@ static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu, return -EINVAL; if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { - if (min >= max) { + if (min > max) { dev_err(smu->adev->dev, - "Minimum clk should be less than the maximum allowed clock\n"); + "Minimum clk should be less/equal to the maximum allowed clock\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index c3cb36813806..a1318409e4b5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -435,10 +435,12 @@ int smu_v15_0_fini_smc_tables(struct smu_context *smu) smu_table->watermarks_table = NULL; smu_table->metrics_time = 0; + kfree(smu_dpm->dpm_policies); kfree(smu_dpm->dpm_context); kfree(smu_dpm->golden_dpm_context); kfree(smu_dpm->dpm_current_power_state); kfree(smu_dpm->dpm_request_power_state); + smu_dpm->dpm_policies = NULL; smu_dpm->dpm_context = NULL; smu_dpm->golden_dpm_context = NULL; smu_dpm->dpm_context_size = 0; @@ -589,52 +591,47 @@ int smu_v15_0_notify_memory_pool_location(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *memory_pool = &smu_table->memory_pool; - struct smu_msg_args args = { - .msg = SMU_MSG_DramLogSetDramAddr, - .num_args = 3, - .num_out_args = 0, - }; + uint32_t params[3]; if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) return 0; /* SMU_MSG_DramLogSetDramAddr: ARG0=low, ARG1=high, ARG2=size */ - args.args[0] = lower_32_bits(memory_pool->mc_address); - args.args[1] = upper_32_bits(memory_pool->mc_address); - args.args[2] = (u32)memory_pool->size; + params[0] = lower_32_bits(memory_pool->mc_address); + params[1] = upper_32_bits(memory_pool->mc_address); + params[2] = (u32)memory_pool->size; - return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); + return smu_cmn_send_smc_msg_with_params(smu, + SMU_MSG_DramLogSetDramAddr, + params, ARRAY_SIZE(params), + NULL, 0); } int smu_v15_0_set_driver_table_location(struct smu_context *smu) { struct smu_table *driver_table = &smu->smu_table.driver_table; - struct smu_msg_args args = { - .msg = SMU_MSG_SetDriverDramAddr, - .num_args = 2, - .num_out_args = 0, + const uint32_t params[] = { + lower_32_bits(driver_table->mc_address), + upper_32_bits(driver_table->mc_address), }; - args.args[0] = lower_32_bits(driver_table->mc_address); - args.args[1] = upper_32_bits(driver_table->mc_address); - - return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); + return smu_cmn_send_smc_msg_with_params(smu, SMU_MSG_SetDriverDramAddr, + params, ARRAY_SIZE(params), + NULL, 0); } int smu_v15_0_set_tool_table_location(struct smu_context *smu) { struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; - struct smu_msg_args args = { - .msg = SMU_MSG_SetToolsDramAddr, - .num_args = 2, - .num_out_args = 0, + const uint32_t params[] = { + lower_32_bits(tool_table->mc_address), + upper_32_bits(tool_table->mc_address), }; /* SMU_MSG_SetToolsDramAddr: ARG0=low, ARG1=high */ - args.args[0] = lower_32_bits(tool_table->mc_address); - args.args[1] = upper_32_bits(tool_table->mc_address); - - return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); + return smu_cmn_send_smc_msg_with_params(smu, SMU_MSG_SetToolsDramAddr, + params, ARRAY_SIZE(params), + NULL, 0); } int smu_v15_0_set_allowed_mask(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index 8d092c347076..fb1145691410 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -248,7 +248,7 @@ static int smu_v15_0_0_update_table(struct smu_context *smu, uint64_t address; uint32_t table_size; int ret; - struct smu_msg_ctl *ctl = &smu->msg_ctl; + uint32_t params[3]; if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) return -EINVAL; @@ -265,20 +265,15 @@ static int smu_v15_0_0_update_table(struct smu_context *smu, } address = table->mc_address; + params[0] = table_id; + params[1] = (uint32_t)lower_32_bits(address); + params[2] = (uint32_t)upper_32_bits(address); - struct smu_msg_args args = { - .msg = drv2smu ? - SMU_MSG_TransferTableDram2Smu : - SMU_MSG_TransferTableSmu2Dram, - .num_args = 3, - .num_out_args = 0, - }; - - args.args[0] = table_id; - args.args[1] = (uint32_t)lower_32_bits(address); - args.args[2] = (uint32_t)upper_32_bits(address); - - ret = ctl->ops->send_msg(ctl, &args); + ret = smu_cmn_send_smc_msg_with_params(smu, + drv2smu ? SMU_MSG_TransferTableDram2Smu : + SMU_MSG_TransferTableSmu2Dram, + params, ARRAY_SIZE(params), + NULL, 0); if (ret) return ret; @@ -535,22 +530,19 @@ static int smu_v15_0_0_read_sensor(struct smu_context *smu, static int smu_v15_0_0_get_enabled_mask(struct smu_context *smu, struct smu_feature_bits *feature_mask) { + uint32_t out[2]; int ret; - struct smu_msg_ctl *ctl = &smu->msg_ctl; if (!feature_mask) return -EINVAL; - struct smu_msg_args args = { - .msg = SMU_MSG_GetEnabledSmuFeatures, - .num_args = 0, - .num_out_args = 2, - }; - - ret = ctl->ops->send_msg(ctl, &args); + ret = smu_cmn_send_smc_msg_with_params(smu, + SMU_MSG_GetEnabledSmuFeatures, + NULL, 0, out, + ARRAY_SIZE(out)); if (!ret) - smu_feature_bits_from_arr32(feature_mask, args.out_args, + smu_feature_bits_from_arr32(feature_mask, out, SMU_FEATURE_NUM_DEFAULT); return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index db85186f2d66..2105a1d7bb34 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -63,6 +63,8 @@ for ((stack_idx) = 0; (umc_mask); \ (umc_mask) >>= 4, (stack_idx)++) \ +#define NUM_JPEG_RINGS_FW 10 + #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) #define SMU_15_0_8_FEA_MAP(smu_feature, smu_15_0_8_feature) \ @@ -171,6 +173,13 @@ static const struct cmn2asic_mapping smu_v15_0_8_table_map[SMU_TABLE_COUNT] = { TAB_MAP(I2C_COMMANDS), }; +static const uint8_t smu_v15_0_8_throttler_map[] = { + [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT), + [THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), + [THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), + [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), +}; + static size_t smu_v15_0_8_get_system_metrics_size(void) { return sizeof(SystemMetricsTable_t); @@ -1062,38 +1071,30 @@ static int smu_v15_0_8_set_driver_pptable(struct smu_context *smu) smu_table->tables[SMU_TABLE_SMU_METRICS].version = table_version; - pptable->MaxSocketPowerLimit = - SMUQ10_ROUND(static_metrics->MaxSocketPowerLimit); - pptable->MaxGfxclkFrequency = - SMUQ10_ROUND(static_metrics->MaxGfxclkFrequency); - pptable->MinGfxclkFrequency = - SMUQ10_ROUND(static_metrics->MinGfxclkFrequency); - pptable->MaxFclkFrequency = - SMUQ10_ROUND(static_metrics->MaxFclkFrequency); - pptable->MinFclkFrequency = - SMUQ10_ROUND(static_metrics->MinFclkFrequency); - pptable->MaxGl2clkFrequency = - SMUQ10_ROUND(static_metrics->MaxGl2clkFrequency); - pptable->MinGl2clkFrequency = - SMUQ10_ROUND(static_metrics->MinGl2clkFrequency); + pptable->MaxSocketPowerLimit = static_metrics->MaxSocketPowerLimit; + pptable->MaxGfxclkFrequency = static_metrics->MaxGfxclkFrequency; + pptable->MinGfxclkFrequency = static_metrics->MinGfxclkFrequency; + pptable->MaxFclkFrequency = static_metrics->MaxFclkFrequency; + pptable->MinFclkFrequency = static_metrics->MinFclkFrequency; + pptable->MaxGl2clkFrequency = static_metrics->MaxGl2clkFrequency; + pptable->MinGl2clkFrequency = static_metrics->MinGl2clkFrequency; for (i = 0; i < ARRAY_SIZE(static_metrics->UclkFrequencyTable); ++i) - pptable->UclkFrequencyTable[i] = - SMUQ10_ROUND(static_metrics->UclkFrequencyTable[i]); + pptable->UclkFrequencyTable[i] = static_metrics->UclkFrequencyTable[i]; - pptable->SocclkFrequency = SMUQ10_ROUND(static_metrics->SocclkFrequency); - pptable->LclkFrequency = SMUQ10_ROUND(static_metrics->LclkFrequency); - pptable->VclkFrequency = SMUQ10_ROUND(static_metrics->VclkFrequency); - pptable->DclkFrequency = SMUQ10_ROUND(static_metrics->DclkFrequency); + pptable->SocclkFrequency = static_metrics->SocclkFrequency; + pptable->LclkFrequency = static_metrics->LclkFrequency; + pptable->VclkFrequency = static_metrics->VclkFrequency; + pptable->DclkFrequency = static_metrics->DclkFrequency; - pptable->CTFLimitMID = SMUQ10_ROUND(static_metrics->CTFLimit_MID); - pptable->CTFLimitAID = SMUQ10_ROUND(static_metrics->CTFLimit_AID); - pptable->CTFLimitXCD = SMUQ10_ROUND(static_metrics->CTFLimit_XCD); - pptable->CTFLimitHBM = SMUQ10_ROUND(static_metrics->CTFLimit_HBM); - pptable->ThermalLimitMID = SMUQ10_ROUND(static_metrics->ThermalLimit_MID); - pptable->ThermalLimitAID = SMUQ10_ROUND(static_metrics->ThermalLimit_AID); - pptable->ThermalLimitXCD = SMUQ10_ROUND(static_metrics->ThermalLimit_XCD); - pptable->ThermalLimitHBM = SMUQ10_ROUND(static_metrics->ThermalLimit_HBM); + pptable->CTFLimitMID = static_metrics->CTFLimit_MID; + pptable->CTFLimitAID = static_metrics->CTFLimit_AID; + pptable->CTFLimitXCD = static_metrics->CTFLimit_XCD; + pptable->CTFLimitHBM = static_metrics->CTFLimit_HBM; + pptable->ThermalLimitMID = static_metrics->ThermalLimit_MID; + pptable->ThermalLimitAID = static_metrics->ThermalLimit_AID; + pptable->ThermalLimitXCD = static_metrics->ThermalLimit_XCD; + pptable->ThermalLimitHBM = static_metrics->ThermalLimit_HBM; /* use MID0 serial number by default */ pptable->PublicSerialNumberMID = @@ -1312,23 +1313,21 @@ static int smu_v15_0_8_system_features_control(struct smu_context *smu, static int smu_v15_0_8_get_enabled_mask(struct smu_context *smu, struct smu_feature_bits *feature_mask) { - struct smu_msg_args args = { - .msg = SMU_MSG_GetEnabledSmuFeatures, - .num_args = 0, - .num_out_args = 2, - }; + uint32_t out[2]; int ret; if (!feature_mask) return -EINVAL; - ret = smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); + ret = smu_cmn_send_smc_msg_with_params(smu, + SMU_MSG_GetEnabledSmuFeatures, + NULL, 0, + out, ARRAY_SIZE(out)); if (ret) return ret; - smu_feature_bits_from_arr32(feature_mask, args.out_args, - SMU_FEATURE_NUM_DEFAULT); + smu_feature_bits_from_arr32(feature_mask, out, SMU_FEATURE_NUM_DEFAULT); return 0; } @@ -1601,6 +1600,81 @@ static ssize_t smu_v15_0_8_get_temp_metrics(struct smu_context *smu, } } +static ssize_t smu_v15_0_8_get_xcp_metrics(struct smu_context *smu, int xcp_id, + void *table) +{ + struct smu_table_context *smu_table = &smu->smu_table; + const u8 num_jpeg_rings = NUM_JPEG_RINGS_FW; + struct smu_v15_0_8_partition_metrics *xcp_metrics; + MetricsTable_t *metrics; + struct amdgpu_device *adev = smu->adev; + int ret, inst, i, j, k, idx; + struct amdgpu_xcp *xcp; + u32 inst_mask; + + if (!table) + return sizeof(*xcp_metrics); + + for_each_xcp(adev->xcp_mgr, xcp, i) { + if (xcp->id == xcp_id) + break; + } + if (i == adev->xcp_mgr->num_xcps) + return -EINVAL; + + xcp_metrics = (struct smu_v15_0_8_partition_metrics *)table; + smu_v15_0_8_partition_metrics_init(xcp_metrics, 1, 1); + + ret = smu_v15_0_8_get_metrics_table_internal(smu, 1, NULL); + if (ret) + return ret; + + metrics = (MetricsTable_t *)smu_table->metrics_table; + + amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); + idx = 0; + for_each_inst(k, inst_mask) { + /* Both JPEG and VCN has same instances */ + inst = GET_INST(VCN, k); + for (j = 0; j < num_jpeg_rings; ++j) { + xcp_metrics->jpeg_busy[(idx * num_jpeg_rings) + j] = + SMUQ10_ROUND(metrics->JpegBusy[(inst * num_jpeg_rings) + j]); + } + xcp_metrics->vcn_busy[idx] = + SMUQ10_ROUND(metrics->VcnBusy[inst]); + + xcp_metrics->current_vclk[idx] = SMUQ10_ROUND(metrics->VclkFrequency[inst]); + xcp_metrics->current_dclk[idx] = SMUQ10_ROUND(metrics->DclkFrequency[inst]); + + idx++; + } + + amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); + idx = 0; + for_each_inst(k, inst_mask) { + inst = GET_INST(GC, k); + xcp_metrics->current_gfxclk[idx] = + SMUQ10_ROUND(metrics->GfxclkFrequency[inst]); + + xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(metrics->GfxBusy[inst]); + xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(metrics->GfxBusyAcc[inst]); + xcp_metrics->gfx_below_host_limit_ppt_acc[idx] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]); + xcp_metrics->gfx_below_host_limit_thm_acc[idx] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]); + xcp_metrics->gfx_low_utilization_acc[idx] = + SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]); + xcp_metrics->gfx_below_host_limit_total_acc[idx] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]); + idx++; + } + + xcp_metrics->accumulation_counter = metrics->AccumulationCounter; + xcp_metrics->firmware_timestamp = metrics->Timestamp; + + return sizeof(*xcp_metrics); +} + static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; @@ -1627,17 +1701,23 @@ static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table if (adev->umc.active_mask) { u64 mask = adev->umc.active_mask; int out_idx = 0; + u16 max_hbm_temp = 0; int stack_idx; - if (unlikely(hweight64(mask)/4 > SMU_15_0_8_MAX_HBM_STACKS)) + if (unlikely(hweight64(mask) / 4 > SMU_15_0_8_MAX_HBM_STACKS)) { dev_warn(adev->dev, "Invalid umc mask %lld\n", mask); - else { + } else { for_each_hbm_stack(stack_idx, mask) { + u16 temp; + if (!hbm_stack_mask_valid(mask)) continue; - gpu_metrics->temperature_hbm[out_idx++] = - SMUQ10_ROUND(metrics->HbmTemperature[stack_idx]); + temp = SMUQ10_ROUND(metrics->HbmTemperature[stack_idx]); + gpu_metrics->temperature_hbm[out_idx++] = temp; + if (temp > max_hbm_temp) + max_hbm_temp = temp; } + gpu_metrics->temperature_mem = max_hbm_temp; } } @@ -2199,6 +2279,71 @@ static int smu_v15_0_8_get_ppt_limit(struct smu_context *smu, return -EOPNOTSUPP; } +static uint32_t smu_v15_0_8_get_throttler_status(struct smu_context *smu) +{ + struct smu_power_context *smu_power = &smu->smu_power; + struct smu_15_0_power_context *power_context = smu_power->power_context; + uint32_t throttler_status = 0; + + throttler_status = atomic_read(&power_context->throttle_status); + dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status); + + return throttler_status; +} + +static const char *const throttling_logging_label[] = { + [THROTTLER_PROCHOT_BIT] = "Prochot", + [THROTTLER_THERMAL_SOCKET_BIT] = "SOC", + [THROTTLER_THERMAL_VR_BIT] = "VR", + [THROTTLER_THERMAL_HBM_BIT] = "HBM" +}; + +static void smu_v15_0_8_log_thermal_throttling_event(struct smu_context *smu) +{ + int throttler_idx, throttling_events = 0, buf_idx = 0; + struct amdgpu_device *adev = smu->adev; + uint32_t throttler_status; + char log_buf[256]; + + throttler_status = smu_v15_0_8_get_throttler_status(smu); + if (!throttler_status) + return; + + memset(log_buf, 0, sizeof(log_buf)); + for (throttler_idx = 0; + throttler_idx < ARRAY_SIZE(throttling_logging_label); + throttler_idx++) { + if (throttler_status & (1U << throttler_idx)) { + throttling_events++; + buf_idx += snprintf( + log_buf + buf_idx, sizeof(log_buf) - buf_idx, + "%s%s", throttling_events > 1 ? " and " : "", + throttling_logging_label[throttler_idx]); + if (buf_idx >= sizeof(log_buf)) { + dev_err(adev->dev, "buffer overflow!\n"); + log_buf[sizeof(log_buf) - 1] = '\0'; + break; + } + } + } + + dev_warn(adev->dev, + "WARN: GPU is throttled, expect performance decrease. %s.\n", + log_buf); + kgd2kfd_smi_event_throttle( + smu->adev->kfd.dev, + smu_cmn_get_indep_throttler_status(throttler_status, + smu_v15_0_8_throttler_map)); +} + +static int smu_v15_0_8_enable_thermal_alert(struct smu_context *smu) +{ + if (!smu->irq_source.num_types) + return 0; + + return amdgpu_irq_get(smu->adev, &smu->irq_source, 0); +} + static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .init_allowed_features = smu_v15_0_8_init_allowed_features, .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, @@ -2216,10 +2361,14 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .get_enabled_mask = smu_v15_0_8_get_enabled_mask, .feature_is_enabled = smu_cmn_feature_is_enabled, .register_irq_handler = smu_v15_0_8_register_irq_handler, + .enable_thermal_alert = smu_v15_0_8_enable_thermal_alert, + .disable_thermal_alert = smu_v15_0_disable_thermal_alert, + .log_thermal_throttling_event = smu_v15_0_8_log_thermal_throttling_event, .setup_pptable = smu_v15_0_8_setup_pptable, .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .wait_for_event = smu_v15_0_wait_for_event, .get_pm_metrics = smu_v15_0_8_get_pm_metrics, + .get_xcp_metrics = smu_v15_0_8_get_xcp_metrics, .mode2_reset = smu_v15_0_8_mode2_reset, .get_dpm_ultimate_freq = smu_v15_0_8_get_dpm_ultimate_freq, .get_gpu_metrics = smu_v15_0_8_get_gpu_metrics, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h index 398ce4482174..4dfc40aaffcb 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h @@ -309,5 +309,39 @@ DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpuboard_temp_metrics, DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_baseboard_temp_metrics, SMU_15_0_8_BASEBOARD_TEMP_METRICS_FIELDS); +#define SMU_15_0_8_PARTITION_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ + SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_gfxclk, SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_vclk, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_dclk, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U8), gfx_busy_inst, SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U8), \ + jpeg_busy, SMU_15_0_8_MAX_JPEG); \ + SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U8), \ + vcn_busy, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(NONE), SMU_MTYPE(U64), \ + gfx_busy_acc, SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_low_utilization_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \ + SMU_MTYPE(U64), firmware_timestamp); + +DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_partition_metrics, + SMU_15_0_8_PARTITION_METRICS_FIELDS); #endif #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 3d49e58794d2..546e64e3ba9c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -127,6 +127,61 @@ int smu_cmn_wait_for_response(struct smu_context *smu) return smu_msg_wait_response(&smu->msg_ctl, 0); } +/** + * smu_cmn_send_smc_msg_with_params_ext - send an SMU message with 0..N args + * @smu: pointer to an SMU context + * @msg: message to send + * @params: optional input argument array + * @num_params: number of input arguments in @params + * @read_args: optional output argument array + * @num_read_args: number of output arguments to read back + * @flags: message flags (SMU_MSG_FLAG_*) + * @timeout: per-message timeout in us (0 = use default) + * + * This helper keeps the raw protocol semantics of struct smu_msg_args while + * hiding the per-call boilerplate. It is intended for true multi-parameter + * messages. Legacy wrappers such as smu_cmn_send_smc_msg() retain their + * existing single-zero-parameter behavior for compatibility. + * + * Return: 0 on success, -errno on failure. + */ +int smu_cmn_send_smc_msg_with_params_ext(struct smu_context *smu, + enum smu_message_type msg, + const uint32_t *params, + size_t num_params, + uint32_t *read_args, + size_t num_read_args, + uint32_t flags, + uint32_t timeout) +{ + struct smu_msg_ctl *ctl = &smu->msg_ctl; + struct smu_msg_args args = { + .msg = msg, + .num_args = num_params, + .num_out_args = num_read_args, + .flags = flags, + .timeout = timeout, + }; + int ret; + + if ((num_params && !params) || (num_read_args && !read_args)) + return -EINVAL; + + if (num_params > SMU_MSG_MAX_ARGS || num_read_args > SMU_MSG_MAX_ARGS) + return -EINVAL; + + if (num_params) + memcpy(args.args, params, num_params * sizeof(*params)); + + ret = ctl->ops->send_msg(ctl, &args); + + if (num_read_args) + memcpy(read_args, args.out_args, + num_read_args * sizeof(*read_args)); + + return ret; +} + /** * smu_cmn_send_smc_msg_with_param -- send a message with parameter * @smu: pointer to an SMU context @@ -164,23 +219,9 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, uint32_t param, uint32_t *read_arg) { - struct smu_msg_ctl *ctl = &smu->msg_ctl; - struct smu_msg_args args = { - .msg = msg, - .args[0] = param, - .num_args = 1, - .num_out_args = read_arg ? 1 : 0, - .flags = 0, - .timeout = 0, - }; - int ret; - - ret = ctl->ops->send_msg(ctl, &args); - - if (read_arg) - *read_arg = args.out_args[0]; - - return ret; + return smu_cmn_send_smc_msg_with_params(smu, msg, + ¶m, 1, + read_arg, read_arg ? 1 : 0); } int smu_cmn_send_smc_msg(struct smu_context *smu, @@ -1071,13 +1112,12 @@ int smu_cmn_update_table_read_arg(struct smu_context *smu, struct amdgpu_device *adev = smu->adev; struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *table = &smu_table->driver_table; - struct smu_msg_ctl *ctl = &smu->msg_ctl; - struct smu_msg_args args; int table_id = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_TABLE, table_index); uint32_t table_size; int ret = 0; + uint32_t param; if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) return -EINVAL; @@ -1093,18 +1133,14 @@ int smu_cmn_update_table_read_arg(struct smu_context *smu, amdgpu_hdp_flush(adev, NULL); } - args.msg = drv2smu ? SMU_MSG_TransferTableDram2Smu : SMU_MSG_TransferTableSmu2Dram; - args.args[0] = ((argument & 0xFFFF) << 16) | (table_id & 0xffff); - args.num_args = 1; - args.out_args[0] = 0; - args.num_out_args = read_arg ? 1 : 0; - args.flags = read_arg ? SMU_MSG_FLAG_FORCE_READ_ARG : 0; - args.timeout = 0; + param = ((argument & 0xFFFF) << 16) | (table_id & 0xffff); - ret = ctl->ops->send_msg(ctl, &args); - - if (read_arg) - *read_arg = args.out_args[0]; + ret = smu_cmn_send_smc_msg_with_params_ext( + smu, + drv2smu ? SMU_MSG_TransferTableDram2Smu : + SMU_MSG_TransferTableSmu2Dram, + ¶m, 1, read_arg, read_arg ? 1 : 0, + read_arg ? SMU_MSG_FLAG_FORCE_READ_ARG : 0, 0); if (ret) return ret; @@ -1370,7 +1406,7 @@ int smu_cmn_print_dpm_clk_levels(struct smu_context *smu, level_index = 1; } - if (!is_fine_grained) { + if (!is_fine_grained || count == 1) { for (i = 0; i < count; i++) { freq_match = !is_deep_sleep && smu_cmn_freqs_match( diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index c6ac0e876aea..0e119965ce13 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -118,6 +118,28 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, uint32_t param, uint32_t *read_arg); +int smu_cmn_send_smc_msg_with_params_ext(struct smu_context *smu, + enum smu_message_type msg, + const uint32_t *params, + size_t num_params, + uint32_t *read_args, + size_t num_read_args, + uint32_t flags, + uint32_t timeout); + +static inline int smu_cmn_send_smc_msg_with_params(struct smu_context *smu, + enum smu_message_type msg, + const uint32_t *params, + size_t num_params, + uint32_t *read_args, + size_t num_read_args) +{ + return smu_cmn_send_smc_msg_with_params_ext(smu, msg, + params, num_params, + read_args, num_read_args, + 0, 0); +} + int smu_cmn_send_smc_msg(struct smu_context *smu, enum smu_message_type msg, uint32_t *read_arg); diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c index cb6498c30834..c22e53e84207 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c @@ -139,7 +139,8 @@ static int amdgpu_ras_get_ras_safe_fb_addr_ranges(struct ras_core_context *ras_c struct amdgpu_mem_partition_info *mem_ranges; uint32_t i = 0; - if (cmd->input_size != sizeof(*input_data)) + if ((cmd->input_size != sizeof(*input_data)) || + (cmd->output_buf_size < sizeof(*ranges))) return RAS_CMD__ERROR_INVALID_INPUT_DATA; mem_ranges = adev->gmc.mem_partitions; @@ -207,7 +208,8 @@ static int amdgpu_ras_translate_fb_address(struct ras_core_context *ras_core, (struct ras_cmd_translate_fb_address_rsp *)cmd->output_buff_raw; int ret = RAS_CMD__ERROR_GENERIC; - if (cmd->input_size != sizeof(struct ras_cmd_translate_fb_address_req)) + if ((cmd->input_size != sizeof(struct ras_cmd_translate_fb_address_req)) || + (cmd->output_buf_size < sizeof(*rsp_buff))) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; if ((req_buff->src_addr_type >= RAS_FB_ADDR_UNKNOWN) || @@ -279,7 +281,7 @@ int amdgpu_ras_submit_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx cmd->cmd_res = res; - if (cmd->output_size > cmd->output_buf_size) { + if (!res && (cmd->output_size > cmd->output_buf_size)) { RAS_DEV_ERR(cmd_core->dev, "Output size 0x%x exceeds output buffer size 0x%x!\n", cmd->output_size, cmd->output_buf_size); diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index ad8862d43263..a22d1aebbeb9 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -291,6 +291,8 @@ static int amdgpu_ras_mgr_sw_init(struct amdgpu_ip_block *ip_block) con->uniras_enabled = false; if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || adev->debug_enable_ras_aca) con->uniras_enabled = true; else @@ -307,13 +309,17 @@ static int amdgpu_ras_mgr_sw_init(struct amdgpu_ip_block *ip_block) if (!ras_mgr->ras_core) { RAS_DEV_ERR(adev, "Failed to create ras core!\n"); ret = -EINVAL; - goto err; + goto err1; } ras_mgr->ras_core->dev = adev; amdgpu_ras_process_init(adev); - ras_core_sw_init(ras_mgr->ras_core); + ret = ras_core_sw_init(ras_mgr->ras_core); + if (ret) { + RAS_DEV_ERR(adev, "ras_core_sw_init failed! ret:%d\n", ret); + goto err2; + } amdgpu_ras_mgr_init_event_mgr(ras_mgr->ras_core); if (amdgpu_sriov_vf(adev)) { @@ -321,14 +327,22 @@ static int amdgpu_ras_mgr_sw_init(struct amdgpu_ip_block *ip_block) if (ret) { RAS_DEV_ERR(adev, "Virt ras sw_init failed! ret:%d\n", ret); - goto err; + goto err3; } } return 0; -err: +err3: + if (ras_mgr->ras_core) + ras_core_sw_fini(ras_mgr->ras_core); +err2: + amdgpu_ras_process_fini(adev); + if (ras_mgr->ras_core) + ras_core_destroy(ras_mgr->ras_core); +err1: kfree(ras_mgr); + con->ras_mgr = NULL; return ret; } @@ -496,8 +510,10 @@ uint64_t amdgpu_ras_mgr_gen_ras_event_seqno(struct amdgpu_device *adev, if ((seqno_type == RAS_SEQNO_TYPE_DE) || (seqno_type == RAS_SEQNO_TYPE_POISON_CONSUMPTION)) { ret = ras_core_put_seqno(ras_mgr->ras_core, seqno_type, seq_no); - if (ret) + if (ret) { RAS_DEV_WARN(adev, "There are too many ras interrupts!"); + return 0; + } } return seq_no; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c index fb4d375e87b2..c2761f3d06a0 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c @@ -192,8 +192,17 @@ static int amdgpu_virt_ras_get_cper_snapshot(struct ras_core_context *ras_core, return RAS_CMD__SUCCESS; } +static bool amdgpu_virt_ras_check_batch_cached(struct ras_cmd_batch_trace_record_rsp *rsp, + uint64_t batch_id) +{ + return rsp->real_batch_num && + rsp->real_batch_num <= RAS_CMD_MAX_BATCH_NUM && + batch_id >= rsp->start_batch_id && + (batch_id - rsp->start_batch_id) < rsp->real_batch_num; +} + static int amdgpu_virt_ras_get_batch_records(struct ras_core_context *ras_core, uint64_t batch_id, - struct ras_log_info **trace_arr, uint32_t arr_num, + struct ras_log_info *trace_arr, uint32_t arr_num, struct ras_cmd_batch_trace_record_rsp *rsp_cache) { struct ras_cmd_batch_trace_record_req req = { @@ -204,27 +213,34 @@ static int amdgpu_virt_ras_get_batch_records(struct ras_core_context *ras_core, struct batch_ras_trace_info *batch; int ret = 0; uint32_t i; + uint32_t idx; - if (!rsp->real_batch_num || (batch_id < rsp->start_batch_id) || - (batch_id >= (rsp->start_batch_id + rsp->real_batch_num))) { - + if (!amdgpu_virt_ras_check_batch_cached(rsp, batch_id)) { memset(rsp, 0, sizeof(*rsp)); ret = amdgpu_virt_ras_send_remote_cmd(ras_core, RAS_CMD__GET_BATCH_TRACE_RECORD, &req, sizeof(req), rsp, sizeof(*rsp)); if (ret) return -EPIPE; + + if (!amdgpu_virt_ras_check_batch_cached(rsp, batch_id)) { + memset(rsp, 0, sizeof(*rsp)); + return -EIO; + } } - batch = &rsp->batchs[batch_id - rsp->start_batch_id]; - if (batch_id != batch->batch_id) - return -ENODATA; - - for (i = 0; i < batch->trace_num; i++) { - if (i >= arr_num) - break; - trace_arr[i] = &rsp->records[batch->offset + i]; + idx = (uint32_t)(batch_id - rsp->start_batch_id); + batch = &rsp->batchs[idx]; + if (batch_id != batch->batch_id || + batch->trace_num > MAX_RECORD_PER_BATCH || + (uint32_t)batch->offset + batch->trace_num > RAS_CMD_MAX_TRACE_NUM) { + memset(rsp, 0, sizeof(*rsp)); + return -EIO; } + for (i = 0; i < batch->trace_num && i < arr_num; i++) + memcpy(&trace_arr[i], + &rsp->records[batch->offset + i], sizeof(*trace_arr)); + return i; } @@ -240,19 +256,22 @@ static int amdgpu_virt_ras_get_cper_records(struct ras_core_context *ras_core, (struct ras_cmd_cper_record_rsp *)cmd->output_buff_raw; struct ras_log_batch_overview *overview = &virt_ras->batch_mgr.batch_overview; struct ras_cmd_batch_trace_record_rsp *rsp_cache = &virt_ras->batch_mgr.batch_trace; - struct ras_log_info **trace; + struct ras_log_info *trace; + uint32_t trace_count = MAX_RECORD_PER_BATCH; uint32_t offset = 0, real_data_len = 0; uint64_t batch_id; uint8_t *out_buf; int ret = 0, i, count; - if (cmd->input_size != sizeof(struct ras_cmd_cper_record_req)) + if (cmd->input_size != sizeof(struct ras_cmd_cper_record_req) || + (cmd->output_buf_size < sizeof(*rsp))) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; - if (!req->buf_size || !req->buf_ptr || !req->cper_num) + if (!req->buf_size || !req->buf_ptr || !req->cper_num || + req->buf_size > RAS_CMD_MAX_CPER_BUF_SZ) return RAS_CMD__ERROR_INVALID_INPUT_DATA; - trace = kzalloc_objs(*trace, MAX_RECORD_PER_BATCH); + trace = kzalloc_objs(*trace, trace_count); if (!trace) return RAS_CMD__ERROR_GENERIC; @@ -269,7 +288,7 @@ static int amdgpu_virt_ras_get_cper_records(struct ras_core_context *ras_core, if (batch_id >= overview->last_batch_id) break; count = amdgpu_virt_ras_get_batch_records(ras_core, batch_id, - trace, MAX_RECORD_PER_BATCH, + trace, trace_count, rsp_cache); if (count > 0) { ret = ras_cper_generate_cper(ras_core, trace, count, @@ -455,7 +474,7 @@ int amdgpu_virt_ras_handle_cmd(struct ras_core_context *ras_core, cmd->cmd_res = res; - if (cmd->output_size > cmd->output_buf_size) { + if (!res && (cmd->output_size > cmd->output_buf_size)) { RAS_DEV_ERR(ras_core->dev, "Output data size 0x%x exceeds buffer size 0x%x!\n", cmd->output_size, cmd->output_buf_size); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h index 6449d7b8627d..c059fcebaf00 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h @@ -329,7 +329,6 @@ struct ras_core_context { struct ras_gfx ras_gfx; struct ras_mp1 ras_mp1; struct ras_process ras_proc; - struct ras_cmd_mgr ras_cmd; struct ras_log_ring ras_log_ring; const struct ras_sys_func *sys_fn; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c index 4f89810d85a1..abd004eee95e 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c @@ -28,20 +28,6 @@ #define RAS_CMD_MINOR_VERSION 0 #define RAS_CMD_VERSION (((RAS_CMD_MAJOR_VERSION) << 10) | (RAS_CMD_MINOR_VERSION)) -static int ras_cmd_add_device(struct ras_core_context *ras_core) -{ - INIT_LIST_HEAD(&ras_core->ras_cmd.head); - ras_core->ras_cmd.ras_core = ras_core; - ras_core->ras_cmd.dev_handle = (uintptr_t)ras_core ^ RAS_CMD_DEV_HANDLE_MAGIC; - return 0; -} - -static int ras_cmd_remove_device(struct ras_core_context *ras_core) -{ - memset(&ras_core->ras_cmd, 0, sizeof(ras_core->ras_cmd)); - return 0; -} - static int ras_get_block_ecc_info(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd, void *data) { @@ -52,7 +38,8 @@ static int ras_get_block_ecc_info(struct ras_core_context *ras_core, struct ras_ecc_count err_data; int ret; - if (cmd->input_size != sizeof(struct ras_cmd_block_ecc_info_req)) + if ((cmd->input_size != sizeof(struct ras_cmd_block_ecc_info_req)) || + (cmd->output_buf_size < sizeof(*output_data))) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; memset(&err_data, 0, sizeof(err_data)); @@ -87,25 +74,31 @@ static int ras_cmd_get_group_bad_pages(struct ras_core_context *ras_core, struct eeprom_umc_record record; struct ras_cmd_bad_page_record *ras_cmd_record; uint32_t i = 0, bp_cnt = 0, group_cnt = 0; + int ret = RAS_CMD__SUCCESS; output_data->bp_in_group = 0; output_data->group_index = 0; + mutex_lock(&ras_core->ras_umc.umc_lock); bp_cnt = ras_umc_get_badpage_count(ras_core); if (bp_cnt) { output_data->group_index = group_index; group_cnt = bp_cnt / RAS_CMD_MAX_BAD_PAGES_PER_GROUP + ((bp_cnt % RAS_CMD_MAX_BAD_PAGES_PER_GROUP) ? 1 : 0); - if (group_index >= group_cnt) - return RAS_CMD__ERROR_INVALID_INPUT_DATA; + if (group_index >= group_cnt) { + ret = RAS_CMD__ERROR_INVALID_INPUT_DATA; + goto out; + } i = group_index * RAS_CMD_MAX_BAD_PAGES_PER_GROUP; for (; i < bp_cnt && output_data->bp_in_group < RAS_CMD_MAX_BAD_PAGES_PER_GROUP; i++) { - if (ras_umc_get_badpage_record(ras_core, i, &record)) - return RAS_CMD__ERROR_GENERIC; + if (ras_umc_get_badpage_record(ras_core, i, &record)) { + ret = RAS_CMD__ERROR_GENERIC; + goto out; + } ras_cmd_record = &output_data->records[i % RAS_CMD_MAX_BAD_PAGES_PER_GROUP]; @@ -115,7 +108,10 @@ static int ras_cmd_get_group_bad_pages(struct ras_core_context *ras_core, } } output_data->bp_total_cnt = bp_cnt; - return RAS_CMD__SUCCESS; + +out: + mutex_unlock(&ras_core->ras_umc.umc_lock); + return ret; } static int ras_cmd_get_bad_pages(struct ras_core_context *ras_core, @@ -127,7 +123,8 @@ static int ras_cmd_get_bad_pages(struct ras_core_context *ras_core, (struct ras_cmd_bad_pages_info_rsp *)cmd->output_buff_raw; int ret; - if (cmd->input_size != sizeof(struct ras_cmd_bad_pages_info_req)) + if ((cmd->input_size != sizeof(struct ras_cmd_bad_pages_info_req)) || + (cmd->output_buf_size < sizeof(*output_data))) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; ret = ras_cmd_get_group_bad_pages(ras_core, input_data->group_index, output_data); @@ -182,7 +179,8 @@ static int ras_cmd_get_cper_snapshot(struct ras_core_context *ras_core, (struct ras_cmd_cper_snapshot_rsp *)cmd->output_buff_raw; struct ras_log_batch_overview overview; - if (cmd->input_size != sizeof(struct ras_cmd_cper_snapshot_req)) + if ((cmd->input_size != sizeof(struct ras_cmd_cper_snapshot_req)) || + (cmd->output_buf_size < sizeof(*output_data))) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; ras_log_ring_get_batch_overview(ras_core, &overview); @@ -204,23 +202,32 @@ static int ras_cmd_get_cper_records(struct ras_core_context *ras_core, (struct ras_cmd_cper_record_req *)cmd->input_buff_raw; struct ras_cmd_cper_record_rsp *rsp = (struct ras_cmd_cper_record_rsp *)cmd->output_buff_raw; - struct ras_log_info *trace[MAX_RECORD_PER_BATCH] = {0}; + struct ras_log_info *trace = NULL; + uint32_t trace_count = MAX_RECORD_PER_BATCH; struct ras_log_batch_overview overview; uint32_t offset = 0, real_data_len = 0; uint64_t batch_id; - uint8_t *buffer; + uint8_t *buffer = NULL; int ret = 0, i, count; - if (cmd->input_size != sizeof(struct ras_cmd_cper_record_req)) + if ((cmd->input_size != sizeof(struct ras_cmd_cper_record_req)) || + (cmd->output_buf_size < sizeof(*rsp))) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; - if (!req->buf_size || !req->buf_ptr || !req->cper_num) + if (!req->buf_size || !req->buf_ptr || !req->cper_num || + req->buf_size > RAS_CMD_MAX_CPER_BUF_SZ) return RAS_CMD__ERROR_INVALID_INPUT_DATA; buffer = kzalloc(req->buf_size, GFP_KERNEL); if (!buffer) return RAS_CMD__ERROR_GENERIC; + trace = kcalloc(trace_count, sizeof(*trace), GFP_KERNEL); + if (!trace) { + ret = RAS_CMD__ERROR_GENERIC; + goto out; + } + ras_log_ring_get_batch_overview(ras_core, &overview); for (i = 0; i < req->cper_num; i++) { batch_id = req->cper_start_id + i; @@ -228,7 +235,7 @@ static int ras_cmd_get_cper_records(struct ras_core_context *ras_core, break; count = ras_log_ring_get_batch_records(ras_core, batch_id, trace, - ARRAY_SIZE(trace)); + trace_count); if (count > 0) { ret = ras_cper_generate_cper(ras_core, trace, count, &buffer[offset], req->buf_size - offset, &real_data_len); @@ -241,8 +248,8 @@ static int ras_cmd_get_cper_records(struct ras_core_context *ras_core, if ((ret && (ret != -ENOMEM)) || copy_to_user(u64_to_user_ptr(req->buf_ptr), buffer, offset)) { - kfree(buffer); - return RAS_CMD__ERROR_GENERIC; + ret = RAS_CMD__ERROR_GENERIC; + goto out; } rsp->real_data_size = offset; @@ -251,10 +258,12 @@ static int ras_cmd_get_cper_records(struct ras_core_context *ras_core, rsp->version = 0; cmd->output_size = sizeof(struct ras_cmd_cper_record_rsp); + ret = RAS_CMD__SUCCESS; +out: + kfree(trace); kfree(buffer); - - return RAS_CMD__SUCCESS; + return ret; } static int ras_cmd_get_batch_trace_snapshot(struct ras_core_context *ras_core, @@ -265,7 +274,8 @@ static int ras_cmd_get_batch_trace_snapshot(struct ras_core_context *ras_core, struct ras_log_batch_overview overview; - if (cmd->input_size != sizeof(struct ras_cmd_batch_trace_snapshot_req)) + if ((cmd->input_size != sizeof(struct ras_cmd_batch_trace_snapshot_req)) || + (cmd->output_buf_size < sizeof(*rsp))) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; ras_log_ring_get_batch_overview(ras_core, &overview); @@ -287,13 +297,15 @@ static int ras_cmd_get_batch_trace_records(struct ras_core_context *ras_core, struct ras_cmd_batch_trace_record_rsp *output_data = (struct ras_cmd_batch_trace_record_rsp *)cmd->output_buff_raw; struct ras_log_batch_overview overview; - struct ras_log_info *trace_arry[MAX_RECORD_PER_BATCH] = {0}; + struct ras_log_info *trace_arry = NULL; + uint32_t trace_count = MAX_RECORD_PER_BATCH; struct ras_log_info *record; int i, j, count = 0, offset = 0; uint64_t id; bool completed = false; - if (cmd->input_size != sizeof(struct ras_cmd_batch_trace_record_req)) + if ((cmd->input_size != sizeof(struct ras_cmd_batch_trace_record_req)) || + (cmd->output_buf_size < sizeof(*output_data))) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; if ((!input_data->batch_num) || (input_data->batch_num > RAS_CMD_MAX_BATCH_NUM)) @@ -304,6 +316,10 @@ static int ras_cmd_get_batch_trace_records(struct ras_core_context *ras_core, (input_data->start_batch_id >= overview.last_batch_id)) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + trace_arry = kcalloc(trace_count, sizeof(*trace_arry), GFP_KERNEL); + if (!trace_arry) + return RAS_CMD__ERROR_GENERIC; + for (i = 0; i < input_data->batch_num; i++) { id = input_data->start_batch_id + i; if (id >= overview.last_batch_id) { @@ -312,17 +328,17 @@ static int ras_cmd_get_batch_trace_records(struct ras_core_context *ras_core, } count = ras_log_ring_get_batch_records(ras_core, - id, trace_arry, ARRAY_SIZE(trace_arry)); + id, trace_arry, trace_count); if (count > 0) { if ((offset + count) > RAS_CMD_MAX_TRACE_NUM) break; for (j = 0; j < count; j++) { record = &output_data->records[offset + j]; - record->seqno = trace_arry[j]->seqno; - record->timestamp = trace_arry[j]->timestamp; - record->event = trace_arry[j]->event; + record->seqno = trace_arry[j].seqno; + record->timestamp = trace_arry[j].timestamp; + record->event = trace_arry[j].event; memcpy(&record->aca_reg, - &trace_arry[j]->aca_reg, sizeof(trace_arry[j]->aca_reg)); + &trace_arry[j].aca_reg, sizeof(trace_arry[j].aca_reg)); } } else { count = 0; @@ -341,6 +357,8 @@ static int ras_cmd_get_batch_trace_records(struct ras_core_context *ras_core, cmd->output_size = sizeof(struct ras_cmd_batch_trace_record_rsp); + kfree(trace_arry); + return RAS_CMD__SUCCESS; } @@ -420,6 +438,10 @@ static int ras_cmd_inject_error(struct ras_core_context *ras_core, .value = req->method, }; + if ((cmd->input_size != sizeof(*req)) || + (cmd->output_buf_size < sizeof(*output_data))) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + ret = ras_psp_trigger_error(ras_core, &block_info, req->instance_mask); if (!ret) { output_data->version = 0; @@ -466,12 +488,11 @@ int rascore_handle_cmd(struct ras_core_context *ras_core, int ras_cmd_init(struct ras_core_context *ras_core) { - return ras_cmd_add_device(ras_core); + return 0; } int ras_cmd_fini(struct ras_core_context *ras_core) { - ras_cmd_remove_device(ras_core); return 0; } @@ -520,8 +541,3 @@ int ras_cmd_translate_bank_to_soc_pa(struct ras_core_context *ras_core, return ras_umc_translate_soc_pa_and_bank(ras_core, soc_pa, &umc_bank, true); } - -uint64_t ras_cmd_get_dev_handle(struct ras_core_context *ras_core) -{ - return ras_core->ras_cmd.dev_handle; -} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h index 7ea35a028987..c376e074e15d 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h @@ -29,8 +29,6 @@ #include "ras_log_ring.h" #include "ras_cper.h" -#define RAS_CMD_DEV_HANDLE_MAGIC 0xFEEDAD00UL - #define RAS_CMD_MAX_IN_SIZE 256 #define RAS_CMD_MAX_GPU_NUM 32 #define RAS_CMD_MAX_BAD_PAGES_PER_GROUP 32 @@ -107,12 +105,6 @@ enum ras_error_type { struct ras_core_context; struct ras_cmd_ctx; -struct ras_cmd_mgr { - struct list_head head; - struct ras_core_context *ras_core; - uint64_t dev_handle; -}; - struct ras_cmd_func_map { uint32_t cmd_id; int (*func)(struct ras_core_context *ras_core, @@ -405,6 +397,9 @@ struct batch_ras_trace_info { #define RAS_CMD_MAX_BATCH_NUM 300 #define RAS_CMD_MAX_TRACE_NUM 300 + +/* Upper bounds for RAS_CMD__GET_CPER_RECORD to limit kernel allocations and work. */ +#define RAS_CMD_MAX_CPER_BUF_SZ (2 * 1024U * 1024U) /* 2 MiB */ struct ras_cmd_batch_trace_record_rsp { uint32_t version; uint16_t real_batch_num; @@ -478,7 +473,6 @@ struct ras_cmd_blocks_ecc_rsp { int ras_cmd_init(struct ras_core_context *ras_core); int ras_cmd_fini(struct ras_core_context *ras_core); int rascore_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd, void *data); -uint64_t ras_cmd_get_dev_handle(struct ras_core_context *ras_core); int ras_cmd_query_interface_info(struct ras_core_context *ras_core, struct ras_query_interface_info_rsp *rsp); int ras_cmd_translate_soc_pa_to_bank(struct ras_core_context *ras_core, diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index 49b3aa7489ff..62d124a3eeac 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -196,9 +196,9 @@ uint64_t ras_core_gen_seqno(struct ras_core_context *ras_core, { uint64_t seqno = 0; - if (ras_core->sys_fn && - ras_core->sys_fn->gen_seqno) - ras_core->sys_fn->gen_seqno(ras_core, type, &seqno); + if (ras_core->sys_fn && ras_core->sys_fn->gen_seqno && + ras_core->sys_fn->gen_seqno(ras_core, type, &seqno)) + return 0; return seqno; } diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cper.c b/drivers/gpu/drm/amd/ras/rascore/ras_cper.c index 0fc7522b7ab6..6e93a13bbc4c 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cper.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cper.c @@ -175,14 +175,14 @@ static int fill_section_runtime(struct ras_core_context *ras_core, } static int cper_generate_runtime_record(struct ras_core_context *ras_core, - struct cper_section_hdr *hdr, struct ras_log_info **trace_arr, uint32_t arr_num, + struct cper_section_hdr *hdr, struct ras_log_info *trace_arr, uint32_t arr_num, enum ras_cper_severity sev) { struct cper_section_descriptor *descriptor; struct cper_section_runtime *runtime; int i; - fill_section_hdr(ras_core, hdr, RAS_CPER_TYPE_RUNTIME, sev, trace_arr[0]); + fill_section_hdr(ras_core, hdr, RAS_CPER_TYPE_RUNTIME, sev, &trace_arr[0]); hdr->record_length = RAS_HDR_LEN + ((RAS_SEC_DESC_LEN + RAS_NONSTD_SEC_LEN) * arr_num); hdr->sec_cnt = arr_num; for (i = 0; i < arr_num; i++) { @@ -194,21 +194,21 @@ static int cper_generate_runtime_record(struct ras_core_context *ras_core, fill_section_descriptor(ras_core, descriptor, sev, RUNTIME, RAS_NONSTD_SEC_OFFSET(hdr->sec_cnt, i), sizeof(struct cper_section_runtime)); - fill_section_runtime(ras_core, runtime, trace_arr[i], sev); + fill_section_runtime(ras_core, runtime, &trace_arr[i], sev); } return 0; } static int cper_generate_fatal_record(struct ras_core_context *ras_core, - uint8_t *buffer, struct ras_log_info **trace_arr, uint32_t arr_num) + uint8_t *buffer, struct ras_log_info *trace_arr, uint32_t arr_num) { struct ras_cper_fatal_record record = {0}; int i = 0; for (i = 0; i < arr_num; i++) { fill_section_hdr(ras_core, &record.hdr, RAS_CPER_TYPE_FATAL, - RAS_CPER_SEV_FATAL_UE, trace_arr[i]); + RAS_CPER_SEV_FATAL_UE, &trace_arr[i]); record.hdr.record_length = RAS_HDR_LEN + RAS_SEC_DESC_LEN + RAS_FATAL_SEC_LEN; record.hdr.sec_cnt = 1; @@ -216,7 +216,7 @@ static int cper_generate_fatal_record(struct ras_core_context *ras_core, CRASHDUMP, offsetof(struct ras_cper_fatal_record, fatal), sizeof(struct cper_section_fatal)); - fill_section_fatal(ras_core, &record.fatal, trace_arr[i]); + fill_section_fatal(ras_core, &record.fatal, &trace_arr[i]); memcpy(buffer + (i * record.hdr.record_length), &record, record.hdr.record_length); @@ -271,7 +271,7 @@ static enum ras_cper_type cper_ras_log_event_to_cper_type(enum ras_log_event eve } int ras_cper_generate_cper(struct ras_core_context *ras_core, - struct ras_log_info **trace_list, uint32_t count, + struct ras_log_info *trace_list, uint32_t count, uint8_t *buf, uint32_t buf_len, uint32_t *real_data_len) { uint8_t *buffer = buf; @@ -281,14 +281,14 @@ int ras_cper_generate_cper(struct ras_core_context *ras_core, /* All the batch traces share the same event */ record_size = cper_get_record_size( - cper_ras_log_event_to_cper_type(trace_list[0]->event), count); + cper_ras_log_event_to_cper_type(trace_list[0].event), count); if ((record_size + saved_size) > buf_size) return -ENOMEM; hdr = (struct cper_section_hdr *)(buffer + saved_size); - switch (trace_list[0]->event) { + switch (trace_list[0].event) { case RAS_LOG_EVENT_RMA: cper_generate_runtime_record(ras_core, hdr, trace_list, count, RAS_CPER_SEV_RMA); break; @@ -304,7 +304,7 @@ int ras_cper_generate_cper(struct ras_core_context *ras_core, cper_generate_fatal_record(ras_core, buffer + saved_size, trace_list, count); break; default: - RAS_DEV_WARN(ras_core->dev, "Unprocessed trace event: %d\n", trace_list[0]->event); + RAS_DEV_WARN(ras_core->dev, "Unprocessed trace event: %d\n", trace_list[0].event); break; } diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cper.h b/drivers/gpu/drm/amd/ras/rascore/ras_cper.h index 076c1883c1ce..e4e3615ecc2e 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cper.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cper.h @@ -299,6 +299,6 @@ struct ras_cper_fatal_record { struct ras_core_context; struct ras_log_info; int ras_cper_generate_cper(struct ras_core_context *ras_core, - struct ras_log_info **trace_list, uint32_t count, + struct ras_log_info *trace_list, uint32_t count, uint8_t *buf, uint32_t buf_len, uint32_t *real_data_len); #endif diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c index 65c1812a10fb..34b798f45af2 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c @@ -1163,6 +1163,13 @@ static int __check_ras_table_status(struct ras_core_context *ras_core) } control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); + if (hdr->first_rec_offset < control->ras_record_offset || + control->ras_fri >= control->ras_max_record_count) { + RAS_DEV_ERR(ras_core->dev, + "RAS header invalid, ras_fri: %u, first_rec_offset:0x%x", + control->ras_fri, hdr->first_rec_offset); + return -EINVAL; + } return 0; } diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c index 29001e606d1b..f5fa80db91fb 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -270,6 +270,7 @@ int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core, struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; int i, ret, end_idx; u64 mca, ipid, ts; + u32 cu, mem_channel, mcumc_id; if (!ras_core->ras_umc.ip_func || !ras_core->ras_umc.ip_func->mca_ipid_parse) @@ -299,9 +300,10 @@ int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core, record_umc[i - rec_idx].err_type = RAS_EEPROM_ERR_NON_RECOVERABLE; ras_core->ras_umc.ip_func->mca_ipid_parse(ras_core, ipid, - (uint32_t *)&(record_umc[i - rec_idx].cu), - (uint32_t *)&(record_umc[i - rec_idx].mem_channel), - (uint32_t *)&(record_umc[i - rec_idx].mcumc_id), NULL); + &cu, &mem_channel, &mcumc_id, NULL); + record_umc[i - rec_idx].cu = (u8)cu; + record_umc[i - rec_idx].mem_channel = (u8)mem_channel; + record_umc[i - rec_idx].mcumc_id = (u8)mcumc_id; /* update bad channel bitmap */ if ((record_umc[i - rec_idx].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c index f10e856f3c8c..c37343db39df 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c @@ -265,8 +265,8 @@ void ras_log_ring_add_log_event(struct ras_core_context *ras_core, ras_log_ring_add_data(ras_core, log, batch_tag); } -static struct ras_log_info *ras_log_ring_lookup_data(struct ras_core_context *ras_core, - uint64_t idx) +static int ras_log_ring_lookup_data(struct ras_core_context *ras_core, + uint64_t idx, struct ras_log_info *log) { struct ras_log_ring *log_ring = &ras_core->ras_log_ring; unsigned long flags = 0; @@ -274,30 +274,27 @@ static struct ras_log_info *ras_log_ring_lookup_data(struct ras_core_context *ra spin_lock_irqsave(&log_ring->spin_lock, flags); data = radix_tree_lookup(&log_ring->ras_log_root, idx); + if (data) + memcpy(log, data, sizeof(*log)); spin_unlock_irqrestore(&log_ring->spin_lock, flags); - return (struct ras_log_info *)data; + return data ? 0 : -ENODATA; } int ras_log_ring_get_batch_records(struct ras_core_context *ras_core, uint64_t batch_id, - struct ras_log_info **log_arr, uint32_t arr_num) + struct ras_log_info *log_arr, uint32_t arr_num) { struct ras_log_ring *log_ring = &ras_core->ras_log_ring; uint32_t i, idx, count = 0; - void *data; - if ((batch_id >= log_ring->mono_upward_batch_id) || + if (!log_arr || !arr_num || (batch_id >= log_ring->mono_upward_batch_id) || (batch_id < log_ring->last_del_batch_id)) return -EINVAL; - for (i = 0; i < MAX_RECORD_PER_BATCH; i++) { + for (i = 0; i < MAX_RECORD_PER_BATCH && i < arr_num; i++) { idx = BATCH_IDX_TO_TREE_IDX(batch_id, i); - data = ras_log_ring_lookup_data(ras_core, idx); - if (data) { - log_arr[count++] = data; - if (count >= arr_num) - break; - } + if (!ras_log_ring_lookup_data(ras_core, idx, &log_arr[count])) + count++; } return count; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.h b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.h index 0ff6cc35678d..cb66beaa9f43 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.h @@ -86,7 +86,7 @@ void ras_log_ring_add_log_event(struct ras_core_context *ras_core, enum ras_log_event event, void *data, struct ras_log_batch_tag *tag); int ras_log_ring_get_batch_records(struct ras_core_context *ras_core, uint64_t batch_idx, - struct ras_log_info **log_arr, uint32_t arr_num); + struct ras_log_info *log_arr, uint32_t arr_num); int ras_log_ring_get_batch_overview(struct ras_core_context *ras_core, struct ras_log_batch_overview *overview); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c index c7ae005ea705..91dd730de3ce 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c @@ -391,9 +391,8 @@ static int ras_umc_update_eeprom_ram_data(struct ras_core_context *ras_core, data->space_left--; } } else { - memcpy(&data->bps[data->count], bps, sizeof(*data->bps)); - data->count++; - data->space_left--; + RAS_DEV_ERR(ras_core->dev, "Failed to convert record to nps pages!"); + return -EINVAL; } return 0; diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 714af5c889d7..e8cb782a6f8e 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -75,7 +75,7 @@ static void komeda_crtc_update_clock_ratio(struct komeda_crtc_state *kcrtc_st) */ static int komeda_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -279,7 +279,7 @@ komeda_crtc_do_flush(struct drm_crtc *crtc, static void komeda_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state, crtc); @@ -325,7 +325,7 @@ komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, static void komeda_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state, crtc); @@ -387,7 +387,7 @@ komeda_crtc_atomic_disable(struct drm_crtc *crtc, static void komeda_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c index 6ed504099188..faa8b041373a 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.c @@ -67,7 +67,7 @@ static const struct drm_driver komeda_kms_driver = { .minor = 1, }; -static void komeda_kms_atomic_commit_hw_done(struct drm_atomic_state *state) +static void komeda_kms_atomic_commit_hw_done(struct drm_atomic_commit *state) { struct drm_device *dev = state->dev; struct komeda_kms_dev *kms = to_kdev(dev); @@ -86,7 +86,7 @@ static void komeda_kms_atomic_commit_hw_done(struct drm_atomic_state *state) drm_atomic_helper_commit_hw_done(state); } -static void komeda_kms_commit_tail(struct drm_atomic_state *old_state) +static void komeda_kms_commit_tail(struct drm_atomic_commit *old_state) { struct drm_device *dev = old_state->dev; bool fence_cookie = dma_fence_begin_signalling(); @@ -153,7 +153,7 @@ static int komeda_plane_state_list_add(struct drm_plane_state *plane_st, static int komeda_crtc_normalize_zpos(struct drm_crtc *crtc, struct drm_crtc_state *crtc_st) { - struct drm_atomic_state *state = crtc_st->state; + struct drm_atomic_commit *state = crtc_st->state; struct komeda_crtc *kcrtc = to_kcrtc(crtc); struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc_st); struct komeda_plane_state *kplane_st; @@ -216,7 +216,7 @@ static int komeda_crtc_normalize_zpos(struct drm_crtc *crtc, } static int komeda_kms_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_st; @@ -228,7 +228,7 @@ static int komeda_kms_check(struct drm_device *dev, /* Komeda need to re-calculate resource assumption in every commit * so need to add all affected_planes (even unchanged) to - * drm_atomic_state. + * drm_atomic_commit. */ for_each_new_crtc_in_state(state, crtc, new_crtc_st, i) { err = drm_atomic_add_affected_planes(state, crtc); diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h index bbee6da43164..955f9f683ce3 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h @@ -155,7 +155,7 @@ struct komeda_component_output { * @komeda_scaler_state */ struct komeda_component_state { - /** @obj: tracking component_state by drm_atomic_state */ + /** @obj: tracking component_state by drm_atomic_commit */ struct drm_private_state obj; /** @component: backpointer to the component */ struct komeda_component *component; @@ -388,7 +388,7 @@ struct komeda_pipeline_funcs { * Represent a complete display pipeline and hold all functional components. */ struct komeda_pipeline { - /** @obj: link pipeline as private obj of drm_atomic_state */ + /** @obj: link pipeline as private obj of drm_atomic_commit */ struct drm_private_obj obj; /** @mdev: the parent komeda_dev */ struct komeda_dev *mdev; @@ -448,10 +448,10 @@ struct komeda_pipeline { * * NOTE: * Unlike the pipeline, pipeline_state doesn’t gather any component_state - * into it. It because all component will be managed by drm_atomic_state. + * into it. It because all component will be managed by drm_atomic_commit. */ struct komeda_pipeline_state { - /** @obj: tracking pipeline_state by drm_atomic_state */ + /** @obj: tracking pipeline_state by drm_atomic_commit */ struct drm_private_state obj; /** @pipe: backpointer to the pipeline */ struct komeda_pipeline *pipe; @@ -555,11 +555,11 @@ int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, struct komeda_pipeline_state * komeda_pipeline_get_old_state(struct komeda_pipeline *pipe, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); bool komeda_pipeline_disable(struct komeda_pipeline *pipe, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); void komeda_pipeline_update(struct komeda_pipeline *pipe, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); void komeda_complete_data_flow_cfg(struct komeda_layer *layer, struct komeda_data_flow_cfg *dflow, diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index 6f9b10cc831f..457b21397014 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -22,7 +22,7 @@ static inline bool is_switching_user(void *old, void *new) static struct komeda_pipeline_state * komeda_pipeline_get_state(struct komeda_pipeline *pipe, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv_st; @@ -35,7 +35,7 @@ komeda_pipeline_get_state(struct komeda_pipeline *pipe, struct komeda_pipeline_state * komeda_pipeline_get_old_state(struct komeda_pipeline *pipe, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv_st; @@ -47,7 +47,7 @@ komeda_pipeline_get_old_state(struct komeda_pipeline *pipe, static struct komeda_pipeline_state * komeda_pipeline_get_new_state(struct komeda_pipeline *pipe, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv_st; @@ -60,7 +60,7 @@ komeda_pipeline_get_new_state(struct komeda_pipeline *pipe, /* Assign pipeline for crtc */ static struct komeda_pipeline_state * komeda_pipeline_get_state_and_set_crtc(struct komeda_pipeline *pipe, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, struct drm_crtc *crtc) { struct komeda_pipeline_state *st; @@ -97,7 +97,7 @@ komeda_pipeline_get_state_and_set_crtc(struct komeda_pipeline *pipe, static struct komeda_component_state * komeda_component_get_state(struct komeda_component *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv_st; @@ -112,7 +112,7 @@ komeda_component_get_state(struct komeda_component *c, static struct komeda_component_state * komeda_component_get_old_state(struct komeda_component *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_private_state *priv_st; @@ -149,7 +149,7 @@ komeda_component_get_old_state(struct komeda_component *c, */ static struct komeda_component_state * komeda_component_get_state_and_set_user(struct komeda_component *c, - struct drm_atomic_state *state, + struct drm_atomic_commit *state, void *user, struct drm_crtc *crtc) { @@ -253,7 +253,7 @@ komeda_component_validate_private(struct komeda_component *c, /* Get current available scaler from the component->supported_outputs */ static struct komeda_scaler * komeda_component_get_avail_scaler(struct komeda_component *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct komeda_pipeline_state *pipe_st; u32 avail_scalers; @@ -505,7 +505,7 @@ komeda_scaler_validate(void *user, struct komeda_crtc_state *kcrtc_st, struct komeda_data_flow_cfg *dflow) { - struct drm_atomic_state *drm_st = kcrtc_st->base.state; + struct drm_atomic_commit *drm_st = kcrtc_st->base.state; struct komeda_component_state *c_st; struct komeda_scaler_state *st; struct komeda_scaler *scaler; @@ -669,7 +669,7 @@ komeda_compiz_set_input(struct komeda_compiz *compiz, struct komeda_crtc_state *kcrtc_st, struct komeda_data_flow_cfg *dflow) { - struct drm_atomic_state *drm_st = kcrtc_st->base.state; + struct drm_atomic_commit *drm_st = kcrtc_st->base.state; struct komeda_component_state *c_st, *old_st; struct komeda_compiz_input_cfg *cin; u16 compiz_w, compiz_h; @@ -1227,7 +1227,7 @@ static int komeda_pipeline_unbound_components(struct komeda_pipeline *pipe, struct komeda_pipeline_state *new) { - struct drm_atomic_state *drm_st = new->obj.state; + struct drm_atomic_commit *drm_st = new->obj.state; struct komeda_pipeline_state *old = priv_to_pipe_st(pipe->obj.state); struct komeda_component_state *c_st; struct komeda_component *c; @@ -1255,7 +1255,7 @@ komeda_pipeline_unbound_components(struct komeda_pipeline *pipe, int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, struct komeda_crtc_state *kcrtc_st) { - struct drm_atomic_state *drm_st = kcrtc_st->base.state; + struct drm_atomic_commit *drm_st = kcrtc_st->base.state; struct komeda_pipeline_state *st; /* ignore the pipeline which is not affected */ @@ -1285,7 +1285,7 @@ int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, * false: disable is complete. */ bool komeda_pipeline_disable(struct komeda_pipeline *pipe, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct komeda_pipeline_state *old; struct komeda_component *c; @@ -1330,7 +1330,7 @@ bool komeda_pipeline_disable(struct komeda_pipeline *pipe, } void komeda_pipeline_update(struct komeda_pipeline *pipe, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct komeda_pipeline_state *new = priv_to_pipe_st(pipe->obj.state); struct komeda_pipeline_state *old; diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c index 835c11fdd7ff..57a4a0c7d404 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c @@ -69,7 +69,7 @@ komeda_plane_init_data_flow(struct drm_plane_state *st, */ static int komeda_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -116,7 +116,7 @@ komeda_plane_atomic_check(struct drm_plane *plane, */ static void komeda_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { } diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c index 4b4a08cb396d..8565749a3e48 100644 --- a/drivers/gpu/drm/arm/hdlcd_crtc.c +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c @@ -175,7 +175,7 @@ static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) } static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); @@ -186,7 +186,7 @@ static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, } static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); @@ -212,7 +212,7 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, } static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_pending_vblank_event *event = crtc->state->event; @@ -236,7 +236,7 @@ static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { }; static int hdlcd_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -267,7 +267,7 @@ static int hdlcd_plane_atomic_check(struct drm_plane *plane, } static void hdlcd_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c index 18e6157b1047..ebe8e1078777 100644 --- a/drivers/gpu/drm/arm/malidp_crtc.c +++ b/drivers/gpu/drm/arm/malidp_crtc.c @@ -47,7 +47,7 @@ static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc, } static void malidp_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct malidp_drm *malidp = crtc_to_malidp_device(crtc); struct malidp_hw_device *hwdev = malidp->dev; @@ -71,7 +71,7 @@ static void malidp_crtc_atomic_enable(struct drm_crtc *crtc, } static void malidp_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -334,7 +334,7 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, } static int malidp_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index b765f6c9eea4..9abe800f598a 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -190,7 +190,7 @@ static int malidp_set_and_wait_config_valid(struct drm_device *drm) return (ret > 0) ? 0 : -ETIMEDOUT; } -static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state) +static void malidp_atomic_commit_hw_done(struct drm_atomic_commit *state) { struct drm_device *drm = state->dev; struct malidp_drm *malidp = drm_to_malidp(drm); @@ -231,7 +231,7 @@ static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state) drm_atomic_helper_commit_hw_done(state); } -static void malidp_atomic_commit_tail(struct drm_atomic_state *state) +static void malidp_atomic_commit_tail(struct drm_atomic_commit *state) { struct drm_device *drm = state->dev; struct malidp_drm *malidp = drm_to_malidp(drm); diff --git a/drivers/gpu/drm/arm/malidp_mw.c b/drivers/gpu/drm/arm/malidp_mw.c index fad343842038..f8be65119e3b 100644 --- a/drivers/gpu/drm/arm/malidp_mw.c +++ b/drivers/gpu/drm/arm/malidp_mw.c @@ -237,7 +237,7 @@ int malidp_mw_connector_init(struct drm_device *drm) } void malidp_mw_atomic_commit(struct drm_device *drm, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct malidp_drm *malidp = drm_to_malidp(drm); struct drm_writeback_connector *mw_conn = &malidp->mw_connector; diff --git a/drivers/gpu/drm/arm/malidp_mw.h b/drivers/gpu/drm/arm/malidp_mw.h index 19a007676a1d..53a2d6a956a9 100644 --- a/drivers/gpu/drm/arm/malidp_mw.h +++ b/drivers/gpu/drm/arm/malidp_mw.h @@ -10,5 +10,5 @@ int malidp_mw_connector_init(struct drm_device *drm); void malidp_mw_atomic_commit(struct drm_device *drm, - struct drm_atomic_state *old_state); + struct drm_atomic_commit *old_state); #endif diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c index 4b9876322501..60b3f2bb153b 100644 --- a/drivers/gpu/drm/arm/malidp_planes.c +++ b/drivers/gpu/drm/arm/malidp_planes.c @@ -490,7 +490,7 @@ static void malidp_de_prefetch_settings(struct malidp_plane *mp, } static int malidp_de_plane_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -779,7 +779,7 @@ static void malidp_de_set_plane_afbc(struct drm_plane *plane) } static void malidp_de_plane_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -900,7 +900,7 @@ static void malidp_de_plane_update(struct drm_plane *plane, } static void malidp_de_plane_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct malidp_plane *mp = to_malidp_plane(plane); diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index d40bb9cf9ff1..5e006212fea0 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -414,7 +414,7 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) } static int armada_drm_crtc_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -430,7 +430,7 @@ static int armada_drm_crtc_atomic_check(struct drm_crtc *crtc, } static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -446,7 +446,7 @@ static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc, } static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -474,7 +474,7 @@ static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc, } static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); @@ -512,7 +512,7 @@ static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc, } static void armada_drm_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 361fdcece4b0..3da0b857ef95 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -69,7 +69,7 @@ static inline u32 armada_csc(struct drm_plane_state *state) /* === Plane support === */ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -220,7 +220,7 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane, } static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -262,7 +262,7 @@ armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, struct drm_modeset_acquire_ctx *ctx) { - struct drm_atomic_state *state; + struct drm_atomic_commit *state; struct drm_plane_state *plane_state; int ret = 0; @@ -270,7 +270,7 @@ armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h); - state = drm_atomic_state_alloc(plane->dev); + state = drm_atomic_commit_alloc(plane->dev); if (!state) return -ENOMEM; @@ -297,7 +297,7 @@ armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, ret = drm_atomic_nonblocking_commit(state); fail: - drm_atomic_state_put(state); + drm_atomic_commit_put(state); return ret; } diff --git a/drivers/gpu/drm/armada/armada_plane.c b/drivers/gpu/drm/armada/armada_plane.c index eba12bba1e09..fe46a8e4508a 100644 --- a/drivers/gpu/drm/armada/armada_plane.c +++ b/drivers/gpu/drm/armada/armada_plane.c @@ -80,7 +80,7 @@ void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3], } int armada_drm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -130,7 +130,7 @@ int armada_drm_plane_atomic_check(struct drm_plane *plane, } static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); @@ -220,7 +220,7 @@ static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane, } static void armada_drm_primary_plane_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); diff --git a/drivers/gpu/drm/armada/armada_plane.h b/drivers/gpu/drm/armada/armada_plane.h index 368415c609a6..69bef09ea028 100644 --- a/drivers/gpu/drm/armada/armada_plane.h +++ b/drivers/gpu/drm/armada/armada_plane.h @@ -24,7 +24,7 @@ void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3], void armada_drm_plane_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state); int armada_drm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state); + struct drm_atomic_commit *state); void armada_plane_reset(struct drm_plane *plane); struct drm_plane_state *armada_plane_duplicate_state(struct drm_plane *plane); void armada_plane_destroy_state(struct drm_plane *plane, diff --git a/drivers/gpu/drm/ast/ast_2000.c b/drivers/gpu/drm/ast/ast_2000.c index fa3bc23ce098..4cf951b3533d 100644 --- a/drivers/gpu/drm/ast/ast_2000.c +++ b/drivers/gpu/drm/ast/ast_2000.c @@ -69,64 +69,59 @@ void ast_2000_set_def_ext_reg(struct ast_device *ast) } static const struct ast_dramstruct ast2000_dram_table_data[] = { - { 0x0108, 0x00000000 }, - { 0x0120, 0x00004a21 }, + AST_DRAMSTRUCT_REG(AST_REG_MCR108, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR120, 0x00004a21), AST_DRAMSTRUCT_UDELAY(67u), - { 0x0000, 0xFFFFFFFF }, - AST_DRAMSTRUCT_INIT(DRAM_TYPE, 0x00000089), - { 0x0008, 0x22331353 }, - { 0x000C, 0x0d07000b }, - { 0x0010, 0x11113333 }, - { 0x0020, 0x00110350 }, - { 0x0028, 0x1e0828f0 }, - { 0x0024, 0x00000001 }, - { 0x001C, 0x00000000 }, - { 0x0014, 0x00000003 }, + AST_DRAMSTRUCT_REG(AST_REG_MCR00, 0xffffffff), /* FIXME: This locks the MCR registers. */ + AST_DRAMSTRUCT_REG(AST_REG_MCR04, 0x00000089), /* DRAM type */ + AST_DRAMSTRUCT_REG(AST_REG_MCR08, 0x22331353), + AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x0d07000b), + AST_DRAMSTRUCT_REG(AST_REG_MCR10, 0x11113333), + AST_DRAMSTRUCT_REG(AST_REG_MCR20, 0x00110350), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x1e0828f0), + AST_DRAMSTRUCT_REG(AST_REG_MCR24, 0x00000001), + AST_DRAMSTRUCT_REG(AST_REG_MCR1C, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x00000003), AST_DRAMSTRUCT_UDELAY(67u), - { 0x0018, 0x00000131 }, - { 0x0014, 0x00000001 }, + AST_DRAMSTRUCT_REG(AST_REG_MCR18, 0x00000131), + AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x00000001), AST_DRAMSTRUCT_UDELAY(67u), - { 0x0018, 0x00000031 }, - { 0x0014, 0x00000001 }, + AST_DRAMSTRUCT_REG(AST_REG_MCR18, 0x00000031), + AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x00000001), AST_DRAMSTRUCT_UDELAY(67u), - { 0x0028, 0x1e0828f1 }, - { 0x0024, 0x00000003 }, - { 0x002C, 0x1f0f28fb }, - { 0x0030, 0xFFFFFE01 }, + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x1e0828f1), + AST_DRAMSTRUCT_REG(AST_REG_MCR24, 0x00000003), + AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x1f0f28fb), + AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0xfffffe01), AST_DRAMSTRUCT_INVALID, }; static void ast_post_chip_2000(struct ast_device *ast) { u8 j; - u32 temp, i; - const struct ast_dramstruct *dram_reg_info; + u32 i; j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); if ((j & 0x80) == 0) { /* VGA only */ - dram_reg_info = ast2000_dram_table_data; - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - ast_write32(ast, 0x10100, 0xa8); + const struct ast_dramstruct *dram_reg_info = ast2000_dram_table_data; + u32 mcr140; - do { - ; - } while (ast_read32(ast, 0x10100) != 0xa8); + ast_moutdwm_poll(ast, AST_REG_MCR100, 0xa8, 0xa8); while (!AST_DRAMSTRUCT_IS(dram_reg_info, INVALID)) { if (AST_DRAMSTRUCT_IS(dram_reg_info, UDELAY)) { for (i = 0; i < 15; i++) udelay(dram_reg_info->data); } else { - ast_write32(ast, 0x10000 + dram_reg_info->index, - dram_reg_info->data); + ast_moutdwm(ast, dram_reg_info->index, dram_reg_info->data); } dram_reg_info++; } - temp = ast_read32(ast, 0x10140); - ast_write32(ast, 0x10140, temp | 0x40); + mcr140 = ast_mindwm(ast, AST_REG_MCR140); + mcr140 |= 0x00000040; + ast_moutdwm(ast, AST_REG_MCR140, mcr140); } /* wait ready */ diff --git a/drivers/gpu/drm/ast/ast_2100.c b/drivers/gpu/drm/ast/ast_2100.c index 05aeb0624d41..5cf8ad9c3446 100644 --- a/drivers/gpu/drm/ast/ast_2100.c +++ b/drivers/gpu/drm/ast/ast_2100.c @@ -40,21 +40,19 @@ static enum ast_dram_layout ast_2100_get_dram_layout_p2a(struct ast_device *ast) { - u32 mcr_cfg; + u32 mcr04; enum ast_dram_layout dram_layout; - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - mcr_cfg = ast_read32(ast, 0x10004); + mcr04 = ast_mindwm(ast, AST_REG_MCR04); - switch (mcr_cfg & 0x0c) { + switch (mcr04 & GENMASK(3, 2)) { case 0: case 4: default: dram_layout = AST_DRAM_512Mx16; break; case 8: - if (mcr_cfg & 0x40) + if (mcr04 & 0x40) dram_layout = AST_DRAM_1Gx16; else dram_layout = AST_DRAM_512Mx32; @@ -72,108 +70,108 @@ static enum ast_dram_layout ast_2100_get_dram_layout_p2a(struct ast_device *ast) */ static const struct ast_dramstruct ast1100_dram_table_data[] = { - { 0x2000, 0x1688a8a8 }, - { 0x2020, 0x000041f0 }, + AST_DRAMSTRUCT_REG(AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY), + AST_DRAMSTRUCT_REG(AST_REG_SCU020, 0x000041f0), AST_DRAMSTRUCT_UDELAY(67u), - { 0x0000, 0xfc600309 }, - { 0x006C, 0x00909090 }, - { 0x0064, 0x00050000 }, - AST_DRAMSTRUCT_INIT(DRAM_TYPE, 0x00000585), - { 0x0008, 0x0011030f }, - { 0x0010, 0x22201724 }, - { 0x0018, 0x1e29011a }, - { 0x0020, 0x00c82222 }, - { 0x0014, 0x01001523 }, - { 0x001C, 0x1024010d }, - { 0x0024, 0x00cb2522 }, - { 0x0038, 0xffffff82 }, - { 0x003C, 0x00000000 }, - { 0x0040, 0x00000000 }, - { 0x0044, 0x00000000 }, - { 0x0048, 0x00000000 }, - { 0x004C, 0x00000000 }, - { 0x0050, 0x00000000 }, - { 0x0054, 0x00000000 }, - { 0x0058, 0x00000000 }, - { 0x005C, 0x00000000 }, - { 0x0060, 0x032aa02a }, - { 0x0064, 0x002d3000 }, - { 0x0068, 0x00000000 }, - { 0x0070, 0x00000000 }, - { 0x0074, 0x00000000 }, - { 0x0078, 0x00000000 }, - { 0x007C, 0x00000000 }, - { 0x0034, 0x00000001 }, + AST_DRAMSTRUCT_REG(AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY), + AST_DRAMSTRUCT_REG(AST_REG_MCR6C, 0x00909090), + AST_DRAMSTRUCT_REG(AST_REG_MCR64, 0x00050000), + AST_DRAMSTRUCT_REG(AST_REG_MCR04, 0x00000585), // DRAM type + AST_DRAMSTRUCT_REG(AST_REG_MCR08, 0x0011030f), + AST_DRAMSTRUCT_REG(AST_REG_MCR10, 0x22201724), + AST_DRAMSTRUCT_REG(AST_REG_MCR18, 0x1e29011a), + AST_DRAMSTRUCT_REG(AST_REG_MCR20, 0x00c82222), + AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x01001523), + AST_DRAMSTRUCT_REG(AST_REG_MCR1C, 0x1024010d), + AST_DRAMSTRUCT_REG(AST_REG_MCR24, 0x00cb2522), + AST_DRAMSTRUCT_REG(AST_REG_MCR38, 0xffffff82), + AST_DRAMSTRUCT_REG(AST_REG_MCR3C, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR40, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR44, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR48, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR4C, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR50, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR54, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR58, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR5C, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR60, 0x032aa02a), + AST_DRAMSTRUCT_REG(AST_REG_MCR64, 0x002d3000), + AST_DRAMSTRUCT_REG(AST_REG_MCR68, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR70, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR74, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR78, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR7C, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR34, 0x00000001), AST_DRAMSTRUCT_UDELAY(67u), - { 0x002C, 0x00000732 }, - { 0x0030, 0x00000040 }, - { 0x0028, 0x00000005 }, - { 0x0028, 0x00000007 }, - { 0x0028, 0x00000003 }, - { 0x0028, 0x00000001 }, - { 0x000C, 0x00005a08 }, - { 0x002C, 0x00000632 }, - { 0x0028, 0x00000001 }, - { 0x0030, 0x000003c0 }, - { 0x0028, 0x00000003 }, - { 0x0030, 0x00000040 }, - { 0x0028, 0x00000003 }, - { 0x000C, 0x00005a21 }, - { 0x0034, 0x00007c03 }, - { 0x0120, 0x00004c41 }, + AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x00000732), + AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x00000040), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000005), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000007), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000001), + AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x00005a08), + AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x00000632), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000001), + AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x000003c0), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003), + AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x00000040), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003), + AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x00005a21), + AST_DRAMSTRUCT_REG(AST_REG_MCR34, 0x00007c03), + AST_DRAMSTRUCT_REG(AST_REG_MCR120, 0x00004c41), AST_DRAMSTRUCT_INVALID, }; static const struct ast_dramstruct ast2100_dram_table_data[] = { - { 0x2000, 0x1688a8a8 }, - { 0x2020, 0x00004120 }, + AST_DRAMSTRUCT_REG(AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY), + AST_DRAMSTRUCT_REG(AST_REG_SCU020, 0x00004120), AST_DRAMSTRUCT_UDELAY(67u), - { 0x0000, 0xfc600309 }, - { 0x006C, 0x00909090 }, - { 0x0064, 0x00070000 }, - AST_DRAMSTRUCT_INIT(DRAM_TYPE, 0x00000489), - { 0x0008, 0x0011030f }, - { 0x0010, 0x32302926 }, - { 0x0018, 0x274c0122 }, - { 0x0020, 0x00ce2222 }, - { 0x0014, 0x01001523 }, - { 0x001C, 0x1024010d }, - { 0x0024, 0x00cb2522 }, - { 0x0038, 0xffffff82 }, - { 0x003C, 0x00000000 }, - { 0x0040, 0x00000000 }, - { 0x0044, 0x00000000 }, - { 0x0048, 0x00000000 }, - { 0x004C, 0x00000000 }, - { 0x0050, 0x00000000 }, - { 0x0054, 0x00000000 }, - { 0x0058, 0x00000000 }, - { 0x005C, 0x00000000 }, - { 0x0060, 0x0f2aa02a }, - { 0x0064, 0x003f3005 }, - { 0x0068, 0x02020202 }, - { 0x0070, 0x00000000 }, - { 0x0074, 0x00000000 }, - { 0x0078, 0x00000000 }, - { 0x007C, 0x00000000 }, - { 0x0034, 0x00000001 }, + AST_DRAMSTRUCT_REG(AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY), + AST_DRAMSTRUCT_REG(AST_REG_MCR6C, 0x00909090), + AST_DRAMSTRUCT_REG(AST_REG_MCR64, 0x00070000), + AST_DRAMSTRUCT_REG(AST_REG_MCR04, 0x00000489), // DRAM type + AST_DRAMSTRUCT_REG(AST_REG_MCR08, 0x0011030f), + AST_DRAMSTRUCT_REG(AST_REG_MCR10, 0x32302926), + AST_DRAMSTRUCT_REG(AST_REG_MCR18, 0x274c0122), + AST_DRAMSTRUCT_REG(AST_REG_MCR20, 0x00ce2222), + AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x01001523), + AST_DRAMSTRUCT_REG(AST_REG_MCR1C, 0x1024010d), + AST_DRAMSTRUCT_REG(AST_REG_MCR24, 0x00cb2522), + AST_DRAMSTRUCT_REG(AST_REG_MCR38, 0xffffff82), + AST_DRAMSTRUCT_REG(AST_REG_MCR3C, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR40, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR44, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR48, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR4C, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR50, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR54, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR58, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR5C, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR60, 0x0f2aa02a), + AST_DRAMSTRUCT_REG(AST_REG_MCR64, 0x003f3005), + AST_DRAMSTRUCT_REG(AST_REG_MCR68, 0x02020202), + AST_DRAMSTRUCT_REG(AST_REG_MCR70, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR74, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR78, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR7C, 0x00000000), + AST_DRAMSTRUCT_REG(AST_REG_MCR34, 0x00000001), AST_DRAMSTRUCT_UDELAY(67u), - { 0x002C, 0x00000942 }, - { 0x0030, 0x00000040 }, - { 0x0028, 0x00000005 }, - { 0x0028, 0x00000007 }, - { 0x0028, 0x00000003 }, - { 0x0028, 0x00000001 }, - { 0x000C, 0x00005a08 }, - { 0x002C, 0x00000842 }, - { 0x0028, 0x00000001 }, - { 0x0030, 0x000003c0 }, - { 0x0028, 0x00000003 }, - { 0x0030, 0x00000040 }, - { 0x0028, 0x00000003 }, - { 0x000C, 0x00005a21 }, - { 0x0034, 0x00007c03 }, - { 0x0120, 0x00005061 }, + AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x00000942), + AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x00000040), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000005), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000007), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000001), + AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x00005a08), + AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x00000842), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000001), + AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x000003c0), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003), + AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x00000040), + AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003), + AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x00005a21), + AST_DRAMSTRUCT_REG(AST_REG_MCR34, 0x00007c03), + AST_DRAMSTRUCT_REG(AST_REG_MCR120, 0x00005061), AST_DRAMSTRUCT_INVALID, }; @@ -209,28 +207,28 @@ static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen) { u32 data, timeout; - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000001 | (datagen << 3)); timeout = 0; do { - data = ast_mindwm(ast, 0x1e6e0070) & 0x40; + data = ast_mindwm(ast, AST_REG_MCR70) & 0x40; if (++timeout > TIMEOUT_AST2150) { - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); return 0xffffffff; } } while (!data); - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000003 | (datagen << 3)); timeout = 0; do { - data = ast_mindwm(ast, 0x1e6e0070) & 0x40; + data = ast_mindwm(ast, AST_REG_MCR70) & 0x40; if (++timeout > TIMEOUT_AST2150) { - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); return 0xffffffff; } } while (!data); - data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); + data = (ast_mindwm(ast, AST_REG_MCR70) & 0x80) >> 7; + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); return data; } @@ -249,7 +247,7 @@ static int cbrscan_ast2150(struct ast_device *ast, int busw) u32 patcnt, loop; for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) { - ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); + ast_moutdwm(ast, AST_REG_MCR7C, pattern_AST2150[patcnt]); for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) { if (cbrtest_ast2150(ast)) break; @@ -276,7 +274,7 @@ static void cbrdlli_ast2150(struct ast_device *ast, int busw) passcnt = 0; for (dlli = 0; dlli < 100; dlli++) { - ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); + ast_moutdwm(ast, AST_REG_MCR68, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); data = cbrscan_ast2150(ast, busw); if (data != 0) { if (data & 0x1) { @@ -294,78 +292,82 @@ static void cbrdlli_ast2150(struct ast_device *ast, int busw) goto cbr_start; dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4); - ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); + ast_moutdwm(ast, AST_REG_MCR68, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); } static void ast_post_chip_2100(struct ast_device *ast) { u8 j; - u32 data, temp, i; - const struct ast_dramstruct *dram_reg_info; - enum ast_dram_layout dram_layout = ast_2100_get_dram_layout_p2a(ast); + u32 i; + enum ast_dram_layout dram_layout = ast_2100_get_dram_layout_p2a(ast); + u32 mcr120; + u32 scu00c, scu040; j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); if ((j & 0x80) == 0) { /* VGA only */ + const struct ast_dramstruct *dram_reg_info; + if (ast->chip == AST2100 || ast->chip == AST2200) dram_reg_info = ast2100_dram_table_data; else dram_reg_info = ast1100_dram_table_data; - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - ast_write32(ast, 0x12000, 0x1688A8A8); - do { - ; - } while (ast_read32(ast, 0x12000) != 0x01); - - ast_write32(ast, 0x10000, 0xfc600309); - do { - ; - } while (ast_read32(ast, 0x10000) != 0x01); + ast_moutdwm_poll(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY, 0x01); + ast_moutdwm_poll(ast, AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY, 0x01); while (!AST_DRAMSTRUCT_IS(dram_reg_info, INVALID)) { if (AST_DRAMSTRUCT_IS(dram_reg_info, UDELAY)) { for (i = 0; i < 15; i++) udelay(dram_reg_info->data); - } else if (AST_DRAMSTRUCT_IS(dram_reg_info, DRAM_TYPE)) { + } else if (AST_DRAMSTRUCT_IS_REG(dram_reg_info, AST_REG_MCR04)) { + u32 mcr04; + u32 scu070; + switch (dram_layout) { case AST_DRAM_1Gx16: - data = 0x00000d89; + mcr04 = 0x00000d89; break; case AST_DRAM_1Gx32: - data = 0x00000c8d; + mcr04 = 0x00000c8d; break; default: - data = dram_reg_info->data; + mcr04 = dram_reg_info->data; break; } - temp = ast_read32(ast, 0x12070); - temp &= 0xc; - temp <<= 2; - ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp); + /* + * FIXME: There might be bits already in MCR04[5:4]. Should + * we only do this in the default case? + */ + scu070 = ast_mindwm(ast, AST_REG_SCU070); + mcr04 |= (scu070 & GENMASK(3, 2)) << 2; + + ast_moutdwm(ast, dram_reg_info->index, mcr04); } else { - ast_write32(ast, 0x10000 + dram_reg_info->index, - dram_reg_info->data); + ast_moutdwm(ast, dram_reg_info->index, dram_reg_info->data); } dram_reg_info++; } /* AST 2100/2150 DRAM calibration */ - data = ast_read32(ast, 0x10120); - if (data == 0x5061) { /* 266Mhz */ - data = ast_read32(ast, 0x10004); - if (data & 0x40) + mcr120 = ast_mindwm(ast, AST_REG_MCR120); + if (mcr120 == 0x5061) { /* 266Mhz */ + u32 mcr04 = ast_mindwm(ast, AST_REG_MCR04); + + if (mcr04 & 0x40) cbrdlli_ast2150(ast, 16); /* 16 bits */ else cbrdlli_ast2150(ast, 32); /* 32 bits */ } - temp = ast_read32(ast, 0x1200c); - ast_write32(ast, 0x1200c, temp & 0xfffffffd); - temp = ast_read32(ast, 0x12040); - ast_write32(ast, 0x12040, temp | 0x40); + scu00c = ast_mindwm(ast, AST_REG_SCU00C); + scu00c &= 0xfffffffd; + ast_moutdwm(ast, AST_REG_SCU00C, scu00c); + + scu040 = ast_mindwm(ast, AST_REG_SCU040); + scu040 |= 0x00000040; + ast_moutdwm(ast, AST_REG_SCU040, scu040); } /* wait ready */ diff --git a/drivers/gpu/drm/ast/ast_2300.c b/drivers/gpu/drm/ast/ast_2300.c index 5f50d9f91ffd..cbeac6990c27 100644 --- a/drivers/gpu/drm/ast/ast_2300.c +++ b/drivers/gpu/drm/ast/ast_2300.c @@ -129,19 +129,19 @@ static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl) { u32 data, timeout; - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, (datagen << 3) | test_ctl); timeout = 0; do { - data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; + data = ast_mindwm(ast, AST_REG_MCR70) & 0x1000; if (++timeout > TIMEOUT) { - ast_moutdwm(ast, 0x1e6e0070, 0x0); + ast_moutdwm(ast, AST_REG_MCR70, 0x0); return 0xffffffff; } } while (!data); - data = ast_mindwm(ast, 0x1e6e0078); + data = ast_mindwm(ast, AST_REG_MCR78); data = (data | (data >> 16)) & 0xffff; - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); return data; } @@ -186,7 +186,7 @@ static int cbr_scan(struct ast_device *ast) data2 = 3; for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { - ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); + ast_moutdwm(ast, AST_REG_MCR7C, pattern[patcnt]); for (loop = 0; loop < CBR_PASSNUM2; loop++) { data = cbr_test(ast); if (data != 0) { @@ -222,7 +222,7 @@ static u32 cbr_scan2(struct ast_device *ast) data2 = 0xffff; for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { - ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); + ast_moutdwm(ast, AST_REG_MCR7C, pattern[patcnt]); for (loop = 0; loop < CBR_PASSNUM2; loop++) { data = cbr_test2(ast); if (data != 0) { @@ -252,7 +252,7 @@ static bool cbr_scan3(struct ast_device *ast) u32 patcnt, loop; for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { - ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); + ast_moutdwm(ast, AST_REG_MCR7C, pattern[patcnt]); for (loop = 0; loop < 2; loop++) { if (cbr_test3(ast)) break; @@ -274,8 +274,8 @@ static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *par } passcnt = 0; for (dlli = 0; dlli < 76; dlli++) { - ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); - ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1); + ast_moutdwm(ast, AST_REG_MCR68, 0x00001400 | (dlli << 16) | (dlli << 24)); + ast_moutdwm(ast, AST_REG_MCR74, CBR_SIZE1); data = cbr_scan2(ast); if (data != 0) { mask = 0x00010001; @@ -330,7 +330,7 @@ static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *par data |= dlli << 21; } } - ast_moutdwm(ast, 0x1E6E0080, data); + ast_moutdwm(ast, AST_REG_MCR80, data); data = 0; for (cnt = 8; cnt < 16; cnt++) { @@ -354,7 +354,7 @@ static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *par data |= dlli << 21; } } - ast_moutdwm(ast, 0x1E6E0084, data); + ast_moutdwm(ast, AST_REG_MCR84, data); return status; } /* finetuneDQI_L */ @@ -367,10 +367,10 @@ static void finetuneDQSI(struct ast_device *ast) char tag[2][76]; /* Disable DQI CBR */ - reg_mcr0c = ast_mindwm(ast, 0x1E6E000C); - reg_mcr18 = ast_mindwm(ast, 0x1E6E0018); + reg_mcr0c = ast_mindwm(ast, AST_REG_MCR0C); + reg_mcr18 = ast_mindwm(ast, AST_REG_MCR18); reg_mcr18 &= 0x0000ffff; - ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); + ast_moutdwm(ast, AST_REG_MCR18, reg_mcr18); for (dlli = 0; dlli < 76; dlli++) { tag[0][dlli] = 0x0; @@ -386,14 +386,14 @@ static void finetuneDQSI(struct ast_device *ast) passcnt[0] = 0; passcnt[1] = 0; for (dqsip = 0; dqsip < 2; dqsip++) { - ast_moutdwm(ast, 0x1E6E000C, 0); - ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); - ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c); + ast_moutdwm(ast, AST_REG_MCR0C, 0); + ast_moutdwm(ast, AST_REG_MCR18, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); + ast_moutdwm(ast, AST_REG_MCR0C, reg_mcr0c); for (dlli = 0; dlli < 76; dlli++) { - ast_moutdwm(ast, 0x1E6E0068, + ast_moutdwm(ast, AST_REG_MCR68, 0x00001300 | (dlli << 16) | (dlli << 24)); - ast_moutdwm(ast, 0x1E6E0070, 0); - ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0); + ast_moutdwm(ast, AST_REG_MCR70, 0); + ast_moutdwm(ast, AST_REG_MCR74, CBR_SIZE0); if (cbr_scan3(ast)) { if (dlli == 0) break; @@ -457,7 +457,7 @@ static void finetuneDQSI(struct ast_device *ast) } } reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23); - ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); + ast_moutdwm(ast, AST_REG_MCR18, reg_mcr18); } static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param) @@ -476,8 +476,8 @@ static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param) dllmax[1] = 0x0; passcnt = 0; for (dlli = 0; dlli < 76; dlli++) { - ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); - ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2); + ast_moutdwm(ast, AST_REG_MCR68, 0x00001300 | (dlli << 16) | (dlli << 24)); + ast_moutdwm(ast, AST_REG_MCR74, CBR_SIZE2); data = cbr_scan(ast); if (data != 0) { if (data & 0x1) { @@ -508,7 +508,7 @@ static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param) dlli = (dllmin[1] + dllmax[1]) >> 1; dlli <<= 8; dlli += (dllmin[0] + dllmax[0]) >> 1; - ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16)); + ast_moutdwm(ast, AST_REG_MCR68, ast_mindwm(ast, AST_REG_A2P58) | (dlli << 16)); return status; } /* CBRDLL2 */ @@ -516,10 +516,10 @@ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *par { u32 trap, trap_AC2, trap_MRS; - ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); + ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); /* Ger trap info */ - trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; + trap = (ast_mindwm(ast, AST_REG_SCU070) >> 25) & 0x3; trap_AC2 = 0x00020000 + (trap << 16); trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19); trap_MRS = 0x00000010 + (trap << 4); @@ -533,7 +533,7 @@ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *par switch (param->dram_freq) { case 336: - ast_moutdwm(ast, 0x1E6E2020, 0x0190); + ast_moutdwm(ast, AST_REG_SCU020, 0x0190); param->wodt = 0; param->reg_AC1 = 0x22202725; param->reg_AC2 = 0xAA007613 | trap_AC2; @@ -561,7 +561,7 @@ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *par break; default: case 396: - ast_moutdwm(ast, 0x1E6E2020, 0x03F1); + ast_moutdwm(ast, AST_REG_SCU020, 0x03F1); param->wodt = 1; param->reg_AC1 = 0x33302825; param->reg_AC2 = 0xCC009617 | trap_AC2; @@ -591,7 +591,7 @@ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *par break; case 408: - ast_moutdwm(ast, 0x1E6E2020, 0x01F0); + ast_moutdwm(ast, AST_REG_SCU020, 0x01F0); param->wodt = 1; param->reg_AC1 = 0x33302825; param->reg_AC2 = 0xCC009617 | trap_AC2; @@ -621,7 +621,7 @@ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *par break; case 456: - ast_moutdwm(ast, 0x1E6E2020, 0x0230); + ast_moutdwm(ast, AST_REG_SCU020, 0x0230); param->wodt = 0; param->reg_AC1 = 0x33302926; param->reg_AC2 = 0xCD44961A; @@ -635,7 +635,7 @@ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *par param->dll2_finetune_step = 4; break; case 504: - ast_moutdwm(ast, 0x1E6E2020, 0x0270); + ast_moutdwm(ast, AST_REG_SCU020, 0x0270); param->wodt = 1; param->reg_AC1 = 0x33302926; param->reg_AC2 = 0xDE44A61D; @@ -649,7 +649,7 @@ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *par param->dll2_finetune_step = 4; break; case 528: - ast_moutdwm(ast, 0x1E6E2020, 0x0290); + ast_moutdwm(ast, AST_REG_SCU020, 0x0290); param->wodt = 1; param->rodt = 1; param->reg_AC1 = 0x33302926; @@ -665,7 +665,7 @@ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *par param->dll2_finetune_step = 3; break; case 576: - ast_moutdwm(ast, 0x1E6E2020, 0x0140); + ast_moutdwm(ast, AST_REG_SCU020, 0x0140); param->reg_MADJ = 0x00136868; param->reg_SADJ = 0x00004534; param->wodt = 1; @@ -683,7 +683,7 @@ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *par param->dll2_finetune_step = 3; break; case 600: - ast_moutdwm(ast, 0x1E6E2020, 0x02E1); + ast_moutdwm(ast, AST_REG_SCU020, 0x02E1); param->reg_MADJ = 0x00136868; param->reg_SADJ = 0x00004534; param->wodt = 1; @@ -701,7 +701,7 @@ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *par param->dll2_finetune_step = 3; break; case 624: - ast_moutdwm(ast, 0x1E6E2020, 0x0160); + ast_moutdwm(ast, AST_REG_SCU020, 0x0160); param->reg_MADJ = 0x00136868; param->reg_SADJ = 0x00004534; param->wodt = 1; @@ -758,115 +758,115 @@ static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param) u32 data, data2, retry = 0; ddr3_init_start: - ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); - ast_moutdwm(ast, 0x1E6E0018, 0x00000100); - ast_moutdwm(ast, 0x1E6E0024, 0x00000000); - ast_moutdwm(ast, 0x1E6E0034, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY); + ast_moutdwm(ast, AST_REG_MCR18, 0x00000100); + ast_moutdwm(ast, AST_REG_MCR24, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR34, 0x00000000); udelay(10); - ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); - ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); + ast_moutdwm(ast, AST_REG_MCR64, param->reg_MADJ); + ast_moutdwm(ast, AST_REG_MCR68, param->reg_SADJ); udelay(10); - ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); + ast_moutdwm(ast, AST_REG_MCR64, param->reg_MADJ | 0xC0000); udelay(10); - ast_moutdwm(ast, 0x1E6E0004, param->dram_config); - ast_moutdwm(ast, 0x1E6E0008, 0x90040f); - ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); - ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); - ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); - ast_moutdwm(ast, 0x1E6E0080, 0x00000000); - ast_moutdwm(ast, 0x1E6E0084, 0x00000000); - ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); - ast_moutdwm(ast, 0x1E6E0018, 0x4000A170); - ast_moutdwm(ast, 0x1E6E0018, 0x00002370); - ast_moutdwm(ast, 0x1E6E0038, 0x00000000); - ast_moutdwm(ast, 0x1E6E0040, 0xFF444444); - ast_moutdwm(ast, 0x1E6E0044, 0x22222222); - ast_moutdwm(ast, 0x1E6E0048, 0x22222222); - ast_moutdwm(ast, 0x1E6E004C, 0x00000002); - ast_moutdwm(ast, 0x1E6E0050, 0x80000000); - ast_moutdwm(ast, 0x1E6E0050, 0x00000000); - ast_moutdwm(ast, 0x1E6E0054, 0); - ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); - ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); - ast_moutdwm(ast, 0x1E6E0070, 0x00000000); - ast_moutdwm(ast, 0x1E6E0074, 0x00000000); - ast_moutdwm(ast, 0x1E6E0078, 0x00000000); - ast_moutdwm(ast, 0x1E6E007C, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR04, param->dram_config); + ast_moutdwm(ast, AST_REG_MCR08, 0x90040f); + ast_moutdwm(ast, AST_REG_MCR10, param->reg_AC1); + ast_moutdwm(ast, AST_REG_MCR14, param->reg_AC2); + ast_moutdwm(ast, AST_REG_MCR20, param->reg_DQSIC); + ast_moutdwm(ast, AST_REG_MCR80, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR84, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR88, param->reg_DQIDLY); + ast_moutdwm(ast, AST_REG_MCR18, 0x4000A170); + ast_moutdwm(ast, AST_REG_MCR18, 0x00002370); + ast_moutdwm(ast, AST_REG_MCR38, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR40, 0xFF444444); + ast_moutdwm(ast, AST_REG_MCR44, 0x22222222); + ast_moutdwm(ast, AST_REG_MCR48, 0x22222222); + ast_moutdwm(ast, AST_REG_MCR4C, 0x00000002); + ast_moutdwm(ast, AST_REG_MCR50, 0x80000000); + ast_moutdwm(ast, AST_REG_MCR50, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR54, 0); + ast_moutdwm(ast, AST_REG_MCR60, param->reg_DRV); + ast_moutdwm(ast, AST_REG_MCR6C, param->reg_IOZ); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR74, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR78, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR7C, 0x00000000); /* Wait MCLK2X lock to MCLK */ do { - data = ast_mindwm(ast, 0x1E6E001C); + data = ast_mindwm(ast, AST_REG_MCR1C); } while (!(data & 0x08000000)); - data = ast_mindwm(ast, 0x1E6E001C); + data = ast_mindwm(ast, AST_REG_MCR1C); data = (data >> 8) & 0xff; while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { - data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; + data2 = (ast_mindwm(ast, AST_REG_MCR64) & 0xfff3ffff) + 4; if ((data2 & 0xff) > param->madj_max) break; - ast_moutdwm(ast, 0x1E6E0064, data2); + ast_moutdwm(ast, AST_REG_MCR64, data2); if (data2 & 0x00100000) data2 = ((data2 & 0xff) >> 3) + 3; else data2 = ((data2 & 0xff) >> 2) + 5; - data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; + data = ast_mindwm(ast, AST_REG_MCR68) & 0xffff00ff; data2 += data & 0xff; data = data | (data2 << 8); - ast_moutdwm(ast, 0x1E6E0068, data); + ast_moutdwm(ast, AST_REG_MCR68, data); udelay(10); - ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); + ast_moutdwm(ast, AST_REG_MCR64, ast_mindwm(ast, AST_REG_MCR64) | 0xC0000); udelay(10); - data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; - ast_moutdwm(ast, 0x1E6E0018, data); + data = ast_mindwm(ast, AST_REG_MCR18) & 0xfffff1ff; + ast_moutdwm(ast, AST_REG_MCR18, data); data = data | 0x200; - ast_moutdwm(ast, 0x1E6E0018, data); + ast_moutdwm(ast, AST_REG_MCR18, data); do { - data = ast_mindwm(ast, 0x1E6E001C); + data = ast_mindwm(ast, AST_REG_MCR1C); } while (!(data & 0x08000000)); - data = ast_mindwm(ast, 0x1E6E001C); + data = ast_mindwm(ast, AST_REG_MCR1C); data = (data >> 8) & 0xff; } - ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff); - data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; - ast_moutdwm(ast, 0x1E6E0018, data); + ast_moutdwm(ast, AST_REG_A2P58, ast_mindwm(ast, AST_REG_MCR68) & 0xffff); + data = ast_mindwm(ast, AST_REG_MCR18) | 0xC00; + ast_moutdwm(ast, AST_REG_MCR18, data); - ast_moutdwm(ast, 0x1E6E0034, 0x00000001); - ast_moutdwm(ast, 0x1E6E000C, 0x00000040); + ast_moutdwm(ast, AST_REG_MCR34, 0x00000001); + ast_moutdwm(ast, AST_REG_MCR0C, 0x00000040); udelay(50); /* Mode Register Setting */ - ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); - ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); - ast_moutdwm(ast, 0x1E6E0028, 0x00000005); - ast_moutdwm(ast, 0x1E6E0028, 0x00000007); - ast_moutdwm(ast, 0x1E6E0028, 0x00000003); - ast_moutdwm(ast, 0x1E6E0028, 0x00000001); - ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); - ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); - ast_moutdwm(ast, 0x1E6E0028, 0x00000001); + ast_moutdwm(ast, AST_REG_MCR2C, param->reg_MRS | 0x100); + ast_moutdwm(ast, AST_REG_MCR30, param->reg_EMRS); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000005); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000007); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000003); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000001); + ast_moutdwm(ast, AST_REG_MCR2C, param->reg_MRS); + ast_moutdwm(ast, AST_REG_MCR0C, 0x00005C08); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000001); - ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); + ast_moutdwm(ast, AST_REG_MCR0C, 0x00005C01); data = 0; if (param->wodt) data = 0x300; if (param->rodt) data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); - ast_moutdwm(ast, 0x1E6E0034, data | 0x3); + ast_moutdwm(ast, AST_REG_MCR34, data | 0x3); /* Calibrate the DQSI delay */ if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) goto ddr3_init_start; - ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); + ast_moutdwm(ast, AST_REG_MCR120, param->reg_FREQ); /* ECC Memory Initialization */ #ifdef ECC - ast_moutdwm(ast, 0x1E6E007C, 0x00000000); - ast_moutdwm(ast, 0x1E6E0070, 0x221); + ast_moutdwm(ast, AST_REG_MCR7C, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, 0x221); do { - data = ast_mindwm(ast, 0x1E6E0070); + data = ast_mindwm(ast, AST_REG_MCR70); } while (!(data & 0x00001000)); - ast_moutdwm(ast, 0x1E6E0070, 0x00000000); - ast_moutdwm(ast, 0x1E6E0050, 0x80000000); - ast_moutdwm(ast, 0x1E6E0050, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR50, 0x80000000); + ast_moutdwm(ast, AST_REG_MCR50, 0x00000000); #endif } @@ -874,10 +874,10 @@ static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *par { u32 trap, trap_AC2, trap_MRS; - ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); + ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); /* Ger trap info */ - trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; + trap = (ast_mindwm(ast, AST_REG_SCU070) >> 25) & 0x3; trap_AC2 = (trap << 20) | (trap << 16); trap_AC2 += 0x00110000; trap_MRS = 0x00000040 | (trap << 4); @@ -890,7 +890,7 @@ static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *par switch (param->dram_freq) { case 264: - ast_moutdwm(ast, 0x1E6E2020, 0x0130); + ast_moutdwm(ast, AST_REG_SCU020, 0x0130); param->wodt = 0; param->reg_AC1 = 0x11101513; param->reg_AC2 = 0x78117011; @@ -905,7 +905,7 @@ static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *par param->dll2_finetune_step = 3; break; case 336: - ast_moutdwm(ast, 0x1E6E2020, 0x0190); + ast_moutdwm(ast, AST_REG_SCU020, 0x0190); param->wodt = 1; param->reg_AC1 = 0x22202613; param->reg_AC2 = 0xAA009016 | trap_AC2; @@ -936,7 +936,7 @@ static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *par break; default: case 396: - ast_moutdwm(ast, 0x1E6E2020, 0x03F1); + ast_moutdwm(ast, AST_REG_SCU020, 0x03F1); param->wodt = 1; param->rodt = 0; param->reg_AC1 = 0x33302714; @@ -970,7 +970,7 @@ static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *par break; case 408: - ast_moutdwm(ast, 0x1E6E2020, 0x01F0); + ast_moutdwm(ast, AST_REG_SCU020, 0x01F0); param->wodt = 1; param->rodt = 0; param->reg_AC1 = 0x33302714; @@ -1003,7 +1003,7 @@ static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *par break; case 456: - ast_moutdwm(ast, 0x1E6E2020, 0x0230); + ast_moutdwm(ast, AST_REG_SCU020, 0x0230); param->wodt = 0; param->reg_AC1 = 0x33302815; param->reg_AC2 = 0xCD44B01E; @@ -1018,7 +1018,7 @@ static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *par param->dll2_finetune_step = 3; break; case 504: - ast_moutdwm(ast, 0x1E6E2020, 0x0261); + ast_moutdwm(ast, AST_REG_SCU020, 0x0261); param->wodt = 1; param->rodt = 1; param->reg_AC1 = 0x33302815; @@ -1034,7 +1034,7 @@ static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *par param->dll2_finetune_step = 3; break; case 528: - ast_moutdwm(ast, 0x1E6E2020, 0x0120); + ast_moutdwm(ast, AST_REG_SCU020, 0x0120); param->wodt = 1; param->rodt = 1; param->reg_AC1 = 0x33302815; @@ -1050,7 +1050,7 @@ static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *par param->dll2_finetune_step = 3; break; case 552: - ast_moutdwm(ast, 0x1E6E2020, 0x02A1); + ast_moutdwm(ast, AST_REG_SCU020, 0x02A1); param->wodt = 1; param->rodt = 1; param->reg_AC1 = 0x43402915; @@ -1066,7 +1066,7 @@ static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *par param->dll2_finetune_step = 3; break; case 576: - ast_moutdwm(ast, 0x1E6E2020, 0x0140); + ast_moutdwm(ast, AST_REG_SCU020, 0x0140); param->wodt = 1; param->rodt = 1; param->reg_AC1 = 0x43402915; @@ -1121,104 +1121,104 @@ static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param) u32 data, data2, retry = 0; ddr2_init_start: - ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); - ast_moutdwm(ast, 0x1E6E0018, 0x00000100); - ast_moutdwm(ast, 0x1E6E0024, 0x00000000); - ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); - ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); + ast_moutdwm(ast, AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY); + ast_moutdwm(ast, AST_REG_MCR18, 0x00000100); + ast_moutdwm(ast, AST_REG_MCR24, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR64, param->reg_MADJ); + ast_moutdwm(ast, AST_REG_MCR68, param->reg_SADJ); udelay(10); - ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); + ast_moutdwm(ast, AST_REG_MCR64, param->reg_MADJ | 0xC0000); udelay(10); - ast_moutdwm(ast, 0x1E6E0004, param->dram_config); - ast_moutdwm(ast, 0x1E6E0008, 0x90040f); - ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); - ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); - ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); - ast_moutdwm(ast, 0x1E6E0080, 0x00000000); - ast_moutdwm(ast, 0x1E6E0084, 0x00000000); - ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); - ast_moutdwm(ast, 0x1E6E0018, 0x4000A130); - ast_moutdwm(ast, 0x1E6E0018, 0x00002330); - ast_moutdwm(ast, 0x1E6E0038, 0x00000000); - ast_moutdwm(ast, 0x1E6E0040, 0xFF808000); - ast_moutdwm(ast, 0x1E6E0044, 0x88848466); - ast_moutdwm(ast, 0x1E6E0048, 0x44440008); - ast_moutdwm(ast, 0x1E6E004C, 0x00000000); - ast_moutdwm(ast, 0x1E6E0050, 0x80000000); - ast_moutdwm(ast, 0x1E6E0050, 0x00000000); - ast_moutdwm(ast, 0x1E6E0054, 0); - ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); - ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); - ast_moutdwm(ast, 0x1E6E0070, 0x00000000); - ast_moutdwm(ast, 0x1E6E0074, 0x00000000); - ast_moutdwm(ast, 0x1E6E0078, 0x00000000); - ast_moutdwm(ast, 0x1E6E007C, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR04, param->dram_config); + ast_moutdwm(ast, AST_REG_MCR08, 0x90040f); + ast_moutdwm(ast, AST_REG_MCR10, param->reg_AC1); + ast_moutdwm(ast, AST_REG_MCR14, param->reg_AC2); + ast_moutdwm(ast, AST_REG_MCR20, param->reg_DQSIC); + ast_moutdwm(ast, AST_REG_MCR80, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR84, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR88, param->reg_DQIDLY); + ast_moutdwm(ast, AST_REG_MCR18, 0x4000A130); + ast_moutdwm(ast, AST_REG_MCR18, 0x00002330); + ast_moutdwm(ast, AST_REG_MCR38, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR40, 0xFF808000); + ast_moutdwm(ast, AST_REG_MCR44, 0x88848466); + ast_moutdwm(ast, AST_REG_MCR48, 0x44440008); + ast_moutdwm(ast, AST_REG_MCR4C, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR50, 0x80000000); + ast_moutdwm(ast, AST_REG_MCR50, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR54, 0); + ast_moutdwm(ast, AST_REG_MCR60, param->reg_DRV); + ast_moutdwm(ast, AST_REG_MCR6C, param->reg_IOZ); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR74, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR78, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR7C, 0x00000000); /* Wait MCLK2X lock to MCLK */ do { - data = ast_mindwm(ast, 0x1E6E001C); + data = ast_mindwm(ast, AST_REG_MCR1C); } while (!(data & 0x08000000)); - data = ast_mindwm(ast, 0x1E6E001C); + data = ast_mindwm(ast, AST_REG_MCR1C); data = (data >> 8) & 0xff; while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { - data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; + data2 = (ast_mindwm(ast, AST_REG_MCR64) & 0xfff3ffff) + 4; if ((data2 & 0xff) > param->madj_max) break; - ast_moutdwm(ast, 0x1E6E0064, data2); + ast_moutdwm(ast, AST_REG_MCR64, data2); if (data2 & 0x00100000) data2 = ((data2 & 0xff) >> 3) + 3; else data2 = ((data2 & 0xff) >> 2) + 5; - data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; + data = ast_mindwm(ast, AST_REG_MCR68) & 0xffff00ff; data2 += data & 0xff; data = data | (data2 << 8); - ast_moutdwm(ast, 0x1E6E0068, data); + ast_moutdwm(ast, AST_REG_MCR68, data); udelay(10); - ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); + ast_moutdwm(ast, AST_REG_MCR64, ast_mindwm(ast, AST_REG_MCR64) | 0xC0000); udelay(10); - data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; - ast_moutdwm(ast, 0x1E6E0018, data); + data = ast_mindwm(ast, AST_REG_MCR18) & 0xfffff1ff; + ast_moutdwm(ast, AST_REG_MCR18, data); data = data | 0x200; - ast_moutdwm(ast, 0x1E6E0018, data); + ast_moutdwm(ast, AST_REG_MCR18, data); do { - data = ast_mindwm(ast, 0x1E6E001C); + data = ast_mindwm(ast, AST_REG_MCR1C); } while (!(data & 0x08000000)); - data = ast_mindwm(ast, 0x1E6E001C); + data = ast_mindwm(ast, AST_REG_MCR1C); data = (data >> 8) & 0xff; } - ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff); - data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; - ast_moutdwm(ast, 0x1E6E0018, data); + ast_moutdwm(ast, AST_REG_A2P58, ast_mindwm(ast, AST_REG_MCR08) & 0xffff); + data = ast_mindwm(ast, AST_REG_MCR18) | 0xC00; + ast_moutdwm(ast, AST_REG_MCR18, data); - ast_moutdwm(ast, 0x1E6E0034, 0x00000001); - ast_moutdwm(ast, 0x1E6E000C, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR34, 0x00000001); + ast_moutdwm(ast, AST_REG_MCR0C, 0x00000000); udelay(50); /* Mode Register Setting */ - ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); - ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); - ast_moutdwm(ast, 0x1E6E0028, 0x00000005); - ast_moutdwm(ast, 0x1E6E0028, 0x00000007); - ast_moutdwm(ast, 0x1E6E0028, 0x00000003); - ast_moutdwm(ast, 0x1E6E0028, 0x00000001); + ast_moutdwm(ast, AST_REG_MCR2C, param->reg_MRS | 0x100); + ast_moutdwm(ast, AST_REG_MCR30, param->reg_EMRS); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000005); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000007); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000003); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000001); - ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); - ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); - ast_moutdwm(ast, 0x1E6E0028, 0x00000001); - ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); - ast_moutdwm(ast, 0x1E6E0028, 0x00000003); - ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); - ast_moutdwm(ast, 0x1E6E0028, 0x00000003); + ast_moutdwm(ast, AST_REG_MCR0C, 0x00005C08); + ast_moutdwm(ast, AST_REG_MCR2C, param->reg_MRS); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000001); + ast_moutdwm(ast, AST_REG_MCR30, param->reg_EMRS | 0x380); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000003); + ast_moutdwm(ast, AST_REG_MCR30, param->reg_EMRS); + ast_moutdwm(ast, AST_REG_MCR28, 0x00000003); - ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); + ast_moutdwm(ast, AST_REG_MCR0C, 0x7FFF5C01); data = 0; if (param->wodt) data = 0x500; if (param->rodt) data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); - ast_moutdwm(ast, 0x1E6E0034, data | 0x3); - ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); + ast_moutdwm(ast, AST_REG_MCR34, data | 0x3); + ast_moutdwm(ast, AST_REG_MCR120, param->reg_FREQ); /* Calibrate the DQSI delay */ if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) @@ -1226,14 +1226,14 @@ static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param) /* ECC Memory Initialization */ #ifdef ECC - ast_moutdwm(ast, 0x1E6E007C, 0x00000000); - ast_moutdwm(ast, 0x1E6E0070, 0x221); + ast_moutdwm(ast, AST_REG_MCR7C, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, 0x221); do { - data = ast_mindwm(ast, 0x1E6E0070); + data = ast_mindwm(ast, AST_REG_MCR70); } while (!(data & 0x00001000)); - ast_moutdwm(ast, 0x1E6E0070, 0x00000000); - ast_moutdwm(ast, 0x1E6E0050, 0x80000000); - ast_moutdwm(ast, 0x1E6E0050, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR50, 0x80000000); + ast_moutdwm(ast, AST_REG_MCR50, 0x00000000); #endif } @@ -1245,26 +1245,19 @@ static void ast_post_chip_2300(struct ast_device *ast) reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); if ((reg & 0x80) == 0) {/* vga only */ - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - ast_write32(ast, 0x12000, 0x1688a8a8); - do { - ; - } while (ast_read32(ast, 0x12000) != 0x1); + u32 scu008, scu040; - ast_write32(ast, 0x10000, 0xfc600309); - do { - ; - } while (ast_read32(ast, 0x10000) != 0x1); + ast_moutdwm_poll(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY, 0x01); + ast_moutdwm_poll(ast, AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY, 0x01); /* Slow down CPU/AHB CLK in VGA only mode */ - temp = ast_read32(ast, 0x12008); - temp |= 0x73; - ast_write32(ast, 0x12008, temp); + scu008 = ast_mindwm(ast, AST_REG_SCU008); + scu008 |= 0x00000073; + ast_moutdwm(ast, AST_REG_SCU008, scu008); param.dram_freq = 396; param.dram_type = AST_DDR3; - temp = ast_mindwm(ast, 0x1e6e2070); + temp = ast_mindwm(ast, AST_REG_SCU070); if (temp & 0x01000000) param.dram_type = AST_DDR2; switch (temp & 0x18000000) { @@ -1306,8 +1299,9 @@ static void ast_post_chip_2300(struct ast_device *ast) ddr2_init(ast, ¶m); } - temp = ast_mindwm(ast, 0x1e6e2040); - ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); + scu040 = ast_mindwm(ast, AST_REG_SCU040); + scu040 |= 0x00000040; + ast_moutdwm(ast, AST_REG_SCU040, scu040); } /* wait ready */ diff --git a/drivers/gpu/drm/ast/ast_2500.c b/drivers/gpu/drm/ast/ast_2500.c index 2a52af0ded56..03a67ec9684b 100644 --- a/drivers/gpu/drm/ast/ast_2500.c +++ b/drivers/gpu/drm/ast/ast_2500.c @@ -109,12 +109,12 @@ void ast_2500_patch_ahb(void __iomem *regs) u32 data; /* Clear bus lock condition */ - __ast_moutdwm(regs, 0x1e600000, 0xAEED1A03); - __ast_moutdwm(regs, 0x1e600084, 0x00010000); - __ast_moutdwm(regs, 0x1e600088, 0x00000000); - __ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8); + __ast_moutdwm(regs, AST_REG_AHBC00, AST_REG_AHBC00_PROTECT_KEY); + __ast_moutdwm(regs, AST_REG_AHBC84, 0x00010000); + __ast_moutdwm(regs, AST_REG_AHBC88, 0x00000000); + __ast_moutdwm(regs, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); - data = __ast_mindwm(regs, 0x1e6e2070); + data = __ast_mindwm(regs, AST_REG_SCU070); if (data & 0x08000000) { /* check fast reset */ /* * If "Fast restet" is enabled for ARM-ICE debugger, @@ -127,18 +127,18 @@ void ast_2500_patch_ahb(void __iomem *regs) * [1]:= 1:WDT will be cleeared and disabled after timeout occurs * [0]:= 1:WDT enable */ - __ast_moutdwm(regs, 0x1E785004, 0x00000010); - __ast_moutdwm(regs, 0x1E785008, 0x00004755); - __ast_moutdwm(regs, 0x1E78500c, 0x00000033); + __ast_moutdwm(regs, AST_REG_WDT04(0), 0x00000010); + __ast_moutdwm(regs, AST_REG_WDT08(0), 0x00004755); + __ast_moutdwm(regs, AST_REG_WDT0C(0), 0x00000033); udelay(1000); } do { - __ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8); - data = __ast_mindwm(regs, 0x1e6e2000); + __ast_moutdwm(regs, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); + data = __ast_mindwm(regs, AST_REG_SCU000); } while (data != 1); - __ast_moutdwm(regs, 0x1e6e207c, 0x08000000); /* clear fast reset */ + __ast_moutdwm(regs, AST_REG_SCU07C, 0x08000000); /* clear fast reset */ } static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen) @@ -148,8 +148,8 @@ static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen) static bool cbr_test_2500(struct ast_device *ast) { - ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); - ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); + ast_moutdwm(ast, AST_REG_MCR74, 0x0000FFFF); + ast_moutdwm(ast, AST_REG_MCR7C, 0xFF00FF00); if (!mmc_test_burst(ast, 0)) return false; if (!mmc_test_single_2500(ast, 0)) @@ -159,8 +159,8 @@ static bool cbr_test_2500(struct ast_device *ast) static bool ddr_test_2500(struct ast_device *ast) { - ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); - ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); + ast_moutdwm(ast, AST_REG_MCR74, 0x0000FFFF); + ast_moutdwm(ast, AST_REG_MCR7C, 0xFF00FF00); if (!mmc_test_burst(ast, 0)) return false; if (!mmc_test_burst(ast, 1)) @@ -176,25 +176,25 @@ static bool ddr_test_2500(struct ast_device *ast) static void ddr_init_common_2500(struct ast_device *ast) { - ast_moutdwm(ast, 0x1E6E0034, 0x00020080); - ast_moutdwm(ast, 0x1E6E0008, 0x2003000F); - ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF); - ast_moutdwm(ast, 0x1E6E0040, 0x88448844); - ast_moutdwm(ast, 0x1E6E0044, 0x24422288); - ast_moutdwm(ast, 0x1E6E0048, 0x22222222); - ast_moutdwm(ast, 0x1E6E004C, 0x22222222); - ast_moutdwm(ast, 0x1E6E0050, 0x80000000); - ast_moutdwm(ast, 0x1E6E0208, 0x00000000); - ast_moutdwm(ast, 0x1E6E0218, 0x00000000); - ast_moutdwm(ast, 0x1E6E0220, 0x00000000); - ast_moutdwm(ast, 0x1E6E0228, 0x00000000); - ast_moutdwm(ast, 0x1E6E0230, 0x00000000); - ast_moutdwm(ast, 0x1E6E02A8, 0x00000000); - ast_moutdwm(ast, 0x1E6E02B0, 0x00000000); - ast_moutdwm(ast, 0x1E6E0240, 0x86000000); - ast_moutdwm(ast, 0x1E6E0244, 0x00008600); - ast_moutdwm(ast, 0x1E6E0248, 0x80000000); - ast_moutdwm(ast, 0x1E6E024C, 0x80808080); + ast_moutdwm(ast, AST_REG_MCR34, 0x00020080); + ast_moutdwm(ast, AST_REG_MCR08, 0x2003000F); + ast_moutdwm(ast, AST_REG_MCR38, 0x00000FFF); + ast_moutdwm(ast, AST_REG_MCR40, 0x88448844); + ast_moutdwm(ast, AST_REG_MCR44, 0x24422288); + ast_moutdwm(ast, AST_REG_MCR48, 0x22222222); + ast_moutdwm(ast, AST_REG_MCR4C, 0x22222222); + ast_moutdwm(ast, AST_REG_MCR50, 0x80000000); + ast_moutdwm(ast, AST_REG_MCR208, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR218, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR220, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR228, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR230, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR2A8, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR2B0, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR240, 0x86000000); + ast_moutdwm(ast, AST_REG_MCR244, 0x00008600); + ast_moutdwm(ast, AST_REG_MCR248, 0x80000000); + ast_moutdwm(ast, AST_REG_MCR24C, 0x80808080); } static void ddr_phy_init_2500(struct ast_device *ast) @@ -202,29 +202,32 @@ static void ddr_phy_init_2500(struct ast_device *ast) u32 data, pass, timecnt; pass = 0; - ast_moutdwm(ast, 0x1E6E0060, 0x00000005); + ast_moutdwm(ast, AST_REG_MCR60, 0x00000005); while (!pass) { for (timecnt = 0; timecnt < TIMEOUT; timecnt++) { - data = ast_mindwm(ast, 0x1E6E0060) & 0x1; + data = ast_mindwm(ast, AST_REG_MCR60) & 0x1; if (!data) break; } if (timecnt != TIMEOUT) { - data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000; + data = ast_mindwm(ast, AST_REG_MCR300) & 0x000A0000; if (!data) pass = 1; } if (!pass) { - ast_moutdwm(ast, 0x1E6E0060, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR60, 0x00000000); udelay(10); /* delay 10 us */ - ast_moutdwm(ast, 0x1E6E0060, 0x00000005); + ast_moutdwm(ast, AST_REG_MCR60, 0x00000005); } } - ast_moutdwm(ast, 0x1E6E0060, 0x00000006); + ast_moutdwm(ast, AST_REG_MCR60, 0x00000006); } /* + * TODO: Review and fix the comments. The function below only detects + * up to 1 GiB of SDRAM. + * * Check DRAM Size * 1Gb : 0x80000000 ~ 0x87FFFFFF * 2Gb : 0x80000000 ~ 0x8FFFFFFF @@ -235,125 +238,123 @@ static void check_dram_size_2500(struct ast_device *ast, u32 tRFC) { u32 reg_04, reg_14; - reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc; - reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00; + reg_04 = ast_mindwm(ast, AST_REG_MCR04) & 0xfffffffc; + reg_14 = ast_mindwm(ast, AST_REG_MCR14) & 0xffffff00; - ast_moutdwm(ast, 0xA0100000, 0x41424344); - ast_moutdwm(ast, 0x90100000, 0x35363738); - ast_moutdwm(ast, 0x88100000, 0x292A2B2C); - ast_moutdwm(ast, 0x80100000, 0x1D1E1F10); + ast_moutdwm(ast, AST_SDRAM(0x20100000), 0x41424344); + ast_moutdwm(ast, AST_SDRAM(0x10100000), 0x35363738); + ast_moutdwm(ast, AST_SDRAM(0x08100000), 0x292A2B2C); + ast_moutdwm(ast, AST_SDRAM(0x00100000), 0x1D1E1F10); /* Check 8Gbit */ - if (ast_mindwm(ast, 0xA0100000) == 0x41424344) { + if (ast_mindwm(ast, AST_SDRAM(0x20100000)) == 0x41424344) { reg_04 |= 0x03; reg_14 |= (tRFC >> 24) & 0xFF; /* Check 4Gbit */ - } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) { + } else if (ast_mindwm(ast, AST_SDRAM(0x10100000)) == 0x35363738) { reg_04 |= 0x02; reg_14 |= (tRFC >> 16) & 0xFF; /* Check 2Gbit */ - } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) { + } else if (ast_mindwm(ast, AST_SDRAM(0x08100000)) == 0x292A2B2C) { reg_04 |= 0x01; reg_14 |= (tRFC >> 8) & 0xFF; } else { reg_14 |= tRFC & 0xFF; } - ast_moutdwm(ast, 0x1E6E0004, reg_04); - ast_moutdwm(ast, 0x1E6E0014, reg_14); + ast_moutdwm(ast, AST_REG_MCR04, reg_04); + ast_moutdwm(ast, AST_REG_MCR14, reg_14); } static void enable_cache_2500(struct ast_device *ast) { u32 reg_04, data; - reg_04 = ast_mindwm(ast, 0x1E6E0004); - ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000); + reg_04 = ast_mindwm(ast, AST_REG_MCR04); + ast_moutdwm(ast, AST_REG_MCR04, reg_04 | 0x1000); do - data = ast_mindwm(ast, 0x1E6E0004); + data = ast_mindwm(ast, AST_REG_MCR04); while (!(data & 0x80000)); - ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400); + ast_moutdwm(ast, AST_REG_MCR04, reg_04 | 0x400); } static void set_mpll_2500(struct ast_device *ast) { - u32 addr, data, param; + u32 mcr, data, param; /* Reset MMC */ - ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); - ast_moutdwm(ast, 0x1E6E0034, 0x00020080); - for (addr = 0x1e6e0004; addr < 0x1e6e0090;) { - ast_moutdwm(ast, addr, 0x0); - addr += 4; - } - ast_moutdwm(ast, 0x1E6E0034, 0x00020000); + ast_moutdwm(ast, AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY); + ast_moutdwm(ast, AST_REG_MCR34, 0x00020080); + for (mcr = AST_REG_MCR04; mcr <= AST_REG_MCR8C; mcr += 4) + ast_moutdwm(ast, mcr, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR34, 0x00020000); - ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); - data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000; + ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); + data = ast_mindwm(ast, AST_REG_SCU070) & 0x00800000; if (data) { /* CLKIN = 25MHz */ param = 0x930023E0; - ast_moutdwm(ast, 0x1E6E2160, 0x00011320); + ast_moutdwm(ast, AST_REG_SCU160, 0x00011320); } else { /* CLKIN = 24MHz */ param = 0x93002400; } - ast_moutdwm(ast, 0x1E6E2020, param); + ast_moutdwm(ast, AST_REG_SCU020, param); udelay(100); } static void reset_mmc_2500(struct ast_device *ast) { - ast_moutdwm(ast, 0x1E78505C, 0x00000004); - ast_moutdwm(ast, 0x1E785044, 0x00000001); - ast_moutdwm(ast, 0x1E785048, 0x00004755); - ast_moutdwm(ast, 0x1E78504C, 0x00000013); + ast_moutdwm(ast, AST_REG_WDT1C(1), 0x00000004); + ast_moutdwm(ast, AST_REG_WDT04(1), 0x00000001); + ast_moutdwm(ast, AST_REG_WDT08(1), 0x00004755); + ast_moutdwm(ast, AST_REG_WDT0C(1), 0x00000013); mdelay(100); - ast_moutdwm(ast, 0x1E785054, 0x00000077); - ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); + ast_moutdwm(ast, AST_REG_WDT14(1), 0x00000077); + ast_moutdwm(ast, AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY); } static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table) { - ast_moutdwm(ast, 0x1E6E0004, 0x00000303); - ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); - ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); - ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); - ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ - ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ - ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ - ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ + ast_moutdwm(ast, AST_REG_MCR04, 0x00000303); + ast_moutdwm(ast, AST_REG_MCR10, ddr_table[REGIDX_010]); + ast_moutdwm(ast, AST_REG_MCR14, ddr_table[REGIDX_014]); + ast_moutdwm(ast, AST_REG_MCR18, ddr_table[REGIDX_018]); + ast_moutdwm(ast, AST_REG_MCR20, ddr_table[REGIDX_020]); /* MODEREG4/6 */ + ast_moutdwm(ast, AST_REG_MCR24, ddr_table[REGIDX_024]); /* MODEREG5 */ + ast_moutdwm(ast, AST_REG_MCR2C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ + ast_moutdwm(ast, AST_REG_MCR30, ddr_table[REGIDX_030]); /* MODEREG1/3 */ /* DDR PHY Setting */ - ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE); - ast_moutdwm(ast, 0x1E6E0204, 0x00001001); - ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); - ast_moutdwm(ast, 0x1E6E0210, 0x20000000); - ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); - ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); - ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); - ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); - ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); - ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); - ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); - ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); - ast_moutdwm(ast, 0x1E6E0290, 0x00100008); - ast_moutdwm(ast, 0x1E6E02C0, 0x00000006); + ast_moutdwm(ast, AST_REG_MCR200, 0x02492AAE); + ast_moutdwm(ast, AST_REG_MCR204, 0x00001001); + ast_moutdwm(ast, AST_REG_MCR20C, 0x55E00B0B); + ast_moutdwm(ast, AST_REG_MCR210, 0x20000000); + ast_moutdwm(ast, AST_REG_MCR214, ddr_table[REGIDX_214]); + ast_moutdwm(ast, AST_REG_MCR2E0, ddr_table[REGIDX_2E0]); + ast_moutdwm(ast, AST_REG_MCR2E4, ddr_table[REGIDX_2E4]); + ast_moutdwm(ast, AST_REG_MCR2E8, ddr_table[REGIDX_2E8]); + ast_moutdwm(ast, AST_REG_MCR2EC, ddr_table[REGIDX_2EC]); + ast_moutdwm(ast, AST_REG_MCR2F0, ddr_table[REGIDX_2F0]); + ast_moutdwm(ast, AST_REG_MCR2F4, ddr_table[REGIDX_2F4]); + ast_moutdwm(ast, AST_REG_MCR2F8, ddr_table[REGIDX_2F8]); + ast_moutdwm(ast, AST_REG_MCR290, 0x00100008); + ast_moutdwm(ast, AST_REG_MCR2C0, 0x00000006); /* Controller Setting */ - ast_moutdwm(ast, 0x1E6E0034, 0x00020091); + ast_moutdwm(ast, AST_REG_MCR34, 0x00020091); /* Wait DDR PHY init done */ ddr_phy_init_2500(ast); - ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); - ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); - ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); + ast_moutdwm(ast, AST_REG_MCR120, ddr_table[REGIDX_PLL]); + ast_moutdwm(ast, AST_REG_MCR0C, 0x42AA5C81); + ast_moutdwm(ast, AST_REG_MCR34, 0x0001AF93); check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); enable_cache_2500(ast); - ast_moutdwm(ast, 0x1E6E001C, 0x00000008); - ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); + ast_moutdwm(ast, AST_REG_MCR1C, 0x00000008); + ast_moutdwm(ast, AST_REG_MCR38, 0xFFFFFF00); } static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table) @@ -363,34 +364,34 @@ static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table) u32 min_ddr_vref = 0, min_phy_vref = 0; u32 max_ddr_vref = 0, max_phy_vref = 0; - ast_moutdwm(ast, 0x1E6E0004, 0x00000313); - ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); - ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); - ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); - ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ - ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ - ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ - ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ + ast_moutdwm(ast, AST_REG_MCR04, 0x00000313); + ast_moutdwm(ast, AST_REG_MCR10, ddr_table[REGIDX_010]); + ast_moutdwm(ast, AST_REG_MCR14, ddr_table[REGIDX_014]); + ast_moutdwm(ast, AST_REG_MCR18, ddr_table[REGIDX_018]); + ast_moutdwm(ast, AST_REG_MCR20, ddr_table[REGIDX_020]); /* MODEREG4/6 */ + ast_moutdwm(ast, AST_REG_MCR24, ddr_table[REGIDX_024]); /* MODEREG5 */ + ast_moutdwm(ast, AST_REG_MCR2C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ + ast_moutdwm(ast, AST_REG_MCR30, ddr_table[REGIDX_030]); /* MODEREG1/3 */ /* DDR PHY Setting */ - ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE); - ast_moutdwm(ast, 0x1E6E0204, 0x09002000); - ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); - ast_moutdwm(ast, 0x1E6E0210, 0x20000000); - ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); - ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); - ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); - ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); - ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); - ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); - ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); - ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); - ast_moutdwm(ast, 0x1E6E0290, 0x00100008); - ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C); - ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E); + ast_moutdwm(ast, AST_REG_MCR200, 0x42492AAE); + ast_moutdwm(ast, AST_REG_MCR204, 0x09002000); + ast_moutdwm(ast, AST_REG_MCR20C, 0x55E00B0B); + ast_moutdwm(ast, AST_REG_MCR210, 0x20000000); + ast_moutdwm(ast, AST_REG_MCR214, ddr_table[REGIDX_214]); + ast_moutdwm(ast, AST_REG_MCR2E0, ddr_table[REGIDX_2E0]); + ast_moutdwm(ast, AST_REG_MCR2E4, ddr_table[REGIDX_2E4]); + ast_moutdwm(ast, AST_REG_MCR2E8, ddr_table[REGIDX_2E8]); + ast_moutdwm(ast, AST_REG_MCR2EC, ddr_table[REGIDX_2EC]); + ast_moutdwm(ast, AST_REG_MCR2F0, ddr_table[REGIDX_2F0]); + ast_moutdwm(ast, AST_REG_MCR2F4, ddr_table[REGIDX_2F4]); + ast_moutdwm(ast, AST_REG_MCR2F8, ddr_table[REGIDX_2F8]); + ast_moutdwm(ast, AST_REG_MCR290, 0x00100008); + ast_moutdwm(ast, AST_REG_MCR2C4, 0x3C183C3C); + ast_moutdwm(ast, AST_REG_MCR2C8, 0x00631E0E); /* Controller Setting */ - ast_moutdwm(ast, 0x1E6E0034, 0x0001A991); + ast_moutdwm(ast, AST_REG_MCR34, 0x0001A991); /* Train PHY Vref first */ pass = 0; @@ -398,17 +399,17 @@ static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table) for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { max_phy_vref = 0x0; pass = 0; - ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06); + ast_moutdwm(ast, AST_REG_MCR2C0, 0x00001C06); for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) { - ast_moutdwm(ast, 0x1E6E000C, 0x00000000); - ast_moutdwm(ast, 0x1E6E0060, 0x00000000); - ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8)); + ast_moutdwm(ast, AST_REG_MCR0C, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR60, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR2CC, phy_vref | (phy_vref << 8)); /* Fire DFI Init */ ddr_phy_init_2500(ast); - ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); + ast_moutdwm(ast, AST_REG_MCR0C, 0x00005C01); if (cbr_test_2500(ast)) { pass++; - data = ast_mindwm(ast, 0x1E6E03D0); + data = ast_mindwm(ast, AST_REG_MCR3D0); data2 = data >> 8; data = data & 0xff; if (data > data2) @@ -422,7 +423,7 @@ static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table) } } } - ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8)); + ast_moutdwm(ast, AST_REG_MCR2CC, min_phy_vref | (min_phy_vref << 8)); /* Train DDR Vref next */ pass = 0; @@ -432,12 +433,12 @@ static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table) max_ddr_vref = 0x0; pass = 0; for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) { - ast_moutdwm(ast, 0x1E6E000C, 0x00000000); - ast_moutdwm(ast, 0x1E6E0060, 0x00000000); - ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); + ast_moutdwm(ast, AST_REG_MCR0C, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR60, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR2C0, 0x00000006 | (ddr_vref << 8)); /* Fire DFI Init */ ddr_phy_init_2500(ast); - ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); + ast_moutdwm(ast, AST_REG_MCR0C, 0x00005C01); if (cbr_test_2500(ast)) { pass++; if (min_ddr_vref > ddr_vref) @@ -450,22 +451,22 @@ static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table) } } - ast_moutdwm(ast, 0x1E6E000C, 0x00000000); - ast_moutdwm(ast, 0x1E6E0060, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR0C, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR60, 0x00000000); ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1; - ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); + ast_moutdwm(ast, AST_REG_MCR2C0, 0x00000006 | (ddr_vref << 8)); /* Wait DDR PHY init done */ ddr_phy_init_2500(ast); - ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); - ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); - ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); + ast_moutdwm(ast, AST_REG_MCR120, ddr_table[REGIDX_PLL]); + ast_moutdwm(ast, AST_REG_MCR0C, 0x42AA5C81); + ast_moutdwm(ast, AST_REG_MCR34, 0x0001AF93); check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); enable_cache_2500(ast); - ast_moutdwm(ast, 0x1E6E001C, 0x00000008); - ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); + ast_moutdwm(ast, AST_REG_MCR1C, 0x00000008); + ast_moutdwm(ast, AST_REG_MCR38, 0xFFFFFF00); } static bool ast_dram_init_2500(struct ast_device *ast) @@ -480,18 +481,18 @@ static bool ast_dram_init_2500(struct ast_device *ast) reset_mmc_2500(ast); ddr_init_common_2500(ast); - data = ast_mindwm(ast, 0x1E6E2070); + data = ast_mindwm(ast, AST_REG_SCU070); if (data & 0x01000000) ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table); else ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table); } while (!ddr_test_2500(ast)); - ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41); + ast_moutdwm(ast, AST_REG_SCU040, ast_mindwm(ast, AST_REG_SCU040) | 0x41); /* Patch code */ - data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF; - ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000); + data = ast_mindwm(ast, AST_REG_SCU00C) & 0xF9FFFFFF; + ast_moutdwm(ast, AST_REG_SCU00C, data | 0x10000000); return true; } @@ -504,12 +505,14 @@ static void ast_post_chip_2500(struct ast_device *ast) reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); if ((reg & AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */ + u32 scu008; + /* Clear bus lock condition */ ast_2500_patch_ahb(ast->regs); /* Disable watchdog */ - ast_moutdwm(ast, 0x1E78502C, 0x00000000); - ast_moutdwm(ast, 0x1E78504C, 0x00000000); + ast_moutdwm(ast, AST_REG_WDT2C(0), 0x00000000); + ast_moutdwm(ast, AST_REG_WDT0C(1), 0x00000000); /* * Reset USB port to patch USB unknown device issue @@ -524,28 +527,28 @@ static void ast_post_chip_2500(struct ast_device *ast) * SCU7C is Write clear reg to SCU70 * [23]:= write 1 and then SCU70[23] will be clear as 0b. */ - ast_moutdwm(ast, 0x1E6E2090, 0x20000000); - ast_moutdwm(ast, 0x1E6E2094, 0x00004000); - if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) { - ast_moutdwm(ast, 0x1E6E207C, 0x00800000); + ast_moutdwm(ast, AST_REG_SCU090, 0x20000000); + ast_moutdwm(ast, AST_REG_SCU094, 0x00004000); + if (ast_mindwm(ast, AST_REG_SCU070) & 0x00800000) { + ast_moutdwm(ast, AST_REG_SCU07C, 0x00800000); mdelay(100); - ast_moutdwm(ast, 0x1E6E2070, 0x00800000); + ast_moutdwm(ast, AST_REG_SCU070, 0x00800000); } /* Modify eSPI reset pin */ - temp = ast_mindwm(ast, 0x1E6E2070); + temp = ast_mindwm(ast, AST_REG_SCU070); if (temp & 0x02000000) - ast_moutdwm(ast, 0x1E6E207C, 0x00004000); + ast_moutdwm(ast, AST_REG_SCU07C, 0x00004000); /* Slow down CPU/AHB CLK in VGA only mode */ - temp = ast_read32(ast, 0x12008); - temp |= 0x73; - ast_write32(ast, 0x12008, temp); + scu008 = ast_mindwm(ast, AST_REG_SCU008); + scu008 |= 0x00000073; + ast_moutdwm(ast, AST_REG_SCU008, scu008); if (!ast_dram_init_2500(ast)) drm_err(dev, "DRAM init failed !\n"); - temp = ast_mindwm(ast, 0x1e6e2040); - ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); + temp = ast_mindwm(ast, AST_REG_SCU040); + ast_moutdwm(ast, AST_REG_SCU040, temp | 0x40); } /* wait ready */ diff --git a/drivers/gpu/drm/ast/ast_cursor.c b/drivers/gpu/drm/ast/ast_cursor.c index 3fa8e75db9c0..fd19c45f2abe 100644 --- a/drivers/gpu/drm/ast/ast_cursor.c +++ b/drivers/gpu/drm/ast/ast_cursor.c @@ -164,7 +164,7 @@ static const uint32_t ast_cursor_plane_formats[] = { }; static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); struct drm_framebuffer *new_fb = new_plane_state->fb; @@ -244,7 +244,7 @@ static const u8 *ast_cursor_plane_get_argb4444(struct ast_cursor_plane *ast_curs } static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane); struct ast_plane *ast_plane = to_ast_plane(plane); @@ -309,7 +309,7 @@ static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, } static void ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(plane->dev); diff --git a/drivers/gpu/drm/ast/ast_dp.c b/drivers/gpu/drm/ast/ast_dp.c index 9d07dad358cf..5f266a05419b 100644 --- a/drivers/gpu/drm/ast/ast_dp.c +++ b/drivers/gpu/drm/ast/ast_dp.c @@ -359,7 +359,7 @@ static void ast_astdp_encoder_helper_atomic_mode_set(struct drm_encoder *encoder } static void ast_astdp_encoder_helper_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(encoder->dev); struct ast_connector *ast_connector = &ast->output.astdp.connector; @@ -374,7 +374,7 @@ static void ast_astdp_encoder_helper_atomic_enable(struct drm_encoder *encoder, } static void ast_astdp_encoder_helper_atomic_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(encoder->dev); diff --git a/drivers/gpu/drm/ast/ast_dp501.c b/drivers/gpu/drm/ast/ast_dp501.c index 677c52c0d99a..6d6ccfad1415 100644 --- a/drivers/gpu/drm/ast/ast_dp501.c +++ b/drivers/gpu/drm/ast/ast_dp501.c @@ -183,7 +183,7 @@ static void ast_set_dp501_video_output(struct ast_device *ast, u8 mode) static u32 get_fw_base(struct ast_device *ast) { - return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff; + return ast_mindwm(ast, AST_REG_SCU104) & 0x7fffffff; } bool ast_backup_fw(struct ast_device *ast, u8 *addr, u32 size) @@ -194,7 +194,7 @@ bool ast_backup_fw(struct ast_device *ast, u8 *addr, u32 size) if (ast->config_mode != ast_use_p2a) return false; - data = ast_mindwm(ast, 0x1e6e2100) & 0x01; + data = ast_mindwm(ast, AST_REG_SCU100) & 0x01; if (data) { boot_address = get_fw_base(ast); for (i = 0; i < size; i += 4) @@ -214,7 +214,7 @@ static bool ast_launch_m68k(struct ast_device *ast) if (ast->config_mode != ast_use_p2a) return false; - data = ast_mindwm(ast, 0x1e6e2100) & 0x01; + data = ast_mindwm(ast, AST_REG_SCU100) & 0x01; if (!data) { if (ast->dp501_fw_addr) { @@ -229,8 +229,8 @@ static bool ast_launch_m68k(struct ast_device *ast) len = ast->dp501_fw->size; } /* Get BootAddress */ - ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8); - data = ast_mindwm(ast, 0x1e6e0004); + ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); + data = ast_mindwm(ast, AST_REG_MCR04); switch (data & 0x03) { case 0: boot_address = 0x44000000; @@ -255,16 +255,16 @@ static bool ast_launch_m68k(struct ast_device *ast) } /* Init SCU */ - ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8); + ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); /* Launch FW */ - ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address); - ast_moutdwm(ast, 0x1e6e2100, 1); + ast_moutdwm(ast, AST_REG_SCU104, 0x80000000 + boot_address); + ast_moutdwm(ast, AST_REG_SCU100, 1); /* Update Scratch */ - data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */ - data |= 0x800; - ast_moutdwm(ast, 0x1e6e2040, data); + data = ast_mindwm(ast, AST_REG_SCU040) & 0xfffff1ff; + data |= 0x800; /* D[11:9] = 100b: UEFI handling */ + ast_moutdwm(ast, AST_REG_SCU040, data); jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */ jreg |= 0x02; @@ -347,68 +347,65 @@ static int ast_dp512_read_edid_block(void *data, u8 *buf, unsigned int block, si static bool ast_init_dvo(struct ast_device *ast) { u8 jreg; - u32 data; - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - ast_write32(ast, 0x12000, 0x1688a8a8); + u32 scu02c; + + ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); if (!(jreg & 0x80)) { + u32 scu008; + /* Init SCU DVO Settings */ - data = ast_read32(ast, 0x12008); - /* delay phase */ - data &= 0xfffff8ff; - data |= 0x00000500; - ast_write32(ast, 0x12008, data); + + scu008 = ast_mindwm(ast, AST_REG_SCU008); + scu008 &= 0xfffff8ff; + scu008 |= 0x00000500; /* delay phase */ + ast_moutdwm(ast, AST_REG_SCU008, scu008); if (IS_AST_GEN4(ast)) { - data = ast_read32(ast, 0x12084); - /* multi-pins for DVO single-edge */ - data |= 0xfffe0000; - ast_write32(ast, 0x12084, data); + u32 scu084, scu088, scu090; - data = ast_read32(ast, 0x12088); - /* multi-pins for DVO single-edge */ - data |= 0x000fffff; - ast_write32(ast, 0x12088, data); + scu084 = ast_mindwm(ast, AST_REG_SCU084); + scu084 |= 0xfffe0000; /* multi-pins for DVO single-edge */ + ast_moutdwm(ast, AST_REG_SCU084, scu084); - data = ast_read32(ast, 0x12090); - /* multi-pins for DVO single-edge */ - data &= 0xffffffcf; - data |= 0x00000020; - ast_write32(ast, 0x12090, data); + scu088 = ast_mindwm(ast, AST_REG_SCU088); + scu088 |= 0x000fffff; /* multi-pins for DVO single-edge */ + ast_moutdwm(ast, AST_REG_SCU088, scu088); + + scu090 = ast_mindwm(ast, AST_REG_SCU090); + scu090 &= 0xffffffcf; + scu090 |= 0x00000020; /* multi-pins for DVO single-edge */ + ast_moutdwm(ast, AST_REG_SCU090, scu090); } else { /* AST GEN5+ */ - data = ast_read32(ast, 0x12088); - /* multi-pins for DVO single-edge */ - data |= 0x30000000; - ast_write32(ast, 0x12088, data); + u32 scu088, scu08c, scu0a4, scu0a8, scu094; - data = ast_read32(ast, 0x1208c); - /* multi-pins for DVO single-edge */ - data |= 0x000000cf; - ast_write32(ast, 0x1208c, data); + scu088 = ast_mindwm(ast, AST_REG_SCU088); + scu088 |= 0x30000000; /* multi-pins for DVO single-edge */ + ast_moutdwm(ast, AST_REG_SCU088, scu088); - data = ast_read32(ast, 0x120a4); - /* multi-pins for DVO single-edge */ - data |= 0xffff0000; - ast_write32(ast, 0x120a4, data); + scu08c = ast_mindwm(ast, AST_REG_SCU08C); + scu08c |= 0x000000cf; /* multi-pins for DVO single-edge */ + ast_moutdwm(ast, AST_REG_SCU08C, scu08c); - data = ast_read32(ast, 0x120a8); - /* multi-pins for DVO single-edge */ - data |= 0x0000000f; - ast_write32(ast, 0x120a8, data); + scu0a4 = ast_mindwm(ast, AST_REG_SCU0A4); + scu0a4 |= 0xffff0000; /* multi-pins for DVO single-edge */ + ast_moutdwm(ast, AST_REG_SCU0A4, scu0a4); - data = ast_read32(ast, 0x12094); - /* multi-pins for DVO single-edge */ - data |= 0x00000002; - ast_write32(ast, 0x12094, data); + scu0a8 = ast_mindwm(ast, AST_REG_SCU0A8); + scu0a8 |= 0x0000000f; /* multi-pins for DVO single-edge */ + ast_moutdwm(ast, AST_REG_SCU0A8, scu0a8); + + scu094 = ast_mindwm(ast, AST_REG_SCU094); + scu094 |= 0x00000002; /* multi-pins for DVO single-edge */ + ast_moutdwm(ast, AST_REG_SCU094, scu094); } } /* Force to DVO */ - data = ast_read32(ast, 0x1202c); - data &= 0xfffbffff; - ast_write32(ast, 0x1202c, data); + scu02c = ast_mindwm(ast, AST_REG_SCU02C); + scu02c &= 0xfffbffff; + ast_moutdwm(ast, AST_REG_SCU02C, scu02c); /* Init VGA DVO Settings */ ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); @@ -418,25 +415,20 @@ static bool ast_init_dvo(struct ast_device *ast) static void ast_init_analog(struct ast_device *ast) { - u32 data; + u32 scu02c; /* * Set DAC source to VGA mode in SCU2C via the P2A - * bridge. First configure the P2U to target the SCU - * in case it isn't at this stage. + * bridge. */ - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - /* Then unlock the SCU with the magic password */ - ast_write32(ast, 0x12000, 0x1688a8a8); - ast_write32(ast, 0x12000, 0x1688a8a8); - ast_write32(ast, 0x12000, 0x1688a8a8); + /* Unlock the SCU with the magic password */ + ast_moutdwm_poll(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY, 0x01); - /* Finally, clear bits [17:16] of SCU2c */ - data = ast_read32(ast, 0x1202c); - data &= 0xfffcffff; - ast_write32(ast, 0x1202c, data); + /* Clear bits [17:16] of SCU2C */ + scu02c = ast_mindwm(ast, AST_REG_SCU02C); + scu02c &= 0xfffcffff; + ast_moutdwm(ast, AST_REG_SCU02C, scu02c); /* Disable DVO */ ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x00); @@ -477,7 +469,7 @@ static const struct drm_encoder_funcs ast_dp501_encoder_funcs = { }; static void ast_dp501_encoder_helper_atomic_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(encoder->dev); @@ -485,7 +477,7 @@ static void ast_dp501_encoder_helper_atomic_enable(struct drm_encoder *encoder, } static void ast_dp501_encoder_helper_atomic_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(encoder->dev); diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c index b9a9b050b546..ba6cf5fa901c 100644 --- a/drivers/gpu/drm/ast/ast_drv.c +++ b/drivers/gpu/drm/ast/ast_drv.c @@ -47,6 +47,77 @@ static int ast_modeset = -1; MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); module_param_named(modeset, ast_modeset, int, 0400); +/* + * Register access + */ + +/* Select R/W segment */ +static void __ast_selseg(void __iomem *regs, u32 r) +{ + u32 p2a04, p2a04_base; + + p2a04 = r & AST_REG_P2A04_BASE_MASK; + __ast_write32(regs, AST_REG_P2A04, p2a04); + __ast_write32(regs, AST_REG_P2A00, AST_REG_P2A00_PROTECTION_KEY); + + do { + cpu_relax(); + p2a04_base = __ast_read32(regs, AST_REG_P2A04); + p2a04_base &= AST_REG_P2A04_BASE_MASK; + } while (p2a04_base != p2a04); +} + +/* Read within segment */ +static u32 __ast_rdseg32(void __iomem *regs, u32 r) +{ + return __ast_read32(regs, AST_REG_P2A_ADDR(r)); +} + +/* Write within segment */ +static void __ast_wrseg32(void __iomem *regs, u32 r, u32 v) +{ + __ast_write32(regs, AST_REG_P2A_ADDR(r), v); +} + +u32 __ast_mindwm(void __iomem *regs, u32 r) +{ + __ast_selseg(regs, r); + + return __ast_rdseg32(regs, r); +} + +void __ast_moutdwm(void __iomem *regs, u32 r, u32 v) +{ + __ast_selseg(regs, r); + __ast_wrseg32(regs, r, v); +} + +u32 ast_mindwm(struct ast_device *ast, u32 r) +{ + return __ast_mindwm(ast->regs, r); +} + +void ast_moutdwm(struct ast_device *ast, u32 r, u32 v) +{ + __ast_moutdwm(ast->regs, r, v); +} + +void ast_moutdwm_poll(struct ast_device *ast, u32 r, u32 v, u32 res) +{ + void __iomem *regs = ast->regs; + + __ast_selseg(regs, r); + __ast_wrseg32(regs, r, v); + + do { + cpu_relax(); + } while (__ast_rdseg32(regs, r) != res); +} + +/* + * AST device + */ + void ast_device_init(struct ast_device *ast, enum ast_chip chip, enum ast_config_mode config_mode, @@ -171,7 +242,7 @@ static int ast_detect_chip(struct pci_dev *pdev, enum ast_config_mode config_mode = ast_use_defaults; uint32_t scu_rev = 0xffffffff; enum ast_chip chip; - u32 data; + u32 data, p2a04, scu07c; u8 vgacrd0, vgacrd1; /* @@ -204,14 +275,13 @@ static int ast_detect_chip(struct pci_dev *pdev, } /* Double check that it's actually working */ - data = __ast_read32(regs, 0xf004); - if ((data != 0xffffffff) && (data != 0x00)) { + p2a04 = __ast_read32(regs, AST_REG_P2A04); + if (p2a04 != 0xffffffff && p2a04 != 0x00000000) { config_mode = ast_use_p2a; - /* Read SCU7c (silicon revision register) */ - __ast_write32(regs, 0xf004, 0x1e6e0000); - __ast_write32(regs, 0xf000, 0x1); - scu_rev = __ast_read32(regs, 0x1207c); + /* Read SCU7C (silicon revision register) */ + scu07c = __ast_mindwm(regs, AST_REG_SCU07C); + scu_rev = scu07c & AST_REG_SCU07C_CHIP_BONDING_MASK; } } } diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index 787e38c6c17d..4f221b848d68 100644 --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h @@ -259,26 +259,20 @@ static inline bool __ast_gen_is_eq(struct ast_device *ast, unsigned long gen) #define IS_AST_GEN6(__ast) __ast_gen_is_eq(__ast, 6) #define IS_AST_GEN7(__ast) __ast_gen_is_eq(__ast, 7) +/* + * MMIO access + */ + static inline u8 __ast_read8(const void __iomem *addr, u32 reg) { return ioread8(addr + reg); } -static inline u32 __ast_read32(const void __iomem *addr, u32 reg) -{ - return ioread32(addr + reg); -} - static inline void __ast_write8(void __iomem *addr, u32 reg, u8 val) { iowrite8(val, addr + reg); } -static inline void __ast_write32(void __iomem *addr, u32 reg, u32 val) -{ - iowrite32(val, addr + reg); -} - static inline u8 __ast_read8_i(void __iomem *addr, u32 reg, u8 index) { __ast_write8(addr, reg, index); @@ -307,16 +301,6 @@ static inline void __ast_write8_i_masked(void __iomem *addr, u32 reg, u8 index, __ast_write8_i(addr, reg, index, tmp | val); } -static inline u32 ast_read32(struct ast_device *ast, u32 reg) -{ - return __ast_read32(ast->regs, reg); -} - -static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val) -{ - __ast_write32(ast->regs, reg, val); -} - static inline u8 ast_io_read8(struct ast_device *ast, u32 reg) { return __ast_read8(ast->ioregs, reg); @@ -349,6 +333,40 @@ static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 i __ast_write8_i_masked(ast->ioregs, base, index, preserve_mask, val); } +/* + * Register access + */ + +static inline u32 __ast_read32(const void __iomem *addr, u32 reg) +{ + return ioread32(addr + reg); +} + +static inline void __ast_write32(void __iomem *addr, u32 reg, u32 val) +{ + iowrite32(val, addr + reg); +} + +static inline u32 ast_read32(struct ast_device *ast, u32 reg) +{ + return __ast_read32(ast->regs, reg); +} + +static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val) +{ + __ast_write32(ast->regs, reg, val); +} + +u32 __ast_mindwm(void __iomem *regs, u32 r); +void __ast_moutdwm(void __iomem *regs, u32 r, u32 v); +u32 ast_mindwm(struct ast_device *ast, u32 r); +void ast_moutdwm(struct ast_device *ast, u32 r, u32 v); +void ast_moutdwm_poll(struct ast_device *ast, u32 r, u32 v, u32 res); + +/* + * VBIOS + */ + struct ast_vbios_stdtable { u8 misc; u8 seq[4]; @@ -517,8 +535,6 @@ struct drm_device *ast_2600_device_create(struct pci_dev *pdev, /* ast post */ int ast_post_gpu(struct ast_device *ast); -u32 ast_mindwm(struct ast_device *ast, u32 r); -void ast_moutdwm(struct ast_device *ast, u32 r, u32 v); int ast_vga_output_init(struct ast_device *ast); int ast_sil164_output_init(struct ast_device *ast); diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index 21abb6a6d8bc..d5ed8c5c7925 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -105,8 +105,9 @@ static void ast_crtc_fill_gamma(struct ast_device *ast, /* gamma table is used as color palette */ drm_crtc_fill_palette_8(crtc, ast_set_gamma_lut); break; + case DRM_FORMAT_XRGB1555: case DRM_FORMAT_RGB565: - /* also uses 8-bit gamma ramp on low-color modes */ + /* also uses 24-bit gamma correction on high-color modes */ fallthrough; case DRM_FORMAT_XRGB8888: drm_crtc_fill_gamma_888(crtc, ast_set_gamma_lut); @@ -129,8 +130,9 @@ static void ast_crtc_load_gamma(struct ast_device *ast, /* gamma table is used as color palette */ drm_crtc_load_palette_8(crtc, lut, ast_set_gamma_lut); break; + case DRM_FORMAT_XRGB1555: case DRM_FORMAT_RGB565: - /* also uses 8-bit gamma ramp on low-color modes */ + /* also uses 24-bit gamma correction on high-color modes */ fallthrough; case DRM_FORMAT_XRGB8888: drm_crtc_load_gamma_888(crtc, lut, ast_set_gamma_lut); @@ -146,30 +148,35 @@ static void ast_set_vbios_color_reg(struct ast_device *ast, const struct drm_format_info *format, const struct ast_vbios_enhtable *vmode) { - u32 color_index; + u8 vgacr8c = 0x00; + u8 vgacr92 = 0x00; - switch (format->cpp[0]) { - case 1: - color_index = VGAModeIndex - 1; + switch (format->format) { + case DRM_FORMAT_C8: + vgacr8c |= AST_IO_VGACR8C_CUR_MODE_VGA; + vgacr92 = 8; break; - case 2: - color_index = HiCModeIndex; + case DRM_FORMAT_XRGB1555: + vgacr8c |= AST_IO_VGACR8C_CUR_MODE_15_BPP; + vgacr92 = 15; break; - case 3: - case 4: - color_index = TrueCModeIndex; + case DRM_FORMAT_RGB565: + vgacr8c |= AST_IO_VGACR8C_CUR_MODE_16_BPP; + vgacr92 = 16; + break; + case DRM_FORMAT_XRGB8888: + vgacr8c |= AST_IO_VGACR8C_CUR_MODE_32_BPP; + vgacr92 = 32; break; - default: - return; } - ast_set_index_reg(ast, AST_IO_VGACRI, 0x8c, (u8)((color_index & 0x0f) << 4)); + ast_set_index_reg(ast, AST_IO_VGACRI, 0x8c, vgacr8c); ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00); if (vmode->flags & NewModeInfo) { - ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0xa8); - ast_set_index_reg(ast, AST_IO_VGACRI, 0x92, format->cpp[0] * 8); + ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, AST_IO_VGACR91_PASSWORD); + ast_set_index_reg(ast, AST_IO_VGACRI, 0x92, vgacr92); } } @@ -188,7 +195,7 @@ static void ast_set_vbios_mode_reg(struct ast_device *ast, ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00); if (vmode->flags & NewModeInfo) { - ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0xa8); + ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, AST_IO_VGACR91_PASSWORD); ast_set_index_reg(ast, AST_IO_VGACRI, 0x93, adjusted_mode->clock / 1000); ast_set_index_reg(ast, AST_IO_VGACRI, 0x94, adjusted_mode->crtc_hdisplay); ast_set_index_reg(ast, AST_IO_VGACRI, 0x95, adjusted_mode->crtc_hdisplay >> 8); @@ -381,30 +388,36 @@ static void ast_set_dclk_reg(struct ast_device *ast, static void ast_set_color_reg(struct ast_device *ast, const struct drm_format_info *format) { - u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; + u8 vgacra0 = 0x00; + u8 vgacra3 = 0x00; + u8 vgacra8 = 0x00; - switch (format->cpp[0] * 8) { - case 8: - jregA0 = 0x70; - jregA3 = 0x01; - jregA8 = 0x00; + vgacra0 |= AST_IO_VGACRA0_MEMORY_CHAIN4_MODE | + AST_IO_VGACRA0_LINEAR_EXT_ACCESS | + AST_IO_VGACRA0_SEGMENTED_EXT_ACCESS; + + switch (format->format) { + case DRM_FORMAT_C8: + vgacra3 |= AST_IO_VGACRA3_256_COLORS; + vgacra8 &= ~AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED; break; - case 15: - case 16: - jregA0 = 0x70; - jregA3 = 0x04; - jregA8 = 0x02; + case DRM_FORMAT_XRGB1555: + vgacra3 |= AST_IO_VGACRA3_15_BPP; + vgacra8 |= AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED; break; - case 32: - jregA0 = 0x70; - jregA3 = 0x08; - jregA8 = 0x02; + case DRM_FORMAT_RGB565: + vgacra3 |= AST_IO_VGACRA3_16_BPP; + vgacra8 |= AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED; + break; + case DRM_FORMAT_XRGB8888: + vgacra3 |= AST_IO_VGACRA3_32_BPP; + vgacra8 |= AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED; break; } - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa0, 0x8f, jregA0); - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xf0, jregA3); - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa8, 0xfd, jregA8); + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa0, 0x8f, vgacra0); + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xf0, vgacra3); + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa8, 0xfd, vgacra8); } static void ast_set_crtthd_reg(struct ast_device *ast) @@ -489,11 +502,12 @@ void __iomem *ast_plane_vaddr(struct ast_plane *ast_plane) static const uint32_t ast_primary_plane_formats[] = { DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB1555, DRM_FORMAT_C8, }; static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = plane->dev; struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -541,7 +555,7 @@ static void ast_handle_damage(struct ast_plane *ast_plane, struct iosys_map *src } static void ast_primary_plane_helper_atomic_update(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = plane->dev; struct ast_device *ast = to_ast_device(dev); @@ -585,7 +599,7 @@ static void ast_primary_plane_helper_atomic_update(struct drm_plane *plane, } static void ast_primary_plane_helper_atomic_enable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(plane->dev); struct ast_plane *ast_plane = to_ast_plane(plane); @@ -600,7 +614,7 @@ static void ast_primary_plane_helper_atomic_enable(struct drm_plane *plane, } static void ast_primary_plane_helper_atomic_disable(struct drm_plane *plane, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { /* * Keep this empty function to avoid calling @@ -708,7 +722,7 @@ static void ast_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) } static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; @@ -762,10 +776,10 @@ static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, case DRM_FORMAT_C8: ast_state->std_table = &vbios_stdtable[VGAModeIndex]; break; + case DRM_FORMAT_XRGB1555: case DRM_FORMAT_RGB565: ast_state->std_table = &vbios_stdtable[HiCModeIndex]; break; - case DRM_FORMAT_RGB888: case DRM_FORMAT_XRGB8888: ast_state->std_table = &vbios_stdtable[TrueCModeIndex]; break; @@ -808,7 +822,7 @@ static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, static void ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); @@ -830,7 +844,7 @@ ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, } } -static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) +static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(crtc->dev); u8 vgacr17 = 0x00; @@ -843,7 +857,7 @@ static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atom ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6); } -static void ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) +static void ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *state) { struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); struct ast_device *ast = to_ast_device(crtc->dev); @@ -952,7 +966,7 @@ static int ast_crtc_init(struct ast_device *ast) * Mode config */ -static void ast_mode_config_helper_atomic_commit_tail(struct drm_atomic_state *state) +static void ast_mode_config_helper_atomic_commit_tail(struct drm_atomic_commit *state) { struct ast_device *ast = to_ast_device(state->dev); diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c index b72914dbed38..297230f1efaf 100644 --- a/drivers/gpu/drm/ast/ast_post.c +++ b/drivers/gpu/drm/ast/ast_post.c @@ -34,44 +34,6 @@ #include "ast_drv.h" #include "ast_post.h" -u32 __ast_mindwm(void __iomem *regs, u32 r) -{ - u32 data; - - __ast_write32(regs, 0xf004, r & 0xffff0000); - __ast_write32(regs, 0xf000, 0x1); - - do { - data = __ast_read32(regs, 0xf004) & 0xffff0000; - } while (data != (r & 0xffff0000)); - - return __ast_read32(regs, 0x10000 + (r & 0x0000ffff)); -} - -void __ast_moutdwm(void __iomem *regs, u32 r, u32 v) -{ - u32 data; - - __ast_write32(regs, 0xf004, r & 0xffff0000); - __ast_write32(regs, 0xf000, 0x1); - - do { - data = __ast_read32(regs, 0xf004) & 0xffff0000; - } while (data != (r & 0xffff0000)); - - __ast_write32(regs, 0x10000 + (r & 0x0000ffff), v); -} - -u32 ast_mindwm(struct ast_device *ast, u32 r) -{ - return __ast_mindwm(ast->regs, r); -} - -void ast_moutdwm(struct ast_device *ast, u32 r, u32 v) -{ - __ast_moutdwm(ast->regs, r, v); -} - int ast_post_gpu(struct ast_device *ast) { int ret; @@ -107,19 +69,19 @@ bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl) { u32 data, timeout; - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); - ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, (datagen << 3) | test_ctl); timeout = 0; do { - data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; + data = ast_mindwm(ast, AST_REG_MCR70) & 0x3000; if (data & 0x2000) return false; if (++timeout > TIMEOUT) { - ast_moutdwm(ast, 0x1e6e0070, 0x00000000); + ast_moutdwm(ast, AST_REG_MCR70, 0x00000000); return false; } } while (!data); - ast_moutdwm(ast, 0x1e6e0070, 0x0); + ast_moutdwm(ast, AST_REG_MCR70, 0x0); return true; } diff --git a/drivers/gpu/drm/ast/ast_post.h b/drivers/gpu/drm/ast/ast_post.h index aa5d247bebe8..41b2db08a870 100644 --- a/drivers/gpu/drm/ast/ast_post.h +++ b/drivers/gpu/drm/ast/ast_post.h @@ -10,13 +10,10 @@ struct ast_device; /* DRAM timing tables */ struct ast_dramstruct { - u16 index; + u32 index; u32 data; }; -/* hardware fields */ -#define __AST_DRAMSTRUCT_DRAM_TYPE 0x0004 - /* control commands */ #define __AST_DRAMSTRUCT_UDELAY 0xff00 #define __AST_DRAMSTRUCT_INVALID 0xffff @@ -24,20 +21,21 @@ struct ast_dramstruct { #define __AST_DRAMSTRUCT_INDEX(_name) \ (__AST_DRAMSTRUCT_ ## _name) -#define AST_DRAMSTRUCT_INIT(_name, _value) \ - { __AST_DRAMSTRUCT_INDEX(_name), (_value) } +#define __AST_DRAMSTRUCT_INIT(_index, _value) \ + { (_index), (_value) } +#define AST_DRAMSTRUCT_REG(_reg, _value) \ + __AST_DRAMSTRUCT_INIT(_reg, _value) #define AST_DRAMSTRUCT_UDELAY(_usecs) \ - AST_DRAMSTRUCT_INIT(UDELAY, _usecs) + __AST_DRAMSTRUCT_INIT(__AST_DRAMSTRUCT_UDELAY, _usecs) #define AST_DRAMSTRUCT_INVALID \ - AST_DRAMSTRUCT_INIT(INVALID, U32_MAX) + __AST_DRAMSTRUCT_INIT(__AST_DRAMSTRUCT_INVALID, U32_MAX) +#define AST_DRAMSTRUCT_IS_REG(_entry, _reg) \ + ((_entry)->index == (_reg)) #define AST_DRAMSTRUCT_IS(_entry, _name) \ ((_entry)->index == __AST_DRAMSTRUCT_INDEX(_name)) -u32 __ast_mindwm(void __iomem *regs, u32 r); -void __ast_moutdwm(void __iomem *regs, u32 r, u32 v); - bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl); bool mmc_test_burst(struct ast_device *ast, u32 datagen); diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h index 30578e3b07e4..b808b0a02ba8 100644 --- a/drivers/gpu/drm/ast/ast_reg.h +++ b/drivers/gpu/drm/ast/ast_reg.h @@ -28,18 +28,49 @@ #define AST_IO_VGAPDR (0x49) #define AST_IO_VGAGRI (0x4E) -#define AST_IO_VGACRI (0x54) -#define AST_IO_VGACR17_SYNC_ENABLE BIT(7) /* called "Hardware reset" in docs */ -#define AST_IO_VGACR80_PASSWORD (0xa8) -#define AST_IO_VGACR99_VGAMEM_RSRV_MASK GENMASK(1, 0) -#define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1) -#define AST_IO_VGACRA1_MMIO_ENABLED BIT(2) -#define AST_IO_VGACRA3_DVO_ENABLED BIT(7) -#define AST_IO_VGACRAA_VGAMEM_SIZE_MASK GENMASK(1, 0) -#define AST_IO_VGACRB6_HSYNC_OFF BIT(0) -#define AST_IO_VGACRB6_VSYNC_OFF BIT(1) -#define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ -#define AST_IO_VGACRCB_HWC_ENABLED BIT(1) +#define AST_IO_VGACRI (0x54) +#define AST_IO_VGACR17_SYNC_ENABLE BIT(7) /* called "Hardware reset" in docs */ +#define AST_IO_VGACR80_PASSWORD (0xa8) + +#define AST_IO_VGACR8C_NEW_MODE_MASK GENMASK(3, 0) +#define AST_IO_VGACR8C_NEW_MODE_EGA (0x00) +#define AST_IO_VGACR8C_NEW_MODE_VGA (0x01) +#define AST_IO_VGACR8C_NEW_MODE_15_BPP (0x02) +#define AST_IO_VGACR8C_NEW_MODE_16_BPP (0x03) +#define AST_IO_VGACR8C_NEW_MODE_32_BPP (0x04) +#define AST_IO_VGACR8C_NEW_MODE_CGA (0x0f) +#define AST_IO_VGACR8C_NEW_MODE_TEXT (0x0e) +#define AST_IO_VGACR8C_CUR_MODE_MASK GENMASK(7, 4) +#define AST_IO_VGACR8C_CUR_MODE_EGA (0x00) +#define AST_IO_VGACR8C_CUR_MODE_VGA (0x10) +#define AST_IO_VGACR8C_CUR_MODE_15_BPP (0x20) +#define AST_IO_VGACR8C_CUR_MODE_16_BPP (0x30) +#define AST_IO_VGACR8C_CUR_MODE_32_BPP (0x40) +#define AST_IO_VGACR8C_CUR_MODE_CGA (0xf0) +#define AST_IO_VGACR8C_CUR_MODE_TEXT (0xe0) + +#define AST_IO_VGACR91_PASSWORD (0xa8) +#define AST_IO_VGACR99_VGAMEM_RSRV_MASK GENMASK(1, 0) + +#define AST_IO_VGACRA0_MEMORY_CHAIN4_MODE BIT(6) +#define AST_IO_VGACRA0_LINEAR_EXT_ACCESS BIT(5) +#define AST_IO_VGACRA0_SEGMENTED_EXT_ACCESS BIT(4) + +#define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1) +#define AST_IO_VGACRA1_MMIO_ENABLED BIT(2) + +#define AST_IO_VGACRA3_DVO_ENABLED BIT(7) +#define AST_IO_VGACRA3_32_BPP BIT(3) +#define AST_IO_VGACRA3_16_BPP BIT(2) +#define AST_IO_VGACRA3_15_BPP BIT(1) +#define AST_IO_VGACRA3_256_COLORS BIT(0) + +#define AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED BIT(1) +#define AST_IO_VGACRAA_VGAMEM_SIZE_MASK GENMASK(1, 0) +#define AST_IO_VGACRB6_HSYNC_OFF BIT(0) +#define AST_IO_VGACRB6_VSYNC_OFF BIT(1) +#define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ +#define AST_IO_VGACRCB_HWC_ENABLED BIT(1) /* mirrors SCU100[7:0] */ #define AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK GENMASK(7, 6) @@ -75,4 +106,160 @@ #define AST_IO_VGAIR1_R (0x5A) #define AST_IO_VGAIR1_VREFRESH BIT(3) +/* + * P-Bus to AHB Bridge (0x00000000 - 0x0001ffff) + */ + +#define AST_REG_P2A_BASE (0x00000000) +#define AST_REG_P2A(__offset) (AST_REG_P2A_BASE + (__offset)) +#define AST_REG_P2A_ADDR(__addr) AST_REG_P2A(0x10000 + ((__addr) & GENMASK(15, 0))) +#define AST_REG_P2A00 AST_REG_P2A(0xf000) +#define AST_REG_P2A00_PROTECTION_KEY (0x01) +#define AST_REG_P2A04 AST_REG_P2A(0xf004) +#define AST_REG_P2A04_BASE_MASK GENMASK(31, 16) + +/* + * AHB Controller (0x1e600000 - 0x1e61ffff) + */ + +#define AST_REG_AHBC_BASE (0x1e600000) +#define AST_REG_AHBC(__offset) (AST_REG_AHBC_BASE + (__offset)) +#define AST_REG_AHBC00 AST_REG_AHBC(0x00) +#define AST_REG_AHBC00_PROTECT_KEY (0xaeed1a03) +#define AST_REG_AHBC84 AST_REG_AHBC(0x84) +#define AST_REG_AHBC88 AST_REG_AHBC(0x88) + +/* + * SDRAM Memory Controller (0x1e6e0000 - 0x1e6e0fff) + */ + +#define AST_REG_MCR_BASE (0x1e6e0000) +#define AST_REG_MCR(__offset) (AST_REG_MCR_BASE + (__offset)) +#define AST_REG_MCR00 AST_REG_MCR(0x00) +#define AST_REG_MCR00_PROTECTION_KEY (0xfc600309) +#define AST_REG_MCR04 AST_REG_MCR(0x04) +#define AST_REG_MCR08 AST_REG_MCR(0x08) +#define AST_REG_MCR0C AST_REG_MCR(0x0c) +#define AST_REG_MCR10 AST_REG_MCR(0x10) +#define AST_REG_MCR14 AST_REG_MCR(0x14) +#define AST_REG_MCR18 AST_REG_MCR(0x18) +#define AST_REG_MCR1C AST_REG_MCR(0x1c) +#define AST_REG_MCR20 AST_REG_MCR(0x20) +#define AST_REG_MCR24 AST_REG_MCR(0x24) +#define AST_REG_MCR28 AST_REG_MCR(0x28) +#define AST_REG_MCR2C AST_REG_MCR(0x2C) +#define AST_REG_MCR30 AST_REG_MCR(0x30) +#define AST_REG_MCR34 AST_REG_MCR(0x34) +#define AST_REG_MCR38 AST_REG_MCR(0x38) +#define AST_REG_MCR3C AST_REG_MCR(0x3c) +#define AST_REG_MCR40 AST_REG_MCR(0x40) +#define AST_REG_MCR44 AST_REG_MCR(0x44) +#define AST_REG_MCR48 AST_REG_MCR(0x48) +#define AST_REG_MCR4C AST_REG_MCR(0x4C) +#define AST_REG_MCR50 AST_REG_MCR(0x50) +#define AST_REG_MCR54 AST_REG_MCR(0x54) +#define AST_REG_MCR58 AST_REG_MCR(0x58) +#define AST_REG_MCR5C AST_REG_MCR(0x5c) +#define AST_REG_MCR60 AST_REG_MCR(0x60) +#define AST_REG_MCR64 AST_REG_MCR(0x64) +#define AST_REG_MCR68 AST_REG_MCR(0x68) +#define AST_REG_MCR6C AST_REG_MCR(0x6c) +#define AST_REG_MCR70 AST_REG_MCR(0x70) +#define AST_REG_MCR74 AST_REG_MCR(0x74) +#define AST_REG_MCR78 AST_REG_MCR(0x78) +#define AST_REG_MCR7C AST_REG_MCR(0x7c) +#define AST_REG_MCR80 AST_REG_MCR(0x80) +#define AST_REG_MCR84 AST_REG_MCR(0x84) +#define AST_REG_MCR88 AST_REG_MCR(0x88) +#define AST_REG_MCR8C AST_REG_MCR(0x8c) +#define AST_REG_MCR100 AST_REG_MCR(0x100) +#define AST_REG_MCR108 AST_REG_MCR(0x108) +#define AST_REG_MCR120 AST_REG_MCR(0x120) +#define AST_REG_MCR140 AST_REG_MCR(0x140) +#define AST_REG_MCR200 AST_REG_MCR(0x200) +#define AST_REG_MCR204 AST_REG_MCR(0x204) +#define AST_REG_MCR208 AST_REG_MCR(0x208) +#define AST_REG_MCR20C AST_REG_MCR(0x20C) +#define AST_REG_MCR210 AST_REG_MCR(0x210) +#define AST_REG_MCR214 AST_REG_MCR(0x214) +#define AST_REG_MCR218 AST_REG_MCR(0x218) +#define AST_REG_MCR220 AST_REG_MCR(0x220) +#define AST_REG_MCR228 AST_REG_MCR(0x228) +#define AST_REG_MCR230 AST_REG_MCR(0x230) +#define AST_REG_MCR2A8 AST_REG_MCR(0x2a8) +#define AST_REG_MCR2B0 AST_REG_MCR(0x2b0) +#define AST_REG_MCR240 AST_REG_MCR(0x240) +#define AST_REG_MCR244 AST_REG_MCR(0x244) +#define AST_REG_MCR248 AST_REG_MCR(0x248) +#define AST_REG_MCR24C AST_REG_MCR(0x24c) +#define AST_REG_MCR290 AST_REG_MCR(0x290) +#define AST_REG_MCR2C0 AST_REG_MCR(0x2c0) +#define AST_REG_MCR2C4 AST_REG_MCR(0x2c4) +#define AST_REG_MCR2C8 AST_REG_MCR(0x2c8) +#define AST_REG_MCR2CC AST_REG_MCR(0x2cc) +#define AST_REG_MCR2E0 AST_REG_MCR(0x2e0) +#define AST_REG_MCR2E4 AST_REG_MCR(0x2e4) +#define AST_REG_MCR2E8 AST_REG_MCR(0x2e8) +#define AST_REG_MCR2EC AST_REG_MCR(0x2ec) +#define AST_REG_MCR2F0 AST_REG_MCR(0x2f0) +#define AST_REG_MCR2F4 AST_REG_MCR(0x2f4) +#define AST_REG_MCR2F8 AST_REG_MCR(0x2f8) +#define AST_REG_MCR300 AST_REG_MCR(0x300) +#define AST_REG_MCR3D0 AST_REG_MCR(0x3d0) + +/* + * System Control Unit (0x1e6e2000 - 0x1e6e2fff) + */ + +#define AST_REG_SCU_BASE (0x1e6e2000) +#define AST_REG_SCU(__offset) (AST_REG_SCU_BASE + (__offset)) +#define AST_REG_SCU000 AST_REG_SCU(0x000) +#define AST_REG_SCU000_PROTECTION_KEY (0x1688a8a8) +#define AST_REG_SCU008 AST_REG_SCU(0x008) +#define AST_REG_SCU00C AST_REG_SCU(0x00c) +#define AST_REG_SCU020 AST_REG_SCU(0x020) +#define AST_REG_SCU02C AST_REG_SCU(0x02c) +#define AST_REG_SCU040 AST_REG_SCU(0x040) +#define AST_REG_SCU070 AST_REG_SCU(0x070) +#define AST_REG_SCU07C AST_REG_SCU(0x07c) +#define AST_REG_SCU07C_CHIP_BONDING_MASK GENMASK(15, 8) +#define AST_REG_SCU084 AST_REG_SCU(0x084) +#define AST_REG_SCU088 AST_REG_SCU(0x088) +#define AST_REG_SCU08C AST_REG_SCU(0x08c) +#define AST_REG_SCU090 AST_REG_SCU(0x090) +#define AST_REG_SCU094 AST_REG_SCU(0x094) +#define AST_REG_SCU0A4 AST_REG_SCU(0x0a4) +#define AST_REG_SCU0A8 AST_REG_SCU(0x0a8) +#define AST_REG_SCU100 AST_REG_SCU(0x100) +#define AST_REG_SCU104 AST_REG_SCU(0x104) +#define AST_REG_SCU160 AST_REG_SCU(0x160) + +/* + * AHB-to-P Bus Bridge (0x1e720000 - 0x1e73ffff) + */ + +#define AST_REG_A2P_BASE (0x1e720000) +#define AST_REG_A2P(__offset) (AST_REG_A2P_BASE + (__offset)) +#define AST_REG_A2P58 AST_REG_A2P(0x58) + +/* + * Watchdog timer (0x1e785000 - 0x1e785fff) + */ + +#define AST_REG_WDT_BASE(__n) (0x1e785000 + (__n) * 0x40) +#define AST_REG_WDT(__n, __offset) (AST_REG_WDT_BASE((__n)) + (__offset)) +#define AST_REG_WDT04(__n) AST_REG_WDT((__n), 0x04) +#define AST_REG_WDT08(__n) AST_REG_WDT((__n), 0x08) +#define AST_REG_WDT0C(__n) AST_REG_WDT((__n), 0x0c) +#define AST_REG_WDT14(__n) AST_REG_WDT((__n), 0x14) +#define AST_REG_WDT1C(__n) AST_REG_WDT((__n), 0x1c) +#define AST_REG_WDT2C(__n) AST_REG_WDT((__n), 0x2c) + +/* + * SDRAM (0x80000000 - 0xffffffff) + */ + +#define AST_SDRAM_BASE (0x80000000) +#define AST_SDRAM(__offset) (AST_SDRAM_BASE + (__offset)) + #endif diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index d8cf3d231920..9dbac2def333 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -200,7 +200,7 @@ atmel_hlcdc_crtc_mode_valid(struct drm_crtc *c, } static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = c->dev; struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); @@ -252,7 +252,7 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, } static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_device *dev = c->dev; struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); @@ -458,7 +458,7 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) } static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_crtc_state *s = drm_atomic_get_new_crtc_state(state, c); int ret; @@ -475,13 +475,13 @@ static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c, } static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { drm_crtc_vblank_on(c); } static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *c, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); unsigned long flags; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index 97482fc82ec2..2f41bce574dc 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -983,7 +983,7 @@ static int atmel_hlcdc_dc_drm_suspend(struct device *dev) struct drm_device *drm_dev = dev_get_drvdata(dev); struct atmel_hlcdc_dc *dc = drm_dev->dev_private; struct regmap *regmap = dc->hlcdc->regmap; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; state = drm_atomic_helper_suspend(drm_dev); if (IS_ERR(state)) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index 26b26185cf34..390dfbf3c77d 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -354,7 +354,7 @@ struct atmel_hlcdc_dc { struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; struct { u32 imr; - struct drm_atomic_state *state; + struct drm_atomic_commit *state; } suspend; }; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index bccd1564216e..f17a832351e9 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -718,7 +718,7 @@ atmel_hlcdc_plane_update_disc_area(struct atmel_hlcdc_plane *plane, } static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *s = drm_atomic_get_new_plane_state(state, p); struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); @@ -869,7 +869,7 @@ static void atmel_xlcdc_atomic_disable(struct atmel_hlcdc_plane *plane, } static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; @@ -919,7 +919,7 @@ static void atmel_xlcdc_atomic_update(struct atmel_hlcdc_plane *plane, } static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_plane_state *new_s = drm_atomic_get_new_plane_state(state, p); diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index c3209b0f4678..f81b566c82a1 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -262,6 +262,16 @@ config DRM_NXP_PTN3460 help NXP PTN3460 eDP-LVDS bridge chip driver. +config DRM_OF_DISPLAY_MODE_BRIDGE + tristate + depends on DRM_BRIDGE && OF + help + This is a DRM bridge implementation that uses of_get_drm_display_mode + to acquire display mode. + + It exists for compatibility with legacy display mode parsing, in order + to conform to the panel-bridge framework. + config DRM_PARADE_PS8622 tristate "Parade eDP/LVDS bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index beab5b695a6e..15cc821d85b7 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o obj-$(CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER) += microchip-lvds.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o +obj-$(CONFIG_DRM_OF_DISPLAY_MODE_BRIDGE) += of-display-mode-bridge.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o obj-$(CONFIG_DRM_SAMSUNG_DSIM) += samsung-dsim.o diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h index 8be7266fd4f4..12c95198d9a4 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511.h +++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h @@ -354,7 +354,6 @@ struct adv7511 { enum drm_connector_status status; bool powered; - struct drm_bridge *next_bridge; struct drm_display_mode curr_mode; unsigned int f_tmds; diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c index 6bd76c1fb007..02f8f7e78a16 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -768,8 +768,6 @@ static int adv7511_connector_init(struct adv7511 *adv) return PTR_ERR(connector); } - drm_connector_attach_encoder(connector, bridge->encoder); - return 0; } @@ -783,7 +781,7 @@ static const struct adv7511 *bridge_to_adv7511_const(const struct drm_bridge *br } static void adv7511_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adv7511 *adv = bridge_to_adv7511(bridge); struct drm_connector *connector; @@ -812,7 +810,7 @@ static void adv7511_bridge_atomic_enable(struct drm_bridge *bridge, } static void adv7511_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct adv7511 *adv = bridge_to_adv7511(bridge); @@ -851,8 +849,8 @@ static int adv7511_bridge_attach(struct drm_bridge *bridge, struct adv7511 *adv = bridge_to_adv7511(bridge); int ret = 0; - if (adv->next_bridge) { - ret = drm_bridge_attach(encoder, adv->next_bridge, bridge, + if (adv->bridge.next_bridge) { + ret = drm_bridge_attach(encoder, adv->bridge.next_bridge, bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret) return ret; @@ -1251,10 +1249,13 @@ static int adv7511_probe(struct i2c_client *i2c) memset(&link_config, 0, sizeof(link_config)); - ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1, NULL, - &adv7511->next_bridge); - if (ret && ret != -ENODEV) - return ret; + adv7511->bridge.next_bridge = of_drm_get_bridge_by_endpoint(dev->of_node, 1, -1); + if (IS_ERR(adv7511->bridge.next_bridge)) { + if (PTR_ERR(adv7511->bridge.next_bridge) == -ENODEV) + adv7511->bridge.next_bridge = NULL; + else + return PTR_ERR(adv7511->bridge.next_bridge); + } if (adv7511->info->link_config) ret = adv7511_parse_dt(dev->of_node, &link_config); diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig index 03dc7ffe824a..57bb2daa5aaf 100644 --- a/drivers/gpu/drm/bridge/analogix/Kconfig +++ b/drivers/gpu/drm/bridge/analogix/Kconfig @@ -15,6 +15,7 @@ config DRM_ANALOGIX_ANX6345 config DRM_ANALOGIX_ANX78XX tristate "Analogix ANX78XX bridge" + depends on OF select DRM_ANALOGIX_DP select DRM_DISPLAY_DP_HELPER select DRM_DISPLAY_HELPER @@ -29,6 +30,8 @@ config DRM_ANALOGIX_ANX78XX config DRM_ANALOGIX_DP tristate depends on DRM + depends on OF + select DRM_DISPLAY_DP_AUX_BUS config DRM_ANALOGIX_ANX7625 tristate "Analogix Anx7625 MIPI to DP interface support" diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 8dee5f2fbde5..8cf6b73bceac 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -6,6 +6,7 @@ * Author: Jingoo Han */ +#include #include #include #include @@ -20,12 +21,14 @@ #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -747,9 +750,6 @@ static int analogix_dp_commit(struct analogix_dp_device *dp) { int ret; - /* Keep the panel disabled while we configure video */ - drm_panel_disable(dp->plat_data->panel); - ret = analogix_dp_train_link(dp); if (ret) { dev_err(dp->dev, "unable to do link train, ret=%d\n", ret); @@ -769,9 +769,6 @@ static int analogix_dp_commit(struct analogix_dp_device *dp) return ret; } - /* Safe to enable the panel now */ - drm_panel_enable(dp->plat_data->panel); - /* Check whether panel supports fast training */ ret = analogix_dp_fast_link_train_detection(dp); if (ret) @@ -856,79 +853,47 @@ static int analogix_dp_disable_psr(struct analogix_dp_device *dp) return analogix_dp_send_psr_spd(dp, &psr_vsc, true); } -static int analogix_dp_get_modes(struct drm_connector *connector) +static const struct drm_edid *analogix_dp_bridge_edid_read(struct drm_bridge *bridge, + struct drm_connector *connector) { - struct analogix_dp_device *dp = to_dp(connector); - const struct drm_edid *drm_edid; - int num_modes = 0; + struct analogix_dp_device *dp = to_dp(bridge); - if (dp->plat_data->panel) { - num_modes += drm_panel_get_modes(dp->plat_data->panel, connector); - } else { - drm_edid = drm_edid_read_ddc(connector, &dp->aux.ddc); + return drm_edid_read_ddc(connector, &dp->aux.ddc); +} - drm_edid_connector_update(&dp->connector, drm_edid); +static int analogix_dp_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct analogix_dp_device *dp = to_dp(bridge); + struct drm_display_info *di = &conn_state->connector->display_info; + u32 mask = BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444) | BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422); - if (drm_edid) { - num_modes += drm_edid_connector_add_modes(&dp->connector); - drm_edid_free(drm_edid); + if (is_rockchip(dp->plat_data->dev_type)) { + if ((di->color_formats & mask)) { + DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n"); + di->color_formats &= ~mask; + di->color_formats |= BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444); + di->bpc = 8; } } - if (dp->plat_data->get_modes) - num_modes += dp->plat_data->get_modes(dp->plat_data, connector); - - return num_modes; -} - -static struct drm_encoder * -analogix_dp_best_encoder(struct drm_connector *connector) -{ - struct analogix_dp_device *dp = to_dp(connector); - - return dp->encoder; -} - - -static int analogix_dp_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) -{ - struct analogix_dp_device *dp = to_dp(connector); - struct drm_connector_state *conn_state; - struct drm_crtc_state *crtc_state; - - conn_state = drm_atomic_get_new_connector_state(state, connector); - if (WARN_ON(!conn_state)) - return -ENODEV; - conn_state->self_refresh_aware = true; - if (!conn_state->crtc) - return 0; - - crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); - if (!crtc_state) - return 0; - if (crtc_state->self_refresh_active && !dp->psr_supported) return -EINVAL; return 0; } -static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = { - .get_modes = analogix_dp_get_modes, - .best_encoder = analogix_dp_best_encoder, - .atomic_check = analogix_dp_atomic_check, -}; - static enum drm_connector_status -analogix_dp_detect(struct drm_connector *connector, bool force) +analogix_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) { - struct analogix_dp_device *dp = to_dp(connector); + struct analogix_dp_device *dp = to_dp(bridge); enum drm_connector_status status = connector_status_disconnected; - if (dp->plat_data->panel) + if (dp->plat_data->next_bridge) return connector_status_connected; if (!analogix_dp_detect_hpd(dp)) @@ -937,55 +902,23 @@ analogix_dp_detect(struct drm_connector *connector, bool force) return status; } -static const struct drm_connector_funcs analogix_dp_connector_funcs = { - .fill_modes = drm_helper_probe_single_connector_modes, - .detect = analogix_dp_detect, - .destroy = drm_connector_cleanup, - .reset = drm_atomic_helper_connector_reset, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - static int analogix_dp_bridge_attach(struct drm_bridge *bridge, struct drm_encoder *encoder, enum drm_bridge_attach_flags flags) { struct analogix_dp_device *dp = to_dp(bridge); - struct drm_connector *connector = NULL; int ret = 0; - if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { - DRM_ERROR("Fix bridge driver to make connector optional!"); + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_ERROR("Unsupported connector creation\n"); return -EINVAL; } - if (!dp->plat_data->skip_connector) { - connector = &dp->connector; - connector->polled = DRM_CONNECTOR_POLL_HPD; - - ret = drm_connector_init(dp->drm_dev, connector, - &analogix_dp_connector_funcs, - DRM_MODE_CONNECTOR_eDP); + if (dp->plat_data->next_bridge) { + ret = drm_bridge_attach(dp->encoder, dp->plat_data->next_bridge, bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret) { - DRM_ERROR("Failed to initialize connector with drm\n"); - return ret; - } - - drm_connector_helper_add(connector, - &analogix_dp_connector_helper_funcs); - drm_connector_attach_encoder(connector, encoder); - } - - /* - * NOTE: the connector registration is implemented in analogix - * platform driver, that to say connector would be exist after - * plat_data->attch return, that's why we record the connector - * point after plat attached. - */ - if (dp->plat_data->attach) { - ret = dp->plat_data->attach(dp->plat_data, bridge, connector); - if (ret) { - DRM_ERROR("Failed at platform attach func\n"); + dev_err(dp->dev, "failed to attach following panel or bridge (%d)\n", ret); return ret; } } @@ -995,7 +928,7 @@ static int analogix_dp_bridge_attach(struct drm_bridge *bridge, static struct drm_crtc *analogix_dp_get_old_crtc(struct analogix_dp_device *dp, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_encoder *encoder = dp->encoder; struct drm_connector *connector; @@ -1014,7 +947,7 @@ struct drm_crtc *analogix_dp_get_old_crtc(struct analogix_dp_device *dp, static struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct drm_encoder *encoder = dp->encoder; struct drm_connector *connector; @@ -1032,7 +965,7 @@ struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp, } static void analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct analogix_dp_device *dp = to_dp(bridge); struct drm_crtc *crtc; @@ -1046,8 +979,6 @@ static void analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge, /* Don't touch the panel if we're coming back from PSR */ if (old_crtc_state && old_crtc_state->self_refresh_active) return; - - drm_panel_prepare(dp->plat_data->panel); } static int analogix_dp_set_bridge(struct analogix_dp_device *dp) @@ -1087,14 +1018,21 @@ static int analogix_dp_set_bridge(struct analogix_dp_device *dp) } static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, + struct drm_atomic_commit *state, const struct drm_display_mode *mode) { struct analogix_dp_device *dp = to_dp(bridge); - struct drm_display_info *display_info = &dp->connector.display_info; struct video_info *video = &dp->video_info; struct device_node *dp_node = dp->dev->of_node; + struct drm_connector *connector; + struct drm_display_info *display_info; int vic; + connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); + if (!connector) + return; + display_info = &connector->display_info; + /* Input video interlaces & hsync pol & vsync pol */ video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); @@ -1163,7 +1101,7 @@ static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, } static void analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct analogix_dp_device *dp = to_dp(bridge); struct drm_crtc *crtc; @@ -1178,7 +1116,7 @@ static void analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge, new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc); if (!new_crtc_state) return; - analogix_dp_bridge_mode_set(bridge, &new_crtc_state->adjusted_mode); + analogix_dp_bridge_mode_set(bridge, old_state, &new_crtc_state->adjusted_mode); old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc); /* Not a full enable, just disable PSR and continue */ @@ -1212,23 +1150,19 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge) if (dp->dpms_mode != DRM_MODE_DPMS_ON) return; - drm_panel_disable(dp->plat_data->panel); - disable_irq(dp->irq); analogix_dp_set_analog_power_down(dp, POWER_ALL, 1); pm_runtime_put_sync(dp->dev); - drm_panel_unprepare(dp->plat_data->panel); - dp->fast_train_enable = false; dp->psr_supported = false; dp->dpms_mode = DRM_MODE_DPMS_OFF; } static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct analogix_dp_device *dp = to_dp(bridge); struct drm_crtc *old_crtc, *new_crtc; @@ -1266,7 +1200,7 @@ static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge, } static void analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *old_state) + struct drm_atomic_commit *old_state) { struct analogix_dp_device *dp = to_dp(bridge); struct drm_crtc *crtc; @@ -1294,7 +1228,10 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = { .atomic_enable = analogix_dp_bridge_atomic_enable, .atomic_disable = analogix_dp_bridge_atomic_disable, .atomic_post_disable = analogix_dp_bridge_atomic_post_disable, + .atomic_check = analogix_dp_bridge_atomic_check, .attach = analogix_dp_bridge_attach, + .edid_read = analogix_dp_bridge_edid_read, + .detect = analogix_dp_bridge_detect, }; static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp) @@ -1524,6 +1461,7 @@ EXPORT_SYMBOL_GPL(analogix_dp_resume); int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev) { + struct drm_bridge *bridge = &dp->bridge; int ret; dp->drm_dev = drm_dev; @@ -1537,7 +1475,23 @@ int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev) return ret; } - ret = drm_bridge_attach(dp->encoder, &dp->bridge, NULL, 0); + bridge->ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; + bridge->of_node = dp->dev->of_node; + bridge->type = DRM_MODE_CONNECTOR_eDP; + ret = devm_drm_bridge_add(dp->dev, &dp->bridge); + if (ret) + goto err_unregister_aux; + + if (dp->plat_data->panel) { + dp->plat_data->next_bridge = devm_drm_panel_bridge_add(dp->dev, + dp->plat_data->panel); + if (IS_ERR(dp->plat_data->next_bridge)) { + ret = PTR_ERR(dp->plat_data->next_bridge); + goto err_unregister_aux; + } + } + + ret = drm_bridge_attach(dp->encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret) { DRM_ERROR("failed to create bridge (%d)\n", ret); goto err_unregister_aux; @@ -1554,18 +1508,15 @@ EXPORT_SYMBOL_GPL(analogix_dp_bind); void analogix_dp_unbind(struct analogix_dp_device *dp) { - analogix_dp_bridge_disable(&dp->bridge); - dp->connector.funcs->destroy(&dp->connector); - - drm_panel_unprepare(dp->plat_data->panel); - drm_dp_aux_unregister(&dp->aux); } EXPORT_SYMBOL_GPL(analogix_dp_unbind); int analogix_dp_start_crc(struct drm_connector *connector) { - struct analogix_dp_device *dp = to_dp(connector); + struct analogix_dp_device *dp; + struct drm_bridge *bridge __free(drm_bridge_put) = + drm_bridge_chain_get_first_bridge(connector->encoder); if (!connector->state->crtc) { DRM_ERROR("Connector %s doesn't currently have a CRTC.\n", @@ -1573,13 +1524,25 @@ int analogix_dp_start_crc(struct drm_connector *connector) return -EINVAL; } + if (!bridge || bridge->type != DRM_MODE_CONNECTOR_eDP) + return -EINVAL; + + dp = to_dp(bridge); + return drm_dp_start_crc(&dp->aux, connector->state->crtc); } EXPORT_SYMBOL_GPL(analogix_dp_start_crc); int analogix_dp_stop_crc(struct drm_connector *connector) { - struct analogix_dp_device *dp = to_dp(connector); + struct analogix_dp_device *dp; + struct drm_bridge *bridge __free(drm_bridge_put) = + drm_bridge_chain_get_first_bridge(connector->encoder); + + if (!bridge || bridge->type != DRM_MODE_CONNECTOR_eDP) + return -EINVAL; + + dp = to_dp(bridge); return drm_dp_stop_crc(&dp->aux); } @@ -1599,6 +1562,50 @@ struct drm_dp_aux *analogix_dp_get_aux(struct analogix_dp_device *dp) } EXPORT_SYMBOL_GPL(analogix_dp_get_aux); +static int analogix_dp_aux_done_probing(struct drm_dp_aux *aux) +{ + struct analogix_dp_device *dp = to_dp(aux); + struct analogix_dp_plat_data *plat_data = dp->plat_data; + int port = plat_data->dev_type == EXYNOS_DP ? 0 : 1; + int ret; + + /* + * If drm_of_find_panel_or_bridge() returns -ENODEV, there may be no valid panel + * or bridge nodes. The driver should go on for the driver-free bridge or the DP + * mode applications. + */ + ret = drm_of_find_panel_or_bridge(dp->dev->of_node, port, 0, + &plat_data->panel, &plat_data->next_bridge); + if (ret && ret != -ENODEV) + return ret; + + return component_add(dp->dev, plat_data->ops); +} + +int analogix_dp_finish_probe(struct analogix_dp_device *dp) +{ + int ret; + + ret = devm_of_dp_aux_populate_bus(&dp->aux, analogix_dp_aux_done_probing); + if (ret) { + /* + * If devm_of_dp_aux_populate_bus() returns -ENODEV, the done_probing() will + * not be called because there are no EP devices. Then the callback function + * analogix_dp_aux_done_probing() will be called directly in order to support + * the other valid DT configurations. + * + * NOTE: The devm_of_dp_aux_populate_bus() is allowed to return -EPROBE_DEFER. + */ + if (ret != -ENODEV) + return dev_err_probe(dp->dev, ret, "failed to populate aux bus\n"); + + return analogix_dp_aux_done_probing(&dp->aux); + } + + return 0; +} +EXPORT_SYMBOL_GPL(analogix_dp_finish_probe); + MODULE_AUTHOR("Jingoo Han "); MODULE_DESCRIPTION("Analogix DP Core Driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h index 91b215c6a0cf..17347448c6b0 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -154,7 +154,6 @@ struct analogix_dp_device { struct drm_encoder *encoder; struct device *dev; struct drm_device *drm_dev; - struct drm_connector connector; struct drm_bridge bridge; struct drm_dp_aux aux; struct clk *clock; diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 54b02242d6db..513c11cdbc74 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -2559,7 +2559,7 @@ static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, } static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct anx7625_data *ctx = bridge_to_anx7625(bridge); struct device *dev = ctx->dev; @@ -2598,7 +2598,7 @@ static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, } static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct anx7625_data *ctx = bridge_to_anx7625(bridge); struct device *dev = ctx->dev; diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c index 0dd85e26248c..cf90d4468b5c 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -591,7 +591,7 @@ cdns_dsi_bridge_mode_valid(struct drm_bridge *bridge, } static void cdns_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge); struct cdns_dsi *dsi = input_to_dsi(input); @@ -701,7 +701,7 @@ static void cdns_dsi_init_link(struct cdns_dsi *dsi) } static void cdns_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge); struct cdns_dsi *dsi = input_to_dsi(input); @@ -1230,7 +1230,7 @@ static const struct mipi_dsi_host_ops cdns_dsi_ops = { .transfer = cdns_dsi_transfer, }; -static int __maybe_unused cdns_dsi_resume(struct device *dev) +static int cdns_dsi_resume(struct device *dev) { struct cdns_dsi *dsi = dev_get_drvdata(dev); @@ -1241,7 +1241,7 @@ static int __maybe_unused cdns_dsi_resume(struct device *dev) return 0; } -static int __maybe_unused cdns_dsi_suspend(struct device *dev) +static int cdns_dsi_suspend(struct device *dev) { struct cdns_dsi *dsi = dev_get_drvdata(dev); @@ -1251,8 +1251,9 @@ static int __maybe_unused cdns_dsi_suspend(struct device *dev) return 0; } -static UNIVERSAL_DEV_PM_OPS(cdns_dsi_pm_ops, cdns_dsi_suspend, cdns_dsi_resume, - NULL); +static const struct dev_pm_ops cdns_dsi_pm_ops = { + RUNTIME_PM_OPS(cdns_dsi_suspend, cdns_dsi_resume, NULL) +}; static int cdns_dsi_drm_probe(struct platform_device *pdev) { @@ -1399,7 +1400,7 @@ static struct platform_driver cdns_dsi_platform_driver = { .driver = { .name = "cdns-dsi", .of_match_table = cdns_dsi_of_match, - .pm = &cdns_dsi_pm_ops, + .pm = pm_ptr(&cdns_dsi_pm_ops), }, }; module_platform_driver(cdns_dsi_platform_driver); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c index 064c6915c896..36c07b71fe04 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c @@ -1750,7 +1750,7 @@ static void cdns_mhdp_sst_enable(struct cdns_mhdp_device *mhdp, } static void cdns_mhdp_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge); struct cdns_mhdp_bridge_state *mhdp_state; @@ -1841,7 +1841,7 @@ static void cdns_mhdp_atomic_enable(struct drm_bridge *bridge, } static void cdns_mhdp_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge); u32 resp; @@ -1963,7 +1963,7 @@ static int cdns_mhdp_atomic_check(struct drm_bridge *bridge, struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge); const struct drm_display_mode *mode = &crtc_state->adjusted_mode; struct drm_connector_state *old_state, *new_state; - struct drm_atomic_state *state = crtc_state->state; + struct drm_atomic_commit *state = crtc_state->state; struct drm_connector *conn = mhdp->connector; u64 old_cp, new_cp; diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c index 814713c5bea9..d8344e011818 100644 --- a/drivers/gpu/drm/bridge/chipone-icn6211.c +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c @@ -341,7 +341,7 @@ static void chipone_configure_pll(struct chipone *icn, } static void chipone_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct chipone *icn = bridge_to_chipone(bridge); struct drm_display_mode *mode = &icn->mode; @@ -444,7 +444,7 @@ static void chipone_atomic_enable(struct drm_bridge *bridge, } static void chipone_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct chipone *icn = bridge_to_chipone(bridge); int ret; @@ -481,7 +481,7 @@ static void chipone_atomic_pre_enable(struct drm_bridge *bridge, } static void chipone_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct chipone *icn = bridge_to_chipone(bridge); @@ -730,13 +730,11 @@ static int chipone_dsi_probe(struct mipi_dsi_device *dsi) mipi_dsi_set_drvdata(dsi, icn); - drm_bridge_add(&icn->bridge); - - ret = chipone_dsi_attach(icn); + ret = devm_drm_bridge_add(dev, &icn->bridge); if (ret) - drm_bridge_remove(&icn->bridge); + return ret; - return ret; + return chipone_dsi_attach(icn); } static int chipone_i2c_probe(struct i2c_client *client) @@ -758,17 +756,16 @@ static int chipone_i2c_probe(struct i2c_client *client) dev_set_drvdata(dev, icn); i2c_set_clientdata(client, icn); - drm_bridge_add(&icn->bridge); + ret = devm_drm_bridge_add(dev, &icn->bridge); + if (ret) + return ret; return chipone_dsi_host_attach(icn); } static void chipone_dsi_remove(struct mipi_dsi_device *dsi) { - struct chipone *icn = mipi_dsi_get_drvdata(dsi); - mipi_dsi_detach(dsi); - drm_bridge_remove(&icn->bridge); } static const struct of_device_id chipone_of_match[] = { diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bridge/chrontel-ch7033.c index 54d49d4882c8..a237c65ebd69 100644 --- a/drivers/gpu/drm/bridge/chrontel-ch7033.c +++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c @@ -199,7 +199,6 @@ enum { struct ch7033_priv { struct regmap *regmap; - struct drm_bridge *next_bridge; struct drm_bridge bridge; struct drm_connector connector; }; @@ -215,7 +214,7 @@ static enum drm_connector_status ch7033_connector_detect( { struct ch7033_priv *priv = conn_to_ch7033_priv(connector); - return drm_bridge_detect(priv->next_bridge, connector); + return drm_bridge_detect(priv->bridge.next_bridge, connector); } static const struct drm_connector_funcs ch7033_connector_funcs = { @@ -233,7 +232,7 @@ static int ch7033_connector_get_modes(struct drm_connector *connector) const struct drm_edid *drm_edid; int ret; - drm_edid = drm_bridge_edid_read(priv->next_bridge, connector); + drm_edid = drm_bridge_edid_read(priv->bridge.next_bridge, connector); drm_edid_connector_update(connector, drm_edid); if (drm_edid) { ret = drm_edid_connector_add_modes(connector); @@ -275,7 +274,7 @@ static int ch7033_bridge_attach(struct drm_bridge *bridge, struct drm_connector *connector = &priv->connector; int ret; - ret = drm_bridge_attach(encoder, priv->next_bridge, bridge, + ret = drm_bridge_attach(encoder, priv->bridge.next_bridge, bridge, DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret) return ret; @@ -283,15 +282,15 @@ static int ch7033_bridge_attach(struct drm_bridge *bridge, if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) return 0; - if (priv->next_bridge->ops & DRM_BRIDGE_OP_DETECT) { + if (priv->bridge.next_bridge->ops & DRM_BRIDGE_OP_DETECT) { connector->polled = DRM_CONNECTOR_POLL_HPD; } else { connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; } - if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) { - drm_bridge_hpd_enable(priv->next_bridge, ch7033_hpd_event, + if (priv->bridge.next_bridge->ops & DRM_BRIDGE_OP_HPD) { + drm_bridge_hpd_enable(priv->bridge.next_bridge, ch7033_hpd_event, priv); } @@ -299,8 +298,8 @@ static int ch7033_bridge_attach(struct drm_bridge *bridge, &ch7033_connector_helper_funcs); ret = drm_connector_init_with_ddc(bridge->dev, &priv->connector, &ch7033_connector_funcs, - priv->next_bridge->type, - priv->next_bridge->ddc); + priv->bridge.next_bridge->type, + priv->bridge.next_bridge->ddc); if (ret) { DRM_ERROR("Failed to initialize connector\n"); return ret; @@ -313,8 +312,8 @@ static void ch7033_bridge_detach(struct drm_bridge *bridge) { struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge); - if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) - drm_bridge_hpd_disable(priv->next_bridge); + if (priv->bridge.next_bridge->ops & DRM_BRIDGE_OP_HPD) + drm_bridge_hpd_disable(priv->bridge.next_bridge); drm_connector_cleanup(&priv->connector); } @@ -543,10 +542,9 @@ static int ch7033_probe(struct i2c_client *client) dev_set_drvdata(dev, priv); - ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1, NULL, - &priv->next_bridge); - if (ret) - return ret; + priv->bridge.next_bridge = of_drm_get_bridge_by_endpoint(dev->of_node, 1, -1); + if (IS_ERR(priv->bridge.next_bridge)) + return PTR_ERR(priv->bridge.next_bridge); priv->regmap = devm_regmap_init_i2c(client, &ch7033_regmap_config); if (IS_ERR(priv->regmap)) { diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index 7b71cde173e0..9bfaa3f93370 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -124,7 +124,7 @@ static int fsl_ldb_attach(struct drm_bridge *bridge, } static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); const struct drm_bridge_state *bridge_state; @@ -228,7 +228,7 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, } static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_atomic_commit *state) { struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index b9028a5e5a06..005a745e5c47 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -3,21 +3,13 @@ if ARCH_MXC || COMPILE_TEST config DRM_IMX_LDB_HELPER tristate -config DRM_IMX_LEGACY_BRIDGE - tristate - depends on DRM_IMX - help - This is a DRM bridge implementation for the DRM i.MX IPUv3 driver, - that uses of_get_drm_display_mode to acquire display mode. - - Newer designs should not use this bridge and should use proper panel - driver instead. - config DRM_IMX8MP_DW_HDMI_BRIDGE tristate "Freescale i.MX8MP HDMI-TX bridge support" depends on OF depends on COMMON_CLK select DRM_DW_HDMI + select OF_OVERLAY + select DRM_DISPLAY_CONNECTOR imply DRM_IMX8MP_HDMI_PAI imply DRM_IMX8MP_HDMI_PVI imply PHY_FSL_SAMSUNG_HDMI_PHY @@ -25,6 +17,22 @@ config DRM_IMX8MP_DW_HDMI_BRIDGE Choose this to enable support for the internal HDMI encoder found on the i.MX8MP SoC. +config DRM_IMX8MP_DW_HDMI_BRIDGE_CONNECTOR_FIXUP + bool + default y + depends on DRM_IMX_LCDIF + depends on DRM_IMX8MP_DW_HDMI_BRIDGE + depends on OF + help + Modifies at early boot the live device tree of boards using the + i.MX8MP fsl,imx8mp-hdmi-tx adding a hdmi-connector node linked to + the hdmi-tx. This is needed to support bridge-connector usage in + the i.MX8MP LCDIF driver. + + You need this if you use the i.MX8MP HDMI output and your board + device tree file does not have an hdmi-connector node connected + to it. + config DRM_IMX8MP_HDMI_PAI tristate "Freescale i.MX8MP HDMI PAI bridge support" depends on OF diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index 8d01fda25451..94ac8c40ebe9 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_DRM_IMX_LDB_HELPER) += imx-ldb-helper.o -obj-$(CONFIG_DRM_IMX_LEGACY_BRIDGE) += imx-legacy-bridge.o obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE) += imx8mp-hdmi-tx.o +obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE_CONNECTOR_FIXUP) += imx8mp-hdmi-tx-connector-fixup.o \ + imx8mp-hdmi-tx-connector-fixup.dtbo.o obj-$(CONFIG_DRM_IMX8MP_HDMI_PAI) += imx8mp-hdmi-pai.o obj-$(CONFIG_DRM_IMX8MP_HDMI_PVI) += imx8mp-hdmi-pvi.o obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o diff --git a/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c b/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c deleted file mode 100644 index 0e31d5000e7c..000000000000 --- a/drivers/gpu/drm/bridge/imx/imx-legacy-bridge.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale i.MX drm driver - * - * bridge driver for legacy DT bindings, utilizing display-timings node - */ - -#include - -#include -#include -#include -#include - -#include