From dc3b7209b5d32194b9088fb40f1787130f34ea5e Mon Sep 17 00:00:00 2001 From: Jiaxing Hu Date: Fri, 31 Jul 2026 13:38:07 +1200 Subject: [PATCH] net: phy: motorcomm: enable the reference clock for YT8521 Commit 42310a24389c ("net: phy: motorcomm: Enable optional clock for YT8531") enables the SoC-provided reference clock for the YT8531 in its probe. The YT8521 has the same need on crystal-less boards but goes through yt8521_probe(), so enable it there too. The clock is optional, so crystal-clocked boards are unaffected. Reviewed-by: Andrew Lunn Tested-by: Gavin Gao Signed-off-by: Jiaxing Hu Link: https://patch.msgid.link/20260731013807.1488843-1-gahing@gahingwoo.com Signed-off-by: Jakub Kicinski --- drivers/net/phy/motorcomm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 3396a38cfc0f..c5a2cda8d31b 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -1065,6 +1065,7 @@ static int yt8521_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; struct yt8521_priv *priv; + struct clk *clk; int chip_config; u16 mask, val; u32 freq; @@ -1076,6 +1077,11 @@ static int yt8521_probe(struct phy_device *phydev) phydev->priv = priv; + clk = devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "failed to get and enable PHY clock\n"); + chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); if (chip_config < 0) return chip_config;