diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
index 2dfe6913ab4f..97608603ea62 100644
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
@@ -1198,6 +1198,1027 @@ to upconvert to 32b float internally?
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@@ -1584,7 +2605,7 @@ to upconvert to 32b float internally?
-
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+ Disable LRZ feedback writes
-
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+ Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have
+ GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass.
+ In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered.
+
+
@@ -2270,7 +3306,7 @@ to upconvert to 32b float internally?
- 0.0 if GREATER
- 1.0 if LESS
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@@ -2284,7 +3320,7 @@ to upconvert to 32b float internally?
Disable LRZ based on previous direction and the current one.
If DIR_WRITE is not enabled - there is no write to direction buffer.
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@@ -2357,7 +3393,10 @@ to upconvert to 32b float internally?
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@@ -2366,7 +3405,10 @@ to upconvert to 32b float internally?
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@@ -2440,7 +3482,7 @@ to upconvert to 32b float internally?
-
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@@ -2448,7 +3490,7 @@ to upconvert to 32b float internally?
-
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@@ -2605,6 +3647,7 @@ to upconvert to 32b float internally?
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@@ -2903,11 +3946,21 @@ to upconvert to 32b float internally?
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-
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@@ -2927,7 +3980,10 @@ to upconvert to 32b float internally?
-
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@@ -4275,7 +5331,7 @@ to upconvert to 32b float internally?
badly named or the functionality moved in a6xx. But downstream kernel
calls this "a6xx_sp_ps_tp_2d_cluster"
-->
-
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@@ -4286,7 +5342,7 @@ to upconvert to 32b float internally?
-
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@@ -4329,7 +5385,12 @@ to upconvert to 32b float internally?
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@@ -4351,7 +5412,8 @@ to upconvert to 32b float internally?
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@@ -4582,15 +5644,15 @@ to upconvert to 32b float internally?
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@@ -4623,6 +5685,19 @@ to upconvert to 32b float internally?
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This register clears pending loads queued up by
@@ -4791,7 +5866,7 @@ to upconvert to 32b float internally?
-
+
Texture constant dwords
@@ -4831,6 +5906,7 @@ to upconvert to 32b float internally?
+