From 324dd7a6ac27b388e605ef136f23c88a5e49edbe Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 27 Jun 2017 01:48:38 -0700 Subject: [PATCH 1/5] ARM: OMAP2+: Fix omap3 prm shared irq Shared interrupts with IRQ_NOAUTOEN got a warning added with commit 04c848d39879 ("genirq: Warn when IRQ_NOAUTOEN is used with shared interrupts"). Let's just drop the IRQ_NOAUTOEN use for omap3 PRM shared interrupt as it does not seem to cause any other issues based on my testing. We have moved a lot of the code to initialize later, and whatever problems the legacy booting had seem to be gone now with pinctrl driver and device tree based booting. Otherwise we will get: WARNING: CPU: 0 PID: 1 at kernel/irq/manage.c:1348 __setup_irq+0x5d0/0x64c [] (__setup_irq) from [] (request_threaded_irq+0xdc/0x188) [] (request_threaded_irq) from [] (pcs_probe+0x6ec/0x8a4) [] (pcs_probe) from [] (platform_drv_probe+0x50/0xb0) [] (platform_drv_probe) from [] (driver_probe_device+0x33c/0x478) Note that we also need to remove the related enable_irq() to avoid getting the following: WARNING: CPU: 0 PID: 1 at kernel/irq/manage.c:529 enable_irq+0x34/0x70 [] (enable_irq) from [] (omap3_pm_init+0x118/0x3f8) [] (omap3_pm_init) from [] (am35xx_init_late+0x10/0x18) Cc: Kevin Hilman Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm34xx.c | 1 - arch/arm/mach-omap2/prm3xxx.c | 7 +------ 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index d44e0e2f1106..841ba19d64a6 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -486,7 +486,6 @@ int __init omap3_pm_init(void) ret = request_irq(omap_prcm_event_to_irq("io"), _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", omap3_pm_init); - enable_irq(omap_prcm_event_to_irq("io")); if (ret) { pr_err("pm: Failed to request pm_io irq\n"); diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 382e236fbfd9..64f6451499a7 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -692,7 +692,6 @@ static int omap3xxx_prm_late_init(void) { struct device_node *np; int irq_num; - int ret; if (!(prm_features & PRM_HAS_IO_WAKEUP)) return 0; @@ -712,12 +711,8 @@ static int omap3xxx_prm_late_init(void) } omap3xxx_prm_enable_io_wakeup(); - ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); - if (!ret) - irq_set_status_flags(omap_prcm_event_to_irq("io"), - IRQ_NOAUTOEN); - return ret; + return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); } static void __exit omap3xxx_prm_exit(void) From c5b3955828baa4d7ae44ec075529d66fa7bdf903 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 30 Jun 2017 03:37:03 -0700 Subject: [PATCH 2/5] ARM: OMAP4: Fix legacy code clean-up regression Commit 2a26d31b1bae ("ARM: OMAP2+: Remove unused legacy code for PRM") removed PRM platform init code that I thought is unused. Turns out omap4 still needs this code, so let's do a partial revert to add it back. I probably missed this earlier as the comments used to say "OMAP4+ is DT only now" for !of_have_populated_dt() to exit early and missed the negative test. Let's not add those lines back as they are confusing and no longer needed as we only boot in device tree mode. Without things things can mysterious fail for i2c, for example LM75 I2C temperature sensor can stop working as the PRM interrupts won't work. Fixes: 2a26d31b1bae ("ARM: OMAP2+: Remove unused legacy code for PRM") Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/prm44xx.c | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 87e86a4a9ead..3ab5df1ce900 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -336,6 +336,27 @@ static void omap44xx_prm_reconfigure_io_chain(void) return; } +/** + * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches + * + * Activates the I/O wakeup event latches and allows events logged by + * those latches to signal a wakeup event to the PRCM. For I/O wakeups + * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and + * omap44xx_prm_reconfigure_io_chain() must be called. No return value. + */ +static void __init omap44xx_prm_enable_io_wakeup(void) +{ + s32 inst = omap4_prmst_get_prm_dev_inst(); + + if (inst == PRM_INSTANCE_UNKNOWN) + return; + + omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, + OMAP4430_GLOBAL_WUEN_MASK, + inst, + omap4_prcm_irq_setup.pm_ctrl); +} + /** * omap44xx_prm_read_reset_sources - return the last SoC reset source * @@ -668,6 +689,8 @@ struct pwrdm_ops omap4_pwrdm_operations = { .pwrdm_has_voltdm = omap4_check_vcvp, }; +static int omap44xx_prm_late_init(void); + /* * XXX document */ @@ -675,6 +698,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = { .read_reset_sources = &omap44xx_prm_read_reset_sources, .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old, .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old, + .late_init = &omap44xx_prm_late_init, .assert_hardreset = omap4_prminst_assert_hardreset, .deassert_hardreset = omap4_prminst_deassert_hardreset, .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted, @@ -711,6 +735,37 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data) return prm_register(&omap44xx_prm_ll_data); } +static int omap44xx_prm_late_init(void) +{ + int irq_num; + + if (!(prm_features & PRM_HAS_IO_WAKEUP)) + return 0; + + irq_num = of_irq_get(prm_init_data->np, 0); + /* + * Already have OMAP4 IRQ num. For all other platforms, we need + * IRQ numbers from DT + */ + if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) { + if (irq_num == -EPROBE_DEFER) + return irq_num; + + /* Have nothing to do */ + return 0; + } + + /* Once OMAP4 DT is filled as well */ + if (irq_num >= 0) { + omap4_prcm_irq_setup.irq = irq_num; + omap4_prcm_irq_setup.xlate_irq = NULL; + } + + omap44xx_prm_enable_io_wakeup(); + + return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); +} + static void __exit omap44xx_prm_exit(void) { prm_unregister(&omap44xx_prm_ll_data); From 0c88e963a3090099725a5edd3b65afb4c9cf7858 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Jul 2017 00:54:36 -0700 Subject: [PATCH 3/5] ARM: dts: dm816x: Correct NAND support nodes The ELM node in dm816x.dtsi needs to declare the correct compatible value here as per the binding only one value is correct, and the current driver handles it correctly. We then add pinmux information for the NAND found on the EVM so that we do not rely on the ROM to do this for us, and also so that we do not try and probe NAND before we probe the ELM. Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: Roger Quadros Cc: Tony Lindgren Cc: Mihail Grigorov Signed-off-by: Tom Rini Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm8168-evm.dts | 32 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/dm816x.dtsi | 2 +- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index 1865976db5f9..996eba0c2e7a 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -68,6 +68,34 @@ usb1_pins: pinmux_usb1_pins { DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ >; }; + + nandflash_pins: nandflash_pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/ + DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */ + DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */ + DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */ + DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */ + DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */ + DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */ + DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */ + DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */ + DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */ + DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */ + DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */ + DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */ + DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */ + DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */ + DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */ + DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */ + DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */ + DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */ + DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */ + DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */ + DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */ + DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */ + >; + }; }; &i2c1 { @@ -90,6 +118,8 @@ extgpio1: pcf8575@20 { &gpmc { ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; nand@0,0 { compatible = "ti,omap2-nand"; @@ -98,9 +128,11 @@ nand@0,0 { interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; nand-bus-width = <16>; gpmc,device-width = <2>; gpmc,sync-clk-ps = <0>; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 59cbf958fcc3..566b2a8c8b96 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -145,7 +145,7 @@ edma: edma@49000000 { }; elm: elm@48080000 { - compatible = "ti,816-elm"; + compatible = "ti,am3352-elm"; ti,hwmods = "elm"; reg = <0x48080000 0x2000>; interrupts = <4>; From 5601ca471f0892acc36e0316844fa6bd774bfc7e Mon Sep 17 00:00:00 2001 From: Mihail Grigorov Date: Wed, 5 Jul 2017 00:54:45 -0700 Subject: [PATCH 4/5] ARM: dts: dm816x: Correct the state of the write protect pin Commit 599c376c4932 ("ARM: dts: Fix gpio interrupts for dm816x") corrected some problems with the MMC. However, it gets the write protect pin backwards. It needs to be ACTIVE_HIGH not ACTIVE_LOW. Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: Tony Lindgren Signed-off-by: Mihail Grigorov Signed-off-by: Tom Rini Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm8168-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index 996eba0c2e7a..c72a2132aa82 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -196,7 +196,7 @@ &mmc1 { vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; }; /* At least dm8168-evm rev c won't support multipoint, later may */ From ff570a01b1bd15cf8a87c9ea774fc9c52ea07f15 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 5 Jul 2017 00:54:52 -0700 Subject: [PATCH 5/5] ARM: dts: dra71-evm: mdio: Fix impedance values v1 series[1] for dp83867 phy impedance-control support, specifies to use ti,impedance-control with a value. These properties got updated iduring review to specify whether min or max impedance. But the DT still uses the old values which never takes effect. Update the DT node by using the proper DT properties. [1] https://patchwork.kernel.org/patch/9239729/ Fixes: 9868bc585ae2c ("ARM: dts: Add support for dra718-evm") Signed-off-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra71-evm.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index 4d57a55473af..a6298eb56978 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -190,7 +190,7 @@ dp83867_0: ethernet-phy@2 { ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; - ti,impedance-control = <0x1f>; + ti,min-output-impedance; }; dp83867_1: ethernet-phy@3 { @@ -198,7 +198,7 @@ dp83867_1: ethernet-phy@3 { ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; - ti,impedance-control = <0x1f>; + ti,min-output-impedance; }; };