From 1fb7a9fb6295220eb96c490581316b35fce180fe Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 10 May 2022 12:06:52 +0100 Subject: [PATCH 01/19] clk: renesas: r9a07g044: Add GPT clock and reset entry Add GPT clock and reset entry to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220510110653.7326-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index b288897852c7..cd2777abd957 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -182,7 +182,7 @@ static const struct { }; static const struct { - struct rzg2l_mod_clk common[71]; + struct rzg2l_mod_clk common[72]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif @@ -204,6 +204,8 @@ static const struct { 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, 0x534, 2), + DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, + 0x540, 0), DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, 0x548, 0), DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, @@ -346,6 +348,7 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), + DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0), DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2), From b6ee0bbf388ab38384f92339aa9a1df15e716cfe Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 10 May 2022 12:06:53 +0100 Subject: [PATCH 02/19] clk: renesas: r9a07g044: Add POEG clock and reset entries Add POEG clock and reset entries to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220510110653.7326-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index cd2777abd957..fd7c4eecd398 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -182,7 +182,7 @@ static const struct { }; static const struct { - struct rzg2l_mod_clk common[72]; + struct rzg2l_mod_clk common[76]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif @@ -206,6 +206,14 @@ static const struct { 0x534, 2), DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, 0x540, 0), + DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0, + 0x544, 0), + DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0, + 0x544, 1), + DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0, + 0x544, 2), + DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0, + 0x544, 3), DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, 0x548, 0), DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, @@ -349,6 +357,10 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0), + DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0), + DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1), + DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2), + DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3), DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2), From e55c4481e71de79d0ef566a238332bd346cef6de Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 18 May 2022 14:52:08 +0100 Subject: [PATCH 03/19] clk: renesas: r9a09g011: Add PFC clock and reset entries Add PFC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220518135208.39885-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g011-cpg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index 40693bb85b80..b01d79a73dd8 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -126,6 +126,7 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { }; static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { + DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2), DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), @@ -137,6 +138,7 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { }; static const struct rzg2l_reset r9a09g011_resets[] = { + DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), }; From efded37b426f4e1b7b004b1e9924ff4bf16ec0fd Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 18 May 2022 16:01:05 +0100 Subject: [PATCH 04/19] clk: renesas: r9a09g011: Add WDT clock and reset entries Add WDT0 clock and reset entries to CPG driver. Signed-off-by: Phil Edworthy Link: https://lore.kernel.org/r/20220518150105.48167-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g011-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index b01d79a73dd8..b21915cf6648 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -132,6 +132,8 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), + DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12), + DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13), DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), @@ -141,6 +143,7 @@ static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), + DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19), }; static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { From f46efcc4746f5c1a539df9db625c04321f75e494 Mon Sep 17 00:00:00 2001 From: Ralph Siemsen Date: Wed, 18 May 2022 13:27:16 -0400 Subject: [PATCH 05/19] clk: renesas: r9a06g032: Drop some unused fields Remove unused fields from struct r9a06g032_clkdesc. As the D_UGATE macro no longer uses _gi, drop it from all declarations. Signed-off-by: Ralph Siemsen Reviewed-by: Phil Edworthy Link: https://lore.kernel.org/r/20220518172808.1691450-2-ralph.siemsen@linaro.org Link: https://lore.kernel.org/r/20220518172808.1691450-3-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a06g032-clocks.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 35ffc462af1a..88865bb8bf94 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -51,11 +51,9 @@ struct r9a06g032_clkdesc { struct { u16 div, mul; }; - unsigned int factor; - unsigned int frequency; /* for dual gate */ struct { - uint16_t group : 1, index: 3; + uint16_t group : 1; u16 sel, g1, r1, g2, r2; } dual; }; @@ -85,10 +83,10 @@ struct r9a06g032_clkdesc { .source = 1 + R9A06G032_##_src, .name = _n, \ .reg = _reg, .div_min = _min, .div_max = _max, \ .div_table = { __VA_ARGS__ } } -#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \ +#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \ { .type = K_DUALGATE, .index = R9A06G032_##_idx, \ .source = 1 + R9A06G032_##_src, .name = _n, \ - .dual = { .group = _g, .index = _gi, \ + .dual = { .group = _g, \ .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, } enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE }; @@ -303,14 +301,14 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .dual.sel = ((0x34 / 4) << 5) | 30, .dual.group = 1, }, - D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), - D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9), - D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd), - D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763), - D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767), - D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b), - D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f), - D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773), + D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), + D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9), + D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd), + D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763), + D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767), + D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b), + D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f), + D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773), }; struct r9a06g032_priv { From 2dee50ab9e72a3cae75b65e5934c8dd3e9bf01bc Mon Sep 17 00:00:00 2001 From: Ralph Siemsen Date: Wed, 18 May 2022 14:25:27 -0400 Subject: [PATCH 06/19] clk: renesas: r9a06g032: Fix UART clkgrp bitsel There are two UART clock groups, each having a mux to select its upstream clock source. The register/bit definitions for accessing these two muxes appear to have been reversed since introduction. Correct them so as to match the hardware manual. Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Ralph Siemsen Reviewed-by: Phil Edworthy Link: https://lore.kernel.org/r/20220518182527.1693156-1-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a06g032-clocks.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 88865bb8bf94..1488c9d6e639 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -288,8 +288,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .name = "uart_group_012", .type = K_BITSEL, .source = 1 + R9A06G032_DIV_UART, - /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ - .dual.sel = ((0xec / 4) << 5) | 24, + /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ + .dual.sel = ((0x34 / 4) << 5) | 30, .dual.group = 0, }, { @@ -297,8 +297,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .name = "uart_group_34567", .type = K_BITSEL, .source = 1 + R9A06G032_DIV_P2_PG, - /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ - .dual.sel = ((0x34 / 4) << 5) | 30, + /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ + .dual.sel = ((0xec / 4) << 5) | 24, .dual.group = 1, }, D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), From 02c96ed9e4cd1f47bfcd10296fec6b0b69d6b3c6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 31 May 2022 08:16:57 +0100 Subject: [PATCH 07/19] clk: renesas: rzg2l: Fix reset status function As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means reset signal is not applied (deassert state) and 1 means reset signal is applied (assert state). reset_control_status() expects a positive value if the reset line is asserted. But rzg2l_cpg_status function returns zero for asserted state. This patch fixes the issue by adding double inverted logic, so that reset_control_status returns a positive value if the reset line is asserted. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220531071657.104121-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rzg2l-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index e2999ab2b53c..3ff6ecd61756 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1180,7 +1180,7 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, s8 monbit = info->resets[id].monbit; if (info->has_clk_mon_regs) { - return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask); + return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask); } else if (monbit >= 0) { u32 monbitmask = BIT(monbit); From 61a6737fcad8810258bdf1329f063b58ac27b230 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 25 May 2022 17:11:30 +0200 Subject: [PATCH 08/19] clk: renesas: r8a779f0: Add thermal clock Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220525151130.24103-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index c17ebe6b5992..0aec5e8ffd96 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -132,6 +132,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), DEF_MOD("wdt", 907, R8A779F0_CLK_R), DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M), + DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M), DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC), }; From 75fe45a000a70ea35e2071eb7f8b873648590982 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sat, 4 Jun 2022 01:34:37 +0200 Subject: [PATCH 09/19] clk: renesas: r8a779f0: Add SDHI0 clock Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220603233437.21819-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 0aec5e8ffd96..e6f41b9f765a 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -128,6 +128,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), + DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0), DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), DEF_MOD("wdt", 907, R8A779F0_CLK_R), From 65d012e415bb3592cd1c492195ff19088166198b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:10 +0200 Subject: [PATCH 10/19] clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg The register block base pointer as stored in the reg member of the r8a73a4_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to r8a73a4_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/f835f3dfcf3bf754065e5002663952cc6341caac.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-r8a73a4.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/renesas/clk-r8a73a4.c b/drivers/clk/renesas/clk-r8a73a4.c index cfed11c659d9..f45c2c45808b 100644 --- a/drivers/clk/renesas/clk-r8a73a4.c +++ b/drivers/clk/renesas/clk-r8a73a4.c @@ -18,7 +18,6 @@ struct r8a73a4_cpg { struct clk_onecell_data data; spinlock_t lock; - void __iomem *reg; }; #define CPG_CKSCR 0xc0 @@ -59,7 +58,7 @@ static const struct clk_div_table div4_div_table[] = { static struct clk * __init r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, - const char *name) + void __iomem *base, const char *name) { const struct clk_div_table *table = NULL; const char *parent_name; @@ -69,7 +68,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, if (!strcmp(name, "main")) { - u32 ckscr = readl(cpg->reg + CPG_CKSCR); + u32 ckscr = readl(base + CPG_CKSCR); switch ((ckscr >> 28) & 3) { case 0: /* extal1 */ @@ -93,14 +92,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, * clock implementation and we currently have no need to change * the multiplier value. */ - u32 value = readl(cpg->reg + CPG_PLL0CR); + u32 value = readl(base + CPG_PLL0CR); parent_name = "main"; mult = ((value >> 24) & 0x7f) + 1; if (value & BIT(20)) div = 2; } else if (!strcmp(name, "pll1")) { - u32 value = readl(cpg->reg + CPG_PLL1CR); + u32 value = readl(base + CPG_PLL1CR); parent_name = "main"; /* XXX: enable bit? */ @@ -123,7 +122,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, default: return ERR_PTR(-EINVAL); } - value = readl(cpg->reg + cr); + value = readl(base + cr); switch ((value >> 5) & 7) { case 0: parent_name = "main"; @@ -159,7 +158,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, shift = 0; } div *= 32; - mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f); + mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f); } else { struct div4_clk *c; @@ -181,7 +180,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, mult, div); } else { return clk_register_divider_table(NULL, name, parent_name, 0, - cpg->reg + reg, shift, 4, 0, + base + reg, shift, 4, 0, table, &cpg->lock); } } @@ -189,6 +188,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, static void __init r8a73a4_cpg_clocks_init(struct device_node *np) { struct r8a73a4_cpg *cpg; + void __iomem *base; struct clk **clks; unsigned int i; int num_clks; @@ -213,8 +213,8 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np) cpg->data.clks = clks; cpg->data.clk_num = num_clks; - cpg->reg = of_iomap(np, 0); - if (WARN_ON(cpg->reg == NULL)) + base = of_iomap(np, 0); + if (WARN_ON(base == NULL)) return; for (i = 0; i < num_clks; ++i) { @@ -224,7 +224,7 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = r8a73a4_cpg_register_clock(np, cpg, name); + clk = r8a73a4_cpg_register_clock(np, cpg, base, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); From a00d077aaa17c873ae1f465c5564d5d88e14d8f7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:11 +0200 Subject: [PATCH 11/19] clk: renesas: r8a7740: Remove r8a7740_cpg.reg The register block base pointer as stored in the reg member of the r8a7740_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to r8a7740_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/7ec676bcc36ef1eda02c2db328c527fc5fd44e99.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-r8a7740.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/renesas/clk-r8a7740.c b/drivers/clk/renesas/clk-r8a7740.c index d8190f007a81..3ee3f57e4e9a 100644 --- a/drivers/clk/renesas/clk-r8a7740.c +++ b/drivers/clk/renesas/clk-r8a7740.c @@ -18,7 +18,6 @@ struct r8a7740_cpg { struct clk_onecell_data data; spinlock_t lock; - void __iomem *reg; }; #define CPG_FRQCRA 0x00 @@ -61,7 +60,7 @@ static u32 cpg_mode __initdata; static struct clk * __init r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, - const char *name) + void __iomem *base, const char *name) { const struct clk_div_table *table = NULL; const char *parent_name; @@ -96,20 +95,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, * clock implementation and we currently have no need to change * the multiplier value. */ - u32 value = readl(cpg->reg + CPG_FRQCRC); + u32 value = readl(base + CPG_FRQCRC); parent_name = "system"; mult = ((value >> 24) & 0x7f) + 1; } else if (!strcmp(name, "pllc1")) { - u32 value = readl(cpg->reg + CPG_FRQCRA); + u32 value = readl(base + CPG_FRQCRA); parent_name = "system"; mult = ((value >> 24) & 0x7f) + 1; div = 2; } else if (!strcmp(name, "pllc2")) { - u32 value = readl(cpg->reg + CPG_PLLC2CR); + u32 value = readl(base + CPG_PLLC2CR); parent_name = "system"; mult = ((value >> 24) & 0x3f) + 1; } else if (!strcmp(name, "usb24s")) { - u32 value = readl(cpg->reg + CPG_USBCKCR); + u32 value = readl(base + CPG_USBCKCR); if (value & BIT(7)) /* extal2 */ parent_name = of_clk_get_parent_name(np, 1); @@ -137,7 +136,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, mult, div); } else { return clk_register_divider_table(NULL, name, parent_name, 0, - cpg->reg + reg, shift, 4, 0, + base + reg, shift, 4, 0, table, &cpg->lock); } } @@ -145,6 +144,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, static void __init r8a7740_cpg_clocks_init(struct device_node *np) { struct r8a7740_cpg *cpg; + void __iomem *base; struct clk **clks; unsigned int i; int num_clks; @@ -172,8 +172,8 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) cpg->data.clks = clks; cpg->data.clk_num = num_clks; - cpg->reg = of_iomap(np, 0); - if (WARN_ON(cpg->reg == NULL)) + base = of_iomap(np, 0); + if (WARN_ON(base == NULL)) return; for (i = 0; i < num_clks; ++i) { @@ -183,7 +183,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = r8a7740_cpg_register_clock(np, cpg, name); + clk = r8a7740_cpg_register_clock(np, cpg, base, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); From 3849716ad32ed80dc27de06a5c377ee4b7378ac2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:12 +0200 Subject: [PATCH 12/19] clk: renesas: sh73a0: Remove sh73a0_cpg.reg The register block base pointer as stored in the reg member of the sh73a0_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to sh73a0_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/5423e43d0cf518691965412fb510097d23ac5955.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-sh73a0.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/clk/renesas/clk-sh73a0.c b/drivers/clk/renesas/clk-sh73a0.c index 4146c1d717b9..8c51090f13e1 100644 --- a/drivers/clk/renesas/clk-sh73a0.c +++ b/drivers/clk/renesas/clk-sh73a0.c @@ -18,7 +18,6 @@ struct sh73a0_cpg { struct clk_onecell_data data; spinlock_t lock; - void __iomem *reg; }; #define CPG_FRQCRA 0x00 @@ -73,7 +72,7 @@ static const struct clk_div_table z_div_table[] = { static struct clk * __init sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, - const char *name) + void __iomem *base, const char *name) { const struct clk_div_table *table = NULL; unsigned int shift, reg, width; @@ -83,12 +82,12 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, if (!strcmp(name, "main")) { /* extal1, extal1_div2, extal2, extal2_div2 */ - u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; + u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3; parent_name = of_clk_get_parent_name(np, parent_idx >> 1); div = (parent_idx & 1) + 1; } else if (!strncmp(name, "pll", 3)) { - void __iomem *enable_reg = cpg->reg; + void __iomem *enable_reg = base; u32 enable_bit = name[3] - '0'; parent_name = "main"; @@ -108,7 +107,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, default: return ERR_PTR(-EINVAL); } - if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { + if (readl(base + CPG_PLLECR) & BIT(enable_bit)) { mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; /* handle CFG bit for PLL1 and PLL2 */ if (enable_bit == 1 || enable_bit == 2) @@ -117,7 +116,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, } } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) { u32 phy_no = name[3] - '0'; - void __iomem *dsi_reg = cpg->reg + + void __iomem *dsi_reg = base + (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR); parent_name = phy_no ? "dsi1pck" : "dsi0pck"; @@ -154,7 +153,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, mult, div); } else { return clk_register_divider_table(NULL, name, parent_name, 0, - cpg->reg + reg, shift, width, 0, + base + reg, shift, width, 0, table, &cpg->lock); } } @@ -162,6 +161,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, static void __init sh73a0_cpg_clocks_init(struct device_node *np) { struct sh73a0_cpg *cpg; + void __iomem *base; struct clk **clks; unsigned int i; int num_clks; @@ -186,14 +186,14 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np) cpg->data.clks = clks; cpg->data.clk_num = num_clks; - cpg->reg = of_iomap(np, 0); - if (WARN_ON(cpg->reg == NULL)) + base = of_iomap(np, 0); + if (WARN_ON(base == NULL)) return; /* Set SDHI clocks to a known state */ - writel(0x108, cpg->reg + CPG_SD0CKCR); - writel(0x108, cpg->reg + CPG_SD1CKCR); - writel(0x108, cpg->reg + CPG_SD2CKCR); + writel(0x108, base + CPG_SD0CKCR); + writel(0x108, base + CPG_SD1CKCR); + writel(0x108, base + CPG_SD2CKCR); for (i = 0; i < num_clks; ++i) { const char *name; @@ -202,7 +202,7 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = sh73a0_cpg_register_clock(np, cpg, name); + clk = sh73a0_cpg_register_clock(np, cpg, base, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); From 1cfeec24273874ffdc5459ef2f138ab61b7207a7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:13 +0200 Subject: [PATCH 13/19] clk: renesas: r8a7778: Remove struct r8a7778_cpg All but the data member of the r8a7778_cpg structure are unused, so the whole structure can be replaced by the single member used. Remove the mapping of the CPG registers, as no code uses the mapped registers. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/4123c1c40a901195f00a825d434553d2052829aa.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-r8a7778.c | 31 +++++++++---------------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/drivers/clk/renesas/clk-r8a7778.c b/drivers/clk/renesas/clk-r8a7778.c index 3ccc53685bdd..797556259370 100644 --- a/drivers/clk/renesas/clk-r8a7778.c +++ b/drivers/clk/renesas/clk-r8a7778.c @@ -11,12 +11,6 @@ #include #include -struct r8a7778_cpg { - struct clk_onecell_data data; - spinlock_t lock; - void __iomem *reg; -}; - /* PLL multipliers per bits 11, 12, and 18 of MODEMR */ static const struct { unsigned long plla_mult; @@ -47,8 +41,7 @@ static u32 cpg_mode_rates __initdata; static u32 cpg_mode_divs __initdata; static struct clk * __init -r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg, - const char *name) +r8a7778_cpg_register_clock(struct device_node *np, const char *name) { if (!strcmp(name, "plla")) { return clk_register_fixed_factor(NULL, "plla", @@ -77,7 +70,7 @@ r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg, static void __init r8a7778_cpg_clocks_init(struct device_node *np) { - struct r8a7778_cpg *cpg; + struct clk_onecell_data *data; struct clk **clks; unsigned int i; int num_clks; @@ -100,23 +93,17 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np) return; } - cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); + data = kzalloc(sizeof(*data), GFP_KERNEL); clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); - if (cpg == NULL || clks == NULL) { + if (data == NULL || clks == NULL) { /* We're leaking memory on purpose, there's no point in cleaning * up as the system won't boot anyway. */ return; } - spin_lock_init(&cpg->lock); - - cpg->data.clks = clks; - cpg->data.clk_num = num_clks; - - cpg->reg = of_iomap(np, 0); - if (WARN_ON(cpg->reg == NULL)) - return; + data->clks = clks; + data->clk_num = num_clks; for (i = 0; i < num_clks; ++i) { const char *name; @@ -125,15 +112,15 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = r8a7778_cpg_register_clock(np, cpg, name); + clk = r8a7778_cpg_register_clock(np, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); else - cpg->data.clks[i] = clk; + data->clks[i] = clk; } - of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); + of_clk_add_provider(np, of_clk_src_onecell_get, data); cpg_mstp_add_clk_domain(np); } From 444877983933d0efaf6788eabf2f750b1c175419 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:14 +0200 Subject: [PATCH 14/19] clk: renesas: r8a7779: Remove struct r8a7779_cpg All but the data member of the r8a7779_cpg structure are unused, so the whole structure can be replaced by the single member used. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/eb94c0f6c54a4f3a7e0e07f12781333a700c0a05.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-r8a7779.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/drivers/clk/renesas/clk-r8a7779.c b/drivers/clk/renesas/clk-r8a7779.c index 9f3b5522eef5..9a2fea8cf4d7 100644 --- a/drivers/clk/renesas/clk-r8a7779.c +++ b/drivers/clk/renesas/clk-r8a7779.c @@ -21,12 +21,6 @@ #define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1) -struct r8a7779_cpg { - struct clk_onecell_data data; - spinlock_t lock; - void __iomem *reg; -}; - /* ----------------------------------------------------------------------------- * CPG Clock Data */ @@ -87,7 +81,7 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; */ static struct clk * __init -r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, +r8a7779_cpg_register_clock(struct device_node *np, const struct cpg_clk_config *config, unsigned int plla_mult, const char *name) { @@ -119,7 +113,7 @@ r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, static void __init r8a7779_cpg_clocks_init(struct device_node *np) { const struct cpg_clk_config *config; - struct r8a7779_cpg *cpg; + struct clk_onecell_data *data; struct clk **clks; unsigned int i, plla_mult; int num_clks; @@ -134,19 +128,17 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) return; } - cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); + data = kzalloc(sizeof(*data), GFP_KERNEL); clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL); - if (cpg == NULL || clks == NULL) { + if (data == NULL || clks == NULL) { /* We're leaking memory on purpose, there's no point in cleaning * up as the system won't boot anyway. */ return; } - spin_lock_init(&cpg->lock); - - cpg->data.clks = clks; - cpg->data.clk_num = num_clks; + data->clks = clks; + data->clk_num = num_clks; config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)]; plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)]; @@ -158,16 +150,15 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = r8a7779_cpg_register_clock(np, cpg, config, - plla_mult, name); + clk = r8a7779_cpg_register_clock(np, config, plla_mult, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); else - cpg->data.clks[i] = clk; + data->clks[i] = clk; } - of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); + of_clk_add_provider(np, of_clk_src_onecell_get, data); cpg_mstp_add_clk_domain(np); } From 980bcaf33988e201dfd09cd75b20eea691fb3a0e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:15 +0200 Subject: [PATCH 15/19] clk: renesas: rza1: Remove struct rz_cpg The register block base pointer as stored in the reg member of the rz_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to rz_cpg_register_clock(). After this, the data member is the only remaining member of the rz_cpg structure, so the whole structure can be replaced by the data member. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/2380285576edaa4ad3dc5eca7e0ca418f068c6ef.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-rz.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c index 7b703f14e20b..e770f09a27ed 100644 --- a/drivers/clk/renesas/clk-rz.c +++ b/drivers/clk/renesas/clk-rz.c @@ -15,11 +15,6 @@ #include #include -struct rz_cpg { - struct clk_onecell_data data; - void __iomem *reg; -}; - #define CPG_FRQCR 0x10 #define CPG_FRQCR2 0x14 @@ -49,7 +44,8 @@ static u16 __init rz_cpg_read_mode_pins(void) } static struct clk * __init -rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) +rz_cpg_register_clock(struct device_node *np, void __iomem *base, + const char *name) { u32 val; unsigned mult; @@ -65,7 +61,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na } /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */ - if (!cpg->reg) + if (!base) return ERR_PTR(-ENXIO); /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3) @@ -73,9 +69,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na * let them run at fixed current speed and implement the details later. */ if (strcmp(name, "i") == 0) - val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3; + val = (readl(base + CPG_FRQCR) >> 8) & 3; else if (strcmp(name, "g") == 0) - val = readl(cpg->reg + CPG_FRQCR2) & 3; + val = readl(base + CPG_FRQCR2) & 3; else return ERR_PTR(-EINVAL); @@ -85,8 +81,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na static void __init rz_cpg_clocks_init(struct device_node *np) { - struct rz_cpg *cpg; + struct clk_onecell_data *data; struct clk **clks; + void __iomem *base; unsigned i; int num_clks; @@ -94,14 +91,14 @@ static void __init rz_cpg_clocks_init(struct device_node *np) if (WARN(num_clks <= 0, "can't count CPG clocks\n")) return; - cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); + data = kzalloc(sizeof(*data), GFP_KERNEL); clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); - BUG_ON(!cpg || !clks); + BUG_ON(!data || !clks); - cpg->data.clks = clks; - cpg->data.clk_num = num_clks; + data->clks = clks; + data->clk_num = num_clks; - cpg->reg = of_iomap(np, 0); + base = of_iomap(np, 0); for (i = 0; i < num_clks; ++i) { const char *name; @@ -109,15 +106,15 @@ static void __init rz_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = rz_cpg_register_clock(np, cpg, name); + clk = rz_cpg_register_clock(np, base, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); else - cpg->data.clks[i] = clk; + data->clks[i] = clk; } - of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); + of_clk_add_provider(np, of_clk_src_onecell_get, data); cpg_mstp_add_clk_domain(np); } From fc9e01676cc4eae0a66a8b5ee60cda68537718b6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:48:34 +0200 Subject: [PATCH 16/19] dt-bindings: clock: renesas,rzg2l: Simplify header file references The bindings already uses to refer to the header files with DT binding definitions for core clocks. Use more wildcards to simplify more references to these files. Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Link: https://lore.kernel.org/r/f274ad16010798dd4a45d2dca5f870da8acbb470.1654696009.git.geert+renesas@glider.be --- .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 8880b834f264..d036675e0779 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -45,10 +45,9 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - + , - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the or - . + a module number, as defined in . const: 2 '#power-domain-cells': @@ -62,7 +61,7 @@ properties: '#reset-cells': description: The single reset specifier cell must be the module number, as defined in - the or . + . const: 1 required: From d5c10876c76f6110a968c4afa065ef09a8630868 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:46:32 +0200 Subject: [PATCH 17/19] clk: renesas: r8a779f0: Add Z0 and Z1 clock support Add support for the Z0 and Z1 (Cortex-A55 Sub-System 0 (CPU 0-3) and Sub-System 1 (CPU 4-7)) clocks on R-Car S4-8, based on the existing support for Z clocks on R-Car Gen4. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/43009e25be1223a717e00c392cb2d416f5d47032.1654695893.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index e6f41b9f765a..ac0383c38aee 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -77,6 +77,8 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), /* Core Clock Outputs */ + DEF_GEN4_Z("z0", R8A779F0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0), + DEF_GEN4_Z("z1", R8A779F0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 8), DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1), From b7f64eaee5a345fe0c454f939252b46a26b47434 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 13 Jun 2022 20:56:27 +0900 Subject: [PATCH 18/19] clk: renesas: r8a779f0: Add PCIe clocks Add the module clocks used by the PCIe controllers on the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220613115627.2831257-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index ac0383c38aee..4610d6bd8b3b 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -126,6 +126,8 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER), + DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2), + DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2), DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), From 080bcd8d5997b1a615e17cab02bd9d16d1d4fbf3 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 14 Jun 2022 11:49:37 +0200 Subject: [PATCH 19/19] clk: renesas: r8a779f0: Add HSCIF clocks Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220614094937.8104-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 4610d6bd8b3b..cd80b6084ece 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -120,6 +120,10 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { + DEF_MOD("hscif0", 514, R8A779F0_CLK_S0D3), + DEF_MOD("hscif1", 515, R8A779F0_CLK_S0D3), + DEF_MOD("hscif2", 516, R8A779F0_CLK_S0D3), + DEF_MOD("hscif3", 517, R8A779F0_CLK_S0D3), DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),