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Merge tag 'mfd-next-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Browse Source 
Pull MFD updates from Lee Jones:
 "New Drivers:
   - Freescale MXS Low Resolution ADC
   - Freescale i.MX23/i.MX28 LRADC touchscreen
   - Motorola CPCAP Power Button
   - TI LMU (Lighting Management Unit)
   - Atmel SMC (Static Memory Controller)

  New Device Support:
   - Add support for X-Powers AXP803 to axp20x
   - Add support for Dialog Semi DA9061 to da9062-core
   - Add support for Intel Cougar Mountain to lpc_ich
   - Add support for Intel Gemini Lake to lpc_ich

  New Functionality:
   - Add Device Tree support; wm831x-*, axp20x, ti-lmu, da9062, sun4i-gpadc
   - Add IRQ sense support; motorola-cpcap
   - Add ACPI support; cros_ec
   - Add Reset support; altera-a10sr
   - Add ADC support; axp20x
   - Add AC Power support; axp20x
   - Add Runtime PM support; atmel-ebi, exynos-lpass
   - Add Battery Power Supply support; axp20x
   - Add Clock support; exynos-lpass, hi655x-pmic

  Fix-ups:
   - Implicitly specify required headers; motorola-cpcap, intel_soc_pmic_bxtwc
   - Add .remove() method; stm32-timers, exynos-lpass
   - Remove unused code; intel_soc_pmic_core, intel-lpss-acpi, ipaq-micro, atmel-smc, menelaus
   - Rename variables for clarity; axp20x
   - Convert pr_warning() to pr_warn(); db8500-prcmu, sta2x11-mfd, twl4030-power
   - Improve formatting; arizona-core, axp20x
   - Use raw_spinlock_*() variants; asic3, t7l66xb, tc6393xb
   - Simplify/refactor code; arizona-core, atmel-ebi
   - Improve error checking; intel_soc_pmic_core

  Bug Fixes:
   - Ensure OMAP3630/3730 boards can successfully reboot; twl4030-power
   - Correct max-register value; stm32-timers
   - Extend timeout to account for clock stretching; cros_ec_spi
   - Use correct IRQ trigger type; motorola-cpcap
   - Fix bad use of IRQ sense register; motorola-cpcap
   - Logic error "||" should be "&&"; mxs-lradc-ts"

* tag 'mfd-next-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (79 commits)
  input: touchscreen: mxs-lradc: || vs && typos
  dt-bindings: Add AXP803's regulator info
  mfd: axp20x: Support AXP803 variant
  dt-bindings: Add device tree binding for X-Powers AXP803 PMIC
  dt-bindings: Make AXP20X compatible strings one per line
  mfd: intel_soc_pmic_core: Fix unchecked return value
  mfd: menelaus: Remove obsolete local_irq_disable() and local_irq_enable()
  mfd: omap-usb-tll: Configure ULPIAUTOIDLE
  mfd: omap-usb-tll: Fix inverted bit use for USB TLL mode
  mfd: palmas: Fixed spelling mistake in error message
  mfd: lpc_ich: Add support for Intel Gemini Lake SoC
  mfd: hi655x: Add the clock cell to provide WiFi and Bluetooth
  mfd: intel_soc_pmic: Fix a mess with compilation units
  mfd: exynos-lpass: Add runtime PM support
  mfd: exynos-lpass: Add missing remove() function
  mfd: exynos-lpass: Add support for clocks
  mfd: exynos-lpass: Remove pad retention control
  iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs
  mfd: cpcap: Fix bad use of IRQ sense register
  mfd: cpcap: Use ack_invert interrupts
  ...
This commit is contained in:
Linus Torvalds
2017-05-03 12:16:25 -07:00
parent e897f267c5 ab6241ae07
commit d26f552ebb
80 changed files with 5574 additions and 2567 deletions
Download Patch File Download Diff File Expand all files Collapse all files

44
include/linux/mfd/axp20x.h
View File

@@ -20,6 +20,7 @@ enum axp20x_variants {
AXP221_ID,
AXP223_ID,
AXP288_ID,
AXP803_ID,
AXP806_ID,
AXP809_ID,
NR_AXP20X_VARIANTS,
@@ -228,13 +229,13 @@ enum axp20x_variants {
#define AXP20X_OCV_MAX 0xf
/* AXP22X specific registers */
#define AXP22X_PMIC_ADC_H 0x56
#define AXP22X_PMIC_ADC_L 0x57
#define AXP22X_PMIC_TEMP_H 0x56
#define AXP22X_PMIC_TEMP_L 0x57
#define AXP22X_TS_ADC_H 0x58
#define AXP22X_TS_ADC_L 0x59
#define AXP22X_BATLOW_THRES1 0xe6
/* AXP288 specific registers */
/* AXP288/AXP803 specific registers */
#define AXP288_POWER_REASON 0x02
#define AXP288_BC_GLOBAL 0x2c
#define AXP288_BC_VBUS_CNTL 0x2d
@@ -475,6 +476,43 @@ enum axp288_irqs {
AXP288_IRQ_BC_USB_CHNG,
};
enum axp803_irqs {
AXP803_IRQ_ACIN_OVER_V = 1,
AXP803_IRQ_ACIN_PLUGIN,
AXP803_IRQ_ACIN_REMOVAL,
AXP803_IRQ_VBUS_OVER_V,
AXP803_IRQ_VBUS_PLUGIN,
AXP803_IRQ_VBUS_REMOVAL,
AXP803_IRQ_BATT_PLUGIN,
AXP803_IRQ_BATT_REMOVAL,
AXP803_IRQ_BATT_ENT_ACT_MODE,
AXP803_IRQ_BATT_EXIT_ACT_MODE,
AXP803_IRQ_CHARG,
AXP803_IRQ_CHARG_DONE,
AXP803_IRQ_BATT_CHG_TEMP_HIGH,
AXP803_IRQ_BATT_CHG_TEMP_HIGH_END,
AXP803_IRQ_BATT_CHG_TEMP_LOW,
AXP803_IRQ_BATT_CHG_TEMP_LOW_END,
AXP803_IRQ_BATT_ACT_TEMP_HIGH,
AXP803_IRQ_BATT_ACT_TEMP_HIGH_END,
AXP803_IRQ_BATT_ACT_TEMP_LOW,
AXP803_IRQ_BATT_ACT_TEMP_LOW_END,
AXP803_IRQ_DIE_TEMP_HIGH,
AXP803_IRQ_GPADC,
AXP803_IRQ_LOW_PWR_LVL1,
AXP803_IRQ_LOW_PWR_LVL2,
AXP803_IRQ_TIMER,
AXP803_IRQ_PEK_RIS_EDGE,
AXP803_IRQ_PEK_FAL_EDGE,
AXP803_IRQ_PEK_SHORT,
AXP803_IRQ_PEK_LONG,
AXP803_IRQ_PEK_OVER_OFF,
AXP803_IRQ_GPIO1_INPUT,
AXP803_IRQ_GPIO0_INPUT,
AXP803_IRQ_BC_USB_CHNG,
AXP803_IRQ_MV_CHNG,
};
enum axp806_irqs {
AXP806_IRQ_DIE_TEMP_HIGH_LV1,
AXP806_IRQ_DIE_TEMP_HIGH_LV2,

18
include/linux/mfd/cros_ec.h
View File

@@ -305,4 +305,22 @@ extern struct attribute_group cros_ec_attr_group;
extern struct attribute_group cros_ec_lightbar_attr_group;
extern struct attribute_group cros_ec_vbc_attr_group;
/* ACPI GPE handler */
#ifdef CONFIG_ACPI
int cros_ec_acpi_install_gpe_handler(struct device *dev);
void cros_ec_acpi_remove_gpe_handler(void);
void cros_ec_acpi_clear_gpe(void);
#else /* CONFIG_ACPI */
static inline int cros_ec_acpi_install_gpe_handler(struct device *dev)
{
return -ENODEV;
}
static inline void cros_ec_acpi_remove_gpe_handler(void) {}
static inline void cros_ec_acpi_clear_gpe(void) {}
#endif /* CONFIG_ACPI */
#endif /* __LINUX_MFD_CROS_EC_H */

29
include/linux/mfd/da9062/core.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2015 Dialog Semiconductor Ltd.
* Copyright (C) 2015-2017 Dialog Semiconductor
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -18,7 +18,31 @@
#include <linux/interrupt.h>
#include <linux/mfd/da9062/registers.h>
/* Interrupts */
enum da9062_compatible_types {
COMPAT_TYPE_DA9061 = 1,
COMPAT_TYPE_DA9062,
};
enum da9061_irqs {
/* IRQ A */
DA9061_IRQ_ONKEY,
DA9061_IRQ_WDG_WARN,
DA9061_IRQ_SEQ_RDY,
/* IRQ B*/
DA9061_IRQ_TEMP,
DA9061_IRQ_LDO_LIM,
DA9061_IRQ_DVC_RDY,
DA9061_IRQ_VDD_WARN,
/* IRQ C */
DA9061_IRQ_GPI0,
DA9061_IRQ_GPI1,
DA9061_IRQ_GPI2,
DA9061_IRQ_GPI3,
DA9061_IRQ_GPI4,
DA9061_NUM_IRQ,
};
enum da9062_irqs {
/* IRQ A */
DA9062_IRQ_ONKEY,
@@ -45,6 +69,7 @@ struct da9062 {
struct device *dev;
struct regmap *regmap;
struct regmap_irq_chip_data *regmap_irq;
enum da9062_compatible_types chip_type;
};
#endif /* __MFD_DA9062_CORE_H__ */

5
include/linux/mfd/da9062/registers.h
View File

@@ -1,6 +1,5 @@
/*
* registers.h - REGISTERS H for DA9062
* Copyright (C) 2015 Dialog Semiconductor Ltd.
* Copyright (C) 2015-2017 Dialog Semiconductor
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -18,6 +17,8 @@
#define DA9062_PMIC_DEVICE_ID 0x62
#define DA9062_PMIC_VARIANT_MRC_AA 0x01
#define DA9062_PMIC_VARIANT_VRC_DA9061 0x01
#define DA9062_PMIC_VARIANT_VRC_DA9062 0x02
#define DA9062_I2C_PAGE_SEL_SHIFT 1

4
include/linux/mfd/intel_bxtwc.h → include/linux/mfd/intel_soc_pmic_bxtwc.h
View File

@@ -1,5 +1,5 @@
/*
* intel_bxtwc.h - Header file for Intel Broxton Whiskey Cove PMIC
* Header file for Intel Broxton Whiskey Cove PMIC
*
* Copyright (C) 2015 Intel Corporation. All rights reserved.
*
@@ -13,8 +13,6 @@
* more details.
*/
#include <linux/mfd/intel_soc_pmic.h>
#ifndef __INTEL_BXTWC_H__
#define __INTEL_BXTWC_H__

2
include/linux/mfd/motorola-cpcap.h
View File

@@ -293,3 +293,5 @@ static inline int cpcap_get_vendor(struct device *dev,
return 0;
}
extern int cpcap_sense_virq(struct regmap *regmap, int virq);

187
include/linux/mfd/mxs-lradc.h Normal file
View File

@@ -0,0 +1,187 @@
/*
* Freescale MXS Low Resolution Analog-to-Digital Converter driver
*
* Copyright (c) 2012 DENX Software Engineering, GmbH.
* Copyright (c) 2016 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
*
* Author: Marek Vasut <marex@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MFD_MXS_LRADC_H
#define __MFD_MXS_LRADC_H
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/stmp_device.h>
#define LRADC_MAX_DELAY_CHANS 4
#define LRADC_MAX_MAPPED_CHANS 8
#define LRADC_MAX_TOTAL_CHANS 16
#define LRADC_DELAY_TIMER_HZ 2000
#define LRADC_CTRL0 0x00
# define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE BIT(23)
# define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE BIT(22)
# define LRADC_CTRL0_MX28_YNNSW /* YM */ BIT(21)
# define LRADC_CTRL0_MX28_YPNSW /* YP */ BIT(20)
# define LRADC_CTRL0_MX28_YPPSW /* YP */ BIT(19)
# define LRADC_CTRL0_MX28_XNNSW /* XM */ BIT(18)
# define LRADC_CTRL0_MX28_XNPSW /* XM */ BIT(17)
# define LRADC_CTRL0_MX28_XPPSW /* XP */ BIT(16)
# define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE BIT(20)
# define LRADC_CTRL0_MX23_YM BIT(19)
# define LRADC_CTRL0_MX23_XM BIT(18)
# define LRADC_CTRL0_MX23_YP BIT(17)
# define LRADC_CTRL0_MX23_XP BIT(16)
# define LRADC_CTRL0_MX28_PLATE_MASK \
(LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
# define LRADC_CTRL0_MX23_PLATE_MASK \
(LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
#define LRADC_CTRL1 0x10
#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN BIT(24)
#define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
#define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
#define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16)
#define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16
#define LRADC_CTRL1_TOUCH_DETECT_IRQ BIT(8)
#define LRADC_CTRL1_LRADC_IRQ(n) BIT(n)
#define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
#define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
#define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
#define LRADC_CTRL2 0x20
#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
#define LRADC_CTRL2_TEMPSENSE_PWD BIT(15)
#define LRADC_STATUS 0x40
#define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0)
#define LRADC_CH(n) (0x50 + (0x10 * (n)))
#define LRADC_CH_ACCUMULATE BIT(29)
#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
#define LRADC_CH_NUM_SAMPLES_OFFSET 24
#define LRADC_CH_NUM_SAMPLES(x) \
((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
#define LRADC_CH_VALUE_MASK 0x3ffff
#define LRADC_CH_VALUE_OFFSET 0
#define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xffUL << 24)
#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
#define LRADC_DELAY_TRIGGER(x) \
(((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
LRADC_DELAY_TRIGGER_LRADCS_MASK)
#define LRADC_DELAY_KICK BIT(20)
#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
#define LRADC_DELAY_TRIGGER_DELAYS(x) \
(((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
LRADC_DELAY_TRIGGER_DELAYS_MASK)
#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
#define LRADC_DELAY_LOOP_COUNT_OFFSET 11
#define LRADC_DELAY_LOOP(x) \
(((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
LRADC_DELAY_LOOP_COUNT_MASK)
#define LRADC_DELAY_DELAY_MASK 0x7ff
#define LRADC_DELAY_DELAY_OFFSET 0
#define LRADC_DELAY_DELAY(x) \
(((x) << LRADC_DELAY_DELAY_OFFSET) & \
LRADC_DELAY_DELAY_MASK)
#define LRADC_CTRL4 0x140
#define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
#define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
#define LRADC_CTRL4_LRADCSELECT(n, x) \
(((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \
LRADC_CTRL4_LRADCSELECT_MASK(n))
#define LRADC_RESOLUTION 12
#define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
#define BUFFER_VCHANS_LIMITED 0x3f
#define BUFFER_VCHANS_ALL 0xff
/*
* Certain LRADC channels are shared between touchscreen
* and/or touch-buttons and generic LRADC block. Therefore when using
* either of these, these channels are not available for the regular
* sampling. The shared channels are as follows:
*
* CH0 -- Touch button #0
* CH1 -- Touch button #1
* CH2 -- Touch screen XPUL
* CH3 -- Touch screen YPLL
* CH4 -- Touch screen XNUL
* CH5 -- Touch screen YNLR
* CH6 -- Touch screen WIPER (5-wire only)
*
* The bit fields below represents which parts of the LRADC block are
* switched into special mode of operation. These channels can not
* be sampled as regular LRADC channels. The driver will refuse any
* attempt to sample these channels.
*/
#define CHAN_MASK_TOUCHBUTTON (BIT(1) | BIT(0))
#define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2)
#define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2)
enum mxs_lradc_id {
IMX23_LRADC,
IMX28_LRADC,
};
enum mxs_lradc_ts_wires {
MXS_LRADC_TOUCHSCREEN_NONE = 0,
MXS_LRADC_TOUCHSCREEN_4WIRE,
MXS_LRADC_TOUCHSCREEN_5WIRE,
};
/**
* struct mxs_lradc
* @soc: soc type (IMX23 or IMX28)
* @clk: 2 kHz clock for delay units
* @buffer_vchans: channels that can be used during buffered capture
* @touchscreen_wire: touchscreen type (4-wire or 5-wire)
* @use_touchbutton: button state (on or off)
*/
struct mxs_lradc {
enum mxs_lradc_id soc;
struct clk *clk;
u8 buffer_vchans;
enum mxs_lradc_ts_wires touchscreen_wire;
bool use_touchbutton;
};
static inline u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
{
switch (lradc->soc) {
case IMX23_LRADC:
return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
case IMX28_LRADC:
return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
default:
return 0;
}
}
#endif /* __MXS_LRADC_H */

229
include/linux/mfd/syscon/atmel-smc.h
View File

@@ -17,157 +17,92 @@
#include <linux/kernel.h>
#include <linux/regmap.h>
#define AT91SAM9_SMC_GENERIC 0x00
#define AT91SAM9_SMC_GENERIC_BLK_SZ 0x10
#define ATMEL_SMC_SETUP(cs) (((cs) * 0x10))
#define ATMEL_HSMC_SETUP(cs) (0x600 + ((cs) * 0x14))
#define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4)
#define ATMEL_HSMC_PULSE(cs) (0x600 + ((cs) * 0x14) + 0x4)
#define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8)
#define ATMEL_HSMC_CYCLE(cs) (0x600 + ((cs) * 0x14) + 0x8)
#define ATMEL_SMC_NWE_SHIFT 0
#define ATMEL_SMC_NCS_WR_SHIFT 8
#define ATMEL_SMC_NRD_SHIFT 16
#define ATMEL_SMC_NCS_RD_SHIFT 24
#define SAMA5_SMC_GENERIC 0x600
#define SAMA5_SMC_GENERIC_BLK_SZ 0x14
#define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc)
#define ATMEL_HSMC_MODE(cs) (0x600 + ((cs) * 0x14) + 0x10)
#define ATMEL_SMC_MODE_READMODE_MASK BIT(0)
#define ATMEL_SMC_MODE_READMODE_NCS (0 << 0)
#define ATMEL_SMC_MODE_READMODE_NRD (1 << 0)
#define ATMEL_SMC_MODE_WRITEMODE_MASK BIT(1)
#define ATMEL_SMC_MODE_WRITEMODE_NCS (0 << 1)
#define ATMEL_SMC_MODE_WRITEMODE_NWE (1 << 1)
#define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4)
#define ATMEL_SMC_MODE_EXNWMODE_DISABLE (0 << 4)
#define ATMEL_SMC_MODE_EXNWMODE_FROZEN (2 << 4)
#define ATMEL_SMC_MODE_EXNWMODE_READY (3 << 4)
#define ATMEL_SMC_MODE_BAT_MASK BIT(8)
#define ATMEL_SMC_MODE_BAT_SELECT (0 << 8)
#define ATMEL_SMC_MODE_BAT_WRITE (1 << 8)
#define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12)
#define ATMEL_SMC_MODE_DBW_8 (0 << 12)
#define ATMEL_SMC_MODE_DBW_16 (1 << 12)
#define ATMEL_SMC_MODE_DBW_32 (2 << 12)
#define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16)
#define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16)
#define ATMEL_SMC_MODE_TDF_MAX 16
#define ATMEL_SMC_MODE_TDF_MIN 1
#define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED BIT(20)
#define ATMEL_SMC_MODE_PMEN BIT(24)
#define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28)
#define ATMEL_SMC_MODE_PS_4 (0 << 28)
#define ATMEL_SMC_MODE_PS_8 (1 << 28)
#define ATMEL_SMC_MODE_PS_16 (2 << 28)
#define ATMEL_SMC_MODE_PS_32 (3 << 28)
#define AT91SAM9_SMC_SETUP(o) ((o) + 0x00)
#define AT91SAM9_SMC_NWESETUP(x) (x)
#define AT91SAM9_SMC_NCS_WRSETUP(x) ((x) << 8)
#define AT91SAM9_SMC_NRDSETUP(x) ((x) << 16)
#define AT91SAM9_SMC_NCS_NRDSETUP(x) ((x) << 24)
#define ATMEL_HSMC_TIMINGS(cs) (0x600 + ((cs) * 0x14) + 0xc)
#define ATMEL_HSMC_TIMINGS_OCMS BIT(12)
#define ATMEL_HSMC_TIMINGS_RBNSEL(x) ((x) << 28)
#define ATMEL_HSMC_TIMINGS_NFSEL BIT(31)
#define ATMEL_HSMC_TIMINGS_TCLR_SHIFT 0
#define ATMEL_HSMC_TIMINGS_TADL_SHIFT 4
#define ATMEL_HSMC_TIMINGS_TAR_SHIFT 8
#define ATMEL_HSMC_TIMINGS_TRR_SHIFT 16
#define ATMEL_HSMC_TIMINGS_TWB_SHIFT 24
#define AT91SAM9_SMC_PULSE(o) ((o) + 0x04)
#define AT91SAM9_SMC_NWEPULSE(x) (x)
#define AT91SAM9_SMC_NCS_WRPULSE(x) ((x) << 8)
#define AT91SAM9_SMC_NRDPULSE(x) ((x) << 16)
#define AT91SAM9_SMC_NCS_NRDPULSE(x) ((x) << 24)
#define AT91SAM9_SMC_CYCLE(o) ((o) + 0x08)
#define AT91SAM9_SMC_NWECYCLE(x) (x)
#define AT91SAM9_SMC_NRDCYCLE(x) ((x) << 16)
#define AT91SAM9_SMC_MODE(o) ((o) + 0x0c)
#define SAMA5_SMC_MODE(o) ((o) + 0x10)
#define AT91_SMC_READMODE BIT(0)
#define AT91_SMC_READMODE_NCS (0 << 0)
#define AT91_SMC_READMODE_NRD (1 << 0)
#define AT91_SMC_WRITEMODE BIT(1)
#define AT91_SMC_WRITEMODE_NCS (0 << 1)
#define AT91_SMC_WRITEMODE_NWE (1 << 1)
#define AT91_SMC_EXNWMODE GENMASK(5, 4)
#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
#define AT91_SMC_EXNWMODE_READY (3 << 4)
#define AT91_SMC_BAT BIT(8)
#define AT91_SMC_BAT_SELECT (0 << 8)
#define AT91_SMC_BAT_WRITE (1 << 8)
#define AT91_SMC_DBW GENMASK(13, 12)
#define AT91_SMC_DBW_8 (0 << 12)
#define AT91_SMC_DBW_16 (1 << 12)
#define AT91_SMC_DBW_32 (2 << 12)
#define AT91_SMC_TDF GENMASK(19, 16)
#define AT91_SMC_TDF_(x) ((((x) - 1) << 16) & AT91_SMC_TDF)
#define AT91_SMC_TDF_MAX 16
#define AT91_SMC_TDFMODE_OPTIMIZED BIT(20)
#define AT91_SMC_PMEN BIT(24)
#define AT91_SMC_PS GENMASK(29, 28)
#define AT91_SMC_PS_4 (0 << 28)
#define AT91_SMC_PS_8 (1 << 28)
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
/*
* This function converts a setup timing expressed in nanoseconds into an
* encoded value that can be written in the SMC_SETUP register.
*
* The following formula is described in atmel datasheets (section
* "SMC Setup Register"):
*
* setup length = (128* SETUP[5] + SETUP[4:0])
*
* where setup length is the timing expressed in cycles.
/**
* struct atmel_smc_cs_conf - SMC CS config as described in the datasheet.
* @setup: NCS/NWE/NRD setup timings (not applicable to at91rm9200)
* @pulse: NCS/NWE/NRD pulse timings (not applicable to at91rm9200)
* @cycle: NWE/NRD cycle timings (not applicable to at91rm9200)
* @timings: advanced NAND related timings (only applicable to HSMC)
* @mode: all kind of config parameters (see the fields definition above).
* The mode fields are different on at91rm9200
*/
static inline u32 at91sam9_smc_setup_ns_to_cycles(unsigned int clk_rate,
u32 timing_ns)
{
u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
u32 coded_cycles = 0;
u32 cycles;
struct atmel_smc_cs_conf {
u32 setup;
u32 pulse;
u32 cycle;
u32 timings;
u32 mode;
};
cycles = DIV_ROUND_UP(timing_ns, clk_period);
if (cycles / 32) {
coded_cycles |= 1 << 5;
if (cycles < 128)
cycles = 0;
}
coded_cycles |= cycles % 32;
return coded_cycles;
}
/*
* This function converts a pulse timing expressed in nanoseconds into an
* encoded value that can be written in the SMC_PULSE register.
*
* The following formula is described in atmel datasheets (section
* "SMC Pulse Register"):
*
* pulse length = (256* PULSE[6] + PULSE[5:0])
*
* where pulse length is the timing expressed in cycles.
*/
static inline u32 at91sam9_smc_pulse_ns_to_cycles(unsigned int clk_rate,
u32 timing_ns)
{
u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
u32 coded_cycles = 0;
u32 cycles;
cycles = DIV_ROUND_UP(timing_ns, clk_period);
if (cycles / 64) {
coded_cycles |= 1 << 6;
if (cycles < 256)
cycles = 0;
}
coded_cycles |= cycles % 64;
return coded_cycles;
}
/*
* This function converts a cycle timing expressed in nanoseconds into an
* encoded value that can be written in the SMC_CYCLE register.
*
* The following formula is described in atmel datasheets (section
* "SMC Cycle Register"):
*
* cycle length = (CYCLE[8:7]*256 + CYCLE[6:0])
*
* where cycle length is the timing expressed in cycles.
*/
static inline u32 at91sam9_smc_cycle_ns_to_cycles(unsigned int clk_rate,
u32 timing_ns)
{
u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
u32 coded_cycles = 0;
u32 cycles;
cycles = DIV_ROUND_UP(timing_ns, clk_period);
if (cycles / 128) {
coded_cycles = cycles / 256;
cycles %= 256;
if (cycles >= 128) {
coded_cycles++;
cycles = 0;
}
if (coded_cycles > 0x3) {
coded_cycles = 0x3;
cycles = 0x7f;
}
coded_cycles <<= 7;
}
coded_cycles |= cycles % 128;
return coded_cycles;
}
void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf);
int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
unsigned int shift,
unsigned int ncycles);
int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
unsigned int shift, unsigned int ncycles);
int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
unsigned int shift, unsigned int ncycles);
int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
unsigned int shift, unsigned int ncycles);
void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
const struct atmel_smc_cs_conf *conf);
void atmel_hsmc_cs_conf_apply(struct regmap *regmap, int cs,
const struct atmel_smc_cs_conf *conf);
void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
struct atmel_smc_cs_conf *conf);
void atmel_hsmc_cs_conf_get(struct regmap *regmap, int cs,
struct atmel_smc_cs_conf *conf);
#endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */

3
include/linux/mfd/syscon/exynos5-pmu.h
View File

@@ -46,7 +46,4 @@
#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1)
#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2)
#define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028)
#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR BIT(28)
#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */

280
include/linux/mfd/ti-lmu-register.h Normal file
View File

@@ -0,0 +1,280 @@
/*
* TI LMU (Lighting Management Unit) Device Register Map
*
* Copyright 2017 Texas Instruments
*
* Author: Milo Kim <milo.kim@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MFD_TI_LMU_REGISTER_H__
#define __MFD_TI_LMU_REGISTER_H__
#include <linux/bitops.h>
/* LM3532 */
#define LM3532_REG_OUTPUT_CFG 0x10
#define LM3532_ILED1_CFG_MASK 0x03
#define LM3532_ILED2_CFG_MASK 0x0C
#define LM3532_ILED3_CFG_MASK 0x30
#define LM3532_ILED1_CFG_SHIFT 0
#define LM3532_ILED2_CFG_SHIFT 2
#define LM3532_ILED3_CFG_SHIFT 4
#define LM3532_REG_RAMPUP 0x12
#define LM3532_REG_RAMPDN LM3532_REG_RAMPUP
#define LM3532_RAMPUP_MASK 0x07
#define LM3532_RAMPUP_SHIFT 0
#define LM3532_RAMPDN_MASK 0x38
#define LM3532_RAMPDN_SHIFT 3
#define LM3532_REG_ENABLE 0x1D
#define LM3532_REG_PWM_A_CFG 0x13
#define LM3532_PWM_A_MASK 0x05 /* zone 0 */
#define LM3532_PWM_ZONE_0 BIT(2)
#define LM3532_REG_PWM_B_CFG 0x14
#define LM3532_PWM_B_MASK 0x09 /* zone 1 */
#define LM3532_PWM_ZONE_1 BIT(3)
#define LM3532_REG_PWM_C_CFG 0x15
#define LM3532_PWM_C_MASK 0x11 /* zone 2 */
#define LM3532_PWM_ZONE_2 BIT(4)
#define LM3532_REG_ZONE_CFG_A 0x16
#define LM3532_REG_ZONE_CFG_B 0x18
#define LM3532_REG_ZONE_CFG_C 0x1A
#define LM3532_ZONE_MASK (BIT(2) | BIT(3) | BIT(4))
#define LM3532_ZONE_0 0
#define LM3532_ZONE_1 BIT(2)
#define LM3532_ZONE_2 BIT(3)
#define LM3532_REG_BRT_A 0x70 /* zone 0 */
#define LM3532_REG_BRT_B 0x76 /* zone 1 */
#define LM3532_REG_BRT_C 0x7C /* zone 2 */
#define LM3532_MAX_REG 0x7E
/* LM3631 */
#define LM3631_REG_DEVCTRL 0x00
#define LM3631_LCD_EN_MASK BIT(1)
#define LM3631_BL_EN_MASK BIT(0)
#define LM3631_REG_BRT_LSB 0x01
#define LM3631_REG_BRT_MSB 0x02
#define LM3631_REG_BL_CFG 0x06
#define LM3631_BL_CHANNEL_MASK BIT(3)
#define LM3631_BL_DUAL_CHANNEL 0
#define LM3631_BL_SINGLE_CHANNEL BIT(3)
#define LM3631_MAP_MASK BIT(5)
#define LM3631_EXPONENTIAL_MAP 0
#define LM3631_REG_BRT_MODE 0x08
#define LM3631_MODE_MASK (BIT(1) | BIT(2) | BIT(3))
#define LM3631_DEFAULT_MODE (BIT(1) | BIT(3))
#define LM3631_REG_SLOPE 0x09
#define LM3631_SLOPE_MASK 0xF0
#define LM3631_SLOPE_SHIFT 4
#define LM3631_REG_LDO_CTRL1 0x0A
#define LM3631_EN_OREF_MASK BIT(0)
#define LM3631_EN_VNEG_MASK BIT(1)
#define LM3631_EN_VPOS_MASK BIT(2)
#define LM3631_REG_LDO_CTRL2 0x0B
#define LM3631_EN_CONT_MASK BIT(0)
#define LM3631_REG_VOUT_CONT 0x0C
#define LM3631_VOUT_CONT_MASK (BIT(6) | BIT(7))
#define LM3631_REG_VOUT_BOOST 0x0C
#define LM3631_REG_VOUT_POS 0x0D
#define LM3631_REG_VOUT_NEG 0x0E
#define LM3631_REG_VOUT_OREF 0x0F
#define LM3631_VOUT_MASK 0x3F
#define LM3631_REG_ENTIME_VCONT 0x0B
#define LM3631_ENTIME_CONT_MASK 0x70
#define LM3631_REG_ENTIME_VOREF 0x0F
#define LM3631_REG_ENTIME_VPOS 0x10
#define LM3631_REG_ENTIME_VNEG 0x11
#define LM3631_ENTIME_MASK 0xF0
#define LM3631_ENTIME_SHIFT 4
#define LM3631_MAX_REG 0x16
/* LM3632 */
#define LM3632_REG_CONFIG1 0x02
#define LM3632_OVP_MASK (BIT(5) | BIT(6) | BIT(7))
#define LM3632_OVP_25V BIT(6)
#define LM3632_REG_CONFIG2 0x03
#define LM3632_SWFREQ_MASK BIT(7)
#define LM3632_SWFREQ_1MHZ BIT(7)
#define LM3632_REG_BRT_LSB 0x04
#define LM3632_REG_BRT_MSB 0x05
#define LM3632_REG_IO_CTRL 0x09
#define LM3632_PWM_MASK BIT(6)
#define LM3632_I2C_MODE 0
#define LM3632_PWM_MODE BIT(6)
#define LM3632_REG_ENABLE 0x0A
#define LM3632_BL_EN_MASK BIT(0)
#define LM3632_BL_CHANNEL_MASK (BIT(3) | BIT(4))
#define LM3632_BL_SINGLE_CHANNEL BIT(4)
#define LM3632_BL_DUAL_CHANNEL BIT(3)
#define LM3632_REG_BIAS_CONFIG 0x0C
#define LM3632_EXT_EN_MASK BIT(0)
#define LM3632_EN_VNEG_MASK BIT(1)
#define LM3632_EN_VPOS_MASK BIT(2)
#define LM3632_REG_VOUT_BOOST 0x0D
#define LM3632_REG_VOUT_POS 0x0E
#define LM3632_REG_VOUT_NEG 0x0F
#define LM3632_VOUT_MASK 0x3F
#define LM3632_MAX_REG 0x10
/* LM3633 */
#define LM3633_REG_HVLED_OUTPUT_CFG 0x10
#define LM3633_HVLED1_CFG_MASK BIT(0)
#define LM3633_HVLED2_CFG_MASK BIT(1)
#define LM3633_HVLED3_CFG_MASK BIT(2)
#define LM3633_HVLED1_CFG_SHIFT 0
#define LM3633_HVLED2_CFG_SHIFT 1
#define LM3633_HVLED3_CFG_SHIFT 2
#define LM3633_REG_BANK_SEL 0x11
#define LM3633_REG_BL0_RAMP 0x12
#define LM3633_REG_BL1_RAMP 0x13
#define LM3633_BL_RAMPUP_MASK 0xF0
#define LM3633_BL_RAMPUP_SHIFT 4
#define LM3633_BL_RAMPDN_MASK 0x0F
#define LM3633_BL_RAMPDN_SHIFT 0
#define LM3633_REG_BL_RAMP_CONF 0x1B
#define LM3633_BL_RAMP_MASK 0x0F
#define LM3633_BL_RAMP_EACH 0x05
#define LM3633_REG_PTN0_RAMP 0x1C
#define LM3633_REG_PTN1_RAMP 0x1D
#define LM3633_PTN_RAMPUP_MASK 0x70
#define LM3633_PTN_RAMPUP_SHIFT 4
#define LM3633_PTN_RAMPDN_MASK 0x07
#define LM3633_PTN_RAMPDN_SHIFT 0
#define LM3633_REG_LED_MAPPING_MODE 0x1F
#define LM3633_LED_EXPONENTIAL BIT(1)
#define LM3633_REG_IMAX_HVLED_A 0x20
#define LM3633_REG_IMAX_HVLED_B 0x21
#define LM3633_REG_IMAX_LVLED_BASE 0x22
#define LM3633_REG_BL_FEEDBACK_ENABLE 0x28
#define LM3633_REG_ENABLE 0x2B
#define LM3633_LED_BANK_OFFSET 2
#define LM3633_REG_PATTERN 0x2C
#define LM3633_REG_BOOST_CFG 0x2D
#define LM3633_OVP_MASK (BIT(1) | BIT(2))
#define LM3633_OVP_40V 0x6
#define LM3633_REG_PWM_CFG 0x2F
#define LM3633_PWM_A_MASK BIT(0)
#define LM3633_PWM_B_MASK BIT(1)
#define LM3633_REG_BRT_HVLED_A_LSB 0x40
#define LM3633_REG_BRT_HVLED_A_MSB 0x41
#define LM3633_REG_BRT_HVLED_B_LSB 0x42
#define LM3633_REG_BRT_HVLED_B_MSB 0x43
#define LM3633_REG_BRT_LVLED_BASE 0x44
#define LM3633_REG_PTN_DELAY 0x50
#define LM3633_REG_PTN_LOWTIME 0x51
#define LM3633_REG_PTN_HIGHTIME 0x52
#define LM3633_REG_PTN_LOWBRT 0x53
#define LM3633_REG_PTN_HIGHBRT LM3633_REG_BRT_LVLED_BASE
#define LM3633_REG_BL_OPEN_FAULT_STATUS 0xB0
#define LM3633_REG_BL_SHORT_FAULT_STATUS 0xB2
#define LM3633_REG_MONITOR_ENABLE 0xB4
#define LM3633_MAX_REG 0xB4
/* LM3695 */
#define LM3695_REG_GP 0x10
#define LM3695_BL_CHANNEL_MASK BIT(3)
#define LM3695_BL_DUAL_CHANNEL 0
#define LM3695_BL_SINGLE_CHANNEL BIT(3)
#define LM3695_BRT_RW_MASK BIT(2)
#define LM3695_BL_EN_MASK BIT(0)
#define LM3695_REG_BRT_LSB 0x13
#define LM3695_REG_BRT_MSB 0x14
#define LM3695_MAX_REG 0x14
/* LM3697 */
#define LM3697_REG_HVLED_OUTPUT_CFG 0x10
#define LM3697_HVLED1_CFG_MASK BIT(0)
#define LM3697_HVLED2_CFG_MASK BIT(1)
#define LM3697_HVLED3_CFG_MASK BIT(2)
#define LM3697_HVLED1_CFG_SHIFT 0
#define LM3697_HVLED2_CFG_SHIFT 1
#define LM3697_HVLED3_CFG_SHIFT 2
#define LM3697_REG_BL0_RAMP 0x11
#define LM3697_REG_BL1_RAMP 0x12
#define LM3697_RAMPUP_MASK 0xF0
#define LM3697_RAMPUP_SHIFT 4
#define LM3697_RAMPDN_MASK 0x0F
#define LM3697_RAMPDN_SHIFT 0
#define LM3697_REG_RAMP_CONF 0x14
#define LM3697_RAMP_MASK 0x0F
#define LM3697_RAMP_EACH 0x05
#define LM3697_REG_PWM_CFG 0x1C
#define LM3697_PWM_A_MASK BIT(0)
#define LM3697_PWM_B_MASK BIT(1)
#define LM3697_REG_IMAX_A 0x17
#define LM3697_REG_IMAX_B 0x18
#define LM3697_REG_FEEDBACK_ENABLE 0x19
#define LM3697_REG_BRT_A_LSB 0x20
#define LM3697_REG_BRT_A_MSB 0x21
#define LM3697_REG_BRT_B_LSB 0x22
#define LM3697_REG_BRT_B_MSB 0x23
#define LM3697_REG_ENABLE 0x24
#define LM3697_REG_OPEN_FAULT_STATUS 0xB0
#define LM3697_REG_SHORT_FAULT_STATUS 0xB2
#define LM3697_REG_MONITOR_ENABLE 0xB4
#define LM3697_MAX_REG 0xB4
#endif

87
include/linux/mfd/ti-lmu.h Normal file
View File

@@ -0,0 +1,87 @@
/*
* TI LMU (Lighting Management Unit) Devices
*
* Copyright 2017 Texas Instruments
*
* Author: Milo Kim <milo.kim@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MFD_TI_LMU_H__
#define __MFD_TI_LMU_H__
#include <linux/gpio.h>
#include <linux/notifier.h>
#include <linux/regmap.h>
/* Notifier event */
#define LMU_EVENT_MONITOR_DONE 0x01
enum ti_lmu_id {
LM3532,
LM3631,
LM3632,
LM3633,
LM3695,
LM3697,
LMU_MAX_ID,
};
enum ti_lmu_max_current {
LMU_IMAX_5mA,
LMU_IMAX_6mA,
LMU_IMAX_7mA = 0x03,
LMU_IMAX_8mA,
LMU_IMAX_9mA,
LMU_IMAX_10mA = 0x07,
LMU_IMAX_11mA,
LMU_IMAX_12mA,
LMU_IMAX_13mA,
LMU_IMAX_14mA,
LMU_IMAX_15mA = 0x0D,
LMU_IMAX_16mA,
LMU_IMAX_17mA,
LMU_IMAX_18mA,
LMU_IMAX_19mA,
LMU_IMAX_20mA = 0x13,
LMU_IMAX_21mA,
LMU_IMAX_22mA,
LMU_IMAX_23mA = 0x17,
LMU_IMAX_24mA,
LMU_IMAX_25mA,
LMU_IMAX_26mA,
LMU_IMAX_27mA = 0x1C,
LMU_IMAX_28mA,
LMU_IMAX_29mA,
LMU_IMAX_30mA,
};
enum lm363x_regulator_id {
LM3631_BOOST, /* Boost output */
LM3631_LDO_CONT, /* Display panel controller */
LM3631_LDO_OREF, /* Gamma reference */
LM3631_LDO_POS, /* Positive display bias output */
LM3631_LDO_NEG, /* Negative display bias output */
LM3632_BOOST, /* Boost output */
LM3632_LDO_POS, /* Positive display bias output */
LM3632_LDO_NEG, /* Negative display bias output */
};
/**
* struct ti_lmu
*
* @dev: Parent device pointer
* @regmap: Used for i2c communcation on accessing registers
* @en_gpio: GPIO for HWEN pin [Optional]
* @notifier: Notifier for reporting hwmon event
*/
struct ti_lmu {
struct device *dev;
struct regmap *regmap;
int en_gpio;
struct blocking_notifier_head notifier;
};
#endif

9
include/linux/mfd/wm831x/core.h
View File

@@ -21,6 +21,8 @@
#include <linux/list.h>
#include <linux/regmap.h>
#include <linux/mfd/wm831x/auxadc.h>
#include <linux/mfd/wm831x/pdata.h>
#include <linux/of.h>
/*
* Register values.
@@ -367,6 +369,9 @@ struct wm831x {
struct regmap *regmap;
struct wm831x_pdata pdata;
enum wm831x_parent type;
int irq; /* Our chip IRQ */
struct mutex irq_lock;
struct irq_domain *irq_domain;
@@ -412,7 +417,7 @@ int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
int count, u16 *buf);
int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq);
int wm831x_device_init(struct wm831x *wm831x, int irq);
void wm831x_device_exit(struct wm831x *wm831x);
int wm831x_device_suspend(struct wm831x *wm831x);
void wm831x_device_shutdown(struct wm831x *wm831x);
@@ -427,4 +432,6 @@ static inline int wm831x_irq(struct wm831x *wm831x, int irq)
extern struct regmap_config wm831x_regmap_config;
extern const struct of_device_id wm831x_of_match[];
#endif