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misc: pch_phub: Drop two unused functions

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The two functions are unused since commit 34afa1d657
("misc/pch_phub.c: use generic power management") but the compiler
didn't warn about it because the same commit marked the functions as
__maybe_unsed.

Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
Link: https://patch.msgid.link/aaa24e2dbb2be5fb2dffa61c89fc190aaa391ad0.1779360001.git.u.kleine-koenig@baylibre.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Uwe Kleine-König (The Capable Hub)
2026-05-21 12:46:35 +02:00
committed by Greg Kroah-Hartman
parent e8c715f3a7
commit d14b649fd9
1 changed files with 0 additions and 123 deletions
Download Patch File Download Diff File Expand all files Collapse all files

123
drivers/misc/pch_phub.c
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@@ -149,129 +149,6 @@ static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr); iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
} }
/* pch_phub_save_reg_conf - saves register configuration */
static void __maybe_unused pch_phub_save_reg_conf(struct pci_dev *pdev)
{
unsigned int i;
struct pch_phub_reg *chip = pci_get_drvdata(pdev);
void __iomem *p = chip->pch_phub_base_address;
chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
chip->comp_resp_timeout_reg =
ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
chip->bus_slave_control_reg =
ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
chip->deadlock_avoid_type_reg =
ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
chip->intpin_reg_wpermit_reg0 =
ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
chip->intpin_reg_wpermit_reg1 =
ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
chip->intpin_reg_wpermit_reg2 =
ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
chip->intpin_reg_wpermit_reg3 =
ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
dev_dbg(&pdev->dev, "%s : "
"chip->phub_id_reg=%x, "
"chip->q_pri_val_reg=%x, "
"chip->rc_q_maxsize_reg=%x, "
"chip->bri_q_maxsize_reg=%x, "
"chip->comp_resp_timeout_reg=%x, "
"chip->bus_slave_control_reg=%x, "
"chip->deadlock_avoid_type_reg=%x, "
"chip->intpin_reg_wpermit_reg0=%x, "
"chip->intpin_reg_wpermit_reg1=%x, "
"chip->intpin_reg_wpermit_reg2=%x, "
"chip->intpin_reg_wpermit_reg3=%x\n", __func__,
chip->phub_id_reg,
chip->q_pri_val_reg,
chip->rc_q_maxsize_reg,
chip->bri_q_maxsize_reg,
chip->comp_resp_timeout_reg,
chip->bus_slave_control_reg,
chip->deadlock_avoid_type_reg,
chip->intpin_reg_wpermit_reg0,
chip->intpin_reg_wpermit_reg1,
chip->intpin_reg_wpermit_reg2,
chip->intpin_reg_wpermit_reg3);
for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
chip->int_reduce_control_reg[i] =
ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
dev_dbg(&pdev->dev, "%s : "
"chip->int_reduce_control_reg[%d]=%x\n",
__func__, i, chip->int_reduce_control_reg[i]);
}
chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
}
/* pch_phub_restore_reg_conf - restore register configuration */
static void __maybe_unused pch_phub_restore_reg_conf(struct pci_dev *pdev)
{
unsigned int i;
struct pch_phub_reg *chip = pci_get_drvdata(pdev);
void __iomem *p;
p = chip->pch_phub_base_address;
iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
iowrite32(chip->comp_resp_timeout_reg,
p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
iowrite32(chip->bus_slave_control_reg,
p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
iowrite32(chip->deadlock_avoid_type_reg,
p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
iowrite32(chip->intpin_reg_wpermit_reg0,
p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
iowrite32(chip->intpin_reg_wpermit_reg1,
p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
iowrite32(chip->intpin_reg_wpermit_reg2,
p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
iowrite32(chip->intpin_reg_wpermit_reg3,
p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
dev_dbg(&pdev->dev, "%s : "
"chip->phub_id_reg=%x, "
"chip->q_pri_val_reg=%x, "
"chip->rc_q_maxsize_reg=%x, "
"chip->bri_q_maxsize_reg=%x, "
"chip->comp_resp_timeout_reg=%x, "
"chip->bus_slave_control_reg=%x, "
"chip->deadlock_avoid_type_reg=%x, "
"chip->intpin_reg_wpermit_reg0=%x, "
"chip->intpin_reg_wpermit_reg1=%x, "
"chip->intpin_reg_wpermit_reg2=%x, "
"chip->intpin_reg_wpermit_reg3=%x\n", __func__,
chip->phub_id_reg,
chip->q_pri_val_reg,
chip->rc_q_maxsize_reg,
chip->bri_q_maxsize_reg,
chip->comp_resp_timeout_reg,
chip->bus_slave_control_reg,
chip->deadlock_avoid_type_reg,
chip->intpin_reg_wpermit_reg0,
chip->intpin_reg_wpermit_reg1,
chip->intpin_reg_wpermit_reg2,
chip->intpin_reg_wpermit_reg3);
for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
iowrite32(chip->int_reduce_control_reg[i],
p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
dev_dbg(&pdev->dev, "%s : "
"chip->int_reduce_control_reg[%d]=%x\n",
__func__, i, chip->int_reduce_control_reg[i]);
}
iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
}
/** /**
* pch_phub_read_serial_rom() - Reading Serial ROM * pch_phub_read_serial_rom() - Reading Serial ROM
* @chip: Pointer to the PHUB register structure * @chip: Pointer to the PHUB register structure