From 4422516114725edd175121751d07c0896876838e Mon Sep 17 00:00:00 2001 From: Pablo Greco Date: Tue, 23 Apr 2019 14:25:58 -0300 Subject: [PATCH 01/21] ARM: dts: sun8i: r40: bananapi-m2-ultra: Add GPIO pin-bank regulator supplies The bananapi-m2-ultra has the PMIC providing voltage to all the pin-bank supply rails from its various regulator outputs, tie them to the pio node. Signed-off-by: Pablo Greco Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index c488aaacbd68..699579d43105 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -201,6 +201,12 @@ &ohci2 { &pio { pinctrl-names = "default"; pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo1>; }; ®_aldo2 { From 30cf87fd3376365675004dcc50a0cc0d87ba5315 Mon Sep 17 00:00:00 2001 From: Pablo Greco Date: Thu, 2 May 2019 10:33:45 -0300 Subject: [PATCH 02/21] ARM: dts: sun8i: v40: bananapi-m2-berry: Add GPIO pin-bank regulator supplies The bananapi-m2-berry has the PMIC providing voltage to all the pin-bank supply rails from its various regulator outputs, tie them to the pio node. Signed-off-by: Pablo Greco Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index f05cabd34b8e..27297f49b16d 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -123,6 +123,21 @@ &mmc1 { status = "okay"; }; +&pio { + vcc-pa-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo1>; +}; + +®_aldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa"; +}; + ®_aldo3 { regulator-always-on; regulator-min-microvolt = <2700000>; From 27e81e1970a86d1574f3ccf11bf6f7599d822db3 Mon Sep 17 00:00:00 2001 From: Pablo Greco Date: Thu, 2 May 2019 10:33:46 -0300 Subject: [PATCH 03/21] ARM: dts: sun8i: v40: bananapi-m2-berry: Enable GMAC ethernet controller Just like the Bananapi M2 Ultra, the Bananapi M2 Berry has a Realtek RTL8211E RGMII PHY tied to the GMAC. The PMIC's DC1SW output provides power for the PHY, while the ALDO2 output provides I/O voltages on both sides. Signed-off-by: Pablo Greco Signed-off-by: Maxime Ripard --- .../boot/dts/sun8i-v40-bananapi-m2-berry.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index 27297f49b16d..0dfde5808bf8 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -50,6 +50,7 @@ / { compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40"; aliases { + ethernet0 = &gmac; serial0 = &uart0; }; @@ -92,6 +93,22 @@ &ehci1 { status = "okay"; }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_dc1sw>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &i2c0 { status = "okay"; @@ -145,6 +162,12 @@ ®_aldo3 { regulator-name = "avcc"; }; +®_dc1sw { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-gmac-phy"; +}; + ®_dcdc1 { regulator-always-on; regulator-min-microvolt = <3000000>; From 4da567ba35a4c4f5b0c42f5c4c16bea3d4fc9f22 Mon Sep 17 00:00:00 2001 From: Pablo Greco Date: Thu, 2 May 2019 10:33:47 -0300 Subject: [PATCH 04/21] ARM: dts: sun8i: v40: bananapi-m2-berry: Enable HDMI output This patch adds the hdmi nodes to the Bananapi M2 Berry, the same way it was done to the Bananapi M2 Ultra Signed-off-by: Pablo Greco Signed-off-by: Maxime Ripard --- .../boot/dts/sun8i-v40-bananapi-m2-berry.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index 0dfde5808bf8..1f4f51f94188 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -58,6 +58,17 @@ chosen { stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -88,6 +99,10 @@ wifi_pwrseq: wifi_pwrseq { }; }; +&de { + status = "okay"; +}; + &ehci1 { /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ status = "okay"; @@ -109,6 +124,16 @@ phy1: ethernet-phy@1 { }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { status = "okay"; @@ -208,6 +233,10 @@ ®_dldo2 { regulator-name = "vcc-wifi"; }; +&tcon_tv0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From 78f8e6d97fa0bc97e6bbf88c8f1eba3a01138634 Mon Sep 17 00:00:00 2001 From: Pablo Greco Date: Thu, 2 May 2019 10:33:48 -0300 Subject: [PATCH 05/21] ARM: dts: sun8i: v40: bananapi-m2-berry: Enable AHCI Just like the Bananapi M2 Ultra, enable the ahci controller and the two regulators needed to activate it. Reviewed-by: Jagan Teki Signed-off-by: Pablo Greco Signed-off-by: Maxime Ripard --- .../boot/dts/sun8i-v40-bananapi-m2-berry.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index 1f4f51f94188..461683c6d1fb 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -99,6 +99,12 @@ wifi_pwrseq: wifi_pwrseq { }; }; +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo3>; + status = "okay"; +}; + &de { status = "okay"; }; @@ -233,6 +239,18 @@ ®_dldo2 { regulator-name = "vcc-wifi"; }; +®_dldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd2v5-sata"; +}; + +®_eldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd1v2-sata"; +}; + &tcon_tv0 { status = "okay"; }; From 3e4a856af3154cf65428818123a7a9fb94a65214 Mon Sep 17 00:00:00 2001 From: Pablo Greco Date: Thu, 2 May 2019 10:33:49 -0300 Subject: [PATCH 06/21] ARM: dts: sun8i: v40: bananapi-m2-berry: Add Bluetooth device node The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side identifies as BCM43430, while the Bluetooth side identifies as BCM43438. The Bluetooth side is connected to UART3 in a 4 wire configuration. Same as the WiFi side, due to being the same chip and package, DLDO1 and DLDO2 regulator outputs from the PMIC provide overall power via VBAT and I/O power via VDDIO. The CLK_OUT_A clock output from the SoC provides the LPO low power clock at 32.768 kHz. This patch enables Bluetooth on this board, and also adds the missing LPO clock on the WiFi side. There is also a PCM connection for Bluetooth, but this is not covered here. The LPO clock is fed from CLK_OUT_A, which needs to be muxed on pin PI12. This can be represented in multiple ways. This patch puts the pinctrl property in the pin controller node. This is due to limitations in Linux, where pinmux settings, even the same one, can not be shared by multiple devices. Thus we cannot put it in both the WiFi and Bluetooth device nodes. Putting it the CCU node is another option, but Linux's CCU driver does not handle pinctrl. Also the pin controller is guaranteed to be initialized after the CCU, when clocks are available. And any other devices that use muxed pins are guaranteed to be initialized after the pin controller. Thus having the CLK_OUT_A pinmux reference be in the pin controller node is a good choice without having to deal with implementation issues. Signed-off-by: Pablo Greco Signed-off-by: Maxime Ripard --- .../boot/dts/sun8i-v40-bananapi-m2-berry.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index 461683c6d1fb..15c22b06fc4b 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -96,6 +96,8 @@ reg_vcc5v0: vcc5v0 { wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; }; }; @@ -172,6 +174,8 @@ &mmc1 { }; &pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; vcc-pa-supply = <®_aldo2>; vcc-pc-supply = <®_dcdc1>; vcc-pd-supply = <®_dcdc1>; @@ -233,12 +237,27 @@ ®_dldo1 { regulator-name = "vcc-wifi-io"; }; +/* + * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same + * time, with the two being in sync, to be able to meet maximum power + * consumption during transmits. Since this is not really supported + * right now, just use the two as always on, and we will fix it later. + */ + ®_dldo2 { + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc-wifi"; }; +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; +}; + ®_dldo4 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; @@ -261,6 +280,25 @@ &uart0 { status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&ccu CLK_OUTA>; + clock-names = "lpo"; + vbat-supply = <®_dldo2>; + vddio-supply = <®_dldo1>; + device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + /* TODO host wake line connected to PMIC GPIO pins */ + shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ + max-speed = <1500000>; + }; +}; + &usbphy { usb1_vbus-supply = <®_vcc5v0>; status = "okay"; From e60f1fd252d70e0f1bc3eb449e395ee089002fb4 Mon Sep 17 00:00:00 2001 From: Pablo Greco Date: Fri, 3 May 2019 20:05:19 -0300 Subject: [PATCH 07/21] ARM: dts: sun8i: r40: bananapi-m2-ultra: Remove regulator-always-on Now that the regulators are tied to the GPIO bank, we can remove the unneeded regulator-always-on in reg_aldo2 Signed-off-by: Pablo Greco Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 699579d43105..42d62d1ba1dc 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -210,7 +210,6 @@ &pio { }; ®_aldo2 { - regulator-always-on; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-name = "vcc-pa"; From a28d1b67cf4f330fb532c8e515025b360d10691a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 7 May 2019 21:38:48 +0200 Subject: [PATCH 08/21] dt-bindings: bus: Convert Allwinner RSB to a schema The newer Allwinner SoCs feature a bus designed for the PMIC, similar to I2C called RSB. Let's convert the device tree bindings for that bus over to a YAML schemas. Signed-off-by: Maxime Ripard --- .../bindings/bus/allwinner,sun8i-a23-rsb.yaml | 79 +++++++++++++++++++ .../devicetree/bindings/bus/sunxi-rsb.txt | 47 ----------- 2 files changed, 79 insertions(+), 47 deletions(-) create mode 100644 Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml delete mode 100644 Documentation/devicetree/bindings/bus/sunxi-rsb.txt diff --git a/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml b/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml new file mode 100644 index 000000000000..fc2f63860cc8 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/allwinner,sun8i-a23-rsb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A23 RSB Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + compatible: + oneOf: + - const: allwinner,sun8i-a23-rsb + - items: + - const: allwinner,sun8i-a83t-rsb + - const: allwinner,sun8i-a23-rsb + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + clock-frequency: + minimum: 1 + maximum: 20000000 + +patternProperties: + "^.*@[0-9a-fA-F]+$": + properties: + reg: + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - interrupts + - clocks + - resets + +examples: + - | + rsb@1f03400 { + compatible = "allwinner,sun8i-a23-rsb"; + reg = <0x01f03400 0x400>; + interrupts = <0 39 4>; + clocks = <&apb0_gates 3>; + clock-frequency = <3000000>; + resets = <&apb0_rst 3>; + #address-cells = <1>; + #size-cells = <0>; + + pmic@3e3 { + compatible = "..."; + reg = <0x3e3>; + + /* ... */ + }; + }; + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/bus/sunxi-rsb.txt b/Documentation/devicetree/bindings/bus/sunxi-rsb.txt deleted file mode 100644 index eb3ed628c6f1..000000000000 --- a/Documentation/devicetree/bindings/bus/sunxi-rsb.txt +++ /dev/null @@ -1,47 +0,0 @@ -Allwinner Reduced Serial Bus (RSB) controller - -The RSB controller found on later Allwinner SoCs is an SMBus like 2 wire -serial bus with 1 master and up to 15 slaves. It is represented by a node -for the controller itself, and child nodes representing the slave devices. - -Required properties : - - - reg : Offset and length of the register set for the controller. - - compatible : Shall be "allwinner,sun8i-a23-rsb". - - interrupts : The interrupt line associated to the RSB controller. - - clocks : The gate clk associated to the RSB controller. - - resets : The reset line associated to the RSB controller. - - #address-cells : shall be 1 - - #size-cells : shall be 0 - -Optional properties : - - - clock-frequency : Desired RSB bus clock frequency in Hz. Maximum is 20MHz. - If not set this defaults to 3MHz. - -Child nodes: - -An RSB controller node can contain zero or more child nodes representing -slave devices on the bus. Child 'reg' properties should contain the slave -device's hardware address. The hardware address is hardwired in the device, -which can normally be found in the datasheet. - -Example: - - rsb@1f03400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x01f03400 0x400>; - interrupts = <0 39 4>; - clocks = <&apb0_gates 3>; - clock-frequency = <3000000>; - resets = <&apb0_rst 3>; - #address-cells = <1>; - #size-cells = <0>; - - pmic@3e3 { - compatible = "..."; - reg = <0x3e3>; - - /* ... */ - }; - }; From ca0961011db57e39880df0b5708df8aa3339dc6f Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 18 May 2019 17:40:14 +0200 Subject: [PATCH 09/21] ARM: dts: sun8i-h3: Fix wifi in Beelink X2 DT mmc1 node where wifi module is connected doesn't have properly defined power supplies so wifi module is never powered up. Fix that by specifying additional power supplies. Additionally, this STB may have either Realtek or Broadcom based wifi module. One based on Broadcom module also needs external clock to work properly. Fix that by adding clock property to wifi_pwrseq node. Fixes: e582b47a9252 ("ARM: dts: sun8i-h3: Add dts for the Beelink X2 STB") Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index 6277f13f3eb3..ac9e26b1d906 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -90,6 +90,8 @@ red { wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; sound_spdif { @@ -155,6 +157,8 @@ &mmc0 { &mmc1 { vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; non-removable; status = "okay"; From 17996e5b0ba40c4d85500e1c9bfbddaf676ab8c7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 20 May 2019 16:50:36 +0200 Subject: [PATCH 10/21] ARM: dts: sun6i: Add default address and size cells for SPI The SPI controller bindings require an address cell size of 1, and a size cell size of 0. Let's put it at the DTSI level to make sure that's properly enforced. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index c04efad81bbc..a57cbf33c12f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -987,6 +987,8 @@ spi0: spi@1c68000 { dma-names = "rx", "tx"; resets = <&ccu RST_AHB1_SPI0>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; spi1: spi@1c69000 { @@ -999,6 +1001,8 @@ spi1: spi@1c69000 { dma-names = "rx", "tx"; resets = <&ccu RST_AHB1_SPI1>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; spi2: spi@1c6a000 { @@ -1011,6 +1015,8 @@ spi2: spi@1c6a000 { dma-names = "rx", "tx"; resets = <&ccu RST_AHB1_SPI2>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; spi3: spi@1c6b000 { @@ -1023,6 +1029,8 @@ spi3: spi@1c6b000 { dma-names = "rx", "tx"; resets = <&ccu RST_AHB1_SPI3>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; gic: interrupt-controller@1c81000 { From 5f49c38a80b94fc27ecd91f0e50949c3525688f1 Mon Sep 17 00:00:00 2001 From: Priit Laes Date: Tue, 28 May 2019 09:35:44 +0300 Subject: [PATCH 11/21] ARM: dts: sun7i: olimex-lime2: Enable ac and power supplies Lime2 has battery connector so enable these supplies. Signed-off-by: Priit Laes Reviewed-by: Paul Kocialkowski Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index 95c6f8949076..56f451c07f93 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -194,6 +194,14 @@ ®_ahci_5v { #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; From dfe8173dfd25206de396592930589770eed48fcb Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 25 May 2019 15:40:03 +0200 Subject: [PATCH 12/21] ARM: dts: sun8i: a711: Change LRADC node names to avoid warnings One of the usage of the LRADC is to implement buttons. The bindings define that we should have one subnode per button, with their associated voltage as a property. However, there was no reg property but we still used the voltage associated to the button as the unit-address, which eventually generated warnings in DTC. Rename the node names to avoid those warnings. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 66d078053d5f..568b90ece342 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -224,14 +224,14 @@ &r_lradc { vref-supply = <®_aldo2>; status = "okay"; - button@210 { + button-210 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <210000>; }; - button@410 { + button-410 { label = "Volume Down"; linux,code = ; channel = <0>; From ae683c816d9f4aadec3eaf1da69a04c07ca9fd3f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 25 May 2019 15:41:39 +0200 Subject: [PATCH 13/21] ARM: dts: sun7i: icnova-swac: Fix the model vendor Even though the SWAC is just a baseboard to the icnova SoM, the vendor of the baseboard somehow ended up with the board name instead of the vendor name. Fix that. Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.yaml | 2 +- arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 285f4fc8519d..000a00d12d6a 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -263,7 +263,7 @@ properties: - description: ICNova A20 SWAC items: - - const: swac,icnova-a20-swac + - const: incircuit,icnova-a20-swac - const: incircuit,icnova-a20 - const: allwinner,sun7i-a20 diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts index 949494730aee..7449aac3f43b 100644 --- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts +++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts @@ -49,7 +49,8 @@ / { model = "ICnova-A20 SWAC"; - compatible = "swac,icnova-a20-swac", "incircuit,icnova-a20", "allwinner,sun7i-a20"; + compatible = "incircuit,icnova-a20-swac", "incircuit,icnova-a20", + "allwinner,sun7i-a20"; aliases { serial0 = &uart0; From bdd33cb6e24f4fc5a6d281ec81d2764698432117 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 25 May 2019 15:41:40 +0200 Subject: [PATCH 14/21] ARM: dts: gr8-evb: Fix RTC vendor For some reason, the RTC vendor is reported to be phg, while the part is actually made by the much more known NXP. Fix that. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-gr8-evb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts index d003b895a696..4c20d731a9c6 100644 --- a/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts @@ -150,7 +150,7 @@ wm8978: codec@1a { }; pcf8563: rtc@51 { - compatible = "phg,pcf8563"; + compatible = "nxp,pcf8563"; reg = <0x51>; }; }; From 96c0dad2f9de50f79216aacf304dcb9bcab9d01b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 20 May 2019 17:06:37 +0200 Subject: [PATCH 15/21] ARM: dts: sun8i: a83t: Add device node for CSI (Camera Sensor Interface) The A83T SoC has a camera sensor interface (known as CSI in Allwinner lingo), which is similar to the one found on the A64 and H3. The only difference seems to be that support of MIPI CSI through a connected MIPI CSI-2 bridge. Add a device node for it, and pinctrl nodes for the commonly used MCLK and 8-bit parallel interface. The property /omit-if-no-ref/ is added to the pinctrl nodes to keep the device tree blob size down if they are unused. Signed-off-by: Chen-Yu Tsai Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 392b0cabbf0d..ada6d08bc540 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -679,6 +679,20 @@ pio: pinctrl@1c20800 { #interrupt-cells = <3>; #gpio-cells = <3>; + /omit-if-no-ref/ + csi_8bit_parallel_pins: csi-8bit-parallel-pins { + pins = "PE0", "PE2", "PE3", "PE6", "PE7", + "PE8", "PE9", "PE10", "PE11", + "PE12", "PE13"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi_mclk_pin: csi-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + emac_rgmii_pins: emac-rgmii-pins { pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD11", "PD12", "PD13", "PD14", "PD18", @@ -997,6 +1011,21 @@ gic: interrupt-controller@1c81000 { interrupts = ; }; + csi: camera@1cb0000 { + compatible = "allwinner,sun8i-a83t-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + csi_in: port { + }; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun8i-a83t-dw-hdmi"; reg = <0x01ee0000 0x10000>; From b9cb524971245fe4e3b3e8f721985036df853bc5 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 23 May 2019 15:20:36 +0200 Subject: [PATCH 16/21] ARM: dts: sun6i: Fix RTC node The RTC node doesn't match what is described in the binding for historical reasons. Let's add the proper description. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index a57cbf33c12f..9361ef70dbab 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -223,7 +223,7 @@ osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; + clock-output-names = "ext_osc32k"; }; /* @@ -588,7 +588,7 @@ ohci2: usb@1c1c400 { ccu: clock@1c20000 { compatible = "allwinner,sun6i-a31-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; + clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -601,7 +601,7 @@ pio: pinctrl@1c20800 { , , ; - clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1287,10 +1287,13 @@ drc0_out_tcon1: endpoint@1 { }; rtc: rtc@1f00000 { + #clock-cells = <1>; compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = , ; + clocks = <&osc32k>; + clock-output-names = "osc32k"; }; nmi_intc: interrupt-controller@1f00c00 { @@ -1308,7 +1311,7 @@ prcm@1f01400 { ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, + clocks = <&rtc 0>, <&osc24M>, <&ccu CLK_PLL_PERIPH>, <&ccu CLK_PLL_PERIPH>; clock-output-names = "ar100"; @@ -1343,7 +1346,7 @@ apb0_gates: apb0_gates_clk { ir_clk: ir_clk { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; + clocks = <&rtc 0>, <&osc24M>; clock-output-names = "ir"; }; @@ -1373,7 +1376,7 @@ r_pio: pinctrl@1f02c00 { reg = <0x01f02c00 0x400>; interrupts = , ; - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; resets = <&apb0_rst 0>; gpio-controller; From 562b9526ee0c1956e4c2c77e73297ac617b2991c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 23 May 2019 15:20:49 +0200 Subject: [PATCH 17/21] ARM: dts: sun6i: Add external crystals accuracy The A31 datasheet mandates oscillators accuracy to be within 50ppm. Let's add that accuracy to their device tree nodes. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 9361ef70dbab..dcddc3392460 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -216,6 +216,7 @@ osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; @@ -223,6 +224,7 @@ osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-accuracy = <50000>; clock-output-names = "ext_osc32k"; }; From 65a4a40215a9488c5dd04c9f2e313cd36c9475fa Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 25 May 2019 15:09:19 +0200 Subject: [PATCH 18/21] ARM: dts: sun8i: v3s: Fix the RTC node For some reason, while the v3s has a dedicated compatible in the RTC binding, the one actually used was the A31's. However, it turns out that the controller is pretty different (which justified the compatible). Let's use the proper compatible, and use the proper binding description as well. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index df72b1719c34..6ba9377458b3 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -91,7 +91,7 @@ osc32k: osc32k_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; + clock-output-names = "ext-osc32k"; }; }; @@ -264,17 +264,20 @@ usbphy: phy@1c19400 { ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; + clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; }; rtc: rtc@1c20400 { - compatible = "allwinner,sun6i-a31-rtc"; + #clock-cells = <1>; + compatible = "allwinner,sun8i-v3-rtc"; reg = <0x01c20400 0x54>; interrupts = , ; + clocks = <&osc32k>; + clock-output-names = "osc32k", "osc32k-out"; }; pio: pinctrl@1c20800 { @@ -282,7 +285,7 @@ pio: pinctrl@1c20800 { reg = <0x01c20800 0x400>; interrupts = , ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; From 33e877f347779dbd4f0e22ca3921e0e6773d4766 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 23 May 2019 15:20:49 +0200 Subject: [PATCH 19/21] ARM: dts: sun8i: v3s: Add external crystals accuracy The V3s datasheet mandates oscillators accuracy to be within 50ppm. Let's add that accuracy to their device tree nodes. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 6ba9377458b3..d7aef128acb3 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -84,6 +84,7 @@ osc24M: osc24M_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; @@ -91,6 +92,7 @@ osc32k: osc32k_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-accuracy = <50000>; clock-output-names = "ext-osc32k"; }; }; From 913f36b6242a52cec5c1b366dbcc3adf4f99eeb9 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 25 May 2019 15:03:29 +0200 Subject: [PATCH 20/21] ARM: dts: sun8i: r40: Change the RTC compatible Unlike what's being reported in the device tree so far, the RTC in the R40 is quite different from the H3. Indeed it doesn't have the internal oscillator output, and it has only a single interrupt. Let's add a compatible for it. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index bb856e53b806..6007d0cc252d 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -318,8 +318,7 @@ ccu: clock@1c20000 { }; rtc: rtc@1c20400 { - compatible = "allwinner,sun8i-r40-rtc", - "allwinner,sun8i-h3-rtc"; + compatible = "allwinner,sun8i-r40-rtc"; reg = <0x01c20400 0x400>; interrupts = ; clock-output-names = "osc32k", "osc32k-out"; From 2269f0c15191af317d64115176a01bf303532af3 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 16 May 2019 14:08:48 +0200 Subject: [PATCH 21/21] dt-bindings: pwm: Convert Allwinner PWM to a schema The Allwinner SoCs have a PWM controller supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by: Maxime Ripard --- .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 57 +++++++++++++++++++ .../devicetree/bindings/pwm/pwm-sun4i.txt | 24 -------- 2 files changed, 57 insertions(+), 24 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun4i.txt diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml new file mode 100644 index 000000000000..0ac52f83a58c --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 PWM Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + "#pwm-cells": + const: 3 + + compatible: + oneOf: + - const: allwinner,sun4i-a10-pwm + - const: allwinner,sun5i-a10s-pwm + - const: allwinner,sun5i-a13-pwm + - const: allwinner,sun7i-a20-pwm + - const: allwinner,sun8i-h3-pwm + - items: + - const: allwinner,sun8i-a83t-pwm + - const: allwinner,sun8i-h3-pwm + - items: + - const: allwinner,sun50i-a64-pwm + - const: allwinner,sun5i-a13-pwm + - items: + - const: allwinner,sun50i-h5-pwm + - const: allwinner,sun5i-a13-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - "#pwm-cells" + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm: pwm@1c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + }; + +... diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt deleted file mode 100644 index 2a1affbff45e..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt +++ /dev/null @@ -1,24 +0,0 @@ -Allwinner sun4i and sun7i SoC PWM controller - -Required properties: - - compatible: should be one of: - - "allwinner,sun4i-a10-pwm" - - "allwinner,sun5i-a10s-pwm" - - "allwinner,sun5i-a13-pwm" - - "allwinner,sun7i-a20-pwm" - - "allwinner,sun8i-h3-pwm" - - "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm" - - "allwinner,sun50i-h5-pwm", "allwinner,sun5i-a13-pwm" - - reg: physical base address and length of the controller's registers - - #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. - - clocks: From common clock binding, handle to the parent clock. - -Example: - - pwm: pwm@1c20e00 { - compatible = "allwinner,sun7i-a20-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - };